Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65973630

1

T1

1461

T2

27302

T3

50019

auto[1]

1134562

1

T2

3465

T3

1089

T4

1089

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65971114

1

T1

1461

T2

27005

T3

50217

auto[1]

1137078

1

T2

3762

T3

891

T4

1287

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5572260	1			T1	273		T2	9057		T3	5278
auto[IdleSt]	17190294	1			T1	116		T2	1700		T3	2327
auto[ClkMuxSt]	29896	1			T1	5		T3	49		T10	7
auto[CntIncrSt]	29681	1			T1	3		T3	49		T10	7
auto[CntProgSt]	1271280	1			T1	6		T3	88		T10	1012
auto[TransCheckSt]	23609	1			T1	3		T3	39		T10	7
auto[TokenHashSt]	20026504	1			T1	175		T3	33308		T10	24517
auto[FlashRmaSt]	29070	1			T1	3		T3	80		T10	44
auto[TokenCheck0St]	10260	1			T1	3		T3	34		T10	7
auto[TokenCheck1St]	7313	1			T1	3		T3	16		T10	7
auto[TransProgSt]	249312	1			T1	6		T3	32		T10	1094
auto[PostTransSt]	9502795	1			T1	865		T3	6579		T10	962
auto[ScrapSt]	296174	1			T10	63		T15	10		T43	569
auto[EscalateSt]	4943677	1			T2	9883		T3	2443		T4	3271
auto[InvalidSt]	7924694	1			T2	10118		T3	786		T12	5763

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1373	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7924694	1			T2	10118		T3	786		T12	5763
EscalateSt	4943677	1			T2	9883		T3	2443		T4	3271
ScrapSt	296174	1			T10	63		T15	10		T43	569
PostTransSt	9502795	1			T1	865		T3	6579		T10	962
TransProgSt	249312	1			T1	6		T3	32		T10	1094
TokenCheck1St	7313	1			T1	3		T3	16		T10	7
TokenCheck0St	10260	1			T1	3		T3	34		T10	7
FlashRmaSt	29070	1			T1	3		T3	80		T10	44
TokenHashSt	20026504	1			T1	175		T3	33308		T10	24517
TransCheckSt	23609	1			T1	3		T3	39		T10	7
CntProgSt	1271280	1			T1	6		T3	88		T10	1012
CntIncrSt	29681	1			T1	3		T3	49		T10	7
ClkMuxSt	29896	1			T1	5		T3	49		T10	7
IdleSt	17190294	1			T1	116		T2	1700		T3	2327
ResetSt	5572260	1			T1	273		T2	9057		T3	5278
arcs[ResetSt=>IdleSt]	43308	1			T1	3		T2	81		T3	60
arcs[IdleSt=>ScrapSt]	245	1			T10	2		T15	1		T43	2
arcs[IdleSt=>ClkMuxSt]	29706	1			T1	3		T3	49		T10	7
arcs[ClkMuxSt=>CntIncrSt]	29681	1			T1	3		T3	49		T10	7
arcs[CntIncrSt=>PostTransSt]	1300	1			T5	9		T16	27		T17	16
arcs[CntIncrSt=>CntProgSt]	28309	1			T1	3		T3	49		T10	7
arcs[CntProgSt=>PostTransSt]	3725	1			T3	10		T4	24		T5	14
arcs[CntProgSt=>TransCheckSt]	23609	1			T1	3		T3	39		T10	7
arcs[TransCheckSt=>PostTransSt]	3305	1			T5	6		T22	27		T16	35
arcs[TransCheckSt=>TokenHashSt]	20171	1			T1	3		T3	39		T10	7
arcs[TokenHashSt=>PostTransSt]	8923	1			T3	5		T11	97		T14	97
arcs[TokenHashSt=>FlashRmaSt]	10302	1			T1	3		T3	34		T10	7
arcs[FlashRmaSt=>TokenCheck0St]	10260	1			T1	3		T3	34		T10	7
arcs[TokenCheck0St=>PostTransSt]	2884	1			T3	18		T5	9		T22	14
arcs[TokenCheck0St=>TokenCheck1St]	7313	1			T1	3		T3	16		T10	7
arcs[TokenCheck1St=>PostTransSt]	642	1			T22	6		T16	5		T51	7
arcs[TransProgSt=>PostTransSt]	5923	1			T1	3		T3	16		T10	7
arcs[IdleSt=>EscalateSt]	142	1			T52	2		T53	8		T54	2
arcs[ClkMuxSt=>EscalateSt]	25	1			T52	1		T53	2		T54	2
arcs[CntIncrSt=>EscalateSt]	72	1			T18	3		T53	4		T54	1
arcs[CntProgSt=>EscalateSt]	975	1			T18	28		T55	34		T52	18
arcs[TransCheckSt=>EscalateSt]	133	1			T55	1		T52	4		T54	7
arcs[TokenHashSt=>EscalateSt]	946	1			T18	14		T16	1		T55	3
arcs[FlashRmaSt=>EscalateSt]	42	1			T55	1		T53	1		T54	3
arcs[TokenCheck0St=>EscalateSt]	63	1			T55	2		T52	1		T53	2
arcs[TokenCheck1St=>EscalateSt]	27	1			T18	1		T55	1		T54	2
arcs[TransProgSt=>EscalateSt]	721	1			T18	20		T55	20		T52	16
arcs[PostTransSt=>EscalateSt]	4147	1			T3	10		T4	24		T5	14
arcs[InvalidSt=>EscalateSt]	9783	1			T2	73		T3	10		T12	41

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5572088	1			T1	273		T2	9057		T3	5278
auto[0]	auto[IdleSt]	17190205	1			T1	116		T2	1700		T3	2327
auto[0]	auto[ClkMuxSt]	29880	1			T1	5		T3	49		T10	7
auto[0]	auto[CntIncrSt]	29627	1			T1	3		T3	49		T10	7
auto[0]	auto[CntProgSt]	1270610	1			T1	6		T3	88		T10	1012
auto[0]	auto[TransCheckSt]	23516	1			T1	3		T3	39		T10	7
auto[0]	auto[TokenHashSt]	20025877	1			T1	175		T3	33308		T10	24517
auto[0]	auto[FlashRmaSt]	29044	1			T1	3		T3	80		T10	44
auto[0]	auto[TokenCheck0St]	10219	1			T1	3		T3	34		T10	7
auto[0]	auto[TokenCheck1St]	7293	1			T1	3		T3	16		T10	7
auto[0]	auto[TransProgSt]	248817	1			T1	6		T3	32		T10	1094
auto[0]	auto[PostTransSt]	9500707	1			T1	865		T3	6574		T10	962
auto[0]	auto[ScrapSt]	296115	1			T10	63		T15	10		T43	569
auto[0]	auto[EscalateSt]	3818455	1			T2	6453		T3	1365		T4	2193
auto[0]	auto[InvalidSt]	7919804	1			T2	10083		T3	780		T12	5737
auto[1]	auto[ResetSt]	172	1			T18	2		T55	6		T52	1
auto[1]	auto[IdleSt]	89	1			T52	2		T53	3		T54	1
auto[1]	auto[ClkMuxSt]	16	1			T52	1		T53	1		T54	2
auto[1]	auto[CntIncrSt]	54	1			T18	3		T53	3		T54	1
auto[1]	auto[CntProgSt]	670	1			T18	21		T55	22		T52	14
auto[1]	auto[TransCheckSt]	93	1			T55	1		T52	3		T54	7
auto[1]	auto[TokenHashSt]	627	1			T18	8		T16	1		T55	3
auto[1]	auto[FlashRmaSt]	26	1			T54	2		T191	1		T192	4
auto[1]	auto[TokenCheck0St]	41	1			T55	1		T53	1		T54	1
auto[1]	auto[TokenCheck1St]	20	1			T55	1		T54	1		T193	1
auto[1]	auto[TransProgSt]	495	1			T18	16		T55	11		T52	12
auto[1]	auto[PostTransSt]	2088	1			T3	5		T4	11		T5	6
auto[1]	auto[ScrapSt]	59	1			T55	2		T52	1		T53	3
auto[1]	auto[EscalateSt]	1125222	1			T2	3430		T3	1078		T4	1078
auto[1]	auto[InvalidSt]	4890	1			T2	35		T3	6		T12	26

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5572084	1			T1	273		T2	9057		T3	5278
auto[0]	auto[IdleSt]	17190201	1			T1	116		T2	1700		T3	2327
auto[0]	auto[ClkMuxSt]	29880	1			T1	5		T3	49		T10	7
auto[0]	auto[CntIncrSt]	29637	1			T1	3		T3	49		T10	7
auto[0]	auto[CntProgSt]	1270650	1			T1	6		T3	88		T10	1012
auto[0]	auto[TransCheckSt]	23528	1			T1	3		T3	39		T10	7
auto[0]	auto[TokenHashSt]	20025873	1			T1	175		T3	33308		T10	24517
auto[0]	auto[FlashRmaSt]	29039	1			T1	3		T3	80		T10	44
auto[0]	auto[TokenCheck0St]	10209	1			T1	3		T3	34		T10	7
auto[0]	auto[TokenCheck1St]	7295	1			T1	3		T3	16		T10	7
auto[0]	auto[TransProgSt]	248841	1			T1	6		T3	32		T10	1094
auto[0]	auto[PostTransSt]	9500597	1			T1	865		T3	6574		T10	962
auto[0]	auto[ScrapSt]	296117	1			T10	63		T15	10		T43	569
auto[0]	auto[EscalateSt]	3815989	1			T2	6159		T3	1561		T4	1997
auto[0]	auto[InvalidSt]	7919801	1			T2	10080		T3	782		T12	5748
auto[1]	auto[ResetSt]	176	1			T18	4		T55	6		T52	2
auto[1]	auto[IdleSt]	93	1			T52	1		T53	7		T54	1
auto[1]	auto[ClkMuxSt]	16	1			T52	1		T53	1		T194	1
auto[1]	auto[CntIncrSt]	44	1			T53	3		T54	1		T194	1
auto[1]	auto[CntProgSt]	630	1			T18	20		T55	24		T52	11
auto[1]	auto[TransCheckSt]	81	1			T52	2		T54	3		T195	3
auto[1]	auto[TokenHashSt]	631	1			T18	10		T55	2		T52	17
auto[1]	auto[FlashRmaSt]	31	1			T55	1		T53	1		T54	3
auto[1]	auto[TokenCheck0St]	51	1			T55	2		T52	1		T53	2
auto[1]	auto[TokenCheck1St]	18	1			T18	1		T54	1		T191	2
auto[1]	auto[TransProgSt]	471	1			T18	12		T55	14		T52	7
auto[1]	auto[PostTransSt]	2198	1			T3	5		T4	13		T5	8
auto[1]	auto[ScrapSt]	57	1			T55	2		T52	2		T53	3
auto[1]	auto[EscalateSt]	1127688	1			T2	3724		T3	882		T4	1274
auto[1]	auto[InvalidSt]	4893	1			T2	38		T3	4		T12	15