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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.11 97.92 95.29 93.40 100.00 98.52 98.51 96.11


Total test records in report: 1000
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T811 /workspace/coverage/default/20.lc_ctrl_prog_failure.1617342598 Aug 12 06:45:42 PM PDT 24 Aug 12 06:45:44 PM PDT 24 262596453 ps
T812 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1690555639 Aug 12 06:46:16 PM PDT 24 Aug 12 06:46:30 PM PDT 24 1346344594 ps
T813 /workspace/coverage/default/46.lc_ctrl_security_escalation.1852680105 Aug 12 06:46:40 PM PDT 24 Aug 12 06:46:55 PM PDT 24 1195130372 ps
T82 /workspace/coverage/default/32.lc_ctrl_smoke.539483869 Aug 12 06:45:57 PM PDT 24 Aug 12 06:45:59 PM PDT 24 15174088 ps
T814 /workspace/coverage/default/16.lc_ctrl_security_escalation.2075949808 Aug 12 06:45:12 PM PDT 24 Aug 12 06:45:22 PM PDT 24 261664253 ps
T815 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2443252677 Aug 12 06:46:13 PM PDT 24 Aug 12 06:46:15 PM PDT 24 161515059 ps
T816 /workspace/coverage/default/23.lc_ctrl_state_post_trans.4098770834 Aug 12 06:45:38 PM PDT 24 Aug 12 06:45:46 PM PDT 24 205203809 ps
T817 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3460140235 Aug 12 06:46:19 PM PDT 24 Aug 12 06:46:27 PM PDT 24 359659284 ps
T818 /workspace/coverage/default/15.lc_ctrl_sec_mubi.2460696492 Aug 12 06:45:13 PM PDT 24 Aug 12 06:45:21 PM PDT 24 467091329 ps
T819 /workspace/coverage/default/8.lc_ctrl_jtag_priority.1523303398 Aug 12 06:44:38 PM PDT 24 Aug 12 06:44:43 PM PDT 24 158163320 ps
T820 /workspace/coverage/default/41.lc_ctrl_errors.2530160033 Aug 12 06:46:27 PM PDT 24 Aug 12 06:46:42 PM PDT 24 1214871594 ps
T821 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3538034329 Aug 12 06:44:28 PM PDT 24 Aug 12 06:44:29 PM PDT 24 43273927 ps
T822 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3710740347 Aug 12 06:44:51 PM PDT 24 Aug 12 06:45:02 PM PDT 24 872934586 ps
T823 /workspace/coverage/default/31.lc_ctrl_security_escalation.1210348698 Aug 12 06:45:59 PM PDT 24 Aug 12 06:46:10 PM PDT 24 1224709785 ps
T824 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.610502968 Aug 12 06:45:47 PM PDT 24 Aug 12 06:46:04 PM PDT 24 1342753866 ps
T825 /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2568772314 Aug 12 06:46:17 PM PDT 24 Aug 12 06:47:12 PM PDT 24 4480377805 ps
T826 /workspace/coverage/default/33.lc_ctrl_state_post_trans.904594620 Aug 12 06:46:04 PM PDT 24 Aug 12 06:46:12 PM PDT 24 56685399 ps
T827 /workspace/coverage/default/16.lc_ctrl_errors.3337172099 Aug 12 06:45:14 PM PDT 24 Aug 12 06:45:27 PM PDT 24 420066925 ps
T828 /workspace/coverage/default/41.lc_ctrl_jtag_access.1946882124 Aug 12 06:46:27 PM PDT 24 Aug 12 06:46:32 PM PDT 24 3845687428 ps
T829 /workspace/coverage/default/12.lc_ctrl_errors.31566547 Aug 12 06:44:54 PM PDT 24 Aug 12 06:45:03 PM PDT 24 980496446 ps
T830 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3525822076 Aug 12 06:45:25 PM PDT 24 Aug 12 06:45:34 PM PDT 24 951019176 ps
T831 /workspace/coverage/default/49.lc_ctrl_alert_test.1893632160 Aug 12 06:46:44 PM PDT 24 Aug 12 06:46:45 PM PDT 24 48666767 ps
T832 /workspace/coverage/default/34.lc_ctrl_alert_test.320190198 Aug 12 06:46:08 PM PDT 24 Aug 12 06:46:09 PM PDT 24 129783741 ps
T833 /workspace/coverage/default/28.lc_ctrl_security_escalation.2533777370 Aug 12 06:45:48 PM PDT 24 Aug 12 06:45:54 PM PDT 24 366448502 ps
T834 /workspace/coverage/default/42.lc_ctrl_state_post_trans.1198268526 Aug 12 06:46:25 PM PDT 24 Aug 12 06:46:28 PM PDT 24 287796877 ps
T835 /workspace/coverage/default/35.lc_ctrl_smoke.4125568128 Aug 12 06:46:11 PM PDT 24 Aug 12 06:46:13 PM PDT 24 66640202 ps
T836 /workspace/coverage/default/14.lc_ctrl_errors.2904317375 Aug 12 06:45:00 PM PDT 24 Aug 12 06:45:13 PM PDT 24 1266411035 ps
T837 /workspace/coverage/default/44.lc_ctrl_state_failure.909275336 Aug 12 06:46:28 PM PDT 24 Aug 12 06:47:01 PM PDT 24 1150498364 ps
T838 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2236447024 Aug 12 06:45:10 PM PDT 24 Aug 12 06:45:22 PM PDT 24 6468075673 ps
T839 /workspace/coverage/default/27.lc_ctrl_sec_mubi.2663641513 Aug 12 06:45:49 PM PDT 24 Aug 12 06:46:06 PM PDT 24 1538133992 ps
T840 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1409751207 Aug 12 06:45:30 PM PDT 24 Aug 12 06:45:37 PM PDT 24 865693918 ps
T841 /workspace/coverage/default/24.lc_ctrl_state_post_trans.208065819 Aug 12 06:45:43 PM PDT 24 Aug 12 06:45:50 PM PDT 24 546232795 ps
T842 /workspace/coverage/default/42.lc_ctrl_smoke.2534691051 Aug 12 06:46:27 PM PDT 24 Aug 12 06:46:31 PM PDT 24 243076316 ps
T843 /workspace/coverage/default/49.lc_ctrl_jtag_access.580181877 Aug 12 06:46:38 PM PDT 24 Aug 12 06:46:42 PM PDT 24 109246478 ps
T844 /workspace/coverage/default/15.lc_ctrl_prog_failure.1443554208 Aug 12 06:45:08 PM PDT 24 Aug 12 06:45:12 PM PDT 24 99594159 ps
T83 /workspace/coverage/default/8.lc_ctrl_jtag_smoke.156126753 Aug 12 06:44:39 PM PDT 24 Aug 12 06:44:46 PM PDT 24 3312682139 ps
T845 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.480255362 Aug 12 06:45:48 PM PDT 24 Aug 12 06:45:56 PM PDT 24 317767830 ps
T846 /workspace/coverage/default/35.lc_ctrl_prog_failure.2995194808 Aug 12 06:46:10 PM PDT 24 Aug 12 06:46:12 PM PDT 24 88388992 ps
T847 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3186487699 Aug 12 06:45:11 PM PDT 24 Aug 12 06:45:13 PM PDT 24 169997015 ps
T185 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.95313167 Aug 12 06:44:21 PM PDT 24 Aug 12 06:44:22 PM PDT 24 11675252 ps
T848 /workspace/coverage/default/29.lc_ctrl_security_escalation.2176858050 Aug 12 06:46:03 PM PDT 24 Aug 12 06:46:15 PM PDT 24 586545969 ps
T849 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2211075838 Aug 12 06:46:16 PM PDT 24 Aug 12 06:46:23 PM PDT 24 640964211 ps
T850 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.948051755 Aug 12 06:44:53 PM PDT 24 Aug 12 06:45:01 PM PDT 24 2353750760 ps
T851 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2795392502 Aug 12 06:45:43 PM PDT 24 Aug 12 06:46:00 PM PDT 24 2994000530 ps
T852 /workspace/coverage/default/24.lc_ctrl_jtag_access.1249638440 Aug 12 06:45:45 PM PDT 24 Aug 12 06:45:54 PM PDT 24 982604532 ps
T853 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3075530832 Aug 12 06:44:52 PM PDT 24 Aug 12 06:45:08 PM PDT 24 584410440 ps
T854 /workspace/coverage/default/30.lc_ctrl_prog_failure.3849113742 Aug 12 06:45:59 PM PDT 24 Aug 12 06:46:01 PM PDT 24 24846224 ps
T855 /workspace/coverage/default/11.lc_ctrl_sec_mubi.2982011319 Aug 12 06:44:54 PM PDT 24 Aug 12 06:45:07 PM PDT 24 270505704 ps
T856 /workspace/coverage/default/6.lc_ctrl_stress_all.1437928346 Aug 12 06:44:30 PM PDT 24 Aug 12 06:46:34 PM PDT 24 13209436613 ps
T857 /workspace/coverage/default/45.lc_ctrl_security_escalation.628921390 Aug 12 06:46:33 PM PDT 24 Aug 12 06:46:45 PM PDT 24 314827241 ps
T858 /workspace/coverage/default/23.lc_ctrl_stress_all.3612386520 Aug 12 06:45:43 PM PDT 24 Aug 12 06:48:53 PM PDT 24 19561830481 ps
T74 /workspace/coverage/default/43.lc_ctrl_alert_test.1610768021 Aug 12 06:46:26 PM PDT 24 Aug 12 06:46:27 PM PDT 24 23110239 ps
T859 /workspace/coverage/default/19.lc_ctrl_smoke.626339780 Aug 12 06:45:28 PM PDT 24 Aug 12 06:45:32 PM PDT 24 58153096 ps
T84 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.700622980 Aug 12 06:44:05 PM PDT 24 Aug 12 06:44:09 PM PDT 24 283316020 ps
T860 /workspace/coverage/default/34.lc_ctrl_state_failure.1177662901 Aug 12 06:46:08 PM PDT 24 Aug 12 06:46:41 PM PDT 24 295229770 ps
T861 /workspace/coverage/default/37.lc_ctrl_stress_all.2089449361 Aug 12 06:46:19 PM PDT 24 Aug 12 06:46:42 PM PDT 24 1149979109 ps
T862 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2403366318 Aug 12 06:45:01 PM PDT 24 Aug 12 06:45:14 PM PDT 24 459005165 ps
T863 /workspace/coverage/default/1.lc_ctrl_errors.2323213415 Aug 12 06:43:56 PM PDT 24 Aug 12 06:44:07 PM PDT 24 526697681 ps
T864 /workspace/coverage/default/20.lc_ctrl_errors.3656180186 Aug 12 06:45:43 PM PDT 24 Aug 12 06:45:50 PM PDT 24 1526392952 ps
T865 /workspace/coverage/default/43.lc_ctrl_errors.1038071786 Aug 12 06:46:26 PM PDT 24 Aug 12 06:46:39 PM PDT 24 745495923 ps
T866 /workspace/coverage/default/10.lc_ctrl_jtag_access.1742593641 Aug 12 06:44:54 PM PDT 24 Aug 12 06:45:08 PM PDT 24 2432408904 ps
T867 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.840546997 Aug 12 06:46:24 PM PDT 24 Aug 12 06:46:31 PM PDT 24 219006936 ps
T868 /workspace/coverage/default/26.lc_ctrl_smoke.1581731484 Aug 12 06:45:47 PM PDT 24 Aug 12 06:45:51 PM PDT 24 95058571 ps
T869 /workspace/coverage/default/31.lc_ctrl_state_failure.581203335 Aug 12 06:46:03 PM PDT 24 Aug 12 06:46:28 PM PDT 24 670181483 ps
T870 /workspace/coverage/default/0.lc_ctrl_security_escalation.786388169 Aug 12 06:43:43 PM PDT 24 Aug 12 06:43:56 PM PDT 24 1614688561 ps
T98 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3747878140 Aug 12 06:18:40 PM PDT 24 Aug 12 06:18:43 PM PDT 24 53041171 ps
T99 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4243305547 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:07 PM PDT 24 392108550 ps
T131 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1423626431 Aug 12 06:18:45 PM PDT 24 Aug 12 06:18:46 PM PDT 24 201187312 ps
T106 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.510385551 Aug 12 06:18:56 PM PDT 24 Aug 12 06:18:57 PM PDT 24 45242528 ps
T165 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1846589555 Aug 12 06:18:38 PM PDT 24 Aug 12 06:18:39 PM PDT 24 36084428 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2124093693 Aug 12 06:18:44 PM PDT 24 Aug 12 06:18:46 PM PDT 24 49093234 ps
T871 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2210170973 Aug 12 06:18:34 PM PDT 24 Aug 12 06:18:35 PM PDT 24 19972398 ps
T166 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3979218932 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:04 PM PDT 24 15897268 ps
T100 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3344781563 Aug 12 06:19:12 PM PDT 24 Aug 12 06:19:18 PM PDT 24 185870258 ps
T129 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1125543395 Aug 12 06:18:54 PM PDT 24 Aug 12 06:18:56 PM PDT 24 76492838 ps
T103 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.502552428 Aug 12 06:19:02 PM PDT 24 Aug 12 06:19:05 PM PDT 24 1784560253 ps
T132 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4268418580 Aug 12 06:19:05 PM PDT 24 Aug 12 06:19:13 PM PDT 24 3247331432 ps
T154 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1489348196 Aug 12 06:18:56 PM PDT 24 Aug 12 06:18:57 PM PDT 24 21971390 ps
T130 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4063486366 Aug 12 06:18:50 PM PDT 24 Aug 12 06:18:53 PM PDT 24 516114455 ps
T104 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1806592638 Aug 12 06:18:47 PM PDT 24 Aug 12 06:18:50 PM PDT 24 468519704 ps
T145 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3421978665 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:02 PM PDT 24 155263548 ps
T112 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.754671809 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:03 PM PDT 24 74824308 ps
T146 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3661226518 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:43 PM PDT 24 104755085 ps
T872 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1208717513 Aug 12 06:18:39 PM PDT 24 Aug 12 06:18:41 PM PDT 24 144012123 ps
T155 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.218396811 Aug 12 06:19:11 PM PDT 24 Aug 12 06:19:12 PM PDT 24 172255733 ps
T111 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2086416857 Aug 12 06:18:38 PM PDT 24 Aug 12 06:18:42 PM PDT 24 429228213 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.415780298 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:34 PM PDT 24 37174317 ps
T874 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3835619213 Aug 12 06:18:55 PM PDT 24 Aug 12 06:18:57 PM PDT 24 119966229 ps
T113 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3886572111 Aug 12 06:18:34 PM PDT 24 Aug 12 06:18:38 PM PDT 24 205680541 ps
T126 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1180008210 Aug 12 06:18:37 PM PDT 24 Aug 12 06:18:39 PM PDT 24 243541489 ps
T109 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1923443883 Aug 12 06:19:06 PM PDT 24 Aug 12 06:19:08 PM PDT 24 81393739 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.263300715 Aug 12 06:18:35 PM PDT 24 Aug 12 06:18:45 PM PDT 24 965193102 ps
T127 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2907622022 Aug 12 06:18:56 PM PDT 24 Aug 12 06:19:05 PM PDT 24 6021406025 ps
T176 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.410804976 Aug 12 06:19:10 PM PDT 24 Aug 12 06:19:12 PM PDT 24 199356832 ps
T876 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1258642940 Aug 12 06:18:55 PM PDT 24 Aug 12 06:18:57 PM PDT 24 68237758 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.912111916 Aug 12 06:18:43 PM PDT 24 Aug 12 06:18:46 PM PDT 24 183991170 ps
T167 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3451631269 Aug 12 06:19:05 PM PDT 24 Aug 12 06:19:06 PM PDT 24 65258289 ps
T177 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2682406764 Aug 12 06:18:34 PM PDT 24 Aug 12 06:18:36 PM PDT 24 39509785 ps
T110 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.892210566 Aug 12 06:18:47 PM PDT 24 Aug 12 06:18:49 PM PDT 24 158548073 ps
T147 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3130988205 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:50 PM PDT 24 18047229 ps
T107 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1151570231 Aug 12 06:18:53 PM PDT 24 Aug 12 06:18:56 PM PDT 24 231345563 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1122609214 Aug 12 06:18:53 PM PDT 24 Aug 12 06:18:54 PM PDT 24 72294130 ps
T879 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3651220203 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:04 PM PDT 24 120366434 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3968896771 Aug 12 06:18:46 PM PDT 24 Aug 12 06:18:49 PM PDT 24 177011462 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1633539939 Aug 12 06:18:56 PM PDT 24 Aug 12 06:19:00 PM PDT 24 1300415538 ps
T117 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3560072835 Aug 12 06:18:54 PM PDT 24 Aug 12 06:18:59 PM PDT 24 694363907 ps
T881 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2357531993 Aug 12 06:18:40 PM PDT 24 Aug 12 06:18:50 PM PDT 24 1528320053 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.317729752 Aug 12 06:18:33 PM PDT 24 Aug 12 06:18:35 PM PDT 24 192134163 ps
T883 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1054335228 Aug 12 06:18:40 PM PDT 24 Aug 12 06:18:42 PM PDT 24 42201104 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4104490413 Aug 12 06:18:48 PM PDT 24 Aug 12 06:18:58 PM PDT 24 1667901412 ps
T178 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2962818864 Aug 12 06:18:54 PM PDT 24 Aug 12 06:18:55 PM PDT 24 67075009 ps
T179 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1317071132 Aug 12 06:18:48 PM PDT 24 Aug 12 06:18:50 PM PDT 24 138775710 ps
T120 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.110579079 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:10 PM PDT 24 93073381 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.405902405 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:07 PM PDT 24 292372435 ps
T180 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.273924569 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:04 PM PDT 24 87704839 ps
T168 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3595378045 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:02 PM PDT 24 18359378 ps
T886 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.656007621 Aug 12 06:18:56 PM PDT 24 Aug 12 06:19:40 PM PDT 24 8909115468 ps
T887 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.485462663 Aug 12 06:19:02 PM PDT 24 Aug 12 06:19:03 PM PDT 24 209518124 ps
T888 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3929249207 Aug 12 06:18:47 PM PDT 24 Aug 12 06:18:58 PM PDT 24 3309930503 ps
T108 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1433799577 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:12 PM PDT 24 124162062 ps
T128 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4131734802 Aug 12 06:18:36 PM PDT 24 Aug 12 06:18:43 PM PDT 24 708953105 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.930275397 Aug 12 06:18:37 PM PDT 24 Aug 12 06:18:40 PM PDT 24 336711733 ps
T114 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2999724663 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:09 PM PDT 24 202165418 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4019027937 Aug 12 06:18:39 PM PDT 24 Aug 12 06:18:42 PM PDT 24 988921555 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1926818326 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:08 PM PDT 24 1612822512 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4029562381 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:51 PM PDT 24 29170859 ps
T893 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1953105941 Aug 12 06:19:05 PM PDT 24 Aug 12 06:19:07 PM PDT 24 123618550 ps
T181 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3139638137 Aug 12 06:19:05 PM PDT 24 Aug 12 06:19:06 PM PDT 24 40401766 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2825931408 Aug 12 06:18:38 PM PDT 24 Aug 12 06:18:41 PM PDT 24 409641200 ps
T895 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2191059895 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:58 PM PDT 24 21814053 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1456954985 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:43 PM PDT 24 14923410 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2183038314 Aug 12 06:18:47 PM PDT 24 Aug 12 06:18:50 PM PDT 24 139737975 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1928972191 Aug 12 06:18:32 PM PDT 24 Aug 12 06:18:33 PM PDT 24 392832938 ps
T899 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.830226965 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:05 PM PDT 24 94203709 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.613334798 Aug 12 06:18:50 PM PDT 24 Aug 12 06:18:52 PM PDT 24 305839861 ps
T901 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2241467711 Aug 12 06:18:38 PM PDT 24 Aug 12 06:18:39 PM PDT 24 37100690 ps
T902 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.489052772 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:02 PM PDT 24 137833165 ps
T119 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2331073301 Aug 12 06:18:55 PM PDT 24 Aug 12 06:18:59 PM PDT 24 113040466 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.41563976 Aug 12 06:18:59 PM PDT 24 Aug 12 06:19:00 PM PDT 24 25346291 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.620676695 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:51 PM PDT 24 19580965 ps
T905 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3735351261 Aug 12 06:18:39 PM PDT 24 Aug 12 06:18:40 PM PDT 24 22894784 ps
T906 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2091965050 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:50 PM PDT 24 41392002 ps
T907 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.486418900 Aug 12 06:18:42 PM PDT 24 Aug 12 06:18:43 PM PDT 24 14867303 ps
T908 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4214150537 Aug 12 06:18:56 PM PDT 24 Aug 12 06:19:00 PM PDT 24 231439296 ps
T909 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2499469816 Aug 12 06:18:35 PM PDT 24 Aug 12 06:18:38 PM PDT 24 30946665 ps
T910 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2319642455 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:09 PM PDT 24 41695842 ps
T911 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2202625460 Aug 12 06:18:56 PM PDT 24 Aug 12 06:18:57 PM PDT 24 13570373 ps
T115 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3117910285 Aug 12 06:18:54 PM PDT 24 Aug 12 06:18:56 PM PDT 24 83845495 ps
T912 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4004896673 Aug 12 06:18:59 PM PDT 24 Aug 12 06:19:01 PM PDT 24 148154965 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3200550896 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:59 PM PDT 24 24371574 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.800113369 Aug 12 06:18:55 PM PDT 24 Aug 12 06:18:56 PM PDT 24 65746822 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1661384709 Aug 12 06:18:40 PM PDT 24 Aug 12 06:18:54 PM PDT 24 1252497810 ps
T916 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1649679692 Aug 12 06:18:48 PM PDT 24 Aug 12 06:18:50 PM PDT 24 94197988 ps
T917 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2949580098 Aug 12 06:18:54 PM PDT 24 Aug 12 06:19:14 PM PDT 24 877337723 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3995452621 Aug 12 06:18:45 PM PDT 24 Aug 12 06:18:48 PM PDT 24 97381589 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2800221889 Aug 12 06:18:40 PM PDT 24 Aug 12 06:18:46 PM PDT 24 724616721 ps
T920 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2712673070 Aug 12 06:19:06 PM PDT 24 Aug 12 06:19:08 PM PDT 24 254157993 ps
T921 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1846970514 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:07 PM PDT 24 348281434 ps
T922 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.612387056 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:10 PM PDT 24 500808133 ps
T169 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2813878126 Aug 12 06:19:08 PM PDT 24 Aug 12 06:19:09 PM PDT 24 22711382 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3682615005 Aug 12 06:18:55 PM PDT 24 Aug 12 06:18:57 PM PDT 24 62647935 ps
T924 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3106049694 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:52 PM PDT 24 114948630 ps
T170 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4166727533 Aug 12 06:18:43 PM PDT 24 Aug 12 06:18:44 PM PDT 24 35935274 ps
T171 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2989565819 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:04 PM PDT 24 14361655 ps
T925 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.768658040 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:50 PM PDT 24 103789553 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.420476860 Aug 12 06:18:42 PM PDT 24 Aug 12 06:18:44 PM PDT 24 36993320 ps
T172 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.268396613 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:04 PM PDT 24 64050836 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1897081853 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:43 PM PDT 24 48759294 ps
T928 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.364784318 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:58 PM PDT 24 36202243 ps
T929 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2643571276 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:08 PM PDT 24 142043288 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4146501590 Aug 12 06:18:42 PM PDT 24 Aug 12 06:18:46 PM PDT 24 321312668 ps
T931 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.159443950 Aug 12 06:19:05 PM PDT 24 Aug 12 06:19:08 PM PDT 24 86992764 ps
T932 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3516087795 Aug 12 06:18:55 PM PDT 24 Aug 12 06:18:57 PM PDT 24 29269387 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1940762806 Aug 12 06:18:34 PM PDT 24 Aug 12 06:18:36 PM PDT 24 97843187 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1862422533 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:50 PM PDT 24 266595120 ps
T935 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.509149334 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:50 PM PDT 24 48952143 ps
T936 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1341837365 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:05 PM PDT 24 49313008 ps
T937 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1999046897 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:02 PM PDT 24 33649252 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.731926987 Aug 12 06:18:47 PM PDT 24 Aug 12 06:18:49 PM PDT 24 65262201 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1729001179 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:44 PM PDT 24 229245415 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.951316622 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:47 PM PDT 24 1134962448 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.214632005 Aug 12 06:18:50 PM PDT 24 Aug 12 06:18:54 PM PDT 24 357306456 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.939534333 Aug 12 06:18:49 PM PDT 24 Aug 12 06:19:06 PM PDT 24 691769066 ps
T943 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2141903586 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:05 PM PDT 24 117050122 ps
T944 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1494649603 Aug 12 06:19:00 PM PDT 24 Aug 12 06:19:01 PM PDT 24 73772827 ps
T945 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4289740773 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:42 PM PDT 24 38818778 ps
T946 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1683901366 Aug 12 06:19:00 PM PDT 24 Aug 12 06:19:02 PM PDT 24 17931752 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3424072107 Aug 12 06:18:39 PM PDT 24 Aug 12 06:18:40 PM PDT 24 200828352 ps
T948 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.745562950 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:07 PM PDT 24 1880069831 ps
T949 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3189479444 Aug 12 06:18:43 PM PDT 24 Aug 12 06:18:48 PM PDT 24 368558424 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.319034116 Aug 12 06:18:51 PM PDT 24 Aug 12 06:18:52 PM PDT 24 65248434 ps
T951 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2126409476 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:05 PM PDT 24 158895601 ps
T952 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3850254505 Aug 12 06:18:35 PM PDT 24 Aug 12 06:18:36 PM PDT 24 86163144 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2712385417 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:05 PM PDT 24 19974821 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.823492308 Aug 12 06:18:48 PM PDT 24 Aug 12 06:18:49 PM PDT 24 34292639 ps
T955 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2294409801 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:05 PM PDT 24 19819404 ps
T116 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4035966619 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:08 PM PDT 24 126462564 ps
T122 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3948088530 Aug 12 06:18:55 PM PDT 24 Aug 12 06:18:59 PM PDT 24 433539359 ps
T118 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.884523937 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:10 PM PDT 24 73178315 ps
T956 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1778789217 Aug 12 06:18:38 PM PDT 24 Aug 12 06:18:44 PM PDT 24 1051206255 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1412892995 Aug 12 06:18:48 PM PDT 24 Aug 12 06:18:50 PM PDT 24 141790141 ps
T958 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3027148298 Aug 12 06:18:48 PM PDT 24 Aug 12 06:18:50 PM PDT 24 108939952 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4144680635 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:58 PM PDT 24 23082714 ps
T960 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2743956550 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:58 PM PDT 24 78971314 ps
T123 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1799283921 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:09 PM PDT 24 204683571 ps
T961 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1761091666 Aug 12 06:18:36 PM PDT 24 Aug 12 06:18:46 PM PDT 24 1475636320 ps
T962 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3294343225 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:08 PM PDT 24 14809279 ps
T963 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3949797486 Aug 12 06:19:02 PM PDT 24 Aug 12 06:19:27 PM PDT 24 6127998984 ps
T964 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.480396523 Aug 12 06:19:00 PM PDT 24 Aug 12 06:19:01 PM PDT 24 100553566 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3737806794 Aug 12 06:18:51 PM PDT 24 Aug 12 06:18:53 PM PDT 24 50472568 ps
T966 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.338949579 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:02 PM PDT 24 39700165 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.942495738 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:05 PM PDT 24 97825529 ps
T968 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.480158810 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:08 PM PDT 24 40149427 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1803976563 Aug 12 06:18:48 PM PDT 24 Aug 12 06:18:49 PM PDT 24 14028589 ps
T173 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1538912545 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:05 PM PDT 24 15856570 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1431008965 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:42 PM PDT 24 72241937 ps
T971 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2404367794 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:58 PM PDT 24 40583250 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.857377511 Aug 12 06:18:49 PM PDT 24 Aug 12 06:19:18 PM PDT 24 6313828580 ps
T973 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3986442454 Aug 12 06:18:52 PM PDT 24 Aug 12 06:19:06 PM PDT 24 2107246177 ps
T974 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4264167165 Aug 12 06:18:57 PM PDT 24 Aug 12 06:19:22 PM PDT 24 20618313503 ps
T121 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.681878621 Aug 12 06:19:05 PM PDT 24 Aug 12 06:19:08 PM PDT 24 142509758 ps
T975 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1315583394 Aug 12 06:18:59 PM PDT 24 Aug 12 06:19:01 PM PDT 24 30717447 ps
T976 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1165922712 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:02 PM PDT 24 18812640 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3906101669 Aug 12 06:19:07 PM PDT 24 Aug 12 06:19:09 PM PDT 24 363099131 ps
T978 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.954086460 Aug 12 06:19:04 PM PDT 24 Aug 12 06:19:05 PM PDT 24 44520645 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3031585248 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:42 PM PDT 24 227819703 ps
T980 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.864273644 Aug 12 06:19:02 PM PDT 24 Aug 12 06:19:03 PM PDT 24 13350555 ps
T981 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2062471301 Aug 12 06:19:06 PM PDT 24 Aug 12 06:19:08 PM PDT 24 40749187 ps
T982 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2264751475 Aug 12 06:18:59 PM PDT 24 Aug 12 06:19:03 PM PDT 24 330597065 ps
T983 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1768459706 Aug 12 06:18:39 PM PDT 24 Aug 12 06:18:40 PM PDT 24 206635129 ps
T984 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2588246092 Aug 12 06:19:02 PM PDT 24 Aug 12 06:19:04 PM PDT 24 18225906 ps
T985 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3216363862 Aug 12 06:18:39 PM PDT 24 Aug 12 06:18:40 PM PDT 24 57550985 ps
T986 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3982009413 Aug 12 06:18:36 PM PDT 24 Aug 12 06:18:39 PM PDT 24 177359687 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3342123502 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:59 PM PDT 24 538352828 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4290406519 Aug 12 06:18:49 PM PDT 24 Aug 12 06:18:50 PM PDT 24 35855726 ps
T174 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3020663615 Aug 12 06:19:02 PM PDT 24 Aug 12 06:19:03 PM PDT 24 120383055 ps
T989 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3595983004 Aug 12 06:18:41 PM PDT 24 Aug 12 06:18:42 PM PDT 24 88149765 ps
T990 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2028323202 Aug 12 06:18:57 PM PDT 24 Aug 12 06:18:58 PM PDT 24 82134361 ps
T991 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4192784811 Aug 12 06:18:38 PM PDT 24 Aug 12 06:18:39 PM PDT 24 189962193 ps
T992 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1489866686 Aug 12 06:18:58 PM PDT 24 Aug 12 06:18:59 PM PDT 24 203256215 ps
T993 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2749479305 Aug 12 06:18:51 PM PDT 24 Aug 12 06:18:52 PM PDT 24 24916979 ps
T994 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2902839816 Aug 12 06:19:05 PM PDT 24 Aug 12 06:19:06 PM PDT 24 56027807 ps
T175 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1371368812 Aug 12 06:18:50 PM PDT 24 Aug 12 06:18:51 PM PDT 24 13530502 ps
T995 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2113166552 Aug 12 06:19:03 PM PDT 24 Aug 12 06:19:05 PM PDT 24 55852267 ps
T996 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.601277201 Aug 12 06:18:45 PM PDT 24 Aug 12 06:18:47 PM PDT 24 39386575 ps
T997 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2645006300 Aug 12 06:18:46 PM PDT 24 Aug 12 06:18:47 PM PDT 24 31831702 ps
T998 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2779887636 Aug 12 06:18:43 PM PDT 24 Aug 12 06:18:45 PM PDT 24 27969442 ps
T999 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2604419931 Aug 12 06:19:01 PM PDT 24 Aug 12 06:19:03 PM PDT 24 95680394 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2358255419 Aug 12 06:19:08 PM PDT 24 Aug 12 06:19:10 PM PDT 24 318494672 ps
T1000 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1265805223 Aug 12 06:19:02 PM PDT 24 Aug 12 06:19:03 PM PDT 24 69881852 ps

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4283887226
Short name T4
Test name
Test status
Simulation time 5200912226 ps
CPU time 98.7 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:47:24 PM PDT 24
Peak memory 220936 kb
Host smart-7606250a-c273-4830-af03-849eca8c98b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283887226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4283887226
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1794299720
Short name T16
Test name
Test status
Simulation time 113933353392 ps
CPU time 461.15 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:52:42 PM PDT 24
Peak memory 251660 kb
Host smart-68332f1d-0646-40ff-bfc8-80a443036992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794299720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1794299720
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2218840309
Short name T54
Test name
Test status
Simulation time 1086930319 ps
CPU time 10.69 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 218844 kb
Host smart-79fdbaee-f819-4da2-a712-208516720b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218840309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2218840309
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.575864365
Short name T216
Test name
Test status
Simulation time 546446101 ps
CPU time 13.56 seconds
Started Aug 12 06:44:21 PM PDT 24
Finished Aug 12 06:44:35 PM PDT 24
Peak memory 219572 kb
Host smart-ce874b58-bce7-4bc7-8bf7-581bb87c846c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575864365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.575864365
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1840143660
Short name T19
Test name
Test status
Simulation time 13551154016 ps
CPU time 157.58 seconds
Started Aug 12 06:45:32 PM PDT 24
Finished Aug 12 06:48:10 PM PDT 24
Peak memory 273544 kb
Host smart-22077d55-6259-436b-b538-3c545729bb35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1840143660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1840143660
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2454735777
Short name T22
Test name
Test status
Simulation time 220299857 ps
CPU time 7.96 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:45:37 PM PDT 24
Peak memory 218752 kb
Host smart-5a38bc84-c5fb-411f-bf2f-993e43678749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454735777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2454735777
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1877706727
Short name T56
Test name
Test status
Simulation time 573661014 ps
CPU time 41.48 seconds
Started Aug 12 06:44:00 PM PDT 24
Finished Aug 12 06:44:41 PM PDT 24
Peak memory 283152 kb
Host smart-8bbc3e0a-7bde-4650-abef-9e87ef9d56df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877706727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1877706727
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1638141388
Short name T150
Test name
Test status
Simulation time 11803325168 ps
CPU time 382.78 seconds
Started Aug 12 06:44:21 PM PDT 24
Finished Aug 12 06:50:44 PM PDT 24
Peak memory 277320 kb
Host smart-8c152a8c-60e2-4c5b-8ef0-7f96fa26b812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638141388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1638141388
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.989740093
Short name T62
Test name
Test status
Simulation time 1933699877 ps
CPU time 10.91 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:11 PM PDT 24
Peak memory 218928 kb
Host smart-c11d713b-c1bb-40b7-991b-f494e66c8341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989740093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.989740093
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3344781563
Short name T100
Test name
Test status
Simulation time 185870258 ps
CPU time 5.88 seconds
Started Aug 12 06:19:12 PM PDT 24
Finished Aug 12 06:19:18 PM PDT 24
Peak memory 218212 kb
Host smart-25f92cc5-2934-46b6-b9a2-551dfe3ffada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344781563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3344781563
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3853811481
Short name T2
Test name
Test status
Simulation time 307692082 ps
CPU time 30.71 seconds
Started Aug 12 06:45:51 PM PDT 24
Finished Aug 12 06:46:22 PM PDT 24
Peak memory 251484 kb
Host smart-5d2ffbfa-8347-4f6f-a281-bac4355a94a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853811481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3853811481
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4243305547
Short name T99
Test name
Test status
Simulation time 392108550 ps
CPU time 2.93 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:07 PM PDT 24
Peak memory 222788 kb
Host smart-7ff34086-8364-41a0-ade7-225fb9963b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243305547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4243305547
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2419991415
Short name T39
Test name
Test status
Simulation time 69891036 ps
CPU time 0.91 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:41 PM PDT 24
Peak memory 209372 kb
Host smart-aa06b7dc-27b6-4faf-a84a-4172ddf27d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419991415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2419991415
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.449484037
Short name T6
Test name
Test status
Simulation time 1470150388 ps
CPU time 3.94 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:16 PM PDT 24
Peak memory 218300 kb
Host smart-3fec6c6f-373f-4f8a-b7b4-54cd5c8de08e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449484037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.449484037
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1846589555
Short name T165
Test name
Test status
Simulation time 36084428 ps
CPU time 1.16 seconds
Started Aug 12 06:18:38 PM PDT 24
Finished Aug 12 06:18:39 PM PDT 24
Peak memory 210072 kb
Host smart-a6896c84-2fda-4e84-ac8a-f2a5284f2ea4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846589555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1846589555
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1180008210
Short name T126
Test name
Test status
Simulation time 243541489 ps
CPU time 2.08 seconds
Started Aug 12 06:18:37 PM PDT 24
Finished Aug 12 06:18:39 PM PDT 24
Peak memory 210004 kb
Host smart-6327d503-1261-4d5e-bbdf-f488eafbf743
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180008210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1180008210
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.556945107
Short name T47
Test name
Test status
Simulation time 4647937926 ps
CPU time 109 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:47:35 PM PDT 24
Peak memory 284368 kb
Host smart-1639bf8c-c5e0-417a-b28b-926ffe4fa090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556945107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.556945107
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.83976841
Short name T9
Test name
Test status
Simulation time 5410563756 ps
CPU time 15.85 seconds
Started Aug 12 06:45:25 PM PDT 24
Finished Aug 12 06:45:41 PM PDT 24
Peak memory 251348 kb
Host smart-dd202a3e-6dd8-444e-8194-526d0ffb485a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83976841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_j
tag_state_post_trans.83976841
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2331073301
Short name T119
Test name
Test status
Simulation time 113040466 ps
CPU time 3.26 seconds
Started Aug 12 06:18:55 PM PDT 24
Finished Aug 12 06:18:59 PM PDT 24
Peak memory 222908 kb
Host smart-da77ac98-c38c-4a1b-9d3b-9b90bcbabfd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331073301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2331073301
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1465378457
Short name T61
Test name
Test status
Simulation time 2778097190 ps
CPU time 118.5 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:47:47 PM PDT 24
Peak memory 276704 kb
Host smart-c4b7a81c-2b83-4d30-9442-c4f469b86473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465378457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1465378457
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1703893483
Short name T20
Test name
Test status
Simulation time 5420052601 ps
CPU time 180.19 seconds
Started Aug 12 06:44:54 PM PDT 24
Finished Aug 12 06:47:54 PM PDT 24
Peak memory 256168 kb
Host smart-2e84248e-fdf7-4334-91e9-bf3164c2ad33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703893483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1703893483
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2327403823
Short name T5
Test name
Test status
Simulation time 6702687170 ps
CPU time 97.34 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:46:50 PM PDT 24
Peak memory 219512 kb
Host smart-51dbccf8-ac4e-444c-a0aa-f3a4bf6acafc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327403823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2327403823
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4035966619
Short name T116
Test name
Test status
Simulation time 126462564 ps
CPU time 4.27 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 218224 kb
Host smart-e575f467-5d26-40a5-936c-e98615af3b43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035966619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4035966619
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.110579079
Short name T120
Test name
Test status
Simulation time 93073381 ps
CPU time 2.69 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:10 PM PDT 24
Peak memory 223132 kb
Host smart-b1713fae-84a7-409b-9291-8833c48dd517
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110579079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.110579079
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2682406764
Short name T177
Test name
Test status
Simulation time 39509785 ps
CPU time 1.87 seconds
Started Aug 12 06:18:34 PM PDT 24
Finished Aug 12 06:18:36 PM PDT 24
Peak memory 210036 kb
Host smart-88f83b46-8fc7-421d-9e5d-b0c07fef2165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682406764 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2682406764
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4162422587
Short name T11
Test name
Test status
Simulation time 375199031 ps
CPU time 14.94 seconds
Started Aug 12 06:46:13 PM PDT 24
Finished Aug 12 06:46:28 PM PDT 24
Peak memory 226496 kb
Host smart-f13e6d89-04bb-45a8-bf09-68b328de95de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162422587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4162422587
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2086416857
Short name T111
Test name
Test status
Simulation time 429228213 ps
CPU time 3.92 seconds
Started Aug 12 06:18:38 PM PDT 24
Finished Aug 12 06:18:42 PM PDT 24
Peak memory 218304 kb
Host smart-b45e9ef2-2a1e-43d0-a851-bef35880b25f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086416857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2086416857
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.386812892
Short name T306
Test name
Test status
Simulation time 38882425 ps
CPU time 1.13 seconds
Started Aug 12 06:43:42 PM PDT 24
Finished Aug 12 06:43:44 PM PDT 24
Peak memory 213532 kb
Host smart-0ee9c8ce-fc75-471d-a0b1-e01dace92c33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386812892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.386812892
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.428121908
Short name T187
Test name
Test status
Simulation time 13699040 ps
CPU time 0.86 seconds
Started Aug 12 06:43:54 PM PDT 24
Finished Aug 12 06:43:55 PM PDT 24
Peak memory 209236 kb
Host smart-851023da-b53e-4330-9b6a-498c87f60a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428121908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.428121908
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2272752459
Short name T195
Test name
Test status
Simulation time 426470622 ps
CPU time 15.24 seconds
Started Aug 12 06:45:37 PM PDT 24
Finished Aug 12 06:45:52 PM PDT 24
Peak memory 225668 kb
Host smart-ace84854-fd25-4dd7-b4a3-5957906a4db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272752459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2272752459
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.95313167
Short name T185
Test name
Test status
Simulation time 11675252 ps
CPU time 0.81 seconds
Started Aug 12 06:44:21 PM PDT 24
Finished Aug 12 06:44:22 PM PDT 24
Peak memory 209088 kb
Host smart-fe6a00f6-098a-48db-93e5-2ad10b8e69e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95313167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.95313167
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.286680097
Short name T189
Test name
Test status
Simulation time 38846850 ps
CPU time 0.92 seconds
Started Aug 12 06:44:27 PM PDT 24
Finished Aug 12 06:44:28 PM PDT 24
Peak memory 209288 kb
Host smart-13ff5afe-4bf2-4037-83d0-6cb786430b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286680097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.286680097
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.385379240
Short name T26
Test name
Test status
Simulation time 2129196785 ps
CPU time 31.93 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 251372 kb
Host smart-091a3fa3-4353-4b40-92d7-12861bde6382
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385379240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.385379240
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2499469816
Short name T909
Test name
Test status
Simulation time 30946665 ps
CPU time 2.22 seconds
Started Aug 12 06:18:35 PM PDT 24
Finished Aug 12 06:18:38 PM PDT 24
Peak memory 219336 kb
Host smart-71206930-3895-42a1-bdf8-1d4095621f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499469816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2499469816
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.884523937
Short name T118
Test name
Test status
Simulation time 73178315 ps
CPU time 2.64 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:10 PM PDT 24
Peak memory 223108 kb
Host smart-97f458e9-2b54-44fd-81df-4b836be02b49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884523937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.884523937
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.681878621
Short name T121
Test name
Test status
Simulation time 142509758 ps
CPU time 2.99 seconds
Started Aug 12 06:19:05 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 222628 kb
Host smart-450e4876-9155-4190-9892-e493dfc07b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681878621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.681878621
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1799283921
Short name T123
Test name
Test status
Simulation time 204683571 ps
CPU time 2.09 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:09 PM PDT 24
Peak memory 222932 kb
Host smart-6ff1e061-b083-4ee7-a3ee-9c9f1a1029ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799283921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1799283921
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2358255419
Short name T124
Test name
Test status
Simulation time 318494672 ps
CPU time 2.58 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:10 PM PDT 24
Peak memory 218352 kb
Host smart-7d2ce431-7605-4074-901a-dbd82800398c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358255419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2358255419
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.892210566
Short name T110
Test name
Test status
Simulation time 158548073 ps
CPU time 2.31 seconds
Started Aug 12 06:18:47 PM PDT 24
Finished Aug 12 06:18:49 PM PDT 24
Peak memory 218164 kb
Host smart-0aec4a0e-eccf-4ea6-9dfc-988acb6470f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892210566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.892210566
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3467736901
Short name T50
Test name
Test status
Simulation time 471854675 ps
CPU time 11.33 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:49 PM PDT 24
Peak memory 226604 kb
Host smart-52bd31e7-2af4-473d-ac2c-30b23a776cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467736901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3467736901
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3982009413
Short name T986
Test name
Test status
Simulation time 177359687 ps
CPU time 2.77 seconds
Started Aug 12 06:18:36 PM PDT 24
Finished Aug 12 06:18:39 PM PDT 24
Peak memory 209320 kb
Host smart-b74f3f2d-fbd7-4b42-90fb-cd751f6c2504
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982009413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3982009413
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.415780298
Short name T873
Test name
Test status
Simulation time 37174317 ps
CPU time 1.24 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:34 PM PDT 24
Peak memory 218588 kb
Host smart-d6b78fd7-f1c7-4277-b455-1686dfc67e10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415780298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.415780298
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2779887636
Short name T998
Test name
Test status
Simulation time 27969442 ps
CPU time 2.14 seconds
Started Aug 12 06:18:43 PM PDT 24
Finished Aug 12 06:18:45 PM PDT 24
Peak memory 220032 kb
Host smart-659f92e7-6f37-4fb9-a7ea-6742db7c6f7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779887636 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2779887636
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2210170973
Short name T871
Test name
Test status
Simulation time 19972398 ps
CPU time 0.99 seconds
Started Aug 12 06:18:34 PM PDT 24
Finished Aug 12 06:18:35 PM PDT 24
Peak memory 210000 kb
Host smart-99d0edc3-51bd-4fe6-9daa-8d5bad43240f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210170973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2210170973
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1928972191
Short name T898
Test name
Test status
Simulation time 392832938 ps
CPU time 1.1 seconds
Started Aug 12 06:18:32 PM PDT 24
Finished Aug 12 06:18:33 PM PDT 24
Peak memory 209940 kb
Host smart-42e88715-72cb-4a3a-bdf9-3182a8290132
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928972191 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1928972191
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4131734802
Short name T128
Test name
Test status
Simulation time 708953105 ps
CPU time 7.05 seconds
Started Aug 12 06:18:36 PM PDT 24
Finished Aug 12 06:18:43 PM PDT 24
Peak memory 209364 kb
Host smart-170d700e-6227-4fab-b98f-966275b3e527
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131734802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4131734802
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.263300715
Short name T875
Test name
Test status
Simulation time 965193102 ps
CPU time 9.14 seconds
Started Aug 12 06:18:35 PM PDT 24
Finished Aug 12 06:18:45 PM PDT 24
Peak memory 209876 kb
Host smart-0b438f21-a6cc-41ec-93c5-1a044616da08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263300715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.263300715
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.317729752
Short name T882
Test name
Test status
Simulation time 192134163 ps
CPU time 1.34 seconds
Started Aug 12 06:18:33 PM PDT 24
Finished Aug 12 06:18:35 PM PDT 24
Peak memory 211356 kb
Host smart-aa59714d-3abf-4fa1-b558-0e30b28c57b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317729752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.317729752
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1940762806
Short name T933
Test name
Test status
Simulation time 97843187 ps
CPU time 2.08 seconds
Started Aug 12 06:18:34 PM PDT 24
Finished Aug 12 06:18:36 PM PDT 24
Peak memory 218304 kb
Host smart-eb740a94-94e5-43b0-9684-21a95296f668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194076
2806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1940762806
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3216363862
Short name T985
Test name
Test status
Simulation time 57550985 ps
CPU time 1.29 seconds
Started Aug 12 06:18:39 PM PDT 24
Finished Aug 12 06:18:40 PM PDT 24
Peak memory 218252 kb
Host smart-b6a12d5b-6411-40ec-a455-6012a305868d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216363862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3216363862
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3886572111
Short name T113
Test name
Test status
Simulation time 205680541 ps
CPU time 3.91 seconds
Started Aug 12 06:18:34 PM PDT 24
Finished Aug 12 06:18:38 PM PDT 24
Peak memory 218164 kb
Host smart-4a73f4b8-f6a0-44ec-a7fe-c92873b6ce23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886572111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3886572111
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.486418900
Short name T907
Test name
Test status
Simulation time 14867303 ps
CPU time 0.97 seconds
Started Aug 12 06:18:42 PM PDT 24
Finished Aug 12 06:18:43 PM PDT 24
Peak memory 210068 kb
Host smart-17edf27a-75c3-46df-8979-46ee46b8fb72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486418900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.486418900
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3850254505
Short name T952
Test name
Test status
Simulation time 86163144 ps
CPU time 1.32 seconds
Started Aug 12 06:18:35 PM PDT 24
Finished Aug 12 06:18:36 PM PDT 24
Peak memory 210000 kb
Host smart-fba05a64-847e-4942-8112-00abbbc46277
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850254505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3850254505
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3735351261
Short name T905
Test name
Test status
Simulation time 22894784 ps
CPU time 1 seconds
Started Aug 12 06:18:39 PM PDT 24
Finished Aug 12 06:18:40 PM PDT 24
Peak memory 210036 kb
Host smart-feadad39-ef14-4995-b460-fd5cf074ee04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735351261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3735351261
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3424072107
Short name T947
Test name
Test status
Simulation time 200828352 ps
CPU time 1.33 seconds
Started Aug 12 06:18:39 PM PDT 24
Finished Aug 12 06:18:40 PM PDT 24
Peak memory 218360 kb
Host smart-9c055a55-7d48-4d23-9f42-29a83843b625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424072107 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3424072107
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1456954985
Short name T896
Test name
Test status
Simulation time 14923410 ps
CPU time 1.01 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:43 PM PDT 24
Peak memory 209536 kb
Host smart-a7794e17-8145-4cc1-827e-ec7f59814640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456954985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1456954985
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1423626431
Short name T131
Test name
Test status
Simulation time 201187312 ps
CPU time 1.3 seconds
Started Aug 12 06:18:45 PM PDT 24
Finished Aug 12 06:18:46 PM PDT 24
Peak memory 209924 kb
Host smart-95d8e858-bc6f-4966-ac6c-5107fd784a3e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423626431 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1423626431
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1761091666
Short name T961
Test name
Test status
Simulation time 1475636320 ps
CPU time 9.64 seconds
Started Aug 12 06:18:36 PM PDT 24
Finished Aug 12 06:18:46 PM PDT 24
Peak memory 209768 kb
Host smart-9e737a44-c98f-482f-a055-0f40119ceb02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761091666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1761091666
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1778789217
Short name T956
Test name
Test status
Simulation time 1051206255 ps
CPU time 5.4 seconds
Started Aug 12 06:18:38 PM PDT 24
Finished Aug 12 06:18:44 PM PDT 24
Peak memory 209732 kb
Host smart-c8615f05-8817-40a2-baf0-4db75e62d721
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778789217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1778789217
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3995452621
Short name T918
Test name
Test status
Simulation time 97381589 ps
CPU time 2.94 seconds
Started Aug 12 06:18:45 PM PDT 24
Finished Aug 12 06:18:48 PM PDT 24
Peak memory 211692 kb
Host smart-5577a2fd-d8fe-4870-8fee-636424bccd53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995452621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3995452621
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4019027937
Short name T890
Test name
Test status
Simulation time 988921555 ps
CPU time 3.35 seconds
Started Aug 12 06:18:39 PM PDT 24
Finished Aug 12 06:18:42 PM PDT 24
Peak memory 219352 kb
Host smart-1ca97712-e33f-422c-b8ba-4b8fa3adaac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401902
7937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4019027937
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3189479444
Short name T949
Test name
Test status
Simulation time 368558424 ps
CPU time 5.18 seconds
Started Aug 12 06:18:43 PM PDT 24
Finished Aug 12 06:18:48 PM PDT 24
Peak memory 209960 kb
Host smart-92247666-57c5-49c7-887c-ed997979b157
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189479444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3189479444
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2124093693
Short name T144
Test name
Test status
Simulation time 49093234 ps
CPU time 2.07 seconds
Started Aug 12 06:18:44 PM PDT 24
Finished Aug 12 06:18:46 PM PDT 24
Peak memory 218268 kb
Host smart-e7efbe15-833c-4f09-a4a4-91fc3c45e8b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124093693 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2124093693
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3661226518
Short name T146
Test name
Test status
Simulation time 104755085 ps
CPU time 1.05 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:43 PM PDT 24
Peak memory 210048 kb
Host smart-45c0fee7-084d-4743-b416-dfbd78be14e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661226518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3661226518
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.420476860
Short name T926
Test name
Test status
Simulation time 36993320 ps
CPU time 2.39 seconds
Started Aug 12 06:18:42 PM PDT 24
Finished Aug 12 06:18:44 PM PDT 24
Peak memory 219304 kb
Host smart-274225b2-d0a4-4846-b8dc-94949fa01c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420476860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.420476860
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3747878140
Short name T98
Test name
Test status
Simulation time 53041171 ps
CPU time 2.38 seconds
Started Aug 12 06:18:40 PM PDT 24
Finished Aug 12 06:18:43 PM PDT 24
Peak memory 222732 kb
Host smart-3d71d12a-7b71-455e-b420-77653cbe72a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747878140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3747878140
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2319642455
Short name T910
Test name
Test status
Simulation time 41695842 ps
CPU time 1.26 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:09 PM PDT 24
Peak memory 219012 kb
Host smart-14a6c3fe-2dcf-4ebf-af89-5e01a75e1ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319642455 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2319642455
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1538912545
Short name T173
Test name
Test status
Simulation time 15856570 ps
CPU time 0.85 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 210028 kb
Host smart-3bbe3beb-2d85-4fd9-92d8-dac4972415b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538912545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1538912545
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2588246092
Short name T984
Test name
Test status
Simulation time 18225906 ps
CPU time 1.17 seconds
Started Aug 12 06:19:02 PM PDT 24
Finished Aug 12 06:19:04 PM PDT 24
Peak memory 210020 kb
Host smart-1c07092e-6c8d-466a-94c6-60be2a249d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588246092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2588246092
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.489052772
Short name T902
Test name
Test status
Simulation time 137833165 ps
CPU time 1.5 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:02 PM PDT 24
Peak memory 218208 kb
Host smart-820bde01-4cda-469c-8a5e-65862cb5e5e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489052772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.489052772
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2999724663
Short name T114
Test name
Test status
Simulation time 202165418 ps
CPU time 2.02 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:09 PM PDT 24
Peak memory 222900 kb
Host smart-6da0c00c-4131-48b6-a7ed-4f705006a6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999724663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2999724663
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.954086460
Short name T978
Test name
Test status
Simulation time 44520645 ps
CPU time 1.07 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 221528 kb
Host smart-f872cdca-0295-4c78-b954-7459ebba899a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954086460 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.954086460
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.864273644
Short name T980
Test name
Test status
Simulation time 13350555 ps
CPU time 0.99 seconds
Started Aug 12 06:19:02 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 210028 kb
Host smart-5b6e44f2-0d37-472d-87c0-faf5ae54cc11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864273644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.864273644
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3294343225
Short name T962
Test name
Test status
Simulation time 14809279 ps
CPU time 1.2 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 210156 kb
Host smart-6ae30156-0712-4a79-b9be-f3f72083d9b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294343225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3294343225
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2604419931
Short name T999
Test name
Test status
Simulation time 95680394 ps
CPU time 1.78 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 219232 kb
Host smart-9fbbc857-2b1d-4214-93b5-ab2d601475bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604419931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2604419931
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3651220203
Short name T879
Test name
Test status
Simulation time 120366434 ps
CPU time 2.75 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:04 PM PDT 24
Peak memory 214036 kb
Host smart-c99873c0-0489-4a4c-99e1-1d11975cf2be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651220203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3651220203
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1953105941
Short name T893
Test name
Test status
Simulation time 123618550 ps
CPU time 1.36 seconds
Started Aug 12 06:19:05 PM PDT 24
Finished Aug 12 06:19:07 PM PDT 24
Peak memory 219568 kb
Host smart-3237dbcd-e7dc-41bd-a9aa-ce92b333ce3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953105941 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1953105941
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.338949579
Short name T966
Test name
Test status
Simulation time 39700165 ps
CPU time 0.95 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:02 PM PDT 24
Peak memory 209664 kb
Host smart-e3bfd68d-f74d-4590-8e64-67e9c27c76bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338949579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.338949579
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.830226965
Short name T899
Test name
Test status
Simulation time 94203709 ps
CPU time 1.53 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 212196 kb
Host smart-04d8ee48-03c4-4d5a-945e-c7278bd430ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830226965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.830226965
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2264751475
Short name T982
Test name
Test status
Simulation time 330597065 ps
CPU time 3.37 seconds
Started Aug 12 06:18:59 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 218220 kb
Host smart-80689b7d-b458-4c28-a068-6d206bd5e219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264751475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2264751475
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.480396523
Short name T964
Test name
Test status
Simulation time 100553566 ps
CPU time 1.23 seconds
Started Aug 12 06:19:00 PM PDT 24
Finished Aug 12 06:19:01 PM PDT 24
Peak memory 219572 kb
Host smart-6252c3d7-a6e4-4ff1-9ed2-39e0b30e29d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480396523 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.480396523
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1165922712
Short name T976
Test name
Test status
Simulation time 18812640 ps
CPU time 0.92 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:02 PM PDT 24
Peak memory 209632 kb
Host smart-f4c14160-885e-4385-9728-97f4f6b3e5fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165922712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1165922712
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2126409476
Short name T951
Test name
Test status
Simulation time 158895601 ps
CPU time 1.23 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 212156 kb
Host smart-61d994dd-1ade-4d91-ac64-96a2145f3e2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126409476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2126409476
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2712673070
Short name T920
Test name
Test status
Simulation time 254157993 ps
CPU time 2.04 seconds
Started Aug 12 06:19:06 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 218184 kb
Host smart-f112f486-d978-4287-a422-b0666737415b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712673070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2712673070
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2113166552
Short name T995
Test name
Test status
Simulation time 55852267 ps
CPU time 2.58 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 218240 kb
Host smart-ac6eaf05-e168-4af3-a9a6-a0362ceafd70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113166552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2113166552
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1494649603
Short name T944
Test name
Test status
Simulation time 73772827 ps
CPU time 1.39 seconds
Started Aug 12 06:19:00 PM PDT 24
Finished Aug 12 06:19:01 PM PDT 24
Peak memory 218340 kb
Host smart-a2da64d6-f779-4617-823b-c67774e417b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494649603 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1494649603
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3979218932
Short name T166
Test name
Test status
Simulation time 15897268 ps
CPU time 1.1 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:04 PM PDT 24
Peak memory 210028 kb
Host smart-53c8bd6a-79be-4bce-b44e-268646c66bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979218932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3979218932
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1999046897
Short name T937
Test name
Test status
Simulation time 33649252 ps
CPU time 1.17 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:02 PM PDT 24
Peak memory 209916 kb
Host smart-275288f3-b7e8-45ec-a64f-00c38c03ff66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999046897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1999046897
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.754671809
Short name T112
Test name
Test status
Simulation time 74824308 ps
CPU time 1.72 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 218196 kb
Host smart-a33c4380-c196-46e4-9bb5-1d0f249e0ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754671809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.754671809
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1265805223
Short name T1000
Test name
Test status
Simulation time 69881852 ps
CPU time 1.27 seconds
Started Aug 12 06:19:02 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 218336 kb
Host smart-e9afc8f5-008e-4989-988e-f7372a046da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265805223 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1265805223
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3451631269
Short name T167
Test name
Test status
Simulation time 65258289 ps
CPU time 0.94 seconds
Started Aug 12 06:19:05 PM PDT 24
Finished Aug 12 06:19:06 PM PDT 24
Peak memory 209756 kb
Host smart-ae3b862e-a3a7-4a9e-afd0-207bd4b183cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451631269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3451631269
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.273924569
Short name T180
Test name
Test status
Simulation time 87704839 ps
CPU time 1.34 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:04 PM PDT 24
Peak memory 210056 kb
Host smart-0250ff3b-44dc-4105-b2fa-41c7fc695a18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273924569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.273924569
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.502552428
Short name T103
Test name
Test status
Simulation time 1784560253 ps
CPU time 3.49 seconds
Started Aug 12 06:19:02 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 219124 kb
Host smart-22bad815-4d2a-4b71-88eb-230dda3bb68e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502552428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.502552428
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.480158810
Short name T968
Test name
Test status
Simulation time 40149427 ps
CPU time 0.98 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 218244 kb
Host smart-fad345b8-09db-44d8-89b5-f7f706489519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480158810 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.480158810
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2989565819
Short name T171
Test name
Test status
Simulation time 14361655 ps
CPU time 0.9 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:04 PM PDT 24
Peak memory 210020 kb
Host smart-c7846063-c6dc-4dde-be83-2baa14459803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989565819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2989565819
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1341837365
Short name T936
Test name
Test status
Simulation time 49313008 ps
CPU time 1.32 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 210028 kb
Host smart-b974e1f2-741d-4ca8-9378-f6d2948b19e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341837365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1341837365
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1433799577
Short name T108
Test name
Test status
Simulation time 124162062 ps
CPU time 4.84 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:12 PM PDT 24
Peak memory 218216 kb
Host smart-5ba21ee9-5fb1-44b4-a2fd-8f184a21c8a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433799577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1433799577
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1683901366
Short name T946
Test name
Test status
Simulation time 17931752 ps
CPU time 1.42 seconds
Started Aug 12 06:19:00 PM PDT 24
Finished Aug 12 06:19:02 PM PDT 24
Peak memory 219316 kb
Host smart-ee506dc6-75e5-43cf-8da5-833a0665ffc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683901366 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1683901366
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3595378045
Short name T168
Test name
Test status
Simulation time 18359378 ps
CPU time 1.15 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:02 PM PDT 24
Peak memory 209748 kb
Host smart-19e8c235-b9d0-4ddb-a527-a291df44d675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595378045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3595378045
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2062471301
Short name T981
Test name
Test status
Simulation time 40749187 ps
CPU time 1.59 seconds
Started Aug 12 06:19:06 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 210004 kb
Host smart-5e42b396-e0a8-4af6-814e-15577bb67f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062471301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2062471301
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.612387056
Short name T922
Test name
Test status
Simulation time 500808133 ps
CPU time 5.17 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:10 PM PDT 24
Peak memory 218220 kb
Host smart-4b7f51e9-ad25-4e15-a42f-1caccc1b093a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612387056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.612387056
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.485462663
Short name T887
Test name
Test status
Simulation time 209518124 ps
CPU time 1.13 seconds
Started Aug 12 06:19:02 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 219292 kb
Host smart-da12f0fe-0d73-4512-9d9b-3932914d164b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485462663 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.485462663
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.268396613
Short name T172
Test name
Test status
Simulation time 64050836 ps
CPU time 0.99 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:04 PM PDT 24
Peak memory 209728 kb
Host smart-0af9adf0-bcf7-4064-96b0-138955d46d20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268396613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.268396613
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2141903586
Short name T943
Test name
Test status
Simulation time 117050122 ps
CPU time 1.42 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 210088 kb
Host smart-65e33047-0cba-4974-8a63-01b71d0b7d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141903586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2141903586
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.159443950
Short name T931
Test name
Test status
Simulation time 86992764 ps
CPU time 3.71 seconds
Started Aug 12 06:19:05 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 218192 kb
Host smart-33742c79-255b-4601-ae14-8f9e7516806a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159443950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.159443950
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.218396811
Short name T155
Test name
Test status
Simulation time 172255733 ps
CPU time 1.09 seconds
Started Aug 12 06:19:11 PM PDT 24
Finished Aug 12 06:19:12 PM PDT 24
Peak memory 221692 kb
Host smart-c0e74b66-bb18-4f1e-9ea8-5fa7ce73d200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218396811 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.218396811
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2813878126
Short name T169
Test name
Test status
Simulation time 22711382 ps
CPU time 0.92 seconds
Started Aug 12 06:19:08 PM PDT 24
Finished Aug 12 06:19:09 PM PDT 24
Peak memory 217880 kb
Host smart-2490bcba-7bd3-4aee-aab8-4709b5196b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813878126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2813878126
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.410804976
Short name T176
Test name
Test status
Simulation time 199356832 ps
CPU time 1.44 seconds
Started Aug 12 06:19:10 PM PDT 24
Finished Aug 12 06:19:12 PM PDT 24
Peak memory 212112 kb
Host smart-d4c09685-0274-4d09-bd9f-b7ba80530537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410804976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.410804976
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4289740773
Short name T945
Test name
Test status
Simulation time 38818778 ps
CPU time 1.15 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:42 PM PDT 24
Peak memory 210040 kb
Host smart-aebf7710-64e2-414c-995a-43e9a32e3b0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289740773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.4289740773
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1208717513
Short name T872
Test name
Test status
Simulation time 144012123 ps
CPU time 1.24 seconds
Started Aug 12 06:18:39 PM PDT 24
Finished Aug 12 06:18:41 PM PDT 24
Peak memory 209264 kb
Host smart-0af9ad98-4bd3-4644-9c11-96134b2a51a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208717513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1208717513
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2241467711
Short name T901
Test name
Test status
Simulation time 37100690 ps
CPU time 1.19 seconds
Started Aug 12 06:18:38 PM PDT 24
Finished Aug 12 06:18:39 PM PDT 24
Peak memory 218944 kb
Host smart-be679cde-055e-4ce3-bf48-82ee7328861c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241467711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2241467711
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3595983004
Short name T989
Test name
Test status
Simulation time 88149765 ps
CPU time 1.41 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:42 PM PDT 24
Peak memory 219920 kb
Host smart-01dfaf78-e7e5-49c3-acde-7bc65468ba76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595983004 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3595983004
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4166727533
Short name T170
Test name
Test status
Simulation time 35935274 ps
CPU time 0.93 seconds
Started Aug 12 06:18:43 PM PDT 24
Finished Aug 12 06:18:44 PM PDT 24
Peak memory 210016 kb
Host smart-9b79a2c6-d593-4ca9-9350-e4aaea29dbf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166727533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4166727533
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1054335228
Short name T883
Test name
Test status
Simulation time 42201104 ps
CPU time 1.12 seconds
Started Aug 12 06:18:40 PM PDT 24
Finished Aug 12 06:18:42 PM PDT 24
Peak memory 209832 kb
Host smart-d20ca66a-60e7-47e9-b5a3-b956f3e566bf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054335228 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1054335228
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.951316622
Short name T940
Test name
Test status
Simulation time 1134962448 ps
CPU time 5.62 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:47 PM PDT 24
Peak memory 209816 kb
Host smart-b66f1a6d-2fb2-4121-a92a-5dbb5e257fbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951316622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.951316622
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2357531993
Short name T881
Test name
Test status
Simulation time 1528320053 ps
CPU time 9.47 seconds
Started Aug 12 06:18:40 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 209776 kb
Host smart-b1bf3266-88a2-47f6-b550-108d78212441
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357531993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2357531993
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2825931408
Short name T894
Test name
Test status
Simulation time 409641200 ps
CPU time 3.1 seconds
Started Aug 12 06:18:38 PM PDT 24
Finished Aug 12 06:18:41 PM PDT 24
Peak memory 211644 kb
Host smart-a2cbc4f1-c2e6-4951-9810-756a7b6f774a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825931408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2825931408
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2800221889
Short name T919
Test name
Test status
Simulation time 724616721 ps
CPU time 5.07 seconds
Started Aug 12 06:18:40 PM PDT 24
Finished Aug 12 06:18:46 PM PDT 24
Peak memory 218304 kb
Host smart-d6ed7c39-1738-4f52-a2a6-167a1ba042e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280022
1889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2800221889
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3031585248
Short name T979
Test name
Test status
Simulation time 227819703 ps
CPU time 1.28 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:42 PM PDT 24
Peak memory 209872 kb
Host smart-b69b67ac-37dd-4cec-aab1-cc611d7af3d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031585248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3031585248
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1431008965
Short name T970
Test name
Test status
Simulation time 72241937 ps
CPU time 1.37 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:42 PM PDT 24
Peak memory 212156 kb
Host smart-2809ff7c-c582-499d-9d4c-a73f34c2828f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431008965 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1431008965
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4192784811
Short name T991
Test name
Test status
Simulation time 189962193 ps
CPU time 1.4 seconds
Started Aug 12 06:18:38 PM PDT 24
Finished Aug 12 06:18:39 PM PDT 24
Peak memory 210032 kb
Host smart-71a8159c-1498-434f-801d-dd4bdb7e4475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192784811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4192784811
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.930275397
Short name T889
Test name
Test status
Simulation time 336711733 ps
CPU time 2.78 seconds
Started Aug 12 06:18:37 PM PDT 24
Finished Aug 12 06:18:40 PM PDT 24
Peak memory 218880 kb
Host smart-71322708-797e-4902-8d88-f1605a05a51c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930275397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.930275397
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.731926987
Short name T938
Test name
Test status
Simulation time 65262201 ps
CPU time 1.21 seconds
Started Aug 12 06:18:47 PM PDT 24
Finished Aug 12 06:18:49 PM PDT 24
Peak memory 209568 kb
Host smart-7e52d2a7-2e9d-4e07-9ac7-65dd0ce3eb76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731926987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.731926987
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2183038314
Short name T897
Test name
Test status
Simulation time 139737975 ps
CPU time 2.5 seconds
Started Aug 12 06:18:47 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 209996 kb
Host smart-41d35c2b-6aad-4aab-bc0f-415c88edd7cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183038314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2183038314
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3130988205
Short name T147
Test name
Test status
Simulation time 18047229 ps
CPU time 1.1 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 210664 kb
Host smart-6fe5d3a7-9afa-4450-955c-2e44e1c545fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130988205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3130988205
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4029562381
Short name T892
Test name
Test status
Simulation time 29170859 ps
CPU time 1.01 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:51 PM PDT 24
Peak memory 220708 kb
Host smart-5bd104d5-1471-4a6e-9283-f0f26eb509cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029562381 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4029562381
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2749479305
Short name T993
Test name
Test status
Simulation time 24916979 ps
CPU time 0.88 seconds
Started Aug 12 06:18:51 PM PDT 24
Finished Aug 12 06:18:52 PM PDT 24
Peak memory 209996 kb
Host smart-998f7dd0-9b98-4a56-b518-3ded3e46c818
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749479305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2749479305
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.601277201
Short name T996
Test name
Test status
Simulation time 39386575 ps
CPU time 1.73 seconds
Started Aug 12 06:18:45 PM PDT 24
Finished Aug 12 06:18:47 PM PDT 24
Peak memory 209872 kb
Host smart-9204485b-b8d2-4825-ace5-26098aac9459
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601277201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.601277201
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1729001179
Short name T939
Test name
Test status
Simulation time 229245415 ps
CPU time 2.8 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:44 PM PDT 24
Peak memory 208692 kb
Host smart-e05a2dcb-86c7-41bc-96fa-3998872058b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729001179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1729001179
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1661384709
Short name T915
Test name
Test status
Simulation time 1252497810 ps
CPU time 14.59 seconds
Started Aug 12 06:18:40 PM PDT 24
Finished Aug 12 06:18:54 PM PDT 24
Peak memory 209168 kb
Host smart-298c59d1-662d-42b0-8cdd-255a55622c1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661384709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1661384709
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1768459706
Short name T983
Test name
Test status
Simulation time 206635129 ps
CPU time 1.7 seconds
Started Aug 12 06:18:39 PM PDT 24
Finished Aug 12 06:18:40 PM PDT 24
Peak memory 211376 kb
Host smart-7febba95-a10d-488a-b20a-20b43dbf1602
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768459706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1768459706
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.912111916
Short name T877
Test name
Test status
Simulation time 183991170 ps
CPU time 3.09 seconds
Started Aug 12 06:18:43 PM PDT 24
Finished Aug 12 06:18:46 PM PDT 24
Peak memory 219112 kb
Host smart-739e4824-ad02-4642-adaf-e88c88db10a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912111
916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.912111916
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4146501590
Short name T930
Test name
Test status
Simulation time 321312668 ps
CPU time 3.98 seconds
Started Aug 12 06:18:42 PM PDT 24
Finished Aug 12 06:18:46 PM PDT 24
Peak memory 209944 kb
Host smart-99154737-ef07-4842-a30d-afbb21fed31e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146501590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4146501590
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2645006300
Short name T997
Test name
Test status
Simulation time 31831702 ps
CPU time 0.97 seconds
Started Aug 12 06:18:46 PM PDT 24
Finished Aug 12 06:18:47 PM PDT 24
Peak memory 210044 kb
Host smart-6f56ecfc-e270-406b-9243-f9ca46263636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645006300 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2645006300
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.620676695
Short name T904
Test name
Test status
Simulation time 19580965 ps
CPU time 1.45 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:51 PM PDT 24
Peak memory 212168 kb
Host smart-6e71db6f-53ab-4302-a00a-5898650f0a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620676695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.620676695
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1897081853
Short name T927
Test name
Test status
Simulation time 48759294 ps
CPU time 2.2 seconds
Started Aug 12 06:18:41 PM PDT 24
Finished Aug 12 06:18:43 PM PDT 24
Peak memory 218180 kb
Host smart-d1f34ec1-2e31-454b-a9cd-a248907e5aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897081853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1897081853
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1803976563
Short name T969
Test name
Test status
Simulation time 14028589 ps
CPU time 0.97 seconds
Started Aug 12 06:18:48 PM PDT 24
Finished Aug 12 06:18:49 PM PDT 24
Peak memory 210128 kb
Host smart-0ce1e7d0-ac26-471c-8265-1898034e4e19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803976563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1803976563
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2091965050
Short name T906
Test name
Test status
Simulation time 41392002 ps
CPU time 1.32 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 210080 kb
Host smart-ab4aa38b-e21d-4e40-9a8b-31c5689f0e45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091965050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2091965050
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.823492308
Short name T954
Test name
Test status
Simulation time 34292639 ps
CPU time 1.23 seconds
Started Aug 12 06:18:48 PM PDT 24
Finished Aug 12 06:18:49 PM PDT 24
Peak memory 212204 kb
Host smart-542f9278-da56-449d-9a0f-83137cd4bd98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823492308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.823492308
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.509149334
Short name T935
Test name
Test status
Simulation time 48952143 ps
CPU time 1.16 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 218356 kb
Host smart-0b1a6ed1-9ed4-4470-a091-9d9c76b9175e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509149334 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.509149334
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1371368812
Short name T175
Test name
Test status
Simulation time 13530502 ps
CPU time 1.02 seconds
Started Aug 12 06:18:50 PM PDT 24
Finished Aug 12 06:18:51 PM PDT 24
Peak memory 209660 kb
Host smart-fe5f11d8-1e6a-45e6-a256-90ea3997acbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371368812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1371368812
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1649679692
Short name T916
Test name
Test status
Simulation time 94197988 ps
CPU time 1.58 seconds
Started Aug 12 06:18:48 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 209820 kb
Host smart-b55a88bf-fb3b-4a6d-abcf-91be7ca63b3f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649679692 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1649679692
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4104490413
Short name T884
Test name
Test status
Simulation time 1667901412 ps
CPU time 9.85 seconds
Started Aug 12 06:18:48 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 209212 kb
Host smart-97beea1e-fd53-4233-b2da-360870c60946
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104490413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4104490413
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.939534333
Short name T942
Test name
Test status
Simulation time 691769066 ps
CPU time 17.26 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:19:06 PM PDT 24
Peak memory 209688 kb
Host smart-1b08f9b4-dead-4808-bd11-9f5c6a802459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939534333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.939534333
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4063486366
Short name T130
Test name
Test status
Simulation time 516114455 ps
CPU time 2.8 seconds
Started Aug 12 06:18:50 PM PDT 24
Finished Aug 12 06:18:53 PM PDT 24
Peak memory 211488 kb
Host smart-9d57b703-0173-4581-bcd0-1122588ffa3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063486366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4063486366
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.768658040
Short name T925
Test name
Test status
Simulation time 103789553 ps
CPU time 1.54 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 218288 kb
Host smart-30c6e738-201b-4373-8a7d-0dded8ea2593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768658
040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.768658040
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.319034116
Short name T950
Test name
Test status
Simulation time 65248434 ps
CPU time 1.82 seconds
Started Aug 12 06:18:51 PM PDT 24
Finished Aug 12 06:18:52 PM PDT 24
Peak memory 209996 kb
Host smart-ef10c72e-913d-4f1d-8753-6597a8c1803e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319034116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.319034116
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1317071132
Short name T179
Test name
Test status
Simulation time 138775710 ps
CPU time 1.83 seconds
Started Aug 12 06:18:48 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 212176 kb
Host smart-c605311e-10eb-461d-a73e-4e5b093534ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317071132 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1317071132
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1412892995
Short name T957
Test name
Test status
Simulation time 141790141 ps
CPU time 1.93 seconds
Started Aug 12 06:18:48 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 210020 kb
Host smart-70ed10d0-ef16-4548-bea4-2f8334955327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412892995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1412892995
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.214632005
Short name T941
Test name
Test status
Simulation time 357306456 ps
CPU time 3.73 seconds
Started Aug 12 06:18:50 PM PDT 24
Finished Aug 12 06:18:54 PM PDT 24
Peak memory 218276 kb
Host smart-27fccd87-e461-476f-b4c0-dc7433acc1ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214632005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.214632005
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1806592638
Short name T104
Test name
Test status
Simulation time 468519704 ps
CPU time 2.91 seconds
Started Aug 12 06:18:47 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 218252 kb
Host smart-afe6294c-47e3-474c-bb7a-6dafe4c81f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806592638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1806592638
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3516087795
Short name T932
Test name
Test status
Simulation time 29269387 ps
CPU time 1.6 seconds
Started Aug 12 06:18:55 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 219164 kb
Host smart-97d58177-676e-42d0-af15-82024958fc28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516087795 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3516087795
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2028323202
Short name T990
Test name
Test status
Simulation time 82134361 ps
CPU time 0.98 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 210028 kb
Host smart-9abf5122-e194-4764-8108-dfbaba914c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028323202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2028323202
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3737806794
Short name T965
Test name
Test status
Simulation time 50472568 ps
CPU time 1.8 seconds
Started Aug 12 06:18:51 PM PDT 24
Finished Aug 12 06:18:53 PM PDT 24
Peak memory 208736 kb
Host smart-8c7751f5-d3da-4149-8c8e-c4ef1fd78fd4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737806794 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3737806794
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3929249207
Short name T888
Test name
Test status
Simulation time 3309930503 ps
CPU time 10.44 seconds
Started Aug 12 06:18:47 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 209960 kb
Host smart-3be06b64-b8bd-4665-96ef-30764aa93019
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929249207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3929249207
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.857377511
Short name T972
Test name
Test status
Simulation time 6313828580 ps
CPU time 28.23 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:19:18 PM PDT 24
Peak memory 209324 kb
Host smart-cabb9c0d-73df-4879-a6ea-7a5530fc86f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857377511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.857377511
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1862422533
Short name T934
Test name
Test status
Simulation time 266595120 ps
CPU time 1.19 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 209904 kb
Host smart-e6339751-772b-4393-858d-5f17076a6afa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862422533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1862422533
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3106049694
Short name T924
Test name
Test status
Simulation time 114948630 ps
CPU time 3.44 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:52 PM PDT 24
Peak memory 219300 kb
Host smart-87394da9-62e4-4a28-8fb9-aab8c1b6f118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310604
9694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3106049694
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4290406519
Short name T988
Test name
Test status
Simulation time 35855726 ps
CPU time 1.53 seconds
Started Aug 12 06:18:49 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 209984 kb
Host smart-33e8bab7-2832-4e89-9101-f1c04231f5c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290406519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4290406519
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3027148298
Short name T958
Test name
Test status
Simulation time 108939952 ps
CPU time 1.04 seconds
Started Aug 12 06:18:48 PM PDT 24
Finished Aug 12 06:18:50 PM PDT 24
Peak memory 209984 kb
Host smart-fa646955-c890-4d74-8126-977af2efe5f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027148298 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3027148298
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.364784318
Short name T928
Test name
Test status
Simulation time 36202243 ps
CPU time 0.95 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 208836 kb
Host smart-fcb481fa-0450-407d-bb78-785eff76af61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364784318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.364784318
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.613334798
Short name T900
Test name
Test status
Simulation time 305839861 ps
CPU time 2.6 seconds
Started Aug 12 06:18:50 PM PDT 24
Finished Aug 12 06:18:52 PM PDT 24
Peak memory 218744 kb
Host smart-ba95a5bf-c9f8-4515-bc32-5c13eea8d662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613334798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.613334798
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3968896771
Short name T125
Test name
Test status
Simulation time 177011462 ps
CPU time 2.29 seconds
Started Aug 12 06:18:46 PM PDT 24
Finished Aug 12 06:18:49 PM PDT 24
Peak memory 218236 kb
Host smart-3caff12f-6b69-44e2-8283-09b41d301fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968896771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3968896771
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2191059895
Short name T895
Test name
Test status
Simulation time 21814053 ps
CPU time 1.33 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 218236 kb
Host smart-60c00ae0-4032-478c-a253-3d9a8098de12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191059895 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2191059895
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4144680635
Short name T959
Test name
Test status
Simulation time 23082714 ps
CPU time 0.83 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 209196 kb
Host smart-1c28430f-428e-4fd5-99b4-da27c2931af4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144680635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4144680635
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2743956550
Short name T960
Test name
Test status
Simulation time 78971314 ps
CPU time 0.88 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 208712 kb
Host smart-7904048a-0bc2-4861-8ba8-b18c49e119d3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743956550 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2743956550
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1633539939
Short name T880
Test name
Test status
Simulation time 1300415538 ps
CPU time 3.99 seconds
Started Aug 12 06:18:56 PM PDT 24
Finished Aug 12 06:19:00 PM PDT 24
Peak memory 209720 kb
Host smart-51f015fb-46fa-425c-acf9-168f109cc8cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633539939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1633539939
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4264167165
Short name T974
Test name
Test status
Simulation time 20618313503 ps
CPU time 24.69 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:19:22 PM PDT 24
Peak memory 209956 kb
Host smart-39b31663-c030-4b00-820c-6eb58142f331
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264167165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4264167165
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.405902405
Short name T885
Test name
Test status
Simulation time 292372435 ps
CPU time 2.67 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:07 PM PDT 24
Peak memory 209940 kb
Host smart-575e25ea-27bc-42f8-aee2-f85611767a1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405902405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.405902405
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3342123502
Short name T987
Test name
Test status
Simulation time 538352828 ps
CPU time 2.19 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:59 PM PDT 24
Peak memory 219356 kb
Host smart-48831956-65b6-453f-8db8-82559f8e27a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334212
3502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3342123502
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1125543395
Short name T129
Test name
Test status
Simulation time 76492838 ps
CPU time 1.36 seconds
Started Aug 12 06:18:54 PM PDT 24
Finished Aug 12 06:18:56 PM PDT 24
Peak memory 209944 kb
Host smart-b1d69cc1-2b98-44d6-b89c-ec4fae1da417
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125543395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1125543395
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2404367794
Short name T971
Test name
Test status
Simulation time 40583250 ps
CPU time 1.1 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:58 PM PDT 24
Peak memory 210084 kb
Host smart-9d042195-f59c-414e-9803-a56214034aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404367794 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2404367794
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.510385551
Short name T106
Test name
Test status
Simulation time 45242528 ps
CPU time 1.02 seconds
Started Aug 12 06:18:56 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 209968 kb
Host smart-e7f28fb4-b342-410f-92d2-3a2fc396a6f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510385551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.510385551
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3560072835
Short name T117
Test name
Test status
Simulation time 694363907 ps
CPU time 5.79 seconds
Started Aug 12 06:18:54 PM PDT 24
Finished Aug 12 06:18:59 PM PDT 24
Peak memory 218200 kb
Host smart-d0838d9b-c8ed-4fba-8457-80fc34f2d51f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560072835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3560072835
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1489348196
Short name T154
Test name
Test status
Simulation time 21971390 ps
CPU time 1.16 seconds
Started Aug 12 06:18:56 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 218372 kb
Host smart-7423f4f6-e1b8-4215-8eb7-edebad7bf091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489348196 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1489348196
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2712385417
Short name T953
Test name
Test status
Simulation time 19974821 ps
CPU time 0.89 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 209456 kb
Host smart-5cb526ee-847c-4cb0-a8ea-fa35bb7d7f22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712385417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2712385417
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4004896673
Short name T912
Test name
Test status
Simulation time 148154965 ps
CPU time 1.86 seconds
Started Aug 12 06:18:59 PM PDT 24
Finished Aug 12 06:19:01 PM PDT 24
Peak memory 208556 kb
Host smart-fb1042b9-5f80-4f3f-8eda-e0e3bed15735
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004896673 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4004896673
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2949580098
Short name T917
Test name
Test status
Simulation time 877337723 ps
CPU time 19.58 seconds
Started Aug 12 06:18:54 PM PDT 24
Finished Aug 12 06:19:14 PM PDT 24
Peak memory 209836 kb
Host smart-5e656df9-c932-4835-8878-7d3e4cc1f014
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949580098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2949580098
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.656007621
Short name T886
Test name
Test status
Simulation time 8909115468 ps
CPU time 43.87 seconds
Started Aug 12 06:18:56 PM PDT 24
Finished Aug 12 06:19:40 PM PDT 24
Peak memory 210004 kb
Host smart-c342700b-09fc-46f6-b421-b7605ce8471f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656007621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.656007621
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.745562950
Short name T948
Test name
Test status
Simulation time 1880069831 ps
CPU time 3.51 seconds
Started Aug 12 06:19:03 PM PDT 24
Finished Aug 12 06:19:07 PM PDT 24
Peak memory 209912 kb
Host smart-ff4d9fbd-72a8-4ad3-9734-615574992dd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745562950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.745562950
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1926818326
Short name T891
Test name
Test status
Simulation time 1612822512 ps
CPU time 4.33 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 218344 kb
Host smart-d1592b2f-9283-4636-aac7-83eb3a4f35d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192681
8326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1926818326
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2902839816
Short name T994
Test name
Test status
Simulation time 56027807 ps
CPU time 1.46 seconds
Started Aug 12 06:19:05 PM PDT 24
Finished Aug 12 06:19:06 PM PDT 24
Peak memory 209936 kb
Host smart-1e7c77f2-032c-4aac-9e7e-dc6fdbd629ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902839816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2902839816
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2962818864
Short name T178
Test name
Test status
Simulation time 67075009 ps
CPU time 1.16 seconds
Started Aug 12 06:18:54 PM PDT 24
Finished Aug 12 06:18:55 PM PDT 24
Peak memory 209976 kb
Host smart-80a94a04-fe18-4e09-9e77-92dc3b9ec5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962818864 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2962818864
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.41563976
Short name T903
Test name
Test status
Simulation time 25346291 ps
CPU time 1.03 seconds
Started Aug 12 06:18:59 PM PDT 24
Finished Aug 12 06:19:00 PM PDT 24
Peak memory 209960 kb
Host smart-28379762-b8a6-47c9-b309-bbedf5bd766b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41563976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_s
ame_csr_outstanding.41563976
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1151570231
Short name T107
Test name
Test status
Simulation time 231345563 ps
CPU time 2.36 seconds
Started Aug 12 06:18:53 PM PDT 24
Finished Aug 12 06:18:56 PM PDT 24
Peak memory 218344 kb
Host smart-0d9b2c4e-8102-4a20-a302-194a2190f54f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151570231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1151570231
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3117910285
Short name T115
Test name
Test status
Simulation time 83845495 ps
CPU time 1.86 seconds
Started Aug 12 06:18:54 PM PDT 24
Finished Aug 12 06:18:56 PM PDT 24
Peak memory 222788 kb
Host smart-a43f1571-3d85-4fc5-a770-c9a5591346a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117910285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3117910285
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1122609214
Short name T878
Test name
Test status
Simulation time 72294130 ps
CPU time 1.2 seconds
Started Aug 12 06:18:53 PM PDT 24
Finished Aug 12 06:18:54 PM PDT 24
Peak memory 222600 kb
Host smart-86c4ddf6-2236-43b0-9449-bed3bbbdfbf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122609214 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1122609214
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2202625460
Short name T911
Test name
Test status
Simulation time 13570373 ps
CPU time 0.88 seconds
Started Aug 12 06:18:56 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 209552 kb
Host smart-bd004817-132f-4356-bc37-f0aac1e04a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202625460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2202625460
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3835619213
Short name T874
Test name
Test status
Simulation time 119966229 ps
CPU time 2.03 seconds
Started Aug 12 06:18:55 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 209920 kb
Host smart-a96f25ea-311e-4948-a0c0-e4762a7bf755
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835619213 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3835619213
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2907622022
Short name T127
Test name
Test status
Simulation time 6021406025 ps
CPU time 8.8 seconds
Started Aug 12 06:18:56 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 209584 kb
Host smart-43ab00a2-7f50-4d0e-b146-46fd50224542
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907622022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2907622022
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3986442454
Short name T973
Test name
Test status
Simulation time 2107246177 ps
CPU time 13.1 seconds
Started Aug 12 06:18:52 PM PDT 24
Finished Aug 12 06:19:06 PM PDT 24
Peak memory 209792 kb
Host smart-acd180e8-8545-4593-ad7e-a6f68e8b4e82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986442454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3986442454
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1258642940
Short name T876
Test name
Test status
Simulation time 68237758 ps
CPU time 1.32 seconds
Started Aug 12 06:18:55 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 211404 kb
Host smart-e8b6d79c-d4a5-4eda-b83a-8f9b8418e1a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258642940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1258642940
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4214150537
Short name T908
Test name
Test status
Simulation time 231439296 ps
CPU time 3.34 seconds
Started Aug 12 06:18:56 PM PDT 24
Finished Aug 12 06:19:00 PM PDT 24
Peak memory 218284 kb
Host smart-5eb59b1b-f26b-40a3-a343-2a7ba173e7ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421415
0537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4214150537
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3682615005
Short name T923
Test name
Test status
Simulation time 62647935 ps
CPU time 2.16 seconds
Started Aug 12 06:18:55 PM PDT 24
Finished Aug 12 06:18:57 PM PDT 24
Peak memory 210036 kb
Host smart-cc989ed2-efc1-4e21-b4db-12ee7f8eadd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682615005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3682615005
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.800113369
Short name T914
Test name
Test status
Simulation time 65746822 ps
CPU time 1.14 seconds
Started Aug 12 06:18:55 PM PDT 24
Finished Aug 12 06:18:56 PM PDT 24
Peak memory 210088 kb
Host smart-85eb656b-6c3e-4da5-a5d8-ffa8cf2a3509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800113369 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.800113369
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3421978665
Short name T145
Test name
Test status
Simulation time 155263548 ps
CPU time 1.42 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:02 PM PDT 24
Peak memory 209984 kb
Host smart-2a2ab2f4-6de0-4c95-a36e-5c52816f1872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421978665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3421978665
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3200550896
Short name T913
Test name
Test status
Simulation time 24371574 ps
CPU time 1.8 seconds
Started Aug 12 06:18:57 PM PDT 24
Finished Aug 12 06:18:59 PM PDT 24
Peak memory 218596 kb
Host smart-9ec4348c-46ce-49e7-9740-eaa6b759c37f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200550896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3200550896
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3948088530
Short name T122
Test name
Test status
Simulation time 433539359 ps
CPU time 3.92 seconds
Started Aug 12 06:18:55 PM PDT 24
Finished Aug 12 06:18:59 PM PDT 24
Peak memory 218268 kb
Host smart-19ae7644-7ee1-46a9-bf20-503a0e985a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948088530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3948088530
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1315583394
Short name T975
Test name
Test status
Simulation time 30717447 ps
CPU time 1.19 seconds
Started Aug 12 06:18:59 PM PDT 24
Finished Aug 12 06:19:01 PM PDT 24
Peak memory 218384 kb
Host smart-8123c801-059b-48cb-9144-de0dc388c346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315583394 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1315583394
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3020663615
Short name T174
Test name
Test status
Simulation time 120383055 ps
CPU time 0.92 seconds
Started Aug 12 06:19:02 PM PDT 24
Finished Aug 12 06:19:03 PM PDT 24
Peak memory 209980 kb
Host smart-4452c0b0-7709-49c3-ade6-ba56a19b2443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020663615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3020663615
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2294409801
Short name T955
Test name
Test status
Simulation time 19819404 ps
CPU time 1.18 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 208708 kb
Host smart-836398e1-c3c7-43e4-a453-fef34c063ca1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294409801 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2294409801
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3949797486
Short name T963
Test name
Test status
Simulation time 6127998984 ps
CPU time 25.41 seconds
Started Aug 12 06:19:02 PM PDT 24
Finished Aug 12 06:19:27 PM PDT 24
Peak memory 209320 kb
Host smart-440e6bcc-7fce-4790-a3c4-459a805269b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949797486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3949797486
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4268418580
Short name T132
Test name
Test status
Simulation time 3247331432 ps
CPU time 8.24 seconds
Started Aug 12 06:19:05 PM PDT 24
Finished Aug 12 06:19:13 PM PDT 24
Peak memory 209264 kb
Host smart-341fbfbe-b55c-4a17-909b-177c17f994ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268418580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4268418580
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1846970514
Short name T921
Test name
Test status
Simulation time 348281434 ps
CPU time 2.4 seconds
Started Aug 12 06:19:04 PM PDT 24
Finished Aug 12 06:19:07 PM PDT 24
Peak memory 211456 kb
Host smart-d8f7f6e3-759f-47eb-9b9b-55271e160003
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846970514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1846970514
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.942495738
Short name T967
Test name
Test status
Simulation time 97825529 ps
CPU time 3.45 seconds
Started Aug 12 06:19:01 PM PDT 24
Finished Aug 12 06:19:05 PM PDT 24
Peak memory 218280 kb
Host smart-7c124d0a-22fd-4b5c-b18a-d6a0347f02a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942495
738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.942495738
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1489866686
Short name T992
Test name
Test status
Simulation time 203256215 ps
CPU time 1.14 seconds
Started Aug 12 06:18:58 PM PDT 24
Finished Aug 12 06:18:59 PM PDT 24
Peak memory 209948 kb
Host smart-77156acf-7a0e-40b6-8618-85db55486340
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489866686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1489866686
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3139638137
Short name T181
Test name
Test status
Simulation time 40401766 ps
CPU time 1.12 seconds
Started Aug 12 06:19:05 PM PDT 24
Finished Aug 12 06:19:06 PM PDT 24
Peak memory 210016 kb
Host smart-ce854df6-92b8-4edf-a4d1-f34344c49f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139638137 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3139638137
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2643571276
Short name T929
Test name
Test status
Simulation time 142043288 ps
CPU time 1.25 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 209992 kb
Host smart-18e81660-e74b-48ad-bac3-118c698df0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643571276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2643571276
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1923443883
Short name T109
Test name
Test status
Simulation time 81393739 ps
CPU time 1.64 seconds
Started Aug 12 06:19:06 PM PDT 24
Finished Aug 12 06:19:08 PM PDT 24
Peak memory 218928 kb
Host smart-9e8171bf-c48e-45d8-bacb-4b50f1faed76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923443883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1923443883
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3906101669
Short name T977
Test name
Test status
Simulation time 363099131 ps
CPU time 2.05 seconds
Started Aug 12 06:19:07 PM PDT 24
Finished Aug 12 06:19:09 PM PDT 24
Peak memory 222840 kb
Host smart-d3003b3c-536b-4904-85b8-5ac462a551e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906101669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3906101669
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3887406110
Short name T88
Test name
Test status
Simulation time 337765927 ps
CPU time 0.91 seconds
Started Aug 12 06:43:43 PM PDT 24
Finished Aug 12 06:43:44 PM PDT 24
Peak memory 209496 kb
Host smart-55f84c43-2100-4424-9205-7f3f5b9b47b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887406110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3887406110
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.541898351
Short name T201
Test name
Test status
Simulation time 14152418 ps
CPU time 0.82 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:43:45 PM PDT 24
Peak memory 209176 kb
Host smart-2c4b54d2-9474-432a-bc5d-c6d24cebbc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541898351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.541898351
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.160771092
Short name T356
Test name
Test status
Simulation time 991963711 ps
CPU time 17.99 seconds
Started Aug 12 06:43:42 PM PDT 24
Finished Aug 12 06:44:00 PM PDT 24
Peak memory 218884 kb
Host smart-9146ac60-13c7-4760-901c-6f02aa59ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160771092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.160771092
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.605006560
Short name T767
Test name
Test status
Simulation time 1020819186 ps
CPU time 12.88 seconds
Started Aug 12 06:43:42 PM PDT 24
Finished Aug 12 06:43:55 PM PDT 24
Peak memory 217656 kb
Host smart-64881e35-9396-4a75-bf31-5b42a3dab18e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605006560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.605006560
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.5497767
Short name T806
Test name
Test status
Simulation time 3945729919 ps
CPU time 28.5 seconds
Started Aug 12 06:43:54 PM PDT 24
Finished Aug 12 06:44:22 PM PDT 24
Peak memory 219484 kb
Host smart-3e75dedd-b811-4336-90fa-d0aab851b3ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5497767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_error
s.5497767
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3733392686
Short name T621
Test name
Test status
Simulation time 1220075028 ps
CPU time 5.35 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:43:50 PM PDT 24
Peak memory 218268 kb
Host smart-1fd6b004-7d48-45a6-8381-5abc3bd7acc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733392686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
733392686
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2555769281
Short name T229
Test name
Test status
Simulation time 497203621 ps
CPU time 4.07 seconds
Started Aug 12 06:43:42 PM PDT 24
Finished Aug 12 06:43:46 PM PDT 24
Peak memory 218808 kb
Host smart-acdcf240-6e72-462b-8c91-351939b78df5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555769281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2555769281
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.65566205
Short name T278
Test name
Test status
Simulation time 1208468127 ps
CPU time 30.84 seconds
Started Aug 12 06:43:47 PM PDT 24
Finished Aug 12 06:44:18 PM PDT 24
Peak memory 218288 kb
Host smart-4bdb4acc-6904-462e-85cb-543af6302317
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65566205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_regwen_during_op.65566205
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.764110790
Short name T329
Test name
Test status
Simulation time 306181317 ps
CPU time 2.49 seconds
Started Aug 12 06:43:45 PM PDT 24
Finished Aug 12 06:43:47 PM PDT 24
Peak memory 218160 kb
Host smart-10413f82-14df-4c51-9011-10c7275dadb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764110790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.764110790
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1798492093
Short name T588
Test name
Test status
Simulation time 5859499937 ps
CPU time 56.56 seconds
Started Aug 12 06:43:47 PM PDT 24
Finished Aug 12 06:44:44 PM PDT 24
Peak memory 268132 kb
Host smart-678feb7a-c0d4-4dd7-8441-da5b81471cc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798492093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1798492093
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.494262119
Short name T394
Test name
Test status
Simulation time 327895814 ps
CPU time 14.22 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:07 PM PDT 24
Peak memory 251396 kb
Host smart-62d5de99-41f5-4111-9181-8b0bb6492a62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494262119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.494262119
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.608903983
Short name T340
Test name
Test status
Simulation time 147378268 ps
CPU time 2.98 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:43:47 PM PDT 24
Peak memory 218844 kb
Host smart-01aacb17-7095-445d-8c05-9c0c7f0607da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608903983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.608903983
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3962824390
Short name T402
Test name
Test status
Simulation time 1470983582 ps
CPU time 22.47 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:44:07 PM PDT 24
Peak memory 218180 kb
Host smart-d087e463-1913-42ea-a335-ae34b4309b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962824390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3962824390
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2741489339
Short name T91
Test name
Test status
Simulation time 414308266 ps
CPU time 40.66 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:33 PM PDT 24
Peak memory 284760 kb
Host smart-6c3814b1-baa5-4f46-9cd8-e31ec47faad8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741489339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2741489339
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.301939563
Short name T274
Test name
Test status
Simulation time 977436118 ps
CPU time 8.77 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:01 PM PDT 24
Peak memory 226632 kb
Host smart-4afbfd6a-991f-48e3-9bde-a4ec36b2d593
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301939563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.301939563
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2584916689
Short name T378
Test name
Test status
Simulation time 831957016 ps
CPU time 7.8 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:43:52 PM PDT 24
Peak memory 226568 kb
Host smart-ef99a370-6b92-417d-9819-ba0457652dea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584916689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2584916689
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3400820860
Short name T568
Test name
Test status
Simulation time 188538103 ps
CPU time 5.87 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:43:50 PM PDT 24
Peak memory 218780 kb
Host smart-5aaec707-c025-430f-85e4-ea2301e7bdd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400820860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
400820860
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.786388169
Short name T870
Test name
Test status
Simulation time 1614688561 ps
CPU time 12.43 seconds
Started Aug 12 06:43:43 PM PDT 24
Finished Aug 12 06:43:56 PM PDT 24
Peak memory 226652 kb
Host smart-18204b98-5890-430f-8c16-0e95b61be66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786388169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.786388169
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1527298812
Short name T273
Test name
Test status
Simulation time 105991139 ps
CPU time 1.14 seconds
Started Aug 12 06:43:47 PM PDT 24
Finished Aug 12 06:43:49 PM PDT 24
Peak memory 218288 kb
Host smart-dc9f9e2d-2090-486e-9e7d-91f6f3e34069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527298812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1527298812
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.144595065
Short name T757
Test name
Test status
Simulation time 1052309467 ps
CPU time 24.32 seconds
Started Aug 12 06:43:42 PM PDT 24
Finished Aug 12 06:44:06 PM PDT 24
Peak memory 251452 kb
Host smart-7edba3da-a62b-4345-a291-d5913f242bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144595065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.144595065
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2087907606
Short name T718
Test name
Test status
Simulation time 55254519 ps
CPU time 6 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:43:50 PM PDT 24
Peak memory 251400 kb
Host smart-c1582dd3-b64f-4572-8db7-2f9946bfedd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087907606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2087907606
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1810420877
Short name T328
Test name
Test status
Simulation time 14088614545 ps
CPU time 150.14 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:46:14 PM PDT 24
Peak memory 311980 kb
Host smart-00f2c275-2a17-4b23-b5ea-873a942c5117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810420877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1810420877
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.698013464
Short name T611
Test name
Test status
Simulation time 8937093429 ps
CPU time 122.31 seconds
Started Aug 12 06:43:54 PM PDT 24
Finished Aug 12 06:45:56 PM PDT 24
Peak memory 256428 kb
Host smart-27990b03-bc4d-4c29-9b01-df204057ece6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=698013464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.698013464
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2376410477
Short name T618
Test name
Test status
Simulation time 61760486 ps
CPU time 0.92 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:43:53 PM PDT 24
Peak memory 209492 kb
Host smart-7d02713c-b6c2-4c95-8312-3a9823f1e994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376410477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2376410477
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2323213415
Short name T863
Test name
Test status
Simulation time 526697681 ps
CPU time 10.9 seconds
Started Aug 12 06:43:56 PM PDT 24
Finished Aug 12 06:44:07 PM PDT 24
Peak memory 218884 kb
Host smart-5267955d-996c-4229-89a0-09e70852002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323213415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2323213415
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2392764244
Short name T403
Test name
Test status
Simulation time 264132123 ps
CPU time 4.47 seconds
Started Aug 12 06:43:53 PM PDT 24
Finished Aug 12 06:43:58 PM PDT 24
Peak memory 217904 kb
Host smart-4d6ea3ed-8a3b-41fd-8b92-51b281e411a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392764244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2392764244
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2236362033
Short name T708
Test name
Test status
Simulation time 2771573152 ps
CPU time 41.34 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:34 PM PDT 24
Peak memory 218812 kb
Host smart-89cadd24-57e8-4c2e-a0f9-5b8dd2c9b057
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236362033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2236362033
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1599428565
Short name T313
Test name
Test status
Simulation time 232729263 ps
CPU time 2.15 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:43:55 PM PDT 24
Peak memory 218232 kb
Host smart-74547718-257c-45ae-8224-184c4d03def0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599428565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
599428565
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2565534223
Short name T723
Test name
Test status
Simulation time 259154419 ps
CPU time 4.79 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:43:57 PM PDT 24
Peak memory 223660 kb
Host smart-ae13e452-746c-4872-b5ee-67fd46f8f592
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565534223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2565534223
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3137637950
Short name T396
Test name
Test status
Simulation time 2113454432 ps
CPU time 31.97 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:24 PM PDT 24
Peak memory 218176 kb
Host smart-831b2dc0-c4c3-4eed-9a74-e77a68114999
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137637950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3137637950
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3760010012
Short name T477
Test name
Test status
Simulation time 677172572 ps
CPU time 3.88 seconds
Started Aug 12 06:43:56 PM PDT 24
Finished Aug 12 06:44:00 PM PDT 24
Peak memory 218140 kb
Host smart-92704ad4-e744-4a01-b6b3-015a9e8cb74e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760010012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3760010012
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.168233079
Short name T479
Test name
Test status
Simulation time 6442851665 ps
CPU time 45.86 seconds
Started Aug 12 06:43:55 PM PDT 24
Finished Aug 12 06:44:41 PM PDT 24
Peak memory 276060 kb
Host smart-b94b8442-e717-422e-be5e-691fdaf25260
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168233079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.168233079
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.4147346347
Short name T435
Test name
Test status
Simulation time 2241953022 ps
CPU time 21.99 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:14 PM PDT 24
Peak memory 248228 kb
Host smart-75db7e42-5560-4fa5-94fb-0e61cd9abb98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147346347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.4147346347
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4059986310
Short name T762
Test name
Test status
Simulation time 49058134 ps
CPU time 1.66 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:43:53 PM PDT 24
Peak memory 218920 kb
Host smart-3e828fd3-84ac-441b-80fa-a4f6a6956a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059986310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4059986310
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2775909150
Short name T503
Test name
Test status
Simulation time 259221404 ps
CPU time 10.52 seconds
Started Aug 12 06:43:51 PM PDT 24
Finished Aug 12 06:44:02 PM PDT 24
Peak memory 218184 kb
Host smart-d6b24748-80b5-4448-bc18-f0b57bb7b364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775909150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2775909150
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2968800642
Short name T57
Test name
Test status
Simulation time 193370434 ps
CPU time 38.23 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:30 PM PDT 24
Peak memory 284788 kb
Host smart-0ded160a-3c7b-48fc-8857-eb4a6f4bdf18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968800642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2968800642
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2625765826
Short name T426
Test name
Test status
Simulation time 1327807692 ps
CPU time 10.5 seconds
Started Aug 12 06:43:53 PM PDT 24
Finished Aug 12 06:44:03 PM PDT 24
Peak memory 219468 kb
Host smart-3786be77-e2d3-4b86-8889-c5ba05b338d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625765826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2625765826
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2479138527
Short name T531
Test name
Test status
Simulation time 516837326 ps
CPU time 19.71 seconds
Started Aug 12 06:43:55 PM PDT 24
Finished Aug 12 06:44:14 PM PDT 24
Peak memory 226576 kb
Host smart-f3703d29-4cb5-4481-ba27-0b29d87b4bcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479138527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2479138527
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1714141279
Short name T290
Test name
Test status
Simulation time 4400242475 ps
CPU time 7.98 seconds
Started Aug 12 06:43:53 PM PDT 24
Finished Aug 12 06:44:01 PM PDT 24
Peak memory 218924 kb
Host smart-b65fdc3a-dca6-4419-a3f3-9d0734232f9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714141279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
714141279
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4134304234
Short name T416
Test name
Test status
Simulation time 259366497 ps
CPU time 7.84 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:00 PM PDT 24
Peak memory 226636 kb
Host smart-c30b2aab-3e52-4e55-b035-f48cf89082bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134304234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4134304234
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.783395867
Short name T606
Test name
Test status
Simulation time 31948937 ps
CPU time 2.53 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:43:55 PM PDT 24
Peak memory 214840 kb
Host smart-901b0de5-cf7a-4634-a30a-027db48eacd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783395867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.783395867
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3705348301
Short name T523
Test name
Test status
Simulation time 274518365 ps
CPU time 29.84 seconds
Started Aug 12 06:43:55 PM PDT 24
Finished Aug 12 06:44:25 PM PDT 24
Peak memory 251472 kb
Host smart-e8bd71da-670b-46fe-a5e3-0cfc294186f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705348301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3705348301
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.199164233
Short name T210
Test name
Test status
Simulation time 224806767 ps
CPU time 6.85 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:00 PM PDT 24
Peak memory 251284 kb
Host smart-6bb7953a-0fd5-42e5-a460-d0c337545469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199164233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.199164233
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2677144484
Short name T152
Test name
Test status
Simulation time 78321979116 ps
CPU time 610.92 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:54:03 PM PDT 24
Peak memory 284228 kb
Host smart-f39b7282-1071-4b5e-bb46-5d9657cb05a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677144484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2677144484
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4103406933
Short name T607
Test name
Test status
Simulation time 2852326225 ps
CPU time 104.13 seconds
Started Aug 12 06:43:55 PM PDT 24
Finished Aug 12 06:45:39 PM PDT 24
Peak memory 272644 kb
Host smart-632c8bc9-41a9-42c8-892f-7d552e5dd2fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4103406933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.4103406933
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3883410894
Short name T514
Test name
Test status
Simulation time 17354873 ps
CPU time 0.92 seconds
Started Aug 12 06:43:44 PM PDT 24
Finished Aug 12 06:43:45 PM PDT 24
Peak memory 212448 kb
Host smart-4d31bd07-89bb-45a9-bf9c-21274c7e2c97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883410894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3883410894
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.674957570
Short name T272
Test name
Test status
Simulation time 23385647 ps
CPU time 1.33 seconds
Started Aug 12 06:44:50 PM PDT 24
Finished Aug 12 06:44:51 PM PDT 24
Peak memory 209644 kb
Host smart-c0489319-024f-48e5-b8e1-b6c75aabcd43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674957570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.674957570
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.617998181
Short name T453
Test name
Test status
Simulation time 1777975264 ps
CPU time 12.53 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:04 PM PDT 24
Peak memory 218856 kb
Host smart-fa61382c-c3f7-4d00-9c62-47209eadac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617998181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.617998181
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1742593641
Short name T866
Test name
Test status
Simulation time 2432408904 ps
CPU time 13.78 seconds
Started Aug 12 06:44:54 PM PDT 24
Finished Aug 12 06:45:08 PM PDT 24
Peak memory 218224 kb
Host smart-63835afd-c912-4016-865e-a3e7916441d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742593641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1742593641
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2169011666
Short name T434
Test name
Test status
Simulation time 11860576403 ps
CPU time 42.77 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:45:34 PM PDT 24
Peak memory 219512 kb
Host smart-437cf0f7-9229-4e96-9a36-cca8c3ae8937
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169011666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2169011666
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2354677584
Short name T550
Test name
Test status
Simulation time 312353182 ps
CPU time 9.19 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:01 PM PDT 24
Peak memory 218824 kb
Host smart-9c50f69d-1769-4a7f-a5f6-b67d3dd6fae6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354677584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2354677584
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1159175095
Short name T766
Test name
Test status
Simulation time 133934778 ps
CPU time 2.35 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:44:54 PM PDT 24
Peak memory 218120 kb
Host smart-db435a5f-991c-4a9d-95b3-aca03493ee01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159175095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1159175095
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3381061339
Short name T350
Test name
Test status
Simulation time 2886842759 ps
CPU time 43.75 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:45:35 PM PDT 24
Peak memory 269656 kb
Host smart-1c4728c7-ef9d-4596-9925-2636714e365f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381061339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3381061339
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.948051755
Short name T850
Test name
Test status
Simulation time 2353750760 ps
CPU time 8.44 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:45:01 PM PDT 24
Peak memory 224376 kb
Host smart-239bbd51-5917-4b64-8316-c7cb548f6a76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948051755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.948051755
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2656790665
Short name T162
Test name
Test status
Simulation time 119143516 ps
CPU time 2.16 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:44:54 PM PDT 24
Peak memory 218808 kb
Host smart-bacd6c5b-6523-42b2-a1ab-b3e6cec398ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656790665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2656790665
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.4009222887
Short name T507
Test name
Test status
Simulation time 1603785442 ps
CPU time 14.18 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:45:07 PM PDT 24
Peak memory 226668 kb
Host smart-116bb66e-6dd0-4073-9978-19bc6de9431b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009222887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4009222887
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3325422150
Short name T302
Test name
Test status
Simulation time 1259087187 ps
CPU time 8.57 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:44:59 PM PDT 24
Peak memory 226556 kb
Host smart-25670d9d-037d-4c61-adfe-f38d6e0c323e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325422150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3325422150
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1587641418
Short name T617
Test name
Test status
Simulation time 3272737974 ps
CPU time 15.91 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:08 PM PDT 24
Peak memory 218880 kb
Host smart-48af8af8-b49d-4d5c-9b0f-c2d7a5ba354d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587641418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1587641418
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2958148680
Short name T545
Test name
Test status
Simulation time 304574733 ps
CPU time 6.89 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:44:58 PM PDT 24
Peak memory 225680 kb
Host smart-b4c09f94-2d68-40f4-95b8-e59b5d39a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958148680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2958148680
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2731908618
Short name T401
Test name
Test status
Simulation time 317992204 ps
CPU time 2.96 seconds
Started Aug 12 06:44:47 PM PDT 24
Finished Aug 12 06:44:50 PM PDT 24
Peak memory 218196 kb
Host smart-b6cf5a44-f2da-4d02-9651-e31b876cadfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731908618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2731908618
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3382374306
Short name T385
Test name
Test status
Simulation time 277107962 ps
CPU time 26.98 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:45:05 PM PDT 24
Peak memory 251480 kb
Host smart-4e01ee9d-f881-42a6-b36d-37ae7b7df6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382374306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3382374306
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3034330085
Short name T774
Test name
Test status
Simulation time 181549237 ps
CPU time 7.81 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 251424 kb
Host smart-501f5e56-a62c-4c9e-8072-36d30bd2552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034330085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3034330085
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2507529027
Short name T398
Test name
Test status
Simulation time 3501053004 ps
CPU time 86.61 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:46:18 PM PDT 24
Peak memory 268196 kb
Host smart-dc60f5a6-a5f1-40dc-bda6-986e85c25e40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2507529027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2507529027
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3867524294
Short name T380
Test name
Test status
Simulation time 34469140 ps
CPU time 0.93 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:41 PM PDT 24
Peak memory 212464 kb
Host smart-373844c9-8292-4f1c-8676-2c5ce5ecffd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867524294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3867524294
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3282525069
Short name T308
Test name
Test status
Simulation time 86548551 ps
CPU time 0.89 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:44:53 PM PDT 24
Peak memory 209464 kb
Host smart-d57f7990-6205-4c56-b70d-ee5e14a2b675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282525069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3282525069
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1011606431
Short name T633
Test name
Test status
Simulation time 282103302 ps
CPU time 10.03 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:45:01 PM PDT 24
Peak memory 226668 kb
Host smart-3142f840-3cbf-4842-83be-ffcf2a78d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011606431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1011606431
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2093184552
Short name T31
Test name
Test status
Simulation time 1168557974 ps
CPU time 5.23 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:44:58 PM PDT 24
Peak memory 217860 kb
Host smart-2deef05a-5435-4a69-9597-506a7904dd18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093184552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2093184552
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2686452670
Short name T590
Test name
Test status
Simulation time 5600711887 ps
CPU time 40.2 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:32 PM PDT 24
Peak memory 218816 kb
Host smart-bd1beece-cc99-463b-bf39-dffb1752ce7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686452670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2686452670
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1421694410
Short name T526
Test name
Test status
Simulation time 423354341 ps
CPU time 6.84 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:45:00 PM PDT 24
Peak memory 224708 kb
Host smart-5ffc4647-1929-446e-a73a-3d3e8ec1e985
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421694410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1421694410
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.660074224
Short name T376
Test name
Test status
Simulation time 980462202 ps
CPU time 8.09 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:00 PM PDT 24
Peak memory 218180 kb
Host smart-bbe4382f-ceee-447f-ad4c-32443ecc172b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660074224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
660074224
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2433976491
Short name T428
Test name
Test status
Simulation time 8290368318 ps
CPU time 47.29 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:45:41 PM PDT 24
Peak memory 284228 kb
Host smart-10cc5d24-b004-4f83-950c-89b79680b86e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433976491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2433976491
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3075530832
Short name T853
Test name
Test status
Simulation time 584410440 ps
CPU time 15.59 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:08 PM PDT 24
Peak memory 250992 kb
Host smart-c7830b6a-83bb-4e9e-805d-a5cfbb44ceed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075530832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3075530832
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2597183870
Short name T268
Test name
Test status
Simulation time 178649846 ps
CPU time 4.77 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:44:58 PM PDT 24
Peak memory 218820 kb
Host smart-1a3960f2-b240-4531-9fe2-9d0fb6b2c4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597183870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2597183870
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2982011319
Short name T855
Test name
Test status
Simulation time 270505704 ps
CPU time 12.82 seconds
Started Aug 12 06:44:54 PM PDT 24
Finished Aug 12 06:45:07 PM PDT 24
Peak memory 226684 kb
Host smart-9281b3ba-4290-47e4-a119-d0f9ba90beda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982011319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2982011319
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2652295386
Short name T472
Test name
Test status
Simulation time 488432436 ps
CPU time 11.33 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:45:03 PM PDT 24
Peak memory 226548 kb
Host smart-6528c6f3-587b-4936-ace8-b259fdf72d1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652295386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2652295386
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3710740347
Short name T822
Test name
Test status
Simulation time 872934586 ps
CPU time 10.85 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:45:02 PM PDT 24
Peak memory 218800 kb
Host smart-16bfead0-e87b-4051-b79f-858f30861f39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710740347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3710740347
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3447023573
Short name T760
Test name
Test status
Simulation time 228821743 ps
CPU time 10.23 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:45:03 PM PDT 24
Peak memory 218924 kb
Host smart-c5e4fd9c-21fd-4b81-bcf2-b52debe2b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447023573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3447023573
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1039049537
Short name T636
Test name
Test status
Simulation time 42757181 ps
CPU time 1.72 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:44:53 PM PDT 24
Peak memory 214424 kb
Host smart-22db5d6b-66fe-4d01-a7b9-437c021e71bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039049537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1039049537
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1753526808
Short name T519
Test name
Test status
Simulation time 253329933 ps
CPU time 30.29 seconds
Started Aug 12 06:44:54 PM PDT 24
Finished Aug 12 06:45:25 PM PDT 24
Peak memory 247468 kb
Host smart-b34ab892-a65f-4435-ab52-05418ef3ce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753526808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1753526808
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.798845613
Short name T749
Test name
Test status
Simulation time 145623142 ps
CPU time 7.18 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:45:00 PM PDT 24
Peak memory 251512 kb
Host smart-77dab235-67ad-458c-8abf-4cbdb3215725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798845613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.798845613
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.609717923
Short name T49
Test name
Test status
Simulation time 729504025 ps
CPU time 18.38 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:11 PM PDT 24
Peak memory 226684 kb
Host smart-9c459049-860a-4381-9b17-30a8d8bc7338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609717923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.609717923
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.572534556
Short name T492
Test name
Test status
Simulation time 24458183 ps
CPU time 0.98 seconds
Started Aug 12 06:44:50 PM PDT 24
Finished Aug 12 06:44:51 PM PDT 24
Peak memory 212552 kb
Host smart-de7a4d30-384f-447b-911a-f43bfad2b511
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572534556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.572534556
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3964550529
Short name T743
Test name
Test status
Simulation time 61876101 ps
CPU time 1.09 seconds
Started Aug 12 06:45:03 PM PDT 24
Finished Aug 12 06:45:04 PM PDT 24
Peak memory 209600 kb
Host smart-cdd0a2bd-fa34-4622-b36e-d16ce70fc418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964550529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3964550529
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.31566547
Short name T829
Test name
Test status
Simulation time 980496446 ps
CPU time 8.55 seconds
Started Aug 12 06:44:54 PM PDT 24
Finished Aug 12 06:45:03 PM PDT 24
Peak memory 226628 kb
Host smart-4b0040b8-c9f4-463d-a55c-5f5fc66fa319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31566547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.31566547
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1054495351
Short name T761
Test name
Test status
Simulation time 189275236 ps
CPU time 1.34 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:01 PM PDT 24
Peak memory 217676 kb
Host smart-d7d21fc0-5ad4-4a76-b433-be62dc329355
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054495351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1054495351
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4202288693
Short name T736
Test name
Test status
Simulation time 3737401456 ps
CPU time 56.56 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:48 PM PDT 24
Peak memory 219508 kb
Host smart-565211e3-37ec-47f5-860b-cd165a180082
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202288693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4202288693
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.834536063
Short name T653
Test name
Test status
Simulation time 2138688698 ps
CPU time 27.8 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:45:21 PM PDT 24
Peak memory 218764 kb
Host smart-20fef267-184c-497b-89b0-6ecda47c9efd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834536063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.834536063
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2508704766
Short name T27
Test name
Test status
Simulation time 175922000 ps
CPU time 1.31 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:44:53 PM PDT 24
Peak memory 218144 kb
Host smart-0aa63434-7e42-4cd8-aed8-2ebd497d6327
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508704766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2508704766
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1248961427
Short name T391
Test name
Test status
Simulation time 1268684766 ps
CPU time 56.16 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:45:48 PM PDT 24
Peak memory 267784 kb
Host smart-132fd558-af09-4e18-8a6b-868d124594df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248961427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1248961427
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2976227875
Short name T686
Test name
Test status
Simulation time 6315701543 ps
CPU time 19.15 seconds
Started Aug 12 06:44:51 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 250976 kb
Host smart-e22a3842-084c-4cb4-9e78-d0316d48c644
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976227875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2976227875
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1244085004
Short name T510
Test name
Test status
Simulation time 143416739 ps
CPU time 2.56 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:44:55 PM PDT 24
Peak memory 218852 kb
Host smart-fb5e3f0a-d5b1-4a19-976c-2ecda7c95bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244085004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1244085004
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2951802162
Short name T235
Test name
Test status
Simulation time 5890433471 ps
CPU time 14.02 seconds
Started Aug 12 06:44:59 PM PDT 24
Finished Aug 12 06:45:13 PM PDT 24
Peak memory 226724 kb
Host smart-3755806b-bb15-4336-9c31-fc143cd56e8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951802162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2951802162
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2403366318
Short name T862
Test name
Test status
Simulation time 459005165 ps
CPU time 12.84 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:14 PM PDT 24
Peak memory 226612 kb
Host smart-4e97b436-9cec-4f27-8bef-54bd5a9b0894
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403366318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2403366318
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1312761616
Short name T748
Test name
Test status
Simulation time 218683602 ps
CPU time 6.94 seconds
Started Aug 12 06:44:58 PM PDT 24
Finished Aug 12 06:45:05 PM PDT 24
Peak memory 218812 kb
Host smart-97e8e065-d2e3-46cf-a664-8f073ae3a905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312761616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1312761616
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3800386690
Short name T497
Test name
Test status
Simulation time 919380655 ps
CPU time 13.91 seconds
Started Aug 12 06:44:54 PM PDT 24
Finished Aug 12 06:45:08 PM PDT 24
Peak memory 226628 kb
Host smart-3f0c6243-721f-4a18-b2b2-db4fd281e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800386690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3800386690
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3967224969
Short name T732
Test name
Test status
Simulation time 209458941 ps
CPU time 1.06 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:44:55 PM PDT 24
Peak memory 218188 kb
Host smart-e58e0dd6-96d0-4cca-8b86-a63b4cabe903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967224969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3967224969
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2167079700
Short name T639
Test name
Test status
Simulation time 1346856678 ps
CPU time 28.65 seconds
Started Aug 12 06:44:52 PM PDT 24
Finished Aug 12 06:45:21 PM PDT 24
Peak memory 251496 kb
Host smart-43d02f19-6eb9-4bd6-987f-30b1fa5619b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167079700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2167079700
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1581707202
Short name T197
Test name
Test status
Simulation time 49021958 ps
CPU time 6.65 seconds
Started Aug 12 06:44:54 PM PDT 24
Finished Aug 12 06:45:00 PM PDT 24
Peak memory 251432 kb
Host smart-56f1950a-ec3d-4cfb-bdd6-20c33694870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581707202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1581707202
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1998775165
Short name T536
Test name
Test status
Simulation time 40678807 ps
CPU time 0.89 seconds
Started Aug 12 06:44:53 PM PDT 24
Finished Aug 12 06:44:54 PM PDT 24
Peak memory 212476 kb
Host smart-0feaf24b-41e2-4346-a566-50b6f5948126
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998775165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1998775165
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.374058289
Short name T700
Test name
Test status
Simulation time 129047444 ps
CPU time 1.03 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:02 PM PDT 24
Peak memory 209560 kb
Host smart-ff5c0d4d-5e00-403f-bcee-256b9a9240da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374058289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.374058289
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.321734534
Short name T333
Test name
Test status
Simulation time 957147654 ps
CPU time 10.5 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 218740 kb
Host smart-0754a677-8165-49a2-8090-f7603faa01eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321734534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.321734534
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2027851352
Short name T335
Test name
Test status
Simulation time 765668274 ps
CPU time 8.17 seconds
Started Aug 12 06:45:02 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 217904 kb
Host smart-6fecda1b-df12-46ab-95ca-a45dd574f80e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027851352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2027851352
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.498587021
Short name T351
Test name
Test status
Simulation time 1540384678 ps
CPU time 28.54 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:29 PM PDT 24
Peak memory 218996 kb
Host smart-550db30a-5acb-48cc-a72a-7ef9dad1425e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498587021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.498587021
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2345872796
Short name T661
Test name
Test status
Simulation time 3161926548 ps
CPU time 19.91 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:21 PM PDT 24
Peak memory 218820 kb
Host smart-7987b64d-6c59-4a69-9594-73deca947d09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345872796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2345872796
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3151717315
Short name T504
Test name
Test status
Simulation time 504783217 ps
CPU time 1.81 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:02 PM PDT 24
Peak memory 218144 kb
Host smart-326151b3-af62-46e2-ad18-9fab1ae6fe2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151717315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3151717315
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.4074071739
Short name T342
Test name
Test status
Simulation time 2176725370 ps
CPU time 81.28 seconds
Started Aug 12 06:44:59 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 283872 kb
Host smart-95c46183-c6a1-44b6-8086-01cb12636e84
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074071739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.4074071739
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2979761311
Short name T414
Test name
Test status
Simulation time 304833962 ps
CPU time 10.31 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:12 PM PDT 24
Peak memory 243252 kb
Host smart-16cd14cd-9206-45ea-a688-b6343026ef24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979761311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2979761311
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.205966040
Short name T41
Test name
Test status
Simulation time 137450710 ps
CPU time 2.77 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:04 PM PDT 24
Peak memory 218900 kb
Host smart-7331ecfb-909f-47a9-ad46-49d39b2b94f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205966040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.205966040
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2568657364
Short name T512
Test name
Test status
Simulation time 430819596 ps
CPU time 10.31 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 218944 kb
Host smart-1691fed4-7a1b-4a60-ae18-93c5ac6dd239
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568657364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2568657364
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2143802831
Short name T478
Test name
Test status
Simulation time 584339201 ps
CPU time 19.81 seconds
Started Aug 12 06:45:04 PM PDT 24
Finished Aug 12 06:45:23 PM PDT 24
Peak memory 226604 kb
Host smart-28c731c0-0fd3-4dd3-bfd2-666e889cf565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143802831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2143802831
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2464952033
Short name T284
Test name
Test status
Simulation time 1981133031 ps
CPU time 9.78 seconds
Started Aug 12 06:45:02 PM PDT 24
Finished Aug 12 06:45:12 PM PDT 24
Peak memory 226636 kb
Host smart-4f4b06dc-193a-46da-85e8-7280bcd105ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464952033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2464952033
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2452558440
Short name T635
Test name
Test status
Simulation time 266822046 ps
CPU time 11.94 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:12 PM PDT 24
Peak memory 218912 kb
Host smart-9e3ddac3-5d6b-45d6-bcff-e85c71b21c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452558440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2452558440
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.519721002
Short name T538
Test name
Test status
Simulation time 21531657 ps
CPU time 1.25 seconds
Started Aug 12 06:45:02 PM PDT 24
Finished Aug 12 06:45:03 PM PDT 24
Peak memory 222488 kb
Host smart-b176d1d0-6776-4c66-bd45-9e865e3b7e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519721002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.519721002
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.4021177131
Short name T244
Test name
Test status
Simulation time 407290948 ps
CPU time 25.2 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:26 PM PDT 24
Peak memory 247296 kb
Host smart-9890ba43-8a9a-4997-881d-cd061491cca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021177131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.4021177131
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.584798158
Short name T779
Test name
Test status
Simulation time 769690752 ps
CPU time 7.6 seconds
Started Aug 12 06:45:02 PM PDT 24
Finished Aug 12 06:45:09 PM PDT 24
Peak memory 251508 kb
Host smart-4e1cd8b6-576e-46a4-871d-2858b9981cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584798158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.584798158
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2803826840
Short name T151
Test name
Test status
Simulation time 43089209985 ps
CPU time 225.91 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:48:47 PM PDT 24
Peak memory 284252 kb
Host smart-248db284-d694-4c57-85c6-513664e1c5c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803826840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2803826840
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.733635067
Short name T712
Test name
Test status
Simulation time 17341333 ps
CPU time 1.01 seconds
Started Aug 12 06:45:03 PM PDT 24
Finished Aug 12 06:45:04 PM PDT 24
Peak memory 213504 kb
Host smart-e6fe6513-576f-488c-8d2e-04281f82a9ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733635067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.733635067
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.856068746
Short name T455
Test name
Test status
Simulation time 23846176 ps
CPU time 1.26 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:13 PM PDT 24
Peak memory 209640 kb
Host smart-7068073d-5528-4d7c-a6c6-ead2e5f73ddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856068746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.856068746
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2904317375
Short name T836
Test name
Test status
Simulation time 1266411035 ps
CPU time 13.17 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:13 PM PDT 24
Peak memory 218856 kb
Host smart-9688d155-f8d8-4aa9-8c65-4ab860405c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904317375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2904317375
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2524097148
Short name T7
Test name
Test status
Simulation time 527398126 ps
CPU time 6.93 seconds
Started Aug 12 06:45:02 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 218172 kb
Host smart-84c77c38-0990-4d95-936b-b3235384899d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524097148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2524097148
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1478557093
Short name T371
Test name
Test status
Simulation time 3000871932 ps
CPU time 86.78 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 220756 kb
Host smart-f992316f-1b53-4281-a38d-fab3b6b5f41c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478557093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1478557093
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2289238160
Short name T726
Test name
Test status
Simulation time 798289926 ps
CPU time 10.07 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 223664 kb
Host smart-4a774d46-24ed-46ea-889a-6a31053e8752
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289238160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2289238160
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1787760815
Short name T24
Test name
Test status
Simulation time 511554534 ps
CPU time 7.83 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:09 PM PDT 24
Peak memory 218168 kb
Host smart-77230f64-0219-4b01-9106-28a508513c58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787760815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1787760815
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3315180033
Short name T803
Test name
Test status
Simulation time 2280352848 ps
CPU time 56.78 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:58 PM PDT 24
Peak memory 267900 kb
Host smart-fa04742b-6acd-40c1-8eb7-f205ea105ab0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315180033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3315180033
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.995732046
Short name T59
Test name
Test status
Simulation time 1674812378 ps
CPU time 14.98 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:16 PM PDT 24
Peak memory 243240 kb
Host smart-e50d93b2-c1f4-4835-b554-1badc06ab3a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995732046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.995732046
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2156548747
Short name T734
Test name
Test status
Simulation time 1188874253 ps
CPU time 3.45 seconds
Started Aug 12 06:45:03 PM PDT 24
Finished Aug 12 06:45:07 PM PDT 24
Peak memory 223208 kb
Host smart-89bcbed6-b4db-45d0-a2f3-5dc624a6c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156548747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2156548747
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.759462852
Short name T681
Test name
Test status
Simulation time 860210214 ps
CPU time 16.06 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:17 PM PDT 24
Peak memory 226668 kb
Host smart-9bebb728-b745-4510-8950-8b1139d6081c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759462852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.759462852
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1252567561
Short name T595
Test name
Test status
Simulation time 1343101350 ps
CPU time 15.39 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:26 PM PDT 24
Peak memory 226556 kb
Host smart-5aaa05ea-5a7b-48ad-a061-d55ce39c41fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252567561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1252567561
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2236447024
Short name T838
Test name
Test status
Simulation time 6468075673 ps
CPU time 11.27 seconds
Started Aug 12 06:45:10 PM PDT 24
Finished Aug 12 06:45:22 PM PDT 24
Peak memory 218896 kb
Host smart-58bf3996-dea7-47f9-b60c-5a57dcd818f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236447024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2236447024
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1149585202
Short name T70
Test name
Test status
Simulation time 48175058 ps
CPU time 1.14 seconds
Started Aug 12 06:45:01 PM PDT 24
Finished Aug 12 06:45:03 PM PDT 24
Peak memory 214048 kb
Host smart-dfa3706b-c7a2-4c34-91a1-5b1916397bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149585202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1149585202
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2974069311
Short name T429
Test name
Test status
Simulation time 984296302 ps
CPU time 22.26 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:23 PM PDT 24
Peak memory 251500 kb
Host smart-b0e16f24-5a23-4af3-97ab-414c16e50462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974069311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2974069311
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.655705817
Short name T94
Test name
Test status
Simulation time 330390867 ps
CPU time 8.68 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:09 PM PDT 24
Peak memory 251416 kb
Host smart-70df8358-8e33-46c0-a142-7d1f32515445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655705817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.655705817
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3147854207
Short name T265
Test name
Test status
Simulation time 3073841889 ps
CPU time 74.99 seconds
Started Aug 12 06:45:13 PM PDT 24
Finished Aug 12 06:46:28 PM PDT 24
Peak memory 284344 kb
Host smart-a2a032c5-0077-4e04-b63f-54ceb2ea68d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147854207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3147854207
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2741484267
Short name T134
Test name
Test status
Simulation time 23772465199 ps
CPU time 127.36 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:47:20 PM PDT 24
Peak memory 276276 kb
Host smart-d9e9e136-3301-4def-a36f-8d905ecf390a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2741484267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2741484267
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3646880696
Short name T447
Test name
Test status
Simulation time 74471357 ps
CPU time 0.85 seconds
Started Aug 12 06:45:00 PM PDT 24
Finished Aug 12 06:45:01 PM PDT 24
Peak memory 212548 kb
Host smart-dded328d-f0ae-4cc2-b9cf-ab3959bba534
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646880696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3646880696
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3401703253
Short name T138
Test name
Test status
Simulation time 57104777 ps
CPU time 0.97 seconds
Started Aug 12 06:45:13 PM PDT 24
Finished Aug 12 06:45:14 PM PDT 24
Peak memory 209484 kb
Host smart-57e94b01-11ad-4a90-b7ba-60fa1616a9dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401703253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3401703253
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3736733008
Short name T283
Test name
Test status
Simulation time 3351045895 ps
CPU time 14.48 seconds
Started Aug 12 06:45:15 PM PDT 24
Finished Aug 12 06:45:30 PM PDT 24
Peak memory 219476 kb
Host smart-526b8e49-ef1d-4d83-8b6b-a2221332d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736733008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3736733008
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.30312529
Short name T467
Test name
Test status
Simulation time 204581864 ps
CPU time 3.01 seconds
Started Aug 12 06:45:24 PM PDT 24
Finished Aug 12 06:45:27 PM PDT 24
Peak memory 217680 kb
Host smart-813150a5-2cab-4c49-9fa7-cfe34928dc92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30312529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.30312529
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.255058784
Short name T249
Test name
Test status
Simulation time 432514142 ps
CPU time 7.93 seconds
Started Aug 12 06:45:20 PM PDT 24
Finished Aug 12 06:45:28 PM PDT 24
Peak memory 218828 kb
Host smart-da847957-dc39-4b58-8282-0f57b910a3cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255058784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.255058784
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3186487699
Short name T847
Test name
Test status
Simulation time 169997015 ps
CPU time 1.9 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:13 PM PDT 24
Peak memory 218180 kb
Host smart-31fe0a13-77d8-4b17-b5a4-607b544f684f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186487699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3186487699
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3070758781
Short name T285
Test name
Test status
Simulation time 8257862021 ps
CPU time 76.7 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 267896 kb
Host smart-66bc48ee-573f-4dc0-9da8-b3d8a476616b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070758781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3070758781
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1443554208
Short name T844
Test name
Test status
Simulation time 99594159 ps
CPU time 3.4 seconds
Started Aug 12 06:45:08 PM PDT 24
Finished Aug 12 06:45:12 PM PDT 24
Peak memory 218824 kb
Host smart-39bb8eb8-8c00-426b-8894-5141dc49f409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443554208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1443554208
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2460696492
Short name T818
Test name
Test status
Simulation time 467091329 ps
CPU time 7.97 seconds
Started Aug 12 06:45:13 PM PDT 24
Finished Aug 12 06:45:21 PM PDT 24
Peak memory 226584 kb
Host smart-9597d166-bdab-4251-87a9-5a33e38ee46d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460696492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2460696492
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2418508076
Short name T670
Test name
Test status
Simulation time 1290654595 ps
CPU time 17.14 seconds
Started Aug 12 06:45:16 PM PDT 24
Finished Aug 12 06:45:33 PM PDT 24
Peak memory 226620 kb
Host smart-77785165-1940-44ea-ad37-994352c8dd08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418508076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2418508076
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3336090465
Short name T275
Test name
Test status
Simulation time 323849439 ps
CPU time 9.32 seconds
Started Aug 12 06:45:25 PM PDT 24
Finished Aug 12 06:45:34 PM PDT 24
Peak memory 226600 kb
Host smart-11afe376-7723-4172-971c-165a5acd42c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336090465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3336090465
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3580212847
Short name T192
Test name
Test status
Simulation time 2133587259 ps
CPU time 10.27 seconds
Started Aug 12 06:45:10 PM PDT 24
Finished Aug 12 06:45:21 PM PDT 24
Peak memory 218936 kb
Host smart-390bafac-37d0-45f3-ae37-f604d6c01470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580212847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3580212847
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3892058917
Short name T69
Test name
Test status
Simulation time 231042708 ps
CPU time 1.54 seconds
Started Aug 12 06:45:25 PM PDT 24
Finished Aug 12 06:45:26 PM PDT 24
Peak memory 223696 kb
Host smart-9672eccd-3a06-4795-8dbd-f4833b613f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892058917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3892058917
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3200445637
Short name T616
Test name
Test status
Simulation time 565110712 ps
CPU time 21.07 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:33 PM PDT 24
Peak memory 251508 kb
Host smart-e32139ba-3518-4f10-bc71-0573b104e52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200445637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3200445637
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1065410452
Short name T605
Test name
Test status
Simulation time 173663793 ps
CPU time 3.21 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:15 PM PDT 24
Peak memory 223176 kb
Host smart-7364c2bd-8318-4a58-961b-29c56397ea8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065410452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1065410452
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.623724023
Short name T701
Test name
Test status
Simulation time 20746950844 ps
CPU time 419.43 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:52:12 PM PDT 24
Peak memory 251448 kb
Host smart-aee3608f-5c47-422c-a6e2-620ae9438ef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623724023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.623724023
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1547531027
Short name T190
Test name
Test status
Simulation time 12128906 ps
CPU time 0.9 seconds
Started Aug 12 06:45:16 PM PDT 24
Finished Aug 12 06:45:17 PM PDT 24
Peak memory 212512 kb
Host smart-04eac040-abcc-463c-a032-5876df0ccfe8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547531027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1547531027
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3197495812
Short name T257
Test name
Test status
Simulation time 114448192 ps
CPU time 0.9 seconds
Started Aug 12 06:45:13 PM PDT 24
Finished Aug 12 06:45:14 PM PDT 24
Peak memory 209472 kb
Host smart-485218bd-9132-49f8-8afd-733eccbd6e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197495812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3197495812
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3337172099
Short name T827
Test name
Test status
Simulation time 420066925 ps
CPU time 13.68 seconds
Started Aug 12 06:45:14 PM PDT 24
Finished Aug 12 06:45:27 PM PDT 24
Peak memory 218760 kb
Host smart-3b6e53e9-0a56-4583-90c8-6bab2d556b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337172099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3337172099
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.267955416
Short name T725
Test name
Test status
Simulation time 4732128412 ps
CPU time 52.26 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:46:03 PM PDT 24
Peak memory 218888 kb
Host smart-0d1b28db-30ab-411d-9a38-8e36c4e9bb45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267955416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.267955416
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1254135089
Short name T267
Test name
Test status
Simulation time 1118615221 ps
CPU time 4.98 seconds
Started Aug 12 06:45:13 PM PDT 24
Finished Aug 12 06:45:18 PM PDT 24
Peak memory 218836 kb
Host smart-bf0db41c-4212-4043-850a-b9a43bbf8d26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254135089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1254135089
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3914224353
Short name T338
Test name
Test status
Simulation time 348571481 ps
CPU time 3.7 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:15 PM PDT 24
Peak memory 218164 kb
Host smart-91df3893-baf1-4874-90e6-7dfcbf327dc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914224353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3914224353
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.251084644
Short name T439
Test name
Test status
Simulation time 958396770 ps
CPU time 36.09 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:47 PM PDT 24
Peak memory 251384 kb
Host smart-b616f0ea-7482-4205-b681-6d7aa23a7ede
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251084644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.251084644
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3140098735
Short name T655
Test name
Test status
Simulation time 3801281614 ps
CPU time 14.49 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:26 PM PDT 24
Peak memory 251196 kb
Host smart-0891745a-e38f-4ea8-9b6a-e44c81edeb42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140098735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3140098735
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2721910962
Short name T501
Test name
Test status
Simulation time 66959540 ps
CPU time 2.68 seconds
Started Aug 12 06:45:10 PM PDT 24
Finished Aug 12 06:45:13 PM PDT 24
Peak memory 218848 kb
Host smart-687ed204-0f6f-418c-8d67-7b624fe1c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721910962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2721910962
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2224523512
Short name T543
Test name
Test status
Simulation time 641844885 ps
CPU time 15.25 seconds
Started Aug 12 06:45:15 PM PDT 24
Finished Aug 12 06:45:31 PM PDT 24
Peak memory 226568 kb
Host smart-1007e040-2a5a-4b0d-8d22-f98a7c3ec074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224523512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2224523512
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.779001961
Short name T277
Test name
Test status
Simulation time 1262727241 ps
CPU time 9.13 seconds
Started Aug 12 06:45:10 PM PDT 24
Finished Aug 12 06:45:20 PM PDT 24
Peak memory 226580 kb
Host smart-8168d26e-941f-4e16-bd24-c1f2aeee02b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779001961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.779001961
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3349215523
Short name T665
Test name
Test status
Simulation time 3251631155 ps
CPU time 9.78 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:21 PM PDT 24
Peak memory 219476 kb
Host smart-40f94a53-09ab-437e-9b2e-65d0d97fce47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349215523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3349215523
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2075949808
Short name T814
Test name
Test status
Simulation time 261664253 ps
CPU time 9.55 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:22 PM PDT 24
Peak memory 225476 kb
Host smart-c47cdfd7-f487-4213-9cce-c2e6c566e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075949808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2075949808
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2610663000
Short name T596
Test name
Test status
Simulation time 189089602 ps
CPU time 1.35 seconds
Started Aug 12 06:45:10 PM PDT 24
Finished Aug 12 06:45:12 PM PDT 24
Peak memory 214308 kb
Host smart-3ea3d753-8c46-413d-8083-b3514a429b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610663000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2610663000
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.851350018
Short name T323
Test name
Test status
Simulation time 1959977141 ps
CPU time 23.7 seconds
Started Aug 12 06:45:16 PM PDT 24
Finished Aug 12 06:45:39 PM PDT 24
Peak memory 251584 kb
Host smart-6f7cb565-6880-43d2-bac6-475e5a109705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851350018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.851350018
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.989567143
Short name T524
Test name
Test status
Simulation time 74606740 ps
CPU time 6.72 seconds
Started Aug 12 06:45:24 PM PDT 24
Finished Aug 12 06:45:31 PM PDT 24
Peak memory 251456 kb
Host smart-f5c5f6ea-b94f-4e3a-9d1c-932472639855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989567143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.989567143
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2865667916
Short name T740
Test name
Test status
Simulation time 50327879424 ps
CPU time 469.67 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:53:02 PM PDT 24
Peak memory 274668 kb
Host smart-c3c0597c-167f-4e72-aa94-5c4b172a1e8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865667916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2865667916
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.148183058
Short name T355
Test name
Test status
Simulation time 17560292 ps
CPU time 1.15 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:13 PM PDT 24
Peak memory 218328 kb
Host smart-028c1a6a-b121-46c4-a74a-37646e708cfe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148183058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.148183058
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1658546176
Short name T218
Test name
Test status
Simulation time 34249066 ps
CPU time 0.86 seconds
Started Aug 12 06:45:25 PM PDT 24
Finished Aug 12 06:45:26 PM PDT 24
Peak memory 209484 kb
Host smart-6d42e05e-69d6-43d0-8fb9-6645df106437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658546176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1658546176
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3876780713
Short name T502
Test name
Test status
Simulation time 2339712480 ps
CPU time 15.13 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:27 PM PDT 24
Peak memory 226680 kb
Host smart-84458e72-9ecd-4a43-8b70-40e0565e2148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876780713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3876780713
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2889165203
Short name T164
Test name
Test status
Simulation time 99594550 ps
CPU time 3.48 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:45:33 PM PDT 24
Peak memory 217604 kb
Host smart-36fb3bae-7cf5-42e5-a306-f0674f4443be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889165203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2889165203
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1719164751
Short name T610
Test name
Test status
Simulation time 1256562493 ps
CPU time 21.56 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:34 PM PDT 24
Peak memory 218892 kb
Host smart-243c6d1f-c224-4db3-810a-d1a1b76bc383
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719164751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1719164751
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1030688464
Short name T220
Test name
Test status
Simulation time 404142647 ps
CPU time 5.87 seconds
Started Aug 12 06:45:10 PM PDT 24
Finished Aug 12 06:45:16 PM PDT 24
Peak memory 218828 kb
Host smart-42b25c5e-1753-48ab-b6c5-37e3deb28377
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030688464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1030688464
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.704376264
Short name T671
Test name
Test status
Simulation time 282400134 ps
CPU time 5.3 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:18 PM PDT 24
Peak memory 218176 kb
Host smart-70a9a9d4-e4fa-419f-954b-540664c10aab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704376264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
704376264
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.369650532
Short name T359
Test name
Test status
Simulation time 9750478746 ps
CPU time 52.94 seconds
Started Aug 12 06:45:13 PM PDT 24
Finished Aug 12 06:46:06 PM PDT 24
Peak memory 278540 kb
Host smart-c343baa4-8173-4a4b-b8dd-9057659261e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369650532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.369650532
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.540669498
Short name T809
Test name
Test status
Simulation time 708305479 ps
CPU time 15.11 seconds
Started Aug 12 06:45:11 PM PDT 24
Finished Aug 12 06:45:26 PM PDT 24
Peak memory 251360 kb
Host smart-3f364ac7-6a3d-4832-a22a-0b58e81dae7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540669498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.540669498
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.610146558
Short name T722
Test name
Test status
Simulation time 279576584 ps
CPU time 3.55 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:16 PM PDT 24
Peak memory 218860 kb
Host smart-fa0275f8-a457-4223-aa40-97f5e435a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610146558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.610146558
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.345982906
Short name T764
Test name
Test status
Simulation time 399853400 ps
CPU time 16.79 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:45:44 PM PDT 24
Peak memory 219516 kb
Host smart-ffee4b15-d0ad-4108-853c-541ff4d019fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345982906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.345982906
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3869328388
Short name T804
Test name
Test status
Simulation time 1104074217 ps
CPU time 13.5 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:45:43 PM PDT 24
Peak memory 226588 kb
Host smart-943bc8e6-feee-4922-be79-6e6b9891fb51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869328388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3869328388
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.4002621710
Short name T382
Test name
Test status
Simulation time 291183989 ps
CPU time 7.12 seconds
Started Aug 12 06:45:16 PM PDT 24
Finished Aug 12 06:45:23 PM PDT 24
Peak memory 225132 kb
Host smart-9adf3052-01b6-4411-8356-9053ccbe085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002621710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.4002621710
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2700378187
Short name T287
Test name
Test status
Simulation time 76789932 ps
CPU time 1.79 seconds
Started Aug 12 06:45:12 PM PDT 24
Finished Aug 12 06:45:14 PM PDT 24
Peak memory 214296 kb
Host smart-e6e94bcf-95f6-4fbc-aba1-5eb44ac7ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700378187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2700378187
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3165068750
Short name T475
Test name
Test status
Simulation time 969298824 ps
CPU time 23.56 seconds
Started Aug 12 06:45:25 PM PDT 24
Finished Aug 12 06:45:49 PM PDT 24
Peak memory 251492 kb
Host smart-65058d48-94d2-43fa-8a8a-e3feab7fc47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165068750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3165068750
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3175177108
Short name T755
Test name
Test status
Simulation time 105266780 ps
CPU time 7.43 seconds
Started Aug 12 06:45:19 PM PDT 24
Finished Aug 12 06:45:27 PM PDT 24
Peak memory 251060 kb
Host smart-6b7e2de3-5fbe-43ff-95f0-e328914381d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175177108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3175177108
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3831656264
Short name T452
Test name
Test status
Simulation time 9064109180 ps
CPU time 96.25 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:47:03 PM PDT 24
Peak memory 251888 kb
Host smart-4ac150a5-df89-4dc2-9ada-d29080c73f5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831656264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3831656264
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.4289420351
Short name T135
Test name
Test status
Simulation time 3195376604 ps
CPU time 29.15 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 226848 kb
Host smart-857db29b-8904-4978-85de-bd2c43ca37f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4289420351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.4289420351
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1903573851
Short name T651
Test name
Test status
Simulation time 51335876 ps
CPU time 0.9 seconds
Started Aug 12 06:45:16 PM PDT 24
Finished Aug 12 06:45:17 PM PDT 24
Peak memory 212448 kb
Host smart-9e57a113-83d1-4fe5-9346-f2e45efd19c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903573851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1903573851
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2910688048
Short name T770
Test name
Test status
Simulation time 31393357 ps
CPU time 0.83 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:45:28 PM PDT 24
Peak memory 209404 kb
Host smart-89df6150-5c6c-4499-9bf8-00880d01f0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910688048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2910688048
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.949362153
Short name T411
Test name
Test status
Simulation time 868072395 ps
CPU time 11.62 seconds
Started Aug 12 06:45:31 PM PDT 24
Finished Aug 12 06:45:43 PM PDT 24
Peak memory 218880 kb
Host smart-3311f3ab-05af-4dbb-85ae-ab562082ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949362153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.949362153
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2411841195
Short name T517
Test name
Test status
Simulation time 483266839 ps
CPU time 1.82 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:28 PM PDT 24
Peak memory 217536 kb
Host smart-b5f90138-d773-4417-b24e-7e89641672b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411841195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2411841195
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2468200602
Short name T688
Test name
Test status
Simulation time 1173123170 ps
CPU time 23.69 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 218876 kb
Host smart-fb04bd45-3f97-40f7-81ce-107a8008d6f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468200602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2468200602
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3525822076
Short name T830
Test name
Test status
Simulation time 951019176 ps
CPU time 8.44 seconds
Started Aug 12 06:45:25 PM PDT 24
Finished Aug 12 06:45:34 PM PDT 24
Peak memory 218776 kb
Host smart-9ca55775-7dae-4a76-b66d-669822b03024
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525822076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3525822076
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1353065410
Short name T336
Test name
Test status
Simulation time 1697378156 ps
CPU time 5.37 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:34 PM PDT 24
Peak memory 218160 kb
Host smart-09e3456a-5556-4425-b4a9-e68878000ec3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353065410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1353065410
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1626491489
Short name T707
Test name
Test status
Simulation time 1626453305 ps
CPU time 67.16 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 276104 kb
Host smart-697f0dad-09c0-4686-8f3a-c8872d26f25e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626491489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1626491489
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.372191493
Short name T413
Test name
Test status
Simulation time 1182967122 ps
CPU time 35.38 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:46:02 PM PDT 24
Peak memory 251348 kb
Host smart-3af36668-753f-494a-bd7c-371b31db4fd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372191493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.372191493
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3174639658
Short name T544
Test name
Test status
Simulation time 206797537 ps
CPU time 2.1 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:29 PM PDT 24
Peak memory 218888 kb
Host smart-41637b99-929f-408c-be6b-03346c2c786e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174639658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3174639658
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3473082999
Short name T705
Test name
Test status
Simulation time 383230822 ps
CPU time 11.84 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:38 PM PDT 24
Peak memory 226684 kb
Host smart-5b2fee05-f956-413d-82e3-eeb8aca430c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473082999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3473082999
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2105870274
Short name T21
Test name
Test status
Simulation time 743918969 ps
CPU time 15.03 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:45:42 PM PDT 24
Peak memory 226580 kb
Host smart-c6e2a8ea-4596-4ae5-8337-788f588eac63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105870274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2105870274
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3043557241
Short name T573
Test name
Test status
Simulation time 5562704035 ps
CPU time 13.1 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:45:42 PM PDT 24
Peak memory 218808 kb
Host smart-e96c67b6-5799-41a9-9aca-e202665c4607
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043557241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3043557241
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.4213421831
Short name T583
Test name
Test status
Simulation time 3544850178 ps
CPU time 11.59 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:45:39 PM PDT 24
Peak memory 218964 kb
Host smart-d735f4d3-4bbe-4b00-8294-e431f75bcc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213421831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.4213421831
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4091283386
Short name T38
Test name
Test status
Simulation time 30203971 ps
CPU time 2.26 seconds
Started Aug 12 06:45:33 PM PDT 24
Finished Aug 12 06:45:35 PM PDT 24
Peak memory 215004 kb
Host smart-b99bce8f-5472-4f49-ad5a-301969fd6aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091283386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4091283386
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3543145422
Short name T746
Test name
Test status
Simulation time 935384552 ps
CPU time 26.82 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:53 PM PDT 24
Peak memory 245960 kb
Host smart-b6f31a28-1459-490b-a664-e51fd30031b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543145422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3543145422
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3244104951
Short name T437
Test name
Test status
Simulation time 46834073 ps
CPU time 6.82 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:35 PM PDT 24
Peak memory 250988 kb
Host smart-fba680f1-f2c8-4294-8108-09b30c211cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244104951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3244104951
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3440804307
Short name T711
Test name
Test status
Simulation time 8880302402 ps
CPU time 331.17 seconds
Started Aug 12 06:45:25 PM PDT 24
Finished Aug 12 06:50:56 PM PDT 24
Peak memory 284324 kb
Host smart-c472b772-9d93-466c-bfa2-572d0cadd487
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440804307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3440804307
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1310247025
Short name T781
Test name
Test status
Simulation time 89314209 ps
CPU time 1 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:29 PM PDT 24
Peak memory 218288 kb
Host smart-a6170c4a-f1c9-46ca-8c42-36b65c7c5e13
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310247025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1310247025
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.44719483
Short name T237
Test name
Test status
Simulation time 61141966 ps
CPU time 1.03 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:29 PM PDT 24
Peak memory 209516 kb
Host smart-30e45320-19f7-414f-800d-aa2f127622ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44719483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.44719483
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.580087929
Short name T374
Test name
Test status
Simulation time 315732732 ps
CPU time 12.72 seconds
Started Aug 12 06:45:30 PM PDT 24
Finished Aug 12 06:45:42 PM PDT 24
Peak memory 218880 kb
Host smart-d3537822-615b-4c03-9a6c-18eec01219bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580087929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.580087929
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1239097714
Short name T399
Test name
Test status
Simulation time 295166045 ps
CPU time 7.72 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:34 PM PDT 24
Peak memory 217860 kb
Host smart-50b72c53-6159-4d89-8c53-f6d56eb53771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239097714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1239097714
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.198700546
Short name T415
Test name
Test status
Simulation time 3333713650 ps
CPU time 47.15 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 219636 kb
Host smart-0c051c95-6212-4340-b8ab-60d7c05354b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198700546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.198700546
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3187578222
Short name T808
Test name
Test status
Simulation time 134958813 ps
CPU time 5.02 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:33 PM PDT 24
Peak memory 218804 kb
Host smart-674d10ff-98ef-4ccf-8282-b163255a520f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187578222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3187578222
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1409751207
Short name T840
Test name
Test status
Simulation time 865693918 ps
CPU time 6.52 seconds
Started Aug 12 06:45:30 PM PDT 24
Finished Aug 12 06:45:37 PM PDT 24
Peak memory 218160 kb
Host smart-1af7ff23-ab2d-4b5f-9a33-afb2ad4e3d91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409751207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1409751207
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1704078248
Short name T560
Test name
Test status
Simulation time 1865524110 ps
CPU time 13.56 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:45:42 PM PDT 24
Peak memory 251372 kb
Host smart-ec8be6e5-42ab-4a77-a988-d7306b299f75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704078248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1704078248
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2005593981
Short name T436
Test name
Test status
Simulation time 61703633 ps
CPU time 3.07 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:45:32 PM PDT 24
Peak memory 222852 kb
Host smart-9f9d7540-c4a3-42a1-8672-b2b6fadd1979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005593981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2005593981
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.791390408
Short name T471
Test name
Test status
Simulation time 848973014 ps
CPU time 19.15 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:45:47 PM PDT 24
Peak memory 218860 kb
Host smart-debf6472-4419-422a-af84-852f94a39a96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791390408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.791390408
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2062450780
Short name T198
Test name
Test status
Simulation time 5491076900 ps
CPU time 10.52 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:37 PM PDT 24
Peak memory 226684 kb
Host smart-daf3b871-73b0-4a01-bada-b4d904afaee0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062450780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2062450780
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2480732642
Short name T202
Test name
Test status
Simulation time 296981597 ps
CPU time 11.31 seconds
Started Aug 12 06:45:27 PM PDT 24
Finished Aug 12 06:45:38 PM PDT 24
Peak memory 218784 kb
Host smart-c71781f1-3920-486f-9856-5dab954d1b9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480732642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2480732642
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2178129294
Short name T149
Test name
Test status
Simulation time 1789109779 ps
CPU time 11.86 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:40 PM PDT 24
Peak memory 226640 kb
Host smart-795bf430-450d-4742-a616-5fe73a98cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178129294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2178129294
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.626339780
Short name T859
Test name
Test status
Simulation time 58153096 ps
CPU time 3.11 seconds
Started Aug 12 06:45:28 PM PDT 24
Finished Aug 12 06:45:32 PM PDT 24
Peak memory 215236 kb
Host smart-b9abddc2-6189-43f3-8afa-0394e89f8ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626339780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.626339780
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3850277847
Short name T527
Test name
Test status
Simulation time 897530324 ps
CPU time 22.15 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:48 PM PDT 24
Peak memory 246312 kb
Host smart-e3c23dd8-67a1-4ed3-ada3-03ee46893254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850277847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3850277847
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2876296675
Short name T461
Test name
Test status
Simulation time 243758002 ps
CPU time 7.92 seconds
Started Aug 12 06:45:30 PM PDT 24
Finished Aug 12 06:45:38 PM PDT 24
Peak memory 251396 kb
Host smart-e4244531-826a-4136-a367-3949599cff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876296675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2876296675
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3757144709
Short name T25
Test name
Test status
Simulation time 22516107920 ps
CPU time 113.27 seconds
Started Aug 12 06:45:32 PM PDT 24
Finished Aug 12 06:47:25 PM PDT 24
Peak memory 276928 kb
Host smart-c56d4a3d-9fc0-4490-a277-c320781decd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757144709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3757144709
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2160042618
Short name T793
Test name
Test status
Simulation time 42604917 ps
CPU time 0.71 seconds
Started Aug 12 06:45:26 PM PDT 24
Finished Aug 12 06:45:27 PM PDT 24
Peak memory 207624 kb
Host smart-42b28121-5dcf-44c2-93fe-79d1c55ae730
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160042618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2160042618
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.914901254
Short name T307
Test name
Test status
Simulation time 66173404 ps
CPU time 1.13 seconds
Started Aug 12 06:44:01 PM PDT 24
Finished Aug 12 06:44:02 PM PDT 24
Peak memory 209568 kb
Host smart-f3fc1264-8495-4490-a4c5-a602331d0ddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914901254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.914901254
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2008970122
Short name T186
Test name
Test status
Simulation time 39063169 ps
CPU time 0.85 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:44:03 PM PDT 24
Peak memory 209112 kb
Host smart-4e83b763-0baf-487e-9ae6-ff24ec6003e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008970122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2008970122
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.588033916
Short name T346
Test name
Test status
Simulation time 303352963 ps
CPU time 15.21 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:07 PM PDT 24
Peak memory 218884 kb
Host smart-3d97e7e2-e6e2-4161-850e-388eb94ef74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588033916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.588033916
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1270117220
Short name T33
Test name
Test status
Simulation time 2717904521 ps
CPU time 17.45 seconds
Started Aug 12 06:44:01 PM PDT 24
Finished Aug 12 06:44:19 PM PDT 24
Peak memory 218052 kb
Host smart-657d411e-1e45-42ce-8335-7699db178583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270117220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1270117220
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3093113595
Short name T44
Test name
Test status
Simulation time 2192923446 ps
CPU time 34.28 seconds
Started Aug 12 06:44:03 PM PDT 24
Finished Aug 12 06:44:38 PM PDT 24
Peak memory 218888 kb
Host smart-c838be6e-ac25-4e5f-b91d-47b3964887a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093113595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3093113595
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2829198374
Short name T697
Test name
Test status
Simulation time 2672428711 ps
CPU time 16.82 seconds
Started Aug 12 06:44:01 PM PDT 24
Finished Aug 12 06:44:18 PM PDT 24
Peak memory 218440 kb
Host smart-7aa7e9e5-220d-4491-970d-7a1fd39855bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829198374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
829198374
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.330319019
Short name T301
Test name
Test status
Simulation time 2807195550 ps
CPU time 6.32 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:44:09 PM PDT 24
Peak memory 224048 kb
Host smart-6365ce50-1b63-4c6f-a987-2065569b2a38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330319019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.330319019
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4034002596
Short name T476
Test name
Test status
Simulation time 8815258565 ps
CPU time 34.44 seconds
Started Aug 12 06:44:05 PM PDT 24
Finished Aug 12 06:44:39 PM PDT 24
Peak memory 218264 kb
Host smart-e074064e-ec0d-4965-814c-a199dd6c501c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034002596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4034002596
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4232056164
Short name T67
Test name
Test status
Simulation time 343285449 ps
CPU time 5.02 seconds
Started Aug 12 06:44:05 PM PDT 24
Finished Aug 12 06:44:10 PM PDT 24
Peak memory 218128 kb
Host smart-18399b63-d7a1-4c7d-9527-ecd4a38afba0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232056164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
4232056164
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.66172651
Short name T305
Test name
Test status
Simulation time 2927230193 ps
CPU time 49.77 seconds
Started Aug 12 06:44:05 PM PDT 24
Finished Aug 12 06:44:55 PM PDT 24
Peak memory 279180 kb
Host smart-4fd7555e-c572-436c-b4ed-fda53fd24c2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66172651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
state_failure.66172651
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.222645386
Short name T348
Test name
Test status
Simulation time 569259901 ps
CPU time 15.4 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:44:17 PM PDT 24
Peak memory 251440 kb
Host smart-ee2b524f-4204-4cf5-bf63-e07cb2b9f637
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222645386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.222645386
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1656124268
Short name T330
Test name
Test status
Simulation time 78744277 ps
CPU time 2.05 seconds
Started Aug 12 06:43:53 PM PDT 24
Finished Aug 12 06:43:55 PM PDT 24
Peak memory 222704 kb
Host smart-0c4daf26-ab68-47c0-9310-6bad5dc8b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656124268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1656124268
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3187388566
Short name T548
Test name
Test status
Simulation time 267961163 ps
CPU time 15.52 seconds
Started Aug 12 06:44:03 PM PDT 24
Finished Aug 12 06:44:18 PM PDT 24
Peak memory 218244 kb
Host smart-3a943f99-75a6-4d9a-ae31-ac664d2e6899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187388566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3187388566
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3472696190
Short name T787
Test name
Test status
Simulation time 1539115405 ps
CPU time 17.23 seconds
Started Aug 12 06:44:03 PM PDT 24
Finished Aug 12 06:44:20 PM PDT 24
Peak memory 226620 kb
Host smart-c2ede6d8-b4fc-49b3-b0f6-882eed410bd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472696190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3472696190
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3034146790
Short name T271
Test name
Test status
Simulation time 1268122090 ps
CPU time 10.37 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:44:13 PM PDT 24
Peak memory 226748 kb
Host smart-2fd52dcd-a4f7-494e-9aae-2173bc71def0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034146790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3034146790
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3709559042
Short name T569
Test name
Test status
Simulation time 301818467 ps
CPU time 9.15 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:44:11 PM PDT 24
Peak memory 218800 kb
Host smart-94980c2e-e2c1-4509-a2bc-9cfb99e0cdf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709559042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
709559042
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2135519736
Short name T741
Test name
Test status
Simulation time 1729876546 ps
CPU time 11.66 seconds
Started Aug 12 06:44:03 PM PDT 24
Finished Aug 12 06:44:15 PM PDT 24
Peak memory 226620 kb
Host smart-98da1b2d-12f9-415c-a73b-4730d51217bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135519736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2135519736
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4059093149
Short name T81
Test name
Test status
Simulation time 199948203 ps
CPU time 5.5 seconds
Started Aug 12 06:43:53 PM PDT 24
Finished Aug 12 06:43:58 PM PDT 24
Peak memory 218228 kb
Host smart-fb931e8e-d8d1-4b33-a94e-a97f5f829298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059093149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4059093149
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1059592370
Short name T696
Test name
Test status
Simulation time 522226330 ps
CPU time 25.6 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:44:18 PM PDT 24
Peak memory 251552 kb
Host smart-f7d51f3d-c19a-4851-a2a8-824b5ddc1041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059592370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1059592370
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.629573075
Short name T352
Test name
Test status
Simulation time 77309009 ps
CPU time 8.18 seconds
Started Aug 12 06:43:53 PM PDT 24
Finished Aug 12 06:44:01 PM PDT 24
Peak memory 251532 kb
Host smart-d0598583-8b51-47e6-9355-4c37542e4900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629573075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.629573075
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.199717770
Short name T682
Test name
Test status
Simulation time 17374054755 ps
CPU time 573.2 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:53:36 PM PDT 24
Peak memory 422440 kb
Host smart-73671ff5-425d-4129-b31f-117721136495
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199717770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.199717770
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1032327224
Short name T460
Test name
Test status
Simulation time 2929979692 ps
CPU time 90.41 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:45:32 PM PDT 24
Peak memory 251708 kb
Host smart-2345c394-76b4-4054-8593-fbc5f2ec6e1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1032327224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.1032327224
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.662264734
Short name T559
Test name
Test status
Simulation time 22193089 ps
CPU time 0.84 seconds
Started Aug 12 06:43:52 PM PDT 24
Finished Aug 12 06:43:53 PM PDT 24
Peak memory 212420 kb
Host smart-a69d49ba-4818-431d-a520-7b8ce6b5d459
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662264734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.662264734
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2884418497
Short name T549
Test name
Test status
Simulation time 67839300 ps
CPU time 0.98 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:44 PM PDT 24
Peak memory 209480 kb
Host smart-044d0380-6a9b-4e70-b933-e4b4c117b18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884418497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2884418497
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3656180186
Short name T864
Test name
Test status
Simulation time 1526392952 ps
CPU time 7.27 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:50 PM PDT 24
Peak memory 226620 kb
Host smart-96afddca-559d-443d-b8e1-e29dc217d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656180186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3656180186
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4253466324
Short name T8
Test name
Test status
Simulation time 1423802625 ps
CPU time 27.33 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:46:08 PM PDT 24
Peak memory 217968 kb
Host smart-eb28fab4-9dcc-477a-96d4-a5be6053161b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253466324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4253466324
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1617342598
Short name T811
Test name
Test status
Simulation time 262596453 ps
CPU time 1.53 seconds
Started Aug 12 06:45:42 PM PDT 24
Finished Aug 12 06:45:44 PM PDT 24
Peak memory 218852 kb
Host smart-73d4816e-c268-4962-97f5-b4c6a27a98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617342598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1617342598
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1497053122
Short name T266
Test name
Test status
Simulation time 313856719 ps
CPU time 13.98 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:54 PM PDT 24
Peak memory 220560 kb
Host smart-7f9067ae-9b68-40ce-90be-5c4b62872fb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497053122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1497053122
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2007721830
Short name T40
Test name
Test status
Simulation time 590303649 ps
CPU time 11.19 seconds
Started Aug 12 06:45:44 PM PDT 24
Finished Aug 12 06:45:55 PM PDT 24
Peak memory 226656 kb
Host smart-aaf6c313-fb36-45e0-abec-bd6d4deec70e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007721830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2007721830
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3022125223
Short name T637
Test name
Test status
Simulation time 1629918595 ps
CPU time 12.3 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:55 PM PDT 24
Peak memory 218776 kb
Host smart-bdb3ccdc-1caf-41a3-8889-2469f587a4c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022125223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3022125223
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3150501125
Short name T706
Test name
Test status
Simulation time 61881771 ps
CPU time 2.53 seconds
Started Aug 12 06:45:29 PM PDT 24
Finished Aug 12 06:45:31 PM PDT 24
Peak memory 215132 kb
Host smart-ab0bb3f2-4f0d-42aa-8044-886dfcecbc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150501125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3150501125
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2649169110
Short name T565
Test name
Test status
Simulation time 1067759468 ps
CPU time 24.63 seconds
Started Aug 12 06:45:36 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 251480 kb
Host smart-ff802d1a-18d8-4506-9831-92c6e2808b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649169110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2649169110
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4065683948
Short name T217
Test name
Test status
Simulation time 1258114784 ps
CPU time 8.66 seconds
Started Aug 12 06:45:37 PM PDT 24
Finished Aug 12 06:45:46 PM PDT 24
Peak memory 251500 kb
Host smart-95023c8c-f9e7-4dad-9204-50c0611fd072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065683948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4065683948
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1627615218
Short name T551
Test name
Test status
Simulation time 9663646627 ps
CPU time 47.72 seconds
Started Aug 12 06:45:41 PM PDT 24
Finished Aug 12 06:46:29 PM PDT 24
Peak memory 267872 kb
Host smart-28dd6703-4088-4455-a12a-1f95834c5c47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627615218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1627615218
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3071801686
Short name T638
Test name
Test status
Simulation time 32591495 ps
CPU time 0.93 seconds
Started Aug 12 06:45:37 PM PDT 24
Finished Aug 12 06:45:38 PM PDT 24
Peak memory 212464 kb
Host smart-d00ad55d-1918-4f81-aafe-9dc47638f595
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071801686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3071801686
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3757072347
Short name T539
Test name
Test status
Simulation time 274527844 ps
CPU time 10.86 seconds
Started Aug 12 06:45:41 PM PDT 24
Finished Aug 12 06:45:52 PM PDT 24
Peak memory 226616 kb
Host smart-5aeea905-631d-4314-ad97-39bed7b2b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757072347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3757072347
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2251125726
Short name T498
Test name
Test status
Simulation time 1693113814 ps
CPU time 14.09 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:59 PM PDT 24
Peak memory 218004 kb
Host smart-dcd879f4-871a-4b46-a75b-472e697a2436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251125726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2251125726
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4108364415
Short name T499
Test name
Test status
Simulation time 23096144 ps
CPU time 1.55 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:40 PM PDT 24
Peak memory 218912 kb
Host smart-1f0bf8bc-ad03-4b86-8aa1-24aaad2af2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108364415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4108364415
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1726914680
Short name T139
Test name
Test status
Simulation time 457608145 ps
CPU time 10.43 seconds
Started Aug 12 06:45:42 PM PDT 24
Finished Aug 12 06:45:52 PM PDT 24
Peak memory 219472 kb
Host smart-f943a6f1-1376-4afc-99d3-879cc0bbf77c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726914680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1726914680
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2795392502
Short name T851
Test name
Test status
Simulation time 2994000530 ps
CPU time 17.2 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:46:00 PM PDT 24
Peak memory 226660 kb
Host smart-951d6312-bfc6-4c79-8821-c68d5461f895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795392502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2795392502
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.570383789
Short name T654
Test name
Test status
Simulation time 497490920 ps
CPU time 10.04 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:55 PM PDT 24
Peak memory 218568 kb
Host smart-31d38c79-4cac-40bf-8742-367102b2ec2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570383789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.570383789
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2838576726
Short name T570
Test name
Test status
Simulation time 160627561 ps
CPU time 7.53 seconds
Started Aug 12 06:45:35 PM PDT 24
Finished Aug 12 06:45:43 PM PDT 24
Peak memory 218940 kb
Host smart-a5ca6fb9-617e-4eaa-999c-656212bf7d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838576726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2838576726
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2630242660
Short name T658
Test name
Test status
Simulation time 45621284 ps
CPU time 2.59 seconds
Started Aug 12 06:45:36 PM PDT 24
Finished Aug 12 06:45:39 PM PDT 24
Peak memory 218220 kb
Host smart-5be539c9-f3cb-46b7-b095-33cdacbc0b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630242660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2630242660
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3550875461
Short name T778
Test name
Test status
Simulation time 1350405262 ps
CPU time 24.69 seconds
Started Aug 12 06:45:42 PM PDT 24
Finished Aug 12 06:46:07 PM PDT 24
Peak memory 251456 kb
Host smart-cabe6e67-4804-45ee-b941-99ad41bc2d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550875461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3550875461
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.233453431
Short name T648
Test name
Test status
Simulation time 94429071 ps
CPU time 3.02 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:46 PM PDT 24
Peak memory 222732 kb
Host smart-fbb4b383-4483-4b76-b414-06e786494a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233453431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.233453431
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2922059748
Short name T316
Test name
Test status
Simulation time 34941877 ps
CPU time 0.83 seconds
Started Aug 12 06:45:46 PM PDT 24
Finished Aug 12 06:45:47 PM PDT 24
Peak memory 212496 kb
Host smart-87e4ba30-c7ee-4fa7-ba2c-a085ceab67a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922059748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2922059748
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1197832731
Short name T530
Test name
Test status
Simulation time 69416667 ps
CPU time 0.92 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:46 PM PDT 24
Peak memory 209520 kb
Host smart-ced0ead9-1ccc-41bd-833a-217dd793d052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197832731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1197832731
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2333889432
Short name T784
Test name
Test status
Simulation time 1066243117 ps
CPU time 9.82 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:53 PM PDT 24
Peak memory 218828 kb
Host smart-751b0388-91f3-4618-ad14-18ef5b540322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333889432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2333889432
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3319136121
Short name T724
Test name
Test status
Simulation time 1866456416 ps
CPU time 2.15 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:40 PM PDT 24
Peak memory 217600 kb
Host smart-792b17b3-b8f0-4f62-adf6-0c447dc2059a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319136121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3319136121
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2270689928
Short name T666
Test name
Test status
Simulation time 207694638 ps
CPU time 5.87 seconds
Started Aug 12 06:45:39 PM PDT 24
Finished Aug 12 06:45:45 PM PDT 24
Peak memory 223580 kb
Host smart-cf5789f1-2a4e-4f09-9321-0370076f039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270689928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2270689928
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.102762176
Short name T643
Test name
Test status
Simulation time 2572291718 ps
CPU time 16.33 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:46:00 PM PDT 24
Peak memory 226504 kb
Host smart-35e974c0-0142-4c09-b3ca-73ffbebb62ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102762176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.102762176
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.807971391
Short name T782
Test name
Test status
Simulation time 1086627272 ps
CPU time 9.49 seconds
Started Aug 12 06:45:42 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 226552 kb
Host smart-8b86f82f-890c-466a-b645-413157e78277
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807971391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.807971391
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3271284579
Short name T807
Test name
Test status
Simulation time 408222380 ps
CPU time 14.4 seconds
Started Aug 12 06:45:42 PM PDT 24
Finished Aug 12 06:45:56 PM PDT 24
Peak memory 226400 kb
Host smart-f0bba72b-dee3-4e15-b898-6530c1ff6c02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271284579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3271284579
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2887087097
Short name T631
Test name
Test status
Simulation time 368806905 ps
CPU time 14.22 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 218912 kb
Host smart-dccec15e-cf31-4dad-925b-7f6efe80457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887087097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2887087097
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3892877969
Short name T282
Test name
Test status
Simulation time 298240332 ps
CPU time 4.58 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:45 PM PDT 24
Peak memory 218216 kb
Host smart-25b5bb7b-ea93-4519-9ec6-b3c58b87171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892877969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3892877969
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2025016323
Short name T586
Test name
Test status
Simulation time 185188332 ps
CPU time 23.92 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:46:04 PM PDT 24
Peak memory 251464 kb
Host smart-6ec6171c-43e4-4e2e-a139-7fb8c13548d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025016323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2025016323
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3040817158
Short name T522
Test name
Test status
Simulation time 217138184 ps
CPU time 6.24 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:45 PM PDT 24
Peak memory 243300 kb
Host smart-ee169656-3fba-4bc8-8958-9725737da2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040817158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3040817158
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.4143710622
Short name T599
Test name
Test status
Simulation time 27790331085 ps
CPU time 79.18 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:47:05 PM PDT 24
Peak memory 226732 kb
Host smart-bb125a75-d4cd-4af3-b61f-8b5294c199b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143710622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.4143710622
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.214590999
Short name T431
Test name
Test status
Simulation time 12820899 ps
CPU time 0.92 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:46 PM PDT 24
Peak memory 212456 kb
Host smart-bf159275-6c09-437a-92d5-3b0c299fbbf4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214590999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.214590999
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1485154468
Short name T71
Test name
Test status
Simulation time 20289778 ps
CPU time 1.27 seconds
Started Aug 12 06:45:39 PM PDT 24
Finished Aug 12 06:45:41 PM PDT 24
Peak memory 209776 kb
Host smart-6cb7cf16-bc6d-41e0-b5cb-11c28fdf61dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485154468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1485154468
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3002146746
Short name T667
Test name
Test status
Simulation time 2984294420 ps
CPU time 14.4 seconds
Started Aug 12 06:45:37 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 219576 kb
Host smart-8dd1b1be-0dc9-4cfb-a81c-878d11e372a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002146746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3002146746
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2243128385
Short name T750
Test name
Test status
Simulation time 170630267 ps
CPU time 2.76 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:41 PM PDT 24
Peak memory 217632 kb
Host smart-7222c2fd-4906-404f-ad06-2e929078cfa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243128385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2243128385
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1006637272
Short name T232
Test name
Test status
Simulation time 170242657 ps
CPU time 4.22 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:49 PM PDT 24
Peak memory 222940 kb
Host smart-7fd5b5ed-2846-4f05-bd63-c8c9519f0504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006637272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1006637272
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3906312077
Short name T775
Test name
Test status
Simulation time 869823989 ps
CPU time 14.27 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:58 PM PDT 24
Peak memory 226660 kb
Host smart-3f190030-b4a9-414a-91f7-6f027291cc49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906312077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3906312077
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1262522354
Short name T604
Test name
Test status
Simulation time 851855895 ps
CPU time 11.48 seconds
Started Aug 12 06:45:39 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 226676 kb
Host smart-23c5b5ad-878b-441f-898d-9aa4c69b154d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262522354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1262522354
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3912425648
Short name T200
Test name
Test status
Simulation time 1098020322 ps
CPU time 10.47 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 218824 kb
Host smart-2e028819-845b-40ee-90dc-79728693abed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912425648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3912425648
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1253236836
Short name T161
Test name
Test status
Simulation time 13507659 ps
CPU time 1.26 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:10 PM PDT 24
Peak memory 212588 kb
Host smart-5cf51479-43d0-4394-8b91-dad1caa2578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253236836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1253236836
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.347348189
Short name T60
Test name
Test status
Simulation time 923228926 ps
CPU time 24.38 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:46:08 PM PDT 24
Peak memory 251480 kb
Host smart-d1821ed0-da8e-44fe-90ef-2b97797b86db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347348189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.347348189
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.4098770834
Short name T816
Test name
Test status
Simulation time 205203809 ps
CPU time 7.68 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:46 PM PDT 24
Peak memory 251472 kb
Host smart-3dfe59af-fb8c-416a-8717-f3c9b248ee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098770834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4098770834
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3612386520
Short name T858
Test name
Test status
Simulation time 19561830481 ps
CPU time 190.21 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:48:53 PM PDT 24
Peak memory 251448 kb
Host smart-6c483de7-cfa0-45ee-90ec-f0b9552ed93e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612386520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3612386520
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2393798277
Short name T397
Test name
Test status
Simulation time 10826164 ps
CPU time 0.96 seconds
Started Aug 12 06:45:42 PM PDT 24
Finished Aug 12 06:45:43 PM PDT 24
Peak memory 212456 kb
Host smart-01a67582-6a4b-4dba-bc60-33e2645e5512
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393798277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2393798277
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3567265113
Short name T390
Test name
Test status
Simulation time 23694658 ps
CPU time 1.18 seconds
Started Aug 12 06:45:51 PM PDT 24
Finished Aug 12 06:45:52 PM PDT 24
Peak memory 209620 kb
Host smart-39e692fa-fae9-49d4-8c0a-faf6565bbe5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567265113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3567265113
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2226090606
Short name T591
Test name
Test status
Simulation time 932174413 ps
CPU time 9.93 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:53 PM PDT 24
Peak memory 218832 kb
Host smart-cceee811-cc9c-4f8c-a237-c21fefc29c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226090606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2226090606
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1249638440
Short name T852
Test name
Test status
Simulation time 982604532 ps
CPU time 8.92 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:54 PM PDT 24
Peak memory 217920 kb
Host smart-c456ff59-a656-428b-b788-9664a3c46d2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249638440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1249638440
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1862749076
Short name T780
Test name
Test status
Simulation time 65708473 ps
CPU time 3.21 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:42 PM PDT 24
Peak memory 218860 kb
Host smart-703605f1-b53e-4a54-a92a-8743c09e042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862749076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1862749076
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2271200438
Short name T381
Test name
Test status
Simulation time 1947743201 ps
CPU time 10.15 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 226400 kb
Host smart-457a8b04-5c6f-4c41-bbe8-0582f942a16a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271200438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2271200438
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.933662306
Short name T602
Test name
Test status
Simulation time 5494779484 ps
CPU time 26.71 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 226724 kb
Host smart-0b90273b-6502-4263-9ca7-0c1784161213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933662306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.933662306
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2047515690
Short name T424
Test name
Test status
Simulation time 439842931 ps
CPU time 15.32 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:56 PM PDT 24
Peak memory 226596 kb
Host smart-789c0328-8ea4-4515-9afb-5bf8928106a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047515690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2047515690
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.350006492
Short name T657
Test name
Test status
Simulation time 2136652192 ps
CPU time 17.84 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:46:03 PM PDT 24
Peak memory 226660 kb
Host smart-22d5f545-fc59-4158-8157-ece6a8886630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350006492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.350006492
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.4136771471
Short name T349
Test name
Test status
Simulation time 31275860 ps
CPU time 2.28 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:45:43 PM PDT 24
Peak memory 218196 kb
Host smart-a1079d1e-3e3a-4043-a102-f48b244b52f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136771471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.4136771471
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2235994690
Short name T263
Test name
Test status
Simulation time 616809368 ps
CPU time 21.66 seconds
Started Aug 12 06:45:40 PM PDT 24
Finished Aug 12 06:46:02 PM PDT 24
Peak memory 251488 kb
Host smart-466d1211-3d91-4424-a1f8-6091c86c2b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235994690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2235994690
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.208065819
Short name T841
Test name
Test status
Simulation time 546232795 ps
CPU time 7.23 seconds
Started Aug 12 06:45:43 PM PDT 24
Finished Aug 12 06:45:50 PM PDT 24
Peak memory 251476 kb
Host smart-2b4cc491-eae3-43ed-b412-ca1ff731fd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208065819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.208065819
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1560655252
Short name T457
Test name
Test status
Simulation time 20805681 ps
CPU time 0.99 seconds
Started Aug 12 06:45:42 PM PDT 24
Finished Aug 12 06:45:43 PM PDT 24
Peak memory 212336 kb
Host smart-6aff6df3-a497-42f4-94ef-9399429655f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560655252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1560655252
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.756152823
Short name T532
Test name
Test status
Simulation time 38242831 ps
CPU time 0.88 seconds
Started Aug 12 06:45:46 PM PDT 24
Finished Aug 12 06:45:47 PM PDT 24
Peak memory 209416 kb
Host smart-b8800e06-8993-4dd9-b472-12861230ae0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756152823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.756152823
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.264431003
Short name T207
Test name
Test status
Simulation time 1370855815 ps
CPU time 15.7 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 226720 kb
Host smart-000b25ba-5441-49ee-b6e9-e5a160c0f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264431003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.264431003
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.99717172
Short name T387
Test name
Test status
Simulation time 906781091 ps
CPU time 7.16 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:52 PM PDT 24
Peak memory 217764 kb
Host smart-ce2a53d9-8ea8-4380-bd67-dd9a11cecfa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99717172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.99717172
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2653891192
Short name T294
Test name
Test status
Simulation time 46530176 ps
CPU time 2.33 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:41 PM PDT 24
Peak memory 218880 kb
Host smart-5a221a2a-1b63-4dee-9519-8b6e01d1323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653891192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2653891192
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1330953325
Short name T735
Test name
Test status
Simulation time 708041254 ps
CPU time 18.38 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:46:06 PM PDT 24
Peak memory 219176 kb
Host smart-c275ee50-e33e-4306-8f1a-240e029dfe20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330953325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1330953325
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.97927132
Short name T251
Test name
Test status
Simulation time 321584516 ps
CPU time 10.23 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:46:00 PM PDT 24
Peak memory 226572 kb
Host smart-55cc9219-2edd-4337-912b-8a2ad28c50aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97927132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_dig
est.97927132
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.427031380
Short name T533
Test name
Test status
Simulation time 1497860599 ps
CPU time 8.86 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:58 PM PDT 24
Peak memory 225592 kb
Host smart-0d5fdd05-b4df-4763-9b3b-f798eceffe49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427031380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.427031380
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1012670639
Short name T400
Test name
Test status
Simulation time 1129276998 ps
CPU time 9.59 seconds
Started Aug 12 06:45:46 PM PDT 24
Finished Aug 12 06:45:56 PM PDT 24
Peak memory 226664 kb
Host smart-c98fc87f-8218-4627-847b-d4a5897a0812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012670639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1012670639
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.783465682
Short name T668
Test name
Test status
Simulation time 184006107 ps
CPU time 2.66 seconds
Started Aug 12 06:45:38 PM PDT 24
Finished Aug 12 06:45:41 PM PDT 24
Peak memory 218252 kb
Host smart-62dbfaa3-5fbf-4e1e-894e-57d2350c5acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783465682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.783465682
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2374365647
Short name T692
Test name
Test status
Simulation time 173156749 ps
CPU time 21.41 seconds
Started Aug 12 06:45:46 PM PDT 24
Finished Aug 12 06:46:08 PM PDT 24
Peak memory 251540 kb
Host smart-5a0c5f0f-54f1-4d4b-abc4-b7358c440d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374365647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2374365647
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2316381183
Short name T309
Test name
Test status
Simulation time 43060309 ps
CPU time 6.9 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:53 PM PDT 24
Peak memory 251484 kb
Host smart-6c99c8c7-f5ba-488f-86c8-7ef495676691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316381183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2316381183
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2655863893
Short name T644
Test name
Test status
Simulation time 14913977081 ps
CPU time 200.77 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:49:10 PM PDT 24
Peak memory 267952 kb
Host smart-3ff8518a-63ac-4bd0-b37b-1e701b8f8062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655863893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2655863893
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3096426375
Short name T343
Test name
Test status
Simulation time 35570441 ps
CPU time 1.01 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:45:46 PM PDT 24
Peak memory 212472 kb
Host smart-87d200c8-70ba-4b27-bdaf-b08b0b4c977d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096426375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3096426375
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2485215957
Short name T489
Test name
Test status
Simulation time 15628979 ps
CPU time 0.9 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:50 PM PDT 24
Peak memory 209444 kb
Host smart-5536072e-cf84-4381-88bb-943cf2e76b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485215957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2485215957
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1731420093
Short name T796
Test name
Test status
Simulation time 256268772 ps
CPU time 12.18 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:46:02 PM PDT 24
Peak memory 218856 kb
Host smart-2e260ef4-d621-4b53-9cc3-d2dd3fd9f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731420093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1731420093
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1173927178
Short name T768
Test name
Test status
Simulation time 580493778 ps
CPU time 2.53 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:50 PM PDT 24
Peak memory 217600 kb
Host smart-672b84c3-53ea-4aef-bf4f-adc0e7990db0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173927178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1173927178
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3267771713
Short name T469
Test name
Test status
Simulation time 207655738 ps
CPU time 2.55 seconds
Started Aug 12 06:45:47 PM PDT 24
Finished Aug 12 06:45:50 PM PDT 24
Peak memory 218960 kb
Host smart-22848e65-864a-472d-ad14-7e454c630450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267771713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3267771713
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.4095908893
Short name T392
Test name
Test status
Simulation time 442726136 ps
CPU time 10.17 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:59 PM PDT 24
Peak memory 219512 kb
Host smart-290d15be-da37-4412-9d83-3f7dc1100f39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095908893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4095908893
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.610502968
Short name T824
Test name
Test status
Simulation time 1342753866 ps
CPU time 16.4 seconds
Started Aug 12 06:45:47 PM PDT 24
Finished Aug 12 06:46:04 PM PDT 24
Peak memory 226608 kb
Host smart-72e92344-84da-4d16-8d29-b69cd13652ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610502968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.610502968
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.480255362
Short name T845
Test name
Test status
Simulation time 317767830 ps
CPU time 8.49 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:56 PM PDT 24
Peak memory 218772 kb
Host smart-813f04e8-66a7-49a3-b177-87931b404191
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480255362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.480255362
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1837187005
Short name T480
Test name
Test status
Simulation time 502276048 ps
CPU time 6.62 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 225168 kb
Host smart-b3672e0d-d44c-4ded-952d-6f12b8308aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837187005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1837187005
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1581731484
Short name T868
Test name
Test status
Simulation time 95058571 ps
CPU time 3.7 seconds
Started Aug 12 06:45:47 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 218304 kb
Host smart-4e3c7983-3927-4d54-99ba-d19c025b6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581731484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1581731484
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.514028480
Short name T421
Test name
Test status
Simulation time 393120557 ps
CPU time 26.06 seconds
Started Aug 12 06:45:45 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 251468 kb
Host smart-3710f13e-5896-493b-95a0-ebed69d68b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514028480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.514028480
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3387563839
Short name T315
Test name
Test status
Simulation time 368489989 ps
CPU time 5.8 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:54 PM PDT 24
Peak memory 247472 kb
Host smart-75eb0eed-c350-48f7-99e7-05af4c59e21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387563839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3387563839
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1255794897
Short name T48
Test name
Test status
Simulation time 61676275723 ps
CPU time 479.99 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:53:48 PM PDT 24
Peak memory 276512 kb
Host smart-2f3cc5bc-16ea-4863-9358-ececb6e8b546
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255794897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1255794897
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.4031734085
Short name T153
Test name
Test status
Simulation time 22561886163 ps
CPU time 140.74 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:48:11 PM PDT 24
Peak memory 300848 kb
Host smart-c0e9d74d-6521-45bd-8985-8bb35f156679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4031734085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.4031734085
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2696138605
Short name T622
Test name
Test status
Simulation time 15070347 ps
CPU time 1.05 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 212432 kb
Host smart-8f6542e4-1b70-4c95-ad90-9dfd4329efd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696138605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2696138605
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2596780725
Short name T765
Test name
Test status
Simulation time 48455700 ps
CPU time 0.95 seconds
Started Aug 12 06:45:51 PM PDT 24
Finished Aug 12 06:45:52 PM PDT 24
Peak memory 209488 kb
Host smart-4b6367c4-3ceb-4cab-82df-070ee3ea93a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596780725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2596780725
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.218548717
Short name T358
Test name
Test status
Simulation time 6626506283 ps
CPU time 12.96 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:46:02 PM PDT 24
Peak memory 219240 kb
Host smart-85e4ace9-08a6-4394-9cf7-a548700ea11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218548717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.218548717
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.335210471
Short name T481
Test name
Test status
Simulation time 394510474 ps
CPU time 9.67 seconds
Started Aug 12 06:45:47 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 217608 kb
Host smart-32488d7e-3d1e-40d4-a4e2-749c2a41c6d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335210471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.335210471
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1672049429
Short name T419
Test name
Test status
Simulation time 83457959 ps
CPU time 3.04 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:52 PM PDT 24
Peak memory 218800 kb
Host smart-0c00cdcd-7d38-4215-b4a8-d385dee19975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672049429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1672049429
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2663641513
Short name T839
Test name
Test status
Simulation time 1538133992 ps
CPU time 17.13 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:46:06 PM PDT 24
Peak memory 226704 kb
Host smart-fd9349ef-8b1b-447b-923d-418a16cfaed5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663641513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2663641513
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2828762001
Short name T405
Test name
Test status
Simulation time 1241461019 ps
CPU time 11.71 seconds
Started Aug 12 06:45:51 PM PDT 24
Finished Aug 12 06:46:03 PM PDT 24
Peak memory 226532 kb
Host smart-ae971418-0369-472d-9fc7-5cc9ba89d823
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828762001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2828762001
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4277815803
Short name T289
Test name
Test status
Simulation time 223840130 ps
CPU time 9.15 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 218748 kb
Host smart-fda1e0d1-38bf-42dc-91a7-ee34241dad17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277815803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4277815803
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3931732296
Short name T608
Test name
Test status
Simulation time 462409106 ps
CPU time 9.18 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:45:59 PM PDT 24
Peak memory 225428 kb
Host smart-6c88e45e-86dd-43f8-b0f3-e1a44f6cac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931732296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3931732296
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1339761249
Short name T427
Test name
Test status
Simulation time 88711352 ps
CPU time 2.06 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 214788 kb
Host smart-f9c161c2-3f49-4e38-a420-b6e128c82864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339761249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1339761249
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1977762288
Short name T341
Test name
Test status
Simulation time 4843865372 ps
CPU time 35.28 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:46:24 PM PDT 24
Peak memory 251552 kb
Host smart-818d1a79-5a72-4247-8777-efcaa355d50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977762288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1977762288
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1956526386
Short name T459
Test name
Test status
Simulation time 324915205 ps
CPU time 8.73 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 251480 kb
Host smart-a881ab66-6382-43ea-a59b-67082974f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956526386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1956526386
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.633584013
Short name T600
Test name
Test status
Simulation time 42796945 ps
CPU time 0.95 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:50 PM PDT 24
Peak memory 212364 kb
Host smart-e577f50a-d6c0-4b37-89da-4e2dc4735011
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633584013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.633584013
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4070525973
Short name T485
Test name
Test status
Simulation time 77158644 ps
CPU time 0.9 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:49 PM PDT 24
Peak memory 209484 kb
Host smart-659444e8-1bb4-4d70-801d-59309d6ff046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070525973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4070525973
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3504190814
Short name T239
Test name
Test status
Simulation time 275863427 ps
CPU time 10.41 seconds
Started Aug 12 06:45:47 PM PDT 24
Finished Aug 12 06:45:58 PM PDT 24
Peak memory 218864 kb
Host smart-115a79af-0e54-4742-8451-6cd367f7ee88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504190814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3504190814
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4033957103
Short name T30
Test name
Test status
Simulation time 694539430 ps
CPU time 5.32 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:53 PM PDT 24
Peak memory 217920 kb
Host smart-8da34714-9ae3-4363-b234-cdb0829ce8a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033957103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4033957103
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2365689589
Short name T417
Test name
Test status
Simulation time 69488781 ps
CPU time 2.86 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:45:53 PM PDT 24
Peak memory 222892 kb
Host smart-e342352a-5669-433a-854b-76a6f54f97b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365689589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2365689589
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3930605908
Short name T410
Test name
Test status
Simulation time 305396858 ps
CPU time 11.73 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:46:02 PM PDT 24
Peak memory 219544 kb
Host smart-e66b7875-f3f8-4c55-b585-ef5ec3bdbaed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930605908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3930605908
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.631628762
Short name T634
Test name
Test status
Simulation time 2306131703 ps
CPU time 28.99 seconds
Started Aug 12 06:45:47 PM PDT 24
Finished Aug 12 06:46:16 PM PDT 24
Peak memory 226684 kb
Host smart-27cf7add-0f9a-4abf-a44b-ae2a91ca6e5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631628762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.631628762
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1411776766
Short name T612
Test name
Test status
Simulation time 441664659 ps
CPU time 8.95 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 218816 kb
Host smart-6d91796a-e741-4827-a9eb-4dfda82a3fe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411776766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1411776766
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2533777370
Short name T833
Test name
Test status
Simulation time 366448502 ps
CPU time 5.96 seconds
Started Aug 12 06:45:48 PM PDT 24
Finished Aug 12 06:45:54 PM PDT 24
Peak memory 225404 kb
Host smart-1e7362c1-acd0-471d-aa41-e6ace8ef1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533777370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2533777370
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.526863337
Short name T288
Test name
Test status
Simulation time 15145273 ps
CPU time 1.24 seconds
Started Aug 12 06:45:47 PM PDT 24
Finished Aug 12 06:45:48 PM PDT 24
Peak memory 218216 kb
Host smart-26ee20bd-c9ef-47e9-acc9-729c5fac692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526863337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.526863337
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3948038456
Short name T729
Test name
Test status
Simulation time 81516023 ps
CPU time 2.54 seconds
Started Aug 12 06:45:51 PM PDT 24
Finished Aug 12 06:45:54 PM PDT 24
Peak memory 222944 kb
Host smart-04b675f5-62f6-4138-80c7-5ecaea1be6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948038456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3948038456
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.134409197
Short name T790
Test name
Test status
Simulation time 14725763218 ps
CPU time 146.03 seconds
Started Aug 12 06:45:51 PM PDT 24
Finished Aug 12 06:48:17 PM PDT 24
Peak memory 251972 kb
Host smart-0e7baa7d-49aa-4b01-b970-f016ef727289
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134409197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.134409197
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2900892643
Short name T579
Test name
Test status
Simulation time 12486654 ps
CPU time 0.88 seconds
Started Aug 12 06:45:46 PM PDT 24
Finished Aug 12 06:45:47 PM PDT 24
Peak memory 208772 kb
Host smart-3737a47e-ff59-4f13-942c-248803479054
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900892643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2900892643
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1632342977
Short name T520
Test name
Test status
Simulation time 30489696 ps
CPU time 1.07 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 209588 kb
Host smart-068aecae-82b0-45d0-b07e-81eb05488d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632342977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1632342977
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2537842594
Short name T331
Test name
Test status
Simulation time 1092015009 ps
CPU time 15.72 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:46:20 PM PDT 24
Peak memory 218856 kb
Host smart-8c9683e9-6abc-4e11-b928-62243d11ebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537842594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2537842594
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2891449393
Short name T468
Test name
Test status
Simulation time 863416539 ps
CPU time 2.6 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 217572 kb
Host smart-06928e6b-4bb4-4e3e-b0a0-fbf1896f4114
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891449393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2891449393
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3737363619
Short name T324
Test name
Test status
Simulation time 22067260 ps
CPU time 1.8 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:51 PM PDT 24
Peak memory 218892 kb
Host smart-aa2a2c78-8f7f-4b49-8fe9-d278d9c294ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737363619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3737363619
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1353266362
Short name T529
Test name
Test status
Simulation time 441268274 ps
CPU time 11.21 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 218860 kb
Host smart-80cea721-5d43-4d17-8f2f-7dc3d74c45b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353266362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1353266362
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3059074618
Short name T23
Test name
Test status
Simulation time 1602878565 ps
CPU time 11.38 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 226572 kb
Host smart-c6ef602e-b441-41c6-a24d-fecfd5dd1d9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059074618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3059074618
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2334189960
Short name T572
Test name
Test status
Simulation time 1119720827 ps
CPU time 10.38 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 218796 kb
Host smart-5dc94b33-5e26-490c-883c-e6e1078d9f44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334189960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2334189960
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2176858050
Short name T848
Test name
Test status
Simulation time 586545969 ps
CPU time 12.26 seconds
Started Aug 12 06:46:03 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 226236 kb
Host smart-556bdd06-6415-46ee-99e3-5d73ea85fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176858050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2176858050
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3422669467
Short name T28
Test name
Test status
Simulation time 32070000 ps
CPU time 1.03 seconds
Started Aug 12 06:45:52 PM PDT 24
Finished Aug 12 06:45:53 PM PDT 24
Peak memory 212708 kb
Host smart-6a837e82-a901-4917-b7db-bc5d14e94b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422669467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3422669467
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3043623591
Short name T623
Test name
Test status
Simulation time 2042896944 ps
CPU time 26.05 seconds
Started Aug 12 06:45:50 PM PDT 24
Finished Aug 12 06:46:16 PM PDT 24
Peak memory 251368 kb
Host smart-3bc87600-736e-4c7a-91dd-b30c02576e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043623591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3043623591
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3535022937
Short name T281
Test name
Test status
Simulation time 149545153 ps
CPU time 8.14 seconds
Started Aug 12 06:45:52 PM PDT 24
Finished Aug 12 06:46:00 PM PDT 24
Peak memory 251456 kb
Host smart-f2d2122c-b14d-4b53-8bf6-0e466b9898e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535022937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3535022937
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3215731464
Short name T473
Test name
Test status
Simulation time 8420634554 ps
CPU time 169.16 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:48:53 PM PDT 24
Peak memory 268664 kb
Host smart-1229192f-3ca7-477e-9c7d-31391cc75d0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215731464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3215731464
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.290448221
Short name T810
Test name
Test status
Simulation time 40397322 ps
CPU time 1.02 seconds
Started Aug 12 06:45:49 PM PDT 24
Finished Aug 12 06:45:50 PM PDT 24
Peak memory 212424 kb
Host smart-a2ce1074-9f1a-42fe-83b7-20eaf917791e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290448221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.290448221
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3880224211
Short name T322
Test name
Test status
Simulation time 20719981 ps
CPU time 0.97 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:44:12 PM PDT 24
Peak memory 209420 kb
Host smart-ee3a7081-b4d4-4e90-a381-da8be0c38d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880224211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3880224211
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3102456539
Short name T521
Test name
Test status
Simulation time 10877034 ps
CPU time 0.85 seconds
Started Aug 12 06:44:01 PM PDT 24
Finished Aug 12 06:44:02 PM PDT 24
Peak memory 209120 kb
Host smart-172ed1a1-732f-4de6-9826-9459e49c0d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102456539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3102456539
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2249659076
Short name T304
Test name
Test status
Simulation time 212738674 ps
CPU time 8.35 seconds
Started Aug 12 06:44:00 PM PDT 24
Finished Aug 12 06:44:09 PM PDT 24
Peak memory 218824 kb
Host smart-d017a6e5-e4b0-43a3-ab65-1c992eab90c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249659076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2249659076
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4060701950
Short name T29
Test name
Test status
Simulation time 484803729 ps
CPU time 13.19 seconds
Started Aug 12 06:44:01 PM PDT 24
Finished Aug 12 06:44:14 PM PDT 24
Peak memory 217996 kb
Host smart-1d665c21-5bd7-4003-b2c9-dad0f782b9cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060701950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4060701950
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1632712679
Short name T589
Test name
Test status
Simulation time 8548440576 ps
CPU time 36.18 seconds
Started Aug 12 06:44:04 PM PDT 24
Finished Aug 12 06:44:40 PM PDT 24
Peak memory 219528 kb
Host smart-92a21a8c-d7d0-447f-b84f-1daf1b8564fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632712679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1632712679
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.598582810
Short name T646
Test name
Test status
Simulation time 377596617 ps
CPU time 4.66 seconds
Started Aug 12 06:44:00 PM PDT 24
Finished Aug 12 06:44:05 PM PDT 24
Peak memory 222404 kb
Host smart-ab44766f-8258-46ab-bcbd-d30a4213e751
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598582810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.598582810
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2403465512
Short name T298
Test name
Test status
Simulation time 1347182438 ps
CPU time 19.58 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:44:30 PM PDT 24
Peak memory 218172 kb
Host smart-ada92bef-e39e-40e1-be6c-068d2c1b8582
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403465512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2403465512
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.700622980
Short name T84
Test name
Test status
Simulation time 283316020 ps
CPU time 4.73 seconds
Started Aug 12 06:44:05 PM PDT 24
Finished Aug 12 06:44:09 PM PDT 24
Peak memory 218212 kb
Host smart-fbd1a228-01c9-4b87-b6a1-c9695bf3d0b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700622980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.700622980
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2629851581
Short name T262
Test name
Test status
Simulation time 10814693134 ps
CPU time 54.55 seconds
Started Aug 12 06:44:01 PM PDT 24
Finished Aug 12 06:44:55 PM PDT 24
Peak memory 276976 kb
Host smart-607d7299-37d3-4047-96d2-8497fdcbd8e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629851581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2629851581
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2939865286
Short name T598
Test name
Test status
Simulation time 441220717 ps
CPU time 8.54 seconds
Started Aug 12 06:44:03 PM PDT 24
Finished Aug 12 06:44:11 PM PDT 24
Peak memory 223364 kb
Host smart-d3416789-e237-4e08-9421-884b135f4243
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939865286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2939865286
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3464799637
Short name T37
Test name
Test status
Simulation time 76366122 ps
CPU time 3.31 seconds
Started Aug 12 06:44:01 PM PDT 24
Finished Aug 12 06:44:05 PM PDT 24
Peak memory 218868 kb
Host smart-e15c5672-dcd8-4d58-8339-413c18f6d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464799637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3464799637
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1688728973
Short name T645
Test name
Test status
Simulation time 553046828 ps
CPU time 9.73 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:44:11 PM PDT 24
Peak memory 218208 kb
Host smart-e6321dde-9ea1-44d4-9c67-81ef9d92028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688728973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1688728973
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3591904821
Short name T92
Test name
Test status
Simulation time 253086842 ps
CPU time 35.84 seconds
Started Aug 12 06:44:10 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 282012 kb
Host smart-920edfdd-91a9-4ce2-8d07-a85955a29578
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591904821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3591904821
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.241574562
Short name T408
Test name
Test status
Simulation time 781712493 ps
CPU time 8.39 seconds
Started Aug 12 06:44:12 PM PDT 24
Finished Aug 12 06:44:20 PM PDT 24
Peak memory 219028 kb
Host smart-4effbd64-ebde-46bc-9e49-06038c77f65f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241574562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.241574562
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.205259471
Short name T339
Test name
Test status
Simulation time 353435919 ps
CPU time 12.75 seconds
Started Aug 12 06:44:13 PM PDT 24
Finished Aug 12 06:44:26 PM PDT 24
Peak memory 226500 kb
Host smart-2eda0ce3-0f99-4898-912b-d12ccdd9dbc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205259471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.205259471
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2162967421
Short name T593
Test name
Test status
Simulation time 934656719 ps
CPU time 9.63 seconds
Started Aug 12 06:44:12 PM PDT 24
Finished Aug 12 06:44:22 PM PDT 24
Peak memory 218808 kb
Host smart-a970f99d-2c3a-4f5d-ae87-70b9462961a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162967421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
162967421
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2622310795
Short name T663
Test name
Test status
Simulation time 980745707 ps
CPU time 9.91 seconds
Started Aug 12 06:44:00 PM PDT 24
Finished Aug 12 06:44:10 PM PDT 24
Peak memory 226148 kb
Host smart-3880d642-2a25-48f0-877f-9f8f1629a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622310795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2622310795
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2976978691
Short name T204
Test name
Test status
Simulation time 116297330 ps
CPU time 2.41 seconds
Started Aug 12 06:44:06 PM PDT 24
Finished Aug 12 06:44:08 PM PDT 24
Peak memory 218184 kb
Host smart-fee05ec7-221b-4bd0-9cc2-901bb13c9497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976978691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2976978691
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.647304024
Short name T710
Test name
Test status
Simulation time 245715231 ps
CPU time 26.33 seconds
Started Aug 12 06:44:00 PM PDT 24
Finished Aug 12 06:44:26 PM PDT 24
Peak memory 251480 kb
Host smart-a08e406a-d5bb-4b68-a693-10d9dd88c409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647304024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.647304024
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1810581452
Short name T474
Test name
Test status
Simulation time 283093352 ps
CPU time 7.05 seconds
Started Aug 12 06:44:03 PM PDT 24
Finished Aug 12 06:44:10 PM PDT 24
Peak memory 246860 kb
Host smart-f1ae56ca-691d-4647-a355-4221be845201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810581452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1810581452
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3357110942
Short name T483
Test name
Test status
Simulation time 10352396269 ps
CPU time 104.9 seconds
Started Aug 12 06:44:12 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 251432 kb
Host smart-711151b7-0427-42d1-8bf3-52ad2ea2fdc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357110942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3357110942
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3232840275
Short name T494
Test name
Test status
Simulation time 15424588 ps
CPU time 0.96 seconds
Started Aug 12 06:44:02 PM PDT 24
Finished Aug 12 06:44:03 PM PDT 24
Peak memory 218292 kb
Host smart-6a25145a-5f47-47aa-bab4-0a4bf79e4be1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232840275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3232840275
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3483201822
Short name T628
Test name
Test status
Simulation time 47493175 ps
CPU time 0.85 seconds
Started Aug 12 06:45:57 PM PDT 24
Finished Aug 12 06:45:58 PM PDT 24
Peak memory 209492 kb
Host smart-22186d0b-ec78-4ef7-8672-222ef3188aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483201822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3483201822
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4058520183
Short name T542
Test name
Test status
Simulation time 1465169964 ps
CPU time 12.43 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:46:17 PM PDT 24
Peak memory 218760 kb
Host smart-e56785fa-fea7-4e4e-8394-fa360a48839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058520183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4058520183
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.24751847
Short name T448
Test name
Test status
Simulation time 2790643028 ps
CPU time 13.2 seconds
Started Aug 12 06:46:02 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 218312 kb
Host smart-75546fda-9f41-4025-a401-1bf50d347e84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24751847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.24751847
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3849113742
Short name T854
Test name
Test status
Simulation time 24846224 ps
CPU time 2 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 218816 kb
Host smart-dc386bf7-8680-4af6-96b4-3e484640501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849113742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3849113742
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1422619894
Short name T456
Test name
Test status
Simulation time 685119686 ps
CPU time 16.74 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 220540 kb
Host smart-11980bfe-d805-4b85-b704-709f9441a3bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422619894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1422619894
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3186331966
Short name T677
Test name
Test status
Simulation time 1182615247 ps
CPU time 12.88 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 226612 kb
Host smart-d1db6b8e-452e-43b0-85df-1b7333fa47a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186331966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3186331966
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.335169032
Short name T406
Test name
Test status
Simulation time 2061192639 ps
CPU time 11.89 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 218844 kb
Host smart-adf845b7-6976-4550-8162-070263127136
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335169032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.335169032
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2513394973
Short name T280
Test name
Test status
Simulation time 1273958759 ps
CPU time 12.41 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 226676 kb
Host smart-8a328b55-aa8c-438e-a9aa-fb2ca5f1fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513394973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2513394973
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3089296030
Short name T630
Test name
Test status
Simulation time 273724872 ps
CPU time 8.05 seconds
Started Aug 12 06:46:03 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 218212 kb
Host smart-0214e566-6338-46d8-b6c4-ddbfed083686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089296030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3089296030
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3162369406
Short name T312
Test name
Test status
Simulation time 445055324 ps
CPU time 24.16 seconds
Started Aug 12 06:46:02 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 251592 kb
Host smart-81432592-6ad5-452f-9757-c2f51dcdc00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162369406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3162369406
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3398455834
Short name T678
Test name
Test status
Simulation time 101413061 ps
CPU time 8.71 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:46:08 PM PDT 24
Peak memory 251520 kb
Host smart-68dc2813-7dd2-473b-8030-c04328915c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398455834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3398455834
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2755554858
Short name T420
Test name
Test status
Simulation time 4125982418 ps
CPU time 147.5 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:48:28 PM PDT 24
Peak memory 276648 kb
Host smart-e21d025e-981b-4458-9883-54bc9141099f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755554858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2755554858
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1239289505
Short name T136
Test name
Test status
Simulation time 12062994813 ps
CPU time 79.6 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:47:23 PM PDT 24
Peak memory 276092 kb
Host smart-04df80ae-a6e7-4efb-81df-6b21372d664f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1239289505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1239289505
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1226543227
Short name T246
Test name
Test status
Simulation time 11091542 ps
CPU time 0.99 seconds
Started Aug 12 06:45:56 PM PDT 24
Finished Aug 12 06:45:57 PM PDT 24
Peak memory 212452 kb
Host smart-32640926-2db3-4b5e-98f8-4de21c8ba9bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226543227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1226543227
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1423017154
Short name T495
Test name
Test status
Simulation time 36162987 ps
CPU time 0.82 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:46:05 PM PDT 24
Peak memory 209252 kb
Host smart-78f13edf-6632-40fc-9889-da7ceae1a969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423017154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1423017154
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.346724207
Short name T206
Test name
Test status
Simulation time 1812935832 ps
CPU time 9.44 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:10 PM PDT 24
Peak memory 226628 kb
Host smart-f95fd1be-aa93-4127-8885-316e279cc868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346724207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.346724207
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3521263697
Short name T759
Test name
Test status
Simulation time 1782111178 ps
CPU time 10.24 seconds
Started Aug 12 06:45:57 PM PDT 24
Finished Aug 12 06:46:08 PM PDT 24
Peak memory 217988 kb
Host smart-2561d2f3-c36c-49c7-81ce-15db4833dfa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521263697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3521263697
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3636941066
Short name T377
Test name
Test status
Simulation time 103200348 ps
CPU time 1.55 seconds
Started Aug 12 06:45:57 PM PDT 24
Finished Aug 12 06:45:59 PM PDT 24
Peak memory 218912 kb
Host smart-68ba19c9-1acc-46bd-800a-83b35c947ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636941066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3636941066
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.765142866
Short name T709
Test name
Test status
Simulation time 462719706 ps
CPU time 10.56 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 226676 kb
Host smart-b6313e17-dd4e-49ef-917d-342f175c54bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765142866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.765142866
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4182380955
Short name T581
Test name
Test status
Simulation time 2654577439 ps
CPU time 10.15 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 226660 kb
Host smart-8e02f897-2eb1-48d4-a0e1-31f3452e1a93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182380955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.4182380955
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2020423307
Short name T562
Test name
Test status
Simulation time 1809389492 ps
CPU time 10.4 seconds
Started Aug 12 06:46:01 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 218852 kb
Host smart-5e6a7f8f-81ca-493b-a686-d674e83c908a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020423307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2020423307
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1210348698
Short name T823
Test name
Test status
Simulation time 1224709785 ps
CPU time 10.92 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:46:10 PM PDT 24
Peak memory 226664 kb
Host smart-cd8655d0-4d8e-4341-9894-597da9c59c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210348698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1210348698
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3809233601
Short name T687
Test name
Test status
Simulation time 389748044 ps
CPU time 3.13 seconds
Started Aug 12 06:46:02 PM PDT 24
Finished Aug 12 06:46:06 PM PDT 24
Peak memory 218136 kb
Host smart-f268537b-52da-4f55-a2db-1000787ec704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809233601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3809233601
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.581203335
Short name T869
Test name
Test status
Simulation time 670181483 ps
CPU time 24.98 seconds
Started Aug 12 06:46:03 PM PDT 24
Finished Aug 12 06:46:28 PM PDT 24
Peak memory 251500 kb
Host smart-c23dd5c9-bb63-4de0-ad97-91075d33dc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581203335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.581203335
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1792243245
Short name T742
Test name
Test status
Simulation time 60574551 ps
CPU time 7.64 seconds
Started Aug 12 06:45:57 PM PDT 24
Finished Aug 12 06:46:05 PM PDT 24
Peak memory 251508 kb
Host smart-d96b2547-6356-4b0b-8549-6eb896a577cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792243245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1792243245
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2193361431
Short name T656
Test name
Test status
Simulation time 15258605238 ps
CPU time 260.91 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:50:20 PM PDT 24
Peak memory 284444 kb
Host smart-b528f45f-f0f8-4927-8136-8bd6af53c09a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193361431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2193361431
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3692869637
Short name T236
Test name
Test status
Simulation time 14428228 ps
CPU time 1.09 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 212432 kb
Host smart-3e497c92-2b05-4d78-b9cf-efc7415a1410
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692869637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3692869637
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1605474438
Short name T574
Test name
Test status
Simulation time 59157184 ps
CPU time 1.06 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:45:59 PM PDT 24
Peak memory 209544 kb
Host smart-5f7a1f21-8d49-4892-9386-3ed872ec22fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605474438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1605474438
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3997526455
Short name T140
Test name
Test status
Simulation time 1610470482 ps
CPU time 17.86 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:18 PM PDT 24
Peak memory 226680 kb
Host smart-56f80423-a8f6-4b58-8376-42bcf3ccc942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997526455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3997526455
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3768699210
Short name T797
Test name
Test status
Simulation time 593304816 ps
CPU time 3.47 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:46:02 PM PDT 24
Peak memory 217664 kb
Host smart-0c276831-6d3b-475d-8d1d-6ffce47c0ba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768699210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3768699210
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.838735102
Short name T632
Test name
Test status
Simulation time 36552269 ps
CPU time 1.88 seconds
Started Aug 12 06:46:03 PM PDT 24
Finished Aug 12 06:46:05 PM PDT 24
Peak memory 218860 kb
Host smart-f04ed8f3-7f8a-4f33-897f-ca89932eb608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838735102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.838735102
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3711635038
Short name T46
Test name
Test status
Simulation time 1302616097 ps
CPU time 11.13 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 218896 kb
Host smart-f507de20-b7a8-426d-a4b4-85e3eff6ab73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711635038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3711635038
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2191067018
Short name T717
Test name
Test status
Simulation time 557077674 ps
CPU time 12.13 seconds
Started Aug 12 06:46:01 PM PDT 24
Finished Aug 12 06:46:13 PM PDT 24
Peak memory 226608 kb
Host smart-91b663a7-076c-406b-9915-8ff12affa275
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191067018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2191067018
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4205841070
Short name T297
Test name
Test status
Simulation time 405508330 ps
CPU time 14.97 seconds
Started Aug 12 06:45:57 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 226592 kb
Host smart-76c78191-a541-44cc-ab59-e0b312fddd10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205841070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4205841070
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3641070894
Short name T679
Test name
Test status
Simulation time 770061130 ps
CPU time 11.38 seconds
Started Aug 12 06:46:03 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 226536 kb
Host smart-ba5c921c-aec2-4cdb-8d9a-473eef2413e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641070894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3641070894
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.539483869
Short name T82
Test name
Test status
Simulation time 15174088 ps
CPU time 1.24 seconds
Started Aug 12 06:45:57 PM PDT 24
Finished Aug 12 06:45:59 PM PDT 24
Peak memory 212840 kb
Host smart-0b563b9a-053b-46a7-a5d8-f7fd30d42b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539483869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.539483869
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3076154842
Short name T86
Test name
Test status
Simulation time 208150917 ps
CPU time 23.12 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:22 PM PDT 24
Peak memory 251184 kb
Host smart-a3335fe8-fd07-467d-a0ca-d48d2e4f5b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076154842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3076154842
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3388318043
Short name T752
Test name
Test status
Simulation time 287951759 ps
CPU time 8.93 seconds
Started Aug 12 06:45:58 PM PDT 24
Finished Aug 12 06:46:07 PM PDT 24
Peak memory 251484 kb
Host smart-91927db0-e79c-45cc-95f8-1bb1f0966266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388318043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3388318043
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1161263671
Short name T17
Test name
Test status
Simulation time 5927945767 ps
CPU time 179.13 seconds
Started Aug 12 06:45:59 PM PDT 24
Finished Aug 12 06:48:58 PM PDT 24
Peak memory 284268 kb
Host smart-4be24c3f-813d-4fbe-99b5-25fac139be20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161263671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1161263671
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3376019530
Short name T430
Test name
Test status
Simulation time 15214358 ps
CPU time 1.12 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:01 PM PDT 24
Peak memory 212400 kb
Host smart-736abb5a-9568-4bcc-b477-f7f22573e779
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376019530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3376019530
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.967310130
Short name T751
Test name
Test status
Simulation time 20941064 ps
CPU time 1.2 seconds
Started Aug 12 06:46:13 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 209472 kb
Host smart-9234f7fb-d6b8-46b4-95f4-b9096e5dfbbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967310130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.967310130
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3993727956
Short name T205
Test name
Test status
Simulation time 374190849 ps
CPU time 9.42 seconds
Started Aug 12 06:46:01 PM PDT 24
Finished Aug 12 06:46:10 PM PDT 24
Peak memory 218840 kb
Host smart-14cf5a4a-74a1-4744-987f-0054a73831db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993727956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3993727956
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1075786076
Short name T395
Test name
Test status
Simulation time 503752808 ps
CPU time 3 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:46:07 PM PDT 24
Peak memory 217560 kb
Host smart-5e8e620b-07b7-4109-8bc7-4533b5617720
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075786076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1075786076
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3264109839
Short name T660
Test name
Test status
Simulation time 256238404 ps
CPU time 3.14 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:46:07 PM PDT 24
Peak memory 223084 kb
Host smart-998ff5e6-9992-4bf9-b62e-26c85b44e735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264109839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3264109839
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1398723502
Short name T247
Test name
Test status
Simulation time 2836620293 ps
CPU time 9.8 seconds
Started Aug 12 06:46:01 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 226708 kb
Host smart-1c628c00-8fe7-4a52-8ac7-685f027356e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398723502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1398723502
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3346106585
Short name T592
Test name
Test status
Simulation time 1576553197 ps
CPU time 11.36 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 226736 kb
Host smart-a04ea6d4-f100-4e61-909a-f4e0cf88a143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346106585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3346106585
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.4151223038
Short name T299
Test name
Test status
Simulation time 637785054 ps
CPU time 7.96 seconds
Started Aug 12 06:46:02 PM PDT 24
Finished Aug 12 06:46:10 PM PDT 24
Peak memory 226604 kb
Host smart-8c56adbf-17c6-42fd-92e7-8ce991fba5f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151223038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
4151223038
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1004259152
Short name T193
Test name
Test status
Simulation time 310967881 ps
CPU time 8.22 seconds
Started Aug 12 06:46:01 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 225520 kb
Host smart-1db9beb4-18cd-41b0-b902-edd5bc83a684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004259152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1004259152
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3357940189
Short name T1
Test name
Test status
Simulation time 60962223 ps
CPU time 1.28 seconds
Started Aug 12 06:46:03 PM PDT 24
Finished Aug 12 06:46:05 PM PDT 24
Peak memory 218224 kb
Host smart-8356c9b3-f5e9-46a1-89f3-179a137dc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357940189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3357940189
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2534965718
Short name T375
Test name
Test status
Simulation time 618944781 ps
CPU time 30.66 seconds
Started Aug 12 06:46:00 PM PDT 24
Finished Aug 12 06:46:31 PM PDT 24
Peak memory 251524 kb
Host smart-e2b9304f-f824-415d-9802-e8ce10985890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534965718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2534965718
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.904594620
Short name T826
Test name
Test status
Simulation time 56685399 ps
CPU time 7.66 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 251412 kb
Host smart-eb14bfd4-4635-401b-8958-a1689be91d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904594620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.904594620
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1735076875
Short name T78
Test name
Test status
Simulation time 4481919133 ps
CPU time 105.6 seconds
Started Aug 12 06:46:04 PM PDT 24
Finished Aug 12 06:47:49 PM PDT 24
Peak memory 272964 kb
Host smart-2cc5216a-3692-4ea5-ad79-50f310de2f65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735076875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1735076875
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4106030777
Short name T721
Test name
Test status
Simulation time 65154651 ps
CPU time 0.99 seconds
Started Aug 12 06:45:57 PM PDT 24
Finished Aug 12 06:45:58 PM PDT 24
Peak memory 212480 kb
Host smart-7bfc4bc3-a082-4a09-8a87-bd04a4097071
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106030777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.4106030777
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.320190198
Short name T832
Test name
Test status
Simulation time 129783741 ps
CPU time 1.04 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 209432 kb
Host smart-de5fef3c-4bba-4c22-ba4d-d21d25075bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320190198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.320190198
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2643007218
Short name T525
Test name
Test status
Simulation time 1101488861 ps
CPU time 10.48 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:18 PM PDT 24
Peak memory 218856 kb
Host smart-cce0e807-2d6c-4037-a25b-9cbe9ebd74ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643007218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2643007218
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2192072985
Short name T32
Test name
Test status
Simulation time 2921317303 ps
CPU time 8.04 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 218076 kb
Host smart-0c83fa16-3933-4761-b63d-e8f6538770f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192072985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2192072985
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2577732320
Short name T211
Test name
Test status
Simulation time 71221385 ps
CPU time 3.76 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 218832 kb
Host smart-fd185eb3-89d7-42f9-aa19-577d3852cb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577732320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2577732320
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1639761624
Short name T3
Test name
Test status
Simulation time 521523288 ps
CPU time 15.47 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:24 PM PDT 24
Peak memory 218872 kb
Host smart-0f3e0c3a-e9e1-4a41-a9ed-1944084dd7a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639761624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1639761624
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.982040644
Short name T14
Test name
Test status
Simulation time 401911239 ps
CPU time 12.57 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 226560 kb
Host smart-43373bbb-050f-4b18-a28e-329e7687f878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982040644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.982040644
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.716066295
Short name T614
Test name
Test status
Simulation time 346847237 ps
CPU time 7.53 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 218792 kb
Host smart-473e9aa9-69bc-4749-8ea8-6d1b0e8996db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716066295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.716066295
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2718686693
Short name T191
Test name
Test status
Simulation time 336381577 ps
CPU time 13.21 seconds
Started Aug 12 06:46:13 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 218832 kb
Host smart-cc00475f-72e0-437d-8a21-228f842996c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718686693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2718686693
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2938098858
Short name T73
Test name
Test status
Simulation time 17221998 ps
CPU time 1.12 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 214192 kb
Host smart-d335f83f-f20a-4ca9-be5d-31e16292cb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938098858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2938098858
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1177662901
Short name T860
Test name
Test status
Simulation time 295229770 ps
CPU time 33.79 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:41 PM PDT 24
Peak memory 251516 kb
Host smart-d1778d3a-c549-44eb-a5d3-673f442d8c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177662901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1177662901
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1352459541
Short name T647
Test name
Test status
Simulation time 418082434 ps
CPU time 3.42 seconds
Started Aug 12 06:46:06 PM PDT 24
Finished Aug 12 06:46:10 PM PDT 24
Peak memory 226660 kb
Host smart-3e5e1e40-496e-48ce-9269-dbf4c1389435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352459541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1352459541
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3103607986
Short name T691
Test name
Test status
Simulation time 13748111378 ps
CPU time 127.62 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:48:15 PM PDT 24
Peak memory 277372 kb
Host smart-fefeece6-8173-488a-80b6-ec99192a8642
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103607986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3103607986
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1523972954
Short name T365
Test name
Test status
Simulation time 80105562 ps
CPU time 0.93 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:08 PM PDT 24
Peak memory 212512 kb
Host smart-7f8499be-6d31-44a7-b27d-b3184a95dda2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523972954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1523972954
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1589060122
Short name T72
Test name
Test status
Simulation time 21371768 ps
CPU time 0.96 seconds
Started Aug 12 06:46:11 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 209412 kb
Host smart-1530a678-6b9e-4940-9baa-6ee6a2f3be16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589060122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1589060122
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.8754196
Short name T641
Test name
Test status
Simulation time 239586810 ps
CPU time 9.57 seconds
Started Aug 12 06:46:12 PM PDT 24
Finished Aug 12 06:46:22 PM PDT 24
Peak memory 218856 kb
Host smart-b4ee19f9-8ba0-4c6b-91dc-eb613570b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8754196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.8754196
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2578818115
Short name T488
Test name
Test status
Simulation time 321257983 ps
CPU time 4.86 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:14 PM PDT 24
Peak memory 217824 kb
Host smart-0b0dcce9-aa1e-4e82-a17e-299929fbea03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578818115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2578818115
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2995194808
Short name T846
Test name
Test status
Simulation time 88388992 ps
CPU time 2.15 seconds
Started Aug 12 06:46:10 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 222856 kb
Host smart-8b64e87a-380b-4b13-87ff-9e7ca774380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995194808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2995194808
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3670533084
Short name T558
Test name
Test status
Simulation time 668122087 ps
CPU time 9.9 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:18 PM PDT 24
Peak memory 226644 kb
Host smart-4b8c86b6-2147-4afe-9534-02d77b0d50f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670533084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3670533084
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.35585539
Short name T337
Test name
Test status
Simulation time 257655093 ps
CPU time 9.31 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:18 PM PDT 24
Peak memory 218804 kb
Host smart-f8e73052-1444-4ccd-b3fe-0fdaeac3fb50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35585539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.35585539
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.810498305
Short name T556
Test name
Test status
Simulation time 1020342832 ps
CPU time 11.88 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:19 PM PDT 24
Peak memory 218968 kb
Host smart-ea8753c3-139c-4cbb-9730-72d3e821826c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810498305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.810498305
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4125568128
Short name T835
Test name
Test status
Simulation time 66640202 ps
CPU time 1.67 seconds
Started Aug 12 06:46:11 PM PDT 24
Finished Aug 12 06:46:13 PM PDT 24
Peak memory 214596 kb
Host smart-193a6373-a0b3-4711-87e4-d1fab3d68538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125568128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4125568128
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1163140649
Short name T241
Test name
Test status
Simulation time 627929941 ps
CPU time 20.11 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 246112 kb
Host smart-4f2abeff-4b62-4f04-a2f9-45b369dfe1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163140649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1163140649
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2441076797
Short name T215
Test name
Test status
Simulation time 102178300 ps
CPU time 9.7 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:19 PM PDT 24
Peak memory 251496 kb
Host smart-3ee067e4-99fc-496a-910d-f9134969dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441076797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2441076797
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2230729858
Short name T425
Test name
Test status
Simulation time 6465052972 ps
CPU time 122.75 seconds
Started Aug 12 06:46:12 PM PDT 24
Finished Aug 12 06:48:15 PM PDT 24
Peak memory 259744 kb
Host smart-a8977b42-4cc8-4669-a75e-a51d48996aa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230729858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2230729858
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1861442274
Short name T105
Test name
Test status
Simulation time 16857461339 ps
CPU time 61.38 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:47:10 PM PDT 24
Peak memory 268032 kb
Host smart-396f5a05-0623-4299-9aa3-d6afbafe7028
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1861442274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1861442274
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2443252677
Short name T815
Test name
Test status
Simulation time 161515059 ps
CPU time 1.1 seconds
Started Aug 12 06:46:13 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 218304 kb
Host smart-5c29d58f-6233-4df7-873b-cc778e826245
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443252677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2443252677
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3722148257
Short name T259
Test name
Test status
Simulation time 34192707 ps
CPU time 0.9 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:10 PM PDT 24
Peak memory 209504 kb
Host smart-a0bd0ab3-785b-47b3-8e76-a871194309cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722148257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3722148257
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.258627126
Short name T758
Test name
Test status
Simulation time 332002595 ps
CPU time 14.24 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:22 PM PDT 24
Peak memory 218800 kb
Host smart-6e1db917-6e31-47e3-903e-a651b4783f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258627126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.258627126
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3661739898
Short name T675
Test name
Test status
Simulation time 306038829 ps
CPU time 2.69 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 217584 kb
Host smart-257321a5-6256-4bfa-b63e-aac08653574d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661739898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3661739898
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.810776800
Short name T208
Test name
Test status
Simulation time 161168560 ps
CPU time 1.56 seconds
Started Aug 12 06:46:07 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 218848 kb
Host smart-cd19fd80-efde-4e30-bd34-d0f2afe730be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810776800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.810776800
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.609901625
Short name T357
Test name
Test status
Simulation time 241911279 ps
CPU time 11.3 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:20 PM PDT 24
Peak memory 219112 kb
Host smart-2b5a0bff-c897-4025-8f5c-476f6634ce4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609901625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.609901625
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1342855082
Short name T486
Test name
Test status
Simulation time 316409554 ps
CPU time 13.02 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:23 PM PDT 24
Peak memory 226424 kb
Host smart-37cfc0d1-9bd2-403c-b1f1-e89b520f7dcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342855082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1342855082
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4172113746
Short name T443
Test name
Test status
Simulation time 677517444 ps
CPU time 13.18 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:23 PM PDT 24
Peak memory 226604 kb
Host smart-d2b3683e-f139-470c-9ea8-d668cb83f34a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172113746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4172113746
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.57559472
Short name T418
Test name
Test status
Simulation time 839577255 ps
CPU time 6.44 seconds
Started Aug 12 06:46:10 PM PDT 24
Finished Aug 12 06:46:16 PM PDT 24
Peak memory 225424 kb
Host smart-7afa0ba0-461f-4ecb-8024-6ec3743502c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57559472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.57559472
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2708238642
Short name T248
Test name
Test status
Simulation time 225410335 ps
CPU time 2.8 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 215348 kb
Host smart-fa3a337d-f2da-4ece-9e1e-8f45d02c48b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708238642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2708238642
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3526934284
Short name T12
Test name
Test status
Simulation time 427169499 ps
CPU time 16.91 seconds
Started Aug 12 06:46:13 PM PDT 24
Finished Aug 12 06:46:30 PM PDT 24
Peak memory 251484 kb
Host smart-a2bdf039-46ef-42a7-b518-cc943f2d6a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526934284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3526934284
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2041457524
Short name T373
Test name
Test status
Simulation time 71888838 ps
CPU time 6.72 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:15 PM PDT 24
Peak memory 251180 kb
Host smart-f3aff3c5-be00-4a06-b42b-7b75a6dc9c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041457524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2041457524
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2141974034
Short name T223
Test name
Test status
Simulation time 2511274968 ps
CPU time 46.25 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:55 PM PDT 24
Peak memory 251544 kb
Host smart-b8fdc54e-80e5-44ae-a83c-d76f39c4e95e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141974034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2141974034
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3455327589
Short name T366
Test name
Test status
Simulation time 67368759 ps
CPU time 0.85 seconds
Started Aug 12 06:46:11 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 212480 kb
Host smart-17700e6d-84eb-43d9-aee5-1cb22b5370fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455327589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3455327589
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2149830674
Short name T389
Test name
Test status
Simulation time 279204768 ps
CPU time 1.01 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:17 PM PDT 24
Peak memory 209488 kb
Host smart-e3545a98-e5dc-4a15-ba4b-e6fb08a31162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149830674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2149830674
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2381508207
Short name T230
Test name
Test status
Simulation time 1191386022 ps
CPU time 16.03 seconds
Started Aug 12 06:46:11 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 226668 kb
Host smart-0e04e348-34be-4733-8c3a-db127a170ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381508207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2381508207
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.505983371
Short name T745
Test name
Test status
Simulation time 107836945 ps
CPU time 3.02 seconds
Started Aug 12 06:46:13 PM PDT 24
Finished Aug 12 06:46:17 PM PDT 24
Peak memory 217576 kb
Host smart-0122aa8a-65fd-4cce-b315-cb5343f2427b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505983371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.505983371
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2471109287
Short name T318
Test name
Test status
Simulation time 75460471 ps
CPU time 2.29 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 218788 kb
Host smart-d59201cb-bb46-4a99-9848-eacfe38775af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471109287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2471109287
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.919483549
Short name T142
Test name
Test status
Simulation time 296429862 ps
CPU time 14.18 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:40 PM PDT 24
Peak memory 219504 kb
Host smart-bd9c0795-b9b5-43dd-a9cc-2c7579667aa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919483549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.919483549
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1234940585
Short name T627
Test name
Test status
Simulation time 2195300476 ps
CPU time 9.87 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:29 PM PDT 24
Peak memory 226664 kb
Host smart-ff06533f-8aa7-4908-836f-10de51ace6a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234940585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1234940585
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1781035892
Short name T321
Test name
Test status
Simulation time 322402683 ps
CPU time 8.09 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:46:32 PM PDT 24
Peak memory 226616 kb
Host smart-14bcd7c4-a3ca-40f2-b9b8-dc20f25d702a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781035892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1781035892
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.654923416
Short name T386
Test name
Test status
Simulation time 284793334 ps
CPU time 7.33 seconds
Started Aug 12 06:46:13 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 218928 kb
Host smart-187c9bf2-c335-485b-91c8-f894b0028753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654923416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.654923416
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2001546920
Short name T800
Test name
Test status
Simulation time 295759509 ps
CPU time 2.66 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:11 PM PDT 24
Peak memory 217952 kb
Host smart-abf2f615-57b3-4b6f-bd1b-1789eb1ae323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001546920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2001546920
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2063719794
Short name T642
Test name
Test status
Simulation time 259252257 ps
CPU time 24.5 seconds
Started Aug 12 06:46:11 PM PDT 24
Finished Aug 12 06:46:35 PM PDT 24
Peak memory 251488 kb
Host smart-38ca4547-62b5-4e84-ad71-79c23aca77d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063719794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2063719794
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2302865411
Short name T620
Test name
Test status
Simulation time 88339105 ps
CPU time 3.34 seconds
Started Aug 12 06:46:09 PM PDT 24
Finished Aug 12 06:46:12 PM PDT 24
Peak memory 222884 kb
Host smart-1cb9ee40-6209-4c79-9b78-477904ab369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302865411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2302865411
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2089449361
Short name T861
Test name
Test status
Simulation time 1149979109 ps
CPU time 23.25 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 226688 kb
Host smart-17656d57-d6c0-49fa-badb-779c10214797
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089449361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2089449361
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2568772314
Short name T825
Test name
Test status
Simulation time 4480377805 ps
CPU time 54.97 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:47:12 PM PDT 24
Peak memory 251632 kb
Host smart-466b14fd-b807-4f70-8964-ede20487c618
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2568772314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2568772314
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.4003662153
Short name T148
Test name
Test status
Simulation time 46265892 ps
CPU time 0.92 seconds
Started Aug 12 06:46:08 PM PDT 24
Finished Aug 12 06:46:09 PM PDT 24
Peak memory 212448 kb
Host smart-59bf7e74-9e72-445f-a96e-d44b0d4eceb2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003662153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.4003662153
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2591294910
Short name T689
Test name
Test status
Simulation time 12968267 ps
CPU time 1.03 seconds
Started Aug 12 06:46:22 PM PDT 24
Finished Aug 12 06:46:23 PM PDT 24
Peak memory 209488 kb
Host smart-00b6cca9-1db4-447a-a0b3-55c490ff1ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591294910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2591294910
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.357681510
Short name T659
Test name
Test status
Simulation time 1157832448 ps
CPU time 13.43 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:30 PM PDT 24
Peak memory 218864 kb
Host smart-164843d2-6cc6-42ee-9511-9763b3bd855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357681510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.357681510
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.703142156
Short name T664
Test name
Test status
Simulation time 769079836 ps
CPU time 3.07 seconds
Started Aug 12 06:46:22 PM PDT 24
Finished Aug 12 06:46:25 PM PDT 24
Peak memory 217664 kb
Host smart-1612f3c8-44fe-41c7-a944-1d7d8ae0e9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703142156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.703142156
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.4212114971
Short name T245
Test name
Test status
Simulation time 160416944 ps
CPU time 4.08 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 218856 kb
Host smart-c8faa061-114a-4b8c-a09b-a118c71a4e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212114971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.4212114971
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1895073892
Short name T578
Test name
Test status
Simulation time 324944212 ps
CPU time 13.91 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:39 PM PDT 24
Peak memory 219700 kb
Host smart-10d37c1b-fa4a-4a52-aac6-881bb2d685d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895073892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1895073892
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2211075838
Short name T849
Test name
Test status
Simulation time 640964211 ps
CPU time 6.61 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:23 PM PDT 24
Peak memory 226416 kb
Host smart-e85d1f4e-dd03-427f-b1c0-03aa672d6765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211075838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2211075838
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3460140235
Short name T817
Test name
Test status
Simulation time 359659284 ps
CPU time 8.22 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 218772 kb
Host smart-7cf98564-fb63-4b89-a396-e70864fd3b0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460140235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3460140235
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2974909041
Short name T789
Test name
Test status
Simulation time 1249579480 ps
CPU time 8.66 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:28 PM PDT 24
Peak memory 218920 kb
Host smart-8cd7fb58-0c59-43a9-a46f-fab4b2d9cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974909041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2974909041
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.189421025
Short name T293
Test name
Test status
Simulation time 36865548 ps
CPU time 2.32 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 222952 kb
Host smart-19c2d7a0-d5e9-4871-bef1-848554c780ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189421025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.189421025
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.63558948
Short name T42
Test name
Test status
Simulation time 807296532 ps
CPU time 31.46 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:46:49 PM PDT 24
Peak memory 251560 kb
Host smart-473bdf3a-47e5-44b2-9492-1bc7dfe4febf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63558948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.63558948
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3391646189
Short name T805
Test name
Test status
Simulation time 501589351 ps
CPU time 9.15 seconds
Started Aug 12 06:46:15 PM PDT 24
Finished Aug 12 06:46:24 PM PDT 24
Peak memory 250980 kb
Host smart-7b25767b-9be6-43ad-b13c-649dcbe7fe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391646189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3391646189
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4158481761
Short name T445
Test name
Test status
Simulation time 3960718213 ps
CPU time 58.7 seconds
Started Aug 12 06:46:15 PM PDT 24
Finished Aug 12 06:47:14 PM PDT 24
Peak memory 251068 kb
Host smart-9bf542a9-183f-4d9f-aa14-eb7dba28d449
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158481761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4158481761
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1785942878
Short name T613
Test name
Test status
Simulation time 19528864 ps
CPU time 1.04 seconds
Started Aug 12 06:46:20 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 212492 kb
Host smart-4a8f7e1f-37bb-48cb-b0f1-ef410d1f49a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785942878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1785942878
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3169358039
Short name T684
Test name
Test status
Simulation time 42060216 ps
CPU time 0.95 seconds
Started Aug 12 06:46:18 PM PDT 24
Finished Aug 12 06:46:19 PM PDT 24
Peak memory 209400 kb
Host smart-239ab037-03c9-4b96-90c1-6e3031fd8d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169358039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3169358039
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.4078807881
Short name T409
Test name
Test status
Simulation time 275579885 ps
CPU time 8.76 seconds
Started Aug 12 06:46:20 PM PDT 24
Finished Aug 12 06:46:29 PM PDT 24
Peak memory 218848 kb
Host smart-4a6c713d-fa7f-4bed-816d-cfc708453b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078807881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.4078807881
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3239106181
Short name T676
Test name
Test status
Simulation time 79769390 ps
CPU time 1.75 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 217696 kb
Host smart-fc82d377-8a0b-4e3e-b11a-d87101968296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239106181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3239106181
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1439952459
Short name T577
Test name
Test status
Simulation time 162349172 ps
CPU time 2.55 seconds
Started Aug 12 06:46:18 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 222888 kb
Host smart-88b676e4-9a73-4ec8-bb61-0af490f87821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439952459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1439952459
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2299847947
Short name T609
Test name
Test status
Simulation time 657537470 ps
CPU time 7.43 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:26 PM PDT 24
Peak memory 225956 kb
Host smart-6549b88a-cd62-4b24-bdb4-1c1448170ed7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299847947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2299847947
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2908294238
Short name T715
Test name
Test status
Simulation time 418575119 ps
CPU time 8.43 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 226588 kb
Host smart-eda620b3-3ed1-41c3-99bf-75f7b36b6a3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908294238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2908294238
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3405637513
Short name T199
Test name
Test status
Simulation time 629207659 ps
CPU time 11.48 seconds
Started Aug 12 06:46:20 PM PDT 24
Finished Aug 12 06:46:32 PM PDT 24
Peak memory 218816 kb
Host smart-cb027f16-6932-417e-b1d8-082d59276f36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405637513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3405637513
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2963260273
Short name T454
Test name
Test status
Simulation time 491307333 ps
CPU time 11.76 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:46:28 PM PDT 24
Peak memory 226660 kb
Host smart-18ed3a3f-638c-4cfc-92c4-67bed336cca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963260273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2963260273
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.8004576
Short name T85
Test name
Test status
Simulation time 247588621 ps
CPU time 3.2 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:46:20 PM PDT 24
Peak memory 215080 kb
Host smart-f0020f5e-24d9-4b10-af7d-a8cc0d12149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8004576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.8004576
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3793589398
Short name T228
Test name
Test status
Simulation time 1110876590 ps
CPU time 32.31 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:46:49 PM PDT 24
Peak memory 251476 kb
Host smart-393c54ab-7910-467b-ba83-4ebe173d91d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793589398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3793589398
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2724738422
Short name T222
Test name
Test status
Simulation time 92133732 ps
CPU time 6.13 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:25 PM PDT 24
Peak memory 247440 kb
Host smart-c5fe80a3-a448-4b60-a314-07bf829fdb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724738422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2724738422
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2118541045
Short name T786
Test name
Test status
Simulation time 5105837248 ps
CPU time 81.75 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:47:39 PM PDT 24
Peak memory 280612 kb
Host smart-8b0b7b5e-fd6c-4676-b6e8-561dbec62bfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118541045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2118541045
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1363328338
Short name T423
Test name
Test status
Simulation time 16103244 ps
CPU time 0.91 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:17 PM PDT 24
Peak memory 218296 kb
Host smart-1fc6e0d1-b08b-4161-a554-ffc0c8d6d73c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363328338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1363328338
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3547676409
Short name T518
Test name
Test status
Simulation time 31485698 ps
CPU time 0.84 seconds
Started Aug 12 06:44:12 PM PDT 24
Finished Aug 12 06:44:13 PM PDT 24
Peak memory 209252 kb
Host smart-efbcb99d-dcbb-4a2f-9c2f-25d558804762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547676409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3547676409
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2307640111
Short name T188
Test name
Test status
Simulation time 13206479 ps
CPU time 0.82 seconds
Started Aug 12 06:44:09 PM PDT 24
Finished Aug 12 06:44:10 PM PDT 24
Peak memory 209136 kb
Host smart-185f4cd5-794f-42d6-a938-e31ee5776044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307640111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2307640111
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2603751107
Short name T214
Test name
Test status
Simulation time 556541942 ps
CPU time 11.11 seconds
Started Aug 12 06:44:14 PM PDT 24
Finished Aug 12 06:44:26 PM PDT 24
Peak memory 218876 kb
Host smart-8404d72f-28e4-431d-b439-f539d60f362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603751107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2603751107
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3974055027
Short name T65
Test name
Test status
Simulation time 291946251 ps
CPU time 2.72 seconds
Started Aug 12 06:44:13 PM PDT 24
Finished Aug 12 06:44:16 PM PDT 24
Peak memory 217656 kb
Host smart-0e2e07cd-beaa-48d7-b381-53935c4ac49c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974055027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3974055027
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3658073006
Short name T537
Test name
Test status
Simulation time 7019653708 ps
CPU time 58.74 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 219528 kb
Host smart-8caf9a26-a37e-4b2f-981a-2cd621ea210d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658073006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3658073006
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2509870607
Short name T393
Test name
Test status
Simulation time 1204124806 ps
CPU time 13.5 seconds
Started Aug 12 06:44:12 PM PDT 24
Finished Aug 12 06:44:26 PM PDT 24
Peak memory 218272 kb
Host smart-705ed78e-fe4b-41a8-8283-817377eeeb17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509870607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
509870607
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3349478418
Short name T466
Test name
Test status
Simulation time 522846120 ps
CPU time 7.68 seconds
Started Aug 12 06:44:14 PM PDT 24
Finished Aug 12 06:44:22 PM PDT 24
Peak memory 224784 kb
Host smart-b5d574ac-da4b-440c-a552-2275a1d257da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349478418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3349478418
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2598465149
Short name T79
Test name
Test status
Simulation time 4695305962 ps
CPU time 31.69 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:44:43 PM PDT 24
Peak memory 218224 kb
Host smart-9c3f3d31-5ebb-4d74-80ea-647c1675be33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598465149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2598465149
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3650768775
Short name T369
Test name
Test status
Simulation time 285620956 ps
CPU time 2.1 seconds
Started Aug 12 06:44:12 PM PDT 24
Finished Aug 12 06:44:14 PM PDT 24
Peak memory 218148 kb
Host smart-f3f01a6d-fd99-440c-a3e1-0e2997b35f95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650768775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3650768775
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.290809855
Short name T798
Test name
Test status
Simulation time 1404066047 ps
CPU time 56.72 seconds
Started Aug 12 06:44:10 PM PDT 24
Finished Aug 12 06:45:07 PM PDT 24
Peak memory 267820 kb
Host smart-22385775-2505-4173-8609-985e6da7b4ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290809855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.290809855
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2481848583
Short name T226
Test name
Test status
Simulation time 748740644 ps
CPU time 15.78 seconds
Started Aug 12 06:44:10 PM PDT 24
Finished Aug 12 06:44:26 PM PDT 24
Peak memory 250952 kb
Host smart-cefd3365-2621-48ca-af58-caed7a53f181
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481848583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2481848583
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1015979504
Short name T582
Test name
Test status
Simulation time 22061017 ps
CPU time 1.65 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:44:13 PM PDT 24
Peak memory 218868 kb
Host smart-2683026e-8fb4-41dd-b608-7960f213aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015979504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1015979504
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2782822805
Short name T68
Test name
Test status
Simulation time 2136975694 ps
CPU time 21.33 seconds
Started Aug 12 06:44:10 PM PDT 24
Finished Aug 12 06:44:32 PM PDT 24
Peak memory 215284 kb
Host smart-d399ea96-8135-4bfc-beaa-2cf95dccc164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782822805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2782822805
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2881329064
Short name T58
Test name
Test status
Simulation time 204579051 ps
CPU time 40.92 seconds
Started Aug 12 06:44:10 PM PDT 24
Finished Aug 12 06:44:51 PM PDT 24
Peak memory 270684 kb
Host smart-ef2d22d5-67b3-4a61-a1af-742167e2de9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881329064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2881329064
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1838865480
Short name T159
Test name
Test status
Simulation time 257370887 ps
CPU time 9.18 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:44:20 PM PDT 24
Peak memory 219524 kb
Host smart-2e526283-16e4-47c7-9df8-a808c7196b4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838865480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1838865480
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3188583743
Short name T213
Test name
Test status
Simulation time 617646649 ps
CPU time 11.48 seconds
Started Aug 12 06:44:10 PM PDT 24
Finished Aug 12 06:44:21 PM PDT 24
Peak memory 226564 kb
Host smart-69f618c8-9c7c-4ec0-b895-77ec286cca54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188583743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3188583743
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2228142911
Short name T783
Test name
Test status
Simulation time 1049456033 ps
CPU time 6.98 seconds
Started Aug 12 06:44:13 PM PDT 24
Finished Aug 12 06:44:20 PM PDT 24
Peak memory 218792 kb
Host smart-574ff1db-427b-4305-a0f2-984fb25d0ad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228142911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
228142911
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3735847157
Short name T601
Test name
Test status
Simulation time 195602706 ps
CPU time 9.1 seconds
Started Aug 12 06:44:12 PM PDT 24
Finished Aug 12 06:44:22 PM PDT 24
Peak memory 218928 kb
Host smart-ad910ea6-af1b-495a-8149-337be773df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735847157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3735847157
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1239231968
Short name T714
Test name
Test status
Simulation time 110336367 ps
CPU time 1.26 seconds
Started Aug 12 06:44:13 PM PDT 24
Finished Aug 12 06:44:14 PM PDT 24
Peak memory 214208 kb
Host smart-9edfae01-065e-4141-aaba-e5559f364817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239231968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1239231968
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2328377137
Short name T254
Test name
Test status
Simulation time 2587945616 ps
CPU time 22.14 seconds
Started Aug 12 06:44:13 PM PDT 24
Finished Aug 12 06:44:35 PM PDT 24
Peak memory 251456 kb
Host smart-60dcb1b3-eb2a-4986-baba-9c9592019dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328377137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2328377137
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.710883295
Short name T143
Test name
Test status
Simulation time 341123668 ps
CPU time 8.1 seconds
Started Aug 12 06:44:13 PM PDT 24
Finished Aug 12 06:44:21 PM PDT 24
Peak memory 251504 kb
Host smart-18ccfe1b-c334-4d02-a2ed-3f300af6fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710883295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.710883295
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.666010638
Short name T704
Test name
Test status
Simulation time 64747119697 ps
CPU time 129.79 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 282128 kb
Host smart-b6df1509-b7aa-4134-a0e0-615d14515a39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666010638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.666010638
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3263456165
Short name T650
Test name
Test status
Simulation time 2728782101 ps
CPU time 75.72 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:45:27 PM PDT 24
Peak memory 255432 kb
Host smart-a7fa4565-11d1-4920-82ac-700c49a7a29b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3263456165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3263456165
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1340245167
Short name T157
Test name
Test status
Simulation time 68920093 ps
CPU time 0.79 seconds
Started Aug 12 06:44:11 PM PDT 24
Finished Aug 12 06:44:12 PM PDT 24
Peak memory 208740 kb
Host smart-e3835835-bc88-4419-b5de-4054a0c21092
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340245167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1340245167
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.72985369
Short name T733
Test name
Test status
Simulation time 18405911 ps
CPU time 0.87 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 209396 kb
Host smart-21bbd177-2cd1-4043-97fd-cea214162301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72985369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.72985369
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3898970870
Short name T567
Test name
Test status
Simulation time 937833464 ps
CPU time 17.75 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:37 PM PDT 24
Peak memory 226628 kb
Host smart-01b13b75-53d3-4ff3-99ba-b48759e81909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898970870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3898970870
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3538217771
Short name T802
Test name
Test status
Simulation time 1925969554 ps
CPU time 2.41 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:46:20 PM PDT 24
Peak memory 217600 kb
Host smart-bd804975-93d5-41dd-ae32-e299fa397a20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538217771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3538217771
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.4215034807
Short name T384
Test name
Test status
Simulation time 88117279 ps
CPU time 2.07 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:18 PM PDT 24
Peak memory 218860 kb
Host smart-69f9cc16-df5f-4b04-8828-10e049931947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215034807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.4215034807
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.510532454
Short name T737
Test name
Test status
Simulation time 266898938 ps
CPU time 11.62 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:46:31 PM PDT 24
Peak memory 226632 kb
Host smart-c3f776fe-fb86-4fec-82f6-bbe0e577f8c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510532454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.510532454
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1690555639
Short name T812
Test name
Test status
Simulation time 1346344594 ps
CPU time 14.31 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:30 PM PDT 24
Peak memory 226520 kb
Host smart-56ba2055-90ef-4beb-a7b3-1dd3115c77e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690555639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1690555639
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1982996241
Short name T713
Test name
Test status
Simulation time 597535609 ps
CPU time 8.91 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:46:26 PM PDT 24
Peak memory 218756 kb
Host smart-c513b738-984b-4e54-9d2a-3dce0051a5a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982996241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1982996241
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1335267431
Short name T52
Test name
Test status
Simulation time 321670992 ps
CPU time 12.83 seconds
Started Aug 12 06:46:18 PM PDT 24
Finished Aug 12 06:46:31 PM PDT 24
Peak memory 218936 kb
Host smart-ab7f4c3c-4c74-4bb2-94c4-809ced77cc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335267431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1335267431
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2509156554
Short name T13
Test name
Test status
Simulation time 61391277 ps
CPU time 2.12 seconds
Started Aug 12 06:46:17 PM PDT 24
Finished Aug 12 06:46:19 PM PDT 24
Peak memory 218212 kb
Host smart-248c1334-4326-4d4d-8f68-21c4ce5dde92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509156554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2509156554
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3068321655
Short name T554
Test name
Test status
Simulation time 231126486 ps
CPU time 28.39 seconds
Started Aug 12 06:46:16 PM PDT 24
Finished Aug 12 06:46:45 PM PDT 24
Peak memory 251544 kb
Host smart-27272abb-25a0-406d-a4dc-a28a3c9f3528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068321655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3068321655
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2735315759
Short name T95
Test name
Test status
Simulation time 605708367 ps
CPU time 2.85 seconds
Started Aug 12 06:46:18 PM PDT 24
Finished Aug 12 06:46:21 PM PDT 24
Peak memory 223180 kb
Host smart-4f032932-11dd-4eeb-ade6-eb95321be75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735315759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2735315759
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3160331773
Short name T326
Test name
Test status
Simulation time 9429476146 ps
CPU time 169.51 seconds
Started Aug 12 06:46:19 PM PDT 24
Finished Aug 12 06:49:08 PM PDT 24
Peak memory 284192 kb
Host smart-92980115-2fc2-4877-8f5c-3b8910eeec30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160331773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3160331773
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.451744099
Short name T97
Test name
Test status
Simulation time 4452498313 ps
CPU time 49.22 seconds
Started Aug 12 06:46:18 PM PDT 24
Finished Aug 12 06:47:08 PM PDT 24
Peak memory 268116 kb
Host smart-f714ddf1-a91e-4c54-aeb6-26660c33a5db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=451744099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.451744099
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.120316425
Short name T93
Test name
Test status
Simulation time 13883667 ps
CPU time 1.1 seconds
Started Aug 12 06:46:15 PM PDT 24
Finished Aug 12 06:46:16 PM PDT 24
Peak memory 210948 kb
Host smart-bbae6707-8aa4-4b47-b1a5-c7a893d0351d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120316425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.120316425
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2899410489
Short name T404
Test name
Test status
Simulation time 15731878 ps
CPU time 1.08 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:46:29 PM PDT 24
Peak memory 209376 kb
Host smart-f9882bc3-6b6c-4b73-b854-97b390654aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899410489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2899410489
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2530160033
Short name T820
Test name
Test status
Simulation time 1214871594 ps
CPU time 14.61 seconds
Started Aug 12 06:46:27 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 218996 kb
Host smart-e07c57cd-9dd8-48f0-895e-831f407ad03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530160033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2530160033
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1946882124
Short name T828
Test name
Test status
Simulation time 3845687428 ps
CPU time 4.92 seconds
Started Aug 12 06:46:27 PM PDT 24
Finished Aug 12 06:46:32 PM PDT 24
Peak memory 218236 kb
Host smart-c1a7044d-584f-4b52-893a-bceb3a228564
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946882124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1946882124
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.983557802
Short name T773
Test name
Test status
Simulation time 44972194 ps
CPU time 2.2 seconds
Started Aug 12 06:46:30 PM PDT 24
Finished Aug 12 06:46:33 PM PDT 24
Peak memory 222900 kb
Host smart-5b64a63a-40fd-43ae-9186-f9e028da7e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983557802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.983557802
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.574169136
Short name T776
Test name
Test status
Simulation time 829706364 ps
CPU time 12.41 seconds
Started Aug 12 06:46:29 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 219012 kb
Host smart-3b679145-693c-405e-8bca-f9145ac88537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574169136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.574169136
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3871506703
Short name T300
Test name
Test status
Simulation time 922640395 ps
CPU time 8.43 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 226616 kb
Host smart-6e91c59f-11b9-41ac-8d80-5cedd4cf0c4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871506703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3871506703
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1915947083
Short name T626
Test name
Test status
Simulation time 745673354 ps
CPU time 10.2 seconds
Started Aug 12 06:46:23 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 218796 kb
Host smart-54aec82a-f741-460d-a4ac-ec77195c0552
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915947083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1915947083
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.4139843492
Short name T194
Test name
Test status
Simulation time 245478334 ps
CPU time 9.63 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:36 PM PDT 24
Peak memory 226632 kb
Host smart-e343dce8-30df-4eea-83ff-fce1ecc14980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139843492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.4139843492
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3338662117
Short name T279
Test name
Test status
Simulation time 148061102 ps
CPU time 1.98 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:46:30 PM PDT 24
Peak memory 218316 kb
Host smart-bf551a16-11e9-4ca7-a984-c5cf9b2a195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338662117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3338662117
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3119976060
Short name T511
Test name
Test status
Simulation time 278189725 ps
CPU time 23.91 seconds
Started Aug 12 06:46:30 PM PDT 24
Finished Aug 12 06:46:54 PM PDT 24
Peak memory 246120 kb
Host smart-f891ec70-e9c6-45c0-badb-6752d79a8617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119976060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3119976060
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2739010094
Short name T96
Test name
Test status
Simulation time 293609767 ps
CPU time 7.22 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 251460 kb
Host smart-8109b9c7-1b16-4bb7-8fb3-8b020c51e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739010094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2739010094
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2749547124
Short name T66
Test name
Test status
Simulation time 2390673853 ps
CPU time 65.74 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:47:30 PM PDT 24
Peak memory 226708 kb
Host smart-e0b90957-b886-49f8-8b5b-c447f8bebce6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749547124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2749547124
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1450086374
Short name T685
Test name
Test status
Simulation time 38282074 ps
CPU time 0.95 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 212580 kb
Host smart-c554d13d-c0ad-48fc-9237-c10afd2e0582
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450086374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1450086374
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2409525668
Short name T462
Test name
Test status
Simulation time 78440834 ps
CPU time 1.22 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:46:25 PM PDT 24
Peak memory 209564 kb
Host smart-19946960-f2d6-4aa3-a436-56f1a9ef24e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409525668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2409525668
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1569006807
Short name T347
Test name
Test status
Simulation time 427171503 ps
CPU time 17.34 seconds
Started Aug 12 06:46:27 PM PDT 24
Finished Aug 12 06:46:45 PM PDT 24
Peak memory 218868 kb
Host smart-706968f9-7356-4008-b3ee-a0f9617edc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569006807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1569006807
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3649806909
Short name T303
Test name
Test status
Simulation time 5092736931 ps
CPU time 11.39 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:49 PM PDT 24
Peak memory 218276 kb
Host smart-c3339f83-583c-4b41-93b4-69f96236d754
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649806909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3649806909
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1189253845
Short name T311
Test name
Test status
Simulation time 255246992 ps
CPU time 3.16 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:46:32 PM PDT 24
Peak memory 218864 kb
Host smart-25d72570-da2e-4e26-9a08-a888a1820bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189253845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1189253845
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4024870630
Short name T463
Test name
Test status
Simulation time 326968759 ps
CPU time 12.15 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:38 PM PDT 24
Peak memory 226020 kb
Host smart-5eb34011-14ba-4797-80b3-80d1e3aa607b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024870630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4024870630
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.515438261
Short name T702
Test name
Test status
Simulation time 295544701 ps
CPU time 11.37 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:46:39 PM PDT 24
Peak memory 226628 kb
Host smart-6c6523fc-1e02-49ff-b6d9-ce5f282dc2dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515438261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.515438261
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3378559730
Short name T619
Test name
Test status
Simulation time 253611584 ps
CPU time 10.04 seconds
Started Aug 12 06:46:23 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 218796 kb
Host smart-d887b151-e8d1-4ad3-938c-417239f196dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378559730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3378559730
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2842626233
Short name T163
Test name
Test status
Simulation time 529652545 ps
CPU time 7.33 seconds
Started Aug 12 06:46:23 PM PDT 24
Finished Aug 12 06:46:30 PM PDT 24
Peak memory 225692 kb
Host smart-da35a6a4-7077-4666-b806-aff3a57274e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842626233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2842626233
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2534691051
Short name T842
Test name
Test status
Simulation time 243076316 ps
CPU time 4.18 seconds
Started Aug 12 06:46:27 PM PDT 24
Finished Aug 12 06:46:31 PM PDT 24
Peak memory 215656 kb
Host smart-dbe87114-782b-479c-89d4-360056b1500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534691051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2534691051
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1956241850
Short name T493
Test name
Test status
Simulation time 205486397 ps
CPU time 29.36 seconds
Started Aug 12 06:46:30 PM PDT 24
Finished Aug 12 06:47:00 PM PDT 24
Peak memory 251504 kb
Host smart-03700af2-2888-4693-b7a8-d60d23dfa4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956241850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1956241850
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1198268526
Short name T834
Test name
Test status
Simulation time 287796877 ps
CPU time 2.53 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:28 PM PDT 24
Peak memory 222588 kb
Host smart-ba92601f-1fa8-45f5-b5f3-b9b6af2d6326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198268526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1198268526
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1233613266
Short name T250
Test name
Test status
Simulation time 52878786256 ps
CPU time 208.47 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:49:53 PM PDT 24
Peak memory 277180 kb
Host smart-f4b5dea3-0008-43ca-ba76-87bb4f8b43ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233613266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1233613266
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2951536604
Short name T101
Test name
Test status
Simulation time 3896722022 ps
CPU time 107.63 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:48:14 PM PDT 24
Peak memory 276292 kb
Host smart-14f82597-a03c-4552-a2f1-d466f246fdbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2951536604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2951536604
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1702311034
Short name T571
Test name
Test status
Simulation time 14049581 ps
CPU time 1.06 seconds
Started Aug 12 06:46:27 PM PDT 24
Finished Aug 12 06:46:28 PM PDT 24
Peak memory 213676 kb
Host smart-d9cba84d-c515-464a-b170-050318b106c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702311034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1702311034
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1610768021
Short name T74
Test name
Test status
Simulation time 23110239 ps
CPU time 1.37 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 209544 kb
Host smart-9e832f9d-464d-425b-be50-e745eda0aa87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610768021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1610768021
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1038071786
Short name T865
Test name
Test status
Simulation time 745495923 ps
CPU time 12.67 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:39 PM PDT 24
Peak memory 218868 kb
Host smart-f514ae97-2fd4-475d-b090-2871e7808301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038071786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1038071786
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2637157595
Short name T597
Test name
Test status
Simulation time 2728995842 ps
CPU time 13.33 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:39 PM PDT 24
Peak memory 218136 kb
Host smart-87b362ca-fd8a-44da-946a-0377e2efe611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637157595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2637157595
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2951356267
Short name T243
Test name
Test status
Simulation time 68094558 ps
CPU time 3.58 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:30 PM PDT 24
Peak memory 218860 kb
Host smart-25514796-3f18-4075-9528-9bc5e51b3705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951356267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2951356267
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.4040634302
Short name T45
Test name
Test status
Simulation time 737472381 ps
CPU time 13.44 seconds
Started Aug 12 06:46:30 PM PDT 24
Finished Aug 12 06:46:44 PM PDT 24
Peak memory 226592 kb
Host smart-083d8098-bc22-4198-b79a-327a9166178f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040634302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.4040634302
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3047414662
Short name T446
Test name
Test status
Simulation time 372961515 ps
CPU time 11.4 seconds
Started Aug 12 06:46:32 PM PDT 24
Finished Aug 12 06:46:44 PM PDT 24
Peak memory 226628 kb
Host smart-797f7608-ebb6-47d2-b184-b80a1a2d7f08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047414662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3047414662
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.737392406
Short name T491
Test name
Test status
Simulation time 907730205 ps
CPU time 8.82 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 218736 kb
Host smart-77fc8464-afcc-47e1-87d1-02fa9445b841
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737392406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.737392406
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.4172601222
Short name T535
Test name
Test status
Simulation time 372444379 ps
CPU time 14.77 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:46:39 PM PDT 24
Peak memory 218908 kb
Host smart-f484f815-e4dc-456c-9062-9ae86ae9c6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172601222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.4172601222
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1306328234
Short name T15
Test name
Test status
Simulation time 113230006 ps
CPU time 2.11 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:27 PM PDT 24
Peak memory 214540 kb
Host smart-7864c241-7a69-49b9-a435-cbea20e0e260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306328234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1306328234
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.604861537
Short name T482
Test name
Test status
Simulation time 1071711417 ps
CPU time 32.13 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:47:01 PM PDT 24
Peak memory 251504 kb
Host smart-2f5f9654-8c7c-4271-ab5f-4be1a4c16cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604861537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.604861537
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3196790485
Short name T672
Test name
Test status
Simulation time 91301022 ps
CPU time 10.08 seconds
Started Aug 12 06:46:27 PM PDT 24
Finished Aug 12 06:46:37 PM PDT 24
Peak memory 251624 kb
Host smart-6c30f576-b560-42a4-abda-c4feb831d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196790485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3196790485
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.560732217
Short name T444
Test name
Test status
Simulation time 21826791056 ps
CPU time 126.99 seconds
Started Aug 12 06:46:30 PM PDT 24
Finished Aug 12 06:48:37 PM PDT 24
Peak memory 271612 kb
Host smart-5261e404-eddd-4d4b-a6a2-5c6501db118e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560732217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.560732217
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3801363705
Short name T320
Test name
Test status
Simulation time 34714730 ps
CPU time 0.93 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:46:25 PM PDT 24
Peak memory 213520 kb
Host smart-8a04f09a-b2a7-4f2f-8833-a3a2674adfe3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801363705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3801363705
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2837334043
Short name T261
Test name
Test status
Simulation time 20732204 ps
CPU time 1.01 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:36 PM PDT 24
Peak memory 209564 kb
Host smart-84ea955e-88fa-4d79-978b-e88cfd36deef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837334043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2837334043
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2879291381
Short name T546
Test name
Test status
Simulation time 1088886130 ps
CPU time 10.12 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 226664 kb
Host smart-7ef87b90-67f1-49a5-b0e2-fad489b9bd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879291381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2879291381
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1417577855
Short name T291
Test name
Test status
Simulation time 186546242 ps
CPU time 2.63 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:46:31 PM PDT 24
Peak memory 217676 kb
Host smart-c2522f7a-25f6-41ef-a6ac-609fb25e840a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417577855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1417577855
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1335959884
Short name T698
Test name
Test status
Simulation time 286145277 ps
CPU time 3.52 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:29 PM PDT 24
Peak memory 218860 kb
Host smart-1529732d-3ae4-4956-a547-ad4d3dc20afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335959884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1335959884
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2266331747
Short name T260
Test name
Test status
Simulation time 1949166611 ps
CPU time 17.57 seconds
Started Aug 12 06:46:26 PM PDT 24
Finished Aug 12 06:46:44 PM PDT 24
Peak memory 226668 kb
Host smart-651d93a7-4b29-45e2-882e-3fcc366e9148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266331747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2266331747
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2317461296
Short name T442
Test name
Test status
Simulation time 876041533 ps
CPU time 18.32 seconds
Started Aug 12 06:46:30 PM PDT 24
Finished Aug 12 06:46:49 PM PDT 24
Peak memory 226564 kb
Host smart-bb6a0e95-1439-452a-b3ac-704945724d53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317461296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2317461296
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.840546997
Short name T867
Test name
Test status
Simulation time 219006936 ps
CPU time 6.24 seconds
Started Aug 12 06:46:24 PM PDT 24
Finished Aug 12 06:46:31 PM PDT 24
Peak memory 225700 kb
Host smart-fa7df50e-833c-43f0-aadc-f953c0dbf53e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840546997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.840546997
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.782216323
Short name T53
Test name
Test status
Simulation time 434652414 ps
CPU time 16.19 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:41 PM PDT 24
Peak memory 218848 kb
Host smart-6c1f903b-8ca1-4296-9bba-a9e52cc512fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782216323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.782216323
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1639733209
Short name T77
Test name
Test status
Simulation time 38583833 ps
CPU time 2.03 seconds
Started Aug 12 06:46:30 PM PDT 24
Finished Aug 12 06:46:33 PM PDT 24
Peak memory 218232 kb
Host smart-0e5c3ece-177d-400f-9cf0-68bb95959dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639733209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1639733209
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.909275336
Short name T837
Test name
Test status
Simulation time 1150498364 ps
CPU time 33.21 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:47:01 PM PDT 24
Peak memory 251488 kb
Host smart-17ea6d51-726a-45c5-83cf-66c3a327375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909275336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.909275336
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1649017002
Short name T332
Test name
Test status
Simulation time 377916028 ps
CPU time 7.9 seconds
Started Aug 12 06:46:25 PM PDT 24
Finished Aug 12 06:46:33 PM PDT 24
Peak memory 251488 kb
Host smart-ff97a781-facb-46b7-bac4-89ab289f0e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649017002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1649017002
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3601068519
Short name T727
Test name
Test status
Simulation time 3366130605 ps
CPU time 44.59 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:47:23 PM PDT 24
Peak memory 251560 kb
Host smart-b1e7555b-62d9-4466-bbba-d3dbfe892b78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601068519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3601068519
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2134633956
Short name T133
Test name
Test status
Simulation time 3378765831 ps
CPU time 75.38 seconds
Started Aug 12 06:46:40 PM PDT 24
Finished Aug 12 06:47:55 PM PDT 24
Peak memory 272724 kb
Host smart-0b1c673c-0ce8-4cd2-8260-6781024af442
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2134633956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2134633956
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.106464402
Short name T695
Test name
Test status
Simulation time 18562267 ps
CPU time 0.73 seconds
Started Aug 12 06:46:28 PM PDT 24
Finished Aug 12 06:46:29 PM PDT 24
Peak memory 207996 kb
Host smart-4e930681-d981-4dce-9578-cd408f45d33d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106464402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.106464402
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3815801955
Short name T699
Test name
Test status
Simulation time 31079465 ps
CPU time 1.14 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:36 PM PDT 24
Peak memory 209628 kb
Host smart-45014ab7-e6f9-4281-aa6e-a4b378b92a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815801955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3815801955
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1512349280
Short name T360
Test name
Test status
Simulation time 3096215322 ps
CPU time 10.69 seconds
Started Aug 12 06:46:40 PM PDT 24
Finished Aug 12 06:46:51 PM PDT 24
Peak memory 226688 kb
Host smart-23023b80-282b-4d98-ab33-f75c986fae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512349280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1512349280
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2550881330
Short name T34
Test name
Test status
Simulation time 414914773 ps
CPU time 11.6 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:46:51 PM PDT 24
Peak memory 217948 kb
Host smart-d27c976f-dac2-4a1d-80bf-dd0b8983c094
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550881330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2550881330
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.872907161
Short name T625
Test name
Test status
Simulation time 156997109 ps
CPU time 4.35 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:41 PM PDT 24
Peak memory 218892 kb
Host smart-729adbe2-4582-46f8-b4a6-c551883870ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872907161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.872907161
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1330225446
Short name T221
Test name
Test status
Simulation time 213296402 ps
CPU time 11.4 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:50 PM PDT 24
Peak memory 218912 kb
Host smart-db5b628c-0d4c-4806-b8c3-fcafc3373e51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330225446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1330225446
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2610149382
Short name T296
Test name
Test status
Simulation time 854770846 ps
CPU time 9.5 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:48 PM PDT 24
Peak memory 226580 kb
Host smart-557a28f4-829b-4a34-b582-73cb591ffe12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610149382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2610149382
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2259742587
Short name T231
Test name
Test status
Simulation time 355853262 ps
CPU time 10.95 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:47 PM PDT 24
Peak memory 218804 kb
Host smart-8db6d80d-b199-4d02-8ec9-eabe9b562392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259742587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2259742587
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.628921390
Short name T857
Test name
Test status
Simulation time 314827241 ps
CPU time 11.94 seconds
Started Aug 12 06:46:33 PM PDT 24
Finished Aug 12 06:46:45 PM PDT 24
Peak memory 226656 kb
Host smart-ccc2cad2-4565-4d75-a0f1-083beae25045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628921390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.628921390
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2238378363
Short name T325
Test name
Test status
Simulation time 233870958 ps
CPU time 2.58 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:38 PM PDT 24
Peak memory 215064 kb
Host smart-c195b9ac-bff3-45c7-a34f-7564566f622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238378363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2238378363
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1005212774
Short name T584
Test name
Test status
Simulation time 419493692 ps
CPU time 30.26 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:47:09 PM PDT 24
Peak memory 251500 kb
Host smart-cb969d0e-a446-4e55-b790-00e2c2a316a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005212774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1005212774
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3642958880
Short name T516
Test name
Test status
Simulation time 75036892 ps
CPU time 6.22 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:43 PM PDT 24
Peak memory 243260 kb
Host smart-3e5206ed-9558-4a1b-9b31-b680da64bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642958880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3642958880
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3343375505
Short name T490
Test name
Test status
Simulation time 38153352335 ps
CPU time 204.73 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:50:03 PM PDT 24
Peak memory 278820 kb
Host smart-eab8ffdc-8e9d-4836-8d31-1b6a2e4d5cd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343375505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3343375505
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3003614268
Short name T739
Test name
Test status
Simulation time 42500772 ps
CPU time 0.91 seconds
Started Aug 12 06:46:40 PM PDT 24
Finished Aug 12 06:46:41 PM PDT 24
Peak memory 213564 kb
Host smart-8580703e-d275-4464-91ee-c515471131a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003614268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3003614268
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2953652033
Short name T137
Test name
Test status
Simulation time 68170671 ps
CPU time 0.9 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:36 PM PDT 24
Peak memory 209476 kb
Host smart-46c3aa43-df5e-4be2-8f94-0ad558ee0bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953652033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2953652033
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3279969458
Short name T255
Test name
Test status
Simulation time 791641990 ps
CPU time 10.13 seconds
Started Aug 12 06:46:41 PM PDT 24
Finished Aug 12 06:46:51 PM PDT 24
Peak memory 218860 kb
Host smart-063015d4-32a0-48ef-8913-677cc83d9265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279969458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3279969458
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3033471095
Short name T500
Test name
Test status
Simulation time 152706433 ps
CPU time 4.91 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 217732 kb
Host smart-a498225a-308b-4f83-8215-4e0ea9491c0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033471095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3033471095
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2586198487
Short name T680
Test name
Test status
Simulation time 201635771 ps
CPU time 3.84 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 218800 kb
Host smart-b2862b61-c285-4407-8ca9-e4b146f802a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586198487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2586198487
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1074462050
Short name T252
Test name
Test status
Simulation time 726518335 ps
CPU time 11.28 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:47 PM PDT 24
Peak memory 226672 kb
Host smart-943d6a4e-e601-441e-bcc8-6b5ccff8fab4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074462050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1074462050
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4105491048
Short name T203
Test name
Test status
Simulation time 327199523 ps
CPU time 9.42 seconds
Started Aug 12 06:46:33 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 226548 kb
Host smart-e5df2f3b-4f83-44b9-8a40-dd1058113a7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105491048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.4105491048
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3349570540
Short name T575
Test name
Test status
Simulation time 797710610 ps
CPU time 5.89 seconds
Started Aug 12 06:46:41 PM PDT 24
Finished Aug 12 06:46:47 PM PDT 24
Peak memory 226592 kb
Host smart-2b3dbb46-eed5-4cd1-9563-0f783d8ccdd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349570540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3349570540
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1852680105
Short name T813
Test name
Test status
Simulation time 1195130372 ps
CPU time 14.91 seconds
Started Aug 12 06:46:40 PM PDT 24
Finished Aug 12 06:46:55 PM PDT 24
Peak memory 218900 kb
Host smart-9c58fe1d-2e2f-48a7-bb53-f0d95bdf8506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852680105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1852680105
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4174997257
Short name T555
Test name
Test status
Simulation time 78965430 ps
CPU time 2.52 seconds
Started Aug 12 06:46:41 PM PDT 24
Finished Aug 12 06:46:44 PM PDT 24
Peak memory 218212 kb
Host smart-7bb49764-983a-4b6d-a2d8-8968dbe48445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174997257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4174997257
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1111157623
Short name T540
Test name
Test status
Simulation time 165399641 ps
CPU time 24.08 seconds
Started Aug 12 06:46:34 PM PDT 24
Finished Aug 12 06:46:58 PM PDT 24
Peak memory 251536 kb
Host smart-0ee54f00-bf8b-4623-b836-f688cfcf1126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111157623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1111157623
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2369248820
Short name T225
Test name
Test status
Simulation time 113865983 ps
CPU time 4.23 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:40 PM PDT 24
Peak memory 226952 kb
Host smart-ced1d4ed-bd09-4510-9a13-832915dc18d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369248820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2369248820
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1716730075
Short name T276
Test name
Test status
Simulation time 9251342057 ps
CPU time 56.59 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:47:36 PM PDT 24
Peak memory 250984 kb
Host smart-26705571-7c7b-4d4b-afb8-2d12051a776c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716730075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1716730075
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3797837983
Short name T528
Test name
Test status
Simulation time 1382114501 ps
CPU time 31.43 seconds
Started Aug 12 06:46:42 PM PDT 24
Finished Aug 12 06:47:14 PM PDT 24
Peak memory 251576 kb
Host smart-df0ffdfa-104e-4716-a5f4-49617cae7ff0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3797837983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3797837983
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2350129566
Short name T747
Test name
Test status
Simulation time 12656161 ps
CPU time 1.01 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:38 PM PDT 24
Peak memory 212492 kb
Host smart-9a1ec3a7-e37c-4667-8ff4-c7e652e99be2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350129566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2350129566
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.4085981231
Short name T576
Test name
Test status
Simulation time 21378404 ps
CPU time 1.23 seconds
Started Aug 12 06:46:41 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 209544 kb
Host smart-70822341-94ba-44d3-a8f1-94430c49ec1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085981231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4085981231
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.560337002
Short name T256
Test name
Test status
Simulation time 747510418 ps
CPU time 18.79 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:57 PM PDT 24
Peak memory 226676 kb
Host smart-6f5fbbd2-d4c2-474e-8381-53fedd59f036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560337002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.560337002
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2880537124
Short name T35
Test name
Test status
Simulation time 1440566965 ps
CPU time 9.29 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:45 PM PDT 24
Peak memory 217812 kb
Host smart-ee5dbc05-528c-4e27-becc-933467c8353c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880537124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2880537124
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1558430472
Short name T314
Test name
Test status
Simulation time 121949560 ps
CPU time 2.63 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:41 PM PDT 24
Peak memory 218988 kb
Host smart-a19d8fb1-22d8-40e0-9bea-bbf0c2c5aeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558430472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1558430472
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2592437186
Short name T464
Test name
Test status
Simulation time 920402931 ps
CPU time 11.89 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:48 PM PDT 24
Peak memory 226668 kb
Host smart-2f0d41fb-035f-4692-882b-223b67231f00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592437186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2592437186
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1142022263
Short name T370
Test name
Test status
Simulation time 1195068118 ps
CPU time 10 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:47 PM PDT 24
Peak memory 226580 kb
Host smart-72e02e63-b9cf-4a90-9b7c-c0f9cea85e1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142022263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1142022263
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1052800012
Short name T372
Test name
Test status
Simulation time 2513361537 ps
CPU time 21.62 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:59 PM PDT 24
Peak memory 226608 kb
Host smart-3b731479-3f51-4517-b292-71576eb3821d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052800012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1052800012
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.589404451
Short name T449
Test name
Test status
Simulation time 656534578 ps
CPU time 9.75 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:48 PM PDT 24
Peak memory 226664 kb
Host smart-da1f0d3e-010b-495b-bd90-8e895d8021fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589404451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.589404451
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3714264872
Short name T615
Test name
Test status
Simulation time 35649831 ps
CPU time 1.65 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:40 PM PDT 24
Peak memory 214564 kb
Host smart-e4c4bca4-8830-4e06-bb7c-1eedfc386a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714264872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3714264872
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1752128795
Short name T36
Test name
Test status
Simulation time 192554169 ps
CPU time 26.91 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:47:05 PM PDT 24
Peak memory 251512 kb
Host smart-4db0c448-20e4-403f-8d09-1f5467accb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752128795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1752128795
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2157529642
Short name T219
Test name
Test status
Simulation time 48281967 ps
CPU time 6.63 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:43 PM PDT 24
Peak memory 250912 kb
Host smart-6d865b35-8a93-493a-ab82-949b8107b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157529642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2157529642
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.688936411
Short name T801
Test name
Test status
Simulation time 10199787163 ps
CPU time 377.29 seconds
Started Aug 12 06:46:40 PM PDT 24
Finished Aug 12 06:52:57 PM PDT 24
Peak memory 279052 kb
Host smart-af1dc6b8-5b55-4de0-b011-feb0c4747a32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688936411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.688936411
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1681591791
Short name T738
Test name
Test status
Simulation time 1604779172 ps
CPU time 41.27 seconds
Started Aug 12 06:46:34 PM PDT 24
Finished Aug 12 06:47:15 PM PDT 24
Peak memory 276216 kb
Host smart-3ab30e7e-27c9-4e81-8661-1a9100c30c8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1681591791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1681591791
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.498568375
Short name T234
Test name
Test status
Simulation time 46476076 ps
CPU time 1.01 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:38 PM PDT 24
Peak memory 212580 kb
Host smart-fb155182-79b9-483d-af17-48a75bb59e66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498568375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.498568375
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.722226237
Short name T716
Test name
Test status
Simulation time 74564916 ps
CPU time 1.18 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:39 PM PDT 24
Peak memory 209596 kb
Host smart-85a07c7c-6b20-4bff-84fa-7aa44901a231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722226237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.722226237
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.4257064933
Short name T669
Test name
Test status
Simulation time 478485433 ps
CPU time 5.66 seconds
Started Aug 12 06:46:40 PM PDT 24
Finished Aug 12 06:46:46 PM PDT 24
Peak memory 217640 kb
Host smart-94008494-87ca-4937-a872-a2a52332a316
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257064933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4257064933
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3770135743
Short name T269
Test name
Test status
Simulation time 262494001 ps
CPU time 2.63 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:39 PM PDT 24
Peak memory 218852 kb
Host smart-6467a234-9019-483d-817b-a5ce04c28023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770135743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3770135743
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3868979180
Short name T771
Test name
Test status
Simulation time 1828134757 ps
CPU time 13.95 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:49 PM PDT 24
Peak memory 226644 kb
Host smart-b50413fa-2f77-4586-b770-8954eb51712d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868979180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3868979180
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1774003520
Short name T557
Test name
Test status
Simulation time 1774659731 ps
CPU time 12.17 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:46:51 PM PDT 24
Peak memory 226608 kb
Host smart-4dda6c16-6301-485b-9013-160788f5b473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774003520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1774003520
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3371486564
Short name T496
Test name
Test status
Simulation time 598546613 ps
CPU time 8.28 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:43 PM PDT 24
Peak memory 218768 kb
Host smart-5b533f7e-3257-4809-8623-6e683727e6ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371486564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3371486564
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2853432208
Short name T364
Test name
Test status
Simulation time 383951064 ps
CPU time 8.88 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:44 PM PDT 24
Peak memory 225976 kb
Host smart-a4da12b6-93c5-4033-8bbc-edf749237081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853432208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2853432208
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3987233744
Short name T509
Test name
Test status
Simulation time 271308996 ps
CPU time 1.87 seconds
Started Aug 12 06:46:35 PM PDT 24
Finished Aug 12 06:46:37 PM PDT 24
Peak memory 213780 kb
Host smart-c4cee343-9361-4703-b92b-c8364e703c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987233744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3987233744
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1203224728
Short name T484
Test name
Test status
Simulation time 222215766 ps
CPU time 29.86 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:47:09 PM PDT 24
Peak memory 251488 kb
Host smart-040f58bd-4fd1-4acd-af5f-516ef47135b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203224728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1203224728
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.4265153514
Short name T440
Test name
Test status
Simulation time 268377491 ps
CPU time 5.92 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:46:43 PM PDT 24
Peak memory 247424 kb
Host smart-5dd4438c-b41d-4d1e-b121-08ca2caeed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265153514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.4265153514
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1505805967
Short name T379
Test name
Test status
Simulation time 4095638851 ps
CPU time 72.67 seconds
Started Aug 12 06:46:37 PM PDT 24
Finished Aug 12 06:47:50 PM PDT 24
Peak memory 251716 kb
Host smart-c06b4f5e-badd-430d-9680-b66b32cdfbac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505805967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1505805967
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1313914454
Short name T769
Test name
Test status
Simulation time 3117484165 ps
CPU time 20.03 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:47:00 PM PDT 24
Peak memory 226312 kb
Host smart-42c50627-0444-4a5e-b935-eed3bca54fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1313914454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1313914454
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2710999322
Short name T624
Test name
Test status
Simulation time 43070568 ps
CPU time 0.85 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:37 PM PDT 24
Peak memory 212520 kb
Host smart-574c7190-4eab-495a-b30c-6bc1c896ce5f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710999322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2710999322
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1893632160
Short name T831
Test name
Test status
Simulation time 48666767 ps
CPU time 1.04 seconds
Started Aug 12 06:46:44 PM PDT 24
Finished Aug 12 06:46:45 PM PDT 24
Peak memory 209548 kb
Host smart-59d95568-6465-497a-ad43-0341f52c49fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893632160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1893632160
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2148120615
Short name T508
Test name
Test status
Simulation time 236134104 ps
CPU time 10.76 seconds
Started Aug 12 06:46:42 PM PDT 24
Finished Aug 12 06:46:53 PM PDT 24
Peak memory 218820 kb
Host smart-9bc0b509-3008-4597-ac0e-efdd65a2a848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148120615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2148120615
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.580181877
Short name T843
Test name
Test status
Simulation time 109246478 ps
CPU time 3.57 seconds
Started Aug 12 06:46:38 PM PDT 24
Finished Aug 12 06:46:42 PM PDT 24
Peak memory 218164 kb
Host smart-9b557db1-66cf-46e9-bf98-eedb23657e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580181877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.580181877
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.255076533
Short name T470
Test name
Test status
Simulation time 146809511 ps
CPU time 1.5 seconds
Started Aug 12 06:46:34 PM PDT 24
Finished Aug 12 06:46:35 PM PDT 24
Peak memory 222456 kb
Host smart-a592ddb4-cd17-4ca4-9f39-453acb4ed195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255076533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.255076533
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3115309590
Short name T674
Test name
Test status
Simulation time 4232766724 ps
CPU time 9.56 seconds
Started Aug 12 06:46:43 PM PDT 24
Finished Aug 12 06:46:53 PM PDT 24
Peak memory 226776 kb
Host smart-67a226bb-716b-41bf-8114-caa8c6893a5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115309590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3115309590
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3464630065
Short name T310
Test name
Test status
Simulation time 453642626 ps
CPU time 10.37 seconds
Started Aug 12 06:46:45 PM PDT 24
Finished Aug 12 06:46:56 PM PDT 24
Peak memory 226584 kb
Host smart-d7a08728-c409-4da6-b58c-97a44d58223f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464630065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3464630065
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.602549164
Short name T51
Test name
Test status
Simulation time 751548470 ps
CPU time 23.16 seconds
Started Aug 12 06:46:44 PM PDT 24
Finished Aug 12 06:47:07 PM PDT 24
Peak memory 218772 kb
Host smart-a3bfe1d5-9f97-46c6-8548-0155987ffcff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602549164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.602549164
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2703561977
Short name T407
Test name
Test status
Simulation time 1481203853 ps
CPU time 7.84 seconds
Started Aug 12 06:46:39 PM PDT 24
Finished Aug 12 06:46:47 PM PDT 24
Peak memory 226632 kb
Host smart-ba9fb601-72ef-4d8f-8ee1-d45e8eab9bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703561977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2703561977
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.434751399
Short name T566
Test name
Test status
Simulation time 949427256 ps
CPU time 13.74 seconds
Started Aug 12 06:46:33 PM PDT 24
Finished Aug 12 06:46:47 PM PDT 24
Peak memory 218220 kb
Host smart-b49b2711-3ad2-4136-ab93-762b301346b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434751399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.434751399
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1721672162
Short name T158
Test name
Test status
Simulation time 737653931 ps
CPU time 21.98 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:58 PM PDT 24
Peak memory 251508 kb
Host smart-7334f5b6-4378-460b-abba-2bb29fdf1379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721672162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1721672162
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3942715642
Short name T603
Test name
Test status
Simulation time 446521263 ps
CPU time 3.96 seconds
Started Aug 12 06:46:40 PM PDT 24
Finished Aug 12 06:46:44 PM PDT 24
Peak memory 223344 kb
Host smart-593add57-7918-4aa4-9e83-43a1ffe71d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942715642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3942715642
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2370863329
Short name T76
Test name
Test status
Simulation time 5105154183 ps
CPU time 49.08 seconds
Started Aug 12 06:46:43 PM PDT 24
Finished Aug 12 06:47:32 PM PDT 24
Peak memory 226676 kb
Host smart-91d0f0d9-b6c3-4363-94f2-97b1237e9f62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370863329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2370863329
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2596041043
Short name T344
Test name
Test status
Simulation time 135389481 ps
CPU time 0.9 seconds
Started Aug 12 06:46:36 PM PDT 24
Finished Aug 12 06:46:37 PM PDT 24
Peak memory 212472 kb
Host smart-2a256ea8-3e45-448d-9a20-5daf2c54ffe1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596041043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2596041043
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2183492628
Short name T547
Test name
Test status
Simulation time 13223313 ps
CPU time 1.01 seconds
Started Aug 12 06:44:25 PM PDT 24
Finished Aug 12 06:44:26 PM PDT 24
Peak memory 209528 kb
Host smart-32db5962-9146-4e26-b438-12db8a1ca454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183492628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2183492628
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2275151779
Short name T212
Test name
Test status
Simulation time 14574230 ps
CPU time 0.99 seconds
Started Aug 12 06:44:24 PM PDT 24
Finished Aug 12 06:44:25 PM PDT 24
Peak memory 209356 kb
Host smart-ea48c76d-9042-48b6-8a62-f5aa6018b6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275151779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2275151779
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3807289325
Short name T209
Test name
Test status
Simulation time 5042492342 ps
CPU time 11.95 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:32 PM PDT 24
Peak memory 219076 kb
Host smart-0fbb4da3-81d1-4032-914f-c9670d2ee586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807289325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3807289325
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2885662926
Short name T720
Test name
Test status
Simulation time 5961933460 ps
CPU time 5.14 seconds
Started Aug 12 06:44:22 PM PDT 24
Finished Aug 12 06:44:27 PM PDT 24
Peak memory 218080 kb
Host smart-72c94881-1e8e-499e-8a9a-31c7abf29040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885662926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2885662926
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2706636887
Short name T585
Test name
Test status
Simulation time 6505234433 ps
CPU time 25.7 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 219472 kb
Host smart-c7fe5467-c330-4296-bc17-ffc68a29123a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706636887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2706636887
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3961034781
Short name T264
Test name
Test status
Simulation time 7646100747 ps
CPU time 44.67 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:45:05 PM PDT 24
Peak memory 218348 kb
Host smart-5178b4cc-7602-480f-9f56-e14d7cffa9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961034781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
961034781
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3349637804
Short name T451
Test name
Test status
Simulation time 1852980082 ps
CPU time 12.18 seconds
Started Aug 12 06:44:18 PM PDT 24
Finished Aug 12 06:44:31 PM PDT 24
Peak memory 224916 kb
Host smart-15da27e5-a0fa-4d32-97e0-0b5405887676
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349637804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3349637804
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.883089453
Short name T43
Test name
Test status
Simulation time 918690255 ps
CPU time 27.06 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:47 PM PDT 24
Peak memory 218160 kb
Host smart-68b0a024-9f3c-485d-b578-0ac78fff7dea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883089453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.883089453
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1461484097
Short name T367
Test name
Test status
Simulation time 255532134 ps
CPU time 1.4 seconds
Started Aug 12 06:44:21 PM PDT 24
Finished Aug 12 06:44:23 PM PDT 24
Peak memory 218116 kb
Host smart-ff23cdc3-1031-4cca-b4cd-205bc4b4b2b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461484097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1461484097
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.739255915
Short name T433
Test name
Test status
Simulation time 3155246194 ps
CPU time 105.57 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:46:05 PM PDT 24
Peak memory 284064 kb
Host smart-ecbcaf43-daab-4d86-9fc8-de5cdc2edb10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739255915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.739255915
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2045226488
Short name T160
Test name
Test status
Simulation time 1368539081 ps
CPU time 7.55 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:28 PM PDT 24
Peak memory 222516 kb
Host smart-f5c67ddf-c0bd-4153-a18e-e54e1dc80cdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045226488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2045226488
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3460050459
Short name T361
Test name
Test status
Simulation time 99259260 ps
CPU time 2.32 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:23 PM PDT 24
Peak memory 218408 kb
Host smart-b31b680f-1fc2-4439-9029-751264ab04fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460050459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3460050459
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.286696925
Short name T10
Test name
Test status
Simulation time 1218502203 ps
CPU time 8.6 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:28 PM PDT 24
Peak memory 218304 kb
Host smart-023fbdd0-9cc0-4280-b859-e4fe3cd01092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286696925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.286696925
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.684973023
Short name T317
Test name
Test status
Simulation time 2674389106 ps
CPU time 12.21 seconds
Started Aug 12 06:44:18 PM PDT 24
Finished Aug 12 06:44:30 PM PDT 24
Peak memory 226700 kb
Host smart-9456aef7-6473-41d1-9454-f809babf863b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684973023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.684973023
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3943630525
Short name T694
Test name
Test status
Simulation time 1314076986 ps
CPU time 9.52 seconds
Started Aug 12 06:44:22 PM PDT 24
Finished Aug 12 06:44:31 PM PDT 24
Peak memory 226600 kb
Host smart-dc787d55-202b-4a85-b57d-516f809839c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943630525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
943630525
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4146163802
Short name T662
Test name
Test status
Simulation time 1082645440 ps
CPU time 9.98 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:30 PM PDT 24
Peak memory 226680 kb
Host smart-f8d28849-f058-40e4-90ff-5d889e530094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146163802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4146163802
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4223326786
Short name T64
Test name
Test status
Simulation time 52694950 ps
CPU time 2.51 seconds
Started Aug 12 06:44:21 PM PDT 24
Finished Aug 12 06:44:24 PM PDT 24
Peak memory 214668 kb
Host smart-e66af626-81e6-407f-8e1b-3359397447da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223326786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4223326786
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2062063750
Short name T788
Test name
Test status
Simulation time 398062407 ps
CPU time 21 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:41 PM PDT 24
Peak memory 251568 kb
Host smart-84376fbf-ea9c-4c6b-964f-d10bb655bf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062063750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2062063750
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.113891120
Short name T792
Test name
Test status
Simulation time 57143481 ps
CPU time 6.56 seconds
Started Aug 12 06:44:22 PM PDT 24
Finished Aug 12 06:44:28 PM PDT 24
Peak memory 245324 kb
Host smart-2297ba65-d0d4-4cce-a99f-50877d0cbda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113891120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.113891120
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.233285704
Short name T102
Test name
Test status
Simulation time 3457373964 ps
CPU time 128.08 seconds
Started Aug 12 06:44:22 PM PDT 24
Finished Aug 12 06:46:30 PM PDT 24
Peak memory 268028 kb
Host smart-2a1ae62b-1bb2-43d5-b674-de814653a55e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=233285704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.233285704
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2151976832
Short name T728
Test name
Test status
Simulation time 37269263 ps
CPU time 0.86 seconds
Started Aug 12 06:44:19 PM PDT 24
Finished Aug 12 06:44:20 PM PDT 24
Peak memory 212568 kb
Host smart-351c4575-546d-4aa6-a4cf-76bffbbae63d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151976832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2151976832
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.278422685
Short name T432
Test name
Test status
Simulation time 49032425 ps
CPU time 0.86 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:31 PM PDT 24
Peak memory 209256 kb
Host smart-f44e3906-6836-457b-a903-d790e84070e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278422685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.278422685
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.79966076
Short name T794
Test name
Test status
Simulation time 387621685 ps
CPU time 12.79 seconds
Started Aug 12 06:44:22 PM PDT 24
Finished Aug 12 06:44:35 PM PDT 24
Peak memory 218860 kb
Host smart-a7ec8539-2f42-4b94-a6f3-9ad9a2cd5c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79966076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.79966076
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3100462258
Short name T552
Test name
Test status
Simulation time 265826963 ps
CPU time 1.93 seconds
Started Aug 12 06:44:27 PM PDT 24
Finished Aug 12 06:44:29 PM PDT 24
Peak memory 217552 kb
Host smart-329c34d0-5a47-4ce3-8cd5-ffad85a78cc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100462258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3100462258
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1017960586
Short name T240
Test name
Test status
Simulation time 11253800429 ps
CPU time 35.08 seconds
Started Aug 12 06:44:27 PM PDT 24
Finished Aug 12 06:45:03 PM PDT 24
Peak memory 219460 kb
Host smart-48194595-86e2-45f5-bb29-e8f9206d3e30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017960586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1017960586
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1121536757
Short name T652
Test name
Test status
Simulation time 4528225206 ps
CPU time 13.08 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:44:45 PM PDT 24
Peak memory 218360 kb
Host smart-c76833e2-c1ab-4895-be53-34878accc303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121536757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
121536757
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1192987210
Short name T731
Test name
Test status
Simulation time 375900816 ps
CPU time 7.56 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:27 PM PDT 24
Peak memory 218828 kb
Host smart-b8d327c7-3722-4596-a756-736f609a9dd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192987210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1192987210
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3103209458
Short name T693
Test name
Test status
Simulation time 4854093804 ps
CPU time 23.64 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:54 PM PDT 24
Peak memory 218252 kb
Host smart-5c1a8bb0-c1e3-4ca9-992d-46965ee44ca6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103209458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3103209458
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2489868903
Short name T580
Test name
Test status
Simulation time 422059703 ps
CPU time 5.29 seconds
Started Aug 12 06:44:22 PM PDT 24
Finished Aug 12 06:44:27 PM PDT 24
Peak memory 218116 kb
Host smart-60e07ae0-858d-40f4-bc5f-4b00c2050e9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489868903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2489868903
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3649574308
Short name T258
Test name
Test status
Simulation time 5272720775 ps
CPU time 42.54 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:45:02 PM PDT 24
Peak memory 268180 kb
Host smart-6a364f5c-6fb0-4533-bd9d-3ca1f75806fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649574308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3649574308
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1300337469
Short name T587
Test name
Test status
Simulation time 805199755 ps
CPU time 26.48 seconds
Started Aug 12 06:44:22 PM PDT 24
Finished Aug 12 06:44:49 PM PDT 24
Peak memory 249156 kb
Host smart-f7a23501-2e88-4bea-990c-e657f2927330
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300337469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1300337469
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1257311341
Short name T224
Test name
Test status
Simulation time 135541949 ps
CPU time 2.09 seconds
Started Aug 12 06:44:21 PM PDT 24
Finished Aug 12 06:44:23 PM PDT 24
Peak memory 222776 kb
Host smart-2da384b4-938b-409e-930e-a65510397ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257311341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1257311341
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.283113267
Short name T388
Test name
Test status
Simulation time 233110135 ps
CPU time 6.62 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:27 PM PDT 24
Peak memory 214520 kb
Host smart-8ff682d6-b9af-4156-a960-510a88228b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283113267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.283113267
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4281199822
Short name T286
Test name
Test status
Simulation time 1376210939 ps
CPU time 12.81 seconds
Started Aug 12 06:44:29 PM PDT 24
Finished Aug 12 06:44:42 PM PDT 24
Peak memory 226664 kb
Host smart-215050d3-efdc-402d-bd1e-b3c0bee0dfa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281199822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4281199822
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1942210637
Short name T795
Test name
Test status
Simulation time 854302641 ps
CPU time 13.17 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:44:45 PM PDT 24
Peak memory 226624 kb
Host smart-3fed8ad0-c6e0-4c49-b927-59f9b523e25a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942210637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1942210637
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1185237331
Short name T534
Test name
Test status
Simulation time 324844014 ps
CPU time 9.41 seconds
Started Aug 12 06:44:28 PM PDT 24
Finished Aug 12 06:44:38 PM PDT 24
Peak memory 226600 kb
Host smart-74be0b80-b49d-4cd4-a5d8-cfd9baec736c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185237331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
185237331
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3597679094
Short name T270
Test name
Test status
Simulation time 5154133276 ps
CPU time 8.36 seconds
Started Aug 12 06:44:21 PM PDT 24
Finished Aug 12 06:44:29 PM PDT 24
Peak memory 226732 kb
Host smart-de5012a2-2e6a-40bd-8f31-285000c72fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597679094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3597679094
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4108033075
Short name T327
Test name
Test status
Simulation time 201995617 ps
CPU time 3.29 seconds
Started Aug 12 06:44:19 PM PDT 24
Finished Aug 12 06:44:23 PM PDT 24
Peak memory 218184 kb
Host smart-224ec42b-0950-4ff2-ad0f-6cbc067b9d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108033075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4108033075
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1773476396
Short name T156
Test name
Test status
Simulation time 260258681 ps
CPU time 24.25 seconds
Started Aug 12 06:44:20 PM PDT 24
Finished Aug 12 06:44:44 PM PDT 24
Peak memory 245840 kb
Host smart-96de278a-0330-4824-9977-251e093d6cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773476396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1773476396
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2547447091
Short name T196
Test name
Test status
Simulation time 414156712 ps
CPU time 3.66 seconds
Started Aug 12 06:44:24 PM PDT 24
Finished Aug 12 06:44:28 PM PDT 24
Peak memory 223188 kb
Host smart-925a769b-b704-42dd-8f46-822d91a21c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547447091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2547447091
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1437928346
Short name T856
Test name
Test status
Simulation time 13209436613 ps
CPU time 124.41 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:46:34 PM PDT 24
Peak memory 267940 kb
Host smart-84e5518e-07e7-4c63-b38e-ba2d15253347
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437928346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1437928346
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3605578930
Short name T594
Test name
Test status
Simulation time 127816047 ps
CPU time 0.81 seconds
Started Aug 12 06:44:19 PM PDT 24
Finished Aug 12 06:44:20 PM PDT 24
Peak memory 212500 kb
Host smart-918e7f0b-eeda-4d2c-b826-430b9c2aca76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605578930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3605578930
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.704951720
Short name T87
Test name
Test status
Simulation time 23659007 ps
CPU time 0.95 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:44:33 PM PDT 24
Peak memory 209444 kb
Host smart-89e76c3f-6be0-4bd5-9de7-fcc8f1afcd1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704951720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.704951720
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3220246099
Short name T319
Test name
Test status
Simulation time 1191454625 ps
CPU time 19.41 seconds
Started Aug 12 06:44:28 PM PDT 24
Finished Aug 12 06:44:47 PM PDT 24
Peak memory 226792 kb
Host smart-0b3ec14d-64ff-423e-b828-24970378d1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220246099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3220246099
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2670026223
Short name T553
Test name
Test status
Simulation time 1334383796 ps
CPU time 5.15 seconds
Started Aug 12 06:44:28 PM PDT 24
Finished Aug 12 06:44:34 PM PDT 24
Peak memory 217912 kb
Host smart-ef4c68c4-586e-477b-9560-223ae6b141ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670026223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2670026223
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2212902135
Short name T649
Test name
Test status
Simulation time 55496216888 ps
CPU time 134.95 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:46:47 PM PDT 24
Peak memory 218880 kb
Host smart-e290bc7d-b134-4373-84ac-6f7a8822a033
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212902135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2212902135
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2620743523
Short name T505
Test name
Test status
Simulation time 220177135 ps
CPU time 3.21 seconds
Started Aug 12 06:44:33 PM PDT 24
Finished Aug 12 06:44:36 PM PDT 24
Peak memory 218228 kb
Host smart-a7b71df7-ff90-46b8-ba55-08b551e23037
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620743523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
620743523
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2610038355
Short name T690
Test name
Test status
Simulation time 568235847 ps
CPU time 15.46 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 218808 kb
Host smart-d4e836d3-beff-444b-a27f-4aa0281289a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610038355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2610038355
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3611683771
Short name T753
Test name
Test status
Simulation time 1273196428 ps
CPU time 20.13 seconds
Started Aug 12 06:44:28 PM PDT 24
Finished Aug 12 06:44:49 PM PDT 24
Peak memory 218148 kb
Host smart-0ed82876-2f0c-4d38-90f2-d2924c2d7f40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611683771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3611683771
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3374069807
Short name T80
Test name
Test status
Simulation time 310296109 ps
CPU time 4.87 seconds
Started Aug 12 06:44:29 PM PDT 24
Finished Aug 12 06:44:34 PM PDT 24
Peak memory 218120 kb
Host smart-4ba04a45-91aa-48df-a5d4-b2eb5488b350
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374069807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3374069807
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2593073738
Short name T253
Test name
Test status
Simulation time 1236333806 ps
CPU time 52.15 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:45:24 PM PDT 24
Peak memory 251520 kb
Host smart-29ff8990-c34d-4d27-92a9-4e7afb1489aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593073738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2593073738
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.620433928
Short name T141
Test name
Test status
Simulation time 375546808 ps
CPU time 10.83 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:44:43 PM PDT 24
Peak memory 250972 kb
Host smart-098c852b-6e0a-44b7-92d3-182b4cda2568
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620433928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.620433928
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.134858022
Short name T353
Test name
Test status
Simulation time 205273754 ps
CPU time 3.39 seconds
Started Aug 12 06:44:33 PM PDT 24
Finished Aug 12 06:44:36 PM PDT 24
Peak memory 223124 kb
Host smart-88e5d839-5ee1-41f5-b1b5-b59dfaa62647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134858022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.134858022
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.9275543
Short name T756
Test name
Test status
Simulation time 1275970399 ps
CPU time 20.37 seconds
Started Aug 12 06:44:33 PM PDT 24
Finished Aug 12 06:44:53 PM PDT 24
Peak memory 223652 kb
Host smart-c5454502-7c20-48c2-a646-c9db1749ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9275543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.9275543
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1218288410
Short name T227
Test name
Test status
Simulation time 3686295541 ps
CPU time 13.61 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 220992 kb
Host smart-897ab2e5-5fb5-4b21-ae12-10a96f198d5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218288410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1218288410
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1318382439
Short name T458
Test name
Test status
Simulation time 1016196203 ps
CPU time 11.39 seconds
Started Aug 12 06:44:33 PM PDT 24
Finished Aug 12 06:44:44 PM PDT 24
Peak memory 226600 kb
Host smart-8b125efd-2d55-4a2c-a3e7-ace22b7931a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318382439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1318382439
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.732448477
Short name T63
Test name
Test status
Simulation time 1445116826 ps
CPU time 8.35 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:38 PM PDT 24
Peak memory 218744 kb
Host smart-a3211b31-6e34-4b04-a799-1483bb2d28f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732448477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.732448477
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1900594392
Short name T18
Test name
Test status
Simulation time 872094705 ps
CPU time 9.51 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:44:42 PM PDT 24
Peak memory 225888 kb
Host smart-4297da79-1727-4f9b-a843-6cf0343a5803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900594392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1900594392
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.4001585813
Short name T238
Test name
Test status
Simulation time 261662900 ps
CPU time 4.05 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:35 PM PDT 24
Peak memory 218360 kb
Host smart-961d0c7b-b78d-4252-a071-17b224f2fbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001585813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.4001585813
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1982140541
Short name T799
Test name
Test status
Simulation time 1271186565 ps
CPU time 27.23 seconds
Started Aug 12 06:44:28 PM PDT 24
Finished Aug 12 06:44:55 PM PDT 24
Peak memory 251524 kb
Host smart-712b890e-072b-4149-91ac-a4451c817fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982140541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1982140541
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3851641133
Short name T334
Test name
Test status
Simulation time 74807225 ps
CPU time 3.26 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:33 PM PDT 24
Peak memory 223244 kb
Host smart-0cee3786-f196-4afe-923d-413cda013c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851641133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3851641133
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.729743587
Short name T487
Test name
Test status
Simulation time 8304783812 ps
CPU time 174.2 seconds
Started Aug 12 06:44:32 PM PDT 24
Finished Aug 12 06:47:26 PM PDT 24
Peak memory 284272 kb
Host smart-8ee305b8-6cf7-4add-9d52-12c32205e588
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729743587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.729743587
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4172149784
Short name T791
Test name
Test status
Simulation time 15508113 ps
CPU time 0.97 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:31 PM PDT 24
Peak memory 212448 kb
Host smart-4e8b3045-c95e-40e8-b3c4-2723f37510a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172149784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4172149784
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1892667616
Short name T629
Test name
Test status
Simulation time 140266273 ps
CPU time 0.9 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:39 PM PDT 24
Peak memory 209444 kb
Host smart-766a03cb-0b0f-468c-bfea-67895c35b0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892667616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1892667616
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.405309301
Short name T184
Test name
Test status
Simulation time 11019858 ps
CPU time 0.83 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:41 PM PDT 24
Peak memory 209144 kb
Host smart-c5714bff-0040-4a69-97a8-cb3268d1f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405309301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.405309301
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3779783966
Short name T513
Test name
Test status
Simulation time 847349788 ps
CPU time 13.22 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:44 PM PDT 24
Peak memory 226668 kb
Host smart-da871121-2760-407c-a15b-8bc2a797ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779783966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3779783966
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.467982387
Short name T412
Test name
Test status
Simulation time 1645972127 ps
CPU time 10.14 seconds
Started Aug 12 06:44:41 PM PDT 24
Finished Aug 12 06:44:52 PM PDT 24
Peak memory 217872 kb
Host smart-3d615544-3c1a-46d9-8d2a-98a15682a19e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467982387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.467982387
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1957486606
Short name T362
Test name
Test status
Simulation time 3298639822 ps
CPU time 44.55 seconds
Started Aug 12 06:44:42 PM PDT 24
Finished Aug 12 06:45:27 PM PDT 24
Peak memory 219596 kb
Host smart-ff5560b0-cc9a-4887-ac0c-6c51ac335fec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957486606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1957486606
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1523303398
Short name T819
Test name
Test status
Simulation time 158163320 ps
CPU time 5.17 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:43 PM PDT 24
Peak memory 218272 kb
Host smart-514a93e1-1ed7-4a21-b0fb-424712ce2b82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523303398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
523303398
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1848374190
Short name T242
Test name
Test status
Simulation time 3215370453 ps
CPU time 7.21 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:48 PM PDT 24
Peak memory 218888 kb
Host smart-1ae85f7d-9cd0-46b6-948b-985b9b561870
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848374190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1848374190
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.922550765
Short name T354
Test name
Test status
Simulation time 5732842280 ps
CPU time 15.93 seconds
Started Aug 12 06:44:41 PM PDT 24
Finished Aug 12 06:44:57 PM PDT 24
Peak memory 218228 kb
Host smart-7704d3c0-f396-460e-8045-ffd7b73a631b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922550765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.922550765
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.156126753
Short name T83
Test name
Test status
Simulation time 3312682139 ps
CPU time 6.56 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 218172 kb
Host smart-2f058ec2-9190-44a2-bc2b-d650fd1e6f27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156126753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.156126753
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3393667811
Short name T561
Test name
Test status
Simulation time 9290686315 ps
CPU time 44.53 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:45:24 PM PDT 24
Peak memory 255948 kb
Host smart-27737093-1722-4493-b9b2-da14bf4cdd23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393667811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3393667811
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2494809959
Short name T441
Test name
Test status
Simulation time 909288091 ps
CPU time 26.39 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:45:06 PM PDT 24
Peak memory 227052 kb
Host smart-01d7ab71-78cf-479e-869a-6eb15a951eec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494809959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2494809959
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2858266201
Short name T422
Test name
Test status
Simulation time 312826804 ps
CPU time 3.48 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:33 PM PDT 24
Peak memory 223232 kb
Host smart-a536ae1e-d016-467f-8f6f-630fcc84d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858266201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2858266201
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.897847873
Short name T183
Test name
Test status
Simulation time 1203878226 ps
CPU time 20.87 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:45:00 PM PDT 24
Peak memory 223000 kb
Host smart-1d30189a-0463-4336-add2-8fb12f1af759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897847873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.897847873
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4110398935
Short name T363
Test name
Test status
Simulation time 484602214 ps
CPU time 13.83 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:52 PM PDT 24
Peak memory 226664 kb
Host smart-13d74a63-fbf4-453d-bdc9-14417d61fc58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110398935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4110398935
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2407791897
Short name T719
Test name
Test status
Simulation time 431143079 ps
CPU time 17.47 seconds
Started Aug 12 06:44:41 PM PDT 24
Finished Aug 12 06:44:59 PM PDT 24
Peak memory 226572 kb
Host smart-0772fa62-3145-4b42-b439-67943495824c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407791897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2407791897
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4003738375
Short name T345
Test name
Test status
Simulation time 191462158 ps
CPU time 8.35 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:48 PM PDT 24
Peak memory 218836 kb
Host smart-8f210a5d-711b-4ff5-9ac9-0fd16dff7196
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003738375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
003738375
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1584939888
Short name T563
Test name
Test status
Simulation time 1239381131 ps
CPU time 11.39 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:51 PM PDT 24
Peak memory 218880 kb
Host smart-617c1cd7-aa16-4b20-93ce-cc0ad263e212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584939888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1584939888
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.783362562
Short name T75
Test name
Test status
Simulation time 730082763 ps
CPU time 3.85 seconds
Started Aug 12 06:44:31 PM PDT 24
Finished Aug 12 06:44:35 PM PDT 24
Peak memory 218240 kb
Host smart-11e8ff7f-f85e-4f79-948e-94d78513ebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783362562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.783362562
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.970238464
Short name T295
Test name
Test status
Simulation time 1308070451 ps
CPU time 29.18 seconds
Started Aug 12 06:44:28 PM PDT 24
Finished Aug 12 06:44:57 PM PDT 24
Peak memory 251504 kb
Host smart-09e349c7-cfbd-47b2-98ad-c777946f3c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970238464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.970238464
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3811526710
Short name T785
Test name
Test status
Simulation time 79433781 ps
CPU time 8.72 seconds
Started Aug 12 06:44:30 PM PDT 24
Finished Aug 12 06:44:39 PM PDT 24
Peak memory 251448 kb
Host smart-487af62f-413f-48bf-82f2-99190fea935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811526710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3811526710
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4189951596
Short name T777
Test name
Test status
Simulation time 67547468853 ps
CPU time 275.52 seconds
Started Aug 12 06:44:42 PM PDT 24
Finished Aug 12 06:49:17 PM PDT 24
Peak memory 256672 kb
Host smart-e5d1b940-6ac9-4383-91ad-f0b2e3407ea7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189951596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.4189951596
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3567099229
Short name T89
Test name
Test status
Simulation time 740288795 ps
CPU time 23.17 seconds
Started Aug 12 06:44:47 PM PDT 24
Finished Aug 12 06:45:10 PM PDT 24
Peak memory 251668 kb
Host smart-e51cac3e-b4c1-4a99-ba2d-234c196fe5b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3567099229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3567099229
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3538034329
Short name T821
Test name
Test status
Simulation time 43273927 ps
CPU time 0.97 seconds
Started Aug 12 06:44:28 PM PDT 24
Finished Aug 12 06:44:29 PM PDT 24
Peak memory 212512 kb
Host smart-02cc9b59-c24e-4776-adf4-d3785d301a3c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538034329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3538034329
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2368444582
Short name T541
Test name
Test status
Simulation time 18852229 ps
CPU time 0.78 seconds
Started Aug 12 06:44:42 PM PDT 24
Finished Aug 12 06:44:43 PM PDT 24
Peak memory 209612 kb
Host smart-b5069924-a100-48bb-8257-27967751d260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368444582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2368444582
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1945180428
Short name T465
Test name
Test status
Simulation time 76260639 ps
CPU time 0.82 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:39 PM PDT 24
Peak memory 209492 kb
Host smart-c3a64f01-3fa1-4b22-bf3e-16024d6be829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945180428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1945180428
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.76693800
Short name T515
Test name
Test status
Simulation time 1195925968 ps
CPU time 12.92 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:51 PM PDT 24
Peak memory 218876 kb
Host smart-63f46fea-ad18-4633-bd38-6888c668c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76693800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.76693800
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.4190922877
Short name T744
Test name
Test status
Simulation time 488296097 ps
CPU time 7.79 seconds
Started Aug 12 06:44:48 PM PDT 24
Finished Aug 12 06:44:56 PM PDT 24
Peak memory 217964 kb
Host smart-f2fa31d5-d882-4d5e-80b4-a7fc8379237f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190922877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.4190922877
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1492492541
Short name T233
Test name
Test status
Simulation time 6930640927 ps
CPU time 37.35 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:45:15 PM PDT 24
Peak memory 219532 kb
Host smart-d51a28a8-0889-4a67-bad3-6ca4d2db0458
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492492541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1492492541
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3313194372
Short name T754
Test name
Test status
Simulation time 263366005 ps
CPU time 2.96 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:44:42 PM PDT 24
Peak memory 218248 kb
Host smart-c6d42f87-de3d-448a-81ce-3e142f6dff84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313194372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
313194372
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1689135849
Short name T450
Test name
Test status
Simulation time 119348669 ps
CPU time 2.77 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:44:42 PM PDT 24
Peak memory 222260 kb
Host smart-a6692a57-6808-4adc-8874-b634ea35d1e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689135849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1689135849
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3426806341
Short name T772
Test name
Test status
Simulation time 1795278233 ps
CPU time 24.28 seconds
Started Aug 12 06:44:41 PM PDT 24
Finished Aug 12 06:45:06 PM PDT 24
Peak memory 218148 kb
Host smart-dea6a183-2f4c-4b56-8cba-cebfc9635b02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426806341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3426806341
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2805392884
Short name T368
Test name
Test status
Simulation time 501757418 ps
CPU time 5.92 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 218172 kb
Host smart-3c2d186b-94e6-450a-bcab-326d0cfbf065
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805392884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2805392884
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3115011752
Short name T383
Test name
Test status
Simulation time 8167999678 ps
CPU time 47.04 seconds
Started Aug 12 06:44:48 PM PDT 24
Finished Aug 12 06:45:35 PM PDT 24
Peak memory 276072 kb
Host smart-6ef73c61-a73a-49da-81a8-db06f933d38d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115011752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3115011752
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1424723139
Short name T640
Test name
Test status
Simulation time 2915734733 ps
CPU time 20.73 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:59 PM PDT 24
Peak memory 249848 kb
Host smart-7f21d839-3117-48cd-8069-69513f8b99d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424723139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1424723139
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2561690302
Short name T763
Test name
Test status
Simulation time 317376822 ps
CPU time 3.48 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:44:43 PM PDT 24
Peak memory 222832 kb
Host smart-fc864ef2-fcf0-43d3-a44f-41ac6340d31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561690302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2561690302
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3175328367
Short name T182
Test name
Test status
Simulation time 357574009 ps
CPU time 19.96 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:44:59 PM PDT 24
Peak memory 218216 kb
Host smart-29ae6af1-eae9-47d5-9bf7-5206324a7653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175328367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3175328367
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.41144441
Short name T292
Test name
Test status
Simulation time 302823395 ps
CPU time 13.28 seconds
Started Aug 12 06:44:42 PM PDT 24
Finished Aug 12 06:44:55 PM PDT 24
Peak memory 218908 kb
Host smart-da9fb870-86a1-42db-86c0-c4e1b90d33a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41144441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.41144441
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.783054998
Short name T673
Test name
Test status
Simulation time 203019360 ps
CPU time 9.46 seconds
Started Aug 12 06:44:39 PM PDT 24
Finished Aug 12 06:44:49 PM PDT 24
Peak memory 226572 kb
Host smart-83a42644-45ee-41aa-b1a0-c65f3968de3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783054998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.783054998
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1195823231
Short name T703
Test name
Test status
Simulation time 3919712017 ps
CPU time 20.52 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:45:01 PM PDT 24
Peak memory 218840 kb
Host smart-ab4fd40f-4340-4a30-b503-c696c8abb552
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195823231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
195823231
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1838653688
Short name T55
Test name
Test status
Simulation time 492973870 ps
CPU time 7.87 seconds
Started Aug 12 06:44:38 PM PDT 24
Finished Aug 12 06:44:46 PM PDT 24
Peak memory 226680 kb
Host smart-064e090b-3ab6-4a2c-a1ba-88d7d6b3907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838653688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1838653688
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1981244131
Short name T506
Test name
Test status
Simulation time 64531313 ps
CPU time 3.01 seconds
Started Aug 12 06:44:48 PM PDT 24
Finished Aug 12 06:44:51 PM PDT 24
Peak memory 218196 kb
Host smart-7dbd208f-472d-4ff9-bad4-3de2c91369c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981244131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1981244131
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2729687048
Short name T730
Test name
Test status
Simulation time 360511926 ps
CPU time 26.13 seconds
Started Aug 12 06:44:41 PM PDT 24
Finished Aug 12 06:45:07 PM PDT 24
Peak memory 251468 kb
Host smart-f1a92a65-866e-4599-a984-2c8bc12a4933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729687048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2729687048
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2612955005
Short name T683
Test name
Test status
Simulation time 119949980 ps
CPU time 3.28 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:43 PM PDT 24
Peak memory 222996 kb
Host smart-d9f902ce-5772-407c-8305-bc4d3b5bda62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612955005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2612955005
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2980378082
Short name T438
Test name
Test status
Simulation time 74838662052 ps
CPU time 341.3 seconds
Started Aug 12 06:44:41 PM PDT 24
Finished Aug 12 06:50:22 PM PDT 24
Peak memory 389876 kb
Host smart-0aa5296e-e378-4ade-a929-70e0c480d47d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980378082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2980378082
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.4116229095
Short name T90
Test name
Test status
Simulation time 29705468399 ps
CPU time 132.87 seconds
Started Aug 12 06:44:47 PM PDT 24
Finished Aug 12 06:47:00 PM PDT 24
Peak memory 263656 kb
Host smart-a9cf79c9-906d-40e8-867b-efab29bc4196
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4116229095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.4116229095
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.833303410
Short name T564
Test name
Test status
Simulation time 15620107 ps
CPU time 1.14 seconds
Started Aug 12 06:44:40 PM PDT 24
Finished Aug 12 06:44:41 PM PDT 24
Peak memory 213536 kb
Host smart-8162796f-332d-41c4-8acb-e048fa562d4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833303410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.833303410
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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