Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55897153

1

T1

44439

T2

7380

T3

5710

auto[1]

1121798

1

T1

396

T3

198

T4

1485

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55894901

1

T1

44538

T2

7380

T3

5611

auto[1]

1124050

1

T1

297

T3

297

T4

990

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5247880	1			T1	10047		T2	113		T3	1685
auto[IdleSt]	16437722	1			T1	6517		T2	7267		T3	908
auto[ClkMuxSt]	27875	1			T1	78		T3	4		T4	70
auto[CntIncrSt]	27709	1			T1	78		T3	4		T4	70
auto[CntProgSt]	1369077	1			T1	127		T3	26		T4	11361
auto[TransCheckSt]	21773	1			T1	61		T3	4		T4	56
auto[TokenHashSt]	12735631	1			T1	13871		T3	76		T4	1148
auto[FlashRmaSt]	25921	1			T1	75		T3	19		T4	179
auto[TokenCheck0St]	9685	1			T1	20		T3	4		T4	50
auto[TokenCheck1St]	6947	1			T1	13		T3	4		T4	33
auto[TransProgSt]	282083	1			T1	23		T3	27		T4	4975
auto[PostTransSt]	8933625	1			T1	12956		T3	1055		T4	11891
auto[ScrapSt]	65629	1			T15	12		T37	335		T38	4
auto[EscalateSt]	4670091	1			T1	969		T3	1250		T4	3586
auto[InvalidSt]	7155970	1			T3	841		T4	2074		T11	14615

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1333	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7155970	1			T3	841		T4	2074		T11	14615
EscalateSt	4670091	1			T1	969		T3	1250		T4	3586
ScrapSt	65629	1			T15	12		T37	335		T38	4
PostTransSt	8933625	1			T1	12956		T3	1055		T4	11891
TransProgSt	282083	1			T1	23		T3	27		T4	4975
TokenCheck1St	6947	1			T1	13		T3	4		T4	33
TokenCheck0St	9685	1			T1	20		T3	4		T4	50
FlashRmaSt	25921	1			T1	75		T3	19		T4	179
TokenHashSt	12735631	1			T1	13871		T3	76		T4	1148
TransCheckSt	21773	1			T1	61		T3	4		T4	56
CntProgSt	1369077	1			T1	127		T3	26		T4	11361
CntIncrSt	27709	1			T1	78		T3	4		T4	70
ClkMuxSt	27875	1			T1	78		T3	4		T4	70
IdleSt	16437722	1			T1	6517		T2	7267		T3	908
ResetSt	5247880	1			T1	10047		T2	113		T3	1685
arcs[ResetSt=>IdleSt]	41181	1			T1	79		T2	1		T3	11
arcs[IdleSt=>ScrapSt]	202	1			T15	3		T37	1		T38	1
arcs[IdleSt=>ClkMuxSt]	27741	1			T1	78		T3	4		T4	70
arcs[ClkMuxSt=>CntIncrSt]	27709	1			T1	78		T3	4		T4	70
arcs[CntIncrSt=>PostTransSt]	1192	1			T1	12		T10	7		T16	9
arcs[CntIncrSt=>CntProgSt]	26461	1			T1	66		T3	4		T4	70
arcs[CntProgSt=>PostTransSt]	3530	1			T1	5		T4	14		T12	24
arcs[CntProgSt=>TransCheckSt]	21773	1			T1	61		T3	4		T4	56
arcs[TransCheckSt=>PostTransSt]	3016	1			T1	10		T10	15		T16	9
arcs[TransCheckSt=>TokenHashSt]	18670	1			T1	51		T3	4		T4	56
arcs[TokenHashSt=>PostTransSt]	8208	1			T1	30		T4	6		T12	8
arcs[TokenHashSt=>FlashRmaSt]	9735	1			T1	20		T3	4		T4	50
arcs[FlashRmaSt=>TokenCheck0St]	9685	1			T1	20		T3	4		T4	50
arcs[TokenCheck0St=>PostTransSt]	2690	1			T1	7		T4	17		T12	11
arcs[TokenCheck0St=>TokenCheck1St]	6947	1			T1	13		T3	4		T4	33
arcs[TokenCheck1St=>PostTransSt]	562	1			T1	1		T4	1		T10	1
arcs[TransProgSt=>PostTransSt]	5505	1			T1	12		T3	4		T4	32
arcs[IdleSt=>EscalateSt]	158	1			T17	7		T38	5		T50	2
arcs[ClkMuxSt=>EscalateSt]	32	1			T38	1		T46	1		T47	1
arcs[CntIncrSt=>EscalateSt]	56	1			T17	3		T48	4		T49	2
arcs[CntProgSt=>EscalateSt]	1158	1			T15	6		T17	18		T48	34
arcs[TransCheckSt=>EscalateSt]	87	1			T15	1		T48	1		T53	1
arcs[TokenHashSt=>EscalateSt]	727	1			T1	1		T15	22		T17	9
arcs[FlashRmaSt=>EscalateSt]	50	1			T15	2		T17	1		T48	1
arcs[TokenCheck0St=>EscalateSt]	48	1			T17	3		T48	1		T53	2
arcs[TokenCheck1St=>EscalateSt]	29	1			T15	1		T48	3		T38	1
arcs[TransProgSt=>EscalateSt]	851	1			T15	9		T17	26		T48	20
arcs[PostTransSt=>EscalateSt]	3815	1			T1	6		T4	14		T12	24
arcs[InvalidSt=>EscalateSt]	9814	1			T3	5		T4	11		T11	79

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5247720	1			T1	10047		T2	113		T3	1685
auto[0]	auto[IdleSt]	16437615	1			T1	6517		T2	7267		T3	908
auto[0]	auto[ClkMuxSt]	27851	1			T1	78		T3	4		T4	70
auto[0]	auto[CntIncrSt]	27671	1			T1	78		T3	4		T4	70
auto[0]	auto[CntProgSt]	1368297	1			T1	127		T3	26		T4	11361
auto[0]	auto[TransCheckSt]	21708	1			T1	61		T3	4		T4	56
auto[0]	auto[TokenHashSt]	12735178	1			T1	13871		T3	76		T4	1148
auto[0]	auto[FlashRmaSt]	25887	1			T1	75		T3	19		T4	179
auto[0]	auto[TokenCheck0St]	9656	1			T1	20		T3	4		T4	50
auto[0]	auto[TokenCheck1St]	6927	1			T1	13		T3	4		T4	33
auto[0]	auto[TransProgSt]	281533	1			T1	23		T3	27		T4	4975
auto[0]	auto[PostTransSt]	8931657	1			T1	12952		T3	1055		T4	11882
auto[0]	auto[ScrapSt]	65593	1			T15	9		T37	335		T38	3
auto[0]	auto[EscalateSt]	3557475	1			T1	577		T3	1054		T4	2116
auto[0]	auto[InvalidSt]	7151052	1			T3	839		T4	2068		T11	14581
auto[1]	auto[ResetSt]	160	1			T15	1		T17	4		T48	6
auto[1]	auto[IdleSt]	107	1			T17	5		T38	2		T50	2
auto[1]	auto[ClkMuxSt]	24	1			T47	1		T207	2		T208	1
auto[1]	auto[CntIncrSt]	38	1			T48	3		T209	1		T51	1
auto[1]	auto[CntProgSt]	780	1			T15	4		T17	12		T48	24
auto[1]	auto[TransCheckSt]	65	1			T53	1		T38	5		T51	2
auto[1]	auto[TokenHashSt]	453	1			T15	15		T17	4		T16	1
auto[1]	auto[FlashRmaSt]	34	1			T15	2		T17	1		T53	1
auto[1]	auto[TokenCheck0St]	29	1			T53	2		T49	1		T50	1
auto[1]	auto[TokenCheck1St]	20	1			T15	1		T48	2		T209	1
auto[1]	auto[TransProgSt]	550	1			T15	7		T17	16		T48	15
auto[1]	auto[PostTransSt]	1968	1			T1	4		T4	9		T12	11
auto[1]	auto[ScrapSt]	36	1			T15	3		T38	1		T46	1
auto[1]	auto[EscalateSt]	1112616	1			T1	392		T3	196		T4	1470
auto[1]	auto[InvalidSt]	4918	1			T3	2		T4	6		T11	34

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5247704	1			T1	10047		T2	113		T3	1685
auto[0]	auto[IdleSt]	16437614	1			T1	6517		T2	7267		T3	908
auto[0]	auto[ClkMuxSt]	27856	1			T1	78		T3	4		T4	70
auto[0]	auto[CntIncrSt]	27666	1			T1	78		T3	4		T4	70
auto[0]	auto[CntProgSt]	1368317	1			T1	127		T3	26		T4	11361
auto[0]	auto[TransCheckSt]	21716	1			T1	61		T3	4		T4	56
auto[0]	auto[TokenHashSt]	12735132	1			T1	13870		T3	76		T4	1148
auto[0]	auto[FlashRmaSt]	25889	1			T1	75		T3	19		T4	179
auto[0]	auto[TokenCheck0St]	9648	1			T1	20		T3	4		T4	50
auto[0]	auto[TokenCheck1St]	6928	1			T1	13		T3	4		T4	33
auto[0]	auto[TransProgSt]	281513	1			T1	23		T3	27		T4	4975
auto[0]	auto[PostTransSt]	8931703	1			T1	12954		T3	1055		T4	11886
auto[0]	auto[ScrapSt]	65582	1			T15	10		T37	335		T38	4
auto[0]	auto[EscalateSt]	3555226	1			T1	675		T3	956		T4	2606
auto[0]	auto[InvalidSt]	7151074	1			T3	838		T4	2069		T11	14570
auto[1]	auto[ResetSt]	176	1			T15	3		T17	7		T48	6
auto[1]	auto[IdleSt]	108	1			T17	4		T38	4		T50	1
auto[1]	auto[ClkMuxSt]	19	1			T38	1		T46	1		T210	1
auto[1]	auto[CntIncrSt]	43	1			T17	3		T48	3		T49	2
auto[1]	auto[CntProgSt]	760	1			T15	4		T17	10		T48	22
auto[1]	auto[TransCheckSt]	57	1			T15	1		T48	1		T38	3
auto[1]	auto[TokenHashSt]	499	1			T1	1		T15	15		T17	6
auto[1]	auto[FlashRmaSt]	32	1			T17	1		T48	1		T53	1
auto[1]	auto[TokenCheck0St]	37	1			T17	3		T48	1		T49	4
auto[1]	auto[TokenCheck1St]	19	1			T15	1		T48	1		T38	1
auto[1]	auto[TransProgSt]	570	1			T15	4		T17	19		T48	14
auto[1]	auto[PostTransSt]	1922	1			T1	2		T4	5		T12	13
auto[1]	auto[ScrapSt]	47	1			T15	2		T51	1		T46	1
auto[1]	auto[EscalateSt]	1114865	1			T1	294		T3	294		T4	980
auto[1]	auto[InvalidSt]	4896	1			T3	3		T4	5		T11	45