Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40201 |
1 |
|
|
T2 |
60 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
1230 |
1 |
|
|
T2 |
11 |
|
T13 |
9 |
|
T14 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40685 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
746 |
1 |
|
|
T17 |
22 |
|
T33 |
21 |
|
T57 |
11 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40017 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
292 |
auto[1] |
1414 |
1 |
|
|
T4 |
27 |
|
T8 |
8 |
|
T20 |
12 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40114 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
297 |
auto[1] |
1317 |
1 |
|
|
T4 |
22 |
|
T8 |
5 |
|
T20 |
11 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40050 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
284 |
auto[1] |
1381 |
1 |
|
|
T4 |
35 |
|
T8 |
11 |
|
T20 |
10 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
38300 |
1 |
|
|
T2 |
71 |
|
T4 |
270 |
|
T9 |
53 |
no_err_inj |
3131 |
1 |
|
|
T3 |
10 |
|
T4 |
49 |
|
T11 |
16 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40213 |
1 |
|
|
T2 |
62 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
1218 |
1 |
|
|
T2 |
9 |
|
T13 |
15 |
|
T14 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40796 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
635 |
1 |
|
|
T17 |
15 |
|
T33 |
21 |
|
T57 |
9 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31916 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
15 |
auto[1] |
9515 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40044 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
295 |
auto[1] |
1387 |
1 |
|
|
T4 |
24 |
|
T8 |
4 |
|
T20 |
11 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40091 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
294 |
auto[1] |
1340 |
1 |
|
|
T4 |
25 |
|
T8 |
2 |
|
T20 |
9 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40028 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
283 |
auto[1] |
1403 |
1 |
|
|
T4 |
36 |
|
T8 |
7 |
|
T20 |
4 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40174 |
1 |
|
|
T2 |
58 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
1257 |
1 |
|
|
T2 |
13 |
|
T13 |
8 |
|
T14 |
6 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39915 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
315 |
auto[1] |
1516 |
1 |
|
|
T4 |
4 |
|
T10 |
8 |
|
T54 |
2 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40719 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
712 |
1 |
|
|
T17 |
14 |
|
T33 |
16 |
|
T57 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40737 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
694 |
1 |
|
|
T17 |
21 |
|
T33 |
21 |
|
T57 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40731 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
700 |
1 |
|
|
T17 |
21 |
|
T33 |
20 |
|
T57 |
10 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39650 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
283 |
auto[1] |
1781 |
1 |
|
|
T4 |
36 |
|
T14 |
21 |
|
T77 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37472 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
3959 |
1 |
|
|
T9 |
53 |
|
T15 |
96 |
|
T41 |
72 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40113 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
284 |
auto[1] |
1318 |
1 |
|
|
T4 |
35 |
|
T8 |
4 |
|
T20 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40095 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
288 |
auto[1] |
1336 |
1 |
|
|
T4 |
31 |
|
T8 |
7 |
|
T20 |
16 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39991 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
288 |
auto[1] |
1440 |
1 |
|
|
T4 |
31 |
|
T8 |
7 |
|
T20 |
16 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40233 |
1 |
|
|
T2 |
62 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
1198 |
1 |
|
|
T2 |
9 |
|
T13 |
9 |
|
T14 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36600 |
1 |
|
|
T2 |
62 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
4831 |
1 |
|
|
T2 |
9 |
|
T12 |
97 |
|
T13 |
9 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37769 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
3662 |
1 |
|
|
T19 |
88 |
|
T55 |
88 |
|
T56 |
63 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41431 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
319 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40221 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
1210 |
1 |
|
|
T2 |
8 |
|
T13 |
14 |
|
T14 |
8 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40238 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
1193 |
1 |
|
|
T2 |
8 |
|
T13 |
10 |
|
T14 |
4 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40228 |
1 |
|
|
T2 |
67 |
|
T3 |
10 |
|
T4 |
319 |
auto[1] |
1203 |
1 |
|
|
T2 |
4 |
|
T13 |
10 |
|
T14 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
37394 |
1 |
|
|
T2 |
71 |
|
T4 |
254 |
|
T9 |
53 |
auto[0] |
no_err_inj |
2256 |
1 |
|
|
T3 |
10 |
|
T4 |
29 |
|
T11 |
16 |
auto[1] |
err_inj |
906 |
1 |
|
|
T4 |
16 |
|
T14 |
12 |
|
T77 |
6 |
auto[1] |
no_err_inj |
875 |
1 |
|
|
T4 |
20 |
|
T14 |
9 |
|
T77 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38399 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
253 |
auto[0] |
auto[1] |
1251 |
1 |
|
|
T4 |
30 |
|
T8 |
7 |
|
T20 |
16 |
auto[1] |
auto[0] |
1696 |
1 |
|
|
T4 |
35 |
|
T14 |
21 |
|
T77 |
10 |
auto[1] |
auto[1] |
85 |
1 |
|
|
T4 |
1 |
|
T77 |
1 |
|
T34 |
5 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38412 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
258 |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T4 |
25 |
|
T8 |
2 |
|
T20 |
9 |
auto[1] |
auto[0] |
1679 |
1 |
|
|
T4 |
36 |
|
T14 |
20 |
|
T77 |
11 |
auto[1] |
auto[1] |
102 |
1 |
|
|
T14 |
1 |
|
T80 |
1 |
|
T214 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38317 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
257 |
auto[0] |
auto[1] |
1333 |
1 |
|
|
T4 |
26 |
|
T8 |
7 |
|
T20 |
16 |
auto[1] |
auto[0] |
1674 |
1 |
|
|
T4 |
31 |
|
T14 |
18 |
|
T77 |
11 |
auto[1] |
auto[1] |
107 |
1 |
|
|
T4 |
5 |
|
T14 |
3 |
|
T149 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38436 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
262 |
auto[0] |
auto[1] |
1214 |
1 |
|
|
T4 |
21 |
|
T8 |
5 |
|
T20 |
11 |
auto[1] |
auto[0] |
1678 |
1 |
|
|
T4 |
35 |
|
T14 |
20 |
|
T77 |
11 |
auto[1] |
auto[1] |
103 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T80 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38368 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
249 |
auto[0] |
auto[1] |
1282 |
1 |
|
|
T4 |
34 |
|
T8 |
11 |
|
T20 |
10 |
auto[1] |
auto[0] |
1682 |
1 |
|
|
T4 |
35 |
|
T14 |
21 |
|
T77 |
10 |
auto[1] |
auto[1] |
99 |
1 |
|
|
T4 |
1 |
|
T77 |
1 |
|
T149 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38356 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
257 |
auto[0] |
auto[1] |
1294 |
1 |
|
|
T4 |
26 |
|
T8 |
8 |
|
T20 |
12 |
auto[1] |
auto[0] |
1661 |
1 |
|
|
T4 |
35 |
|
T14 |
20 |
|
T77 |
9 |
auto[1] |
auto[1] |
120 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T77 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31102 |
1 |
|
|
T2 |
60 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
814 |
1 |
|
|
T2 |
11 |
|
T13 |
9 |
|
T14 |
9 |
auto[1] |
auto[0] |
9099 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
416 |
1 |
|
|
T81 |
13 |
|
T52 |
2 |
|
T30 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31123 |
1 |
|
|
T2 |
62 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
793 |
1 |
|
|
T2 |
9 |
|
T13 |
15 |
|
T14 |
6 |
auto[1] |
auto[0] |
9090 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
425 |
1 |
|
|
T81 |
11 |
|
T82 |
5 |
|
T30 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30981 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
11 |
auto[0] |
auto[1] |
935 |
1 |
|
|
T4 |
4 |
|
T10 |
8 |
|
T54 |
2 |
auto[1] |
auto[0] |
8934 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
581 |
1 |
|
|
T34 |
9 |
|
T152 |
18 |
|
T215 |
14 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31086 |
1 |
|
|
T2 |
58 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
830 |
1 |
|
|
T2 |
13 |
|
T13 |
8 |
|
T14 |
6 |
auto[1] |
auto[0] |
9088 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
427 |
1 |
|
|
T81 |
13 |
|
T82 |
4 |
|
T30 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
27489 |
1 |
|
|
T2 |
62 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
4427 |
1 |
|
|
T2 |
9 |
|
T12 |
97 |
|
T13 |
9 |
auto[1] |
auto[0] |
9111 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
404 |
1 |
|
|
T81 |
12 |
|
T52 |
1 |
|
T82 |
2 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31070 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
846 |
1 |
|
|
T14 |
7 |
|
T77 |
1 |
|
T78 |
4 |
auto[1] |
auto[0] |
9025 |
1 |
|
|
T4 |
273 |
|
T5 |
12 |
|
T8 |
48 |
auto[1] |
auto[1] |
490 |
1 |
|
|
T4 |
31 |
|
T8 |
7 |
|
T20 |
16 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31014 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
14 |
auto[0] |
auto[1] |
902 |
1 |
|
|
T4 |
1 |
|
T14 |
11 |
|
T77 |
1 |
auto[1] |
auto[0] |
9099 |
1 |
|
|
T4 |
270 |
|
T5 |
12 |
|
T8 |
51 |
auto[1] |
auto[1] |
416 |
1 |
|
|
T4 |
34 |
|
T8 |
4 |
|
T20 |
8 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31068 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
848 |
1 |
|
|
T14 |
14 |
|
T78 |
10 |
|
T79 |
13 |
auto[1] |
auto[0] |
9023 |
1 |
|
|
T4 |
279 |
|
T5 |
12 |
|
T8 |
53 |
auto[1] |
auto[1] |
492 |
1 |
|
|
T4 |
25 |
|
T8 |
2 |
|
T20 |
9 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31009 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
14 |
auto[0] |
auto[1] |
907 |
1 |
|
|
T4 |
1 |
|
T14 |
11 |
|
T78 |
8 |
auto[1] |
auto[0] |
9035 |
1 |
|
|
T4 |
281 |
|
T5 |
12 |
|
T8 |
51 |
auto[1] |
auto[1] |
480 |
1 |
|
|
T4 |
23 |
|
T8 |
4 |
|
T20 |
11 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31053 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
863 |
1 |
|
|
T14 |
14 |
|
T78 |
8 |
|
T79 |
6 |
auto[1] |
auto[0] |
9061 |
1 |
|
|
T4 |
282 |
|
T5 |
12 |
|
T8 |
50 |
auto[1] |
auto[1] |
454 |
1 |
|
|
T4 |
22 |
|
T8 |
5 |
|
T20 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30988 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
928 |
1 |
|
|
T14 |
10 |
|
T77 |
2 |
|
T78 |
6 |
auto[1] |
auto[0] |
9029 |
1 |
|
|
T4 |
277 |
|
T5 |
12 |
|
T8 |
47 |
auto[1] |
auto[1] |
486 |
1 |
|
|
T4 |
27 |
|
T8 |
8 |
|
T20 |
12 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31148 |
1 |
|
|
T2 |
67 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
768 |
1 |
|
|
T2 |
4 |
|
T13 |
10 |
|
T14 |
9 |
auto[1] |
auto[0] |
9080 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
435 |
1 |
|
|
T81 |
13 |
|
T52 |
3 |
|
T82 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31146 |
1 |
|
|
T2 |
63 |
|
T3 |
10 |
|
T4 |
15 |
auto[0] |
auto[1] |
770 |
1 |
|
|
T2 |
8 |
|
T13 |
10 |
|
T14 |
4 |
auto[1] |
auto[0] |
9092 |
1 |
|
|
T4 |
304 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
423 |
1 |
|
|
T81 |
7 |
|
T52 |
1 |
|
T82 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30843 |
1 |
|
|
T2 |
71 |
|
T3 |
10 |
|
T4 |
4 |
auto[0] |
auto[1] |
1073 |
1 |
|
|
T4 |
11 |
|
T14 |
21 |
|
T77 |
11 |
auto[1] |
auto[0] |
8807 |
1 |
|
|
T4 |
279 |
|
T5 |
12 |
|
T8 |
55 |
auto[1] |
auto[1] |
708 |
1 |
|
|
T4 |
25 |
|
T82 |
3 |
|
T50 |
6 |