Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53175457

1

T1

33852

T2

41687

T3

47324

auto[1]

1174535

1

T2

396

T4

9898

T9

7263

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53164803

1

T1

33852

T2

41390

T3

47324

auto[1]

1185189

1

T2

693

T4

10003

T9

6006

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5446074	1			T1	76		T2	6528		T3	906
auto[IdleSt]	14805609	1			T1	33776		T2	6064		T3	1336
auto[ClkMuxSt]	27990	1			T2	71		T3	10		T4	53
auto[CntIncrSt]	27847	1			T2	71		T3	10		T4	53
auto[CntProgSt]	1335334	1			T2	11404		T3	4570		T4	1490
auto[TransCheckSt]	22065	1			T2	52		T3	10		T4	49
auto[TokenHashSt]	11843129	1			T2	2058		T3	35365		T4	7855
auto[FlashRmaSt]	28510	1			T2	48		T3	35		T4	182
auto[TokenCheck0St]	9832	1			T2	22		T3	10		T4	49
auto[TokenCheck1St]	7152	1			T2	15		T3	10		T4	49
auto[TransProgSt]	287484	1			T2	3210		T3	3796		T4	1368
auto[PostTransSt]	8201293	1			T2	11040		T3	1266		T4	31837
auto[ScrapSt]	170680	1			T9	12		T11	10		T14	1067
auto[EscalateSt]	4733555	1			T2	1500		T4	87008		T9	10152
auto[InvalidSt]	7402025	1			T4	263912		T8	143782		T20	185625

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1413	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7402025	1			T4	263912		T8	143782		T20	185625
EscalateSt	4733555	1			T2	1500		T4	87008		T9	10152
ScrapSt	170680	1			T9	12		T11	10		T14	1067
PostTransSt	8201293	1			T2	11040		T3	1266		T4	31837
TransProgSt	287484	1			T2	3210		T3	3796		T4	1368
TokenCheck1St	7152	1			T2	15		T3	10		T4	49
TokenCheck0St	9832	1			T2	22		T3	10		T4	49
FlashRmaSt	28510	1			T2	48		T3	35		T4	182
TokenHashSt	11843129	1			T2	2058		T3	35365		T4	7855
TransCheckSt	22065	1			T2	52		T3	10		T4	49
CntProgSt	1335334	1			T2	11404		T3	4570		T4	1490
CntIncrSt	27847	1			T2	71		T3	10		T4	53
ClkMuxSt	27990	1			T2	71		T3	10		T4	53
IdleSt	14805609	1			T1	33776		T2	6064		T3	1336
ResetSt	5446074	1			T1	76		T2	6528		T3	906
arcs[ResetSt=>IdleSt]	41942	1			T1	1		T2	72		T3	10
arcs[IdleSt=>ScrapSt]	220	1			T9	3		T11	1		T14	1
arcs[IdleSt=>ClkMuxSt]	27878	1			T2	71		T3	10		T4	53
arcs[ClkMuxSt=>CntIncrSt]	27847	1			T2	71		T3	10		T4	53
arcs[CntIncrSt=>PostTransSt]	1194	1			T2	8		T13	10		T14	4
arcs[CntIncrSt=>CntProgSt]	26580	1			T2	63		T3	10		T4	53
arcs[CntProgSt=>PostTransSt]	3478	1			T2	11		T4	4		T10	8
arcs[CntProgSt=>TransCheckSt]	22065	1			T2	52		T3	10		T4	49
arcs[TransCheckSt=>PostTransSt]	3037	1			T2	4		T13	10		T14	9
arcs[TransCheckSt=>TokenHashSt]	18904	1			T2	48		T3	10		T4	49
arcs[TokenHashSt=>PostTransSt]	8128	1			T2	26		T12	97		T13	32
arcs[TokenHashSt=>FlashRmaSt]	9880	1			T2	22		T3	10		T4	49
arcs[FlashRmaSt=>TokenCheck0St]	9832	1			T2	22		T3	10		T4	49
arcs[TokenCheck0St=>PostTransSt]	2613	1			T2	7		T13	14		T14	6
arcs[TokenCheck0St=>TokenCheck1St]	7152	1			T2	15		T3	10		T4	49
arcs[TokenCheck1St=>PostTransSt]	610	1			T2	1		T13	1		T17	1
arcs[TransProgSt=>PostTransSt]	5753	1			T2	14		T3	10		T4	49
arcs[IdleSt=>EscalateSt]	184	1			T9	4		T15	10		T41	7
arcs[ClkMuxSt=>EscalateSt]	31	1			T38	2		T39	1		T40	2
arcs[CntIncrSt=>EscalateSt]	73	1			T9	2		T15	2		T41	5
arcs[CntProgSt=>EscalateSt]	1037	1			T9	17		T15	31		T41	20
arcs[TransCheckSt=>EscalateSt]	124	1			T9	1		T15	2		T47	1
arcs[TokenHashSt=>EscalateSt]	896	1			T9	5		T15	10		T41	9
arcs[FlashRmaSt=>EscalateSt]	48	1			T15	3		T41	1		T42	1
arcs[TokenCheck0St=>EscalateSt]	67	1			T9	1		T15	3		T41	1
arcs[TokenCheck1St=>EscalateSt]	35	1			T15	1		T46	1		T38	2
arcs[TransProgSt=>EscalateSt]	754	1			T9	16		T15	24		T41	25
arcs[PostTransSt=>EscalateSt]	3888	1			T2	11		T4	4		T9	1
arcs[InvalidSt=>EscalateSt]	10205	1			T4	199		T8	41		T20	77

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5445910	1			T1	76		T2	6528		T3	906
auto[0]	auto[IdleSt]	14805482	1			T1	33776		T2	6064		T3	1336
auto[0]	auto[ClkMuxSt]	27967	1			T2	71		T3	10		T4	53
auto[0]	auto[CntIncrSt]	27807	1			T2	71		T3	10		T4	53
auto[0]	auto[CntProgSt]	1334657	1			T2	11404		T3	4570		T4	1490
auto[0]	auto[TransCheckSt]	21976	1			T2	52		T3	10		T4	49
auto[0]	auto[TokenHashSt]	11842513	1			T2	2058		T3	35365		T4	7855
auto[0]	auto[FlashRmaSt]	28477	1			T2	48		T3	35		T4	182
auto[0]	auto[TokenCheck0St]	9788	1			T2	22		T3	10		T4	49
auto[0]	auto[TokenCheck1St]	7133	1			T2	15		T3	10		T4	49
auto[0]	auto[TransProgSt]	286981	1			T2	3210		T3	3796		T4	1368
auto[0]	auto[PostTransSt]	8199277	1			T2	11036		T3	1266		T4	31837
auto[0]	auto[ScrapSt]	170644	1			T9	9		T11	10		T14	1067
auto[0]	auto[EscalateSt]	3568493	1			T2	1108		T4	77211		T9	2928
auto[0]	auto[InvalidSt]	7396939	1			T4	263811		T8	143763		T20	185594
auto[1]	auto[ResetSt]	164	1			T9	2		T15	3		T41	1
auto[1]	auto[IdleSt]	127	1			T9	2		T15	10		T41	2
auto[1]	auto[ClkMuxSt]	23	1			T38	1		T39	1		T40	1
auto[1]	auto[CntIncrSt]	40	1			T9	2		T15	2		T41	3
auto[1]	auto[CntProgSt]	677	1			T9	12		T15	17		T41	10
auto[1]	auto[TransCheckSt]	89	1			T9	1		T15	2		T47	1
auto[1]	auto[TokenHashSt]	616	1			T9	5		T15	5		T41	5
auto[1]	auto[FlashRmaSt]	33	1			T15	2		T41	1		T42	1
auto[1]	auto[TokenCheck0St]	44	1			T9	1		T15	2		T41	1
auto[1]	auto[TokenCheck1St]	19	1			T38	2		T40	2		T212	1
auto[1]	auto[TransProgSt]	503	1			T9	11		T15	21		T41	17
auto[1]	auto[PostTransSt]	2016	1			T2	4		T10	4		T13	3
auto[1]	auto[ScrapSt]	36	1			T9	3		T41	1		T47	1
auto[1]	auto[EscalateSt]	1165062	1			T2	392		T4	9797		T9	7224
auto[1]	auto[InvalidSt]	5086	1			T4	101		T8	19		T20	31

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5445878	1			T1	76		T2	6528		T3	906
auto[0]	auto[IdleSt]	14805493	1			T1	33776		T2	6064		T3	1336
auto[0]	auto[ClkMuxSt]	27974	1			T2	71		T3	10		T4	53
auto[0]	auto[CntIncrSt]	27794	1			T2	71		T3	10		T4	53
auto[0]	auto[CntProgSt]	1334614	1			T2	11404		T3	4570		T4	1490
auto[0]	auto[TransCheckSt]	21988	1			T2	52		T3	10		T4	49
auto[0]	auto[TokenHashSt]	11842528	1			T2	2058		T3	35365		T4	7855
auto[0]	auto[FlashRmaSt]	28478	1			T2	48		T3	35		T4	182
auto[0]	auto[TokenCheck0St]	9789	1			T2	22		T3	10		T4	49
auto[0]	auto[TokenCheck1St]	7125	1			T2	15		T3	10		T4	49
auto[0]	auto[TransProgSt]	286985	1			T2	3210		T3	3796		T4	1368
auto[0]	auto[PostTransSt]	8199294	1			T2	11033		T3	1266		T4	31833
auto[0]	auto[ScrapSt]	170639	1			T9	12		T11	10		T14	1067
auto[0]	auto[EscalateSt]	3557905	1			T2	814		T4	77107		T9	4175
auto[0]	auto[InvalidSt]	7396906	1			T4	263814		T8	143760		T20	185579
auto[1]	auto[ResetSt]	196	1			T9	2		T15	4		T41	1
auto[1]	auto[IdleSt]	116	1			T9	3		T15	3		T41	5
auto[1]	auto[ClkMuxSt]	16	1			T38	1		T40	1		T213	1
auto[1]	auto[CntIncrSt]	53	1			T15	1		T41	4		T46	1
auto[1]	auto[CntProgSt]	720	1			T9	7		T15	23		T41	11
auto[1]	auto[TransCheckSt]	77	1			T9	1		T15	2		T47	1
auto[1]	auto[TokenHashSt]	601	1			T9	3		T15	8		T41	7
auto[1]	auto[FlashRmaSt]	32	1			T15	2		T41	1		T42	1
auto[1]	auto[TokenCheck0St]	43	1			T15	2		T46	2		T38	2
auto[1]	auto[TokenCheck1St]	27	1			T15	1		T46	1		T39	1
auto[1]	auto[TransProgSt]	499	1			T9	12		T15	14		T41	18
auto[1]	auto[PostTransSt]	1999	1			T2	7		T4	4		T9	1
auto[1]	auto[ScrapSt]	41	1			T15	3		T41	1		T47	2
auto[1]	auto[EscalateSt]	1175650	1			T2	686		T4	9901		T9	5977
auto[1]	auto[InvalidSt]	5119	1			T4	98		T8	22		T20	46