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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.95 97.92 96.12 93.40 97.62 98.52 98.76 96.29


Total test records in report: 1000
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T64 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2980097074 Aug 14 05:30:19 PM PDT 24 Aug 14 05:30:21 PM PDT 24 201503054 ps
T114 /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3423405189 Aug 14 05:30:55 PM PDT 24 Aug 14 05:33:56 PM PDT 24 5650577184 ps
T811 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.893820541 Aug 14 05:31:13 PM PDT 24 Aug 14 05:31:27 PM PDT 24 5669878152 ps
T812 /workspace/coverage/default/36.lc_ctrl_state_failure.3500412197 Aug 14 05:31:26 PM PDT 24 Aug 14 05:31:53 PM PDT 24 326653851 ps
T813 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3672878765 Aug 14 05:30:01 PM PDT 24 Aug 14 05:30:14 PM PDT 24 3048235791 ps
T814 /workspace/coverage/default/22.lc_ctrl_sec_mubi.3154108730 Aug 14 05:30:55 PM PDT 24 Aug 14 05:31:13 PM PDT 24 1748670176 ps
T815 /workspace/coverage/default/10.lc_ctrl_jtag_errors.3092856040 Aug 14 05:30:10 PM PDT 24 Aug 14 05:30:45 PM PDT 24 4809897763 ps
T816 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2549320218 Aug 14 05:31:26 PM PDT 24 Aug 14 05:31:27 PM PDT 24 15880843 ps
T817 /workspace/coverage/default/46.lc_ctrl_errors.2645944489 Aug 14 05:31:42 PM PDT 24 Aug 14 05:31:58 PM PDT 24 2288946073 ps
T818 /workspace/coverage/default/38.lc_ctrl_errors.811498140 Aug 14 05:31:32 PM PDT 24 Aug 14 05:31:42 PM PDT 24 241056997 ps
T165 /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2637293832 Aug 14 05:31:20 PM PDT 24 Aug 14 05:33:16 PM PDT 24 20008918024 ps
T819 /workspace/coverage/default/15.lc_ctrl_jtag_access.2504060431 Aug 14 05:30:26 PM PDT 24 Aug 14 05:30:46 PM PDT 24 10207256224 ps
T820 /workspace/coverage/default/31.lc_ctrl_jtag_access.2370891588 Aug 14 05:31:12 PM PDT 24 Aug 14 05:31:27 PM PDT 24 628192577 ps
T821 /workspace/coverage/default/17.lc_ctrl_smoke.3733108508 Aug 14 05:30:45 PM PDT 24 Aug 14 05:30:47 PM PDT 24 111555688 ps
T822 /workspace/coverage/default/40.lc_ctrl_errors.4244373317 Aug 14 05:31:44 PM PDT 24 Aug 14 05:31:54 PM PDT 24 217741290 ps
T823 /workspace/coverage/default/7.lc_ctrl_prog_failure.2694175009 Aug 14 05:30:00 PM PDT 24 Aug 14 05:30:02 PM PDT 24 76656721 ps
T824 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3300206548 Aug 14 05:31:36 PM PDT 24 Aug 14 05:31:53 PM PDT 24 3252782439 ps
T825 /workspace/coverage/default/34.lc_ctrl_jtag_access.552398632 Aug 14 05:31:32 PM PDT 24 Aug 14 05:31:47 PM PDT 24 1196793178 ps
T826 /workspace/coverage/default/30.lc_ctrl_security_escalation.28579933 Aug 14 05:31:06 PM PDT 24 Aug 14 05:31:14 PM PDT 24 300299202 ps
T827 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1805266474 Aug 14 05:29:50 PM PDT 24 Aug 14 05:30:03 PM PDT 24 2053577796 ps
T828 /workspace/coverage/default/31.lc_ctrl_stress_all.173104547 Aug 14 05:31:22 PM PDT 24 Aug 14 05:31:59 PM PDT 24 2283806712 ps
T829 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.626673904 Aug 14 05:30:43 PM PDT 24 Aug 14 05:30:44 PM PDT 24 54175143 ps
T830 /workspace/coverage/default/9.lc_ctrl_jtag_errors.330093299 Aug 14 05:30:08 PM PDT 24 Aug 14 05:31:08 PM PDT 24 8815589756 ps
T831 /workspace/coverage/default/16.lc_ctrl_jtag_errors.1400747754 Aug 14 05:30:26 PM PDT 24 Aug 14 05:30:59 PM PDT 24 4011429969 ps
T832 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2066895583 Aug 14 05:30:17 PM PDT 24 Aug 14 05:30:20 PM PDT 24 465377588 ps
T833 /workspace/coverage/default/45.lc_ctrl_alert_test.3510285755 Aug 14 05:31:44 PM PDT 24 Aug 14 05:31:45 PM PDT 24 82003065 ps
T834 /workspace/coverage/default/45.lc_ctrl_jtag_access.2837155094 Aug 14 05:31:41 PM PDT 24 Aug 14 05:31:45 PM PDT 24 497293198 ps
T835 /workspace/coverage/default/48.lc_ctrl_state_failure.1971571558 Aug 14 05:31:47 PM PDT 24 Aug 14 05:32:11 PM PDT 24 146546878 ps
T836 /workspace/coverage/default/22.lc_ctrl_jtag_access.3559181750 Aug 14 05:30:48 PM PDT 24 Aug 14 05:30:49 PM PDT 24 73332631 ps
T837 /workspace/coverage/default/17.lc_ctrl_state_post_trans.4115001746 Aug 14 05:30:32 PM PDT 24 Aug 14 05:30:38 PM PDT 24 164573203 ps
T838 /workspace/coverage/default/3.lc_ctrl_jtag_priority.2291454158 Aug 14 05:29:40 PM PDT 24 Aug 14 05:29:45 PM PDT 24 642780175 ps
T839 /workspace/coverage/default/29.lc_ctrl_stress_all.3480172165 Aug 14 05:31:04 PM PDT 24 Aug 14 05:34:20 PM PDT 24 19694463691 ps
T840 /workspace/coverage/default/48.lc_ctrl_prog_failure.924489736 Aug 14 05:31:52 PM PDT 24 Aug 14 05:31:54 PM PDT 24 53558263 ps
T841 /workspace/coverage/default/26.lc_ctrl_errors.991011598 Aug 14 05:30:55 PM PDT 24 Aug 14 05:31:07 PM PDT 24 1364526504 ps
T842 /workspace/coverage/default/15.lc_ctrl_security_escalation.656729476 Aug 14 05:30:27 PM PDT 24 Aug 14 05:30:43 PM PDT 24 886342161 ps
T843 /workspace/coverage/default/11.lc_ctrl_sec_mubi.4214224750 Aug 14 05:30:09 PM PDT 24 Aug 14 05:30:23 PM PDT 24 314194055 ps
T844 /workspace/coverage/default/23.lc_ctrl_errors.1338869589 Aug 14 05:30:53 PM PDT 24 Aug 14 05:31:07 PM PDT 24 569282265 ps
T845 /workspace/coverage/default/32.lc_ctrl_sec_mubi.2713208883 Aug 14 05:31:13 PM PDT 24 Aug 14 05:31:23 PM PDT 24 245341053 ps
T846 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3430260958 Aug 14 05:31:42 PM PDT 24 Aug 14 05:31:51 PM PDT 24 1365779483 ps
T847 /workspace/coverage/default/43.lc_ctrl_state_failure.1353205064 Aug 14 05:31:42 PM PDT 24 Aug 14 05:32:07 PM PDT 24 728647351 ps
T848 /workspace/coverage/default/48.lc_ctrl_errors.3574368351 Aug 14 05:31:48 PM PDT 24 Aug 14 05:32:00 PM PDT 24 1326768459 ps
T849 /workspace/coverage/default/12.lc_ctrl_state_post_trans.3200508895 Aug 14 05:30:16 PM PDT 24 Aug 14 05:30:24 PM PDT 24 231335802 ps
T850 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1762259113 Aug 14 05:30:25 PM PDT 24 Aug 14 05:30:37 PM PDT 24 5012729562 ps
T851 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1135799676 Aug 14 05:29:19 PM PDT 24 Aug 14 05:29:41 PM PDT 24 5666129858 ps
T852 /workspace/coverage/default/7.lc_ctrl_jtag_access.652318854 Aug 14 05:29:59 PM PDT 24 Aug 14 05:30:08 PM PDT 24 7282349759 ps
T853 /workspace/coverage/default/34.lc_ctrl_stress_all.1493760923 Aug 14 05:31:24 PM PDT 24 Aug 14 05:32:55 PM PDT 24 2547391261 ps
T854 /workspace/coverage/default/2.lc_ctrl_alert_test.1816675020 Aug 14 05:29:37 PM PDT 24 Aug 14 05:29:38 PM PDT 24 60116395 ps
T855 /workspace/coverage/default/39.lc_ctrl_sec_mubi.2324679068 Aug 14 05:31:32 PM PDT 24 Aug 14 05:31:43 PM PDT 24 763928317 ps
T110 /workspace/coverage/default/32.lc_ctrl_stress_all.2318490649 Aug 14 05:31:13 PM PDT 24 Aug 14 05:36:53 PM PDT 24 33278293575 ps
T856 /workspace/coverage/default/16.lc_ctrl_sec_mubi.3903549159 Aug 14 05:30:26 PM PDT 24 Aug 14 05:30:39 PM PDT 24 2062064034 ps
T857 /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1945961409 Aug 14 05:29:21 PM PDT 24 Aug 14 05:29:42 PM PDT 24 2748771586 ps
T858 /workspace/coverage/default/0.lc_ctrl_smoke.3468777898 Aug 14 05:29:26 PM PDT 24 Aug 14 05:29:29 PM PDT 24 327923188 ps
T859 /workspace/coverage/default/33.lc_ctrl_smoke.4288189494 Aug 14 05:31:12 PM PDT 24 Aug 14 05:31:15 PM PDT 24 37953303 ps
T860 /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2019059208 Aug 14 05:31:32 PM PDT 24 Aug 14 05:31:44 PM PDT 24 456597714 ps
T861 /workspace/coverage/default/16.lc_ctrl_stress_all.3243620645 Aug 14 05:30:24 PM PDT 24 Aug 14 05:32:20 PM PDT 24 6976605903 ps
T862 /workspace/coverage/default/23.lc_ctrl_sec_token_digest.464597832 Aug 14 05:30:55 PM PDT 24 Aug 14 05:31:09 PM PDT 24 808582609 ps
T863 /workspace/coverage/default/21.lc_ctrl_prog_failure.1267972602 Aug 14 05:30:45 PM PDT 24 Aug 14 05:30:47 PM PDT 24 23380803 ps
T864 /workspace/coverage/default/14.lc_ctrl_smoke.2794684411 Aug 14 05:30:22 PM PDT 24 Aug 14 05:30:29 PM PDT 24 195483093 ps
T865 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3203519612 Aug 14 05:29:38 PM PDT 24 Aug 14 05:29:45 PM PDT 24 218265411 ps
T866 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2635771553 Aug 14 05:31:31 PM PDT 24 Aug 14 05:31:32 PM PDT 24 136058728 ps
T867 /workspace/coverage/default/18.lc_ctrl_alert_test.3219618460 Aug 14 05:30:39 PM PDT 24 Aug 14 05:30:40 PM PDT 24 13206718 ps
T868 /workspace/coverage/default/23.lc_ctrl_state_post_trans.4125625719 Aug 14 05:30:53 PM PDT 24 Aug 14 05:30:56 PM PDT 24 55356303 ps
T869 /workspace/coverage/default/44.lc_ctrl_state_failure.1832473418 Aug 14 05:31:41 PM PDT 24 Aug 14 05:32:05 PM PDT 24 308776125 ps
T870 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2730444651 Aug 14 05:30:09 PM PDT 24 Aug 14 05:30:18 PM PDT 24 1242058343 ps
T871 /workspace/coverage/default/6.lc_ctrl_jtag_priority.928172583 Aug 14 05:29:47 PM PDT 24 Aug 14 05:29:50 PM PDT 24 395056772 ps
T118 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3675744914 Aug 14 04:35:42 PM PDT 24 Aug 14 04:35:44 PM PDT 24 186820483 ps
T111 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3877460192 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:23 PM PDT 24 145716506 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2567566530 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:07 PM PDT 24 22588139 ps
T124 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.64781257 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:08 PM PDT 24 24866720 ps
T112 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1333492254 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:11 PM PDT 24 65068905 ps
T113 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.872351492 Aug 14 04:35:05 PM PDT 24 Aug 14 04:35:07 PM PDT 24 66398091 ps
T142 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.678956383 Aug 14 04:35:12 PM PDT 24 Aug 14 04:35:20 PM PDT 24 2295825829 ps
T198 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.477174151 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:15 PM PDT 24 38508495 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4265666490 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:17 PM PDT 24 69141322 ps
T116 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1087978482 Aug 14 04:35:26 PM PDT 24 Aug 14 04:35:29 PM PDT 24 231718819 ps
T169 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3443009986 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:15 PM PDT 24 14923143 ps
T199 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3597176360 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:09 PM PDT 24 106215710 ps
T872 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3740512034 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:18 PM PDT 24 47882701 ps
T117 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.485401100 Aug 14 04:35:30 PM PDT 24 Aug 14 04:35:32 PM PDT 24 113004606 ps
T120 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.188427601 Aug 14 04:35:33 PM PDT 24 Aug 14 04:35:36 PM PDT 24 74554370 ps
T140 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1025401414 Aug 14 04:35:15 PM PDT 24 Aug 14 04:35:17 PM PDT 24 39878275 ps
T184 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4205436548 Aug 14 04:35:05 PM PDT 24 Aug 14 04:35:06 PM PDT 24 46580751 ps
T170 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.382038603 Aug 14 04:35:02 PM PDT 24 Aug 14 04:35:04 PM PDT 24 34191674 ps
T128 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2809006866 Aug 14 04:35:21 PM PDT 24 Aug 14 04:35:23 PM PDT 24 42544650 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.716740583 Aug 14 04:34:54 PM PDT 24 Aug 14 04:34:56 PM PDT 24 99523522 ps
T873 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2637933781 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:10 PM PDT 24 170342342 ps
T141 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3585339100 Aug 14 04:34:52 PM PDT 24 Aug 14 04:34:55 PM PDT 24 84638919 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1095954031 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:11 PM PDT 24 1117719207 ps
T122 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2855092888 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:23 PM PDT 24 197336767 ps
T132 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1660352839 Aug 14 04:35:49 PM PDT 24 Aug 14 04:35:51 PM PDT 24 339323782 ps
T200 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.783029042 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:30 PM PDT 24 117650262 ps
T875 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.927037605 Aug 14 04:35:12 PM PDT 24 Aug 14 04:35:15 PM PDT 24 750204048 ps
T185 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3376042271 Aug 14 04:34:58 PM PDT 24 Aug 14 04:34:59 PM PDT 24 37877332 ps
T876 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2882415620 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:18 PM PDT 24 593382814 ps
T201 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2459740204 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:09 PM PDT 24 15327028 ps
T877 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4269474555 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:09 PM PDT 24 228090139 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1396315730 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:41 PM PDT 24 1031928512 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1270235118 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:10 PM PDT 24 76823720 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3436710556 Aug 14 04:35:01 PM PDT 24 Aug 14 04:35:04 PM PDT 24 256043548 ps
T138 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.405261047 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:11 PM PDT 24 195627356 ps
T156 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3925742146 Aug 14 04:35:16 PM PDT 24 Aug 14 04:35:18 PM PDT 24 112170284 ps
T881 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1729833797 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:08 PM PDT 24 43753378 ps
T882 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3048964722 Aug 14 04:35:30 PM PDT 24 Aug 14 04:35:56 PM PDT 24 1100495603 ps
T883 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.865122688 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:11 PM PDT 24 462783390 ps
T202 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2021173490 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:15 PM PDT 24 20276251 ps
T203 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1205199656 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:18 PM PDT 24 14856420 ps
T125 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2138749160 Aug 14 04:35:12 PM PDT 24 Aug 14 04:35:15 PM PDT 24 156663051 ps
T884 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1186400594 Aug 14 04:35:39 PM PDT 24 Aug 14 04:35:42 PM PDT 24 54675702 ps
T885 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.64551220 Aug 14 04:35:26 PM PDT 24 Aug 14 04:35:28 PM PDT 24 219962619 ps
T204 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1626656926 Aug 14 04:35:24 PM PDT 24 Aug 14 04:35:25 PM PDT 24 58014096 ps
T886 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.154012532 Aug 14 04:35:45 PM PDT 24 Aug 14 04:35:46 PM PDT 24 16899323 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1837194057 Aug 14 04:34:57 PM PDT 24 Aug 14 04:35:00 PM PDT 24 410261032 ps
T888 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.28832877 Aug 14 04:35:21 PM PDT 24 Aug 14 04:35:22 PM PDT 24 27678514 ps
T205 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2526093743 Aug 14 04:35:24 PM PDT 24 Aug 14 04:35:26 PM PDT 24 58948819 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2538309664 Aug 14 04:35:13 PM PDT 24 Aug 14 04:35:14 PM PDT 24 59596893 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1789970823 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:07 PM PDT 24 142167182 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3892770427 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:08 PM PDT 24 259794427 ps
T892 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2696618991 Aug 14 04:35:13 PM PDT 24 Aug 14 04:35:16 PM PDT 24 194752561 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.689562836 Aug 14 04:34:53 PM PDT 24 Aug 14 04:34:56 PM PDT 24 88174253 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.626811697 Aug 14 04:35:05 PM PDT 24 Aug 14 04:35:10 PM PDT 24 2360053483 ps
T134 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2879644144 Aug 14 04:35:23 PM PDT 24 Aug 14 04:35:26 PM PDT 24 377228495 ps
T895 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4174019681 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:09 PM PDT 24 1411854583 ps
T896 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3611996055 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:19 PM PDT 24 67337619 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1204261518 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:19 PM PDT 24 161191503 ps
T898 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3960243086 Aug 14 04:35:25 PM PDT 24 Aug 14 04:35:27 PM PDT 24 156506345 ps
T186 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3018373450 Aug 14 04:35:09 PM PDT 24 Aug 14 04:35:11 PM PDT 24 303005512 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2742662563 Aug 14 04:35:03 PM PDT 24 Aug 14 04:35:15 PM PDT 24 447759099 ps
T900 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3164600199 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:20 PM PDT 24 98260753 ps
T187 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1597232268 Aug 14 04:35:12 PM PDT 24 Aug 14 04:35:13 PM PDT 24 11511440 ps
T901 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3042456037 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:22 PM PDT 24 1734263978 ps
T902 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3887930936 Aug 14 04:35:09 PM PDT 24 Aug 14 04:35:10 PM PDT 24 21730477 ps
T903 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3470321513 Aug 14 04:35:28 PM PDT 24 Aug 14 04:35:29 PM PDT 24 48597288 ps
T904 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.343071783 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:31 PM PDT 24 45119553 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2812823871 Aug 14 04:35:02 PM PDT 24 Aug 14 04:35:03 PM PDT 24 33304085 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1616879686 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:13 PM PDT 24 19597592 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2256381769 Aug 14 04:35:04 PM PDT 24 Aug 14 04:35:05 PM PDT 24 16490202 ps
T908 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4101247735 Aug 14 04:35:20 PM PDT 24 Aug 14 04:35:38 PM PDT 24 702333087 ps
T909 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2976417684 Aug 14 04:35:43 PM PDT 24 Aug 14 04:35:44 PM PDT 24 142008616 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1937072966 Aug 14 04:35:16 PM PDT 24 Aug 14 04:35:18 PM PDT 24 212258506 ps
T911 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.960011841 Aug 14 04:35:13 PM PDT 24 Aug 14 04:35:15 PM PDT 24 77814614 ps
T912 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3823824384 Aug 14 04:35:03 PM PDT 24 Aug 14 04:35:18 PM PDT 24 10181738538 ps
T126 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2611497761 Aug 14 04:35:51 PM PDT 24 Aug 14 04:35:54 PM PDT 24 107919084 ps
T913 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2471200017 Aug 14 04:35:16 PM PDT 24 Aug 14 04:35:17 PM PDT 24 46139906 ps
T914 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.758027661 Aug 14 04:35:09 PM PDT 24 Aug 14 04:35:15 PM PDT 24 3779743341 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2399095297 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:19 PM PDT 24 12312462 ps
T188 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2558854303 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:30 PM PDT 24 76494807 ps
T189 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4106635765 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:20 PM PDT 24 67130795 ps
T916 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3557608157 Aug 14 04:35:04 PM PDT 24 Aug 14 04:35:06 PM PDT 24 52213240 ps
T917 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1890522437 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:13 PM PDT 24 58867340 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.799027934 Aug 14 04:35:05 PM PDT 24 Aug 14 04:35:12 PM PDT 24 1065103703 ps
T919 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.313129999 Aug 14 04:35:27 PM PDT 24 Aug 14 04:35:28 PM PDT 24 359428299 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1470883712 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:17 PM PDT 24 2053548170 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1618189011 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:19 PM PDT 24 1252273941 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4069435878 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:22 PM PDT 24 1546566818 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.533253437 Aug 14 04:35:12 PM PDT 24 Aug 14 04:35:13 PM PDT 24 41267452 ps
T924 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.954570933 Aug 14 04:34:57 PM PDT 24 Aug 14 04:34:58 PM PDT 24 25507295 ps
T925 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.698883331 Aug 14 04:35:33 PM PDT 24 Aug 14 04:35:52 PM PDT 24 2767850437 ps
T926 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2289048685 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:09 PM PDT 24 21503098 ps
T927 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.462026382 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:13 PM PDT 24 331270687 ps
T137 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3590834472 Aug 14 04:34:51 PM PDT 24 Aug 14 04:34:54 PM PDT 24 243047659 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2928843240 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:08 PM PDT 24 17709881 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.485084191 Aug 14 04:35:27 PM PDT 24 Aug 14 04:35:30 PM PDT 24 389062850 ps
T123 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.419732057 Aug 14 04:35:15 PM PDT 24 Aug 14 04:35:19 PM PDT 24 302884156 ps
T190 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3139328347 Aug 14 04:35:25 PM PDT 24 Aug 14 04:35:26 PM PDT 24 32750878 ps
T191 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2805076864 Aug 14 04:35:01 PM PDT 24 Aug 14 04:35:02 PM PDT 24 16807821 ps
T930 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1708672117 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:10 PM PDT 24 537327403 ps
T931 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3973371923 Aug 14 04:35:16 PM PDT 24 Aug 14 04:35:18 PM PDT 24 19241266 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3082744083 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:09 PM PDT 24 80135529 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2941400658 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:20 PM PDT 24 1202039328 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1118906089 Aug 14 04:35:36 PM PDT 24 Aug 14 04:35:51 PM PDT 24 968007905 ps
T135 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1250330503 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:13 PM PDT 24 255442214 ps
T127 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1533474779 Aug 14 04:34:55 PM PDT 24 Aug 14 04:34:59 PM PDT 24 119031253 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2303091883 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:08 PM PDT 24 51970856 ps
T936 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4110791265 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:10 PM PDT 24 40857651 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2423733638 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:10 PM PDT 24 59569825 ps
T938 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.943296212 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:21 PM PDT 24 61146547 ps
T939 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.573944721 Aug 14 04:35:44 PM PDT 24 Aug 14 04:35:45 PM PDT 24 16396917 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3519079255 Aug 14 04:35:27 PM PDT 24 Aug 14 04:35:33 PM PDT 24 43501443 ps
T192 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1215514745 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:18 PM PDT 24 11793172 ps
T133 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1439594669 Aug 14 04:35:22 PM PDT 24 Aug 14 04:35:25 PM PDT 24 64150400 ps
T941 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3624302620 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:17 PM PDT 24 117611868 ps
T942 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3535773589 Aug 14 04:35:36 PM PDT 24 Aug 14 04:35:37 PM PDT 24 21041586 ps
T943 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2715873394 Aug 14 04:34:53 PM PDT 24 Aug 14 04:34:57 PM PDT 24 545690497 ps
T944 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3525175721 Aug 14 04:35:26 PM PDT 24 Aug 14 04:35:28 PM PDT 24 192806788 ps
T945 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2288418019 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:11 PM PDT 24 233185372 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.608240964 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:08 PM PDT 24 169370998 ps
T947 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3898735183 Aug 14 04:35:10 PM PDT 24 Aug 14 04:35:12 PM PDT 24 50524797 ps
T948 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1501388292 Aug 14 04:34:51 PM PDT 24 Aug 14 04:34:54 PM PDT 24 421535117 ps
T949 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3420092996 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:19 PM PDT 24 353626248 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3056741064 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:08 PM PDT 24 21312170 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3272203672 Aug 14 04:35:26 PM PDT 24 Aug 14 04:35:28 PM PDT 24 77758868 ps
T139 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1438036878 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:19 PM PDT 24 930499895 ps
T952 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1843892417 Aug 14 04:35:05 PM PDT 24 Aug 14 04:35:07 PM PDT 24 97210281 ps
T193 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3304966018 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:20 PM PDT 24 15572336 ps
T953 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2466088325 Aug 14 04:35:01 PM PDT 24 Aug 14 04:35:02 PM PDT 24 79102935 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1642767963 Aug 14 04:35:04 PM PDT 24 Aug 14 04:35:07 PM PDT 24 50668614 ps
T955 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3662406802 Aug 14 04:35:10 PM PDT 24 Aug 14 04:35:12 PM PDT 24 234533071 ps
T956 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3478432162 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:19 PM PDT 24 71835410 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4253660589 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:29 PM PDT 24 1523042898 ps
T194 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3197830605 Aug 14 04:35:24 PM PDT 24 Aug 14 04:35:25 PM PDT 24 18957508 ps
T136 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3052954593 Aug 14 04:35:18 PM PDT 24 Aug 14 04:35:21 PM PDT 24 139652960 ps
T958 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.612117687 Aug 14 04:35:15 PM PDT 24 Aug 14 04:35:18 PM PDT 24 165954369 ps
T959 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2822789664 Aug 14 04:34:56 PM PDT 24 Aug 14 04:34:59 PM PDT 24 93756527 ps
T960 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.511751923 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:20 PM PDT 24 2612701304 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2314062434 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:07 PM PDT 24 337709480 ps
T962 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3077473223 Aug 14 04:35:44 PM PDT 24 Aug 14 04:35:45 PM PDT 24 14923210 ps
T963 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.310617082 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:25 PM PDT 24 18712464 ps
T195 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2602493341 Aug 14 04:35:12 PM PDT 24 Aug 14 04:35:13 PM PDT 24 28273369 ps
T964 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2970539168 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:14 PM PDT 24 187079419 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1424651772 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:17 PM PDT 24 2901499196 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2878551212 Aug 14 04:35:13 PM PDT 24 Aug 14 04:35:14 PM PDT 24 17228598 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3964581073 Aug 14 04:35:13 PM PDT 24 Aug 14 04:35:18 PM PDT 24 602348826 ps
T130 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3725815489 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:16 PM PDT 24 82261398 ps
T968 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2929775194 Aug 14 04:35:14 PM PDT 24 Aug 14 04:35:15 PM PDT 24 127024907 ps
T969 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1146905495 Aug 14 04:35:48 PM PDT 24 Aug 14 04:35:49 PM PDT 24 28772224 ps
T970 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2797726199 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:20 PM PDT 24 28278222 ps
T971 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2527767966 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:18 PM PDT 24 22961745 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2018763910 Aug 14 04:35:13 PM PDT 24 Aug 14 04:35:28 PM PDT 24 2179236792 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.763825310 Aug 14 04:35:09 PM PDT 24 Aug 14 04:35:13 PM PDT 24 118891150 ps
T974 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2305164639 Aug 14 04:35:15 PM PDT 24 Aug 14 04:35:17 PM PDT 24 37278558 ps
T196 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2663117047 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:12 PM PDT 24 43949910 ps
T975 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.867332727 Aug 14 04:34:51 PM PDT 24 Aug 14 04:34:52 PM PDT 24 239458036 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1263770371 Aug 14 04:35:04 PM PDT 24 Aug 14 04:35:06 PM PDT 24 45438097 ps
T977 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.816994904 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:08 PM PDT 24 219612608 ps
T131 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4121407281 Aug 14 04:35:29 PM PDT 24 Aug 14 04:35:32 PM PDT 24 108987015 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3677239577 Aug 14 04:35:00 PM PDT 24 Aug 14 04:35:01 PM PDT 24 13597457 ps
T979 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2196343242 Aug 14 04:35:21 PM PDT 24 Aug 14 04:35:23 PM PDT 24 96181445 ps
T980 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3096442194 Aug 14 04:35:03 PM PDT 24 Aug 14 04:35:05 PM PDT 24 154775519 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.696340167 Aug 14 04:34:53 PM PDT 24 Aug 14 04:34:54 PM PDT 24 23103055 ps
T982 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1781548470 Aug 14 04:35:03 PM PDT 24 Aug 14 04:35:05 PM PDT 24 892977291 ps
T983 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.770820844 Aug 14 04:35:16 PM PDT 24 Aug 14 04:35:18 PM PDT 24 26159565 ps
T984 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2026313408 Aug 14 04:35:24 PM PDT 24 Aug 14 04:35:26 PM PDT 24 15502584 ps
T985 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.547623309 Aug 14 04:35:24 PM PDT 24 Aug 14 04:35:26 PM PDT 24 115604928 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.708955745 Aug 14 04:35:23 PM PDT 24 Aug 14 04:35:25 PM PDT 24 32604727 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2026353034 Aug 14 04:35:09 PM PDT 24 Aug 14 04:35:11 PM PDT 24 26727815 ps
T197 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1154078551 Aug 14 04:35:02 PM PDT 24 Aug 14 04:35:04 PM PDT 24 27685824 ps
T988 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1799742648 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:09 PM PDT 24 62715248 ps
T989 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3287254010 Aug 14 04:35:39 PM PDT 24 Aug 14 04:35:40 PM PDT 24 37388046 ps
T990 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4067041196 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:09 PM PDT 24 49260627 ps
T991 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.729435440 Aug 14 04:35:30 PM PDT 24 Aug 14 04:35:32 PM PDT 24 142414150 ps
T992 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1081780289 Aug 14 04:35:08 PM PDT 24 Aug 14 04:35:10 PM PDT 24 82011206 ps
T993 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.271501362 Aug 14 04:35:36 PM PDT 24 Aug 14 04:35:41 PM PDT 24 735551507 ps
T994 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.706876007 Aug 14 04:35:07 PM PDT 24 Aug 14 04:35:11 PM PDT 24 219389120 ps
T995 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1031470467 Aug 14 04:35:11 PM PDT 24 Aug 14 04:35:12 PM PDT 24 40203062 ps
T996 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1433982112 Aug 14 04:35:19 PM PDT 24 Aug 14 04:35:21 PM PDT 24 238847863 ps
T129 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3993479865 Aug 14 04:35:17 PM PDT 24 Aug 14 04:35:20 PM PDT 24 164836172 ps
T997 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3631360314 Aug 14 04:35:04 PM PDT 24 Aug 14 04:35:06 PM PDT 24 78890961 ps
T998 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3586988597 Aug 14 04:34:57 PM PDT 24 Aug 14 04:34:58 PM PDT 24 207454725 ps
T999 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.947439746 Aug 14 04:35:06 PM PDT 24 Aug 14 04:35:07 PM PDT 24 24338105 ps
T1000 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2578892700 Aug 14 04:35:15 PM PDT 24 Aug 14 04:35:17 PM PDT 24 90908037 ps

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1933966117
Short name T4
Test name
Test status
Simulation time 5578733805 ps
CPU time 127.46 seconds
Started Aug 14 05:31:28 PM PDT 24
Finished Aug 14 05:33:36 PM PDT 24
Peak memory 283728 kb
Host smart-6b978c9a-cf8c-482b-bf0b-da07ab1a74b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933966117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1933966117
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1660434030
Short name T15
Test name
Test status
Simulation time 384131605 ps
CPU time 14.03 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:29:55 PM PDT 24
Peak memory 225356 kb
Host smart-33f002d6-ee25-437d-98e9-a60bdb923cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660434030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1660434030
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2006572571
Short name T14
Test name
Test status
Simulation time 85777485026 ps
CPU time 144.18 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:33:27 PM PDT 24
Peak memory 316500 kb
Host smart-9f3c05f1-5964-4953-be0b-89659742b7ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006572571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2006572571
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.124090688
Short name T17
Test name
Test status
Simulation time 1219802458 ps
CPU time 15.72 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:19 PM PDT 24
Peak memory 226016 kb
Host smart-0d1c3ed3-7a3f-4b40-a3e5-1f85ca5998f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124090688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.124090688
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1573808902
Short name T50
Test name
Test status
Simulation time 9102657349 ps
CPU time 32.34 seconds
Started Aug 14 05:31:14 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 240588 kb
Host smart-2b08a27d-a48f-4806-935a-374b387b3b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1573808902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1573808902
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3877460192
Short name T111
Test name
Test status
Simulation time 145716506 ps
CPU time 5.22 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 218136 kb
Host smart-0817f6cd-b6d1-4223-8564-21ddd112464f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877460192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3877460192
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2911930815
Short name T44
Test name
Test status
Simulation time 460269870 ps
CPU time 34.46 seconds
Started Aug 14 05:29:28 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 270560 kb
Host smart-4ade9f23-787f-46c0-8d92-a629d315ca08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911930815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2911930815
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4152972316
Short name T1
Test name
Test status
Simulation time 348999588 ps
CPU time 5.2 seconds
Started Aug 14 05:30:21 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 217340 kb
Host smart-0b1f7734-356b-451f-9e2b-8d6f9c99f6f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152972316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4152972316
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2750129178
Short name T213
Test name
Test status
Simulation time 435494379 ps
CPU time 9.52 seconds
Started Aug 14 05:30:50 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 225352 kb
Host smart-ed7510f4-8048-4746-9ae8-a33391bf8358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750129178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2750129178
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1333492254
Short name T112
Test name
Test status
Simulation time 65068905 ps
CPU time 2.73 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 218224 kb
Host smart-31ce0c6d-2490-4e74-a008-85ded10c8175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333492254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1333492254
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3586564497
Short name T65
Test name
Test status
Simulation time 16695094735 ps
CPU time 249.7 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:34:45 PM PDT 24
Peak memory 267668 kb
Host smart-c79582ee-e474-404f-91e8-c72a518463cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586564497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3586564497
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.770392626
Short name T19
Test name
Test status
Simulation time 3386078765 ps
CPU time 14.08 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:30:13 PM PDT 24
Peak memory 218944 kb
Host smart-6c48c8ce-b99c-4d3b-8670-4426ea6774ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770392626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.770392626
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1544802249
Short name T85
Test name
Test status
Simulation time 49610915 ps
CPU time 0.88 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:29:52 PM PDT 24
Peak memory 208820 kb
Host smart-a180efc8-3656-4b7e-a3a6-c08aa32da105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544802249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1544802249
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.927037605
Short name T875
Test name
Test status
Simulation time 750204048 ps
CPU time 2.64 seconds
Started Aug 14 04:35:12 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 219384 kb
Host smart-95f4d526-3542-40a7-aa6c-5b99742a1e84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927037
605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.927037605
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1597232268
Short name T187
Test name
Test status
Simulation time 11511440 ps
CPU time 0.96 seconds
Started Aug 14 04:35:12 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 209856 kb
Host smart-070cbc54-e457-4462-8e00-9f879c970142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597232268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1597232268
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2138749160
Short name T125
Test name
Test status
Simulation time 156663051 ps
CPU time 2.8 seconds
Started Aug 14 04:35:12 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 222632 kb
Host smart-4f70fcaf-957c-4ccf-89a1-3fefa2992bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138749160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2138749160
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3674567323
Short name T590
Test name
Test status
Simulation time 1287758905 ps
CPU time 13.95 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:31:38 PM PDT 24
Peak memory 226100 kb
Host smart-50d7d399-dbdb-49db-92b1-8490f62276e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674567323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3674567323
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2611497761
Short name T126
Test name
Test status
Simulation time 107919084 ps
CPU time 2.8 seconds
Started Aug 14 04:35:51 PM PDT 24
Finished Aug 14 04:35:54 PM PDT 24
Peak memory 223040 kb
Host smart-a1a0ab78-d1d9-488c-ad48-7e2a90d27110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611497761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2611497761
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3052954593
Short name T136
Test name
Test status
Simulation time 139652960 ps
CPU time 2.59 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 223080 kb
Host smart-4bd8197a-11f8-46a3-9bc3-97084474fc8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052954593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3052954593
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.22874745
Short name T108
Test name
Test status
Simulation time 28834678 ps
CPU time 0.85 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:37 PM PDT 24
Peak memory 211836 kb
Host smart-8f0d9bad-e207-41ba-9e11-d99334b97db6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_volatile_unlock_smoke.22874745
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2855092888
Short name T122
Test name
Test status
Simulation time 197336767 ps
CPU time 4.19 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 218140 kb
Host smart-68065819-e137-4d13-8ca6-5ffc8221fe4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855092888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2855092888
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2318490649
Short name T110
Test name
Test status
Simulation time 33278293575 ps
CPU time 339.91 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:36:53 PM PDT 24
Peak memory 277764 kb
Host smart-cd215c45-eb31-4591-8f8d-87f1bea08962
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318490649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2318490649
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4121407281
Short name T131
Test name
Test status
Simulation time 108987015 ps
CPU time 2.89 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:32 PM PDT 24
Peak memory 222612 kb
Host smart-e8714497-da73-4ad3-8e9a-43c70e3169b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121407281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4121407281
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3376042271
Short name T185
Test name
Test status
Simulation time 37877332 ps
CPU time 0.81 seconds
Started Aug 14 04:34:58 PM PDT 24
Finished Aug 14 04:34:59 PM PDT 24
Peak memory 209708 kb
Host smart-ef7d7d7d-cfef-4a80-be71-7dfcd33feaf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376042271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3376042271
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2821644556
Short name T90
Test name
Test status
Simulation time 8664410164 ps
CPU time 76.58 seconds
Started Aug 14 05:31:39 PM PDT 24
Finished Aug 14 05:32:56 PM PDT 24
Peak memory 259284 kb
Host smart-255f4d1d-c18a-4492-8129-0aa3ffc82326
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2821644556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2821644556
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.768292015
Short name T5
Test name
Test status
Simulation time 2348580757 ps
CPU time 4.54 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 217648 kb
Host smart-c751d6eb-6872-410c-ac9e-cc23b12e03f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768292015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
768292015
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1087978482
Short name T116
Test name
Test status
Simulation time 231718819 ps
CPU time 2.5 seconds
Started Aug 14 04:35:26 PM PDT 24
Finished Aug 14 04:35:29 PM PDT 24
Peak memory 218200 kb
Host smart-8f40486e-4d72-4f81-9ffd-82c852507051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087978482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1087978482
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3706478696
Short name T209
Test name
Test status
Simulation time 12732531 ps
CPU time 0.82 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:21 PM PDT 24
Peak memory 208520 kb
Host smart-62c242f6-0a15-40a0-8f57-df45f2588ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706478696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3706478696
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.547851973
Short name T210
Test name
Test status
Simulation time 42088576 ps
CPU time 0.83 seconds
Started Aug 14 05:29:31 PM PDT 24
Finished Aug 14 05:29:32 PM PDT 24
Peak memory 208924 kb
Host smart-ed3894eb-14ef-4d8e-a53b-ce4688992b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547851973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.547851973
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.4084269333
Short name T532
Test name
Test status
Simulation time 282203316 ps
CPU time 8.64 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:18 PM PDT 24
Peak memory 226080 kb
Host smart-aa7a1421-1342-428b-af84-2fd69089eec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084269333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.4084269333
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1272638049
Short name T211
Test name
Test status
Simulation time 33814301 ps
CPU time 0.84 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 208952 kb
Host smart-191f9a47-85f7-42c5-a1c3-4e56ef2d6999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272638049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1272638049
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3548573468
Short name T61
Test name
Test status
Simulation time 11880130 ps
CPU time 0.88 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:29:41 PM PDT 24
Peak memory 208700 kb
Host smart-875a1f16-752a-4506-82ea-cdf85883041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548573468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3548573468
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.405261047
Short name T138
Test name
Test status
Simulation time 195627356 ps
CPU time 2.81 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 222880 kb
Host smart-ec5c2e67-fbbe-46f7-8c14-e49866e3a092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405261047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.405261047
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3993479865
Short name T129
Test name
Test status
Simulation time 164836172 ps
CPU time 3.14 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 223012 kb
Host smart-39ddef5e-cc24-4f83-8501-5f3351dac16e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993479865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3993479865
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1250330503
Short name T135
Test name
Test status
Simulation time 255442214 ps
CPU time 1.88 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 222604 kb
Host smart-8052d120-ffe7-4019-814c-49587094d0df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250330503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1250330503
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3886857629
Short name T37
Test name
Test status
Simulation time 7237948801 ps
CPU time 163.07 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:33:38 PM PDT 24
Peak memory 239052 kb
Host smart-9adef3ac-eb57-4bf2-a731-3e0ae1b22b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886857629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3886857629
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.917544740
Short name T36
Test name
Test status
Simulation time 38801080842 ps
CPU time 428.31 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:38:36 PM PDT 24
Peak memory 226136 kb
Host smart-a9e73d9e-8ce0-41fa-8706-474c0e68c500
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917544740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.917544740
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3798730644
Short name T10
Test name
Test status
Simulation time 72113272 ps
CPU time 2.68 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:31:27 PM PDT 24
Peak memory 222396 kb
Host smart-0dd63ef2-cfa8-416f-a66e-3cc7c2bc67df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798730644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3798730644
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3426466269
Short name T22
Test name
Test status
Simulation time 7786482672 ps
CPU time 81.73 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 277788 kb
Host smart-fb2c84f9-a424-4fb9-ac1d-cf0a3d9d4ffa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426466269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3426466269
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2256381769
Short name T907
Test name
Test status
Simulation time 16490202 ps
CPU time 1.04 seconds
Started Aug 14 04:35:04 PM PDT 24
Finished Aug 14 04:35:05 PM PDT 24
Peak memory 209804 kb
Host smart-a9e8dfe5-669d-4be0-ad8c-852b7c65a1dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256381769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2256381769
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3892770427
Short name T891
Test name
Test status
Simulation time 259794427 ps
CPU time 1.94 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 209820 kb
Host smart-fe98b475-b444-4dec-8d85-5aeea1fa83ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892770427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3892770427
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2805076864
Short name T191
Test name
Test status
Simulation time 16807821 ps
CPU time 1.29 seconds
Started Aug 14 04:35:01 PM PDT 24
Finished Aug 14 04:35:02 PM PDT 24
Peak memory 219668 kb
Host smart-42bb58ce-c48a-4004-981c-f82c6235e962
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805076864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2805076864
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1616879686
Short name T906
Test name
Test status
Simulation time 19597592 ps
CPU time 1.61 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 219332 kb
Host smart-02ba6b29-b4f9-47d3-9f83-42be0785a7bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616879686 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1616879686
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3586988597
Short name T998
Test name
Test status
Simulation time 207454725 ps
CPU time 1.03 seconds
Started Aug 14 04:34:57 PM PDT 24
Finished Aug 14 04:34:58 PM PDT 24
Peak memory 209784 kb
Host smart-4b435f5c-63a0-489b-8b7f-8a3e31a1e784
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586988597 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3586988597
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2742662563
Short name T899
Test name
Test status
Simulation time 447759099 ps
CPU time 11.2 seconds
Started Aug 14 04:35:03 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 209652 kb
Host smart-93c074f6-d68a-48c7-a4f6-39d41626c948
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742662563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2742662563
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.678956383
Short name T142
Test name
Test status
Simulation time 2295825829 ps
CPU time 7.34 seconds
Started Aug 14 04:35:12 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 209804 kb
Host smart-5660fdc9-1f52-4838-89b9-9ff73f24661a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678956383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.678956383
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1837194057
Short name T887
Test name
Test status
Simulation time 410261032 ps
CPU time 2.91 seconds
Started Aug 14 04:34:57 PM PDT 24
Finished Aug 14 04:35:00 PM PDT 24
Peak memory 211528 kb
Host smart-ea7dc037-629c-4aa8-ace7-21884faffe1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837194057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1837194057
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.689562836
Short name T893
Test name
Test status
Simulation time 88174253 ps
CPU time 3.16 seconds
Started Aug 14 04:34:53 PM PDT 24
Finished Aug 14 04:34:56 PM PDT 24
Peak memory 218420 kb
Host smart-c86c4852-1b62-4361-b06a-c3f7c6b47f93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689562
836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.689562836
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1501388292
Short name T948
Test name
Test status
Simulation time 421535117 ps
CPU time 3.08 seconds
Started Aug 14 04:34:51 PM PDT 24
Finished Aug 14 04:34:54 PM PDT 24
Peak memory 209884 kb
Host smart-22988794-2217-4997-9167-bc8338671eb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501388292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1501388292
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2021173490
Short name T202
Test name
Test status
Simulation time 20276251 ps
CPU time 1.28 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 212012 kb
Host smart-0646222c-53f2-4703-8879-23f53b28ef97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021173490 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2021173490
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2289048685
Short name T926
Test name
Test status
Simulation time 21503098 ps
CPU time 1.48 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 210016 kb
Host smart-3866aa3d-fe09-45a8-891e-e6d23d187db6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289048685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2289048685
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1642767963
Short name T954
Test name
Test status
Simulation time 50668614 ps
CPU time 2.28 seconds
Started Aug 14 04:35:04 PM PDT 24
Finished Aug 14 04:35:07 PM PDT 24
Peak memory 219004 kb
Host smart-8f68a7a8-6bc3-49f5-a0eb-8c02f4e65c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642767963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1642767963
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3590834472
Short name T137
Test name
Test status
Simulation time 243047659 ps
CPU time 2.55 seconds
Started Aug 14 04:34:51 PM PDT 24
Finished Aug 14 04:34:54 PM PDT 24
Peak memory 218320 kb
Host smart-4ad73026-48f5-4bc9-a72d-d64b54ce262c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590834472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3590834472
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1799742648
Short name T988
Test name
Test status
Simulation time 62715248 ps
CPU time 1.23 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 209904 kb
Host smart-8dc6b8fd-4ea7-4bef-91da-99e14e476e35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799742648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1799742648
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1154078551
Short name T197
Test name
Test status
Simulation time 27685824 ps
CPU time 1.81 seconds
Started Aug 14 04:35:02 PM PDT 24
Finished Aug 14 04:35:04 PM PDT 24
Peak memory 208580 kb
Host smart-9798cfcd-5929-41be-89d9-b345bb2dc619
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154078551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1154078551
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2602493341
Short name T195
Test name
Test status
Simulation time 28273369 ps
CPU time 1.02 seconds
Started Aug 14 04:35:12 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 211060 kb
Host smart-fc3cec58-3cb5-468a-932b-c71157a25817
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602493341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2602493341
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.382038603
Short name T170
Test name
Test status
Simulation time 34191674 ps
CPU time 1.07 seconds
Started Aug 14 04:35:02 PM PDT 24
Finished Aug 14 04:35:04 PM PDT 24
Peak memory 218336 kb
Host smart-c3995772-82fe-4aaf-9bf6-7a554d661206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382038603 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.382038603
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2466088325
Short name T953
Test name
Test status
Simulation time 79102935 ps
CPU time 1 seconds
Started Aug 14 04:35:01 PM PDT 24
Finished Aug 14 04:35:02 PM PDT 24
Peak memory 209956 kb
Host smart-e2a68183-08ac-4299-9da4-6088595d6a67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466088325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2466088325
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.696340167
Short name T981
Test name
Test status
Simulation time 23103055 ps
CPU time 0.91 seconds
Started Aug 14 04:34:53 PM PDT 24
Finished Aug 14 04:34:54 PM PDT 24
Peak memory 209832 kb
Host smart-bb791b96-7230-4d57-9008-16eb4f2dfd37
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696340167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.696340167
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.626811697
Short name T894
Test name
Test status
Simulation time 2360053483 ps
CPU time 4.34 seconds
Started Aug 14 04:35:05 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 209120 kb
Host smart-72070078-644d-4d35-9419-fa314dd94956
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626811697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.626811697
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3823824384
Short name T912
Test name
Test status
Simulation time 10181738538 ps
CPU time 14.56 seconds
Started Aug 14 04:35:03 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209820 kb
Host smart-0d447dde-0132-4b33-8e4d-cdb2a314ff30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823824384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3823824384
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2715873394
Short name T943
Test name
Test status
Simulation time 545690497 ps
CPU time 3.91 seconds
Started Aug 14 04:34:53 PM PDT 24
Finished Aug 14 04:34:57 PM PDT 24
Peak memory 211576 kb
Host smart-47c963f4-4aed-47b7-93ab-2cbd14676a8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715873394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2715873394
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3585339100
Short name T141
Test name
Test status
Simulation time 84638919 ps
CPU time 2.69 seconds
Started Aug 14 04:34:52 PM PDT 24
Finished Aug 14 04:34:55 PM PDT 24
Peak memory 218352 kb
Host smart-18593cdd-0f06-47e3-826f-2761cef1fba2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358533
9100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3585339100
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4269474555
Short name T877
Test name
Test status
Simulation time 228090139 ps
CPU time 1.6 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 209788 kb
Host smart-7a51968a-b67d-4076-9edc-03cd3cd83293
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269474555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4269474555
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.954570933
Short name T924
Test name
Test status
Simulation time 25507295 ps
CPU time 0.92 seconds
Started Aug 14 04:34:57 PM PDT 24
Finished Aug 14 04:34:58 PM PDT 24
Peak memory 210056 kb
Host smart-f1db14d1-19d3-45a0-827f-d577484b308e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954570933 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.954570933
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1263770371
Short name T976
Test name
Test status
Simulation time 45438097 ps
CPU time 1.97 seconds
Started Aug 14 04:35:04 PM PDT 24
Finished Aug 14 04:35:06 PM PDT 24
Peak memory 212064 kb
Host smart-223295ee-ed4d-4796-ac40-d8d851d81d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263770371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1263770371
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.716740583
Short name T121
Test name
Test status
Simulation time 99523522 ps
CPU time 1.79 seconds
Started Aug 14 04:34:54 PM PDT 24
Finished Aug 14 04:34:56 PM PDT 24
Peak memory 218072 kb
Host smart-2743fc1f-7374-4456-becd-6cd5480c3848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716740583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.716740583
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3887930936
Short name T902
Test name
Test status
Simulation time 21730477 ps
CPU time 1.34 seconds
Started Aug 14 04:35:09 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 219856 kb
Host smart-7450b2a2-cc8d-4ae3-a33c-dc2175ef5c0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887930936 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3887930936
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3139328347
Short name T190
Test name
Test status
Simulation time 32750878 ps
CPU time 0.84 seconds
Started Aug 14 04:35:25 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 209628 kb
Host smart-458656ee-2b6a-4098-b8f1-13519a7674b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139328347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3139328347
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3525175721
Short name T944
Test name
Test status
Simulation time 192806788 ps
CPU time 1.4 seconds
Started Aug 14 04:35:26 PM PDT 24
Finished Aug 14 04:35:28 PM PDT 24
Peak memory 209808 kb
Host smart-e11ab652-c4d4-41d3-abb3-6669ee37ebc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525175721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3525175721
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2578892700
Short name T1000
Test name
Test status
Simulation time 90908037 ps
CPU time 1.66 seconds
Started Aug 14 04:35:15 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 219224 kb
Host smart-ab965a62-4dd6-4d3a-b669-ad9b2550bdde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578892700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2578892700
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2288418019
Short name T945
Test name
Test status
Simulation time 233185372 ps
CPU time 2.66 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 218040 kb
Host smart-ca90f2b1-b286-4d70-808c-2fce9c0832a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288418019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2288418019
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.313129999
Short name T919
Test name
Test status
Simulation time 359428299 ps
CPU time 1.06 seconds
Started Aug 14 04:35:27 PM PDT 24
Finished Aug 14 04:35:28 PM PDT 24
Peak memory 218052 kb
Host smart-3a5cd9d7-8c69-4742-853d-e0b140569336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313129999 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.313129999
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1626656926
Short name T204
Test name
Test status
Simulation time 58014096 ps
CPU time 1.16 seconds
Started Aug 14 04:35:24 PM PDT 24
Finished Aug 14 04:35:25 PM PDT 24
Peak memory 209788 kb
Host smart-d04e4b39-d981-46ca-ad30-3c6e6fd7dd05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626656926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1626656926
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.547623309
Short name T985
Test name
Test status
Simulation time 115604928 ps
CPU time 1.82 seconds
Started Aug 14 04:35:24 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 218008 kb
Host smart-0347a284-febb-4fbf-82da-6f4e57e2be8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547623309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.547623309
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.816994904
Short name T977
Test name
Test status
Simulation time 219612608 ps
CPU time 1.09 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 220456 kb
Host smart-8490de3a-2181-465f-85c5-e54b9f927bcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816994904 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.816994904
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4205436548
Short name T184
Test name
Test status
Simulation time 46580751 ps
CPU time 1 seconds
Started Aug 14 04:35:05 PM PDT 24
Finished Aug 14 04:35:06 PM PDT 24
Peak memory 210028 kb
Host smart-d967b6b2-0978-4d53-86a4-b67c16ba0043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205436548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.4205436548
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.310617082
Short name T963
Test name
Test status
Simulation time 18712464 ps
CPU time 1.16 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:25 PM PDT 24
Peak memory 212008 kb
Host smart-a7e35ce0-80d3-4073-9f83-ae40424844a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310617082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.310617082
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2970539168
Short name T964
Test name
Test status
Simulation time 187079419 ps
CPU time 2.65 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:14 PM PDT 24
Peak memory 218580 kb
Host smart-4efcc332-7e9b-4db4-826d-39afbf1636f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970539168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2970539168
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3611996055
Short name T896
Test name
Test status
Simulation time 67337619 ps
CPU time 0.93 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 218208 kb
Host smart-a1dbdd36-813c-4533-8a3a-2e01f06412b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611996055 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3611996055
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3287254010
Short name T989
Test name
Test status
Simulation time 37388046 ps
CPU time 0.95 seconds
Started Aug 14 04:35:39 PM PDT 24
Finished Aug 14 04:35:40 PM PDT 24
Peak memory 209920 kb
Host smart-b95b1d41-ebe3-42a4-81b4-b2e8a2116267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287254010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3287254010
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2196343242
Short name T979
Test name
Test status
Simulation time 96181445 ps
CPU time 1.07 seconds
Started Aug 14 04:35:21 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 209692 kb
Host smart-22bc7015-5a47-4f20-a9bb-a4166f2035cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196343242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2196343242
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.612117687
Short name T958
Test name
Test status
Simulation time 165954369 ps
CPU time 2.97 seconds
Started Aug 14 04:35:15 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 218180 kb
Host smart-9ec05f58-02a6-439c-a1e1-c9a19ceb5ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612117687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.612117687
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.419732057
Short name T123
Test name
Test status
Simulation time 302884156 ps
CPU time 3.54 seconds
Started Aug 14 04:35:15 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 218144 kb
Host smart-363501a3-fe23-42a8-8914-8c95c39b7e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419732057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.419732057
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1146905495
Short name T969
Test name
Test status
Simulation time 28772224 ps
CPU time 0.94 seconds
Started Aug 14 04:35:48 PM PDT 24
Finished Aug 14 04:35:49 PM PDT 24
Peak memory 218232 kb
Host smart-f8ce0ca7-67ba-4d6f-8fda-a52823aceac5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146905495 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1146905495
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1215514745
Short name T192
Test name
Test status
Simulation time 11793172 ps
CPU time 0.87 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209816 kb
Host smart-b0b771a6-22e4-4aa8-b210-1bc985da9b5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215514745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1215514745
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2471200017
Short name T913
Test name
Test status
Simulation time 46139906 ps
CPU time 1.33 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 209936 kb
Host smart-48343cc9-9aeb-4ec2-a42a-1dd11eb3fd58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471200017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2471200017
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3164600199
Short name T900
Test name
Test status
Simulation time 98260753 ps
CPU time 3.48 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 217976 kb
Host smart-f7b1ce81-f77c-4e19-91f2-8ad5ef0129a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164600199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3164600199
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3925742146
Short name T156
Test name
Test status
Simulation time 112170284 ps
CPU time 1.41 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 218184 kb
Host smart-3539da8c-7402-4868-b145-073353b2531d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925742146 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3925742146
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3077473223
Short name T962
Test name
Test status
Simulation time 14923210 ps
CPU time 0.89 seconds
Started Aug 14 04:35:44 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 209884 kb
Host smart-027c02a0-aadd-4a72-a883-5e227c7417b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077473223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3077473223
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1433982112
Short name T996
Test name
Test status
Simulation time 238847863 ps
CPU time 1.9 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 212176 kb
Host smart-d88ebbc6-1f90-4ea5-bcff-b89afd382b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433982112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1433982112
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.64551220
Short name T885
Test name
Test status
Simulation time 219962619 ps
CPU time 2.28 seconds
Started Aug 14 04:35:26 PM PDT 24
Finished Aug 14 04:35:28 PM PDT 24
Peak memory 218064 kb
Host smart-9fd0ed46-bb9d-486f-b94c-f3fd67c3d961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64551220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.64551220
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.573944721
Short name T939
Test name
Test status
Simulation time 16396917 ps
CPU time 0.98 seconds
Started Aug 14 04:35:44 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 218208 kb
Host smart-fab51d6c-abc0-457c-9a91-77d847b09a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573944721 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.573944721
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.154012532
Short name T886
Test name
Test status
Simulation time 16899323 ps
CPU time 1.11 seconds
Started Aug 14 04:35:45 PM PDT 24
Finished Aug 14 04:35:46 PM PDT 24
Peak memory 209880 kb
Host smart-fa889fc1-52e6-4a9e-af4f-655213b84d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154012532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.154012532
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2976417684
Short name T909
Test name
Test status
Simulation time 142008616 ps
CPU time 1.03 seconds
Started Aug 14 04:35:43 PM PDT 24
Finished Aug 14 04:35:44 PM PDT 24
Peak memory 209948 kb
Host smart-7d48aec0-bb76-48a7-9a2f-5f5da44c6e70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976417684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2976417684
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.343071783
Short name T904
Test name
Test status
Simulation time 45119553 ps
CPU time 2.65 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:31 PM PDT 24
Peak memory 218056 kb
Host smart-dedc827e-2d41-435f-8b20-3f39b0f30ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343071783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.343071783
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1660352839
Short name T132
Test name
Test status
Simulation time 339323782 ps
CPU time 1.92 seconds
Started Aug 14 04:35:49 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 222580 kb
Host smart-f9b2b412-13ac-43f6-8310-357e3ff99bee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660352839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1660352839
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3973371923
Short name T931
Test name
Test status
Simulation time 19241266 ps
CPU time 1.59 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 218080 kb
Host smart-8fb4560f-72ba-45f0-b77f-40ee91d0e413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973371923 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3973371923
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3740512034
Short name T872
Test name
Test status
Simulation time 47882701 ps
CPU time 1.04 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209972 kb
Host smart-df1d5aa5-e4c4-4147-a951-fff67ce4349b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740512034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3740512034
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.783029042
Short name T200
Test name
Test status
Simulation time 117650262 ps
CPU time 1.08 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:30 PM PDT 24
Peak memory 209956 kb
Host smart-06dd0135-fb84-43c8-8acd-64364975c832
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783029042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.783029042
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.485401100
Short name T117
Test name
Test status
Simulation time 113004606 ps
CPU time 1.95 seconds
Started Aug 14 04:35:30 PM PDT 24
Finished Aug 14 04:35:32 PM PDT 24
Peak memory 218176 kb
Host smart-686e6fd5-7eb2-4797-999c-adbcadef9be7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485401100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.485401100
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1439594669
Short name T133
Test name
Test status
Simulation time 64150400 ps
CPU time 2.57 seconds
Started Aug 14 04:35:22 PM PDT 24
Finished Aug 14 04:35:25 PM PDT 24
Peak memory 218152 kb
Host smart-28fe19c0-f0d0-41f4-ae39-4a9dd4892866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439594669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1439594669
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3470321513
Short name T903
Test name
Test status
Simulation time 48597288 ps
CPU time 1.85 seconds
Started Aug 14 04:35:28 PM PDT 24
Finished Aug 14 04:35:29 PM PDT 24
Peak memory 225848 kb
Host smart-f02b32cd-bc21-4d65-8937-166ab2b2afe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470321513 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3470321513
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2797726199
Short name T970
Test name
Test status
Simulation time 28278222 ps
CPU time 0.92 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 209968 kb
Host smart-c0e906a1-0b3a-445b-a44e-ca669c3ae415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797726199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2797726199
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.770820844
Short name T983
Test name
Test status
Simulation time 26159565 ps
CPU time 1.14 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209872 kb
Host smart-45852572-f0c8-4615-982c-e6490bcad352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770820844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.770820844
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3420092996
Short name T949
Test name
Test status
Simulation time 353626248 ps
CPU time 1.55 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 219156 kb
Host smart-5d677d20-05fa-41cc-828a-b4e0c212223a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420092996 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3420092996
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1205199656
Short name T203
Test name
Test status
Simulation time 14856420 ps
CPU time 0.83 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209672 kb
Host smart-23ce58cc-5b35-4504-b870-d2a622b63029
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205199656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1205199656
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2026313408
Short name T984
Test name
Test status
Simulation time 15502584 ps
CPU time 1.27 seconds
Started Aug 14 04:35:24 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 209888 kb
Host smart-17347526-23b6-462f-a635-d7abf1e4fa94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026313408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2026313408
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.943296212
Short name T938
Test name
Test status
Simulation time 61146547 ps
CPU time 2.66 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:21 PM PDT 24
Peak memory 218108 kb
Host smart-6d251fc6-a526-4f28-a127-4e8744f8a813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943296212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.943296212
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1438036878
Short name T139
Test name
Test status
Simulation time 930499895 ps
CPU time 1.89 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 222232 kb
Host smart-75f3074f-41d6-4e1e-9718-85c7fed2e978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438036878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1438036878
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3018373450
Short name T186
Test name
Test status
Simulation time 303005512 ps
CPU time 1.64 seconds
Started Aug 14 04:35:09 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 209904 kb
Host smart-3914109d-4998-4610-b095-4b0822663c6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018373450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3018373450
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3096442194
Short name T980
Test name
Test status
Simulation time 154775519 ps
CPU time 1.75 seconds
Started Aug 14 04:35:03 PM PDT 24
Finished Aug 14 04:35:05 PM PDT 24
Peak memory 209868 kb
Host smart-cb96114b-40dc-4c3d-954e-1f8b8b0f39e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096442194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3096442194
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2538309664
Short name T889
Test name
Test status
Simulation time 59596893 ps
CPU time 0.92 seconds
Started Aug 14 04:35:13 PM PDT 24
Finished Aug 14 04:35:14 PM PDT 24
Peak memory 210412 kb
Host smart-a81267f6-0f74-40b7-888c-1d6e59749ba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538309664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2538309664
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3082744083
Short name T932
Test name
Test status
Simulation time 80135529 ps
CPU time 1.41 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 218192 kb
Host smart-e543c677-0c3d-45c4-b228-341c9b7a5fa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082744083 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3082744083
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2812823871
Short name T905
Test name
Test status
Simulation time 33304085 ps
CPU time 0.95 seconds
Started Aug 14 04:35:02 PM PDT 24
Finished Aug 14 04:35:03 PM PDT 24
Peak memory 209708 kb
Host smart-febd6b88-c442-43bb-8f92-ff212c1aae1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812823871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2812823871
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1095954031
Short name T874
Test name
Test status
Simulation time 1117719207 ps
CPU time 3.23 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 209572 kb
Host smart-4ee05220-2da1-40c6-9222-5c984518a91a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095954031 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1095954031
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3964581073
Short name T967
Test name
Test status
Simulation time 602348826 ps
CPU time 5.16 seconds
Started Aug 14 04:35:13 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209148 kb
Host smart-af1b8409-d935-4c0a-a426-7aa38a7e8d42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964581073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3964581073
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4253660589
Short name T957
Test name
Test status
Simulation time 1523042898 ps
CPU time 22.8 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:29 PM PDT 24
Peak memory 209644 kb
Host smart-5bf68a43-ce70-4acb-9460-82b2d7574140
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253660589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4253660589
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.865122688
Short name T883
Test name
Test status
Simulation time 462783390 ps
CPU time 5.26 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 211584 kb
Host smart-43c37a85-4092-49af-be40-5124db5ab96e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865122688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.865122688
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2822789664
Short name T959
Test name
Test status
Simulation time 93756527 ps
CPU time 2.98 seconds
Started Aug 14 04:34:56 PM PDT 24
Finished Aug 14 04:34:59 PM PDT 24
Peak memory 219200 kb
Host smart-c2966e05-2283-491d-9ddd-38e0eb52f98c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282278
9664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2822789664
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1729833797
Short name T881
Test name
Test status
Simulation time 43753378 ps
CPU time 1.14 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 209760 kb
Host smart-ced3f373-1604-4081-8508-7c2e7bbf1f1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729833797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1729833797
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2305164639
Short name T974
Test name
Test status
Simulation time 37278558 ps
CPU time 1.89 seconds
Started Aug 14 04:35:15 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 212108 kb
Host smart-a2350bd6-e0a8-45eb-9b95-b0ef8dd9ed6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305164639 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2305164639
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2878551212
Short name T966
Test name
Test status
Simulation time 17228598 ps
CPU time 1.2 seconds
Started Aug 14 04:35:13 PM PDT 24
Finished Aug 14 04:35:14 PM PDT 24
Peak memory 210004 kb
Host smart-4649dfb7-42f9-4846-8ac0-48b5141c9894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878551212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2878551212
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.867332727
Short name T975
Test name
Test status
Simulation time 239458036 ps
CPU time 1.67 seconds
Started Aug 14 04:34:51 PM PDT 24
Finished Aug 14 04:34:52 PM PDT 24
Peak memory 218272 kb
Host smart-f94bf2c7-f41d-441d-a9f2-ca196ce69e49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867332727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.867332727
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3725815489
Short name T130
Test name
Test status
Simulation time 82261398 ps
CPU time 2.2 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:16 PM PDT 24
Peak memory 222040 kb
Host smart-7efe0d6c-c1b7-49ce-8e7d-7df57abf1d4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725815489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3725815489
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2663117047
Short name T196
Test name
Test status
Simulation time 43949910 ps
CPU time 1.28 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:12 PM PDT 24
Peak memory 209488 kb
Host smart-61e62008-c705-4702-965a-a60a24d95994
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663117047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2663117047
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3436710556
Short name T880
Test name
Test status
Simulation time 256043548 ps
CPU time 2.58 seconds
Started Aug 14 04:35:01 PM PDT 24
Finished Aug 14 04:35:04 PM PDT 24
Peak memory 209792 kb
Host smart-3f2e6e64-b553-4419-a94b-7e35adda5d27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436710556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3436710556
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1081780289
Short name T992
Test name
Test status
Simulation time 82011206 ps
CPU time 1.14 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 211948 kb
Host smart-16f49098-69ed-4aae-843c-9d5fd0f77997
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081780289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1081780289
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3443009986
Short name T169
Test name
Test status
Simulation time 14923143 ps
CPU time 1.01 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 218200 kb
Host smart-c3a9203e-2674-454e-9522-fd5cb57c57f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443009986 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3443009986
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2399095297
Short name T915
Test name
Test status
Simulation time 12312462 ps
CPU time 0.82 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 209724 kb
Host smart-8035a603-7bee-4458-ae2b-401b400ab6a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399095297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2399095297
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1843892417
Short name T952
Test name
Test status
Simulation time 97210281 ps
CPU time 1.6 seconds
Started Aug 14 04:35:05 PM PDT 24
Finished Aug 14 04:35:07 PM PDT 24
Peak memory 209764 kb
Host smart-914fdd3e-8801-40ea-9cd1-a68f97b6fa0d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843892417 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1843892417
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.799027934
Short name T918
Test name
Test status
Simulation time 1065103703 ps
CPU time 6.85 seconds
Started Aug 14 04:35:05 PM PDT 24
Finished Aug 14 04:35:12 PM PDT 24
Peak memory 209600 kb
Host smart-06ba4e76-a6aa-4213-b3d3-9c6521047fd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799027934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.799027934
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.511751923
Short name T960
Test name
Test status
Simulation time 2612701304 ps
CPU time 13.03 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 209196 kb
Host smart-45bb1197-5d28-416a-b170-8ab65b15f144
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511751923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.511751923
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2303091883
Short name T935
Test name
Test status
Simulation time 51970856 ps
CPU time 1.33 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 211212 kb
Host smart-1f57441f-05b7-4d87-bc86-66cf7321e0a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303091883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2303091883
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3624302620
Short name T941
Test name
Test status
Simulation time 117611868 ps
CPU time 2.54 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 220668 kb
Host smart-15878b1f-c37b-452e-ae2f-48ddebb7562a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362430
2620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3624302620
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1025401414
Short name T140
Test name
Test status
Simulation time 39878275 ps
CPU time 1.14 seconds
Started Aug 14 04:35:15 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 209724 kb
Host smart-8ad15e0a-fcca-4117-bf52-0e9af4489479
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025401414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1025401414
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.477174151
Short name T198
Test name
Test status
Simulation time 38508495 ps
CPU time 1.35 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 211904 kb
Host smart-f6dbb834-8914-483e-96cb-191c46448f34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477174151 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.477174151
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.947439746
Short name T999
Test name
Test status
Simulation time 24338105 ps
CPU time 1.24 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:07 PM PDT 24
Peak memory 209964 kb
Host smart-abed978b-b223-4860-97a0-b06852fecace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947439746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.947439746
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3478432162
Short name T956
Test name
Test status
Simulation time 71835410 ps
CPU time 2.28 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 218276 kb
Host smart-9a2b8afe-7461-4679-9f1f-fe01a49d86fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478432162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3478432162
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2567566530
Short name T119
Test name
Test status
Simulation time 22588139 ps
CPU time 1.01 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:07 PM PDT 24
Peak memory 209900 kb
Host smart-51126566-0a0f-4475-8194-aee5e213c2aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567566530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2567566530
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1031470467
Short name T995
Test name
Test status
Simulation time 40203062 ps
CPU time 1.4 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:12 PM PDT 24
Peak memory 209904 kb
Host smart-6a2b8949-d3e6-4084-99d4-f88721adfb0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031470467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1031470467
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2558854303
Short name T188
Test name
Test status
Simulation time 76494807 ps
CPU time 1.04 seconds
Started Aug 14 04:35:29 PM PDT 24
Finished Aug 14 04:35:30 PM PDT 24
Peak memory 218824 kb
Host smart-1c72f1e6-739f-4575-93bf-479726928f83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558854303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2558854303
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3056741064
Short name T950
Test name
Test status
Simulation time 21312170 ps
CPU time 1.12 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 218840 kb
Host smart-eba258e6-bad0-4502-a8dd-82529a26136e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056741064 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3056741064
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3677239577
Short name T978
Test name
Test status
Simulation time 13597457 ps
CPU time 1.1 seconds
Started Aug 14 04:35:00 PM PDT 24
Finished Aug 14 04:35:01 PM PDT 24
Peak memory 209860 kb
Host smart-068a3825-65c3-4f45-a4c5-9d5da719c2d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677239577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3677239577
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3557608157
Short name T916
Test name
Test status
Simulation time 52213240 ps
CPU time 1.2 seconds
Started Aug 14 04:35:04 PM PDT 24
Finished Aug 14 04:35:06 PM PDT 24
Peak memory 209876 kb
Host smart-43785d39-0c03-42ee-8d0d-51d7763791b3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557608157 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3557608157
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2018763910
Short name T972
Test name
Test status
Simulation time 2179236792 ps
CPU time 15.22 seconds
Started Aug 14 04:35:13 PM PDT 24
Finished Aug 14 04:35:28 PM PDT 24
Peak memory 209748 kb
Host smart-b89dc4fb-302e-48ab-8700-eeb191586c20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018763910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2018763910
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1424651772
Short name T965
Test name
Test status
Simulation time 2901499196 ps
CPU time 10.96 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 209764 kb
Host smart-73795a8c-c5f2-4cad-bc51-4bd4f38b04b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424651772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1424651772
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2941400658
Short name T933
Test name
Test status
Simulation time 1202039328 ps
CPU time 1.54 seconds
Started Aug 14 04:35:18 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 211240 kb
Host smart-0d57ac23-d39f-4265-87d5-b144453b847c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941400658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2941400658
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.763825310
Short name T973
Test name
Test status
Simulation time 118891150 ps
CPU time 3.98 seconds
Started Aug 14 04:35:09 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 219672 kb
Host smart-6f47c866-ff21-4338-a5d9-e445be3838b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763825
310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.763825310
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1781548470
Short name T982
Test name
Test status
Simulation time 892977291 ps
CPU time 1.57 seconds
Started Aug 14 04:35:03 PM PDT 24
Finished Aug 14 04:35:05 PM PDT 24
Peak memory 209832 kb
Host smart-e2287b9e-5211-48fe-8c3e-446132b77148
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781548470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1781548470
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3631360314
Short name T997
Test name
Test status
Simulation time 78890961 ps
CPU time 1.55 seconds
Started Aug 14 04:35:04 PM PDT 24
Finished Aug 14 04:35:06 PM PDT 24
Peak memory 209948 kb
Host smart-432d4cd0-137b-4c5c-84c1-b35fa605b956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631360314 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3631360314
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3272203672
Short name T951
Test name
Test status
Simulation time 77758868 ps
CPU time 1.36 seconds
Started Aug 14 04:35:26 PM PDT 24
Finished Aug 14 04:35:28 PM PDT 24
Peak memory 219292 kb
Host smart-e1c83761-a20d-465b-afd1-f6fc8ec833ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272203672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3272203672
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1270235118
Short name T879
Test name
Test status
Simulation time 76823720 ps
CPU time 1.58 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 219020 kb
Host smart-dbf124b9-6910-4fd7-a28e-fe45434e347e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270235118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1270235118
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1533474779
Short name T127
Test name
Test status
Simulation time 119031253 ps
CPU time 4.01 seconds
Started Aug 14 04:34:55 PM PDT 24
Finished Aug 14 04:34:59 PM PDT 24
Peak memory 222924 kb
Host smart-434713f1-b0ce-41a7-b5bc-fa33ddafa10b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533474779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1533474779
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3535773589
Short name T942
Test name
Test status
Simulation time 21041586 ps
CPU time 1.42 seconds
Started Aug 14 04:35:36 PM PDT 24
Finished Aug 14 04:35:37 PM PDT 24
Peak memory 219624 kb
Host smart-f036cb42-b378-4672-9930-0f19c716e86c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535773589 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3535773589
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.28832877
Short name T888
Test name
Test status
Simulation time 27678514 ps
CPU time 0.85 seconds
Started Aug 14 04:35:21 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 209376 kb
Host smart-7d718745-9a9b-42f9-86d4-57204ffb30ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28832877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.28832877
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2314062434
Short name T961
Test name
Test status
Simulation time 337709480 ps
CPU time 1.17 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:07 PM PDT 24
Peak memory 208476 kb
Host smart-28c1235b-260e-4bf6-b2a0-257f0abfea57
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314062434 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2314062434
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2882415620
Short name T876
Test name
Test status
Simulation time 593382814 ps
CPU time 3.77 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209632 kb
Host smart-2c9a185c-0748-4067-b94b-78deb9ba6093
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882415620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2882415620
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1118906089
Short name T934
Test name
Test status
Simulation time 968007905 ps
CPU time 14.47 seconds
Started Aug 14 04:35:36 PM PDT 24
Finished Aug 14 04:35:51 PM PDT 24
Peak memory 208556 kb
Host smart-e54169e2-82c8-42b8-9ab7-baba5ee668af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118906089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1118906089
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.462026382
Short name T927
Test name
Test status
Simulation time 331270687 ps
CPU time 2.61 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 211352 kb
Host smart-cacea40e-6f4e-4963-a957-e420fd5972a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462026382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.462026382
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1204261518
Short name T897
Test name
Test status
Simulation time 161191503 ps
CPU time 4.58 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 218216 kb
Host smart-8f6573ab-2567-4cc0-93b6-49a8c9fc8b75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120426
1518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1204261518
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4174019681
Short name T895
Test name
Test status
Simulation time 1411854583 ps
CPU time 2.07 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 209868 kb
Host smart-42f3f253-e9b5-4969-bd17-7be61af3f032
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174019681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4174019681
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3597176360
Short name T199
Test name
Test status
Simulation time 106215710 ps
CPU time 0.98 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 209804 kb
Host smart-a53a3817-2b38-431e-bc4d-dbfd51fd0777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597176360 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3597176360
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3960243086
Short name T898
Test name
Test status
Simulation time 156506345 ps
CPU time 1.45 seconds
Started Aug 14 04:35:25 PM PDT 24
Finished Aug 14 04:35:27 PM PDT 24
Peak memory 212088 kb
Host smart-f7dfaac8-15a6-4e2e-8f8c-7a75451a5901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960243086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3960243086
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1186400594
Short name T884
Test name
Test status
Simulation time 54675702 ps
CPU time 2.55 seconds
Started Aug 14 04:35:39 PM PDT 24
Finished Aug 14 04:35:42 PM PDT 24
Peak memory 218128 kb
Host smart-99db1657-9d07-485c-885f-c6d0d0a8316c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186400594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1186400594
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2026353034
Short name T987
Test name
Test status
Simulation time 26727815 ps
CPU time 1.16 seconds
Started Aug 14 04:35:09 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 218124 kb
Host smart-8bf57fb1-a083-4139-afd7-eec29d0b81d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026353034 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2026353034
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3197830605
Short name T194
Test name
Test status
Simulation time 18957508 ps
CPU time 0.86 seconds
Started Aug 14 04:35:24 PM PDT 24
Finished Aug 14 04:35:25 PM PDT 24
Peak memory 209940 kb
Host smart-6c964803-c162-4047-81d5-e6ea7f521a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197830605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3197830605
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2929775194
Short name T968
Test name
Test status
Simulation time 127024907 ps
CPU time 1.25 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 208556 kb
Host smart-d8c31007-5a3e-4e8e-9bcc-c54964e4765a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929775194 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2929775194
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4069435878
Short name T922
Test name
Test status
Simulation time 1546566818 ps
CPU time 4.94 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 209704 kb
Host smart-d81d83f8-50bc-4a20-beef-6a8f6e6c3125
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069435878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4069435878
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3048964722
Short name T882
Test name
Test status
Simulation time 1100495603 ps
CPU time 26.59 seconds
Started Aug 14 04:35:30 PM PDT 24
Finished Aug 14 04:35:56 PM PDT 24
Peak memory 209632 kb
Host smart-53037eb5-74f1-4617-843a-44cc039e466e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048964722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3048964722
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3675744914
Short name T118
Test name
Test status
Simulation time 186820483 ps
CPU time 1.94 seconds
Started Aug 14 04:35:42 PM PDT 24
Finished Aug 14 04:35:44 PM PDT 24
Peak memory 211288 kb
Host smart-132a4c13-0906-4364-b23c-41ac405f5d70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675744914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3675744914
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.706876007
Short name T994
Test name
Test status
Simulation time 219389120 ps
CPU time 3.84 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:11 PM PDT 24
Peak memory 220040 kb
Host smart-6f729f8e-7305-4187-a65e-11d953aaa0fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706876
007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.706876007
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.533253437
Short name T923
Test name
Test status
Simulation time 41267452 ps
CPU time 1.14 seconds
Started Aug 14 04:35:12 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 209848 kb
Host smart-75e39048-8edb-4486-a5d9-796661f76577
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533253437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.533253437
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2928843240
Short name T928
Test name
Test status
Simulation time 17709881 ps
CPU time 1.22 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 209952 kb
Host smart-5f38a933-fc86-424a-9023-a810383512cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928843240 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2928843240
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3898735183
Short name T947
Test name
Test status
Simulation time 50524797 ps
CPU time 1.03 seconds
Started Aug 14 04:35:10 PM PDT 24
Finished Aug 14 04:35:12 PM PDT 24
Peak memory 209872 kb
Host smart-a5b3261b-7a0d-4346-b4a0-b746c94d5d74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898735183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3898735183
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.188427601
Short name T120
Test name
Test status
Simulation time 74554370 ps
CPU time 2.94 seconds
Started Aug 14 04:35:33 PM PDT 24
Finished Aug 14 04:35:36 PM PDT 24
Peak memory 218092 kb
Host smart-d774bd85-50d2-43d7-bf36-dc0a07c03fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188427601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.188427601
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.872351492
Short name T113
Test name
Test status
Simulation time 66398091 ps
CPU time 2.41 seconds
Started Aug 14 04:35:05 PM PDT 24
Finished Aug 14 04:35:07 PM PDT 24
Peak memory 218132 kb
Host smart-e6d4e031-b41b-420c-9ba5-918e5e318a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872351492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.872351492
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2637933781
Short name T873
Test name
Test status
Simulation time 170342342 ps
CPU time 1.68 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 218076 kb
Host smart-46233520-3c48-4a11-a525-89897f13c11e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637933781 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2637933781
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4106635765
Short name T189
Test name
Test status
Simulation time 67130795 ps
CPU time 0.89 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 209872 kb
Host smart-81f9ca00-8160-4863-ac92-4865a7a455a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106635765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4106635765
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1890522437
Short name T917
Test name
Test status
Simulation time 58867340 ps
CPU time 1.08 seconds
Started Aug 14 04:35:11 PM PDT 24
Finished Aug 14 04:35:13 PM PDT 24
Peak memory 209736 kb
Host smart-a64a1f97-760e-4ddc-a900-439a792055d4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890522437 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1890522437
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1470883712
Short name T920
Test name
Test status
Simulation time 2053548170 ps
CPU time 9.72 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 209076 kb
Host smart-f1212f77-16d4-45b9-8b6f-934d83f0dfff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470883712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1470883712
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.698883331
Short name T925
Test name
Test status
Simulation time 2767850437 ps
CPU time 18.83 seconds
Started Aug 14 04:35:33 PM PDT 24
Finished Aug 14 04:35:52 PM PDT 24
Peak memory 209220 kb
Host smart-28f93fc3-9a3e-4fa9-964f-6573ba57f9ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698883331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.698883331
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.271501362
Short name T993
Test name
Test status
Simulation time 735551507 ps
CPU time 5.01 seconds
Started Aug 14 04:35:36 PM PDT 24
Finished Aug 14 04:35:41 PM PDT 24
Peak memory 210516 kb
Host smart-a3bf1d0d-50f3-4dc1-97dd-f54ed4bd9902
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271501362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.271501362
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2696618991
Short name T892
Test name
Test status
Simulation time 194752561 ps
CPU time 2.02 seconds
Started Aug 14 04:35:13 PM PDT 24
Finished Aug 14 04:35:16 PM PDT 24
Peak memory 219360 kb
Host smart-8c163e9a-d3ab-4359-8f63-2ae827f17ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269661
8991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2696618991
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1789970823
Short name T890
Test name
Test status
Simulation time 142167182 ps
CPU time 1.8 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:07 PM PDT 24
Peak memory 209796 kb
Host smart-414f33d9-e8c8-4575-863c-1b28440c5dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789970823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1789970823
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4067041196
Short name T990
Test name
Test status
Simulation time 49260627 ps
CPU time 2.18 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 212064 kb
Host smart-1b23abc1-6577-43c2-b2ac-c38d01087fbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067041196 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4067041196
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2526093743
Short name T205
Test name
Test status
Simulation time 58948819 ps
CPU time 0.96 seconds
Started Aug 14 04:35:24 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 218176 kb
Host smart-c41a1672-0e5b-4105-bf7c-a272e5e1c413
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526093743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2526093743
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2423733638
Short name T937
Test name
Test status
Simulation time 59569825 ps
CPU time 1.65 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 218228 kb
Host smart-c0c020f4-e6e6-4baa-8c86-91161fc29e79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423733638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2423733638
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2879644144
Short name T134
Test name
Test status
Simulation time 377228495 ps
CPU time 2.72 seconds
Started Aug 14 04:35:23 PM PDT 24
Finished Aug 14 04:35:26 PM PDT 24
Peak memory 222924 kb
Host smart-84d29944-c27d-484a-8bfe-015653090963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879644144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2879644144
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2809006866
Short name T128
Test name
Test status
Simulation time 42544650 ps
CPU time 1.65 seconds
Started Aug 14 04:35:21 PM PDT 24
Finished Aug 14 04:35:23 PM PDT 24
Peak memory 219836 kb
Host smart-e4f7ccff-7338-4a70-83ac-25133c8ec8f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809006866 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2809006866
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2527767966
Short name T971
Test name
Test status
Simulation time 22961745 ps
CPU time 0.95 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 209796 kb
Host smart-c1def5ee-7dc9-4385-9927-f16b4f9dd184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527767966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2527767966
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.485084191
Short name T929
Test name
Test status
Simulation time 389062850 ps
CPU time 2.91 seconds
Started Aug 14 04:35:27 PM PDT 24
Finished Aug 14 04:35:30 PM PDT 24
Peak memory 209816 kb
Host smart-b3d85285-9f8e-48fe-aef4-09cbcdbdfa7c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485084191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.485084191
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1396315730
Short name T878
Test name
Test status
Simulation time 1031928512 ps
CPU time 24.14 seconds
Started Aug 14 04:35:17 PM PDT 24
Finished Aug 14 04:35:41 PM PDT 24
Peak memory 209708 kb
Host smart-9d95bb1f-1d01-4e5e-aab7-7880cf5d8a81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396315730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1396315730
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1618189011
Short name T921
Test name
Test status
Simulation time 1252273941 ps
CPU time 13.04 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:19 PM PDT 24
Peak memory 209144 kb
Host smart-2a39aff6-8263-40cb-b7cc-cb1f2c4573e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618189011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1618189011
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1937072966
Short name T910
Test name
Test status
Simulation time 212258506 ps
CPU time 1.75 seconds
Started Aug 14 04:35:16 PM PDT 24
Finished Aug 14 04:35:18 PM PDT 24
Peak memory 211580 kb
Host smart-32436475-e091-41f5-b96a-7bf0580f4cb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937072966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1937072966
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3042456037
Short name T901
Test name
Test status
Simulation time 1734263978 ps
CPU time 1.69 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:22 PM PDT 24
Peak memory 219152 kb
Host smart-341e3774-b9db-4d3d-a7c4-2d89c5236527
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304245
6037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3042456037
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.960011841
Short name T911
Test name
Test status
Simulation time 77814614 ps
CPU time 1.99 seconds
Started Aug 14 04:35:13 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 209900 kb
Host smart-9af79eac-df48-4a56-8271-ad3749797857
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960011841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.960011841
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.64781257
Short name T124
Test name
Test status
Simulation time 24866720 ps
CPU time 1.14 seconds
Started Aug 14 04:35:07 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 209668 kb
Host smart-edd21500-65b4-4a0b-aafb-cfd2fdad038e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64781257 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.64781257
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2459740204
Short name T201
Test name
Test status
Simulation time 15327028 ps
CPU time 0.98 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:09 PM PDT 24
Peak memory 217988 kb
Host smart-dc2c266b-76e5-4713-a843-e18475f01823
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459740204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2459740204
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.708955745
Short name T986
Test name
Test status
Simulation time 32604727 ps
CPU time 2.04 seconds
Started Aug 14 04:35:23 PM PDT 24
Finished Aug 14 04:35:25 PM PDT 24
Peak memory 218180 kb
Host smart-1c532bf0-9518-4f38-a21e-07dbc102154b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708955745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.708955745
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4110791265
Short name T936
Test name
Test status
Simulation time 40857651 ps
CPU time 1.52 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 219856 kb
Host smart-ac174dae-e72d-42c7-99c6-fbf051a0e230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110791265 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.4110791265
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3304966018
Short name T193
Test name
Test status
Simulation time 15572336 ps
CPU time 0.86 seconds
Started Aug 14 04:35:19 PM PDT 24
Finished Aug 14 04:35:20 PM PDT 24
Peak memory 209932 kb
Host smart-001b83a2-4da6-41ee-85e8-360d1bb73fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304966018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3304966018
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3662406802
Short name T955
Test name
Test status
Simulation time 234533071 ps
CPU time 2.14 seconds
Started Aug 14 04:35:10 PM PDT 24
Finished Aug 14 04:35:12 PM PDT 24
Peak memory 209736 kb
Host smart-01adec8c-5bb9-4f94-8dbb-d61f3c60bf9a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662406802 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3662406802
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.758027661
Short name T914
Test name
Test status
Simulation time 3779743341 ps
CPU time 6.26 seconds
Started Aug 14 04:35:09 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 209936 kb
Host smart-67149d60-afcd-4224-bc3d-b45480b1332b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758027661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.758027661
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4101247735
Short name T908
Test name
Test status
Simulation time 702333087 ps
CPU time 17.7 seconds
Started Aug 14 04:35:20 PM PDT 24
Finished Aug 14 04:35:38 PM PDT 24
Peak memory 209712 kb
Host smart-7f46aa00-7494-4262-9639-05156c8fb04b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101247735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4101247735
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1708672117
Short name T930
Test name
Test status
Simulation time 537327403 ps
CPU time 1.94 seconds
Started Aug 14 04:35:08 PM PDT 24
Finished Aug 14 04:35:10 PM PDT 24
Peak memory 211208 kb
Host smart-a3009be4-d66e-468e-b198-f8b4453c5c0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708672117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1708672117
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.729435440
Short name T991
Test name
Test status
Simulation time 142414150 ps
CPU time 1.44 seconds
Started Aug 14 04:35:30 PM PDT 24
Finished Aug 14 04:35:32 PM PDT 24
Peak memory 209816 kb
Host smart-df6149c9-c31e-4f68-a12f-c43d28dd0215
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729435440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.729435440
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3519079255
Short name T940
Test name
Test status
Simulation time 43501443 ps
CPU time 1.4 seconds
Started Aug 14 04:35:27 PM PDT 24
Finished Aug 14 04:35:33 PM PDT 24
Peak memory 212064 kb
Host smart-5570e154-5b7f-4dcc-ae4e-68f40e4d8def
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519079255 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3519079255
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.608240964
Short name T946
Test name
Test status
Simulation time 169370998 ps
CPU time 2.01 seconds
Started Aug 14 04:35:06 PM PDT 24
Finished Aug 14 04:35:08 PM PDT 24
Peak memory 211976 kb
Host smart-22605d1b-ef1a-4a33-8e68-64c34f9e41dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608240964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.608240964
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4265666490
Short name T115
Test name
Test status
Simulation time 69141322 ps
CPU time 3.04 seconds
Started Aug 14 04:35:14 PM PDT 24
Finished Aug 14 04:35:17 PM PDT 24
Peak memory 218012 kb
Host smart-245b385b-070c-4b74-b885-845b2534129c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265666490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4265666490
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2509801444
Short name T363
Test name
Test status
Simulation time 17035492 ps
CPU time 0.87 seconds
Started Aug 14 05:29:22 PM PDT 24
Finished Aug 14 05:29:23 PM PDT 24
Peak memory 208860 kb
Host smart-448d371e-d56b-4759-8df3-56113de27497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509801444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2509801444
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3041994635
Short name T605
Test name
Test status
Simulation time 452655305 ps
CPU time 13.46 seconds
Started Aug 14 05:29:22 PM PDT 24
Finished Aug 14 05:29:36 PM PDT 24
Peak memory 218376 kb
Host smart-31d7bb8a-7a89-411c-b083-ca83213eace7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041994635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3041994635
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2861332017
Short name T180
Test name
Test status
Simulation time 397330773 ps
CPU time 4.9 seconds
Started Aug 14 05:29:26 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 217220 kb
Host smart-e872e0b3-78b7-4ab5-affe-d87dd90710b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861332017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2861332017
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.457980103
Short name T263
Test name
Test status
Simulation time 3220502903 ps
CPU time 28.8 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:50 PM PDT 24
Peak memory 218920 kb
Host smart-51e626d8-246d-4e01-8155-a9747efed3df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457980103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.457980103
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.841389136
Short name T179
Test name
Test status
Simulation time 296738241 ps
CPU time 5.28 seconds
Started Aug 14 05:29:26 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 217336 kb
Host smart-4005a215-5ff4-4f75-b629-2c25a584f6ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841389136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.841389136
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1840582863
Short name T795
Test name
Test status
Simulation time 702931903 ps
CPU time 7.08 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:28 PM PDT 24
Peak memory 218252 kb
Host smart-158f4568-1004-417a-99b0-78ee7f3d81fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840582863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1840582863
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1135799676
Short name T851
Test name
Test status
Simulation time 5666129858 ps
CPU time 21.79 seconds
Started Aug 14 05:29:19 PM PDT 24
Finished Aug 14 05:29:41 PM PDT 24
Peak memory 217660 kb
Host smart-9aa57ea2-bc48-44a8-8c74-627d539b7ca4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135799676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1135799676
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3983241841
Short name T73
Test name
Test status
Simulation time 1064824571 ps
CPU time 9.08 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:30 PM PDT 24
Peak memory 217544 kb
Host smart-e186e91f-50ad-4879-89f4-a945b16221be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983241841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3983241841
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.682949000
Short name T705
Test name
Test status
Simulation time 1850027064 ps
CPU time 49.76 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 283740 kb
Host smart-791b76c2-3142-475a-bf72-3167ec03212a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682949000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.682949000
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1556736622
Short name T407
Test name
Test status
Simulation time 264170545 ps
CPU time 12.64 seconds
Started Aug 14 05:29:25 PM PDT 24
Finished Aug 14 05:29:37 PM PDT 24
Peak memory 246340 kb
Host smart-b428e2af-b317-49a5-aafb-b44777d8b214
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556736622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1556736622
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2381829551
Short name T462
Test name
Test status
Simulation time 29468056 ps
CPU time 1.76 seconds
Started Aug 14 05:29:29 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 218292 kb
Host smart-3987018d-da5c-4ad0-a3e7-c4c45ebadbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381829551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2381829551
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1945961409
Short name T857
Test name
Test status
Simulation time 2748771586 ps
CPU time 21.11 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:42 PM PDT 24
Peak memory 214976 kb
Host smart-fa4604fd-8338-472d-a3f8-0e43c5567f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945961409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1945961409
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1229692958
Short name T83
Test name
Test status
Simulation time 128001966 ps
CPU time 25.94 seconds
Started Aug 14 05:29:29 PM PDT 24
Finished Aug 14 05:29:55 PM PDT 24
Peak memory 282312 kb
Host smart-809c0dcc-9d55-4b7e-a8ba-d359dfb3429a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229692958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1229692958
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3149070275
Short name T100
Test name
Test status
Simulation time 1756785378 ps
CPU time 12.72 seconds
Started Aug 14 05:29:26 PM PDT 24
Finished Aug 14 05:29:39 PM PDT 24
Peak memory 226108 kb
Host smart-a7a4f3fd-bb75-48fa-ade3-3e6d20c6c824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149070275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3149070275
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4125337811
Short name T448
Test name
Test status
Simulation time 1257777037 ps
CPU time 12.01 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:32 PM PDT 24
Peak memory 225932 kb
Host smart-d9609fca-5ac1-44f1-90a0-d706fcca6464
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125337811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.4125337811
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3401354943
Short name T680
Test name
Test status
Simulation time 975278399 ps
CPU time 8.36 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:30 PM PDT 24
Peak memory 226040 kb
Host smart-d83c5672-3733-4251-9b37-d7a6ec2bda14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401354943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
401354943
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2707956328
Short name T755
Test name
Test status
Simulation time 1858054830 ps
CPU time 14.74 seconds
Started Aug 14 05:29:28 PM PDT 24
Finished Aug 14 05:29:43 PM PDT 24
Peak memory 218368 kb
Host smart-cbbaf50f-6371-4b32-8308-94da75472d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707956328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2707956328
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3468777898
Short name T858
Test name
Test status
Simulation time 327923188 ps
CPU time 2.97 seconds
Started Aug 14 05:29:26 PM PDT 24
Finished Aug 14 05:29:29 PM PDT 24
Peak memory 214928 kb
Host smart-35ddab8f-a2f5-4858-80a1-e795d27c7e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468777898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3468777898
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.277357361
Short name T520
Test name
Test status
Simulation time 258896422 ps
CPU time 32.13 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:53 PM PDT 24
Peak memory 250936 kb
Host smart-1dca99b8-af66-4090-aa3d-db1ce202e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277357361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.277357361
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2210917319
Short name T350
Test name
Test status
Simulation time 362007343 ps
CPU time 8.79 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:30 PM PDT 24
Peak memory 250868 kb
Host smart-dbc4ae92-361e-4394-9511-5fce7b6dd5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210917319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2210917319
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2435796127
Short name T368
Test name
Test status
Simulation time 16331989925 ps
CPU time 210.92 seconds
Started Aug 14 05:29:23 PM PDT 24
Finished Aug 14 05:32:54 PM PDT 24
Peak memory 283752 kb
Host smart-166c085b-2f20-47df-9df8-96c19c0cc137
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435796127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2435796127
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1770515158
Short name T144
Test name
Test status
Simulation time 2123059584 ps
CPU time 82.73 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:30:44 PM PDT 24
Peak memory 271276 kb
Host smart-f0cfecd5-b10c-4549-8016-1ed84a87b755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1770515158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.1770515158
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1826729110
Short name T331
Test name
Test status
Simulation time 22746466 ps
CPU time 0.85 seconds
Started Aug 14 05:29:19 PM PDT 24
Finished Aug 14 05:29:20 PM PDT 24
Peak memory 211932 kb
Host smart-714df433-5b43-42b0-90c8-d0f46c3ad2da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826729110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1826729110
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.663871534
Short name T742
Test name
Test status
Simulation time 60625028 ps
CPU time 1.09 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 209032 kb
Host smart-8522032b-6061-4311-ad39-eeb6e61555b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663871534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.663871534
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1860417289
Short name T773
Test name
Test status
Simulation time 280160626 ps
CPU time 14.62 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:36 PM PDT 24
Peak memory 225556 kb
Host smart-4853ec2b-19fb-4214-a51d-5fb509894ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860417289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1860417289
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1924799828
Short name T783
Test name
Test status
Simulation time 153945164 ps
CPU time 2.5 seconds
Started Aug 14 05:29:32 PM PDT 24
Finished Aug 14 05:29:34 PM PDT 24
Peak memory 217588 kb
Host smart-cb254821-d6f9-42ec-89e1-43251817e1e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924799828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1924799828
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3676379561
Short name T494
Test name
Test status
Simulation time 8465339900 ps
CPU time 33.62 seconds
Started Aug 14 05:29:32 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 218780 kb
Host smart-52176061-a29e-4789-b079-d11cdfbc56df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676379561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3676379561
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1468446189
Short name T21
Test name
Test status
Simulation time 409967594 ps
CPU time 5.89 seconds
Started Aug 14 05:29:29 PM PDT 24
Finished Aug 14 05:29:35 PM PDT 24
Peak memory 217716 kb
Host smart-b80fc678-efb6-43b7-91fe-f0afd4221266
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468446189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
468446189
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3735380920
Short name T713
Test name
Test status
Simulation time 233337250 ps
CPU time 4.63 seconds
Started Aug 14 05:29:27 PM PDT 24
Finished Aug 14 05:29:32 PM PDT 24
Peak memory 218236 kb
Host smart-e8b67264-1412-4e0d-811a-297bdae61d13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735380920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3735380920
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3064808072
Short name T709
Test name
Test status
Simulation time 1425569513 ps
CPU time 23.74 seconds
Started Aug 14 05:29:28 PM PDT 24
Finished Aug 14 05:29:52 PM PDT 24
Peak memory 217544 kb
Host smart-0966f959-6f76-4d85-bff2-bdc7a8ccdab2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064808072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3064808072
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.373664280
Short name T445
Test name
Test status
Simulation time 307012697 ps
CPU time 2.85 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:33 PM PDT 24
Peak memory 217584 kb
Host smart-f75b5698-3343-4124-a962-1f3154b7a8cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373664280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.373664280
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.694281688
Short name T224
Test name
Test status
Simulation time 9755716144 ps
CPU time 86.54 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 267428 kb
Host smart-50d12883-4a41-40ca-8459-12c33032b351
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694281688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.694281688
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.940960036
Short name T596
Test name
Test status
Simulation time 4414315408 ps
CPU time 19.2 seconds
Started Aug 14 05:29:33 PM PDT 24
Finished Aug 14 05:29:52 PM PDT 24
Peak memory 250896 kb
Host smart-e1c2590d-4c2b-4d50-aff0-abc1541e87c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940960036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.940960036
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.292377991
Short name T452
Test name
Test status
Simulation time 76775093 ps
CPU time 2.82 seconds
Started Aug 14 05:29:22 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 218256 kb
Host smart-4c9052c6-0b0b-4ac7-bf60-d96b6d0885d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292377991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.292377991
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3452564008
Short name T53
Test name
Test status
Simulation time 519584427 ps
CPU time 13.73 seconds
Started Aug 14 05:29:29 PM PDT 24
Finished Aug 14 05:29:42 PM PDT 24
Peak memory 217644 kb
Host smart-bb7c8ef0-3445-4971-a3d7-0c30bd8375de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452564008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3452564008
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2150194017
Short name T266
Test name
Test status
Simulation time 406889105 ps
CPU time 14.26 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:44 PM PDT 24
Peak memory 218372 kb
Host smart-df6b00e1-6455-44c0-8b16-ad0ba1f61d3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150194017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2150194017
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3607373346
Short name T670
Test name
Test status
Simulation time 624964595 ps
CPU time 12.17 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:43 PM PDT 24
Peak memory 225800 kb
Host smart-daef4c17-13a7-4972-a12e-215d0df842ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607373346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3607373346
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.433889971
Short name T695
Test name
Test status
Simulation time 645395683 ps
CPU time 11.22 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:41 PM PDT 24
Peak memory 218232 kb
Host smart-2ae0d4b2-4768-4e66-a9df-2551a314800e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433889971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.433889971
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.531694372
Short name T613
Test name
Test status
Simulation time 644900239 ps
CPU time 11.34 seconds
Started Aug 14 05:29:26 PM PDT 24
Finished Aug 14 05:29:38 PM PDT 24
Peak memory 225960 kb
Host smart-4139fa2e-0239-4f9c-add8-d8a66931ff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531694372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.531694372
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1970874674
Short name T636
Test name
Test status
Simulation time 62576997 ps
CPU time 3.95 seconds
Started Aug 14 05:29:23 PM PDT 24
Finished Aug 14 05:29:27 PM PDT 24
Peak memory 217660 kb
Host smart-78821b63-cf54-41a3-8a66-56cc666db7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970874674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1970874674
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3219112024
Short name T659
Test name
Test status
Simulation time 582512641 ps
CPU time 26.04 seconds
Started Aug 14 05:29:23 PM PDT 24
Finished Aug 14 05:29:50 PM PDT 24
Peak memory 251008 kb
Host smart-cd9bbdb2-148b-4293-9bf3-93cb880eb7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219112024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3219112024
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1989330865
Short name T98
Test name
Test status
Simulation time 253258283 ps
CPU time 8.42 seconds
Started Aug 14 05:29:22 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 251044 kb
Host smart-0224b803-572d-46ed-ad8c-ff26997f972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989330865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1989330865
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.649603959
Short name T385
Test name
Test status
Simulation time 3444267827 ps
CPU time 46.05 seconds
Started Aug 14 05:29:31 PM PDT 24
Finished Aug 14 05:30:17 PM PDT 24
Peak memory 267328 kb
Host smart-0be1770e-67ae-4a4b-9967-a42ab2e6737e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649603959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.649603959
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2308358585
Short name T280
Test name
Test status
Simulation time 19444724 ps
CPU time 1.22 seconds
Started Aug 14 05:29:24 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 217728 kb
Host smart-4efc2bcf-dafc-4a2d-b99c-d6ea709cb13b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308358585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2308358585
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2354556830
Short name T562
Test name
Test status
Simulation time 37923594 ps
CPU time 0.93 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 208884 kb
Host smart-5d5ee82a-a8e6-4baa-baec-2881531355e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354556830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2354556830
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3788682001
Short name T473
Test name
Test status
Simulation time 299137745 ps
CPU time 11 seconds
Started Aug 14 05:30:12 PM PDT 24
Finished Aug 14 05:30:23 PM PDT 24
Peak memory 226052 kb
Host smart-bbef1d72-65b2-4b19-a6b6-92f47d70c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788682001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3788682001
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.104867710
Short name T420
Test name
Test status
Simulation time 544323206 ps
CPU time 3.49 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:13 PM PDT 24
Peak memory 217036 kb
Host smart-5b4870f1-67ed-4603-b10e-a3e0df57f51a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104867710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.104867710
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3092856040
Short name T815
Test name
Test status
Simulation time 4809897763 ps
CPU time 35.35 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 218972 kb
Host smart-7a56852d-37eb-4805-b929-ef21c7b1f585
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092856040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3092856040
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3682719181
Short name T215
Test name
Test status
Simulation time 1375032277 ps
CPU time 6.41 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 218204 kb
Host smart-17605b4e-b948-49e2-9821-9c260768d101
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682719181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3682719181
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3582896598
Short name T728
Test name
Test status
Simulation time 13255657988 ps
CPU time 59.91 seconds
Started Aug 14 05:30:13 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 276460 kb
Host smart-d78d7366-1d2f-4010-be2c-ef1d71ba80e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582896598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3582896598
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3193858405
Short name T272
Test name
Test status
Simulation time 258107922 ps
CPU time 11.25 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 249700 kb
Host smart-c3b1d390-5d2b-4f83-bac6-6b9f2692f9c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193858405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3193858405
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2214427333
Short name T644
Test name
Test status
Simulation time 148617180 ps
CPU time 2.45 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 222292 kb
Host smart-fdafe904-9b13-41b2-a712-8eb6eb4be735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214427333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2214427333
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.22552275
Short name T164
Test name
Test status
Simulation time 1512507325 ps
CPU time 12.63 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:22 PM PDT 24
Peak memory 219024 kb
Host smart-69dafb98-84f7-469f-b4a5-e2b4a47a81d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22552275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.22552275
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.4022487228
Short name T158
Test name
Test status
Simulation time 255213413 ps
CPU time 7.79 seconds
Started Aug 14 05:30:11 PM PDT 24
Finished Aug 14 05:30:18 PM PDT 24
Peak memory 225956 kb
Host smart-63fc49c0-d3df-4f9d-b47b-6145339b109b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022487228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.4022487228
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3219192350
Short name T487
Test name
Test status
Simulation time 1319879394 ps
CPU time 14.51 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:23 PM PDT 24
Peak memory 225956 kb
Host smart-a827f8ab-8c9c-433d-92d3-bd0563111587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219192350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3219192350
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.509312071
Short name T718
Test name
Test status
Simulation time 1629286341 ps
CPU time 10.15 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:19 PM PDT 24
Peak memory 225072 kb
Host smart-32e10f0e-cb35-4310-8d33-cbd41f15a9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509312071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.509312071
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3195278303
Short name T753
Test name
Test status
Simulation time 32997236 ps
CPU time 2.83 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:12 PM PDT 24
Peak memory 214564 kb
Host smart-bb4c5ef9-3bce-4871-89fd-701e6936cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195278303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3195278303
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3376584368
Short name T479
Test name
Test status
Simulation time 307590158 ps
CPU time 24.6 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:30:33 PM PDT 24
Peak memory 250896 kb
Host smart-3aa4f152-385f-443b-b88f-e3da756b69a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376584368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3376584368
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4007363446
Short name T442
Test name
Test status
Simulation time 641914163 ps
CPU time 3.59 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:12 PM PDT 24
Peak memory 222312 kb
Host smart-f4a257a1-acbb-4f7d-b040-b4d178d5723a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007363446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4007363446
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.8717913
Short name T75
Test name
Test status
Simulation time 31988785334 ps
CPU time 325.67 seconds
Started Aug 14 05:30:07 PM PDT 24
Finished Aug 14 05:35:33 PM PDT 24
Peak memory 288680 kb
Host smart-fedc6cca-c140-43aa-86d2-8c52bd57d8d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8717913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.lc_ctrl_stress_all.8717913
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2156835693
Short name T143
Test name
Test status
Simulation time 15614977572 ps
CPU time 158.22 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:32:47 PM PDT 24
Peak memory 254112 kb
Host smart-54c745c1-5a66-4abb-982b-10f538484ca3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2156835693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2156835693
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2166592044
Short name T335
Test name
Test status
Simulation time 16415936 ps
CPU time 0.93 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 212908 kb
Host smart-7a5dd3e3-fab5-45a4-8f39-66f25c59e119
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166592044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2166592044
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1654756755
Short name T787
Test name
Test status
Simulation time 71265629 ps
CPU time 0.97 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 208888 kb
Host smart-16232d07-a434-4d9e-a479-7f6247fb5dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654756755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1654756755
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.4109296577
Short name T554
Test name
Test status
Simulation time 938262901 ps
CPU time 11.22 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 226092 kb
Host smart-df4db030-8932-4f52-9483-555e6e872796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109296577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.4109296577
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1421798376
Short name T482
Test name
Test status
Simulation time 1297296101 ps
CPU time 6.92 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:17 PM PDT 24
Peak memory 217032 kb
Host smart-3414c965-5eb8-4a36-bf49-7cde5d4c02a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421798376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1421798376
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3501479598
Short name T581
Test name
Test status
Simulation time 2234328229 ps
CPU time 35.95 seconds
Started Aug 14 05:30:11 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 218232 kb
Host smart-b5851367-1236-4dff-8ba2-8d3d242d5362
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501479598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3501479598
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1947308409
Short name T690
Test name
Test status
Simulation time 421117608 ps
CPU time 10.89 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:20 PM PDT 24
Peak memory 223280 kb
Host smart-e33f305c-e6bb-4113-aad6-17b7348c7e18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947308409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1947308409
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1797255680
Short name T499
Test name
Test status
Simulation time 924825003 ps
CPU time 4.15 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 217580 kb
Host smart-d831ed40-e9c9-4c20-a284-1030b2972aa9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797255680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1797255680
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.190432590
Short name T20
Test name
Test status
Simulation time 10803382541 ps
CPU time 58.38 seconds
Started Aug 14 05:30:11 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 267304 kb
Host smart-63c94329-b6dd-4c86-b162-d14601226259
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190432590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.190432590
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4058741181
Short name T584
Test name
Test status
Simulation time 2456997127 ps
CPU time 8.58 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 223480 kb
Host smart-bafb41f0-cce4-4e6a-849a-c48a60c8bd1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058741181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4058741181
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4287184635
Short name T551
Test name
Test status
Simulation time 99002346 ps
CPU time 1.7 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 218280 kb
Host smart-4ddac207-cd38-4ae3-adec-8c0705f96b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287184635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4287184635
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4214224750
Short name T843
Test name
Test status
Simulation time 314194055 ps
CPU time 13.36 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:23 PM PDT 24
Peak memory 226096 kb
Host smart-4bd2f1ae-e83e-4f56-b88e-b8c5e810519b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214224750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4214224750
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1299981823
Short name T157
Test name
Test status
Simulation time 3607242747 ps
CPU time 12.33 seconds
Started Aug 14 05:30:13 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 226072 kb
Host smart-761c110c-679b-421c-8098-82853ccf696a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299981823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1299981823
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2859344572
Short name T175
Test name
Test status
Simulation time 726584627 ps
CPU time 5.47 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 225956 kb
Host smart-202fbfcf-1745-4eef-befb-3e699385a145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859344572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2859344572
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.336539558
Short name T293
Test name
Test status
Simulation time 117778335 ps
CPU time 2.09 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 217752 kb
Host smart-01cf46ad-cb21-48e2-b8e4-fd56d7489504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336539558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.336539558
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.691320536
Short name T327
Test name
Test status
Simulation time 939297030 ps
CPU time 20.03 seconds
Started Aug 14 05:30:11 PM PDT 24
Finished Aug 14 05:30:31 PM PDT 24
Peak memory 250948 kb
Host smart-9ffaa962-0389-4fe1-9234-32227e045461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691320536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.691320536
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2972638131
Short name T361
Test name
Test status
Simulation time 88995391 ps
CPU time 6.8 seconds
Started Aug 14 05:30:12 PM PDT 24
Finished Aug 14 05:30:19 PM PDT 24
Peak memory 247080 kb
Host smart-3886a432-f08d-4119-ac01-ed4079bd2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972638131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2972638131
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3954202855
Short name T720
Test name
Test status
Simulation time 28017169222 ps
CPU time 218.83 seconds
Started Aug 14 05:30:13 PM PDT 24
Finished Aug 14 05:33:52 PM PDT 24
Peak memory 251044 kb
Host smart-8ad63870-2cce-47a7-b7b5-e8ef9596463c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954202855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3954202855
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1786381903
Short name T321
Test name
Test status
Simulation time 41646612 ps
CPU time 0.96 seconds
Started Aug 14 05:30:10 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 211928 kb
Host smart-5bb25679-542b-4959-99e6-df2f35de4004
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786381903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1786381903
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.495482706
Short name T382
Test name
Test status
Simulation time 136528433 ps
CPU time 1 seconds
Started Aug 14 05:30:23 PM PDT 24
Finished Aug 14 05:30:24 PM PDT 24
Peak memory 208916 kb
Host smart-d4898f73-2e87-4ba2-87a6-c28513de9e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495482706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.495482706
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3077585779
Short name T31
Test name
Test status
Simulation time 295449053 ps
CPU time 13.14 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:29 PM PDT 24
Peak memory 226092 kb
Host smart-411dd309-06af-4c77-bd22-31981fa0309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077585779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3077585779
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.455328111
Short name T95
Test name
Test status
Simulation time 572954157 ps
CPU time 13.93 seconds
Started Aug 14 05:30:18 PM PDT 24
Finished Aug 14 05:30:32 PM PDT 24
Peak memory 217188 kb
Host smart-a78eab3f-49c3-419e-8520-ed747f0cb99a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455328111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.455328111
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3458721545
Short name T624
Test name
Test status
Simulation time 15195054424 ps
CPU time 45.89 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 218896 kb
Host smart-968ff52a-417a-4b60-b913-f9f3b7d926e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458721545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3458721545
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2826934884
Short name T425
Test name
Test status
Simulation time 1853471038 ps
CPU time 7.18 seconds
Started Aug 14 05:30:15 PM PDT 24
Finished Aug 14 05:30:22 PM PDT 24
Peak memory 218248 kb
Host smart-f6d146f7-fe94-4f22-a1c0-d0c3a3a317e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826934884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2826934884
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2980097074
Short name T64
Test name
Test status
Simulation time 201503054 ps
CPU time 2.35 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 217592 kb
Host smart-ba748691-466c-43dc-a938-85a8fc334580
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980097074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2980097074
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3553857425
Short name T254
Test name
Test status
Simulation time 6368931971 ps
CPU time 70.13 seconds
Started Aug 14 05:30:18 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 267288 kb
Host smart-8d45f7b3-4811-47f7-b9b9-751fe3d0103f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553857425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3553857425
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2771456041
Short name T492
Test name
Test status
Simulation time 3829627984 ps
CPU time 15.37 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:31 PM PDT 24
Peak memory 250396 kb
Host smart-bf815b78-9301-4ff3-80d5-9627d8c58e91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771456041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2771456041
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1918492744
Short name T470
Test name
Test status
Simulation time 111522089 ps
CPU time 2.89 seconds
Started Aug 14 05:30:18 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 222368 kb
Host smart-9d8d4ba5-61d3-4158-b8a2-93aaa457671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918492744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1918492744
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2143836012
Short name T216
Test name
Test status
Simulation time 3366421073 ps
CPU time 10.54 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 226152 kb
Host smart-37a00df1-cb15-40e9-883a-832cb45519bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143836012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2143836012
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1121072297
Short name T333
Test name
Test status
Simulation time 1021361096 ps
CPU time 24.29 seconds
Started Aug 14 05:30:18 PM PDT 24
Finished Aug 14 05:30:42 PM PDT 24
Peak memory 226024 kb
Host smart-16876849-70a5-412d-90ee-93a382da9306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121072297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1121072297
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.488206892
Short name T799
Test name
Test status
Simulation time 1197174842 ps
CPU time 8.22 seconds
Started Aug 14 05:30:23 PM PDT 24
Finished Aug 14 05:30:31 PM PDT 24
Peak memory 226020 kb
Host smart-7da8c617-970f-4289-86a7-0094bad176ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488206892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.488206892
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2330728288
Short name T711
Test name
Test status
Simulation time 692190532 ps
CPU time 12.37 seconds
Started Aug 14 05:30:14 PM PDT 24
Finished Aug 14 05:30:27 PM PDT 24
Peak memory 226064 kb
Host smart-d4ad8d5a-9557-47ff-b63a-6afb006c2f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330728288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2330728288
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.290396966
Short name T392
Test name
Test status
Simulation time 27437872 ps
CPU time 0.99 seconds
Started Aug 14 05:30:15 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 217684 kb
Host smart-93158b12-ab98-4239-a1a1-c7f486629fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290396966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.290396966
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1052347207
Short name T292
Test name
Test status
Simulation time 530604165 ps
CPU time 18.11 seconds
Started Aug 14 05:30:18 PM PDT 24
Finished Aug 14 05:30:37 PM PDT 24
Peak memory 251012 kb
Host smart-f28de3f9-9a8a-4bb5-a0db-11c56dd62028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052347207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1052347207
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3200508895
Short name T849
Test name
Test status
Simulation time 231335802 ps
CPU time 7.6 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:24 PM PDT 24
Peak memory 250928 kb
Host smart-801d6638-a2c4-452f-8c86-0c8b22d64f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200508895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3200508895
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2827252371
Short name T364
Test name
Test status
Simulation time 7923342659 ps
CPU time 105.72 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:32:05 PM PDT 24
Peak memory 226152 kb
Host smart-bcb28f6f-dc84-4a26-8b7a-99d5dc659bb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827252371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2827252371
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2060781079
Short name T474
Test name
Test status
Simulation time 22736341139 ps
CPU time 136.07 seconds
Started Aug 14 05:30:20 PM PDT 24
Finished Aug 14 05:32:36 PM PDT 24
Peak memory 282976 kb
Host smart-bcdbc672-5868-432c-92b6-35c3588599ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2060781079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2060781079
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3174637106
Short name T491
Test name
Test status
Simulation time 63345692 ps
CPU time 0.96 seconds
Started Aug 14 05:30:21 PM PDT 24
Finished Aug 14 05:30:22 PM PDT 24
Peak memory 211916 kb
Host smart-5ceb7cb3-1f24-47a0-a1d0-b8b9b15ef5c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174637106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3174637106
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3863556067
Short name T485
Test name
Test status
Simulation time 38719904 ps
CPU time 0.97 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:17 PM PDT 24
Peak memory 208848 kb
Host smart-1c2addbd-177b-4e28-9440-1782654e171b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863556067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3863556067
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1718865303
Short name T232
Test name
Test status
Simulation time 1283239696 ps
CPU time 11.12 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 218292 kb
Host smart-6d0ddc5c-27bd-41be-a2e6-e28b190c5f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718865303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1718865303
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2792706761
Short name T454
Test name
Test status
Simulation time 13803670404 ps
CPU time 43.29 seconds
Started Aug 14 05:30:20 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 218932 kb
Host smart-7dddbdf5-8ba6-4063-a85d-9873e0a8280d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792706761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2792706761
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.67671861
Short name T389
Test name
Test status
Simulation time 433941301 ps
CPU time 13.11 seconds
Started Aug 14 05:30:18 PM PDT 24
Finished Aug 14 05:30:32 PM PDT 24
Peak memory 223252 kb
Host smart-515bc7d4-4858-4c32-a2c3-f0dfe19600f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67671861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_
prog_failure.67671861
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1112619356
Short name T662
Test name
Test status
Simulation time 122045288 ps
CPU time 2.79 seconds
Started Aug 14 05:30:15 PM PDT 24
Finished Aug 14 05:30:18 PM PDT 24
Peak memory 217700 kb
Host smart-49a841af-c490-4272-9443-f28e3b4227fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112619356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1112619356
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1568730213
Short name T161
Test name
Test status
Simulation time 2192196253 ps
CPU time 42.68 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 250920 kb
Host smart-3401e944-406a-4b91-8869-af532abfb4ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568730213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1568730213
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2097820504
Short name T326
Test name
Test status
Simulation time 4431482552 ps
CPU time 31.92 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:49 PM PDT 24
Peak memory 250924 kb
Host smart-e9291bd9-9fc4-4d7a-947b-ff915a43b3a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097820504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2097820504
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3241684105
Short name T314
Test name
Test status
Simulation time 68648759 ps
CPU time 3.53 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:30:23 PM PDT 24
Peak memory 218292 kb
Host smart-74b96e30-f4c3-4ce9-865f-83971e188833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241684105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3241684105
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3010706357
Short name T366
Test name
Test status
Simulation time 287004474 ps
CPU time 10.35 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:30:30 PM PDT 24
Peak memory 226096 kb
Host smart-40bdaac8-ff64-4fbb-9999-6713a8c60109
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010706357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3010706357
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.957715814
Short name T148
Test name
Test status
Simulation time 327805751 ps
CPU time 8.71 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:25 PM PDT 24
Peak memory 226016 kb
Host smart-686f288a-7374-4d0a-aaa3-2af2b49ccdbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957715814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.957715814
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2716044689
Short name T310
Test name
Test status
Simulation time 2536415628 ps
CPU time 9.03 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 218292 kb
Host smart-6475f631-ca06-4244-b53c-2b6513f5f1b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716044689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2716044689
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.184653220
Short name T765
Test name
Test status
Simulation time 860262520 ps
CPU time 7.17 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:24 PM PDT 24
Peak memory 225104 kb
Host smart-3fed8603-f877-4e1d-b852-2ae98302a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184653220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.184653220
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3577405059
Short name T758
Test name
Test status
Simulation time 204873252 ps
CPU time 3.1 seconds
Started Aug 14 05:30:23 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 223064 kb
Host smart-e0da847f-b1b0-4e5d-88ca-0f74d8f9eb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577405059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3577405059
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3936119113
Short name T248
Test name
Test status
Simulation time 229881924 ps
CPU time 23.43 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:40 PM PDT 24
Peak memory 250800 kb
Host smart-508ff2c5-e0ee-454d-b282-39619ff0ebb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936119113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3936119113
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1528081037
Short name T234
Test name
Test status
Simulation time 289077838 ps
CPU time 9.1 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:30:29 PM PDT 24
Peak memory 244092 kb
Host smart-3d76184a-d640-4366-84b1-d3d0d94008b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528081037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1528081037
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3040621367
Short name T702
Test name
Test status
Simulation time 2669239254 ps
CPU time 64.75 seconds
Started Aug 14 05:30:18 PM PDT 24
Finished Aug 14 05:31:23 PM PDT 24
Peak memory 250972 kb
Host smart-2363d7d5-5007-4ab7-8b02-023d987404b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040621367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3040621367
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1921436849
Short name T580
Test name
Test status
Simulation time 170791964 ps
CPU time 0.9 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:17 PM PDT 24
Peak memory 212816 kb
Host smart-6d733439-b0a9-4e78-a4b2-8cf95f1524c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921436849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1921436849
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.340953020
Short name T86
Test name
Test status
Simulation time 68566435 ps
CPU time 0.83 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 208672 kb
Host smart-f1d55b0e-34f5-4da2-a5cd-04ba77b1aabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340953020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.340953020
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.57418723
Short name T498
Test name
Test status
Simulation time 897438502 ps
CPU time 9.16 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 225904 kb
Host smart-27dfe1e7-7b17-49b2-b143-e217e3ada95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57418723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.57418723
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.610932687
Short name T365
Test name
Test status
Simulation time 1635122271 ps
CPU time 11.89 seconds
Started Aug 14 05:30:27 PM PDT 24
Finished Aug 14 05:30:39 PM PDT 24
Peak memory 217160 kb
Host smart-0923ab8e-a74b-405b-9fcc-cb97f5579a57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610932687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.610932687
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.905441712
Short name T91
Test name
Test status
Simulation time 11223178661 ps
CPU time 44.75 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:31:11 PM PDT 24
Peak memory 218948 kb
Host smart-9dc02b5c-f533-4106-b2aa-cb3262ef5a66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905441712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.905441712
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1125234093
Short name T594
Test name
Test status
Simulation time 2640041664 ps
CPU time 19.93 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:37 PM PDT 24
Peak memory 218284 kb
Host smart-d1b0de9e-cde2-42e1-8d66-70584358c41b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125234093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1125234093
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2066895583
Short name T832
Test name
Test status
Simulation time 465377588 ps
CPU time 2.58 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:20 PM PDT 24
Peak memory 217584 kb
Host smart-77661339-3318-4795-ae87-189579b268c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066895583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2066895583
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3748797672
Short name T727
Test name
Test status
Simulation time 4815278366 ps
CPU time 38.76 seconds
Started Aug 14 05:30:22 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 252008 kb
Host smart-32bca4b2-e0f0-40ce-9728-e27ac0bc62e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748797672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3748797672
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.428459589
Short name T704
Test name
Test status
Simulation time 359214928 ps
CPU time 12.09 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:29 PM PDT 24
Peak memory 250872 kb
Host smart-bd85054b-89fb-40b4-9183-82ead6a5352a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428459589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.428459589
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.406961411
Short name T517
Test name
Test status
Simulation time 258286943 ps
CPU time 3.02 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:30:22 PM PDT 24
Peak memory 218292 kb
Host smart-cb03adc2-2221-4ec5-ab16-647b1b21d4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406961411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.406961411
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1039471122
Short name T652
Test name
Test status
Simulation time 551620667 ps
CPU time 10.5 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:36 PM PDT 24
Peak memory 226096 kb
Host smart-f8e647d6-3c82-423a-b1f2-2477a0799b8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039471122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1039471122
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4100268684
Short name T377
Test name
Test status
Simulation time 570514226 ps
CPU time 18.2 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:44 PM PDT 24
Peak memory 226020 kb
Host smart-32e51fec-052f-4fd2-bb11-ac8902288343
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100268684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4100268684
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2254515100
Short name T730
Test name
Test status
Simulation time 1609246519 ps
CPU time 15.03 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:40 PM PDT 24
Peak memory 218256 kb
Host smart-0d79e527-a55b-4f4a-971b-584ef73d1bb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254515100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2254515100
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1230832917
Short name T346
Test name
Test status
Simulation time 258330963 ps
CPU time 11.29 seconds
Started Aug 14 05:30:20 PM PDT 24
Finished Aug 14 05:30:32 PM PDT 24
Peak memory 226032 kb
Host smart-796f8118-f4cd-4dfa-b89f-e8356dad3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230832917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1230832917
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2794684411
Short name T864
Test name
Test status
Simulation time 195483093 ps
CPU time 6.14 seconds
Started Aug 14 05:30:22 PM PDT 24
Finished Aug 14 05:30:29 PM PDT 24
Peak memory 217640 kb
Host smart-4e546e82-f9dc-4309-9e80-8f99482c0642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794684411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2794684411
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3058345512
Short name T549
Test name
Test status
Simulation time 630990684 ps
CPU time 37.51 seconds
Started Aug 14 05:30:17 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 250932 kb
Host smart-f6683871-c25e-42cf-968f-cb06a332cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058345512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3058345512
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1643950499
Short name T708
Test name
Test status
Simulation time 204684017 ps
CPU time 3.72 seconds
Started Aug 14 05:30:16 PM PDT 24
Finished Aug 14 05:30:20 PM PDT 24
Peak memory 222680 kb
Host smart-359cc1df-57a0-4dc2-a548-456c8abc48e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643950499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1643950499
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.360326460
Short name T587
Test name
Test status
Simulation time 3700337178 ps
CPU time 135.3 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:32:41 PM PDT 24
Peak memory 228524 kb
Host smart-b290192f-8120-4d92-9272-4885131aaf4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360326460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.360326460
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3495139859
Short name T530
Test name
Test status
Simulation time 34774607 ps
CPU time 0.82 seconds
Started Aug 14 05:30:19 PM PDT 24
Finished Aug 14 05:30:20 PM PDT 24
Peak memory 211856 kb
Host smart-ebb3ea4b-9dad-48e1-90d1-5bc617025691
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495139859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3495139859
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2297309643
Short name T566
Test name
Test status
Simulation time 33416333 ps
CPU time 1.17 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:27 PM PDT 24
Peak memory 208980 kb
Host smart-31a31f77-9486-43fd-a022-54ee2ae00587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297309643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2297309643
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3572456213
Short name T225
Test name
Test status
Simulation time 2718106390 ps
CPU time 15.4 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:41 PM PDT 24
Peak memory 219184 kb
Host smart-40ae12c9-0793-4dc7-a076-de34beaa1a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572456213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3572456213
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2504060431
Short name T819
Test name
Test status
Simulation time 10207256224 ps
CPU time 19.59 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 217700 kb
Host smart-245314f3-0ed7-4095-8b02-37508388586a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504060431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2504060431
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4133534049
Short name T547
Test name
Test status
Simulation time 2292340259 ps
CPU time 30.77 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 218324 kb
Host smart-6992a088-e9d5-4c8c-a198-91ff02a1ac12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133534049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4133534049
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4041823049
Short name T658
Test name
Test status
Simulation time 384808431 ps
CPU time 6.33 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:32 PM PDT 24
Peak memory 223024 kb
Host smart-983be57d-5163-491f-bcec-03085f20a3ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041823049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4041823049
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1770068405
Short name T434
Test name
Test status
Simulation time 541587551 ps
CPU time 3.96 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:30 PM PDT 24
Peak memory 217484 kb
Host smart-5fda14a3-440c-485e-b981-366a3c3b0e79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770068405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1770068405
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.4156205823
Short name T806
Test name
Test status
Simulation time 450229078 ps
CPU time 11.97 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:38 PM PDT 24
Peak memory 250424 kb
Host smart-08e5607c-7812-4091-8424-6caadf618768
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156205823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.4156205823
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2485943474
Short name T548
Test name
Test status
Simulation time 151638492 ps
CPU time 2.31 seconds
Started Aug 14 05:30:24 PM PDT 24
Finished Aug 14 05:30:27 PM PDT 24
Peak memory 218296 kb
Host smart-57350025-ac38-492c-b73c-886b52c5d020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485943474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2485943474
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3661458130
Short name T726
Test name
Test status
Simulation time 853843075 ps
CPU time 7.82 seconds
Started Aug 14 05:30:23 PM PDT 24
Finished Aug 14 05:30:31 PM PDT 24
Peak memory 226208 kb
Host smart-0d9d0876-0602-4f8e-80f5-d3eccd558046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661458130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3661458130
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3056612675
Short name T794
Test name
Test status
Simulation time 774960144 ps
CPU time 24.93 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:31:02 PM PDT 24
Peak memory 226008 kb
Host smart-2dc822fa-eb04-435c-bb04-e435009a4d9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056612675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3056612675
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.26307393
Short name T546
Test name
Test status
Simulation time 2961415902 ps
CPU time 10.59 seconds
Started Aug 14 05:30:37 PM PDT 24
Finished Aug 14 05:30:48 PM PDT 24
Peak memory 218276 kb
Host smart-32f921a7-19ca-42ee-93aa-675a59378555
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.26307393
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.656729476
Short name T842
Test name
Test status
Simulation time 886342161 ps
CPU time 15.39 seconds
Started Aug 14 05:30:27 PM PDT 24
Finished Aug 14 05:30:43 PM PDT 24
Peak memory 225132 kb
Host smart-763c1145-4ac2-49c2-80f4-9344d2d0d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656729476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.656729476
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2316151437
Short name T171
Test name
Test status
Simulation time 218935636 ps
CPU time 3.18 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:29 PM PDT 24
Peak memory 217640 kb
Host smart-a21107fe-54e1-4f63-84c0-a3658646665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316151437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2316151437
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2418576782
Short name T762
Test name
Test status
Simulation time 751277793 ps
CPU time 34.81 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 250916 kb
Host smart-254a0631-9658-42f9-8f0d-bae0afdf160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418576782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2418576782
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.436934163
Short name T324
Test name
Test status
Simulation time 148378290 ps
CPU time 6.62 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:42 PM PDT 24
Peak memory 247344 kb
Host smart-8458362f-5157-4edb-b892-4f437d0d577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436934163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.436934163
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3833074410
Short name T635
Test name
Test status
Simulation time 1859078480 ps
CPU time 49.13 seconds
Started Aug 14 05:30:28 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 250924 kb
Host smart-a2580166-7a8d-4712-9d45-9ab494a334cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833074410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3833074410
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.711924449
Short name T84
Test name
Test status
Simulation time 28751184 ps
CPU time 0.88 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 208876 kb
Host smart-606ba06e-17f1-43f2-a564-d1ec2c9393ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711924449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.711924449
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.398822864
Short name T693
Test name
Test status
Simulation time 747601967 ps
CPU time 14.96 seconds
Started Aug 14 05:30:31 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 218376 kb
Host smart-47d00d8e-afa2-4ca6-88f5-53dc0c068fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398822864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.398822864
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.61549329
Short name T282
Test name
Test status
Simulation time 2981249999 ps
CPU time 9.03 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:36 PM PDT 24
Peak memory 217616 kb
Host smart-db8cdaad-8d95-4d4e-8ba1-74c7b2673ce7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61549329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.61549329
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1400747754
Short name T831
Test name
Test status
Simulation time 4011429969 ps
CPU time 32.38 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:59 PM PDT 24
Peak memory 219048 kb
Host smart-1d9162bd-0414-4416-8ba8-daa9e138c335
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400747754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1400747754
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1993088890
Short name T374
Test name
Test status
Simulation time 615983915 ps
CPU time 6.97 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:32 PM PDT 24
Peak memory 218232 kb
Host smart-e20697c6-8f9c-4532-8270-fbd5bf9f358d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993088890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1993088890
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1090996952
Short name T685
Test name
Test status
Simulation time 375997991 ps
CPU time 3.6 seconds
Started Aug 14 05:30:31 PM PDT 24
Finished Aug 14 05:30:35 PM PDT 24
Peak memory 217648 kb
Host smart-4ea05311-ccf0-4336-b6fe-68ba6f3d76e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090996952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1090996952
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.542171535
Short name T8
Test name
Test status
Simulation time 9021232537 ps
CPU time 44.09 seconds
Started Aug 14 05:30:28 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 278832 kb
Host smart-5a5ab641-86e5-4049-85c8-ec14ed659f05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542171535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.542171535
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2094941780
Short name T290
Test name
Test status
Simulation time 1124627986 ps
CPU time 10.82 seconds
Started Aug 14 05:30:32 PM PDT 24
Finished Aug 14 05:30:43 PM PDT 24
Peak memory 250864 kb
Host smart-beb6f49f-7856-4bf7-b5b1-29d5731a28a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094941780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2094941780
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1522080793
Short name T640
Test name
Test status
Simulation time 61844917 ps
CPU time 1.69 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 221676 kb
Host smart-e4562d57-0cc3-411a-975c-b75afca0c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522080793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1522080793
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3903549159
Short name T856
Test name
Test status
Simulation time 2062064034 ps
CPU time 13.22 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:39 PM PDT 24
Peak memory 218516 kb
Host smart-d8f73866-8518-442e-ac9c-469fa85901f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903549159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3903549159
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1762259113
Short name T850
Test name
Test status
Simulation time 5012729562 ps
CPU time 11.57 seconds
Started Aug 14 05:30:25 PM PDT 24
Finished Aug 14 05:30:37 PM PDT 24
Peak memory 226092 kb
Host smart-b3d217a7-0419-4e19-b1d7-d8cb70b4905e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762259113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1762259113
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2752341094
Short name T261
Test name
Test status
Simulation time 5881132633 ps
CPU time 16.3 seconds
Started Aug 14 05:30:24 PM PDT 24
Finished Aug 14 05:30:41 PM PDT 24
Peak memory 226108 kb
Host smart-c15f4532-f773-4e31-9f08-9c9225adcdeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752341094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2752341094
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.871094211
Short name T502
Test name
Test status
Simulation time 280248207 ps
CPU time 8.04 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:34 PM PDT 24
Peak memory 218356 kb
Host smart-73865b46-a7d4-4b0a-9486-c5cb62fc45f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871094211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.871094211
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3072457379
Short name T60
Test name
Test status
Simulation time 26741365 ps
CPU time 1.77 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 214084 kb
Host smart-e2f486a4-cb05-4036-9b94-0e5cadfab88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072457379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3072457379
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3032664033
Short name T575
Test name
Test status
Simulation time 194618926 ps
CPU time 21.35 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:48 PM PDT 24
Peak memory 250960 kb
Host smart-25f06a06-b039-416a-8887-32f10daf48a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032664033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3032664033
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3142242519
Short name T80
Test name
Test status
Simulation time 109822131 ps
CPU time 8.39 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 247052 kb
Host smart-ea18ca8f-192d-4bcd-b278-ab05357ad440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142242519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3142242519
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3243620645
Short name T861
Test name
Test status
Simulation time 6976605903 ps
CPU time 115.52 seconds
Started Aug 14 05:30:24 PM PDT 24
Finished Aug 14 05:32:20 PM PDT 24
Peak memory 250900 kb
Host smart-7445fec9-8524-4ae4-b7a3-0beeb035a3f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243620645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3243620645
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2834891544
Short name T155
Test name
Test status
Simulation time 3179541476 ps
CPU time 19.29 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 259296 kb
Host smart-6e0d0379-8260-44ac-b465-34b3a9ee957a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2834891544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2834891544
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2472583670
Short name T779
Test name
Test status
Simulation time 40325864 ps
CPU time 0.84 seconds
Started Aug 14 05:30:26 PM PDT 24
Finished Aug 14 05:30:27 PM PDT 24
Peak memory 211796 kb
Host smart-388e27f2-dba3-4750-87fc-fcdb35aab429
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472583670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2472583670
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2093469882
Short name T655
Test name
Test status
Simulation time 250940954 ps
CPU time 0.92 seconds
Started Aug 14 05:30:34 PM PDT 24
Finished Aug 14 05:30:35 PM PDT 24
Peak memory 208876 kb
Host smart-63a10cdc-d359-48b9-8c2a-64b273e82b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093469882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2093469882
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1907275784
Short name T96
Test name
Test status
Simulation time 986040970 ps
CPU time 19.86 seconds
Started Aug 14 05:30:40 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 218292 kb
Host smart-85ac89f9-f0d9-4565-bf19-31023409555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907275784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1907275784
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2265061252
Short name T24
Test name
Test status
Simulation time 194309903 ps
CPU time 5.57 seconds
Started Aug 14 05:30:33 PM PDT 24
Finished Aug 14 05:30:39 PM PDT 24
Peak memory 217128 kb
Host smart-25fd11e5-7b75-41f4-bf41-98bbfffbdb73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265061252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2265061252
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3357692260
Short name T30
Test name
Test status
Simulation time 1772526361 ps
CPU time 31.41 seconds
Started Aug 14 05:30:40 PM PDT 24
Finished Aug 14 05:31:11 PM PDT 24
Peak memory 218860 kb
Host smart-23da7417-95f0-4c78-b0c0-87e51ac975af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357692260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3357692260
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.823325677
Short name T754
Test name
Test status
Simulation time 154255336 ps
CPU time 5.73 seconds
Started Aug 14 05:30:34 PM PDT 24
Finished Aug 14 05:30:40 PM PDT 24
Peak memory 218228 kb
Host smart-64926bfe-009b-42f3-92f4-dbca448a53b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823325677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.823325677
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3307695675
Short name T759
Test name
Test status
Simulation time 2940331798 ps
CPU time 5.76 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:30:42 PM PDT 24
Peak memory 217308 kb
Host smart-dce258d4-4dde-4734-a128-3f4eae007ba3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307695675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3307695675
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1677887377
Short name T446
Test name
Test status
Simulation time 8108585796 ps
CPU time 68.67 seconds
Started Aug 14 05:30:38 PM PDT 24
Finished Aug 14 05:31:46 PM PDT 24
Peak memory 277628 kb
Host smart-ea33cc49-d864-420d-ade6-aaa788405534
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677887377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1677887377
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1057984967
Short name T607
Test name
Test status
Simulation time 450956746 ps
CPU time 18.9 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 250592 kb
Host smart-4fe9dfa2-09b8-4be6-853a-c9fa2e8ebb8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057984967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1057984967
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.69311033
Short name T569
Test name
Test status
Simulation time 39611331 ps
CPU time 2.32 seconds
Started Aug 14 05:30:34 PM PDT 24
Finished Aug 14 05:30:36 PM PDT 24
Peak memory 218296 kb
Host smart-7be91b9e-4d9d-420c-8a58-811801c95681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69311033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.69311033
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2279371012
Short name T639
Test name
Test status
Simulation time 171930412 ps
CPU time 9.41 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 226060 kb
Host smart-6e6c3a62-b103-4814-b6be-97fac3e4eb9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279371012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2279371012
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1764538725
Short name T153
Test name
Test status
Simulation time 902587300 ps
CPU time 7.47 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:43 PM PDT 24
Peak memory 226016 kb
Host smart-4e4f5ce7-d6b4-4394-af88-2eb19550eb86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764538725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1764538725
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.532005105
Short name T49
Test name
Test status
Simulation time 1047537209 ps
CPU time 10.26 seconds
Started Aug 14 05:30:34 PM PDT 24
Finished Aug 14 05:30:44 PM PDT 24
Peak memory 218252 kb
Host smart-3e6c6622-82bc-4f63-8ef9-15f0bae8ed44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532005105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.532005105
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1898259651
Short name T750
Test name
Test status
Simulation time 2553713610 ps
CPU time 14.63 seconds
Started Aug 14 05:30:40 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 218404 kb
Host smart-0b57e7b4-03b7-45a4-afc0-d358c7cdc7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898259651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1898259651
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3733108508
Short name T821
Test name
Test status
Simulation time 111555688 ps
CPU time 1.86 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 217636 kb
Host smart-1f0a7c8b-fd0a-4b63-b872-61f0747884da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733108508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3733108508
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2359385794
Short name T102
Test name
Test status
Simulation time 907766928 ps
CPU time 27.3 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 250924 kb
Host smart-3525d7b4-7b59-4bcb-96d4-7b564c78cdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359385794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2359385794
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4115001746
Short name T837
Test name
Test status
Simulation time 164573203 ps
CPU time 5.95 seconds
Started Aug 14 05:30:32 PM PDT 24
Finished Aug 14 05:30:38 PM PDT 24
Peak memory 244868 kb
Host smart-42eaaa96-0e04-4cc9-be1f-85a75c2f62e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115001746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4115001746
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.252392612
Short name T466
Test name
Test status
Simulation time 18143119146 ps
CPU time 182.38 seconds
Started Aug 14 05:30:39 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 276800 kb
Host smart-a35ac21b-cd96-4519-8fac-abed68c1e479
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252392612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.252392612
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4169742828
Short name T347
Test name
Test status
Simulation time 11552504 ps
CPU time 0.86 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 211912 kb
Host smart-55273a6e-67fe-42d1-b0bc-12d7865b19fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169742828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4169742828
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3219618460
Short name T867
Test name
Test status
Simulation time 13206718 ps
CPU time 0.83 seconds
Started Aug 14 05:30:39 PM PDT 24
Finished Aug 14 05:30:40 PM PDT 24
Peak memory 208660 kb
Host smart-71ac25c4-e3b0-4ee3-8328-622ef12bb8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219618460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3219618460
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.964438889
Short name T453
Test name
Test status
Simulation time 1639830764 ps
CPU time 15.01 seconds
Started Aug 14 05:30:41 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 218288 kb
Host smart-970e982f-e5ba-4ed2-a1a2-0e989d593e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964438889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.964438889
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3528280255
Short name T676
Test name
Test status
Simulation time 1080364624 ps
CPU time 6.93 seconds
Started Aug 14 05:30:34 PM PDT 24
Finished Aug 14 05:30:41 PM PDT 24
Peak memory 217072 kb
Host smart-ef667e4f-f3d1-423c-9646-0dc33b3f4b0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528280255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3528280255
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1449545298
Short name T81
Test name
Test status
Simulation time 8726425658 ps
CPU time 64.5 seconds
Started Aug 14 05:30:37 PM PDT 24
Finished Aug 14 05:31:41 PM PDT 24
Peak memory 219056 kb
Host smart-79495d4d-1962-4693-a255-890223711e4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449545298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1449545298
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1145692782
Short name T443
Test name
Test status
Simulation time 277180427 ps
CPU time 4.74 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:30:41 PM PDT 24
Peak memory 218224 kb
Host smart-db6855f5-7217-432d-9d16-d0e4f2b62758
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145692782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1145692782
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2167273396
Short name T70
Test name
Test status
Simulation time 1488905131 ps
CPU time 10.17 seconds
Started Aug 14 05:30:38 PM PDT 24
Finished Aug 14 05:30:49 PM PDT 24
Peak memory 217560 kb
Host smart-016bb233-eb4a-408e-a720-5ad1a513fb8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167273396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2167273396
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.28292347
Short name T560
Test name
Test status
Simulation time 1003858981 ps
CPU time 36.65 seconds
Started Aug 14 05:30:41 PM PDT 24
Finished Aug 14 05:31:18 PM PDT 24
Peak memory 267264 kb
Host smart-8678a703-67ce-448d-8744-61fed593a2d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_state_failure.28292347
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1390555360
Short name T330
Test name
Test status
Simulation time 965465694 ps
CPU time 11.31 seconds
Started Aug 14 05:30:34 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 247548 kb
Host smart-f0c1c726-4605-4d75-b515-57fc44670fb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390555360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1390555360
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.4147370161
Short name T573
Test name
Test status
Simulation time 139109503 ps
CPU time 4.14 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:30:40 PM PDT 24
Peak memory 218296 kb
Host smart-0e195902-28ba-466c-90e1-737f84df5a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147370161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.4147370161
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2781014088
Short name T667
Test name
Test status
Simulation time 466770050 ps
CPU time 9.05 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:44 PM PDT 24
Peak memory 218208 kb
Host smart-c218fd22-0f37-450b-b4ac-4114c1b0f3d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781014088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2781014088
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2945093725
Short name T731
Test name
Test status
Simulation time 245945711 ps
CPU time 9.85 seconds
Started Aug 14 05:30:41 PM PDT 24
Finished Aug 14 05:30:51 PM PDT 24
Peak memory 226028 kb
Host smart-1d5547c3-7a29-4b05-b309-4772aea02495
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945093725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2945093725
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3291424751
Short name T93
Test name
Test status
Simulation time 200898812 ps
CPU time 8.61 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:44 PM PDT 24
Peak memory 226016 kb
Host smart-2c3421d2-94ac-40b2-b3ca-210d0c85a102
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291424751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3291424751
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3501933356
Short name T564
Test name
Test status
Simulation time 283580933 ps
CPU time 7.99 seconds
Started Aug 14 05:30:37 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 224388 kb
Host smart-41fd220d-cec7-4bdc-ade0-c3931f2eb3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501933356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3501933356
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3756065641
Short name T150
Test name
Test status
Simulation time 46157206 ps
CPU time 2.7 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:30:39 PM PDT 24
Peak memory 214012 kb
Host smart-6487e256-0bea-49e1-ad2b-ed4d586a6649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756065641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3756065641
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.279218964
Short name T631
Test name
Test status
Simulation time 215396495 ps
CPU time 24.34 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:31:10 PM PDT 24
Peak memory 250932 kb
Host smart-d84c2f2a-7e16-4f5f-bd35-883a7d9915f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279218964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.279218964
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.979809890
Short name T519
Test name
Test status
Simulation time 87959156 ps
CPU time 6.46 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:42 PM PDT 24
Peak memory 246772 kb
Host smart-bba7b133-53c8-4a4f-902b-bdd4ec8fdf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979809890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.979809890
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.45921337
Short name T89
Test name
Test status
Simulation time 20565471254 ps
CPU time 99.45 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:32:26 PM PDT 24
Peak memory 275232 kb
Host smart-08220b96-7b53-4765-a0d8-3d9695cda184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=45921337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.45921337
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2429365112
Short name T500
Test name
Test status
Simulation time 15013683 ps
CPU time 0.93 seconds
Started Aug 14 05:30:35 PM PDT 24
Finished Aug 14 05:30:36 PM PDT 24
Peak memory 211916 kb
Host smart-3b133837-94e3-44d2-a5dd-84592a2a3444
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429365112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2429365112
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.375173159
Short name T270
Test name
Test status
Simulation time 20845350 ps
CPU time 1.22 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 209080 kb
Host smart-a43df8fa-beb5-4f10-9b23-c656edf5e6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375173159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.375173159
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.755842701
Short name T495
Test name
Test status
Simulation time 232397788 ps
CPU time 9.49 seconds
Started Aug 14 05:31:15 PM PDT 24
Finished Aug 14 05:31:25 PM PDT 24
Peak memory 218220 kb
Host smart-a730c515-9586-445f-aa86-610a42bf5ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755842701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.755842701
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2582558413
Short name T668
Test name
Test status
Simulation time 276210573 ps
CPU time 4.4 seconds
Started Aug 14 05:30:43 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 217024 kb
Host smart-96e64465-1ec9-456a-87d6-3e57c3a5f4cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582558413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2582558413
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2513930698
Short name T793
Test name
Test status
Simulation time 1117268705 ps
CPU time 35.28 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:31:19 PM PDT 24
Peak memory 218872 kb
Host smart-a8179a5c-1acd-4c31-96c7-b1b812c6b82f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513930698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2513930698
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.903469508
Short name T451
Test name
Test status
Simulation time 705419788 ps
CPU time 10.53 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 223128 kb
Host smart-72aa42f0-516d-4d2a-aaf1-3f9056e7d971
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903469508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.903469508
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2278459162
Short name T76
Test name
Test status
Simulation time 215901593 ps
CPU time 6.82 seconds
Started Aug 14 05:30:43 PM PDT 24
Finished Aug 14 05:30:50 PM PDT 24
Peak memory 217572 kb
Host smart-70a15fcb-0c42-412c-995d-ada667f3e95b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278459162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2278459162
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2083797915
Short name T615
Test name
Test status
Simulation time 2283631537 ps
CPU time 81.23 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 281216 kb
Host smart-89c32dbd-7393-422c-abba-54cd5a3fa57b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083797915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2083797915
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3658416926
Short name T745
Test name
Test status
Simulation time 345142184 ps
CPU time 10.7 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 250776 kb
Host smart-7ddf7fd3-8b63-4b4a-a92a-d251e6864dba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658416926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3658416926
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1826681169
Short name T503
Test name
Test status
Simulation time 64687870 ps
CPU time 2.72 seconds
Started Aug 14 05:30:43 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 218276 kb
Host smart-b638bfd2-6ee2-4557-b279-58932b59e820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826681169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1826681169
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4012398904
Short name T734
Test name
Test status
Simulation time 1032707278 ps
CPU time 12.91 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 226108 kb
Host smart-6c719f95-3241-452d-b61d-6e6ff2d12b1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012398904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4012398904
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1980028409
Short name T237
Test name
Test status
Simulation time 549146689 ps
CPU time 10.29 seconds
Started Aug 14 05:30:42 PM PDT 24
Finished Aug 14 05:30:53 PM PDT 24
Peak memory 226028 kb
Host smart-9d67b72c-cb10-400c-b54e-99a8608b92b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980028409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1980028409
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2630025310
Short name T278
Test name
Test status
Simulation time 1174548842 ps
CPU time 12.22 seconds
Started Aug 14 05:30:48 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 218252 kb
Host smart-05c0ad82-1c4d-4b52-89a8-cad58d8fd565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630025310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2630025310
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1047866769
Short name T561
Test name
Test status
Simulation time 587940626 ps
CPU time 11.03 seconds
Started Aug 14 05:30:50 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 226096 kb
Host smart-5537ecf8-28fc-488e-93dd-15cc33c7d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047866769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1047866769
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1114532571
Short name T378
Test name
Test status
Simulation time 165893337 ps
CPU time 1.43 seconds
Started Aug 14 05:30:36 PM PDT 24
Finished Aug 14 05:30:38 PM PDT 24
Peak memory 217640 kb
Host smart-07529a5c-dc04-452f-b32d-012f3efeac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114532571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1114532571
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1748521487
Short name T323
Test name
Test status
Simulation time 1455933889 ps
CPU time 32.54 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:31:18 PM PDT 24
Peak memory 250892 kb
Host smart-36e881bb-85bb-49af-9835-b971f99d9f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748521487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1748521487
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.712438217
Short name T307
Test name
Test status
Simulation time 70824127 ps
CPU time 9.05 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:53 PM PDT 24
Peak memory 242740 kb
Host smart-9ae223c5-46c0-4c5a-b6e1-007eea94778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712438217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.712438217
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1261418461
Short name T177
Test name
Test status
Simulation time 22830486694 ps
CPU time 123.3 seconds
Started Aug 14 05:30:41 PM PDT 24
Finished Aug 14 05:32:45 PM PDT 24
Peak memory 283712 kb
Host smart-11740b12-3ef1-4381-90fc-16572eb87cb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261418461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1261418461
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1732629846
Short name T260
Test name
Test status
Simulation time 22424129 ps
CPU time 0.97 seconds
Started Aug 14 05:30:40 PM PDT 24
Finished Aug 14 05:30:41 PM PDT 24
Peak memory 211888 kb
Host smart-417eae1d-55dd-4b20-be48-ac7812f01d1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732629846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1732629846
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1816675020
Short name T854
Test name
Test status
Simulation time 60116395 ps
CPU time 1.1 seconds
Started Aug 14 05:29:37 PM PDT 24
Finished Aug 14 05:29:38 PM PDT 24
Peak memory 209044 kb
Host smart-96bc187e-0867-482e-a70e-3b15ca51ce24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816675020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1816675020
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3937392274
Short name T741
Test name
Test status
Simulation time 1194498411 ps
CPU time 12.5 seconds
Started Aug 14 05:29:31 PM PDT 24
Finished Aug 14 05:29:44 PM PDT 24
Peak memory 226072 kb
Host smart-ce11ca1d-3060-46a7-ac04-f95d2131d142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937392274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3937392274
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2737945963
Short name T28
Test name
Test status
Simulation time 580224684 ps
CPU time 2.92 seconds
Started Aug 14 05:29:32 PM PDT 24
Finished Aug 14 05:29:35 PM PDT 24
Peak memory 217100 kb
Host smart-03214ff0-aa8d-451f-ae02-c4a0139b628f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737945963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2737945963
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.328568559
Short name T663
Test name
Test status
Simulation time 10034751820 ps
CPU time 59.61 seconds
Started Aug 14 05:29:29 PM PDT 24
Finished Aug 14 05:30:29 PM PDT 24
Peak memory 219852 kb
Host smart-bec8e90f-ae7b-4175-a3af-a39df28ef5cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328568559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.328568559
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2738591685
Short name T689
Test name
Test status
Simulation time 648788493 ps
CPU time 7.54 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:38 PM PDT 24
Peak memory 217404 kb
Host smart-2c15098e-58ef-4664-a926-49705656bb70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738591685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
738591685
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1890380253
Short name T415
Test name
Test status
Simulation time 859009862 ps
CPU time 6.62 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:37 PM PDT 24
Peak memory 222856 kb
Host smart-6754734a-aa1c-4ccf-9979-7d072209a73e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890380253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1890380253
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.803669694
Short name T648
Test name
Test status
Simulation time 21301901122 ps
CPU time 29.65 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 217636 kb
Host smart-426324b6-e77b-4165-a967-c7e5f26e7eb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803669694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.803669694
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1634036301
Short name T533
Test name
Test status
Simulation time 1164912000 ps
CPU time 15.52 seconds
Started Aug 14 05:29:32 PM PDT 24
Finished Aug 14 05:29:48 PM PDT 24
Peak memory 217560 kb
Host smart-083bd6cd-e715-4bde-8324-580b6255596b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634036301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1634036301
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2465888227
Short name T281
Test name
Test status
Simulation time 1076929986 ps
CPU time 31.82 seconds
Started Aug 14 05:29:33 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 250900 kb
Host smart-f7fdadd8-2352-45ca-a184-905510280768
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465888227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2465888227
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.4188376050
Short name T486
Test name
Test status
Simulation time 2384096010 ps
CPU time 13.35 seconds
Started Aug 14 05:29:33 PM PDT 24
Finished Aug 14 05:29:46 PM PDT 24
Peak memory 247488 kb
Host smart-f1c9bf9f-dce3-4523-935a-79345797bc53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188376050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.4188376050
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.812614197
Short name T735
Test name
Test status
Simulation time 68423822 ps
CPU time 2.95 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:33 PM PDT 24
Peak memory 218304 kb
Host smart-a4fbce93-a2b8-4856-b0cb-154edf12e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812614197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.812614197
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2824347828
Short name T360
Test name
Test status
Simulation time 374252328 ps
CPU time 14.61 seconds
Started Aug 14 05:29:28 PM PDT 24
Finished Aug 14 05:29:43 PM PDT 24
Peak memory 214708 kb
Host smart-542ba890-ee4a-4616-aa90-523087375486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824347828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2824347828
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.582015336
Short name T43
Test name
Test status
Simulation time 1076885475 ps
CPU time 40.12 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 271240 kb
Host smart-39cd1073-4af1-46f0-972d-6b8d0f71d34b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582015336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.582015336
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1287653419
Short name T308
Test name
Test status
Simulation time 521694492 ps
CPU time 11.83 seconds
Started Aug 14 05:29:32 PM PDT 24
Finished Aug 14 05:29:44 PM PDT 24
Peak memory 218940 kb
Host smart-1b02e0ca-8198-4974-b39b-7114cfdc8f53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287653419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1287653419
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.504210598
Short name T657
Test name
Test status
Simulation time 899784883 ps
CPU time 10.16 seconds
Started Aug 14 05:29:31 PM PDT 24
Finished Aug 14 05:29:41 PM PDT 24
Peak memory 226020 kb
Host smart-f61c40b5-e435-448e-9c84-2d7abe34c569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504210598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.504210598
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3799573791
Short name T715
Test name
Test status
Simulation time 721211187 ps
CPU time 8.17 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:38 PM PDT 24
Peak memory 218236 kb
Host smart-18f09ad0-9272-4ba4-8776-673c5ec5d63f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799573791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
799573791
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3154381954
Short name T717
Test name
Test status
Simulation time 231606877 ps
CPU time 7.41 seconds
Started Aug 14 05:29:28 PM PDT 24
Finished Aug 14 05:29:36 PM PDT 24
Peak memory 226068 kb
Host smart-c025f54c-8b8f-4da2-95c9-f1ff06a830b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154381954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3154381954
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3143066543
Short name T309
Test name
Test status
Simulation time 268107914 ps
CPU time 2.65 seconds
Started Aug 14 05:29:31 PM PDT 24
Finished Aug 14 05:29:34 PM PDT 24
Peak memory 217652 kb
Host smart-6b96ff94-34e1-4d05-ae95-9529dcab799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143066543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3143066543
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3017882937
Short name T106
Test name
Test status
Simulation time 635832153 ps
CPU time 38.1 seconds
Started Aug 14 05:29:32 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 250912 kb
Host smart-10ad11d6-423c-423f-83cb-00487274e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017882937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3017882937
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.686540258
Short name T214
Test name
Test status
Simulation time 383182442 ps
CPU time 7.55 seconds
Started Aug 14 05:29:30 PM PDT 24
Finished Aug 14 05:29:37 PM PDT 24
Peak memory 250920 kb
Host smart-4b5ec1e8-842a-467b-87b1-ee6564cccb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686540258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.686540258
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.628590464
Short name T303
Test name
Test status
Simulation time 8145837174 ps
CPU time 97.25 seconds
Started Aug 14 05:29:33 PM PDT 24
Finished Aug 14 05:31:10 PM PDT 24
Peak memory 272256 kb
Host smart-653f2451-490e-4a93-a824-9b733c2e81f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628590464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.628590464
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1841527355
Short name T431
Test name
Test status
Simulation time 41572268 ps
CPU time 0.97 seconds
Started Aug 14 05:29:33 PM PDT 24
Finished Aug 14 05:29:34 PM PDT 24
Peak memory 211900 kb
Host smart-88fa4cad-994d-4cf2-8a1f-63038235780a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841527355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1841527355
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1952469625
Short name T756
Test name
Test status
Simulation time 39262879 ps
CPU time 1.27 seconds
Started Aug 14 05:30:47 PM PDT 24
Finished Aug 14 05:30:48 PM PDT 24
Peak memory 208980 kb
Host smart-cdd2381a-ce3b-4f3b-91b9-e40138033355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952469625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1952469625
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2767647567
Short name T406
Test name
Test status
Simulation time 1240752506 ps
CPU time 15.57 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 217100 kb
Host smart-fae5873e-1609-4fe1-be45-cba1c157a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767647567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2767647567
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.251709030
Short name T493
Test name
Test status
Simulation time 578928025 ps
CPU time 6.98 seconds
Started Aug 14 05:30:42 PM PDT 24
Finished Aug 14 05:30:49 PM PDT 24
Peak memory 217184 kb
Host smart-e4d9b247-7ab6-4642-9682-90c56035521c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251709030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.251709030
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1988031861
Short name T535
Test name
Test status
Simulation time 64672386 ps
CPU time 3.46 seconds
Started Aug 14 05:30:43 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 218296 kb
Host smart-1c37be60-c39e-49a5-bfef-26471f45a026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988031861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1988031861
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2051629550
Short name T688
Test name
Test status
Simulation time 6143212756 ps
CPU time 16.06 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:31:02 PM PDT 24
Peak memory 220024 kb
Host smart-47d4feb4-6090-4c86-b21f-d7da81d033a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051629550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2051629550
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1800023528
Short name T545
Test name
Test status
Simulation time 371017888 ps
CPU time 11.35 seconds
Started Aug 14 05:30:42 PM PDT 24
Finished Aug 14 05:30:53 PM PDT 24
Peak memory 226016 kb
Host smart-3beb0fe0-fca2-47a9-8a22-01075876a5ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800023528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1800023528
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2957225453
Short name T672
Test name
Test status
Simulation time 252869594 ps
CPU time 8.61 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 218264 kb
Host smart-8b0d2fde-783b-4e60-9dd9-9d766481bf54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957225453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2957225453
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3556985269
Short name T671
Test name
Test status
Simulation time 758023855 ps
CPU time 9.24 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 225328 kb
Host smart-996bd816-026d-4596-ad74-7ad0bd771989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556985269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3556985269
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3835115643
Short name T62
Test name
Test status
Simulation time 165359433 ps
CPU time 1.16 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 217648 kb
Host smart-e35128b0-e4c2-4b39-af54-6616fe57d532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835115643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3835115643
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.108328802
Short name T348
Test name
Test status
Simulation time 184467145 ps
CPU time 19.92 seconds
Started Aug 14 05:30:43 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 250980 kb
Host smart-13abec11-31e8-4c2c-a47d-ff58d006b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108328802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.108328802
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4033620865
Short name T341
Test name
Test status
Simulation time 60222349 ps
CPU time 3.3 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 226332 kb
Host smart-bf8c7145-bc3d-4f55-a58a-73e54025454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033620865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4033620865
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3928116912
Short name T469
Test name
Test status
Simulation time 6810750948 ps
CPU time 79.11 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 277676 kb
Host smart-7ee1d5e5-c54d-433b-be57-1cea3eb7c1ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928116912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3928116912
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.626673904
Short name T829
Test name
Test status
Simulation time 54175143 ps
CPU time 0.9 seconds
Started Aug 14 05:30:43 PM PDT 24
Finished Aug 14 05:30:44 PM PDT 24
Peak memory 212924 kb
Host smart-42d05f7f-d65d-470a-8617-eba4a32c91ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626673904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.626673904
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.38693202
Short name T450
Test name
Test status
Simulation time 17442099 ps
CPU time 0.86 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 208872 kb
Host smart-4d409b2a-91f8-48d5-a455-db31b16a6013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.38693202
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.440094256
Short name T355
Test name
Test status
Simulation time 282001117 ps
CPU time 13.36 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 218304 kb
Host smart-955170dc-1261-4815-a4e7-e35a9919a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440094256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.440094256
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4047021120
Short name T23
Test name
Test status
Simulation time 1107236911 ps
CPU time 14.92 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 217352 kb
Host smart-7b27b53f-49bd-4d13-82b7-184217445af9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047021120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4047021120
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1267972602
Short name T863
Test name
Test status
Simulation time 23380803 ps
CPU time 1.73 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 222028 kb
Host smart-d7370cad-a992-4d50-a4d9-75b2187ad330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267972602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1267972602
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1905789640
Short name T285
Test name
Test status
Simulation time 1441230714 ps
CPU time 9.47 seconds
Started Aug 14 05:30:42 PM PDT 24
Finished Aug 14 05:30:51 PM PDT 24
Peak memory 226084 kb
Host smart-5ffccbda-92de-4208-926f-9869dae89090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905789640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1905789640
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.158225894
Short name T233
Test name
Test status
Simulation time 231853137 ps
CPU time 9 seconds
Started Aug 14 05:30:46 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 226016 kb
Host smart-c5131f61-6134-4056-a5c0-b29bfd655543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158225894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.158225894
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2393702462
Short name T675
Test name
Test status
Simulation time 330387815 ps
CPU time 13.17 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 226032 kb
Host smart-7920931c-16a4-4206-a81e-90eabc77beb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393702462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2393702462
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1390310239
Short name T351
Test name
Test status
Simulation time 372270036 ps
CPU time 8.6 seconds
Started Aug 14 05:30:42 PM PDT 24
Finished Aug 14 05:30:51 PM PDT 24
Peak memory 224708 kb
Host smart-22dd3824-12af-4274-a036-82fb90096d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390310239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1390310239
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4075050826
Short name T343
Test name
Test status
Simulation time 196694354 ps
CPU time 3.27 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:48 PM PDT 24
Peak memory 216456 kb
Host smart-2be7babb-c795-472e-a928-69344a7f8b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075050826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4075050826
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.4096171892
Short name T274
Test name
Test status
Simulation time 1020006001 ps
CPU time 28.67 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 250920 kb
Host smart-4e1eefbf-bade-4e18-b787-329d59213f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096171892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.4096171892
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1014370006
Short name T733
Test name
Test status
Simulation time 1648133019 ps
CPU time 11.4 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 250912 kb
Host smart-c84ee390-b0e4-4d13-8f54-74dcda0a6d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014370006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1014370006
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4157208673
Short name T782
Test name
Test status
Simulation time 2572608696 ps
CPU time 63.23 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 267412 kb
Host smart-3d132146-cb6d-423e-8ba1-3e3ce332c533
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157208673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4157208673
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2606611508
Short name T271
Test name
Test status
Simulation time 11622929 ps
CPU time 1.01 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 211928 kb
Host smart-60d6600f-e2e1-42f8-87ab-12d904deffcf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606611508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2606611508
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1330800402
Short name T267
Test name
Test status
Simulation time 34348207 ps
CPU time 0.88 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 208948 kb
Host smart-74f54e8c-5033-4457-8c43-4c39b9c4fa65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330800402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1330800402
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.170697742
Short name T384
Test name
Test status
Simulation time 341428371 ps
CPU time 7.98 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:52 PM PDT 24
Peak memory 218232 kb
Host smart-1957a0c4-7740-4475-99a7-d96e6189deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170697742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.170697742
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3559181750
Short name T836
Test name
Test status
Simulation time 73332631 ps
CPU time 1.22 seconds
Started Aug 14 05:30:48 PM PDT 24
Finished Aug 14 05:30:49 PM PDT 24
Peak memory 216880 kb
Host smart-f518e111-d853-4cab-8a7e-25aaa9aa9cb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559181750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3559181750
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.370974814
Short name T317
Test name
Test status
Simulation time 92388861 ps
CPU time 2.05 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 218292 kb
Host smart-9a06605b-0990-4f23-b5c8-848957f644d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370974814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.370974814
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3154108730
Short name T814
Test name
Test status
Simulation time 1748670176 ps
CPU time 18.54 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 218420 kb
Host smart-09304866-72dc-4070-b3f2-54c8f3261c56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154108730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3154108730
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3715353147
Short name T236
Test name
Test status
Simulation time 2219337976 ps
CPU time 18.07 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 218280 kb
Host smart-7b3acbd0-49d7-4187-b446-6282e8fd6c89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715353147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3715353147
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2234636323
Short name T611
Test name
Test status
Simulation time 1846095036 ps
CPU time 9.45 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 218264 kb
Host smart-17f9993a-866c-499c-a45c-e1e62011b7e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234636323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2234636323
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3712944610
Short name T358
Test name
Test status
Simulation time 46106601 ps
CPU time 1.94 seconds
Started Aug 14 05:30:43 PM PDT 24
Finished Aug 14 05:30:45 PM PDT 24
Peak memory 217648 kb
Host smart-d1463e41-a029-48ec-a972-6d7242a83767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712944610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3712944610
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2719131512
Short name T245
Test name
Test status
Simulation time 176846415 ps
CPU time 20.22 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 250924 kb
Host smart-223208c1-e697-4cd1-a420-c5083fc6489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719131512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2719131512
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2029400353
Short name T475
Test name
Test status
Simulation time 188995426 ps
CPU time 7.64 seconds
Started Aug 14 05:30:44 PM PDT 24
Finished Aug 14 05:30:52 PM PDT 24
Peak memory 250940 kb
Host smart-933bc76e-8e0d-470e-8911-a5e2795e964b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029400353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2029400353
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.404103692
Short name T542
Test name
Test status
Simulation time 61331550 ps
CPU time 1.21 seconds
Started Aug 14 05:30:45 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 217732 kb
Host smart-66b0999d-b6ee-4a56-8c21-c21fb7526228
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404103692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.404103692
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2481481826
Short name T618
Test name
Test status
Simulation time 16495238 ps
CPU time 1.08 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 208988 kb
Host smart-a59c4249-ae30-4743-883f-7461a33b94a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481481826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2481481826
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1338869589
Short name T844
Test name
Test status
Simulation time 569282265 ps
CPU time 14.56 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:07 PM PDT 24
Peak memory 218276 kb
Host smart-199a953e-1dd5-472e-816e-4a10ca986f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338869589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1338869589
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3992980616
Short name T26
Test name
Test status
Simulation time 84936741 ps
CPU time 1.56 seconds
Started Aug 14 05:30:51 PM PDT 24
Finished Aug 14 05:30:52 PM PDT 24
Peak memory 217100 kb
Host smart-cbd36dcf-fc60-4171-82c5-ef54ca8e4abe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992980616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3992980616
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2157255825
Short name T792
Test name
Test status
Simulation time 191768179 ps
CPU time 4.91 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 218204 kb
Host smart-ccf8d8d4-3db1-4acb-af58-197c4c6d4286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157255825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2157255825
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1546515335
Short name T653
Test name
Test status
Simulation time 1124687485 ps
CPU time 13.81 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:07 PM PDT 24
Peak memory 218984 kb
Host smart-f025e62b-9f3a-49b1-a75e-82591ef35689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546515335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1546515335
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.464597832
Short name T862
Test name
Test status
Simulation time 808582609 ps
CPU time 14.65 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 226024 kb
Host smart-47a49223-321e-4c96-8bda-6b1214fb526d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464597832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.464597832
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1035225181
Short name T630
Test name
Test status
Simulation time 178243409 ps
CPU time 7.72 seconds
Started Aug 14 05:30:57 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 226012 kb
Host smart-a69d41bd-d694-4592-a77b-2d937f825494
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035225181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1035225181
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3516624704
Short name T42
Test name
Test status
Simulation time 614399943 ps
CPU time 12 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:31:08 PM PDT 24
Peak memory 224916 kb
Host smart-1482036d-cbe5-490f-b711-24e251e3ec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516624704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3516624704
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2406620231
Short name T92
Test name
Test status
Simulation time 126577684 ps
CPU time 2.05 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 217664 kb
Host smart-adce6e20-26c3-4322-80dd-176052f0b37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406620231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2406620231
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1218126398
Short name T288
Test name
Test status
Simulation time 328163556 ps
CPU time 24.39 seconds
Started Aug 14 05:30:57 PM PDT 24
Finished Aug 14 05:31:21 PM PDT 24
Peak memory 250924 kb
Host smart-3c46e256-13e4-46e7-a7b7-f222edb1f5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218126398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1218126398
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.4125625719
Short name T868
Test name
Test status
Simulation time 55356303 ps
CPU time 3.46 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 222500 kb
Host smart-eb0eccfd-5e8b-452b-b660-202db984dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125625719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4125625719
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1835518913
Short name T747
Test name
Test status
Simulation time 622562449 ps
CPU time 5.84 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 217948 kb
Host smart-2f1352b0-52e8-4c13-8aa0-0843a82735c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835518913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1835518913
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3538988398
Short name T147
Test name
Test status
Simulation time 2076173202 ps
CPU time 76.44 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 226232 kb
Host smart-91cf3e98-376f-4e0d-9530-d12f56f3eb95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3538988398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3538988398
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1900158792
Short name T372
Test name
Test status
Simulation time 15448427 ps
CPU time 0.9 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 211936 kb
Host smart-28619d4c-466e-4301-b959-0e47d2292590
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900158792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1900158792
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2187964508
Short name T778
Test name
Test status
Simulation time 79754228 ps
CPU time 0.87 seconds
Started Aug 14 05:30:58 PM PDT 24
Finished Aug 14 05:30:59 PM PDT 24
Peak memory 208692 kb
Host smart-61472f8a-78e2-48a3-8144-431d339dc387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187964508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2187964508
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.594662640
Short name T13
Test name
Test status
Simulation time 1899326025 ps
CPU time 14.92 seconds
Started Aug 14 05:30:54 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 218128 kb
Host smart-019f5044-802e-46de-a790-712309b2c528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594662640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.594662640
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.733023642
Short name T647
Test name
Test status
Simulation time 249534196 ps
CPU time 2.12 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:30:57 PM PDT 24
Peak memory 216936 kb
Host smart-d7b07f00-f84a-44e9-bc3a-3740e42b7cbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733023642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.733023642
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1388752133
Short name T567
Test name
Test status
Simulation time 190117969 ps
CPU time 2.42 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:30:57 PM PDT 24
Peak memory 222368 kb
Host smart-d19d33a9-7d9b-4bfe-9271-318e43345171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388752133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1388752133
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.979107200
Short name T437
Test name
Test status
Simulation time 1635551607 ps
CPU time 18.36 seconds
Started Aug 14 05:30:54 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 226176 kb
Host smart-f1dc6d4c-d793-405c-a450-be0f0c7c6460
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979107200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.979107200
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.443234253
Short name T797
Test name
Test status
Simulation time 262203772 ps
CPU time 10.71 seconds
Started Aug 14 05:30:51 PM PDT 24
Finished Aug 14 05:31:02 PM PDT 24
Peak memory 226024 kb
Host smart-b77d41af-2e6c-4ea3-90b6-3bf3b7f1aba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443234253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.443234253
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3693119753
Short name T380
Test name
Test status
Simulation time 353970876 ps
CPU time 8.52 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 226044 kb
Host smart-a3fed035-674b-4edc-9fed-31c75bb39575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693119753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3693119753
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3363946358
Short name T665
Test name
Test status
Simulation time 3889825913 ps
CPU time 16.13 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:10 PM PDT 24
Peak memory 226140 kb
Host smart-dc9eaf31-069c-424c-af0c-8c536d0f6d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363946358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3363946358
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2226014778
Short name T788
Test name
Test status
Simulation time 76974296 ps
CPU time 2.23 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 214352 kb
Host smart-b2517f60-4e4b-4c9c-96ce-5f573f6f87a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226014778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2226014778
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1255633066
Short name T219
Test name
Test status
Simulation time 323353646 ps
CPU time 22.44 seconds
Started Aug 14 05:30:54 PM PDT 24
Finished Aug 14 05:31:16 PM PDT 24
Peak memory 247204 kb
Host smart-f516f908-a005-4015-8f16-e1d3807436a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255633066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1255633066
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1548766766
Short name T496
Test name
Test status
Simulation time 120533543 ps
CPU time 6.89 seconds
Started Aug 14 05:30:57 PM PDT 24
Finished Aug 14 05:31:04 PM PDT 24
Peak memory 246880 kb
Host smart-5a64b4a4-0951-4963-9e8c-75260bc6cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548766766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1548766766
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.392960465
Short name T559
Test name
Test status
Simulation time 44506740686 ps
CPU time 87.81 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 255124 kb
Host smart-dbb40a44-184c-4e4b-b3dc-4479af551a68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392960465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.392960465
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3870466283
Short name T220
Test name
Test status
Simulation time 13462161 ps
CPU time 1.01 seconds
Started Aug 14 05:30:57 PM PDT 24
Finished Aug 14 05:30:58 PM PDT 24
Peak memory 211700 kb
Host smart-a85d07ea-a8f4-4fb9-804f-ad495d7aed44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870466283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3870466283
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.234518646
Short name T706
Test name
Test status
Simulation time 16663575 ps
CPU time 0.92 seconds
Started Aug 14 05:30:54 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 208904 kb
Host smart-fa188ca1-dba9-418e-bbec-830a364548bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234518646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.234518646
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2491322383
Short name T700
Test name
Test status
Simulation time 323591950 ps
CPU time 11.29 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:31:07 PM PDT 24
Peak memory 218308 kb
Host smart-db153cdc-1851-4b54-a26a-a968194842b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491322383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2491322383
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2110394114
Short name T529
Test name
Test status
Simulation time 1197141993 ps
CPU time 7.85 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 217448 kb
Host smart-6c2cc872-d2e8-46a0-af98-1365bc2e8eb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110394114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2110394114
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3246614570
Short name T654
Test name
Test status
Simulation time 37481459 ps
CPU time 2.48 seconds
Started Aug 14 05:30:57 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 222276 kb
Host smart-8be5f1cd-dd41-4f4d-b4a3-14fa6d0a1d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246614570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3246614570
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1605774619
Short name T57
Test name
Test status
Simulation time 204950500 ps
CPU time 8.16 seconds
Started Aug 14 05:30:54 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 225640 kb
Host smart-45ba1f71-0594-45fe-9b69-794af36847cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605774619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1605774619
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.392571843
Short name T710
Test name
Test status
Simulation time 370967104 ps
CPU time 10.39 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 226028 kb
Host smart-6306fa1e-81b3-405e-a56d-c1a19d10f14c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392571843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.392571843
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3895654617
Short name T509
Test name
Test status
Simulation time 914201787 ps
CPU time 6.9 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:30:59 PM PDT 24
Peak memory 218228 kb
Host smart-7116ca74-47b9-4fc3-998a-f71b8f816307
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895654617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3895654617
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1194820566
Short name T264
Test name
Test status
Simulation time 450117488 ps
CPU time 6.63 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 218356 kb
Host smart-c59c45c8-86bc-4345-bb8e-4ce88ba45f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194820566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1194820566
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.419433480
Short name T629
Test name
Test status
Simulation time 21133218 ps
CPU time 1.46 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:30:58 PM PDT 24
Peak memory 217728 kb
Host smart-e88c3fa9-cae8-495f-87a3-484548f4b8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419433480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.419433480
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3687296601
Short name T168
Test name
Test status
Simulation time 283799542 ps
CPU time 19.67 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 250976 kb
Host smart-e7f21da7-ad9d-47f9-b8f5-2253cd76252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687296601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3687296601
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1668363082
Short name T633
Test name
Test status
Simulation time 383052073 ps
CPU time 9.23 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 250840 kb
Host smart-53908984-87f7-4b63-9d7f-7ac7cfd2ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668363082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1668363082
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3824607232
Short name T557
Test name
Test status
Simulation time 2180274525 ps
CPU time 38.92 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 250876 kb
Host smart-0bec4975-160d-490b-a9ac-113d658804f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824607232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3824607232
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.733967014
Short name T612
Test name
Test status
Simulation time 15426044 ps
CPU time 0.89 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:30:57 PM PDT 24
Peak memory 211900 kb
Host smart-9a904c64-2301-4290-aad4-fd85e326e627
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733967014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.733967014
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.73480721
Short name T789
Test name
Test status
Simulation time 39687408 ps
CPU time 0.93 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 208880 kb
Host smart-6715707b-9892-441c-ba62-f3a2f63325e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73480721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.73480721
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.991011598
Short name T841
Test name
Test status
Simulation time 1364526504 ps
CPU time 12.03 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:07 PM PDT 24
Peak memory 218196 kb
Host smart-084d5b2d-7f01-45d1-a0ae-a87c87790740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991011598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.991011598
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3001817782
Short name T699
Test name
Test status
Simulation time 292036245 ps
CPU time 2.41 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:30:59 PM PDT 24
Peak memory 217120 kb
Host smart-b2ce91e2-f323-4413-bf5f-c469dca1e2e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001817782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3001817782
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.792600690
Short name T682
Test name
Test status
Simulation time 42399062 ps
CPU time 2.42 seconds
Started Aug 14 05:30:54 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 218208 kb
Host smart-e592d26a-d53e-4e7f-ae02-0b0b32d6d285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792600690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.792600690
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2770229987
Short name T526
Test name
Test status
Simulation time 720775468 ps
CPU time 8.79 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:31:04 PM PDT 24
Peak memory 225740 kb
Host smart-380da645-b37d-4c26-b62e-55607ed097e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770229987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2770229987
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.662276487
Short name T527
Test name
Test status
Simulation time 265166310 ps
CPU time 13.3 seconds
Started Aug 14 05:30:54 PM PDT 24
Finished Aug 14 05:31:08 PM PDT 24
Peak memory 225996 kb
Host smart-6d477875-5b45-4f2f-8be5-47111eb2ac6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662276487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.662276487
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3895693807
Short name T471
Test name
Test status
Simulation time 3184790166 ps
CPU time 12.3 seconds
Started Aug 14 05:30:57 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 226084 kb
Host smart-6ad90ff2-402b-49a3-bea6-75698bcda53f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895693807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3895693807
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3006200055
Short name T212
Test name
Test status
Simulation time 234009848 ps
CPU time 7.5 seconds
Started Aug 14 05:30:56 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 218396 kb
Host smart-836903ac-bc89-44a7-9d40-f1c5085412b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006200055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3006200055
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.153726263
Short name T373
Test name
Test status
Simulation time 209290750 ps
CPU time 3.53 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 217580 kb
Host smart-1ece4c14-9be7-40b7-8383-38c6f04649ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153726263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.153726263
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3414741073
Short name T521
Test name
Test status
Simulation time 2397342906 ps
CPU time 16.47 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 250968 kb
Host smart-cbb69ba3-0fed-4f73-b9a8-4f38f43ab27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414741073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3414741073
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1861051268
Short name T538
Test name
Test status
Simulation time 229912004 ps
CPU time 6.61 seconds
Started Aug 14 05:30:52 PM PDT 24
Finished Aug 14 05:30:59 PM PDT 24
Peak memory 250424 kb
Host smart-d3bd26bd-291b-40d0-8baf-5990dab372d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861051268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1861051268
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2993459708
Short name T513
Test name
Test status
Simulation time 5722461836 ps
CPU time 82.45 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:32:18 PM PDT 24
Peak memory 248108 kb
Host smart-642e321e-fbf4-4c1b-b362-dbff6c9dc908
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993459708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2993459708
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3423405189
Short name T114
Test name
Test status
Simulation time 5650577184 ps
CPU time 180.63 seconds
Started Aug 14 05:30:55 PM PDT 24
Finished Aug 14 05:33:56 PM PDT 24
Peak memory 273044 kb
Host smart-cd623a87-0372-4da9-a204-427a6b2ef266
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3423405189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3423405189
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2156515087
Short name T315
Test name
Test status
Simulation time 12300524 ps
CPU time 0.83 seconds
Started Aug 14 05:30:53 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 211992 kb
Host smart-70239806-685a-4efd-867f-fffd096381b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156515087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2156515087
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2783034231
Short name T87
Test name
Test status
Simulation time 21307482 ps
CPU time 0.9 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:10 PM PDT 24
Peak memory 208844 kb
Host smart-441d3994-cd0b-499c-b315-ef6c2a128d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783034231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2783034231
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2832591432
Short name T609
Test name
Test status
Simulation time 1697791858 ps
CPU time 18.42 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:31:20 PM PDT 24
Peak memory 226044 kb
Host smart-61322d1c-053d-4556-9040-7b8b6c42f7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832591432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2832591432
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.437559275
Short name T94
Test name
Test status
Simulation time 221444052 ps
CPU time 1.47 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:04 PM PDT 24
Peak memory 217028 kb
Host smart-94514dc7-8dff-4807-88a9-c1f09ede382d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437559275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.437559275
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3035044544
Short name T736
Test name
Test status
Simulation time 860781487 ps
CPU time 2.51 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:31:06 PM PDT 24
Peak memory 218276 kb
Host smart-662b07a1-9a34-4097-a1a7-d931a0783f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035044544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3035044544
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2987609358
Short name T398
Test name
Test status
Simulation time 229535166 ps
CPU time 6.97 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 226024 kb
Host smart-b4b8d487-d802-476a-b15f-68d32830569d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987609358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2987609358
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1149441824
Short name T602
Test name
Test status
Simulation time 271266413 ps
CPU time 8.94 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:14 PM PDT 24
Peak memory 225996 kb
Host smart-3a7bd9b4-4d3e-4cb1-b414-7b5de67a015e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149441824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1149441824
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1446932749
Short name T514
Test name
Test status
Simulation time 2163602933 ps
CPU time 12.41 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:18 PM PDT 24
Peak memory 226104 kb
Host smart-e4b7fb12-8cdf-4183-a8ce-1101bfbcfbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446932749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1446932749
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3979529344
Short name T724
Test name
Test status
Simulation time 33053809 ps
CPU time 2.21 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:08 PM PDT 24
Peak memory 214632 kb
Host smart-9de75b05-f368-4f00-8244-12778e43b267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979529344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3979529344
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2335718486
Short name T78
Test name
Test status
Simulation time 381026164 ps
CPU time 22.63 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 250696 kb
Host smart-5c7198f7-a454-47bb-8d0d-00348b2ef61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335718486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2335718486
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.732047812
Short name T249
Test name
Test status
Simulation time 319180937 ps
CPU time 4.3 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 222624 kb
Host smart-0255fbfb-efac-43d9-b1a7-437fb44ef474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732047812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.732047812
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1230149413
Short name T523
Test name
Test status
Simulation time 30191049891 ps
CPU time 104.78 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:32:46 PM PDT 24
Peak memory 275984 kb
Host smart-7ee0737a-e3ea-4264-a8fb-50757e47e1c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230149413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1230149413
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2114699877
Short name T740
Test name
Test status
Simulation time 12937820868 ps
CPU time 78.73 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:32:23 PM PDT 24
Peak memory 259404 kb
Host smart-6bf4c435-9318-4438-b67a-b87b76aca67d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2114699877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2114699877
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1251059753
Short name T712
Test name
Test status
Simulation time 25767189 ps
CPU time 0.9 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 211960 kb
Host smart-c1e99be2-9328-4d35-9281-65522b3b19f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251059753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1251059753
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3777981058
Short name T807
Test name
Test status
Simulation time 47510801 ps
CPU time 1.09 seconds
Started Aug 14 05:31:06 PM PDT 24
Finished Aug 14 05:31:07 PM PDT 24
Peak memory 208856 kb
Host smart-81eaa929-62e3-46fb-be03-0f749e1e4cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777981058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3777981058
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.956312159
Short name T371
Test name
Test status
Simulation time 1177796694 ps
CPU time 15.93 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:19 PM PDT 24
Peak memory 218304 kb
Host smart-b14c4506-6b09-4f48-accc-f6624cc0c8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956312159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.956312159
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.74798811
Short name T7
Test name
Test status
Simulation time 3762867712 ps
CPU time 5.05 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:14 PM PDT 24
Peak memory 217692 kb
Host smart-7711c8a1-91d2-4a54-8116-c5e5ddbaa32e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74798811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.74798811
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3336492984
Short name T227
Test name
Test status
Simulation time 23544149 ps
CPU time 2 seconds
Started Aug 14 05:31:01 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 218304 kb
Host smart-5aa4981c-924e-4119-a3ae-ae570565b549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336492984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3336492984
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1599542229
Short name T33
Test name
Test status
Simulation time 472607366 ps
CPU time 14.96 seconds
Started Aug 14 05:31:01 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 225968 kb
Host smart-2d057307-7954-4583-8d46-040ae610f9cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599542229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1599542229
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3898439242
Short name T656
Test name
Test status
Simulation time 1420912758 ps
CPU time 9.11 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 226008 kb
Host smart-12eedecd-78e9-477a-91be-c0cefad189ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898439242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3898439242
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.864890976
Short name T400
Test name
Test status
Simulation time 658977103 ps
CPU time 8.83 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 218248 kb
Host smart-d209b650-9bb5-4810-b710-e25ac78a65e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864890976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.864890976
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2815746317
Short name T38
Test name
Test status
Simulation time 391913828 ps
CPU time 14.72 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:18 PM PDT 24
Peak memory 226072 kb
Host smart-bc79ee96-ff0c-4d60-9105-ff92d1889f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815746317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2815746317
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4110830545
Short name T411
Test name
Test status
Simulation time 903108406 ps
CPU time 3.35 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 217604 kb
Host smart-41ac9503-9163-4694-8f19-19c8a7ebc07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110830545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4110830545
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1239569160
Short name T79
Test name
Test status
Simulation time 3105242133 ps
CPU time 24.22 seconds
Started Aug 14 05:31:07 PM PDT 24
Finished Aug 14 05:31:31 PM PDT 24
Peak memory 250888 kb
Host smart-707269e8-b519-4f16-8a5f-e543e5bc0604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239569160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1239569160
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.530704854
Short name T242
Test name
Test status
Simulation time 81125095 ps
CPU time 8.46 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:14 PM PDT 24
Peak memory 250692 kb
Host smart-c8cb7109-8ac1-48b8-8243-3a176c883524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530704854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.530704854
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3926281217
Short name T181
Test name
Test status
Simulation time 41845268880 ps
CPU time 339.5 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:36:45 PM PDT 24
Peak memory 283640 kb
Host smart-88a385c3-2e36-4391-898d-1e5ea31fcfe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926281217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3926281217
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.361032170
Short name T154
Test name
Test status
Simulation time 593373676 ps
CPU time 36.34 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:31:41 PM PDT 24
Peak memory 268360 kb
Host smart-befb5488-4f5b-45dd-9485-22fb0a3c38f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=361032170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.361032170
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2301633473
Short name T578
Test name
Test status
Simulation time 11169741 ps
CPU time 1.03 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:31:03 PM PDT 24
Peak memory 211880 kb
Host smart-d1ffa40f-f641-4320-84ba-3269b5527e0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301633473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2301633473
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.951316224
Short name T250
Test name
Test status
Simulation time 55368551 ps
CPU time 0.9 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:04 PM PDT 24
Peak memory 208900 kb
Host smart-a57a0fd1-5b27-47c8-acd6-af59a203833d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951316224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.951316224
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3474687269
Short name T405
Test name
Test status
Simulation time 395975335 ps
CPU time 11.66 seconds
Started Aug 14 05:31:16 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 218296 kb
Host smart-83546e9b-6e5c-43f3-b718-d3c32a284df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474687269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3474687269
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2562381393
Short name T183
Test name
Test status
Simulation time 2356627972 ps
CPU time 8.12 seconds
Started Aug 14 05:31:01 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 217476 kb
Host smart-9271a7bc-e1e1-4ace-a8cf-678d69357817
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562381393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2562381393
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3155017990
Short name T54
Test name
Test status
Simulation time 44967878 ps
CPU time 1.83 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:07 PM PDT 24
Peak memory 218256 kb
Host smart-82509156-b98e-4da5-adce-c8c4bfa11248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155017990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3155017990
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2541071451
Short name T247
Test name
Test status
Simulation time 439393516 ps
CPU time 12.1 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 226236 kb
Host smart-9f03299f-ecb7-416b-967c-c250db021c40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541071451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2541071451
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1237618993
Short name T625
Test name
Test status
Simulation time 1016468784 ps
CPU time 9.36 seconds
Started Aug 14 05:31:01 PM PDT 24
Finished Aug 14 05:31:10 PM PDT 24
Peak memory 225996 kb
Host smart-0a603cb2-39d2-448d-8229-f771c0747b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237618993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1237618993
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.516839397
Short name T56
Test name
Test status
Simulation time 267528078 ps
CPU time 7.49 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 218248 kb
Host smart-1fcdc9c9-e989-43eb-afe6-1e6b3611cc8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516839397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.516839397
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1184276423
Short name T276
Test name
Test status
Simulation time 242662694 ps
CPU time 9.93 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:31:14 PM PDT 24
Peak memory 225232 kb
Host smart-319e68ef-4be9-4d0b-8223-b395d5a6cfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184276423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1184276423
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1396565424
Short name T11
Test name
Test status
Simulation time 94969918 ps
CPU time 2.59 seconds
Started Aug 14 05:31:06 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 214216 kb
Host smart-d5934048-62fc-42fd-9ed7-027dbc95b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396565424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1396565424
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.979631119
Short name T388
Test name
Test status
Simulation time 211214055 ps
CPU time 25.47 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 250956 kb
Host smart-5ea60e1c-b137-4c90-a9e6-b7a3aa66fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979631119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.979631119
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.691321714
Short name T544
Test name
Test status
Simulation time 262909230 ps
CPU time 8.52 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 250912 kb
Host smart-3e6e7275-cee8-4de0-abe6-4a3f26630eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691321714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.691321714
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3480172165
Short name T839
Test name
Test status
Simulation time 19694463691 ps
CPU time 196.52 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:34:20 PM PDT 24
Peak memory 316436 kb
Host smart-fff1c027-1d3e-46a0-83a0-335609c63272
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480172165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3480172165
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2350800021
Short name T679
Test name
Test status
Simulation time 41081187 ps
CPU time 0.98 seconds
Started Aug 14 05:31:06 PM PDT 24
Finished Aug 14 05:31:07 PM PDT 24
Peak memory 211844 kb
Host smart-a048b9e4-821d-401b-9bc5-4cd7d864dddb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350800021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2350800021
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2718627534
Short name T235
Test name
Test status
Simulation time 55852284 ps
CPU time 1 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:40 PM PDT 24
Peak memory 208896 kb
Host smart-0fad5ab4-097e-408c-8206-04760fea58ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718627534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2718627534
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.119252054
Short name T480
Test name
Test status
Simulation time 463531044 ps
CPU time 12.39 seconds
Started Aug 14 05:29:37 PM PDT 24
Finished Aug 14 05:29:50 PM PDT 24
Peak memory 226000 kb
Host smart-a6a97fc3-8ddc-41bd-aaac-c0291768f070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119252054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.119252054
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2203963250
Short name T367
Test name
Test status
Simulation time 236988890 ps
CPU time 1.99 seconds
Started Aug 14 05:29:36 PM PDT 24
Finished Aug 14 05:29:38 PM PDT 24
Peak memory 217112 kb
Host smart-0680e0b2-ed2f-4df0-9c6c-32353aaa5507
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203963250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2203963250
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3171821608
Short name T565
Test name
Test status
Simulation time 6703603111 ps
CPU time 41.8 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 218816 kb
Host smart-741d8af5-edf4-49f0-9360-edf9241eb525
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171821608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3171821608
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2291454158
Short name T838
Test name
Test status
Simulation time 642780175 ps
CPU time 5.12 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:29:45 PM PDT 24
Peak memory 217700 kb
Host smart-9332cfc7-906a-47f2-b74e-b71b65d975e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291454158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
291454158
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.599994365
Short name T572
Test name
Test status
Simulation time 490176987 ps
CPU time 7.43 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:47 PM PDT 24
Peak memory 218236 kb
Host smart-43f15e1a-6179-44cd-a125-1ea5fa6f1b47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599994365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.599994365
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1825959730
Short name T403
Test name
Test status
Simulation time 746506818 ps
CPU time 21.47 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 217532 kb
Host smart-3d921469-fb16-40cc-a35e-555414a179e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825959730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1825959730
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2867892791
Short name T101
Test name
Test status
Simulation time 560865179 ps
CPU time 7.91 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:47 PM PDT 24
Peak memory 217580 kb
Host smart-b88f6820-c835-4b14-a5e3-b1b4818356d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867892791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2867892791
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3846246979
Short name T739
Test name
Test status
Simulation time 3221856484 ps
CPU time 45.93 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 275548 kb
Host smart-af37e9f4-957a-44f8-b279-b7e98267e221
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846246979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3846246979
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3081223376
Short name T678
Test name
Test status
Simulation time 946147040 ps
CPU time 23.14 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:30:02 PM PDT 24
Peak memory 249452 kb
Host smart-350f2bab-c1f8-44e9-95d6-5676f34b90ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081223376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3081223376
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2440668385
Short name T240
Test name
Test status
Simulation time 124248120 ps
CPU time 3.49 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:42 PM PDT 24
Peak memory 218252 kb
Host smart-0a3708fe-367a-484b-9d94-b93a86686cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440668385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2440668385
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3637047872
Short name T614
Test name
Test status
Simulation time 441057751 ps
CPU time 6.4 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:46 PM PDT 24
Peak memory 217640 kb
Host smart-57ff0859-5af0-441d-8275-0b0437680748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637047872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3637047872
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1294162758
Short name T99
Test name
Test status
Simulation time 253154747 ps
CPU time 24.22 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 268988 kb
Host smart-a37948bb-e9fe-4a8b-9047-5ae66ea5adb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294162758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1294162758
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2763400382
Short name T585
Test name
Test status
Simulation time 2795275248 ps
CPU time 16.27 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:55 PM PDT 24
Peak memory 226156 kb
Host smart-1e0a904e-73f9-4f78-b0be-b16b912aaf12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763400382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2763400382
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3409030425
Short name T770
Test name
Test status
Simulation time 928047643 ps
CPU time 11.39 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:49 PM PDT 24
Peak memory 226036 kb
Host smart-e78325ec-aecc-4bb3-bc14-80ba3e75116f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409030425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3409030425
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3203519612
Short name T865
Test name
Test status
Simulation time 218265411 ps
CPU time 6.74 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:45 PM PDT 24
Peak memory 218248 kb
Host smart-78c1a4fe-a91f-4943-b7bb-5124869dd189
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203519612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
203519612
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1993241726
Short name T69
Test name
Test status
Simulation time 45098041 ps
CPU time 1.32 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:40 PM PDT 24
Peak memory 213636 kb
Host smart-a805d63f-f059-48f8-9a47-6b6b2822c576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993241726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1993241726
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3614967116
Short name T780
Test name
Test status
Simulation time 474312006 ps
CPU time 30.45 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 250912 kb
Host smart-5e6722bb-1f56-407f-8bd4-07a66ace1d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614967116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3614967116
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.646327201
Short name T623
Test name
Test status
Simulation time 325627701 ps
CPU time 8.45 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:48 PM PDT 24
Peak memory 250888 kb
Host smart-09164b5f-8f59-4076-b947-3704bc1b54f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646327201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.646327201
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3351452556
Short name T774
Test name
Test status
Simulation time 25388141212 ps
CPU time 81.88 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 278616 kb
Host smart-a994715a-f85c-4798-b41b-8cfb97dacbed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351452556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3351452556
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1207671655
Short name T238
Test name
Test status
Simulation time 15466601 ps
CPU time 1.02 seconds
Started Aug 14 05:29:37 PM PDT 24
Finished Aug 14 05:29:38 PM PDT 24
Peak memory 217792 kb
Host smart-fdcc55b6-be94-40dc-b263-25bf0afeb5c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207671655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1207671655
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3928151628
Short name T359
Test name
Test status
Simulation time 18134509 ps
CPU time 1.17 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:04 PM PDT 24
Peak memory 208924 kb
Host smart-f9d5a781-1d58-49c0-88cd-0d08d69f4079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928151628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3928151628
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1941436198
Short name T2
Test name
Test status
Simulation time 1753549946 ps
CPU time 13.26 seconds
Started Aug 14 05:31:01 PM PDT 24
Finished Aug 14 05:31:15 PM PDT 24
Peak memory 218300 kb
Host smart-466f45d0-8a9f-44db-a8e8-e0b53125c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941436198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1941436198
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2545104437
Short name T749
Test name
Test status
Simulation time 399252422 ps
CPU time 10.85 seconds
Started Aug 14 05:31:01 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 217428 kb
Host smart-56cb80f7-1ef5-4bfb-b65c-b6b403322dca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545104437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2545104437
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1881101442
Short name T402
Test name
Test status
Simulation time 43817512 ps
CPU time 1.91 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:31:06 PM PDT 24
Peak memory 218216 kb
Host smart-9a6d9b03-6c0d-49fb-afb6-02816a6ee7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881101442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1881101442
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3618744244
Short name T616
Test name
Test status
Simulation time 565617390 ps
CPU time 16.76 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:26 PM PDT 24
Peak memory 226104 kb
Host smart-842c92e9-74ed-4009-8dc7-9a77ba7a73a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618744244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3618744244
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.20394609
Short name T277
Test name
Test status
Simulation time 690171385 ps
CPU time 11.01 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 226032 kb
Host smart-0f2ae916-14c7-4436-83e1-b95edb8f0ef5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20394609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_dig
est.20394609
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3121505059
Short name T313
Test name
Test status
Simulation time 909192258 ps
CPU time 6.13 seconds
Started Aug 14 05:31:03 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 218232 kb
Host smart-af1f1dd2-fa7b-4419-a777-5ea47f4e6a44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121505059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3121505059
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.28579933
Short name T826
Test name
Test status
Simulation time 300299202 ps
CPU time 8.16 seconds
Started Aug 14 05:31:06 PM PDT 24
Finished Aug 14 05:31:14 PM PDT 24
Peak memory 218360 kb
Host smart-19924e1c-6237-44b2-a013-1b3cd56700a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28579933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.28579933
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2216985641
Short name T289
Test name
Test status
Simulation time 51843473 ps
CPU time 2.82 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:08 PM PDT 24
Peak memory 217740 kb
Host smart-f64e38e3-ad01-4cab-8452-9593b3506c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216985641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2216985641
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2445745327
Short name T477
Test name
Test status
Simulation time 388514377 ps
CPU time 31.72 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 250892 kb
Host smart-6d1849a5-df26-4fb3-9367-833cbc3af1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445745327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2445745327
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.473901237
Short name T352
Test name
Test status
Simulation time 127319985 ps
CPU time 6.76 seconds
Started Aug 14 05:31:05 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 250912 kb
Host smart-e0676ed6-a2b8-4fe2-bcbd-378490a738c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473901237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.473901237
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1904415001
Short name T775
Test name
Test status
Simulation time 18544069111 ps
CPU time 148.34 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:33:31 PM PDT 24
Peak memory 273916 kb
Host smart-dbbf108e-ab84-4b0b-8723-0cf8bbb8c23b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1904415001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1904415001
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3571583990
Short name T16
Test name
Test status
Simulation time 46758185 ps
CPU time 1.02 seconds
Started Aug 14 05:31:04 PM PDT 24
Finished Aug 14 05:31:05 PM PDT 24
Peak memory 211972 kb
Host smart-a91c925a-8a1c-41c9-b5d5-0ddf48304610
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571583990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3571583990
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3693213669
Short name T459
Test name
Test status
Simulation time 27437565 ps
CPU time 1.32 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 208504 kb
Host smart-0c35239d-cfff-4f35-b38a-b1ffa4f6ca1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693213669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3693213669
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.454454839
Short name T345
Test name
Test status
Simulation time 2986366568 ps
CPU time 16.47 seconds
Started Aug 14 05:31:23 PM PDT 24
Finished Aug 14 05:31:39 PM PDT 24
Peak memory 218988 kb
Host smart-f61580e9-d6f7-479e-83a9-2d3d3f54e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454454839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.454454839
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2370891588
Short name T820
Test name
Test status
Simulation time 628192577 ps
CPU time 15.46 seconds
Started Aug 14 05:31:12 PM PDT 24
Finished Aug 14 05:31:27 PM PDT 24
Peak memory 217656 kb
Host smart-b79fcf08-a319-4989-b907-fef224c0da99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370891588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2370891588
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.4012180812
Short name T531
Test name
Test status
Simulation time 256429730 ps
CPU time 2.71 seconds
Started Aug 14 05:31:14 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 222420 kb
Host smart-33345de5-62ca-438d-bdce-715412193f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012180812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.4012180812
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.280921383
Short name T686
Test name
Test status
Simulation time 304462093 ps
CPU time 15.03 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:31:43 PM PDT 24
Peak memory 218304 kb
Host smart-8a1a0d73-1f90-4283-9ae4-35ea5a4d3bc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280921383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.280921383
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1174095529
Short name T353
Test name
Test status
Simulation time 1757888408 ps
CPU time 10.43 seconds
Started Aug 14 05:31:14 PM PDT 24
Finished Aug 14 05:31:25 PM PDT 24
Peak memory 226060 kb
Host smart-eb2e9863-8d8a-4143-bb6d-6184f629d7ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174095529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1174095529
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4052403944
Short name T342
Test name
Test status
Simulation time 1826095028 ps
CPU time 10.69 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:37 PM PDT 24
Peak memory 217508 kb
Host smart-10c9259b-a012-47d3-87bd-e38930b54d14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052403944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4052403944
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3839457329
Short name T518
Test name
Test status
Simulation time 210113370 ps
CPU time 7.93 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:31:35 PM PDT 24
Peak memory 218368 kb
Host smart-4d924af7-b254-4aa3-96ab-34131cce5e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839457329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3839457329
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1682880631
Short name T574
Test name
Test status
Simulation time 75216263 ps
CPU time 2.61 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 217660 kb
Host smart-a2c6b7e4-1890-450f-a407-2ad9a897ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682880631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1682880631
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3292707629
Short name T683
Test name
Test status
Simulation time 163968114 ps
CPU time 21.42 seconds
Started Aug 14 05:31:02 PM PDT 24
Finished Aug 14 05:31:24 PM PDT 24
Peak memory 250960 kb
Host smart-f1330408-3f0a-40f5-892d-a0bad8bcf149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292707629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3292707629
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3229258450
Short name T719
Test name
Test status
Simulation time 343224114 ps
CPU time 3.29 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:29 PM PDT 24
Peak memory 226080 kb
Host smart-18a5be88-3bfc-4ed8-8e01-3caa6a18b5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229258450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3229258450
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.173104547
Short name T828
Test name
Test status
Simulation time 2283806712 ps
CPU time 36.59 seconds
Started Aug 14 05:31:22 PM PDT 24
Finished Aug 14 05:31:59 PM PDT 24
Peak memory 250968 kb
Host smart-19522edc-760d-47be-a072-3dd40c4a6d79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173104547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.173104547
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2307781414
Short name T217
Test name
Test status
Simulation time 38908554 ps
CPU time 0.91 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:10 PM PDT 24
Peak memory 211856 kb
Host smart-9dddd26d-99e5-47f0-8feb-c4e1e9232a58
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307781414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2307781414
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1692293834
Short name T375
Test name
Test status
Simulation time 145436733 ps
CPU time 1.02 seconds
Started Aug 14 05:31:16 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 208920 kb
Host smart-43d15c07-5946-44ab-9e20-6da4d07063fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692293834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1692293834
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3314619559
Short name T51
Test name
Test status
Simulation time 539760351 ps
CPU time 16.3 seconds
Started Aug 14 05:31:16 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 226080 kb
Host smart-4bfeeb2a-a865-4c3a-8d9d-060980768ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314619559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3314619559
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3966106439
Short name T29
Test name
Test status
Simulation time 1799906059 ps
CPU time 5.75 seconds
Started Aug 14 05:31:23 PM PDT 24
Finished Aug 14 05:31:29 PM PDT 24
Peak memory 217156 kb
Host smart-770272ec-e5fc-47ff-87e1-c4ac24414b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966106439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3966106439
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.43243539
Short name T304
Test name
Test status
Simulation time 86737919 ps
CPU time 1.7 seconds
Started Aug 14 05:31:11 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 218292 kb
Host smart-a9bbf595-503b-4f82-981e-b7c56d7a41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43243539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.43243539
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2713208883
Short name T845
Test name
Test status
Simulation time 245341053 ps
CPU time 10.05 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:23 PM PDT 24
Peak memory 218948 kb
Host smart-c9cd7a97-18c8-4a7b-bb2b-6ce2b103501a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713208883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2713208883
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3459531640
Short name T349
Test name
Test status
Simulation time 232289946 ps
CPU time 11.87 seconds
Started Aug 14 05:31:23 PM PDT 24
Finished Aug 14 05:31:35 PM PDT 24
Peak memory 225956 kb
Host smart-a60c292f-f11c-4251-844e-d3f4a81a807a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459531640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3459531640
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.306767567
Short name T273
Test name
Test status
Simulation time 225662439 ps
CPU time 8.87 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:18 PM PDT 24
Peak memory 218232 kb
Host smart-1e1a9fd8-2d50-4979-9861-6108c394d731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306767567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.306767567
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3709484367
Short name T781
Test name
Test status
Simulation time 303400957 ps
CPU time 10.64 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:31:37 PM PDT 24
Peak memory 225168 kb
Host smart-662e55aa-9843-4499-935b-8a318a2bfe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709484367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3709484367
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1611218051
Short name T74
Test name
Test status
Simulation time 16572289 ps
CPU time 1.44 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 213680 kb
Host smart-e5303c4d-50a6-4919-880f-2691f9a66512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611218051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1611218051
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3927014679
Short name T642
Test name
Test status
Simulation time 932503024 ps
CPU time 31.13 seconds
Started Aug 14 05:31:28 PM PDT 24
Finished Aug 14 05:31:59 PM PDT 24
Peak memory 250912 kb
Host smart-3843aad9-11d5-459c-92df-2de153a169fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927014679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3927014679
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2673411823
Short name T305
Test name
Test status
Simulation time 147857819 ps
CPU time 8.57 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:21 PM PDT 24
Peak memory 250832 kb
Host smart-fa3e677a-770d-4dcc-b645-69702e02a3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673411823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2673411823
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2637293832
Short name T165
Test name
Test status
Simulation time 20008918024 ps
CPU time 115.99 seconds
Started Aug 14 05:31:20 PM PDT 24
Finished Aug 14 05:33:16 PM PDT 24
Peak memory 279432 kb
Host smart-c95550b2-24a2-41fb-9ae2-c632ccd44a79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2637293832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2637293832
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3634053013
Short name T178
Test name
Test status
Simulation time 21743032 ps
CPU time 0.85 seconds
Started Aug 14 05:31:09 PM PDT 24
Finished Aug 14 05:31:10 PM PDT 24
Peak memory 211904 kb
Host smart-f1204895-4bc4-4a15-862c-917abb564599
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634053013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3634053013
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.4180908998
Short name T763
Test name
Test status
Simulation time 31177650 ps
CPU time 0.91 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:14 PM PDT 24
Peak memory 208892 kb
Host smart-47f670cd-bbfd-417b-8454-36b0214116e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180908998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.4180908998
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3490595856
Short name T390
Test name
Test status
Simulation time 492498132 ps
CPU time 17.75 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:31:42 PM PDT 24
Peak memory 226092 kb
Host smart-e14e5af1-f4c8-4b8f-b81c-c110561bc984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490595856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3490595856
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.684690733
Short name T6
Test name
Test status
Simulation time 891262216 ps
CPU time 4.48 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:31 PM PDT 24
Peak memory 217116 kb
Host smart-ce2ec701-3585-4631-bc32-1bd08149b991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684690733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.684690733
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1124146481
Short name T306
Test name
Test status
Simulation time 129484732 ps
CPU time 1.86 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 217724 kb
Host smart-411182ea-2144-4855-ac1c-7a7c894fa3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124146481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1124146481
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1740195845
Short name T649
Test name
Test status
Simulation time 405969102 ps
CPU time 11.3 seconds
Started Aug 14 05:31:12 PM PDT 24
Finished Aug 14 05:31:24 PM PDT 24
Peak memory 226056 kb
Host smart-eafd8dd6-4abb-4178-9cab-8c5fd3132552
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740195845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1740195845
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.525780830
Short name T48
Test name
Test status
Simulation time 944754843 ps
CPU time 12.06 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 226032 kb
Host smart-e32c02bf-a042-40d3-9146-bb8adcd1a6d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525780830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.525780830
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1316385
Short name T536
Test name
Test status
Simulation time 848306808 ps
CPU time 5.87 seconds
Started Aug 14 05:31:11 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 218232 kb
Host smart-8a3ef6cf-48e9-463b-92dc-e339bf08bea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.1316385
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2762946663
Short name T41
Test name
Test status
Simulation time 719184642 ps
CPU time 8.85 seconds
Started Aug 14 05:31:12 PM PDT 24
Finished Aug 14 05:31:21 PM PDT 24
Peak memory 225660 kb
Host smart-2672ce40-cc0f-4a34-908e-30f90644880c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762946663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2762946663
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4288189494
Short name T859
Test name
Test status
Simulation time 37953303 ps
CPU time 2.72 seconds
Started Aug 14 05:31:12 PM PDT 24
Finished Aug 14 05:31:15 PM PDT 24
Peak memory 214180 kb
Host smart-092ca36d-f3a0-414a-8922-745ff397680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288189494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4288189494
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3647255629
Short name T409
Test name
Test status
Simulation time 1177321743 ps
CPU time 40.88 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 247112 kb
Host smart-1c6205ed-47c6-487a-86a8-06ea4e7a130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647255629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3647255629
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1413883662
Short name T515
Test name
Test status
Simulation time 183457786 ps
CPU time 8.76 seconds
Started Aug 14 05:31:22 PM PDT 24
Finished Aug 14 05:31:31 PM PDT 24
Peak memory 250932 kb
Host smart-3b905c79-020b-4c88-922d-51440db3edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413883662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1413883662
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1445856899
Short name T555
Test name
Test status
Simulation time 1372864826 ps
CPU time 53.57 seconds
Started Aug 14 05:31:12 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 267316 kb
Host smart-71977f89-a3d3-4a69-8329-a2ea7f8beee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445856899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1445856899
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1008497166
Short name T344
Test name
Test status
Simulation time 113825105 ps
CPU time 0.97 seconds
Started Aug 14 05:31:11 PM PDT 24
Finished Aug 14 05:31:12 PM PDT 24
Peak memory 211864 kb
Host smart-cd567ccc-e7c2-4c93-9181-854d25849b5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008497166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1008497166
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3263852264
Short name T244
Test name
Test status
Simulation time 19952302 ps
CPU time 0.89 seconds
Started Aug 14 05:31:28 PM PDT 24
Finished Aug 14 05:31:29 PM PDT 24
Peak memory 208880 kb
Host smart-43dd8ba8-1012-4a93-b0fa-b37364bee0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263852264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3263852264
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3684246156
Short name T283
Test name
Test status
Simulation time 306495606 ps
CPU time 9.87 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:36 PM PDT 24
Peak memory 226088 kb
Host smart-91339141-474a-40b5-9a29-9a716ead068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684246156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3684246156
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.552398632
Short name T825
Test name
Test status
Simulation time 1196793178 ps
CPU time 14.58 seconds
Started Aug 14 05:31:32 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 217004 kb
Host smart-b8a3e15c-37a3-4619-a37a-f6bd379f7b59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552398632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.552398632
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.4185568290
Short name T512
Test name
Test status
Simulation time 70544668 ps
CPU time 2.74 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:31:30 PM PDT 24
Peak memory 218284 kb
Host smart-d925e073-aa2a-43b6-ac42-9c6e789a2df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185568290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.4185568290
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3390243116
Short name T329
Test name
Test status
Simulation time 417821802 ps
CPU time 12.79 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:31:37 PM PDT 24
Peak memory 218956 kb
Host smart-3b362442-9c04-453b-9a96-c82d63d934aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390243116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3390243116
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.893820541
Short name T811
Test name
Test status
Simulation time 5669878152 ps
CPU time 13.44 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:27 PM PDT 24
Peak memory 226068 kb
Host smart-aa88228e-e5cf-4275-9cbd-6ac412d238de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893820541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.893820541
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2019059208
Short name T860
Test name
Test status
Simulation time 456597714 ps
CPU time 11.97 seconds
Started Aug 14 05:31:32 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 218188 kb
Host smart-a200afb8-2eef-42e6-826c-3c0d34ed1955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019059208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2019059208
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3030613421
Short name T716
Test name
Test status
Simulation time 261568972 ps
CPU time 12.71 seconds
Started Aug 14 05:31:16 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 218356 kb
Host smart-025e573b-dd5b-485c-91cd-13d1901f1204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030613421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3030613421
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1536384871
Short name T524
Test name
Test status
Simulation time 58369687 ps
CPU time 1.11 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:14 PM PDT 24
Peak memory 212360 kb
Host smart-9dbce3b6-1b8c-419b-9c6e-30bb64e2c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536384871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1536384871
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.322369055
Short name T511
Test name
Test status
Simulation time 198981124 ps
CPU time 18.75 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:50 PM PDT 24
Peak memory 245200 kb
Host smart-be9b9ef6-2f7b-43bc-acf2-19a080018708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322369055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.322369055
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3306907655
Short name T218
Test name
Test status
Simulation time 105312189 ps
CPU time 8.02 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:21 PM PDT 24
Peak memory 242704 kb
Host smart-3247d6eb-1c9d-4c55-b95e-9f67373d6333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306907655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3306907655
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1493760923
Short name T853
Test name
Test status
Simulation time 2547391261 ps
CPU time 90.89 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:32:55 PM PDT 24
Peak memory 267496 kb
Host smart-7f856e2f-770d-4948-94aa-945746480e5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493760923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1493760923
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2255634266
Short name T299
Test name
Test status
Simulation time 7846495305 ps
CPU time 86.4 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:32:39 PM PDT 24
Peak memory 277112 kb
Host smart-0ade8b6e-44ea-43c7-bee2-7651255d8f4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2255634266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2255634266
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3841612742
Short name T784
Test name
Test status
Simulation time 33910468 ps
CPU time 1.08 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:33 PM PDT 24
Peak memory 217844 kb
Host smart-40318e73-ee13-47cd-8ba3-9060f48c3d5f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841612742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3841612742
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2166529541
Short name T159
Test name
Test status
Simulation time 13333101 ps
CPU time 0.86 seconds
Started Aug 14 05:31:28 PM PDT 24
Finished Aug 14 05:31:29 PM PDT 24
Peak memory 208684 kb
Host smart-96586440-a85f-4cad-b040-e0166115ba61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166529541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2166529541
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.890144682
Short name T322
Test name
Test status
Simulation time 2543076111 ps
CPU time 16.38 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:30 PM PDT 24
Peak memory 219116 kb
Host smart-a8b3e70a-7302-4d96-911c-d2d65b60e3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890144682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.890144682
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3645847836
Short name T422
Test name
Test status
Simulation time 299294269 ps
CPU time 3.14 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:30 PM PDT 24
Peak memory 217652 kb
Host smart-4405d4e1-94cf-4842-a605-14a9d89bf399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645847836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3645847836
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.530754975
Short name T300
Test name
Test status
Simulation time 329761101 ps
CPU time 4.67 seconds
Started Aug 14 05:31:21 PM PDT 24
Finished Aug 14 05:31:26 PM PDT 24
Peak memory 218288 kb
Host smart-97e93a4b-4163-4c1b-87bf-fb34e6c03381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530754975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.530754975
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2445449452
Short name T286
Test name
Test status
Simulation time 3054719601 ps
CPU time 12.2 seconds
Started Aug 14 05:31:16 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 226148 kb
Host smart-e7c4f28d-3103-4ed9-8a8c-9e1e309a7c6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445449452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2445449452
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1413112648
Short name T604
Test name
Test status
Simulation time 467621850 ps
CPU time 11.98 seconds
Started Aug 14 05:31:15 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 226016 kb
Host smart-447f29b3-8952-402c-bfb0-2f99c3bd1007
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413112648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1413112648
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3227990899
Short name T772
Test name
Test status
Simulation time 817353335 ps
CPU time 10.6 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:41 PM PDT 24
Peak memory 218152 kb
Host smart-03163d5b-a610-4b50-8887-462612ceef44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227990899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3227990899
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3190805338
Short name T39
Test name
Test status
Simulation time 727851264 ps
CPU time 13.35 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:27 PM PDT 24
Peak memory 218364 kb
Host smart-322f9112-b06d-4489-b419-b77d5a6d307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190805338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3190805338
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4234077616
Short name T251
Test name
Test status
Simulation time 160221203 ps
CPU time 1.87 seconds
Started Aug 14 05:31:37 PM PDT 24
Finished Aug 14 05:31:38 PM PDT 24
Peak memory 213916 kb
Host smart-6929b348-976a-4729-9a78-9186383cd007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234077616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4234077616
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3050170870
Short name T748
Test name
Test status
Simulation time 844001738 ps
CPU time 19.39 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 250984 kb
Host smart-87534a19-1b00-43d6-9a29-e396d6d80890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050170870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3050170870
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.260870143
Short name T660
Test name
Test status
Simulation time 411192829 ps
CPU time 8.7 seconds
Started Aug 14 05:31:13 PM PDT 24
Finished Aug 14 05:31:22 PM PDT 24
Peak memory 243664 kb
Host smart-f1f3c835-6a74-4e42-82ef-f64a589b1526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260870143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.260870143
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2549320218
Short name T816
Test name
Test status
Simulation time 15880843 ps
CPU time 0.89 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:27 PM PDT 24
Peak memory 211932 kb
Host smart-dc00ee58-0071-45b7-ada7-4e8e56b3e324
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549320218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2549320218
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2000020639
Short name T396
Test name
Test status
Simulation time 44339148 ps
CPU time 0.93 seconds
Started Aug 14 05:31:23 PM PDT 24
Finished Aug 14 05:31:24 PM PDT 24
Peak memory 208900 kb
Host smart-567c3433-dcf6-4536-9b1d-b6ad4e274109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000020639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2000020639
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.70014511
Short name T641
Test name
Test status
Simulation time 367977356 ps
CPU time 14.1 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:39 PM PDT 24
Peak memory 226068 kb
Host smart-93a84827-03c5-4470-aa49-ccd181398b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70014511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.70014511
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.4104690700
Short name T357
Test name
Test status
Simulation time 88518120 ps
CPU time 1.87 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 216924 kb
Host smart-c0c3b868-f10d-463b-9b29-0939c0fe8f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104690700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.4104690700
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2913904780
Short name T151
Test name
Test status
Simulation time 102425769 ps
CPU time 3.02 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:33 PM PDT 24
Peak memory 222504 kb
Host smart-b58e7626-ecda-4cbc-b014-bf193d0edeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913904780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2913904780
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1029094434
Short name T737
Test name
Test status
Simulation time 355949529 ps
CPU time 14.44 seconds
Started Aug 14 05:31:34 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 226076 kb
Host smart-ce793c5a-acb0-4134-9844-817b56a91eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029094434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1029094434
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1146117727
Short name T275
Test name
Test status
Simulation time 221125846 ps
CPU time 9.71 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:41 PM PDT 24
Peak memory 226024 kb
Host smart-c79595ad-1bd3-469c-bc13-4b67307be288
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146117727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1146117727
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2039425575
Short name T297
Test name
Test status
Simulation time 320126817 ps
CPU time 13.02 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:38 PM PDT 24
Peak memory 225992 kb
Host smart-92e8bcd6-b68e-4943-a5f2-1fc2ddba762b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039425575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2039425575
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2432729671
Short name T673
Test name
Test status
Simulation time 263086965 ps
CPU time 10.53 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:31:35 PM PDT 24
Peak memory 218328 kb
Host smart-ccddb459-9a6a-4274-8ad7-965bcbcf8650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432729671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2432729671
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1463676800
Short name T617
Test name
Test status
Simulation time 73259311 ps
CPU time 3.09 seconds
Started Aug 14 05:31:14 PM PDT 24
Finished Aug 14 05:31:17 PM PDT 24
Peak memory 214956 kb
Host smart-04d7ae46-2cb5-4bc1-b795-9a2a80e359dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463676800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1463676800
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3500412197
Short name T812
Test name
Test status
Simulation time 326653851 ps
CPU time 27.57 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 250988 kb
Host smart-5e9aed37-20a1-4f24-8c2f-e1b3a58678fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500412197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3500412197
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3559786435
Short name T537
Test name
Test status
Simulation time 239330924 ps
CPU time 7.02 seconds
Started Aug 14 05:31:33 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 250392 kb
Host smart-4677fa76-98cc-4645-8b69-99ea0c9c4da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559786435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3559786435
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1606601869
Short name T82
Test name
Test status
Simulation time 3884569642 ps
CPU time 45.32 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 251088 kb
Host smart-62977d53-b15b-4f57-9678-4615c5d04b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1606601869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1606601869
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3697114474
Short name T163
Test name
Test status
Simulation time 21279445 ps
CPU time 0.84 seconds
Started Aug 14 05:31:33 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 211912 kb
Host smart-62950872-d11f-40fe-b854-41181105928a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697114474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3697114474
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3101081483
Short name T230
Test name
Test status
Simulation time 31270491 ps
CPU time 1.08 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:31:26 PM PDT 24
Peak memory 208972 kb
Host smart-e286064c-f557-456f-8058-5c90b1e348f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101081483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3101081483
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1311956639
Short name T790
Test name
Test status
Simulation time 682594921 ps
CPU time 2.32 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:27 PM PDT 24
Peak memory 217032 kb
Host smart-a43a6895-1eb6-4f77-be40-fba47675a401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311956639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1311956639
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.4239659750
Short name T295
Test name
Test status
Simulation time 1281613316 ps
CPU time 11.03 seconds
Started Aug 14 05:31:32 PM PDT 24
Finished Aug 14 05:31:43 PM PDT 24
Peak memory 226096 kb
Host smart-069687f2-d09b-4c8e-89c2-d98609a9bdce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239659750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.4239659750
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2597971076
Short name T601
Test name
Test status
Simulation time 375351324 ps
CPU time 11.55 seconds
Started Aug 14 05:31:27 PM PDT 24
Finished Aug 14 05:31:39 PM PDT 24
Peak memory 226060 kb
Host smart-38d2a63e-a9ad-4af7-b4be-b916dc2cccea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597971076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2597971076
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2088043682
Short name T103
Test name
Test status
Simulation time 396912989 ps
CPU time 14.03 seconds
Started Aug 14 05:31:29 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 226008 kb
Host smart-28de6f19-78c1-4371-8109-6cacb911073a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088043682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2088043682
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1371524834
Short name T738
Test name
Test status
Simulation time 973283277 ps
CPU time 7.79 seconds
Started Aug 14 05:31:33 PM PDT 24
Finished Aug 14 05:31:41 PM PDT 24
Peak memory 218276 kb
Host smart-f3610c64-f484-4f59-b418-dcbb9401b1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371524834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1371524834
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2314284453
Short name T803
Test name
Test status
Simulation time 186809186 ps
CPU time 2.27 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 217784 kb
Host smart-485e52a8-89ad-443c-8b1b-1377bc27f0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314284453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2314284453
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3975848778
Short name T556
Test name
Test status
Simulation time 315900377 ps
CPU time 31.3 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 247508 kb
Host smart-98dea651-f770-4201-b035-553f8847a8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975848778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3975848778
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1670190493
Short name T77
Test name
Test status
Simulation time 46647188 ps
CPU time 8.51 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 250928 kb
Host smart-654a0d32-c36e-4fe3-b0c3-d366fe39b469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670190493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1670190493
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4275024769
Short name T71
Test name
Test status
Simulation time 5219627101 ps
CPU time 115.62 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 275620 kb
Host smart-90434497-5dbe-4b44-ba84-dce37114bedf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275024769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4275024769
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3891202707
Short name T456
Test name
Test status
Simulation time 21832217 ps
CPU time 0.99 seconds
Started Aug 14 05:31:22 PM PDT 24
Finished Aug 14 05:31:23 PM PDT 24
Peak memory 211988 kb
Host smart-17af495f-f5d6-43d6-85d7-9ca3182ec4cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891202707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3891202707
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2758792036
Short name T166
Test name
Test status
Simulation time 58340331 ps
CPU time 1.37 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 208956 kb
Host smart-a8a9106f-910d-4e7a-a838-70c5e0364810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758792036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2758792036
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.811498140
Short name T818
Test name
Test status
Simulation time 241056997 ps
CPU time 10.16 seconds
Started Aug 14 05:31:32 PM PDT 24
Finished Aug 14 05:31:42 PM PDT 24
Peak memory 218308 kb
Host smart-ccb4c61e-de93-4477-9c72-07868eeb33fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811498140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.811498140
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3664141083
Short name T173
Test name
Test status
Simulation time 746830596 ps
CPU time 15.91 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:46 PM PDT 24
Peak memory 217328 kb
Host smart-97cdd90b-f2a6-41c4-a678-7a3963d9bc2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664141083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3664141083
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3148508503
Short name T804
Test name
Test status
Simulation time 84131926 ps
CPU time 3.76 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:35 PM PDT 24
Peak memory 218272 kb
Host smart-fce701fe-dd0b-41f6-8ed2-c6096f787217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148508503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3148508503
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1528471927
Short name T255
Test name
Test status
Simulation time 388923399 ps
CPU time 8.7 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 218320 kb
Host smart-2a49fa7f-9565-4dd9-baf9-2a7e000b2d12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528471927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1528471927
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2036357904
Short name T651
Test name
Test status
Simulation time 493324344 ps
CPU time 8.62 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:35 PM PDT 24
Peak memory 226032 kb
Host smart-2b27ad7b-635e-44f9-8381-93be7fede9cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036357904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2036357904
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.4132267425
Short name T645
Test name
Test status
Simulation time 783700358 ps
CPU time 7.23 seconds
Started Aug 14 05:31:24 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 218224 kb
Host smart-0d32700c-890d-4dc7-805b-f514227df966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132267425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
4132267425
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4184752909
Short name T476
Test name
Test status
Simulation time 1301088162 ps
CPU time 9.87 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:41 PM PDT 24
Peak memory 226004 kb
Host smart-e3d74a2c-65b6-4f51-a4f3-0079f538b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184752909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4184752909
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3720540328
Short name T109
Test name
Test status
Simulation time 52133231 ps
CPU time 3.19 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 217632 kb
Host smart-42cfc8c5-e965-41fe-8c6a-e234ca772096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720540328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3720540328
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.4031348019
Short name T328
Test name
Test status
Simulation time 311533877 ps
CPU time 34.86 seconds
Started Aug 14 05:31:53 PM PDT 24
Finished Aug 14 05:32:28 PM PDT 24
Peak memory 250908 kb
Host smart-cf14a5f1-a87e-4410-9d54-c11405dee999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031348019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.4031348019
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.882837379
Short name T481
Test name
Test status
Simulation time 291324472 ps
CPU time 7.63 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:39 PM PDT 24
Peak memory 247212 kb
Host smart-486a0048-7457-4967-910d-80bd4172407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882837379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.882837379
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4118617010
Short name T362
Test name
Test status
Simulation time 40821025 ps
CPU time 0.82 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:26 PM PDT 24
Peak memory 211972 kb
Host smart-b0b91327-5b12-4e84-8297-49ff863a26f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118617010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4118617010
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3130330102
Short name T550
Test name
Test status
Simulation time 241714145 ps
CPU time 0.96 seconds
Started Aug 14 05:31:33 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 208904 kb
Host smart-62e7843c-8bdd-40c9-8600-28c698cc8056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130330102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3130330102
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.4113445445
Short name T508
Test name
Test status
Simulation time 410622860 ps
CPU time 13.59 seconds
Started Aug 14 05:31:33 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 226080 kb
Host smart-d22ec128-a795-4dc7-ad85-eeff23142ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113445445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.4113445445
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3848085787
Short name T798
Test name
Test status
Simulation time 578838539 ps
CPU time 2.68 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:34 PM PDT 24
Peak memory 217204 kb
Host smart-42de5f8f-4a26-46ca-95e7-8a85213e2f60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848085787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3848085787
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.735048342
Short name T646
Test name
Test status
Simulation time 297255875 ps
CPU time 2.88 seconds
Started Aug 14 05:31:36 PM PDT 24
Finished Aug 14 05:31:39 PM PDT 24
Peak memory 218288 kb
Host smart-3b970616-4885-41e6-b56e-7c81c66e32f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735048342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.735048342
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2324679068
Short name T855
Test name
Test status
Simulation time 763928317 ps
CPU time 11.4 seconds
Started Aug 14 05:31:32 PM PDT 24
Finished Aug 14 05:31:43 PM PDT 24
Peak memory 219012 kb
Host smart-069805d7-5825-49cf-b8aa-fad4dd2d6142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324679068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2324679068
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2309444070
Short name T598
Test name
Test status
Simulation time 662935048 ps
CPU time 11.18 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:42 PM PDT 24
Peak memory 225992 kb
Host smart-9333161b-b557-4596-845f-e50d82833c72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309444070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2309444070
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.573920958
Short name T221
Test name
Test status
Simulation time 261096153 ps
CPU time 9.55 seconds
Started Aug 14 05:31:37 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 226044 kb
Host smart-bbdceabf-da82-4653-a306-ae0be334e4bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573920958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.573920958
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2961875876
Short name T467
Test name
Test status
Simulation time 8315049349 ps
CPU time 10.43 seconds
Started Aug 14 05:31:37 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 226156 kb
Host smart-43210f9d-a436-405e-94fc-b83e7e818136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961875876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2961875876
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1039492183
Short name T525
Test name
Test status
Simulation time 130727346 ps
CPU time 4.05 seconds
Started Aug 14 05:31:23 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 217648 kb
Host smart-2ef42214-a67e-4f9b-875d-b63c12e7cc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039492183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1039492183
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1278296152
Short name T302
Test name
Test status
Simulation time 572095639 ps
CPU time 28.57 seconds
Started Aug 14 05:31:25 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 250920 kb
Host smart-b9573b39-e8e9-4421-8f72-3c48d5cf66c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278296152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1278296152
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1984527316
Short name T600
Test name
Test status
Simulation time 221857896 ps
CPU time 3.57 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:46 PM PDT 24
Peak memory 226352 kb
Host smart-fd7a5ed6-8a82-44fe-a023-46b9069086d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984527316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1984527316
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.464737298
Short name T593
Test name
Test status
Simulation time 9573621674 ps
CPU time 43.32 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:32:14 PM PDT 24
Peak memory 221076 kb
Host smart-03cd9eaa-ef14-4198-b67f-346e5fcbd8a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464737298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.464737298
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3956662950
Short name T52
Test name
Test status
Simulation time 6276986204 ps
CPU time 45.45 seconds
Started Aug 14 05:31:32 PM PDT 24
Finished Aug 14 05:32:18 PM PDT 24
Peak memory 267480 kb
Host smart-2df6ed4f-3eb8-42a7-9c28-5d0ad6e3cf67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3956662950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3956662950
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2653567243
Short name T436
Test name
Test status
Simulation time 16067482 ps
CPU time 1.01 seconds
Started Aug 14 05:31:26 PM PDT 24
Finished Aug 14 05:31:28 PM PDT 24
Peak memory 212964 kb
Host smart-48828772-9d44-45b2-9e3f-4a3c7413b0b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653567243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2653567243
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.4144099669
Short name T461
Test name
Test status
Simulation time 12979153 ps
CPU time 1.04 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:29:52 PM PDT 24
Peak memory 208904 kb
Host smart-c90b4392-b277-4ea1-b0a0-97d9106ebd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144099669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.4144099669
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1195949523
Short name T771
Test name
Test status
Simulation time 35756853 ps
CPU time 0.78 seconds
Started Aug 14 05:29:41 PM PDT 24
Finished Aug 14 05:29:42 PM PDT 24
Peak memory 208940 kb
Host smart-22749985-e0fb-459e-adb0-e59df92b2c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195949523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1195949523
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1738143699
Short name T455
Test name
Test status
Simulation time 701860195 ps
CPU time 24.78 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 218284 kb
Host smart-f38057b2-e2c0-418f-9b45-6de5c1af0a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738143699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1738143699
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1128833876
Short name T465
Test name
Test status
Simulation time 644562789 ps
CPU time 4.54 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:29:45 PM PDT 24
Peak memory 217336 kb
Host smart-55a663ca-80b1-4b64-939b-7e16dd7f08a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128833876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1128833876
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2512885314
Short name T619
Test name
Test status
Simulation time 1270892220 ps
CPU time 30.99 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:30:09 PM PDT 24
Peak memory 218320 kb
Host smart-f62bc309-1d35-4144-bb4b-f4cd79c20c4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512885314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2512885314
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.684679282
Short name T291
Test name
Test status
Simulation time 821393249 ps
CPU time 21.02 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 217696 kb
Host smart-e87db151-f4bc-45b1-910a-617fb95f59ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684679282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.684679282
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1352541643
Short name T318
Test name
Test status
Simulation time 1127819006 ps
CPU time 5.04 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:43 PM PDT 24
Peak memory 218252 kb
Host smart-be54e538-0732-4afd-99b0-3411c593da3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352541643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1352541643
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1676042581
Short name T67
Test name
Test status
Simulation time 4061861061 ps
CPU time 10.29 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:29:50 PM PDT 24
Peak memory 217724 kb
Host smart-3ecc35b2-4470-4741-8de8-d67196cf8fc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676042581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1676042581
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.826305123
Short name T599
Test name
Test status
Simulation time 88241043 ps
CPU time 2.08 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:41 PM PDT 24
Peak memory 217604 kb
Host smart-93d9ee72-3681-4aad-926e-70719b5d7f36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826305123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.826305123
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2113280801
Short name T800
Test name
Test status
Simulation time 1129653383 ps
CPU time 33.6 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:30:13 PM PDT 24
Peak memory 250852 kb
Host smart-965521bb-7bf6-4e06-b029-eb1a54435d9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113280801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2113280801
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1768779194
Short name T516
Test name
Test status
Simulation time 6460913172 ps
CPU time 19.43 seconds
Started Aug 14 05:29:41 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 250932 kb
Host smart-673ae5cb-1b71-44fe-adbd-9bee921fb10f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768779194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1768779194
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2963748178
Short name T489
Test name
Test status
Simulation time 177696724 ps
CPU time 2.85 seconds
Started Aug 14 05:29:37 PM PDT 24
Finished Aug 14 05:29:40 PM PDT 24
Peak memory 218292 kb
Host smart-821456dd-1d04-45f7-8361-c74172c33c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963748178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2963748178
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2572803988
Short name T58
Test name
Test status
Simulation time 339694102 ps
CPU time 9.35 seconds
Started Aug 14 05:29:40 PM PDT 24
Finished Aug 14 05:29:49 PM PDT 24
Peak memory 217628 kb
Host smart-9281224a-bfc8-42cb-8d04-f1a8e51e7b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572803988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2572803988
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3945746132
Short name T45
Test name
Test status
Simulation time 109117696 ps
CPU time 23.07 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 284344 kb
Host smart-428841e1-fca9-42d8-bea8-3528845d86fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945746132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3945746132
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3908336231
Short name T722
Test name
Test status
Simulation time 346342871 ps
CPU time 10.88 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:49 PM PDT 24
Peak memory 218916 kb
Host smart-49b6887c-5956-403d-a4e7-09647b370e26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908336231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3908336231
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2491593672
Short name T504
Test name
Test status
Simulation time 237637949 ps
CPU time 9.67 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 226032 kb
Host smart-eb3dbcbe-a875-4734-831a-b9b09c307acb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491593672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2491593672
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3610411605
Short name T18
Test name
Test status
Simulation time 210164325 ps
CPU time 6.75 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:46 PM PDT 24
Peak memory 218252 kb
Host smart-38af48a1-b82e-4ae0-8f51-e6d9f7fd7c25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610411605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
610411605
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.596450234
Short name T9
Test name
Test status
Simulation time 235327572 ps
CPU time 6.38 seconds
Started Aug 14 05:29:39 PM PDT 24
Finished Aug 14 05:29:45 PM PDT 24
Peak memory 224472 kb
Host smart-d398e851-cd03-4e4f-a3da-d716b3090173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596450234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.596450234
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1547196291
Short name T791
Test name
Test status
Simulation time 713260579 ps
CPU time 5.11 seconds
Started Aug 14 05:29:37 PM PDT 24
Finished Aug 14 05:29:42 PM PDT 24
Peak memory 217660 kb
Host smart-25093d97-804e-47ab-b222-d660db22eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547196291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1547196291
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2097775361
Short name T751
Test name
Test status
Simulation time 270568727 ps
CPU time 31.94 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 250916 kb
Host smart-4ac858e0-3fa2-4f14-99ff-cdf32d780643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097775361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2097775361
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.690331362
Short name T632
Test name
Test status
Simulation time 195202229 ps
CPU time 6.51 seconds
Started Aug 14 05:29:37 PM PDT 24
Finished Aug 14 05:29:43 PM PDT 24
Peak memory 246864 kb
Host smart-082a367e-c65f-4945-a01c-c696532c5b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690331362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.690331362
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.548523400
Short name T457
Test name
Test status
Simulation time 13275750535 ps
CPU time 70.37 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:30:58 PM PDT 24
Peak memory 278732 kb
Host smart-3dd0aede-7453-465e-ba07-389f621261bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548523400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.548523400
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1809934644
Short name T433
Test name
Test status
Simulation time 9938231849 ps
CPU time 23.22 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 267216 kb
Host smart-eaaacd37-c8b7-45be-b5ef-95103411bfc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1809934644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1809934644
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2732555074
Short name T785
Test name
Test status
Simulation time 39786738 ps
CPU time 0.84 seconds
Started Aug 14 05:29:38 PM PDT 24
Finished Aug 14 05:29:39 PM PDT 24
Peak memory 211836 kb
Host smart-fbbf5e01-df1c-47f9-b69a-cefe848869ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732555074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2732555074
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.244653827
Short name T301
Test name
Test status
Simulation time 16081102 ps
CPU time 0.91 seconds
Started Aug 14 05:31:38 PM PDT 24
Finished Aug 14 05:31:39 PM PDT 24
Peak memory 208876 kb
Host smart-1e9cd858-0692-49c3-bb54-74eea8e24fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244653827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.244653827
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4244373317
Short name T822
Test name
Test status
Simulation time 217741290 ps
CPU time 10.05 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 226092 kb
Host smart-76177712-ea59-4195-ab18-155462698851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244373317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4244373317
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1962377974
Short name T687
Test name
Test status
Simulation time 8839970455 ps
CPU time 32.05 seconds
Started Aug 14 05:31:36 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 217688 kb
Host smart-547cfb85-947b-495f-b744-4456076f6d35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962377974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1962377974
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.138387213
Short name T104
Test name
Test status
Simulation time 89656005 ps
CPU time 1.61 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 218288 kb
Host smart-d0459d05-c7fd-4f87-a10f-111da4e4136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138387213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.138387213
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1596185150
Short name T468
Test name
Test status
Simulation time 427826245 ps
CPU time 10.1 seconds
Started Aug 14 05:31:34 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 226112 kb
Host smart-8a65a846-30ce-4a47-b441-a430f1de754e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596185150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1596185150
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.101957610
Short name T507
Test name
Test status
Simulation time 894595006 ps
CPU time 10.32 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 226032 kb
Host smart-246ccc0c-1f73-4cfb-beac-fe207d79537f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101957610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.101957610
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3143598120
Short name T628
Test name
Test status
Simulation time 425876782 ps
CPU time 9.67 seconds
Started Aug 14 05:31:39 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 226032 kb
Host smart-6ef38396-8f0c-45fe-bd39-30e63d07eab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143598120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3143598120
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2590500131
Short name T397
Test name
Test status
Simulation time 307217649 ps
CPU time 9.77 seconds
Started Aug 14 05:31:37 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 225272 kb
Host smart-5333cd33-2ec1-4f60-b142-f8af6983f582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590500131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2590500131
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1633612615
Short name T68
Test name
Test status
Simulation time 243811865 ps
CPU time 2.54 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:45 PM PDT 24
Peak memory 214568 kb
Host smart-de125861-95e9-402a-a191-562cd7da9092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633612615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1633612615
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1892485066
Short name T464
Test name
Test status
Simulation time 308804548 ps
CPU time 24.43 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 250920 kb
Host smart-b8a73707-132e-4756-a3ff-4b418b8bc0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892485066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1892485066
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3741864409
Short name T312
Test name
Test status
Simulation time 638651380 ps
CPU time 4.39 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:35 PM PDT 24
Peak memory 222996 kb
Host smart-705fdf62-dc26-48f2-97bd-1e89336e6254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741864409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3741864409
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1362386344
Short name T697
Test name
Test status
Simulation time 13170818727 ps
CPU time 140.82 seconds
Started Aug 14 05:31:34 PM PDT 24
Finished Aug 14 05:33:55 PM PDT 24
Peak memory 274696 kb
Host smart-e36a314b-fb12-45ee-9c71-56cf8d6fbf52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362386344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1362386344
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1498235114
Short name T767
Test name
Test status
Simulation time 32093132 ps
CPU time 0.89 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:31 PM PDT 24
Peak memory 212988 kb
Host smart-d2eb3c6f-f6a4-45f7-9ce3-4c00d8f669ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498235114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1498235114
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3326137980
Short name T441
Test name
Test status
Simulation time 21325983 ps
CPU time 0.9 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:31 PM PDT 24
Peak memory 208896 kb
Host smart-0678b2c2-7cd2-44cc-ada7-ec8ce46fcf28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326137980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3326137980
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3038906896
Short name T257
Test name
Test status
Simulation time 1431815313 ps
CPU time 10.7 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 218296 kb
Host smart-3d5758e3-92e0-4e22-acee-be9a97b731cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038906896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3038906896
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.844474207
Short name T752
Test name
Test status
Simulation time 261251382 ps
CPU time 7.25 seconds
Started Aug 14 05:31:36 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 217300 kb
Host smart-173f352d-db72-42f4-9848-1eb0f7413bf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844474207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.844474207
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3646807346
Short name T253
Test name
Test status
Simulation time 21361448 ps
CPU time 1.55 seconds
Started Aug 14 05:31:29 PM PDT 24
Finished Aug 14 05:31:31 PM PDT 24
Peak memory 222040 kb
Host smart-3e8bb35a-4827-4030-9baa-248ea118a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646807346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3646807346
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.162257155
Short name T691
Test name
Test status
Simulation time 778379757 ps
CPU time 15.72 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:46 PM PDT 24
Peak memory 226096 kb
Host smart-e589cb3f-785d-4c9e-9a0f-2f079b952b56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162257155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.162257155
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.86794167
Short name T12
Test name
Test status
Simulation time 1456450548 ps
CPU time 11.93 seconds
Started Aug 14 05:31:32 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 226096 kb
Host smart-43fe3670-6c69-4ead-af8c-80efaeecc4d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86794167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_dig
est.86794167
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2798748875
Short name T744
Test name
Test status
Simulation time 182694819 ps
CPU time 7.78 seconds
Started Aug 14 05:31:39 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 218268 kb
Host smart-bcfa2516-a2a2-4621-846c-f1c0a3d7cdd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798748875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2798748875
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.81877250
Short name T610
Test name
Test status
Simulation time 765391791 ps
CPU time 9.36 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:52 PM PDT 24
Peak memory 218360 kb
Host smart-4eade659-313a-4147-bb5b-b037d15c8ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81877250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.81877250
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.197706449
Short name T417
Test name
Test status
Simulation time 46755917 ps
CPU time 1.84 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 214028 kb
Host smart-62e21042-e7d7-42d9-83de-bc8a4b2cf7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197706449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.197706449
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.401085022
Short name T707
Test name
Test status
Simulation time 217097831 ps
CPU time 19.63 seconds
Started Aug 14 05:31:38 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 245956 kb
Host smart-37bbc852-fefa-4e20-9a3a-9127f93c6e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401085022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.401085022
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3812791643
Short name T802
Test name
Test status
Simulation time 375952361 ps
CPU time 9.12 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 250936 kb
Host smart-bd59d549-ddbe-4c75-8ea1-fe4e21c1b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812791643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3812791643
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3580440118
Short name T447
Test name
Test status
Simulation time 33857157053 ps
CPU time 283.18 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:36:26 PM PDT 24
Peak memory 421912 kb
Host smart-80f73673-eeef-4481-b0a1-d8468afe4d21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580440118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3580440118
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.360095992
Short name T296
Test name
Test status
Simulation time 6979748077 ps
CPU time 46.52 seconds
Started Aug 14 05:31:36 PM PDT 24
Finished Aug 14 05:32:22 PM PDT 24
Peak memory 259420 kb
Host smart-3cd5ac1b-e694-4ad2-96dd-79836872ca5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=360095992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.360095992
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1979259763
Short name T483
Test name
Test status
Simulation time 154061787 ps
CPU time 0.71 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:42 PM PDT 24
Peak memory 207032 kb
Host smart-1ba1aa5a-1d74-44c6-a73b-d63f2e03f616
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979259763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1979259763
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3844515757
Short name T776
Test name
Test status
Simulation time 49786165 ps
CPU time 1.09 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 208976 kb
Host smart-0e323e30-9a73-4d49-a41b-b24d3caa79f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844515757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3844515757
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2435229093
Short name T571
Test name
Test status
Simulation time 1165408109 ps
CPU time 9.75 seconds
Started Aug 14 05:31:36 PM PDT 24
Finished Aug 14 05:31:46 PM PDT 24
Peak memory 218300 kb
Host smart-5753ec3f-d250-465b-a79e-36cd3aac0863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435229093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2435229093
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3265698685
Short name T608
Test name
Test status
Simulation time 534871953 ps
CPU time 6.06 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 217344 kb
Host smart-496491ca-9a18-4600-8824-440718f2861c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265698685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3265698685
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.4178488335
Short name T262
Test name
Test status
Simulation time 198198984 ps
CPU time 2.56 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 218288 kb
Host smart-a90c09fa-0260-41f4-9d0c-a481a626aebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178488335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.4178488335
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.721962943
Short name T627
Test name
Test status
Simulation time 687937949 ps
CPU time 17.31 seconds
Started Aug 14 05:31:30 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 218932 kb
Host smart-6cbf603e-1674-4770-840b-99cbf5a8031d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721962943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.721962943
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.520299749
Short name T768
Test name
Test status
Simulation time 553355045 ps
CPU time 18.25 seconds
Started Aug 14 05:31:29 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 226036 kb
Host smart-192aa6aa-aa3b-4767-881c-9ffe620e0587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520299749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.520299749
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4096126450
Short name T222
Test name
Test status
Simulation time 2037552521 ps
CPU time 8.94 seconds
Started Aug 14 05:31:37 PM PDT 24
Finished Aug 14 05:31:46 PM PDT 24
Peak memory 218168 kb
Host smart-ccb1eeae-d20d-46e4-a14d-5b3f3c96bbfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096126450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4096126450
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2384638984
Short name T418
Test name
Test status
Simulation time 730295461 ps
CPU time 13.38 seconds
Started Aug 14 05:31:33 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 226008 kb
Host smart-2bfc4f64-483f-4711-8098-6f2667cad33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384638984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2384638984
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.262132245
Short name T252
Test name
Test status
Simulation time 27430889 ps
CPU time 1.87 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:33 PM PDT 24
Peak memory 214140 kb
Host smart-9b28a749-4e9d-4c51-a03a-1a153de8dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262132245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.262132245
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1003695396
Short name T809
Test name
Test status
Simulation time 528158727 ps
CPU time 17.51 seconds
Started Aug 14 05:31:39 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 250916 kb
Host smart-f1e7f893-6f54-4cb7-b540-9ec181dba74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003695396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1003695396
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3797980711
Short name T149
Test name
Test status
Simulation time 92522650 ps
CPU time 7.37 seconds
Started Aug 14 05:31:41 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 250932 kb
Host smart-64e3cb2d-7bc6-4cac-817e-35f695322cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797980711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3797980711
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3259201581
Short name T34
Test name
Test status
Simulation time 8127713332 ps
CPU time 149.5 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:34:11 PM PDT 24
Peak memory 332884 kb
Host smart-ba817b23-e448-4b60-a72f-827761a8179c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259201581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3259201581
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3535849901
Short name T146
Test name
Test status
Simulation time 4532709941 ps
CPU time 120.2 seconds
Started Aug 14 05:31:34 PM PDT 24
Finished Aug 14 05:33:34 PM PDT 24
Peak memory 267520 kb
Host smart-f5f1fc27-885f-4703-a40d-f3b4821f7b25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3535849901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3535849901
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2635771553
Short name T866
Test name
Test status
Simulation time 136058728 ps
CPU time 0.72 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 207048 kb
Host smart-14f1ede0-eb1f-46e3-a8d3-b3212786127f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635771553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2635771553
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.486789619
Short name T229
Test name
Test status
Simulation time 18159496 ps
CPU time 0.9 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 208880 kb
Host smart-6afee771-fe5c-43b3-91ed-2bf41955aa46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486789619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.486789619
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3657455166
Short name T637
Test name
Test status
Simulation time 1249280744 ps
CPU time 10.28 seconds
Started Aug 14 05:31:37 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 218284 kb
Host smart-a64c6de2-43e5-4245-89ed-326f0b431ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657455166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3657455166
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2674542301
Short name T27
Test name
Test status
Simulation time 1267002130 ps
CPU time 20.49 seconds
Started Aug 14 05:31:39 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 217356 kb
Host smart-0fc012e2-ef41-4b53-a171-7d65cf051950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674542301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2674542301
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.75857400
Short name T319
Test name
Test status
Simulation time 58058154 ps
CPU time 3.23 seconds
Started Aug 14 05:31:37 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 218288 kb
Host smart-e9862e8a-8013-4b42-9778-be020aed961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75857400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.75857400
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1596504594
Short name T723
Test name
Test status
Simulation time 407749095 ps
CPU time 16.56 seconds
Started Aug 14 05:31:40 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 218304 kb
Host smart-f0276b35-ab8e-4835-bf37-1771b7cf87b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596504594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1596504594
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3300206548
Short name T824
Test name
Test status
Simulation time 3252782439 ps
CPU time 17.25 seconds
Started Aug 14 05:31:36 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 226108 kb
Host smart-62b0a2c8-4e43-43c5-8963-f28815351c10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300206548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3300206548
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2781404511
Short name T55
Test name
Test status
Simulation time 993065330 ps
CPU time 10.74 seconds
Started Aug 14 05:31:40 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 226024 kb
Host smart-4b65f01c-3cb1-45a4-9fea-8dbffd3af400
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781404511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2781404511
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2323227755
Short name T650
Test name
Test status
Simulation time 448124546 ps
CPU time 15.55 seconds
Started Aug 14 05:31:38 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 226100 kb
Host smart-4327071d-901a-4646-a381-20be4b8f342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323227755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2323227755
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.735837109
Short name T777
Test name
Test status
Simulation time 106664111 ps
CPU time 3.29 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 217652 kb
Host smart-e5f9e4ce-1382-473b-b79b-47ee8aa0253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735837109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.735837109
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1353205064
Short name T847
Test name
Test status
Simulation time 728647351 ps
CPU time 24.87 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:32:07 PM PDT 24
Peak memory 250916 kb
Host smart-6ce72ed6-00a7-4468-abb7-f0311c7ff1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353205064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1353205064
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.887117021
Short name T311
Test name
Test status
Simulation time 786382244 ps
CPU time 8.49 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:52 PM PDT 24
Peak memory 250920 kb
Host smart-fc684d27-e422-41c8-8af0-67960eded203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887117021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.887117021
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3154580547
Short name T553
Test name
Test status
Simulation time 8649359635 ps
CPU time 85.67 seconds
Started Aug 14 05:31:40 PM PDT 24
Finished Aug 14 05:33:06 PM PDT 24
Peak memory 278500 kb
Host smart-a0f35d73-8ca3-42a7-9cee-341920e80147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154580547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3154580547
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1726158495
Short name T540
Test name
Test status
Simulation time 35874135 ps
CPU time 0.72 seconds
Started Aug 14 05:31:31 PM PDT 24
Finished Aug 14 05:31:31 PM PDT 24
Peak memory 207040 kb
Host smart-56dbc413-eaee-422c-9821-3aa650fe65e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726158495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1726158495
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4112391422
Short name T746
Test name
Test status
Simulation time 88654274 ps
CPU time 1.02 seconds
Started Aug 14 05:31:46 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 208884 kb
Host smart-7021b1aa-d4d2-47fd-94b1-5d90b1fa96cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112391422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4112391422
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.537119347
Short name T265
Test name
Test status
Simulation time 998682710 ps
CPU time 11.48 seconds
Started Aug 14 05:31:47 PM PDT 24
Finished Aug 14 05:31:59 PM PDT 24
Peak memory 218292 kb
Host smart-77e99ba6-591b-4d56-ad0a-0335791c0cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537119347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.537119347
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3235077147
Short name T395
Test name
Test status
Simulation time 150412525 ps
CPU time 3.11 seconds
Started Aug 14 05:31:45 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 217036 kb
Host smart-f0b0adf9-afbd-4c3b-82bc-ff314589d49c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235077147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3235077147
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.5032081
Short name T761
Test name
Test status
Simulation time 33839638 ps
CPU time 2.02 seconds
Started Aug 14 05:31:45 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 222240 kb
Host smart-e54d0bd6-0a90-40f5-a407-949e07b00e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5032081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.5032081
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.971101428
Short name T226
Test name
Test status
Simulation time 400298831 ps
CPU time 12.31 seconds
Started Aug 14 05:31:46 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 226104 kb
Host smart-a89cb2a6-dff0-44ff-93dc-2804e98041e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971101428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.971101428
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2389342349
Short name T506
Test name
Test status
Simulation time 221206897 ps
CPU time 8.47 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:50 PM PDT 24
Peak memory 226012 kb
Host smart-5c0fb2b3-bb48-4e13-8832-66018b29f7b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389342349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2389342349
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2063681259
Short name T786
Test name
Test status
Simulation time 1721149565 ps
CPU time 10.54 seconds
Started Aug 14 05:31:52 PM PDT 24
Finished Aug 14 05:32:02 PM PDT 24
Peak memory 218220 kb
Host smart-2f5eef6c-364e-4d99-a1ab-756715d50ffc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063681259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2063681259
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2572157341
Short name T46
Test name
Test status
Simulation time 306117951 ps
CPU time 8.9 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:52 PM PDT 24
Peak memory 225008 kb
Host smart-bc546ef0-4170-4b36-9ee1-8cef15ea3b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572157341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2572157341
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3410024510
Short name T72
Test name
Test status
Simulation time 32356804 ps
CPU time 1.82 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:31:46 PM PDT 24
Peak memory 214072 kb
Host smart-b38a07f0-e356-4674-83de-a021ec02e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410024510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3410024510
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1832473418
Short name T869
Test name
Test status
Simulation time 308776125 ps
CPU time 24.05 seconds
Started Aug 14 05:31:41 PM PDT 24
Finished Aug 14 05:32:05 PM PDT 24
Peak memory 250916 kb
Host smart-71602f37-9b1c-4bd6-bb2d-44816a226b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832473418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1832473418
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3581506816
Short name T725
Test name
Test status
Simulation time 405625880 ps
CPU time 7.37 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 250920 kb
Host smart-b7209ba8-8853-43ee-b5f6-ef3781e74e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581506816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3581506816
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3322239398
Short name T622
Test name
Test status
Simulation time 4235911625 ps
CPU time 23.75 seconds
Started Aug 14 05:31:45 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 249640 kb
Host smart-debbbe8d-875b-44aa-b01e-e4c4b8297ab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322239398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3322239398
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2584139651
Short name T206
Test name
Test status
Simulation time 13853955 ps
CPU time 1.11 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 211696 kb
Host smart-027f0918-9899-41fd-8393-30e5e5f56271
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584139651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2584139651
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3510285755
Short name T833
Test name
Test status
Simulation time 82003065 ps
CPU time 0.94 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:31:45 PM PDT 24
Peak memory 208908 kb
Host smart-a08ec6ea-d362-411c-a486-bf9bb47f6681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510285755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3510285755
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.271035777
Short name T408
Test name
Test status
Simulation time 220090437 ps
CPU time 10.82 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 218288 kb
Host smart-95878372-e96b-4fa3-b9f4-f8ac2fe0b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271035777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.271035777
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2837155094
Short name T834
Test name
Test status
Simulation time 497293198 ps
CPU time 3.95 seconds
Started Aug 14 05:31:41 PM PDT 24
Finished Aug 14 05:31:45 PM PDT 24
Peak memory 217340 kb
Host smart-4173184e-7d7d-486b-ab55-f48e41a49088
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837155094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2837155094
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3458339814
Short name T325
Test name
Test status
Simulation time 49137874 ps
CPU time 1.72 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 222172 kb
Host smart-b2ce8578-0e34-4480-819b-924624fc11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458339814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3458339814
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.226371840
Short name T241
Test name
Test status
Simulation time 5043438933 ps
CPU time 13.52 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 226148 kb
Host smart-2dae9b94-72fc-47e5-a7a8-10c0be9f6189
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226371840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.226371840
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.4161032186
Short name T414
Test name
Test status
Simulation time 585726939 ps
CPU time 16.32 seconds
Started Aug 14 05:31:46 PM PDT 24
Finished Aug 14 05:32:03 PM PDT 24
Peak memory 226024 kb
Host smart-0fe48a30-4f0b-4a54-89e1-26a6030bad39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161032186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.4161032186
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3430260958
Short name T846
Test name
Test status
Simulation time 1365779483 ps
CPU time 8.28 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 218192 kb
Host smart-5e452b3a-2c4b-4225-80fd-9f50695348eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430260958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3430260958
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1141649336
Short name T316
Test name
Test status
Simulation time 2663325877 ps
CPU time 11.89 seconds
Started Aug 14 05:31:52 PM PDT 24
Finished Aug 14 05:32:04 PM PDT 24
Peak memory 218484 kb
Host smart-ef235fe5-8b6a-41bb-9f74-d9fa088d8542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141649336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1141649336
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2743079856
Short name T552
Test name
Test status
Simulation time 321490310 ps
CPU time 1.64 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 217644 kb
Host smart-26737e25-fd80-4961-b73f-2982c1e19eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743079856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2743079856
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3743378861
Short name T621
Test name
Test status
Simulation time 186471684 ps
CPU time 14.45 seconds
Started Aug 14 05:31:45 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 250932 kb
Host smart-1ac326e9-0dfe-4abf-a972-6536b746d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743378861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3743378861
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1131586945
Short name T796
Test name
Test status
Simulation time 43410875 ps
CPU time 6.39 seconds
Started Aug 14 05:31:49 PM PDT 24
Finished Aug 14 05:31:55 PM PDT 24
Peak memory 248556 kb
Host smart-8b7c3940-0cbe-45ac-aea7-20eeaf86f52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131586945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1131586945
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.50379788
Short name T340
Test name
Test status
Simulation time 17775058538 ps
CPU time 98.23 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:33:21 PM PDT 24
Peak memory 268196 kb
Host smart-ac92806f-76d5-4da8-8d7c-de94adc09ca4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50379788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.lc_ctrl_stress_all.50379788
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2094414030
Short name T810
Test name
Test status
Simulation time 59049416 ps
CPU time 0.92 seconds
Started Aug 14 05:31:39 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 211932 kb
Host smart-1076eadf-de09-4c7f-92fd-2db19b9e0974
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094414030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2094414030
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.808980595
Short name T497
Test name
Test status
Simulation time 14284526 ps
CPU time 0.88 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 208688 kb
Host smart-225dd935-8d22-49d8-912a-f629c76f9218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808980595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.808980595
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2645944489
Short name T817
Test name
Test status
Simulation time 2288946073 ps
CPU time 16.17 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 218348 kb
Host smart-c4d23244-91e0-4af2-9038-ab023922f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645944489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2645944489
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1673998606
Short name T413
Test name
Test status
Simulation time 224076461 ps
CPU time 3.17 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:31:47 PM PDT 24
Peak memory 217036 kb
Host smart-b41c8e20-4353-43d1-a6e1-2744742abe43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673998606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1673998606
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.880890144
Short name T337
Test name
Test status
Simulation time 59339067 ps
CPU time 2.3 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:45 PM PDT 24
Peak memory 222240 kb
Host smart-5b359718-0581-420e-ae2e-eb83246c6713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880890144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.880890144
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1081577558
Short name T568
Test name
Test status
Simulation time 2341641769 ps
CPU time 12.39 seconds
Started Aug 14 05:31:41 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 226148 kb
Host smart-53d5ad13-1e7e-4db4-a97c-071de734e772
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081577558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1081577558
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3277338936
Short name T732
Test name
Test status
Simulation time 249503060 ps
CPU time 10.74 seconds
Started Aug 14 05:31:45 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 226052 kb
Host smart-26415cac-e1c3-4945-b2bd-45acd1295bdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277338936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3277338936
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1895307861
Short name T279
Test name
Test status
Simulation time 1347733056 ps
CPU time 12.62 seconds
Started Aug 14 05:31:45 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 218204 kb
Host smart-1a47f439-5dba-476c-8deb-cda494ed9579
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895307861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1895307861
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4255219004
Short name T40
Test name
Test status
Simulation time 4835627853 ps
CPU time 14.37 seconds
Started Aug 14 05:31:45 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 218424 kb
Host smart-09d62888-2176-403b-908e-5c43e5021737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255219004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4255219004
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2621121983
Short name T59
Test name
Test status
Simulation time 37656242 ps
CPU time 1.61 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:45 PM PDT 24
Peak memory 217468 kb
Host smart-a462e394-c6c9-448f-b80d-b605f7a7fdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621121983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2621121983
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3945095232
Short name T449
Test name
Test status
Simulation time 776619343 ps
CPU time 30.11 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:32:13 PM PDT 24
Peak memory 247412 kb
Host smart-612e0f6e-3d96-42e9-ab0c-22bd61274fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945095232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3945095232
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.660291884
Short name T808
Test name
Test status
Simulation time 204392090 ps
CPU time 6.76 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 250472 kb
Host smart-572685ad-4bc4-4678-8a8f-2c9cd6a8cf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660291884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.660291884
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2311092804
Short name T32
Test name
Test status
Simulation time 13294014838 ps
CPU time 210.47 seconds
Started Aug 14 05:31:51 PM PDT 24
Finished Aug 14 05:35:22 PM PDT 24
Peak memory 270332 kb
Host smart-18006e16-5449-4cf5-87b4-835757fc85c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311092804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2311092804
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.116020456
Short name T88
Test name
Test status
Simulation time 3142503799 ps
CPU time 24.26 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 226280 kb
Host smart-d3b81b36-fcf2-46c1-b425-999278934f91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=116020456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.116020456
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3126928341
Short name T435
Test name
Test status
Simulation time 40786653 ps
CPU time 0.86 seconds
Started Aug 14 05:31:47 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 208492 kb
Host smart-a5764246-ecf6-43fb-ad32-682921fccbf7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126928341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3126928341
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3025812423
Short name T582
Test name
Test status
Simulation time 56065754 ps
CPU time 1.09 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 208952 kb
Host smart-b8b5591a-cdfa-4134-82df-3b45e3e733ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025812423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3025812423
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.420677438
Short name T579
Test name
Test status
Simulation time 327385707 ps
CPU time 10.95 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 226104 kb
Host smart-b910d368-c88a-43df-ade9-84dfe581ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420677438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.420677438
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.866839734
Short name T428
Test name
Test status
Simulation time 1113535767 ps
CPU time 6.25 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:49 PM PDT 24
Peak memory 217176 kb
Host smart-fe52af22-6ee5-45c6-b6cb-85e53f630d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866839734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.866839734
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.4040149079
Short name T801
Test name
Test status
Simulation time 289596384 ps
CPU time 2.91 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 218288 kb
Host smart-689618b8-1f78-4996-b485-df762af09f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040149079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.4040149079
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3160692226
Short name T577
Test name
Test status
Simulation time 1333728379 ps
CPU time 14.79 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 226016 kb
Host smart-2dc15e80-dd59-4556-8021-7147153cfaf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160692226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3160692226
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.197246581
Short name T589
Test name
Test status
Simulation time 618191567 ps
CPU time 16.41 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 226032 kb
Host smart-e0515474-1ca5-401a-9e26-b2d62638ab30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197246581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.197246581
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.413845352
Short name T595
Test name
Test status
Simulation time 1382692810 ps
CPU time 9.72 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 218236 kb
Host smart-9f1f26e3-8093-4c3d-9eb0-52f2f7fb6670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413845352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.413845352
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1797874052
Short name T47
Test name
Test status
Simulation time 386324530 ps
CPU time 13.62 seconds
Started Aug 14 05:31:46 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 226016 kb
Host smart-ee58fc7f-f910-4779-8f58-babae8ede31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797874052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1797874052
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2006236381
Short name T379
Test name
Test status
Simulation time 105301404 ps
CPU time 2 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 214280 kb
Host smart-7b9cc655-2f5f-4184-9e3d-97ab58d126e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006236381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2006236381
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.206650213
Short name T597
Test name
Test status
Simulation time 314473992 ps
CPU time 29.27 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:32:13 PM PDT 24
Peak memory 250924 kb
Host smart-e9ae39eb-4709-493f-80b2-2ecf6c29cc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206650213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.206650213
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2134527144
Short name T320
Test name
Test status
Simulation time 1057855340 ps
CPU time 9.43 seconds
Started Aug 14 05:31:44 PM PDT 24
Finished Aug 14 05:31:53 PM PDT 24
Peak memory 250960 kb
Host smart-3bc9bfe9-b10f-4f9a-b3a4-8b2aab90ce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134527144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2134527144
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3687295067
Short name T427
Test name
Test status
Simulation time 7114480985 ps
CPU time 36.13 seconds
Started Aug 14 05:31:49 PM PDT 24
Finished Aug 14 05:32:25 PM PDT 24
Peak memory 250932 kb
Host smart-6fd05a69-b526-4237-a274-5e727314c187
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687295067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3687295067
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.672306524
Short name T369
Test name
Test status
Simulation time 10998116 ps
CPU time 0.78 seconds
Started Aug 14 05:31:47 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 208440 kb
Host smart-9832396b-e7bb-42e3-b7cd-df4f563bf52a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672306524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.672306524
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.618316284
Short name T661
Test name
Test status
Simulation time 31126208 ps
CPU time 0.87 seconds
Started Aug 14 05:32:10 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 208892 kb
Host smart-94fde21e-09fb-4789-a92d-7e39d7a01c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618316284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.618316284
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3574368351
Short name T848
Test name
Test status
Simulation time 1326768459 ps
CPU time 12.25 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 218280 kb
Host smart-f627ea96-c23f-43e7-b8c0-cc1f83a36844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574368351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3574368351
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1774395503
Short name T592
Test name
Test status
Simulation time 247893012 ps
CPU time 1.43 seconds
Started Aug 14 05:31:49 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 216948 kb
Host smart-0c6f14fa-cd5d-4676-9994-98762ada429b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774395503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1774395503
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.924489736
Short name T840
Test name
Test status
Simulation time 53558263 ps
CPU time 2.47 seconds
Started Aug 14 05:31:52 PM PDT 24
Finished Aug 14 05:31:54 PM PDT 24
Peak memory 218272 kb
Host smart-79e57d0c-0d9a-4927-acf7-eb3c3c32abbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924489736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.924489736
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1477071998
Short name T243
Test name
Test status
Simulation time 1834487049 ps
CPU time 12.37 seconds
Started Aug 14 05:31:49 PM PDT 24
Finished Aug 14 05:32:02 PM PDT 24
Peak memory 218944 kb
Host smart-b70c1a18-2167-4fb6-b958-2edd94951ad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477071998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1477071998
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3866999505
Short name T805
Test name
Test status
Simulation time 1254496148 ps
CPU time 13.65 seconds
Started Aug 14 05:31:51 PM PDT 24
Finished Aug 14 05:32:05 PM PDT 24
Peak memory 225952 kb
Host smart-8d4f4802-12d9-4fae-bc93-4ece93e14177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866999505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3866999505
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.260673771
Short name T356
Test name
Test status
Simulation time 1645277165 ps
CPU time 6.63 seconds
Started Aug 14 05:32:02 PM PDT 24
Finished Aug 14 05:32:09 PM PDT 24
Peak memory 218252 kb
Host smart-2cafe741-bd57-4801-9dd9-76578c165dc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260673771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.260673771
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2762082380
Short name T563
Test name
Test status
Simulation time 1182219906 ps
CPU time 9.91 seconds
Started Aug 14 05:31:56 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 226112 kb
Host smart-691ec960-0f90-4284-ba3b-ce2ec1b54be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762082380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2762082380
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3951913177
Short name T478
Test name
Test status
Simulation time 150698524 ps
CPU time 1.17 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 217636 kb
Host smart-75b4b2bb-64fe-440e-a7fd-9a6b5ae2e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951913177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3951913177
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1971571558
Short name T835
Test name
Test status
Simulation time 146546878 ps
CPU time 23.47 seconds
Started Aug 14 05:31:47 PM PDT 24
Finished Aug 14 05:32:11 PM PDT 24
Peak memory 250916 kb
Host smart-a9610519-3ad2-4355-9549-85173915420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971571558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1971571558
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3285017955
Short name T336
Test name
Test status
Simulation time 88024190 ps
CPU time 7.67 seconds
Started Aug 14 05:31:43 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 250860 kb
Host smart-5c0d5e16-7af3-41b5-b39f-7755c8d2fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285017955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3285017955
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1298761554
Short name T539
Test name
Test status
Simulation time 5523205662 ps
CPU time 112.79 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:33:41 PM PDT 24
Peak memory 251532 kb
Host smart-b336b912-b599-4868-8f12-5115d366e539
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298761554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1298761554
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.709606401
Short name T383
Test name
Test status
Simulation time 19858984 ps
CPU time 0.97 seconds
Started Aug 14 05:31:42 PM PDT 24
Finished Aug 14 05:31:43 PM PDT 24
Peak memory 211880 kb
Host smart-1bbb9d53-6aef-4a0c-bb50-b13e2cd1db0d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709606401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.709606401
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1015004758
Short name T63
Test name
Test status
Simulation time 136558968 ps
CPU time 1.14 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 208920 kb
Host smart-88552a44-dbd2-402c-8904-2f6f44387707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015004758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1015004758
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3632223509
Short name T416
Test name
Test status
Simulation time 480243989 ps
CPU time 18.39 seconds
Started Aug 14 05:31:50 PM PDT 24
Finished Aug 14 05:32:10 PM PDT 24
Peak memory 218296 kb
Host smart-d46c2717-e750-487e-84af-487483f01ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632223509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3632223509
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3416348957
Short name T681
Test name
Test status
Simulation time 890906029 ps
CPU time 3.03 seconds
Started Aug 14 05:31:53 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 217028 kb
Host smart-bc82e9a3-315a-4cf5-8370-e5c0b70b5f48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416348957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3416348957
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3569458502
Short name T528
Test name
Test status
Simulation time 36518677 ps
CPU time 2.41 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 218300 kb
Host smart-6a30fed1-80e6-4d44-83e3-2dc0a1c54539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569458502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3569458502
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.719975030
Short name T160
Test name
Test status
Simulation time 524749268 ps
CPU time 8.19 seconds
Started Aug 14 05:31:48 PM PDT 24
Finished Aug 14 05:31:56 PM PDT 24
Peak memory 226104 kb
Host smart-827d6fb5-8283-460e-8039-944203b8fccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719975030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.719975030
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2087555110
Short name T620
Test name
Test status
Simulation time 359188888 ps
CPU time 15.2 seconds
Started Aug 14 05:31:52 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 226028 kb
Host smart-2e414d58-fe87-4850-bda0-30fe3822d89b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087555110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2087555110
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1431434615
Short name T463
Test name
Test status
Simulation time 594280018 ps
CPU time 11.71 seconds
Started Aug 14 05:32:00 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 218248 kb
Host smart-9eccb4cc-31e3-4f0f-a00b-d85ff1c96eea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431434615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1431434615
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4195906257
Short name T586
Test name
Test status
Simulation time 541278659 ps
CPU time 12.65 seconds
Started Aug 14 05:31:49 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 226000 kb
Host smart-ae77b1e7-b363-43cc-9296-d94c89df91e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195906257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4195906257
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.360406649
Short name T626
Test name
Test status
Simulation time 122030521 ps
CPU time 2.16 seconds
Started Aug 14 05:31:55 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 217580 kb
Host smart-59b4d28b-910c-4d1c-985b-f91f3f588f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360406649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.360406649
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1086129134
Short name T339
Test name
Test status
Simulation time 980955732 ps
CPU time 30.16 seconds
Started Aug 14 05:31:56 PM PDT 24
Finished Aug 14 05:32:26 PM PDT 24
Peak memory 250952 kb
Host smart-56d35079-91aa-4eb7-b70c-bb7579eb08c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086129134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1086129134
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.4113631099
Short name T246
Test name
Test status
Simulation time 201843378 ps
CPU time 9.52 seconds
Started Aug 14 05:31:52 PM PDT 24
Finished Aug 14 05:32:02 PM PDT 24
Peak memory 250828 kb
Host smart-b0b516f5-3f07-4c04-84f9-54bd82eeee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113631099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.4113631099
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1741418281
Short name T172
Test name
Test status
Simulation time 689516827 ps
CPU time 23.68 seconds
Started Aug 14 05:31:54 PM PDT 24
Finished Aug 14 05:32:18 PM PDT 24
Peak memory 242732 kb
Host smart-15b59980-cc7c-4452-a138-c6f004b8bb5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741418281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1741418281
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3536831395
Short name T176
Test name
Test status
Simulation time 20913549 ps
CPU time 1.11 seconds
Started Aug 14 05:31:49 PM PDT 24
Finished Aug 14 05:31:51 PM PDT 24
Peak memory 213056 kb
Host smart-9da47f29-a336-4ae6-8860-836854a0ac26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536831395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3536831395
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1803537722
Short name T208
Test name
Test status
Simulation time 16979546 ps
CPU time 0.88 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:29:52 PM PDT 24
Peak memory 208772 kb
Host smart-7d8640c4-2c84-4814-9808-669817bb7bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803537722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1803537722
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3713064539
Short name T510
Test name
Test status
Simulation time 223076976 ps
CPU time 10.89 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 226096 kb
Host smart-3ec678c9-5706-434f-a7f0-92e18ac94ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713064539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3713064539
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2629975987
Short name T606
Test name
Test status
Simulation time 2852546371 ps
CPU time 5 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:29:56 PM PDT 24
Peak memory 217332 kb
Host smart-dbaf9468-d06f-4651-9a68-473b77f496c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629975987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2629975987
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2736210314
Short name T692
Test name
Test status
Simulation time 6982275409 ps
CPU time 29.75 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:20 PM PDT 24
Peak memory 218680 kb
Host smart-20c74485-c86b-4545-b7b0-7176e859dd3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736210314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2736210314
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.63430086
Short name T370
Test name
Test status
Simulation time 628003791 ps
CPU time 7.66 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:29:56 PM PDT 24
Peak memory 217680 kb
Host smart-57c805c4-c3d1-469c-8cce-024b2e80bca0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63430086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.63430086
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3822080823
Short name T338
Test name
Test status
Simulation time 1064976694 ps
CPU time 6.33 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:29:58 PM PDT 24
Peak memory 221772 kb
Host smart-3ef596bc-16c6-45ab-863c-612439898fb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822080823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3822080823
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.990847098
Short name T764
Test name
Test status
Simulation time 5807931892 ps
CPU time 40.55 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:30:31 PM PDT 24
Peak memory 217632 kb
Host smart-06af9c63-50b5-4a8f-b286-d6401410014d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990847098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.990847098
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3492229428
Short name T694
Test name
Test status
Simulation time 1034593434 ps
CPU time 5.52 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:29:56 PM PDT 24
Peak memory 217548 kb
Host smart-04ce426d-aba3-4e1a-aebf-82a9c789e13b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492229428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3492229428
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4028309415
Short name T412
Test name
Test status
Simulation time 1284384767 ps
CPU time 41.63 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:32 PM PDT 24
Peak memory 267172 kb
Host smart-8355c7bf-b021-485c-8447-0ae476cfd9a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028309415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.4028309415
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3763012019
Short name T576
Test name
Test status
Simulation time 574473170 ps
CPU time 12.74 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 250740 kb
Host smart-003c0df3-efee-43e6-99b5-9bbe5a8e2fc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763012019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3763012019
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2631263823
Short name T394
Test name
Test status
Simulation time 85076424 ps
CPU time 4.05 seconds
Started Aug 14 05:29:49 PM PDT 24
Finished Aug 14 05:29:53 PM PDT 24
Peak memory 218288 kb
Host smart-5a049475-3bd9-48f6-ab65-aef7406e9641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631263823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2631263823
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3221977978
Short name T488
Test name
Test status
Simulation time 353393925 ps
CPU time 20.61 seconds
Started Aug 14 05:29:47 PM PDT 24
Finished Aug 14 05:30:08 PM PDT 24
Peak memory 217652 kb
Host smart-61438bad-cae0-48fb-8403-59d698a9dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221977978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3221977978
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1830237907
Short name T757
Test name
Test status
Simulation time 1012374498 ps
CPU time 13.17 seconds
Started Aug 14 05:29:46 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 226012 kb
Host smart-1f8e499f-e746-4287-a336-235804d731f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830237907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1830237907
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1680281258
Short name T701
Test name
Test status
Simulation time 1435866314 ps
CPU time 12.55 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 226016 kb
Host smart-66a1b6a4-9fc4-4c72-b8f8-021fbf08c3be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680281258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1680281258
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2440283234
Short name T541
Test name
Test status
Simulation time 210186386 ps
CPU time 8.4 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:29:59 PM PDT 24
Peak memory 218244 kb
Host smart-96c06169-b172-4091-aa01-8800c046e908
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440283234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
440283234
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4098231469
Short name T684
Test name
Test status
Simulation time 1905814188 ps
CPU time 6.22 seconds
Started Aug 14 05:29:47 PM PDT 24
Finished Aug 14 05:29:53 PM PDT 24
Peak memory 218344 kb
Host smart-84a7a4ab-ebaf-42ff-a3b5-b83773eedf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098231469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4098231469
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4170136618
Short name T421
Test name
Test status
Simulation time 155799241 ps
CPU time 6.73 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:29:54 PM PDT 24
Peak memory 217652 kb
Host smart-c0863390-871d-427b-b351-273d68b4e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170136618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4170136618
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3621279605
Short name T419
Test name
Test status
Simulation time 253121934 ps
CPU time 25.23 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 250912 kb
Host smart-7a52d49e-cf5d-49fb-9986-cfaeac4cde58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621279605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3621279605
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1564352003
Short name T769
Test name
Test status
Simulation time 491388069 ps
CPU time 3.8 seconds
Started Aug 14 05:29:47 PM PDT 24
Finished Aug 14 05:29:51 PM PDT 24
Peak memory 226388 kb
Host smart-603e149a-1d72-405a-8b27-efa30f1ecb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564352003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1564352003
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1530174327
Short name T460
Test name
Test status
Simulation time 12790575683 ps
CPU time 112.82 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:31:43 PM PDT 24
Peak memory 272304 kb
Host smart-4bb25e9a-db0b-4563-a262-a8620a76c507
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530174327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1530174327
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2976545929
Short name T334
Test name
Test status
Simulation time 46977241 ps
CPU time 0.99 seconds
Started Aug 14 05:29:47 PM PDT 24
Finished Aug 14 05:29:48 PM PDT 24
Peak memory 211808 kb
Host smart-357295b1-8732-4431-a809-9d8ce9a91dbd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976545929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2976545929
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1661810346
Short name T534
Test name
Test status
Simulation time 12030845 ps
CPU time 0.84 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 208688 kb
Host smart-011e94f0-84e1-42ba-9ce7-32e443455374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661810346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1661810346
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.4028966038
Short name T298
Test name
Test status
Simulation time 13493968 ps
CPU time 0.85 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:29:51 PM PDT 24
Peak memory 208576 kb
Host smart-9b2d3810-d7d3-4c89-9cf6-309633e3a7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028966038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.4028966038
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4078578968
Short name T643
Test name
Test status
Simulation time 289510187 ps
CPU time 14.59 seconds
Started Aug 14 05:29:49 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 218296 kb
Host smart-5b40ef5b-b352-4025-95ff-f15d40ed9d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078578968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4078578968
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2739570468
Short name T25
Test name
Test status
Simulation time 401626996 ps
CPU time 10.51 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 217084 kb
Host smart-d1614f6f-ce74-447e-8eba-d1220e91839b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739570468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2739570468
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3685235751
Short name T522
Test name
Test status
Simulation time 1647577239 ps
CPU time 52.39 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:42 PM PDT 24
Peak memory 218868 kb
Host smart-2d1e2058-44f6-4bab-ad53-00b32b77e97b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685235751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3685235751
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.928172583
Short name T871
Test name
Test status
Simulation time 395056772 ps
CPU time 3.29 seconds
Started Aug 14 05:29:47 PM PDT 24
Finished Aug 14 05:29:50 PM PDT 24
Peak memory 217672 kb
Host smart-74024eb2-b7dc-4812-9139-8f793094fe8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928172583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.928172583
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3978840786
Short name T714
Test name
Test status
Simulation time 205170542 ps
CPU time 1.88 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:29:53 PM PDT 24
Peak memory 218176 kb
Host smart-8c59c22e-ae43-44b4-b071-867748a1c826
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978840786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3978840786
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1226240988
Short name T399
Test name
Test status
Simulation time 3183932025 ps
CPU time 12 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 217640 kb
Host smart-c447d4c6-0934-4a9f-ac42-5616d8b1658e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226240988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1226240988
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1456212110
Short name T438
Test name
Test status
Simulation time 412834034 ps
CPU time 2.78 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:29:51 PM PDT 24
Peak memory 217580 kb
Host smart-0970de94-a891-42b9-9ade-98fd55c2459d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456212110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1456212110
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1270457187
Short name T107
Test name
Test status
Simulation time 3112023963 ps
CPU time 30.62 seconds
Started Aug 14 05:29:49 PM PDT 24
Finished Aug 14 05:30:19 PM PDT 24
Peak memory 250920 kb
Host smart-0b517f08-e054-4de3-b529-d70a868f7cd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270457187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1270457187
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1092884470
Short name T760
Test name
Test status
Simulation time 8288570169 ps
CPU time 15.37 seconds
Started Aug 14 05:29:49 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 248108 kb
Host smart-54b9828d-955c-406e-ac6a-a8525213f96c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092884470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1092884470
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3853147616
Short name T167
Test name
Test status
Simulation time 241037300 ps
CPU time 3.29 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:29:53 PM PDT 24
Peak memory 222716 kb
Host smart-5ff5281c-7c44-497a-9ef0-ec7e48fac171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853147616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3853147616
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3951264338
Short name T3
Test name
Test status
Simulation time 493006424 ps
CPU time 11.21 seconds
Started Aug 14 05:29:53 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 217656 kb
Host smart-8dab57ef-50ce-4d30-bdec-b3a5de221e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951264338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3951264338
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.210779595
Short name T634
Test name
Test status
Simulation time 3177707228 ps
CPU time 7.8 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:29:56 PM PDT 24
Peak memory 226268 kb
Host smart-3abc473f-9524-44db-95c2-7845972a91fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210779595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.210779595
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1805266474
Short name T827
Test name
Test status
Simulation time 2053577796 ps
CPU time 12.94 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 226020 kb
Host smart-478c2f8a-f832-4990-b956-3a15e6a48303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805266474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1805266474
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4121494867
Short name T603
Test name
Test status
Simulation time 982286681 ps
CPU time 10.6 seconds
Started Aug 14 05:29:49 PM PDT 24
Finished Aug 14 05:29:59 PM PDT 24
Peak memory 218244 kb
Host smart-bd554c56-c3d0-4704-9e34-8dea5e9c4453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121494867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
121494867
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3459158984
Short name T444
Test name
Test status
Simulation time 512164624 ps
CPU time 9.86 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 225332 kb
Host smart-196fc14f-733d-41d4-96b9-5d4a50fc1f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459158984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3459158984
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.406070897
Short name T401
Test name
Test status
Simulation time 519002836 ps
CPU time 2.64 seconds
Started Aug 14 05:29:50 PM PDT 24
Finished Aug 14 05:29:52 PM PDT 24
Peak memory 217656 kb
Host smart-dcb6f793-b8d6-4448-a5ec-dc4c06d87a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406070897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.406070897
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.489910822
Short name T287
Test name
Test status
Simulation time 236742633 ps
CPU time 20.38 seconds
Started Aug 14 05:29:48 PM PDT 24
Finished Aug 14 05:30:08 PM PDT 24
Peak memory 245816 kb
Host smart-e5bd1fd3-c3c4-4da6-a69c-e6ab1bc01c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489910822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.489910822
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2344507154
Short name T258
Test name
Test status
Simulation time 57114971 ps
CPU time 7.33 seconds
Started Aug 14 05:29:49 PM PDT 24
Finished Aug 14 05:29:56 PM PDT 24
Peak memory 250916 kb
Host smart-27cd8cdf-1111-42e2-b108-f779fe58c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344507154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2344507154
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1999617584
Short name T677
Test name
Test status
Simulation time 2072863038 ps
CPU time 63.56 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:30:55 PM PDT 24
Peak memory 275680 kb
Host smart-b43d7c58-16a2-4896-bead-5b7069df6f45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999617584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1999617584
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4041846633
Short name T393
Test name
Test status
Simulation time 30262162 ps
CPU time 0.97 seconds
Started Aug 14 05:29:51 PM PDT 24
Finished Aug 14 05:29:52 PM PDT 24
Peak memory 212980 kb
Host smart-83813437-3276-4065-819d-cdd31329929b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041846633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4041846633
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3508181187
Short name T376
Test name
Test status
Simulation time 14919365 ps
CPU time 0.85 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 208820 kb
Host smart-a4e378d4-d359-401a-b8a4-01574ef9de2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508181187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3508181187
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3311412909
Short name T207
Test name
Test status
Simulation time 33283395 ps
CPU time 0.79 seconds
Started Aug 14 05:29:58 PM PDT 24
Finished Aug 14 05:29:59 PM PDT 24
Peak memory 208872 kb
Host smart-722c3a1f-614a-4086-afb9-45a2252b26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311412909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3311412909
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2712099405
Short name T505
Test name
Test status
Simulation time 1673927315 ps
CPU time 19.83 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:20 PM PDT 24
Peak memory 218272 kb
Host smart-a2f965ea-81da-4bbd-b925-f9d06f3ccaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712099405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2712099405
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.652318854
Short name T852
Test name
Test status
Simulation time 7282349759 ps
CPU time 8.96 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:30:08 PM PDT 24
Peak memory 217716 kb
Host smart-027959c0-e5aa-47ac-9d66-bb29f1208846
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652318854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.652318854
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2701849078
Short name T426
Test name
Test status
Simulation time 3422406762 ps
CPU time 29.7 seconds
Started Aug 14 05:30:02 PM PDT 24
Finished Aug 14 05:30:31 PM PDT 24
Peak memory 219016 kb
Host smart-abbb68ab-58cf-46d7-ba1c-4522cda678a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701849078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2701849078
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3067354183
Short name T182
Test name
Test status
Simulation time 268344885 ps
CPU time 7.84 seconds
Started Aug 14 05:30:02 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 217724 kb
Host smart-64510c82-674e-40bc-b38c-eda540100972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067354183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
067354183
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2487279589
Short name T638
Test name
Test status
Simulation time 260979888 ps
CPU time 8.87 seconds
Started Aug 14 05:30:04 PM PDT 24
Finished Aug 14 05:30:13 PM PDT 24
Peak memory 223168 kb
Host smart-393ce012-ea63-400a-86df-bfe7c171d896
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487279589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2487279589
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2309178341
Short name T558
Test name
Test status
Simulation time 2940618001 ps
CPU time 15.7 seconds
Started Aug 14 05:29:58 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 217652 kb
Host smart-e544568a-c8a6-4ace-a1f8-6b45c880644d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309178341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2309178341
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3610244185
Short name T432
Test name
Test status
Simulation time 189360678 ps
CPU time 2.78 seconds
Started Aug 14 05:29:58 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 217576 kb
Host smart-ba97e930-be61-4ecd-a8e1-10723018a581
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610244185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3610244185
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1602475053
Short name T664
Test name
Test status
Simulation time 1117101667 ps
CPU time 52.25 seconds
Started Aug 14 05:30:04 PM PDT 24
Finished Aug 14 05:30:56 PM PDT 24
Peak memory 283636 kb
Host smart-e09e0b52-2f93-44cd-821c-bd1abf1313d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602475053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1602475053
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1795791308
Short name T570
Test name
Test status
Simulation time 622976539 ps
CPU time 13.86 seconds
Started Aug 14 05:29:57 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 249992 kb
Host smart-715b06ee-2de6-48aa-85e9-1e43ee913dd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795791308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1795791308
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2694175009
Short name T823
Test name
Test status
Simulation time 76656721 ps
CPU time 1.77 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:02 PM PDT 24
Peak memory 218204 kb
Host smart-f1343a04-a377-440d-a0d7-0db84eb6adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694175009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2694175009
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2419206159
Short name T430
Test name
Test status
Simulation time 1470279610 ps
CPU time 11.39 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:13 PM PDT 24
Peak memory 217640 kb
Host smart-273e2a78-0eb9-4b9b-af23-8e91d296c885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419206159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2419206159
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2808000225
Short name T386
Test name
Test status
Simulation time 5876862767 ps
CPU time 15.65 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 219836 kb
Host smart-04802364-bc96-4545-ac3a-18d8c3eca0fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808000225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2808000225
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.4029115251
Short name T259
Test name
Test status
Simulation time 208900225 ps
CPU time 8.85 seconds
Started Aug 14 05:30:03 PM PDT 24
Finished Aug 14 05:30:12 PM PDT 24
Peak memory 225836 kb
Host smart-1931cdda-ef8c-45db-b006-0113e3eae8bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029115251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.4029115251
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2979303026
Short name T669
Test name
Test status
Simulation time 1647992655 ps
CPU time 10.71 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 218368 kb
Host smart-9e0ad835-1921-4ad6-98cb-414bb1376b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979303026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2979303026
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.211418311
Short name T721
Test name
Test status
Simulation time 121412304 ps
CPU time 1.59 seconds
Started Aug 14 05:30:02 PM PDT 24
Finished Aug 14 05:30:04 PM PDT 24
Peak memory 213592 kb
Host smart-3fe6eae0-41d9-4546-95cb-c96ded1548d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211418311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.211418311
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2083852662
Short name T354
Test name
Test status
Simulation time 186175165 ps
CPU time 22.16 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:23 PM PDT 24
Peak memory 250924 kb
Host smart-dc3c54fe-28c5-479a-87aa-75188fed3242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083852662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2083852662
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3203734970
Short name T588
Test name
Test status
Simulation time 270391747 ps
CPU time 6.8 seconds
Started Aug 14 05:30:04 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 250240 kb
Host smart-26540a8f-f194-4125-84cb-c4ce34e86bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203734970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3203734970
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3629344377
Short name T666
Test name
Test status
Simulation time 20392864842 ps
CPU time 163.99 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 283740 kb
Host smart-f633b59d-5fcb-4340-9bf6-7f5b52849818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629344377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3629344377
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3638986688
Short name T231
Test name
Test status
Simulation time 24782490 ps
CPU time 0.9 seconds
Started Aug 14 05:30:02 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 211888 kb
Host smart-52190256-e263-4739-98fa-29d51977b25e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638986688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3638986688
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1622141856
Short name T391
Test name
Test status
Simulation time 21095867 ps
CPU time 1.02 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 208968 kb
Host smart-ddde5189-acd2-443d-a482-3bb4e6f22802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622141856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1622141856
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.513870148
Short name T429
Test name
Test status
Simulation time 11040858 ps
CPU time 0.82 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:02 PM PDT 24
Peak memory 208944 kb
Host smart-5e65e192-a90c-454b-a80a-096b3776b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513870148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.513870148
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3108251988
Short name T404
Test name
Test status
Simulation time 2525848016 ps
CPU time 14.63 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:15 PM PDT 24
Peak memory 219080 kb
Host smart-d295a52c-5632-4d87-b7f2-d56ec4d13f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108251988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3108251988
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2438473047
Short name T458
Test name
Test status
Simulation time 631168018 ps
CPU time 8.69 seconds
Started Aug 14 05:30:02 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 217180 kb
Host smart-ee75aa62-3f04-4afe-b616-6adeb613af5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438473047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2438473047
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2167507398
Short name T381
Test name
Test status
Simulation time 1752033704 ps
CPU time 25.18 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:30:24 PM PDT 24
Peak memory 218196 kb
Host smart-257f6a14-6355-4bb1-b534-2595ae55a915
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167507398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2167507398
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1705944208
Short name T743
Test name
Test status
Simulation time 855528612 ps
CPU time 5.02 seconds
Started Aug 14 05:29:56 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 217716 kb
Host smart-cd6cd978-55d6-43a7-b056-f9ad7cd4f2dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705944208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
705944208
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3723888824
Short name T583
Test name
Test status
Simulation time 765761282 ps
CPU time 6.36 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:08 PM PDT 24
Peak memory 221884 kb
Host smart-9732c567-3a80-4400-94fd-ebb1f1abfc4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723888824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3723888824
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3338654651
Short name T698
Test name
Test status
Simulation time 4316524028 ps
CPU time 14.25 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 217652 kb
Host smart-61598904-aa59-4d0c-9c39-6e50863ffe17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338654651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3338654651
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.988455205
Short name T268
Test name
Test status
Simulation time 127658443 ps
CPU time 2.35 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:04 PM PDT 24
Peak memory 217588 kb
Host smart-8ac8918b-8795-4205-8693-ab6c34bb8a03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988455205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.988455205
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1844455546
Short name T174
Test name
Test status
Simulation time 1314680211 ps
CPU time 50.62 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:30:49 PM PDT 24
Peak memory 275484 kb
Host smart-70208636-acd8-426e-ad31-0ce203f6bd52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844455546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1844455546
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3672878765
Short name T813
Test name
Test status
Simulation time 3048235791 ps
CPU time 12.63 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 226340 kb
Host smart-8b35988a-78c9-4a04-b576-3d83fa1573ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672878765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3672878765
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3939259962
Short name T239
Test name
Test status
Simulation time 74158878 ps
CPU time 2.11 seconds
Started Aug 14 05:30:03 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 222344 kb
Host smart-2518ede1-5778-4b0e-81d7-b21d7b01cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939259962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3939259962
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.463290694
Short name T97
Test name
Test status
Simulation time 190085415 ps
CPU time 10.72 seconds
Started Aug 14 05:30:03 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 214332 kb
Host smart-006c376f-1694-4ada-83b4-63b193a62c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463290694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.463290694
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.633572485
Short name T440
Test name
Test status
Simulation time 228815750 ps
CPU time 10.57 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:12 PM PDT 24
Peak memory 218316 kb
Host smart-a735ba5c-3386-49cb-acaa-dd6d2ec36707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633572485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.633572485
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3728861062
Short name T703
Test name
Test status
Simulation time 2707709060 ps
CPU time 10.14 seconds
Started Aug 14 05:29:58 PM PDT 24
Finished Aug 14 05:30:08 PM PDT 24
Peak memory 226052 kb
Host smart-a1977b3e-b849-4019-a9e8-3477af1a985a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728861062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3728861062
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.231328499
Short name T472
Test name
Test status
Simulation time 430455902 ps
CPU time 5.27 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:07 PM PDT 24
Peak memory 224440 kb
Host smart-9f43fe1a-8705-48d7-8148-a564a897be5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231328499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.231328499
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.385095513
Short name T543
Test name
Test status
Simulation time 325236340 ps
CPU time 12.41 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 218364 kb
Host smart-36c8e193-18a7-4849-8529-de45cbbef36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385095513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.385095513
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3334844881
Short name T410
Test name
Test status
Simulation time 200518995 ps
CPU time 3.85 seconds
Started Aug 14 05:30:04 PM PDT 24
Finished Aug 14 05:30:08 PM PDT 24
Peak memory 214616 kb
Host smart-71453d2c-4d73-40c5-8489-62fda6d15d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334844881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3334844881
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.207994306
Short name T162
Test name
Test status
Simulation time 1540122722 ps
CPU time 34.1 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:35 PM PDT 24
Peak memory 250928 kb
Host smart-13d2e142-fcad-4df7-a46d-1650d2146876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207994306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.207994306
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3708617536
Short name T256
Test name
Test status
Simulation time 81793355 ps
CPU time 7.24 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:07 PM PDT 24
Peak memory 250924 kb
Host smart-99513705-2aec-465a-9973-f9fc7f35c756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708617536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3708617536
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2447456214
Short name T501
Test name
Test status
Simulation time 2978149624 ps
CPU time 93.15 seconds
Started Aug 14 05:29:59 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 276908 kb
Host smart-2de32e84-de3e-4ed1-9376-62241a26f697
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447456214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2447456214
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2354773025
Short name T145
Test name
Test status
Simulation time 770832125 ps
CPU time 32.26 seconds
Started Aug 14 05:30:02 PM PDT 24
Finished Aug 14 05:30:35 PM PDT 24
Peak memory 225884 kb
Host smart-a12d6a9e-14c7-4cb1-aec9-3d9b0fff79e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2354773025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2354773025
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2351326039
Short name T484
Test name
Test status
Simulation time 31804824 ps
CPU time 0.85 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 212016 kb
Host smart-3964b464-d4c2-45ef-8a47-3bf26cd61f27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351326039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2351326039
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.147952023
Short name T674
Test name
Test status
Simulation time 35875049 ps
CPU time 1.17 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 208940 kb
Host smart-aa3cd72e-34b7-42c5-9af9-0f2e32e5ad9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147952023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.147952023
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3462973665
Short name T387
Test name
Test status
Simulation time 26913350 ps
CPU time 0.81 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:30:09 PM PDT 24
Peak memory 208960 kb
Host smart-342ac91b-0883-49dd-989c-65156baa4af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462973665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3462973665
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2511698614
Short name T35
Test name
Test status
Simulation time 775929072 ps
CPU time 12.33 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:13 PM PDT 24
Peak memory 218256 kb
Host smart-72a9861c-5cb5-4077-92cc-6a14ac3ab5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511698614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2511698614
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1791949000
Short name T284
Test name
Test status
Simulation time 655949846 ps
CPU time 4.92 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 217356 kb
Host smart-bc8d8a94-6f8e-4094-9385-356361082602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791949000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1791949000
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.330093299
Short name T830
Test name
Test status
Simulation time 8815589756 ps
CPU time 60.32 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:31:08 PM PDT 24
Peak memory 218944 kb
Host smart-355c34c4-2eb2-41ab-b9dc-63fdc1da07f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330093299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.330093299
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2471136846
Short name T105
Test name
Test status
Simulation time 727833358 ps
CPU time 5.1 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 217664 kb
Host smart-0e392aa9-8fa5-4c58-806d-087985e437f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471136846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
471136846
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1519556121
Short name T152
Test name
Test status
Simulation time 341506326 ps
CPU time 6.32 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 223160 kb
Host smart-733fd8c7-9fb5-4916-8496-78e0081b9db4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519556121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1519556121
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2361505069
Short name T766
Test name
Test status
Simulation time 786587650 ps
CPU time 14.67 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:24 PM PDT 24
Peak memory 217592 kb
Host smart-2f3bef54-ba53-4411-858d-f564c18d00ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361505069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2361505069
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3839739754
Short name T66
Test name
Test status
Simulation time 78554694 ps
CPU time 2.55 seconds
Started Aug 14 05:30:07 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 217632 kb
Host smart-7c682de3-7d74-45c7-aafd-386f10423a52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839739754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3839739754
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.255106149
Short name T294
Test name
Test status
Simulation time 6358575342 ps
CPU time 63.95 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:31:13 PM PDT 24
Peak memory 278792 kb
Host smart-75f0b867-23c0-4d85-8eb8-f4735e26bfb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255106149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.255106149
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2093799116
Short name T332
Test name
Test status
Simulation time 1643151770 ps
CPU time 16.17 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:26 PM PDT 24
Peak memory 245760 kb
Host smart-edd40b05-1a26-4d4b-9fb4-ae06fe50a6e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093799116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2093799116
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.952017585
Short name T223
Test name
Test status
Simulation time 96589901 ps
CPU time 3.22 seconds
Started Aug 14 05:30:00 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 222640 kb
Host smart-1fbe8fd2-c715-4c43-bfdf-20ae20367e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952017585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.952017585
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1071198426
Short name T696
Test name
Test status
Simulation time 972097028 ps
CPU time 9.71 seconds
Started Aug 14 05:30:05 PM PDT 24
Finished Aug 14 05:30:15 PM PDT 24
Peak memory 214432 kb
Host smart-7784f2de-742c-4b1f-83ce-f3e344cc822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071198426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1071198426
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.4268057169
Short name T490
Test name
Test status
Simulation time 851460837 ps
CPU time 18.61 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 226100 kb
Host smart-c34983a6-52c0-4e48-ade6-ee49e3572294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268057169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.4268057169
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2133151579
Short name T439
Test name
Test status
Simulation time 552271705 ps
CPU time 8.22 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 226004 kb
Host smart-c298da2e-5275-4afd-9bc1-ecbbbd37dfeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133151579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2133151579
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2730444651
Short name T870
Test name
Test status
Simulation time 1242058343 ps
CPU time 8.56 seconds
Started Aug 14 05:30:09 PM PDT 24
Finished Aug 14 05:30:18 PM PDT 24
Peak memory 226016 kb
Host smart-10029033-22ce-47db-821e-bf9ade809c54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730444651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
730444651
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.197009848
Short name T269
Test name
Test status
Simulation time 203384098 ps
CPU time 9.33 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 218376 kb
Host smart-5c0cb60e-197e-4041-811e-b93efc2ba667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197009848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.197009848
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.56495496
Short name T591
Test name
Test status
Simulation time 223916012 ps
CPU time 2.52 seconds
Started Aug 14 05:30:04 PM PDT 24
Finished Aug 14 05:30:07 PM PDT 24
Peak memory 213932 kb
Host smart-abbe0489-2249-486b-966d-e06917c8877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56495496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.56495496
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.119244839
Short name T228
Test name
Test status
Simulation time 251480582 ps
CPU time 24.2 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:25 PM PDT 24
Peak memory 250880 kb
Host smart-f244dc25-11a6-45df-bda5-444f59b57e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119244839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.119244839
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1321314596
Short name T729
Test name
Test status
Simulation time 71700041 ps
CPU time 7.6 seconds
Started Aug 14 05:30:03 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 250912 kb
Host smart-dfbfa46f-6582-4d14-b01d-bc8ddc122930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321314596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1321314596
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2377293228
Short name T424
Test name
Test status
Simulation time 30633495796 ps
CPU time 111.54 seconds
Started Aug 14 05:30:08 PM PDT 24
Finished Aug 14 05:32:00 PM PDT 24
Peak memory 252404 kb
Host smart-9f85ecab-30ed-4705-a9df-8f4011ba35dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377293228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2377293228
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2428987839
Short name T423
Test name
Test status
Simulation time 63239944 ps
CPU time 1.01 seconds
Started Aug 14 05:30:01 PM PDT 24
Finished Aug 14 05:30:02 PM PDT 24
Peak memory 212992 kb
Host smart-47b2336a-6210-4a4e-a015-8deeb6230a8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428987839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2428987839
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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