Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60866603

1

T1

12732

T2

22028

T3

1105

auto[1]

1161880

1

T1

8182

T2

9877

T12

1188

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60882627

1

T1

15848

T2

22406

T3

1105

auto[1]

1145856

1

T1

5066

T2

9499

T4

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5545105	1			T1	4807		T2	7077		T3	110
auto[IdleSt]	14775530	1			T1	5021		T2	5977		T3	16
auto[ClkMuxSt]	27960	1			T1	46		T2	69		T3	1
auto[CntIncrSt]	27818	1			T1	46		T2	68		T3	1
auto[CntProgSt]	1330267	1			T1	90		T2	667		T3	2
auto[TransCheckSt]	22089	1			T1	42		T2	38		T3	1
auto[TokenHashSt]	18932845	1			T1	870		T2	2439		T3	121
auto[FlashRmaSt]	29354	1			T1	87		T2	128		T12	169
auto[TokenCheck0St]	9882	1			T1	18		T2	25		T12	37
auto[TokenCheck1St]	7090	1			T1	17		T2	22		T12	14
auto[TransProgSt]	338786	1			T1	31		T2	77		T12	136
auto[PostTransSt]	8063552	1			T1	14		T2	5		T3	853
auto[ScrapSt]	100120	1			T1	8		T27	2316		T36	838
auto[EscalateSt]	4846348	1			T1	9817		T2	15313		T4	400
auto[InvalidSt]	7970285	1			T12	2575		T13	853		T19	3396

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1452	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7970285	1			T12	2575		T13	853		T19	3396
EscalateSt	4846348	1			T1	9817		T2	15313		T4	400
ScrapSt	100120	1			T1	8		T27	2316		T36	838
PostTransSt	8063552	1			T1	14		T2	5		T3	853
TransProgSt	338786	1			T1	31		T2	77		T12	136
TokenCheck1St	7090	1			T1	17		T2	22		T12	14
TokenCheck0St	9882	1			T1	18		T2	25		T12	37
FlashRmaSt	29354	1			T1	87		T2	128		T12	169
TokenHashSt	18932845	1			T1	870		T2	2439		T3	121
TransCheckSt	22089	1			T1	42		T2	38		T3	1
CntProgSt	1330267	1			T1	90		T2	667		T3	2
CntIncrSt	27818	1			T1	46		T2	68		T3	1
ClkMuxSt	27960	1			T1	46		T2	69		T3	1
IdleSt	14775530	1			T1	5021		T2	5977		T3	16
ResetSt	5545105	1			T1	4807		T2	7077		T3	110
arcs[ResetSt=>IdleSt]	42003	1			T1	50		T2	75		T3	1
arcs[IdleSt=>ScrapSt]	240	1			T1	2		T27	1		T36	1
arcs[IdleSt=>ClkMuxSt]	27852	1			T1	46		T2	69		T3	1
arcs[ClkMuxSt=>CntIncrSt]	27818	1			T1	46		T2	68		T3	1
arcs[CntIncrSt=>PostTransSt]	1166	1			T6	8		T14	12		T15	12
arcs[CntIncrSt=>CntProgSt]	26585	1			T1	46		T2	66		T3	1
arcs[CntProgSt=>PostTransSt]	3479	1			T4	3		T12	17		T6	13
arcs[CntProgSt=>TransCheckSt]	22089	1			T1	42		T2	38		T3	1
arcs[TransCheckSt=>PostTransSt]	3022	1			T6	8		T18	43		T14	8
arcs[TransCheckSt=>TokenHashSt]	18922	1			T1	38		T2	38		T3	1
arcs[TokenHashSt=>PostTransSt]	8147	1			T3	1		T11	1		T12	7
arcs[TokenHashSt=>FlashRmaSt]	9929	1			T1	19		T2	27		T12	37
arcs[FlashRmaSt=>TokenCheck0St]	9882	1			T1	18		T2	25		T12	37
arcs[TokenCheck0St=>PostTransSt]	2740	1			T12	23		T6	5		T13	10
arcs[TokenCheck0St=>TokenCheck1St]	7090	1			T1	17		T2	22		T12	14
arcs[TokenCheck1St=>PostTransSt]	547	1			T12	1		T6	1		T18	16
arcs[TransProgSt=>PostTransSt]	5757	1			T1	8		T2	3		T12	13
arcs[IdleSt=>EscalateSt]	158	1			T1	1		T2	5		T46	5
arcs[ClkMuxSt=>EscalateSt]	34	1			T2	1		T46	1		T47	2
arcs[CntIncrSt=>EscalateSt]	67	1			T2	2		T21	1		T48	2
arcs[CntProgSt=>EscalateSt]	1017	1			T1	4		T2	28		T21	5
arcs[TransCheckSt=>EscalateSt]	145	1			T1	4		T21	6		T46	6
arcs[TokenHashSt=>EscalateSt]	846	1			T1	19		T2	11		T21	27
arcs[FlashRmaSt=>EscalateSt]	47	1			T1	1		T2	2		T21	2
arcs[TokenCheck0St=>EscalateSt]	52	1			T1	1		T2	3		T21	1
arcs[TokenCheck1St=>EscalateSt]	33	1			T51	1		T48	1		T52	2
arcs[TransProgSt=>EscalateSt]	753	1			T1	9		T2	19		T21	6
arcs[PostTransSt=>EscalateSt]	3868	1			T1	8		T2	3		T4	3
arcs[InvalidSt=>EscalateSt]	10300	1			T12	13		T13	11		T19	18

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5544923	1			T1	4805		T2	7074		T3	110
auto[0]	auto[IdleSt]	14775422	1			T1	5020		T2	5973		T3	16
auto[0]	auto[ClkMuxSt]	27935	1			T1	46		T2	68		T3	1
auto[0]	auto[CntIncrSt]	27776	1			T1	46		T2	66		T3	1
auto[0]	auto[CntProgSt]	1329568	1			T1	86		T2	649		T3	2
auto[0]	auto[TransCheckSt]	21991	1			T1	38		T2	38		T3	1
auto[0]	auto[TokenHashSt]	18932276	1			T1	854		T2	2432		T3	121
auto[0]	auto[FlashRmaSt]	29324	1			T1	86		T2	127		T12	169
auto[0]	auto[TokenCheck0St]	9851	1			T1	18		T2	23		T12	37
auto[0]	auto[TokenCheck1St]	7067	1			T1	17		T2	22		T12	14
auto[0]	auto[TransProgSt]	338266	1			T1	24		T2	67		T12	136
auto[0]	auto[PostTransSt]	8061516	1			T1	9		T2	2		T3	853
auto[0]	auto[ScrapSt]	100062	1			T1	7		T27	2316		T36	838
auto[0]	auto[EscalateSt]	3694036	1			T1	1676		T2	5487		T4	400
auto[0]	auto[InvalidSt]	7965138	1			T12	2569		T13	845		T19	3385
auto[1]	auto[ResetSt]	182	1			T1	2		T2	3		T21	4
auto[1]	auto[IdleSt]	108	1			T1	1		T2	4		T46	2
auto[1]	auto[ClkMuxSt]	25	1			T2	1		T46	1		T47	2
auto[1]	auto[CntIncrSt]	42	1			T2	2		T48	2		T198	4
auto[1]	auto[CntProgSt]	699	1			T1	4		T2	18		T21	3
auto[1]	auto[TransCheckSt]	98	1			T1	4		T21	5		T46	5
auto[1]	auto[TokenHashSt]	569	1			T1	16		T2	7		T21	18
auto[1]	auto[FlashRmaSt]	30	1			T1	1		T2	1		T51	1
auto[1]	auto[TokenCheck0St]	31	1			T2	2		T21	1		T51	1
auto[1]	auto[TokenCheck1St]	23	1			T51	1		T48	1		T52	1
auto[1]	auto[TransProgSt]	520	1			T1	7		T2	10		T21	4
auto[1]	auto[PostTransSt]	2036	1			T1	5		T2	3		T12	6
auto[1]	auto[ScrapSt]	58	1			T1	1		T21	2		T46	2
auto[1]	auto[EscalateSt]	1152312	1			T1	8141		T2	9826		T12	1176
auto[1]	auto[InvalidSt]	5147	1			T12	6		T13	8		T19	11

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5544917	1			T1	4807		T2	7074		T3	110
auto[0]	auto[IdleSt]	14775426	1			T1	5020		T2	5974		T3	16
auto[0]	auto[ClkMuxSt]	27938	1			T1	46		T2	69		T3	1
auto[0]	auto[CntIncrSt]	27765	1			T1	46		T2	66		T3	1
auto[0]	auto[CntProgSt]	1329595	1			T1	88		T2	649		T3	2
auto[0]	auto[TransCheckSt]	21987	1			T1	39		T2	38		T3	1
auto[0]	auto[TokenHashSt]	18932292	1			T1	859		T2	2433		T3	121
auto[0]	auto[FlashRmaSt]	29318	1			T1	87		T2	127		T12	169
auto[0]	auto[TokenCheck0St]	9846	1			T1	17		T2	22		T12	37
auto[0]	auto[TokenCheck1St]	7070	1			T1	17		T2	22		T12	14
auto[0]	auto[TransProgSt]	338297	1			T1	28		T2	65		T12	136
auto[0]	auto[PostTransSt]	8061611	1			T1	9		T2	5		T3	853
auto[0]	auto[ScrapSt]	100071	1			T1	7		T27	2316		T36	838
auto[0]	auto[EscalateSt]	3709910	1			T1	4778		T2	5862		T4	106
auto[0]	auto[InvalidSt]	7965132	1			T12	2568		T13	850		T19	3389
auto[1]	auto[ResetSt]	188	1			T2	3		T21	3		T46	1
auto[1]	auto[IdleSt]	104	1			T1	1		T2	3		T46	3
auto[1]	auto[ClkMuxSt]	22	1			T46	1		T47	1		T52	2
auto[1]	auto[CntIncrSt]	53	1			T2	2		T21	1		T198	2
auto[1]	auto[CntProgSt]	672	1			T1	2		T2	18		T21	5
auto[1]	auto[TransCheckSt]	102	1			T1	3		T21	4		T46	3
auto[1]	auto[TokenHashSt]	553	1			T1	11		T2	6		T21	18
auto[1]	auto[FlashRmaSt]	36	1			T2	1		T21	2		T51	1
auto[1]	auto[TokenCheck0St]	36	1			T1	1		T2	3		T21	1
auto[1]	auto[TokenCheck1St]	20	1			T52	2		T199	1		T200	1
auto[1]	auto[TransProgSt]	489	1			T1	3		T2	12		T21	4
auto[1]	auto[PostTransSt]	1941	1			T1	5		T4	3		T12	11
auto[1]	auto[ScrapSt]	49	1			T1	1		T21	1		T48	2
auto[1]	auto[EscalateSt]	1136438	1			T1	5039		T2	9451		T4	294
auto[1]	auto[InvalidSt]	5153	1			T12	7		T13	3		T19	7