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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.86 97.92 95.93 93.40 97.62 98.52 98.51 96.11


Total test records in report: 1000
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T812 /workspace/coverage/default/18.lc_ctrl_smoke.2448857020 Aug 15 06:06:58 PM PDT 24 Aug 15 06:07:00 PM PDT 24 471969648 ps
T813 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3722669602 Aug 15 06:06:25 PM PDT 24 Aug 15 06:06:55 PM PDT 24 2733294786 ps
T814 /workspace/coverage/default/25.lc_ctrl_state_post_trans.3836011030 Aug 15 06:07:14 PM PDT 24 Aug 15 06:07:24 PM PDT 24 75091617 ps
T815 /workspace/coverage/default/7.lc_ctrl_prog_failure.2886031151 Aug 15 06:06:24 PM PDT 24 Aug 15 06:06:27 PM PDT 24 161642501 ps
T816 /workspace/coverage/default/43.lc_ctrl_prog_failure.3961695972 Aug 15 06:07:40 PM PDT 24 Aug 15 06:07:43 PM PDT 24 46156620 ps
T817 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1122875039 Aug 15 06:07:09 PM PDT 24 Aug 15 06:07:10 PM PDT 24 14000115 ps
T818 /workspace/coverage/default/13.lc_ctrl_jtag_errors.3470493026 Aug 15 06:06:51 PM PDT 24 Aug 15 06:07:25 PM PDT 24 5402551237 ps
T819 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1223498623 Aug 15 06:06:18 PM PDT 24 Aug 15 06:06:24 PM PDT 24 423209918 ps
T820 /workspace/coverage/default/35.lc_ctrl_prog_failure.812597061 Aug 15 06:07:55 PM PDT 24 Aug 15 06:07:59 PM PDT 24 311810656 ps
T821 /workspace/coverage/default/22.lc_ctrl_jtag_access.1996303260 Aug 15 06:07:11 PM PDT 24 Aug 15 06:07:12 PM PDT 24 189949639 ps
T822 /workspace/coverage/default/1.lc_ctrl_state_post_trans.1058516776 Aug 15 06:06:10 PM PDT 24 Aug 15 06:06:17 PM PDT 24 57028754 ps
T823 /workspace/coverage/default/22.lc_ctrl_security_escalation.1121738819 Aug 15 06:07:03 PM PDT 24 Aug 15 06:07:13 PM PDT 24 529892703 ps
T824 /workspace/coverage/default/27.lc_ctrl_state_failure.249327593 Aug 15 06:07:00 PM PDT 24 Aug 15 06:07:30 PM PDT 24 252479325 ps
T825 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1753358915 Aug 15 06:07:10 PM PDT 24 Aug 15 06:07:22 PM PDT 24 1218642629 ps
T826 /workspace/coverage/default/48.lc_ctrl_stress_all.461448746 Aug 15 06:08:04 PM PDT 24 Aug 15 06:08:49 PM PDT 24 1310396280 ps
T827 /workspace/coverage/default/1.lc_ctrl_state_failure.1179229390 Aug 15 06:05:57 PM PDT 24 Aug 15 06:06:27 PM PDT 24 319476145 ps
T828 /workspace/coverage/default/42.lc_ctrl_errors.444434355 Aug 15 06:07:40 PM PDT 24 Aug 15 06:07:54 PM PDT 24 1937659372 ps
T829 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3261384556 Aug 15 06:07:19 PM PDT 24 Aug 15 06:07:30 PM PDT 24 699387603 ps
T830 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.546934692 Aug 15 06:06:53 PM PDT 24 Aug 15 06:07:02 PM PDT 24 2039184220 ps
T831 /workspace/coverage/default/22.lc_ctrl_sec_mubi.2576032321 Aug 15 06:07:06 PM PDT 24 Aug 15 06:07:18 PM PDT 24 493747007 ps
T832 /workspace/coverage/default/4.lc_ctrl_jtag_priority.3093126892 Aug 15 06:06:22 PM PDT 24 Aug 15 06:06:26 PM PDT 24 144885318 ps
T833 /workspace/coverage/default/34.lc_ctrl_jtag_access.1990570431 Aug 15 06:07:16 PM PDT 24 Aug 15 06:07:18 PM PDT 24 795167833 ps
T834 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1304454820 Aug 15 06:07:31 PM PDT 24 Aug 15 06:07:40 PM PDT 24 466925029 ps
T835 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1728125280 Aug 15 06:06:29 PM PDT 24 Aug 15 06:06:36 PM PDT 24 481150483 ps
T836 /workspace/coverage/default/45.lc_ctrl_state_failure.1184621132 Aug 15 06:08:05 PM PDT 24 Aug 15 06:08:37 PM PDT 24 188990889 ps
T837 /workspace/coverage/default/31.lc_ctrl_state_failure.1247847396 Aug 15 06:07:15 PM PDT 24 Aug 15 06:07:39 PM PDT 24 173002194 ps
T838 /workspace/coverage/default/12.lc_ctrl_jtag_access.1333707341 Aug 15 06:06:16 PM PDT 24 Aug 15 06:06:23 PM PDT 24 244448961 ps
T839 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3403192319 Aug 15 06:06:25 PM PDT 24 Aug 15 06:06:37 PM PDT 24 1491943043 ps
T840 /workspace/coverage/default/10.lc_ctrl_smoke.3185432882 Aug 15 06:06:30 PM PDT 24 Aug 15 06:06:33 PM PDT 24 164523977 ps
T841 /workspace/coverage/default/39.lc_ctrl_errors.3079302158 Aug 15 06:07:40 PM PDT 24 Aug 15 06:07:52 PM PDT 24 1645665577 ps
T842 /workspace/coverage/default/42.lc_ctrl_security_escalation.3749262876 Aug 15 06:07:38 PM PDT 24 Aug 15 06:07:46 PM PDT 24 307771159 ps
T843 /workspace/coverage/default/35.lc_ctrl_smoke.4150879874 Aug 15 06:07:15 PM PDT 24 Aug 15 06:07:18 PM PDT 24 90940962 ps
T844 /workspace/coverage/default/7.lc_ctrl_errors.3873912972 Aug 15 06:06:17 PM PDT 24 Aug 15 06:06:30 PM PDT 24 529025472 ps
T845 /workspace/coverage/default/38.lc_ctrl_jtag_access.1766215312 Aug 15 06:07:41 PM PDT 24 Aug 15 06:07:46 PM PDT 24 957346880 ps
T846 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2796641171 Aug 15 06:06:44 PM PDT 24 Aug 15 06:06:57 PM PDT 24 780680050 ps
T847 /workspace/coverage/default/25.lc_ctrl_errors.3070301828 Aug 15 06:07:05 PM PDT 24 Aug 15 06:07:18 PM PDT 24 1357131534 ps
T848 /workspace/coverage/default/1.lc_ctrl_smoke.3129721495 Aug 15 06:06:13 PM PDT 24 Aug 15 06:06:19 PM PDT 24 94794339 ps
T849 /workspace/coverage/default/19.lc_ctrl_jtag_errors.846305384 Aug 15 06:06:52 PM PDT 24 Aug 15 06:08:03 PM PDT 24 9904276850 ps
T850 /workspace/coverage/default/39.lc_ctrl_sec_mubi.3836007665 Aug 15 06:07:45 PM PDT 24 Aug 15 06:07:59 PM PDT 24 817163742 ps
T851 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4282173059 Aug 15 06:06:10 PM PDT 24 Aug 15 06:06:11 PM PDT 24 276824372 ps
T852 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3418344703 Aug 15 06:07:40 PM PDT 24 Aug 15 06:07:52 PM PDT 24 1329395009 ps
T853 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.888911790 Aug 15 06:06:35 PM PDT 24 Aug 15 06:07:25 PM PDT 24 2564335968 ps
T854 /workspace/coverage/default/26.lc_ctrl_prog_failure.4061232694 Aug 15 06:07:11 PM PDT 24 Aug 15 06:07:14 PM PDT 24 245058445 ps
T855 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2526340871 Aug 15 06:06:52 PM PDT 24 Aug 15 06:07:01 PM PDT 24 229969941 ps
T856 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3148279751 Aug 15 06:07:10 PM PDT 24 Aug 15 06:07:18 PM PDT 24 349683357 ps
T857 /workspace/coverage/default/43.lc_ctrl_stress_all.3937935313 Aug 15 06:07:51 PM PDT 24 Aug 15 06:08:07 PM PDT 24 15369757087 ps
T858 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3742811839 Aug 15 06:06:28 PM PDT 24 Aug 15 06:06:47 PM PDT 24 6535063243 ps
T859 /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2837783137 Aug 15 06:06:08 PM PDT 24 Aug 15 06:07:54 PM PDT 24 25813891675 ps
T860 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3015355402 Aug 15 06:07:15 PM PDT 24 Aug 15 06:07:21 PM PDT 24 243100792 ps
T861 /workspace/coverage/default/13.lc_ctrl_smoke.1792998355 Aug 15 06:06:30 PM PDT 24 Aug 15 06:06:32 PM PDT 24 103081162 ps
T862 /workspace/coverage/default/26.lc_ctrl_state_post_trans.947646886 Aug 15 06:07:17 PM PDT 24 Aug 15 06:07:24 PM PDT 24 314647270 ps
T863 /workspace/coverage/default/41.lc_ctrl_prog_failure.908961896 Aug 15 06:07:38 PM PDT 24 Aug 15 06:07:42 PM PDT 24 82354985 ps
T864 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1977838080 Aug 15 06:06:13 PM PDT 24 Aug 15 06:06:25 PM PDT 24 2609911885 ps
T865 /workspace/coverage/default/9.lc_ctrl_security_escalation.1707342980 Aug 15 06:06:27 PM PDT 24 Aug 15 06:06:37 PM PDT 24 3717726749 ps
T866 /workspace/coverage/default/45.lc_ctrl_alert_test.2347410768 Aug 15 06:07:56 PM PDT 24 Aug 15 06:07:57 PM PDT 24 15586086 ps
T867 /workspace/coverage/default/2.lc_ctrl_errors.860737255 Aug 15 06:06:03 PM PDT 24 Aug 15 06:06:17 PM PDT 24 2086862364 ps
T92 /workspace/coverage/default/22.lc_ctrl_stress_all.3717908372 Aug 15 06:06:53 PM PDT 24 Aug 15 06:10:36 PM PDT 24 59520505093 ps
T868 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2894954091 Aug 15 06:07:27 PM PDT 24 Aug 15 06:07:28 PM PDT 24 30586903 ps
T869 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.476013458 Aug 15 06:07:03 PM PDT 24 Aug 15 06:07:17 PM PDT 24 1070345192 ps
T870 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2083060462 Aug 15 06:07:17 PM PDT 24 Aug 15 06:07:31 PM PDT 24 1537471411 ps
T871 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3581152377 Aug 15 06:06:24 PM PDT 24 Aug 15 06:06:58 PM PDT 24 7578044819 ps
T872 /workspace/coverage/default/26.lc_ctrl_security_escalation.2299137305 Aug 15 06:07:04 PM PDT 24 Aug 15 06:07:11 PM PDT 24 1001766470 ps
T873 /workspace/coverage/default/9.lc_ctrl_state_post_trans.1090514840 Aug 15 06:06:45 PM PDT 24 Aug 15 06:06:55 PM PDT 24 149720141 ps
T874 /workspace/coverage/default/49.lc_ctrl_jtag_access.2281424838 Aug 15 06:08:02 PM PDT 24 Aug 15 06:08:10 PM PDT 24 3005579338 ps
T875 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.704762703 Aug 15 06:06:29 PM PDT 24 Aug 15 06:06:30 PM PDT 24 35366469 ps
T103 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4254811158 Aug 15 06:31:37 PM PDT 24 Aug 15 06:31:38 PM PDT 24 14463851 ps
T104 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1548335282 Aug 15 06:31:16 PM PDT 24 Aug 15 06:31:17 PM PDT 24 107090227 ps
T109 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1101832872 Aug 15 06:31:24 PM PDT 24 Aug 15 06:31:27 PM PDT 24 81239621 ps
T105 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3452915682 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:20 PM PDT 24 72758085 ps
T171 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1338110539 Aug 15 06:31:19 PM PDT 24 Aug 15 06:31:21 PM PDT 24 36624252 ps
T102 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1124489326 Aug 15 06:31:58 PM PDT 24 Aug 15 06:32:00 PM PDT 24 54469951 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1360041408 Aug 15 06:31:27 PM PDT 24 Aug 15 06:31:28 PM PDT 24 324994068 ps
T95 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3042764697 Aug 15 06:31:10 PM PDT 24 Aug 15 06:31:13 PM PDT 24 424104996 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.794093886 Aug 15 06:31:17 PM PDT 24 Aug 15 06:31:19 PM PDT 24 315393093 ps
T172 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1512877264 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:26 PM PDT 24 12979591 ps
T876 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.805458575 Aug 15 06:31:24 PM PDT 24 Aug 15 06:31:26 PM PDT 24 135455790 ps
T138 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1152436101 Aug 15 06:31:47 PM PDT 24 Aug 15 06:31:49 PM PDT 24 30138099 ps
T99 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.529878725 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:42 PM PDT 24 18493466 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2861184311 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:34 PM PDT 24 110718034 ps
T190 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.195459030 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:35 PM PDT 24 695749574 ps
T173 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3438449352 Aug 15 06:31:48 PM PDT 24 Aug 15 06:31:49 PM PDT 24 20420809 ps
T139 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2847910421 Aug 15 06:31:42 PM PDT 24 Aug 15 06:31:44 PM PDT 24 379878275 ps
T878 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.144586323 Aug 15 06:31:14 PM PDT 24 Aug 15 06:31:22 PM PDT 24 763717095 ps
T879 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1462140538 Aug 15 06:31:39 PM PDT 24 Aug 15 06:31:43 PM PDT 24 291949616 ps
T114 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3478454597 Aug 15 06:31:57 PM PDT 24 Aug 15 06:31:59 PM PDT 24 50689189 ps
T140 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1290290497 Aug 15 06:31:26 PM PDT 24 Aug 15 06:31:28 PM PDT 24 187237631 ps
T128 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.755135704 Aug 15 06:31:17 PM PDT 24 Aug 15 06:31:30 PM PDT 24 2331634391 ps
T880 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1130557249 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:33 PM PDT 24 112226842 ps
T174 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3292188463 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:13 PM PDT 24 44234550 ps
T96 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2969903193 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:13 PM PDT 24 41078508 ps
T141 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.726922558 Aug 15 06:31:52 PM PDT 24 Aug 15 06:31:53 PM PDT 24 16905413 ps
T129 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1385020647 Aug 15 06:31:26 PM PDT 24 Aug 15 06:31:32 PM PDT 24 2499165105 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2014454635 Aug 15 06:31:26 PM PDT 24 Aug 15 06:31:34 PM PDT 24 2785492160 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.228257126 Aug 15 06:31:09 PM PDT 24 Aug 15 06:31:11 PM PDT 24 447153059 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1538452204 Aug 15 06:31:12 PM PDT 24 Aug 15 06:31:14 PM PDT 24 207483481 ps
T97 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2313030993 Aug 15 06:31:49 PM PDT 24 Aug 15 06:31:52 PM PDT 24 88647468 ps
T106 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1764202877 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:19 PM PDT 24 314470394 ps
T165 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.684720643 Aug 15 06:31:31 PM PDT 24 Aug 15 06:31:34 PM PDT 24 237820781 ps
T108 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3529164590 Aug 15 06:31:58 PM PDT 24 Aug 15 06:31:59 PM PDT 24 37190465 ps
T100 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.642706789 Aug 15 06:31:50 PM PDT 24 Aug 15 06:31:54 PM PDT 24 235740250 ps
T101 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2042352903 Aug 15 06:31:47 PM PDT 24 Aug 15 06:31:50 PM PDT 24 123150814 ps
T884 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1640845924 Aug 15 06:31:39 PM PDT 24 Aug 15 06:31:53 PM PDT 24 2613782911 ps
T116 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2921403465 Aug 15 06:31:19 PM PDT 24 Aug 15 06:31:21 PM PDT 24 92164679 ps
T885 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4150006572 Aug 15 06:31:13 PM PDT 24 Aug 15 06:31:14 PM PDT 24 15906473 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3086559561 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:30 PM PDT 24 190836572 ps
T187 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2561597816 Aug 15 06:31:56 PM PDT 24 Aug 15 06:31:57 PM PDT 24 18349215 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.333877153 Aug 15 06:31:52 PM PDT 24 Aug 15 06:31:54 PM PDT 24 27010792 ps
T188 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1784077512 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:26 PM PDT 24 77877803 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1448567961 Aug 15 06:31:26 PM PDT 24 Aug 15 06:31:27 PM PDT 24 63822014 ps
T889 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.518062520 Aug 15 06:31:20 PM PDT 24 Aug 15 06:31:24 PM PDT 24 386879173 ps
T175 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4214301665 Aug 15 06:31:19 PM PDT 24 Aug 15 06:31:20 PM PDT 24 22482305 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1288660082 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:20 PM PDT 24 55641797 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2158327801 Aug 15 06:31:12 PM PDT 24 Aug 15 06:31:13 PM PDT 24 21706097 ps
T110 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3216166413 Aug 15 06:31:49 PM PDT 24 Aug 15 06:31:52 PM PDT 24 195771342 ps
T892 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2430334389 Aug 15 06:31:40 PM PDT 24 Aug 15 06:31:42 PM PDT 24 348774451 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472664602 Aug 15 06:31:12 PM PDT 24 Aug 15 06:31:13 PM PDT 24 82805390 ps
T189 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.244826124 Aug 15 06:31:57 PM PDT 24 Aug 15 06:31:58 PM PDT 24 12228222 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2531674382 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:20 PM PDT 24 27162640 ps
T115 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3420867398 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:44 PM PDT 24 148674529 ps
T123 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1843313698 Aug 15 06:31:34 PM PDT 24 Aug 15 06:31:37 PM PDT 24 62221466 ps
T895 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2967189335 Aug 15 06:31:58 PM PDT 24 Aug 15 06:32:01 PM PDT 24 98309621 ps
T896 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.65948651 Aug 15 06:31:51 PM PDT 24 Aug 15 06:31:52 PM PDT 24 116150924 ps
T897 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2685892036 Aug 15 06:31:31 PM PDT 24 Aug 15 06:31:34 PM PDT 24 581361654 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2634674384 Aug 15 06:31:20 PM PDT 24 Aug 15 06:31:22 PM PDT 24 221832045 ps
T120 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4175624210 Aug 15 06:31:28 PM PDT 24 Aug 15 06:31:30 PM PDT 24 79792477 ps
T899 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4051196457 Aug 15 06:31:38 PM PDT 24 Aug 15 06:31:40 PM PDT 24 2383764664 ps
T117 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3786326123 Aug 15 06:31:17 PM PDT 24 Aug 15 06:31:21 PM PDT 24 445424550 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2786658761 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:13 PM PDT 24 58694922 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.760573827 Aug 15 06:31:28 PM PDT 24 Aug 15 06:31:30 PM PDT 24 58506473 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3483498367 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:43 PM PDT 24 216992817 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1269762965 Aug 15 06:31:17 PM PDT 24 Aug 15 06:31:19 PM PDT 24 320334367 ps
T904 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2487936538 Aug 15 06:31:49 PM PDT 24 Aug 15 06:31:50 PM PDT 24 17527540 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.760581298 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:33 PM PDT 24 2555835971 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1245938699 Aug 15 06:31:20 PM PDT 24 Aug 15 06:31:21 PM PDT 24 119637665 ps
T907 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.132953910 Aug 15 06:31:50 PM PDT 24 Aug 15 06:31:52 PM PDT 24 102441310 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2324350556 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:12 PM PDT 24 85289560 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.121261068 Aug 15 06:31:13 PM PDT 24 Aug 15 06:31:15 PM PDT 24 73286018 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1416856551 Aug 15 06:31:24 PM PDT 24 Aug 15 06:31:26 PM PDT 24 66420572 ps
T121 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.937564718 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:13 PM PDT 24 45230044 ps
T911 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.236058885 Aug 15 06:31:34 PM PDT 24 Aug 15 06:31:41 PM PDT 24 264467946 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.160493922 Aug 15 06:31:31 PM PDT 24 Aug 15 06:31:33 PM PDT 24 126353019 ps
T176 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4187444318 Aug 15 06:31:19 PM PDT 24 Aug 15 06:31:20 PM PDT 24 36242669 ps
T177 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.579018669 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:26 PM PDT 24 20477652 ps
T913 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3223505128 Aug 15 06:31:27 PM PDT 24 Aug 15 06:31:32 PM PDT 24 654469356 ps
T111 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4291170373 Aug 15 06:31:50 PM PDT 24 Aug 15 06:31:52 PM PDT 24 46885726 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2404218409 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:27 PM PDT 24 52568193 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1459462047 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:44 PM PDT 24 277763795 ps
T916 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3314668460 Aug 15 06:31:26 PM PDT 24 Aug 15 06:31:35 PM PDT 24 352742398 ps
T917 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1935399525 Aug 15 06:31:34 PM PDT 24 Aug 15 06:31:36 PM PDT 24 151337303 ps
T178 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2644302631 Aug 15 06:31:56 PM PDT 24 Aug 15 06:31:57 PM PDT 24 67056276 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2448595127 Aug 15 06:31:12 PM PDT 24 Aug 15 06:31:13 PM PDT 24 211274976 ps
T112 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2411627277 Aug 15 06:31:56 PM PDT 24 Aug 15 06:31:59 PM PDT 24 49488873 ps
T919 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.748334905 Aug 15 06:31:51 PM PDT 24 Aug 15 06:31:54 PM PDT 24 94796273 ps
T920 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3203945945 Aug 15 06:31:34 PM PDT 24 Aug 15 06:31:36 PM PDT 24 103971476 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1293993927 Aug 15 06:31:31 PM PDT 24 Aug 15 06:31:55 PM PDT 24 2358819310 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2347096047 Aug 15 06:31:13 PM PDT 24 Aug 15 06:31:14 PM PDT 24 16854466 ps
T923 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1460681419 Aug 15 06:31:10 PM PDT 24 Aug 15 06:31:13 PM PDT 24 599711014 ps
T924 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2430910632 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:27 PM PDT 24 228447431 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.525747982 Aug 15 06:31:17 PM PDT 24 Aug 15 06:31:20 PM PDT 24 859142220 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2341661516 Aug 15 06:31:27 PM PDT 24 Aug 15 06:31:30 PM PDT 24 94917006 ps
T926 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.466847643 Aug 15 06:31:47 PM PDT 24 Aug 15 06:31:49 PM PDT 24 142165799 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3908952177 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:12 PM PDT 24 16119718 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.278179734 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:26 PM PDT 24 420535548 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.279204198 Aug 15 06:31:21 PM PDT 24 Aug 15 06:31:22 PM PDT 24 15044208 ps
T107 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2258713384 Aug 15 06:31:40 PM PDT 24 Aug 15 06:31:44 PM PDT 24 601544579 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2213114709 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:20 PM PDT 24 73642861 ps
T931 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2173190317 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:20 PM PDT 24 105564805 ps
T932 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.233140114 Aug 15 06:31:27 PM PDT 24 Aug 15 06:31:29 PM PDT 24 39394898 ps
T933 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3739122053 Aug 15 06:31:40 PM PDT 24 Aug 15 06:31:42 PM PDT 24 91853321 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.271769826 Aug 15 06:31:13 PM PDT 24 Aug 15 06:31:15 PM PDT 24 32703855 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1311556931 Aug 15 06:31:29 PM PDT 24 Aug 15 06:31:34 PM PDT 24 188579788 ps
T936 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3033230949 Aug 15 06:31:47 PM PDT 24 Aug 15 06:31:48 PM PDT 24 11863647 ps
T179 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3529355646 Aug 15 06:31:57 PM PDT 24 Aug 15 06:31:58 PM PDT 24 12804148 ps
T937 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.566886975 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:15 PM PDT 24 228992330 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.780414637 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:12 PM PDT 24 20587784 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3304120169 Aug 15 06:31:17 PM PDT 24 Aug 15 06:31:20 PM PDT 24 181949996 ps
T119 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3250309713 Aug 15 06:31:49 PM PDT 24 Aug 15 06:31:51 PM PDT 24 134814133 ps
T940 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1247916635 Aug 15 06:31:28 PM PDT 24 Aug 15 06:31:30 PM PDT 24 72360937 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1088917335 Aug 15 06:31:34 PM PDT 24 Aug 15 06:31:38 PM PDT 24 612347152 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3034478301 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:43 PM PDT 24 301934084 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2711050540 Aug 15 06:31:26 PM PDT 24 Aug 15 06:31:28 PM PDT 24 34878025 ps
T944 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.902873151 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:33 PM PDT 24 17515538 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1909693975 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:36 PM PDT 24 287178488 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2574408380 Aug 15 06:31:37 PM PDT 24 Aug 15 06:31:38 PM PDT 24 17184968 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3653887293 Aug 15 06:31:40 PM PDT 24 Aug 15 06:31:42 PM PDT 24 26843385 ps
T113 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1738422416 Aug 15 06:31:51 PM PDT 24 Aug 15 06:31:55 PM PDT 24 695354024 ps
T126 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1686655523 Aug 15 06:31:57 PM PDT 24 Aug 15 06:31:59 PM PDT 24 202559297 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.118706870 Aug 15 06:31:31 PM PDT 24 Aug 15 06:31:32 PM PDT 24 13793012 ps
T949 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1091020414 Aug 15 06:31:48 PM PDT 24 Aug 15 06:31:51 PM PDT 24 505135145 ps
T950 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1308259568 Aug 15 06:31:31 PM PDT 24 Aug 15 06:31:38 PM PDT 24 1906150945 ps
T951 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3654245996 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:19 PM PDT 24 45682120 ps
T180 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.543045900 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:42 PM PDT 24 12415581 ps
T952 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.682168207 Aug 15 06:31:42 PM PDT 24 Aug 15 06:31:45 PM PDT 24 220093820 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2186712976 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:19 PM PDT 24 298020660 ps
T954 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.752263238 Aug 15 06:31:48 PM PDT 24 Aug 15 06:31:50 PM PDT 24 43882052 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.532625565 Aug 15 06:31:11 PM PDT 24 Aug 15 06:31:14 PM PDT 24 50051554 ps
T185 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3065144084 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:42 PM PDT 24 67871966 ps
T956 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2385349703 Aug 15 06:31:19 PM PDT 24 Aug 15 06:31:21 PM PDT 24 20460070 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.32330075 Aug 15 06:31:42 PM PDT 24 Aug 15 06:31:44 PM PDT 24 57173597 ps
T958 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3117693712 Aug 15 06:31:40 PM PDT 24 Aug 15 06:31:41 PM PDT 24 32985086 ps
T959 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.379385977 Aug 15 06:31:58 PM PDT 24 Aug 15 06:31:59 PM PDT 24 41159068 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1318932798 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:33 PM PDT 24 107202908 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4225543179 Aug 15 06:31:16 PM PDT 24 Aug 15 06:31:18 PM PDT 24 119669575 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4180302671 Aug 15 06:31:24 PM PDT 24 Aug 15 06:31:26 PM PDT 24 48740509 ps
T963 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3341260016 Aug 15 06:31:50 PM PDT 24 Aug 15 06:31:52 PM PDT 24 18807015 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1474761212 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:22 PM PDT 24 631255279 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3026351035 Aug 15 06:31:27 PM PDT 24 Aug 15 06:31:42 PM PDT 24 2485272974 ps
T966 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3073334026 Aug 15 06:31:48 PM PDT 24 Aug 15 06:31:49 PM PDT 24 20780975 ps
T967 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1968326714 Aug 15 06:31:14 PM PDT 24 Aug 15 06:31:17 PM PDT 24 373884513 ps
T968 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1068863723 Aug 15 06:31:25 PM PDT 24 Aug 15 06:31:27 PM PDT 24 116491262 ps
T969 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1971223201 Aug 15 06:31:54 PM PDT 24 Aug 15 06:31:56 PM PDT 24 37317800 ps
T182 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2275553330 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:42 PM PDT 24 81008103 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.137911215 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:19 PM PDT 24 99959518 ps
T181 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2652022514 Aug 15 06:31:42 PM PDT 24 Aug 15 06:31:43 PM PDT 24 39576874 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1400052022 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:35 PM PDT 24 78564928 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.915115975 Aug 15 06:31:24 PM PDT 24 Aug 15 06:31:25 PM PDT 24 35811718 ps
T973 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2054787234 Aug 15 06:31:18 PM PDT 24 Aug 15 06:31:20 PM PDT 24 191586298 ps
T974 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2137950440 Aug 15 06:31:20 PM PDT 24 Aug 15 06:31:21 PM PDT 24 54391031 ps
T975 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1444896998 Aug 15 06:31:57 PM PDT 24 Aug 15 06:31:58 PM PDT 24 31784143 ps
T124 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3980468418 Aug 15 06:31:33 PM PDT 24 Aug 15 06:31:37 PM PDT 24 200320233 ps
T976 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1330137804 Aug 15 06:31:51 PM PDT 24 Aug 15 06:31:52 PM PDT 24 118821998 ps
T977 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2688910017 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:34 PM PDT 24 179161596 ps
T978 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3679014601 Aug 15 06:31:50 PM PDT 24 Aug 15 06:31:52 PM PDT 24 123624523 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2828522163 Aug 15 06:31:19 PM PDT 24 Aug 15 06:31:20 PM PDT 24 74283110 ps
T980 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4035761165 Aug 15 06:31:42 PM PDT 24 Aug 15 06:31:43 PM PDT 24 33213011 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3562419093 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:50 PM PDT 24 3047869647 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.372407505 Aug 15 06:31:41 PM PDT 24 Aug 15 06:31:48 PM PDT 24 1017926000 ps
T183 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3161282800 Aug 15 06:31:26 PM PDT 24 Aug 15 06:31:28 PM PDT 24 163346270 ps
T983 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2256506993 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:35 PM PDT 24 138923977 ps
T984 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3462051794 Aug 15 06:31:14 PM PDT 24 Aug 15 06:31:15 PM PDT 24 22408665 ps
T118 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2442223193 Aug 15 06:31:31 PM PDT 24 Aug 15 06:31:36 PM PDT 24 415765600 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.63103149 Aug 15 06:31:16 PM PDT 24 Aug 15 06:31:25 PM PDT 24 977803784 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.181036370 Aug 15 06:31:34 PM PDT 24 Aug 15 06:31:38 PM PDT 24 168719020 ps
T184 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1377762789 Aug 15 06:31:09 PM PDT 24 Aug 15 06:31:10 PM PDT 24 32688048 ps
T987 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2728173254 Aug 15 06:31:32 PM PDT 24 Aug 15 06:31:36 PM PDT 24 110066711 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2692431567 Aug 15 06:31:20 PM PDT 24 Aug 15 06:31:21 PM PDT 24 30448985 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2129402711 Aug 15 06:31:42 PM PDT 24 Aug 15 06:31:47 PM PDT 24 805068400 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2812012798 Aug 15 06:31:40 PM PDT 24 Aug 15 06:31:44 PM PDT 24 500179660 ps
T990 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3064187220 Aug 15 06:32:00 PM PDT 24 Aug 15 06:32:02 PM PDT 24 86105435 ps
T991 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.652632031 Aug 15 06:31:10 PM PDT 24 Aug 15 06:31:33 PM PDT 24 2081962543 ps
T992 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2120107874 Aug 15 06:31:37 PM PDT 24 Aug 15 06:31:39 PM PDT 24 301676807 ps
T993 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.427393850 Aug 15 06:31:49 PM PDT 24 Aug 15 06:31:51 PM PDT 24 20331665 ps
T994 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.539647282 Aug 15 06:31:42 PM PDT 24 Aug 15 06:31:44 PM PDT 24 67421751 ps
T186 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2528332475 Aug 15 06:31:17 PM PDT 24 Aug 15 06:31:19 PM PDT 24 39477262 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1294728933 Aug 15 06:31:33 PM PDT 24 Aug 15 06:31:35 PM PDT 24 56703845 ps
T996 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1077646533 Aug 15 06:31:48 PM PDT 24 Aug 15 06:31:50 PM PDT 24 384878713 ps
T997 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3684498103 Aug 15 06:31:50 PM PDT 24 Aug 15 06:31:51 PM PDT 24 32927990 ps
T998 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3284855672 Aug 15 06:31:33 PM PDT 24 Aug 15 06:31:39 PM PDT 24 518688132 ps
T999 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2403830053 Aug 15 06:31:14 PM PDT 24 Aug 15 06:31:16 PM PDT 24 36527797 ps
T1000 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2064997190 Aug 15 06:31:48 PM PDT 24 Aug 15 06:31:49 PM PDT 24 18874647 ps

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4082652887
Short name T12
Test name
Test status
Simulation time 686640405 ps
CPU time 10.71 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 218952 kb
Host smart-2e422815-588c-41ab-a186-d498332ee866
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082652887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4082652887
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2085657414
Short name T15
Test name
Test status
Simulation time 60201162538 ps
CPU time 494.76 seconds
Started Aug 15 06:07:34 PM PDT 24
Finished Aug 15 06:15:49 PM PDT 24
Peak memory 268612 kb
Host smart-e12c4a40-d147-4baa-b636-4f909a33afc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085657414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2085657414
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2256069849
Short name T2
Test name
Test status
Simulation time 1329486579 ps
CPU time 8.29 seconds
Started Aug 15 06:07:28 PM PDT 24
Finished Aug 15 06:07:36 PM PDT 24
Peak memory 225008 kb
Host smart-a3d1329a-5c34-4bee-9dad-5546e53158b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256069849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2256069849
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1882272679
Short name T200
Test name
Test status
Simulation time 2418499694 ps
CPU time 12.6 seconds
Started Aug 15 06:06:31 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 226136 kb
Host smart-7426e6db-fdf8-4ae0-9896-c5f58996d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882272679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1882272679
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2857341799
Short name T80
Test name
Test status
Simulation time 2784773888 ps
CPU time 123.36 seconds
Started Aug 15 06:07:20 PM PDT 24
Finished Aug 15 06:09:24 PM PDT 24
Peak memory 280748 kb
Host smart-3b08061f-b063-48bc-bbb5-8e475d50e45c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2857341799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2857341799
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.529878725
Short name T99
Test name
Test status
Simulation time 18493466 ps
CPU time 1.16 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 218136 kb
Host smart-976c6026-79a9-4a62-b347-e82231d3fa03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529878725 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.529878725
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.629256440
Short name T5
Test name
Test status
Simulation time 1105030781 ps
CPU time 8.17 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:13 PM PDT 24
Peak memory 217392 kb
Host smart-9997a958-3d36-4c2b-b8f1-fd0824e3fad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629256440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.629256440
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3623686219
Short name T49
Test name
Test status
Simulation time 470646210 ps
CPU time 38.8 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:43 PM PDT 24
Peak memory 283236 kb
Host smart-0d6dc794-f68d-423c-907c-0de492a65453
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623686219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3623686219
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2116948181
Short name T53
Test name
Test status
Simulation time 27046351311 ps
CPU time 134.79 seconds
Started Aug 15 06:07:56 PM PDT 24
Finished Aug 15 06:10:11 PM PDT 24
Peak memory 251708 kb
Host smart-daa5f5cc-ca85-40b6-a88f-a1491b7808e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116948181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2116948181
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2555654897
Short name T18
Test name
Test status
Simulation time 396751464 ps
CPU time 14.46 seconds
Started Aug 15 06:07:52 PM PDT 24
Finished Aug 15 06:08:07 PM PDT 24
Peak memory 218204 kb
Host smart-c20bec9a-a154-4197-bb0a-9b6574c9285d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555654897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2555654897
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.642706789
Short name T100
Test name
Test status
Simulation time 235740250 ps
CPU time 3.19 seconds
Started Aug 15 06:31:50 PM PDT 24
Finished Aug 15 06:31:54 PM PDT 24
Peak memory 222916 kb
Host smart-e61dc46b-60c1-49cd-8c63-c5ab27756fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642706789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.642706789
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2057605774
Short name T28
Test name
Test status
Simulation time 27665011 ps
CPU time 1.06 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 208872 kb
Host smart-0b8d3d01-6da2-4aba-bf5a-8002dc2b7da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057605774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2057605774
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.543045900
Short name T180
Test name
Test status
Simulation time 12415581 ps
CPU time 0.83 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 209744 kb
Host smart-108ab709-834c-426b-9648-76a8ff507437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543045900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.543045900
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.755135704
Short name T128
Test name
Test status
Simulation time 2331634391 ps
CPU time 13.36 seconds
Started Aug 15 06:31:17 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 209764 kb
Host smart-8a71433f-a3af-4c13-b16b-b8c0aea44922
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755135704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.755135704
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3223770786
Short name T40
Test name
Test status
Simulation time 2427939611 ps
CPU time 54.08 seconds
Started Aug 15 06:06:19 PM PDT 24
Finished Aug 15 06:07:13 PM PDT 24
Peak memory 248732 kb
Host smart-e7994e40-9d37-4b6c-bf78-bda976654682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223770786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3223770786
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1764202877
Short name T106
Test name
Test status
Simulation time 314470394 ps
CPU time 8.07 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 219220 kb
Host smart-53401d60-63e0-4e0f-9a03-8e31e6951bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176420
2877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1764202877
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3420867398
Short name T115
Test name
Test status
Simulation time 148674529 ps
CPU time 2.59 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 223228 kb
Host smart-4c4e5d7d-0c5c-4c20-babd-81183f47a75d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420867398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3420867398
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3843363116
Short name T7
Test name
Test status
Simulation time 15083262120 ps
CPU time 122.56 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:09:35 PM PDT 24
Peak memory 272272 kb
Host smart-c7c72587-c199-4440-9653-c894802bbd1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3843363116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3843363116
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3042764697
Short name T95
Test name
Test status
Simulation time 424104996 ps
CPU time 3.08 seconds
Started Aug 15 06:31:10 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 223144 kb
Host smart-49b0ce9c-16d4-4749-affd-e6cf5e65996b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042764697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3042764697
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3609274120
Short name T93
Test name
Test status
Simulation time 9705410793 ps
CPU time 333.65 seconds
Started Aug 15 06:06:56 PM PDT 24
Finished Aug 15 06:12:30 PM PDT 24
Peak memory 276796 kb
Host smart-f8a4c5d1-b329-4a19-8d13-3af2d880899d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609274120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3609274120
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2667021
Short name T13
Test name
Test status
Simulation time 488193363 ps
CPU time 14.56 seconds
Started Aug 15 06:06:05 PM PDT 24
Finished Aug 15 06:06:20 PM PDT 24
Peak memory 226064 kb
Host smart-a0a4a2f5-0de9-4b2b-8ef0-53f9e407dc11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2667021
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2042352903
Short name T101
Test name
Test status
Simulation time 123150814 ps
CPU time 2.96 seconds
Started Aug 15 06:31:47 PM PDT 24
Finished Aug 15 06:31:50 PM PDT 24
Peak memory 218152 kb
Host smart-04c82e2d-5813-4ce4-b129-90a95d6bca15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042352903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2042352903
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1152436101
Short name T138
Test name
Test status
Simulation time 30138099 ps
CPU time 1.48 seconds
Started Aug 15 06:31:47 PM PDT 24
Finished Aug 15 06:31:49 PM PDT 24
Peak memory 209956 kb
Host smart-e30c2279-0220-4388-b0a8-951c6a9cd010
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152436101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1152436101
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3128245091
Short name T11
Test name
Test status
Simulation time 29154130 ps
CPU time 0.81 seconds
Started Aug 15 06:05:59 PM PDT 24
Finished Aug 15 06:06:00 PM PDT 24
Peak memory 211896 kb
Host smart-24626bd7-bbb8-4b01-ac22-986b935f9cdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128245091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3128245091
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.937564718
Short name T121
Test name
Test status
Simulation time 45230044 ps
CPU time 2.13 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 222336 kb
Host smart-cfc8c0fb-343b-4c40-a5ce-fca7cfbc049a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937564718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.937564718
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2411627277
Short name T112
Test name
Test status
Simulation time 49488873 ps
CPU time 2.06 seconds
Started Aug 15 06:31:56 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 222788 kb
Host smart-af0bfd4b-8ec1-491a-948d-0f991a98d35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411627277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2411627277
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2442223193
Short name T118
Test name
Test status
Simulation time 415765600 ps
CPU time 4.26 seconds
Started Aug 15 06:31:31 PM PDT 24
Finished Aug 15 06:31:36 PM PDT 24
Peak memory 218084 kb
Host smart-e9c37fd5-baa5-413c-8da4-7691d929f578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442223193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2442223193
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2258713384
Short name T107
Test name
Test status
Simulation time 601544579 ps
CPU time 3.87 seconds
Started Aug 15 06:31:40 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 218272 kb
Host smart-33e0696a-11ab-492e-8e16-338872f67e24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258713384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2258713384
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2052893974
Short name T194
Test name
Test status
Simulation time 10634226 ps
CPU time 0.83 seconds
Started Aug 15 06:05:49 PM PDT 24
Finished Aug 15 06:05:50 PM PDT 24
Peak memory 208948 kb
Host smart-cf6f93ec-511e-44ae-9c6f-ca7b16551c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052893974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2052893974
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1381697483
Short name T193
Test name
Test status
Simulation time 23736523 ps
CPU time 0.83 seconds
Started Aug 15 06:06:05 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 208584 kb
Host smart-ca492772-c612-4e72-9f8c-569b3e428b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381697483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1381697483
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2087995446
Short name T192
Test name
Test status
Simulation time 71275244 ps
CPU time 0.95 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:06:16 PM PDT 24
Peak memory 208732 kb
Host smart-c973da73-155e-4d75-82ee-235f18428c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087995446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2087995446
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2812012798
Short name T125
Test name
Test status
Simulation time 500179660 ps
CPU time 4.06 seconds
Started Aug 15 06:31:40 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 218124 kb
Host smart-9163327a-55c2-4c2c-b753-dda22b7b4d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812012798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2812012798
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3216166413
Short name T110
Test name
Test status
Simulation time 195771342 ps
CPU time 3.35 seconds
Started Aug 15 06:31:49 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 218244 kb
Host smart-97ea75a3-4c33-41f3-8197-881f439a24b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216166413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3216166413
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.525747982
Short name T122
Test name
Test status
Simulation time 859142220 ps
CPU time 2.94 seconds
Started Aug 15 06:31:17 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 214068 kb
Host smart-6d24bab2-ea37-4f7e-86fe-ab6ca0f6d17e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525747982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.525747982
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3786326123
Short name T117
Test name
Test status
Simulation time 445424550 ps
CPU time 2.8 seconds
Started Aug 15 06:31:17 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 222764 kb
Host smart-ac618050-9eca-4bf8-88e1-11cd761b46eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786326123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3786326123
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1843313698
Short name T123
Test name
Test status
Simulation time 62221466 ps
CPU time 2.8 seconds
Started Aug 15 06:31:34 PM PDT 24
Finished Aug 15 06:31:37 PM PDT 24
Peak memory 218124 kb
Host smart-476d3cfa-1c5d-4c39-9c8b-97a2de8889c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843313698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1843313698
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3715591209
Short name T45
Test name
Test status
Simulation time 251857680 ps
CPU time 9.37 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:18 PM PDT 24
Peak memory 226060 kb
Host smart-01e4ee63-0383-407c-9d20-959b23201dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715591209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3715591209
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.852514216
Short name T42
Test name
Test status
Simulation time 6637304984 ps
CPU time 232.91 seconds
Started Aug 15 06:07:53 PM PDT 24
Finished Aug 15 06:11:46 PM PDT 24
Peak memory 283136 kb
Host smart-a35448c5-5f5e-4e34-966e-1d76cc33ef18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852514216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.852514216
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4012937232
Short name T54
Test name
Test status
Simulation time 19326672 ps
CPU time 1.7 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:06:32 PM PDT 24
Peak memory 213636 kb
Host smart-2bb24e07-36dc-4867-81db-f9a2a368ae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012937232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4012937232
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1319445605
Short name T206
Test name
Test status
Simulation time 758127941 ps
CPU time 20.56 seconds
Started Aug 15 06:06:34 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 245148 kb
Host smart-d33c1719-31f6-458b-a03d-6d6ac5ae34e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319445605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1319445605
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2448962266
Short name T57
Test name
Test status
Simulation time 91525621 ps
CPU time 4.27 seconds
Started Aug 15 06:06:50 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 218288 kb
Host smart-34c3ec38-2a38-4e0d-9959-79fade87996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448962266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2448962266
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3292188463
Short name T174
Test name
Test status
Simulation time 44234550 ps
CPU time 1.07 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 209936 kb
Host smart-6a1fa5ce-75d2-480d-9acf-4763504e8a4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292188463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3292188463
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.780414637
Short name T938
Test name
Test status
Simulation time 20587784 ps
CPU time 1.46 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:12 PM PDT 24
Peak memory 208876 kb
Host smart-3cbbf4fa-16ff-4418-834d-864e133a8ce8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780414637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.780414637
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1377762789
Short name T184
Test name
Test status
Simulation time 32688048 ps
CPU time 1.17 seconds
Started Aug 15 06:31:09 PM PDT 24
Finished Aug 15 06:31:10 PM PDT 24
Peak memory 210564 kb
Host smart-eda933b7-2b70-40e0-8bf2-c4017e06507b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377762789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1377762789
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2158327801
Short name T891
Test name
Test status
Simulation time 21706097 ps
CPU time 1.34 seconds
Started Aug 15 06:31:12 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 220076 kb
Host smart-dfea063f-9fa1-4e29-b1bc-04df17608d03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158327801 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2158327801
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2347096047
Short name T922
Test name
Test status
Simulation time 16854466 ps
CPU time 0.88 seconds
Started Aug 15 06:31:13 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 209688 kb
Host smart-af04f03b-f74b-4ff3-9763-278fe79e5897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347096047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2347096047
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.228257126
Short name T882
Test name
Test status
Simulation time 447153059 ps
CPU time 1.2 seconds
Started Aug 15 06:31:09 PM PDT 24
Finished Aug 15 06:31:11 PM PDT 24
Peak memory 209848 kb
Host smart-6bdce109-ee1d-487f-a13a-2bb24e851761
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228257126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.228257126
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2186712976
Short name T953
Test name
Test status
Simulation time 298020660 ps
CPU time 7.84 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 209760 kb
Host smart-104e9907-e300-4adb-91ef-6f84ca112e4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186712976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2186712976
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.652632031
Short name T991
Test name
Test status
Simulation time 2081962543 ps
CPU time 22.8 seconds
Started Aug 15 06:31:10 PM PDT 24
Finished Aug 15 06:31:33 PM PDT 24
Peak memory 209788 kb
Host smart-05ce5447-1f71-4859-af1e-d2b4b553af78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652632031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.652632031
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2786658761
Short name T900
Test name
Test status
Simulation time 58694922 ps
CPU time 2.03 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 211532 kb
Host smart-5e03fcfa-4578-4cc4-b6dd-012c6ffc7547
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786658761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2786658761
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472664602
Short name T893
Test name
Test status
Simulation time 82805390 ps
CPU time 1.34 seconds
Started Aug 15 06:31:12 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 221028 kb
Host smart-991aed01-119f-4d19-ae2c-e54f8ec33160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347266
4602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472664602
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2448595127
Short name T918
Test name
Test status
Simulation time 211274976 ps
CPU time 1.08 seconds
Started Aug 15 06:31:12 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 208936 kb
Host smart-4b8212d6-a000-47a7-958c-bcdeaf8b0f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448595127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2448595127
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2324350556
Short name T908
Test name
Test status
Simulation time 85289560 ps
CPU time 1.17 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:12 PM PDT 24
Peak memory 209920 kb
Host smart-de45ef25-d319-449c-93d7-6c9b2eff981d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324350556 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2324350556
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.532625565
Short name T955
Test name
Test status
Simulation time 50051554 ps
CPU time 1.96 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 209940 kb
Host smart-cb01a059-a0e3-43af-abac-ed34377b527b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532625565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.532625565
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2403830053
Short name T999
Test name
Test status
Simulation time 36527797 ps
CPU time 1.8 seconds
Started Aug 15 06:31:14 PM PDT 24
Finished Aug 15 06:31:16 PM PDT 24
Peak memory 209936 kb
Host smart-8aeebc37-d639-4c61-805a-df72497060a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403830053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2403830053
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3908952177
Short name T927
Test name
Test status
Simulation time 16119718 ps
CPU time 1.17 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:12 PM PDT 24
Peak memory 209932 kb
Host smart-0c147188-5178-4b27-8c01-e41e4f3f73a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908952177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3908952177
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.121261068
Short name T909
Test name
Test status
Simulation time 73286018 ps
CPU time 1.76 seconds
Started Aug 15 06:31:13 PM PDT 24
Finished Aug 15 06:31:15 PM PDT 24
Peak memory 209896 kb
Host smart-a6bdfd43-105d-41fd-9544-7e84c7d3ded6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121261068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.121261068
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3462051794
Short name T984
Test name
Test status
Simulation time 22408665 ps
CPU time 0.82 seconds
Started Aug 15 06:31:14 PM PDT 24
Finished Aug 15 06:31:15 PM PDT 24
Peak memory 209720 kb
Host smart-f9497984-383c-4cbc-90a9-adf59f7c4436
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462051794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3462051794
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.137911215
Short name T970
Test name
Test status
Simulation time 99959518 ps
CPU time 1.55 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 219168 kb
Host smart-01df6702-1237-4f79-89de-14c4d1cfe0f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137911215 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.137911215
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4150006572
Short name T885
Test name
Test status
Simulation time 15906473 ps
CPU time 1.08 seconds
Started Aug 15 06:31:13 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 209936 kb
Host smart-99604849-79eb-474a-a8a6-93836697182c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150006572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.4150006572
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1538452204
Short name T883
Test name
Test status
Simulation time 207483481 ps
CPU time 1.82 seconds
Started Aug 15 06:31:12 PM PDT 24
Finished Aug 15 06:31:14 PM PDT 24
Peak memory 209840 kb
Host smart-27af41e1-fefd-4f5d-b970-123d6f5748b7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538452204 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1538452204
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.566886975
Short name T937
Test name
Test status
Simulation time 228992330 ps
CPU time 3.36 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:15 PM PDT 24
Peak memory 209136 kb
Host smart-8242561e-a5ca-4d80-b395-d93fe8caeef4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566886975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.566886975
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.144586323
Short name T878
Test name
Test status
Simulation time 763717095 ps
CPU time 7.84 seconds
Started Aug 15 06:31:14 PM PDT 24
Finished Aug 15 06:31:22 PM PDT 24
Peak memory 209952 kb
Host smart-4433c016-7dc0-4a6a-bcc6-1d2cf6650723
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144586323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.144586323
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1460681419
Short name T923
Test name
Test status
Simulation time 599711014 ps
CPU time 2.13 seconds
Started Aug 15 06:31:10 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 211496 kb
Host smart-4cba42a8-b6e2-44f7-9918-ef9f284853dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460681419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1460681419
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1968326714
Short name T967
Test name
Test status
Simulation time 373884513 ps
CPU time 2.83 seconds
Started Aug 15 06:31:14 PM PDT 24
Finished Aug 15 06:31:17 PM PDT 24
Peak memory 209820 kb
Host smart-187288ca-6442-4734-b4dc-82d59121023c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968326714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1968326714
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.271769826
Short name T934
Test name
Test status
Simulation time 32703855 ps
CPU time 1.4 seconds
Started Aug 15 06:31:13 PM PDT 24
Finished Aug 15 06:31:15 PM PDT 24
Peak memory 209924 kb
Host smart-b89792e4-a8fa-4fb1-9b82-980c5219a7b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271769826 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.271769826
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2828522163
Short name T979
Test name
Test status
Simulation time 74283110 ps
CPU time 1.22 seconds
Started Aug 15 06:31:19 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 209764 kb
Host smart-be56abe2-2eb0-4b0e-8d03-43733fa58f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828522163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2828522163
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2969903193
Short name T96
Test name
Test status
Simulation time 41078508 ps
CPU time 1.55 seconds
Started Aug 15 06:31:11 PM PDT 24
Finished Aug 15 06:31:13 PM PDT 24
Peak memory 218128 kb
Host smart-ecc7530a-0281-44aa-a5ef-4c9c37337572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969903193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2969903193
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3117693712
Short name T958
Test name
Test status
Simulation time 32985086 ps
CPU time 0.95 seconds
Started Aug 15 06:31:40 PM PDT 24
Finished Aug 15 06:31:41 PM PDT 24
Peak memory 218256 kb
Host smart-c55dc314-f220-4ef3-9927-f0062c4ba69b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117693712 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3117693712
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2275553330
Short name T182
Test name
Test status
Simulation time 81008103 ps
CPU time 1.09 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 209932 kb
Host smart-486044e8-38e4-42aa-87c0-2f1721e539a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275553330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2275553330
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.539647282
Short name T994
Test name
Test status
Simulation time 67421751 ps
CPU time 1.48 seconds
Started Aug 15 06:31:42 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 212140 kb
Host smart-6b3bb295-2e34-4821-a728-d87c16cbd191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539647282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.539647282
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.682168207
Short name T952
Test name
Test status
Simulation time 220093820 ps
CPU time 2.68 seconds
Started Aug 15 06:31:42 PM PDT 24
Finished Aug 15 06:31:45 PM PDT 24
Peak memory 218136 kb
Host smart-f6621695-33c3-4a49-8bcb-19fdde88de66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682168207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.682168207
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3341260016
Short name T963
Test name
Test status
Simulation time 18807015 ps
CPU time 0.99 seconds
Started Aug 15 06:31:50 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 218120 kb
Host smart-edc9e9f6-d0b4-41aa-a3b8-c9f972c2f6c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341260016 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3341260016
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4035761165
Short name T980
Test name
Test status
Simulation time 33213011 ps
CPU time 1.34 seconds
Started Aug 15 06:31:42 PM PDT 24
Finished Aug 15 06:31:43 PM PDT 24
Peak memory 210012 kb
Host smart-c65e669d-b1a0-4cf6-8b1d-6faf81ae50a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035761165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.4035761165
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3739122053
Short name T933
Test name
Test status
Simulation time 91853321 ps
CPU time 1.69 seconds
Started Aug 15 06:31:40 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 218188 kb
Host smart-409a6f96-9716-433d-a351-35f672744b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739122053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3739122053
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2487936538
Short name T904
Test name
Test status
Simulation time 17527540 ps
CPU time 1.19 seconds
Started Aug 15 06:31:49 PM PDT 24
Finished Aug 15 06:31:50 PM PDT 24
Peak memory 218228 kb
Host smart-c4662d65-ef67-4190-8c35-a8d164526d1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487936538 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2487936538
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3033230949
Short name T936
Test name
Test status
Simulation time 11863647 ps
CPU time 0.85 seconds
Started Aug 15 06:31:47 PM PDT 24
Finished Aug 15 06:31:48 PM PDT 24
Peak memory 209800 kb
Host smart-604207db-c662-4f14-8a98-5d15d370a240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033230949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3033230949
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1971223201
Short name T969
Test name
Test status
Simulation time 37317800 ps
CPU time 2.54 seconds
Started Aug 15 06:31:54 PM PDT 24
Finished Aug 15 06:31:56 PM PDT 24
Peak memory 219204 kb
Host smart-23118b3f-1a37-4d7e-b1cb-dd33c579a653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971223201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1971223201
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3250309713
Short name T119
Test name
Test status
Simulation time 134814133 ps
CPU time 1.8 seconds
Started Aug 15 06:31:49 PM PDT 24
Finished Aug 15 06:31:51 PM PDT 24
Peak memory 222580 kb
Host smart-af37e4b6-8dca-499f-b8c2-59cd2eac6b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250309713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3250309713
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.65948651
Short name T896
Test name
Test status
Simulation time 116150924 ps
CPU time 1.16 seconds
Started Aug 15 06:31:51 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 219140 kb
Host smart-5743fcb8-bb22-4035-b5df-b417a9f33788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65948651 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.65948651
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3438449352
Short name T173
Test name
Test status
Simulation time 20420809 ps
CPU time 0.97 seconds
Started Aug 15 06:31:48 PM PDT 24
Finished Aug 15 06:31:49 PM PDT 24
Peak memory 209896 kb
Host smart-0d6521ab-230e-4474-887b-91bf83614e91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438449352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3438449352
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3684498103
Short name T997
Test name
Test status
Simulation time 32927990 ps
CPU time 1.06 seconds
Started Aug 15 06:31:50 PM PDT 24
Finished Aug 15 06:31:51 PM PDT 24
Peak memory 210008 kb
Host smart-c9d4ccff-5fbe-44a3-b071-e9da607230ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684498103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3684498103
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.748334905
Short name T919
Test name
Test status
Simulation time 94796273 ps
CPU time 3.27 seconds
Started Aug 15 06:31:51 PM PDT 24
Finished Aug 15 06:31:54 PM PDT 24
Peak memory 218108 kb
Host smart-6030343f-5564-4631-89d5-0de378b5a2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748334905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.748334905
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1330137804
Short name T976
Test name
Test status
Simulation time 118821998 ps
CPU time 1.34 seconds
Started Aug 15 06:31:51 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 218184 kb
Host smart-f19e0874-c9f4-4e8c-b7c1-ffb349cabb22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330137804 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1330137804
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2064997190
Short name T1000
Test name
Test status
Simulation time 18874647 ps
CPU time 1.11 seconds
Started Aug 15 06:31:48 PM PDT 24
Finished Aug 15 06:31:49 PM PDT 24
Peak memory 209968 kb
Host smart-e2c761c5-022c-49fc-a0f1-0f243dfd662c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064997190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2064997190
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.752263238
Short name T954
Test name
Test status
Simulation time 43882052 ps
CPU time 1.29 seconds
Started Aug 15 06:31:48 PM PDT 24
Finished Aug 15 06:31:50 PM PDT 24
Peak memory 209952 kb
Host smart-5c88696a-c78b-449b-b115-c9bcbc4e880d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752263238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.752263238
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2313030993
Short name T97
Test name
Test status
Simulation time 88647468 ps
CPU time 3.06 seconds
Started Aug 15 06:31:49 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 218132 kb
Host smart-f8373d6f-72b4-4c4a-a612-df0d94cd05ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313030993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2313030993
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1738422416
Short name T113
Test name
Test status
Simulation time 695354024 ps
CPU time 2.76 seconds
Started Aug 15 06:31:51 PM PDT 24
Finished Aug 15 06:31:55 PM PDT 24
Peak memory 218100 kb
Host smart-970d2768-8416-4768-a859-2882d4c1b769
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738422416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1738422416
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.333877153
Short name T887
Test name
Test status
Simulation time 27010792 ps
CPU time 1.67 seconds
Started Aug 15 06:31:52 PM PDT 24
Finished Aug 15 06:31:54 PM PDT 24
Peak memory 218320 kb
Host smart-d153fd56-bf24-4e7d-bb28-f8ae738941b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333877153 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.333877153
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.726922558
Short name T141
Test name
Test status
Simulation time 16905413 ps
CPU time 1.14 seconds
Started Aug 15 06:31:52 PM PDT 24
Finished Aug 15 06:31:53 PM PDT 24
Peak memory 209868 kb
Host smart-9fa31f40-b626-4c3d-b9df-707e88c3c9dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726922558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.726922558
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.466847643
Short name T926
Test name
Test status
Simulation time 142165799 ps
CPU time 1.78 seconds
Started Aug 15 06:31:47 PM PDT 24
Finished Aug 15 06:31:49 PM PDT 24
Peak memory 210028 kb
Host smart-c238ee61-92ee-4d73-bde1-eb6663b7610c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466847643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.466847643
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3679014601
Short name T978
Test name
Test status
Simulation time 123624523 ps
CPU time 1.64 seconds
Started Aug 15 06:31:50 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 218212 kb
Host smart-319632a3-b47d-4952-a3fc-68a90291e8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679014601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3679014601
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3073334026
Short name T966
Test name
Test status
Simulation time 20780975 ps
CPU time 1.37 seconds
Started Aug 15 06:31:48 PM PDT 24
Finished Aug 15 06:31:49 PM PDT 24
Peak memory 218092 kb
Host smart-c7f86219-bb7b-4ebf-adc7-1bf0864d132e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073334026 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3073334026
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.427393850
Short name T993
Test name
Test status
Simulation time 20331665 ps
CPU time 1.15 seconds
Started Aug 15 06:31:49 PM PDT 24
Finished Aug 15 06:31:51 PM PDT 24
Peak memory 209884 kb
Host smart-013cccf1-6672-4894-9762-b9b23c64cd4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427393850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.427393850
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.132953910
Short name T907
Test name
Test status
Simulation time 102441310 ps
CPU time 1.35 seconds
Started Aug 15 06:31:50 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 209952 kb
Host smart-885dc53e-601d-4edd-b81d-15e50850f6e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132953910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.132953910
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1077646533
Short name T996
Test name
Test status
Simulation time 384878713 ps
CPU time 2.09 seconds
Started Aug 15 06:31:48 PM PDT 24
Finished Aug 15 06:31:50 PM PDT 24
Peak memory 219160 kb
Host smart-c3185991-f66b-4d76-96be-8ee1016a7ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077646533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1077646533
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4291170373
Short name T111
Test name
Test status
Simulation time 46885726 ps
CPU time 1.77 seconds
Started Aug 15 06:31:50 PM PDT 24
Finished Aug 15 06:31:52 PM PDT 24
Peak memory 222264 kb
Host smart-7ad2d1ac-4af0-466d-9234-d3aa467a2e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291170373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4291170373
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3478454597
Short name T114
Test name
Test status
Simulation time 50689189 ps
CPU time 1.62 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 218268 kb
Host smart-36952606-1a90-4e5f-a669-3ff7d9bfeab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478454597 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3478454597
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3529355646
Short name T179
Test name
Test status
Simulation time 12804148 ps
CPU time 0.88 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 209904 kb
Host smart-e66d7cdd-5dac-4284-a95a-1a83b778a4c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529355646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3529355646
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2561597816
Short name T187
Test name
Test status
Simulation time 18349215 ps
CPU time 0.98 seconds
Started Aug 15 06:31:56 PM PDT 24
Finished Aug 15 06:31:57 PM PDT 24
Peak memory 209976 kb
Host smart-a1e8172d-c8d8-46c1-b398-26343aabf8f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561597816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2561597816
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1091020414
Short name T949
Test name
Test status
Simulation time 505135145 ps
CPU time 2.85 seconds
Started Aug 15 06:31:48 PM PDT 24
Finished Aug 15 06:31:51 PM PDT 24
Peak memory 218128 kb
Host smart-a26e9d25-4ffd-44a4-8b57-ba3c951c238a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091020414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1091020414
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1124489326
Short name T102
Test name
Test status
Simulation time 54469951 ps
CPU time 1.14 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:32:00 PM PDT 24
Peak memory 219916 kb
Host smart-d73f961c-9553-410c-884f-7e5875ff1887
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124489326 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1124489326
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.244826124
Short name T189
Test name
Test status
Simulation time 12228222 ps
CPU time 0.93 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 209884 kb
Host smart-fd143b43-9aef-46a6-8acb-88276614cdd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244826124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.244826124
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.379385977
Short name T959
Test name
Test status
Simulation time 41159068 ps
CPU time 1.28 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 218120 kb
Host smart-21d19415-a411-4ce4-94e4-e24ea768d515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379385977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.379385977
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2967189335
Short name T895
Test name
Test status
Simulation time 98309621 ps
CPU time 3.23 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 218128 kb
Host smart-e0d5e416-2627-42a6-9818-4e1d7e51a3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967189335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2967189335
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1686655523
Short name T126
Test name
Test status
Simulation time 202559297 ps
CPU time 2.02 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 222544 kb
Host smart-4c20830f-76c0-4409-895f-64c67f5ed5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686655523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1686655523
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3064187220
Short name T990
Test name
Test status
Simulation time 86105435 ps
CPU time 1.75 seconds
Started Aug 15 06:32:00 PM PDT 24
Finished Aug 15 06:32:02 PM PDT 24
Peak memory 219744 kb
Host smart-0bef2c2e-fdbe-4937-b662-7802e09bbe42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064187220 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3064187220
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2644302631
Short name T178
Test name
Test status
Simulation time 67056276 ps
CPU time 0.83 seconds
Started Aug 15 06:31:56 PM PDT 24
Finished Aug 15 06:31:57 PM PDT 24
Peak memory 209380 kb
Host smart-08f6ae28-ad6c-49ad-88ae-9639818c254d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644302631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2644302631
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1444896998
Short name T975
Test name
Test status
Simulation time 31784143 ps
CPU time 0.97 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 209932 kb
Host smart-c897df13-fdb7-41f6-84de-2667aa15ee53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444896998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1444896998
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3529164590
Short name T108
Test name
Test status
Simulation time 37190465 ps
CPU time 1.5 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 218340 kb
Host smart-a6c048f8-85c9-44ea-a98c-7a394805f920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529164590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3529164590
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2528332475
Short name T186
Test name
Test status
Simulation time 39477262 ps
CPU time 1.27 seconds
Started Aug 15 06:31:17 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 209960 kb
Host smart-c9ab5fff-1cc9-4b61-ae14-bed6472ed455
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528332475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2528332475
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2385349703
Short name T956
Test name
Test status
Simulation time 20460070 ps
CPU time 1.39 seconds
Started Aug 15 06:31:19 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 209772 kb
Host smart-0671b2ce-de66-41f6-89fc-b841551f6af7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385349703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2385349703
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2137950440
Short name T974
Test name
Test status
Simulation time 54391031 ps
CPU time 1.09 seconds
Started Aug 15 06:31:20 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 210552 kb
Host smart-08fd6e23-8d5c-43b6-b46f-52862e9faba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137950440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2137950440
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1288660082
Short name T890
Test name
Test status
Simulation time 55641797 ps
CPU time 1.59 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 219292 kb
Host smart-33c6843f-3ce9-4ee0-afaf-ff846ca5e03f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288660082 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1288660082
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4187444318
Short name T176
Test name
Test status
Simulation time 36242669 ps
CPU time 0.91 seconds
Started Aug 15 06:31:19 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 209836 kb
Host smart-d7ea6808-0ee2-4724-b1f8-1ed8f7a310d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187444318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4187444318
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3654245996
Short name T951
Test name
Test status
Simulation time 45682120 ps
CPU time 1.11 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 208508 kb
Host smart-668d1a0f-a7c1-4eb8-bfb6-e2af90593d45
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654245996 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3654245996
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.760581298
Short name T905
Test name
Test status
Simulation time 2555835971 ps
CPU time 15.43 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:33 PM PDT 24
Peak memory 209156 kb
Host smart-0f2d9cd6-f133-4d61-87b3-7ffb9cfa947b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760581298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.760581298
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.195459030
Short name T190
Test name
Test status
Simulation time 695749574 ps
CPU time 17.36 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:35 PM PDT 24
Peak memory 209736 kb
Host smart-77def7cd-9009-424c-8bd9-826310ebb7f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195459030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.195459030
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1269762965
Short name T903
Test name
Test status
Simulation time 320334367 ps
CPU time 2.49 seconds
Started Aug 15 06:31:17 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 211356 kb
Host smart-1afff31a-ddb3-41fc-89c9-6385e4401017
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269762965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1269762965
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2634674384
Short name T898
Test name
Test status
Simulation time 221832045 ps
CPU time 2.15 seconds
Started Aug 15 06:31:20 PM PDT 24
Finished Aug 15 06:31:22 PM PDT 24
Peak memory 219164 kb
Host smart-05308ca7-469d-46da-a797-ff4fc1446874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263467
4384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2634674384
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4225543179
Short name T961
Test name
Test status
Simulation time 119669575 ps
CPU time 1.75 seconds
Started Aug 15 06:31:16 PM PDT 24
Finished Aug 15 06:31:18 PM PDT 24
Peak memory 209852 kb
Host smart-fdf4b54f-584b-454c-a45f-8f3b22a0df2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225543179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.4225543179
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3304120169
Short name T939
Test name
Test status
Simulation time 181949996 ps
CPU time 1.93 seconds
Started Aug 15 06:31:17 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 212212 kb
Host smart-4be67b4e-43eb-4d87-a44e-512f58fd3edf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304120169 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3304120169
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1548335282
Short name T104
Test name
Test status
Simulation time 107090227 ps
CPU time 1.29 seconds
Started Aug 15 06:31:16 PM PDT 24
Finished Aug 15 06:31:17 PM PDT 24
Peak memory 210004 kb
Host smart-a6167fff-d781-4262-932c-80f4e44ceb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548335282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1548335282
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2531674382
Short name T894
Test name
Test status
Simulation time 27162640 ps
CPU time 1.67 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 218136 kb
Host smart-fe37eb6d-b74a-4079-b7bc-78a4c4b17a26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531674382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2531674382
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1338110539
Short name T171
Test name
Test status
Simulation time 36624252 ps
CPU time 1.62 seconds
Started Aug 15 06:31:19 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 209840 kb
Host smart-9749e7e0-d754-4eda-9331-e147d72ab5e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338110539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1338110539
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2173190317
Short name T931
Test name
Test status
Simulation time 105564805 ps
CPU time 1.59 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 209852 kb
Host smart-3e7f790b-ac3f-4076-83cc-c394b44e6b3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173190317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2173190317
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.279204198
Short name T929
Test name
Test status
Simulation time 15044208 ps
CPU time 0.88 seconds
Started Aug 15 06:31:21 PM PDT 24
Finished Aug 15 06:31:22 PM PDT 24
Peak memory 209416 kb
Host smart-1380aa1e-650a-4368-ba4f-bc6696c938c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279204198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.279204198
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2921403465
Short name T116
Test name
Test status
Simulation time 92164679 ps
CPU time 1.58 seconds
Started Aug 15 06:31:19 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 218208 kb
Host smart-8d92aaf7-ffb5-4c32-8b1a-7ca6d1898a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921403465 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2921403465
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4214301665
Short name T175
Test name
Test status
Simulation time 22482305 ps
CPU time 1 seconds
Started Aug 15 06:31:19 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 209916 kb
Host smart-5182052e-3d58-483b-b2dd-31de188b7198
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214301665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4214301665
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1474761212
Short name T964
Test name
Test status
Simulation time 631255279 ps
CPU time 3.15 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:22 PM PDT 24
Peak memory 209860 kb
Host smart-ab3be39a-513a-4bb9-b7dd-46bf0accb8a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474761212 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1474761212
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.63103149
Short name T985
Test name
Test status
Simulation time 977803784 ps
CPU time 9.06 seconds
Started Aug 15 06:31:16 PM PDT 24
Finished Aug 15 06:31:25 PM PDT 24
Peak memory 209104 kb
Host smart-864c3f0c-0edf-47a2-9547-d312895c996f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63103149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.63103149
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.794093886
Short name T127
Test name
Test status
Simulation time 315393093 ps
CPU time 1.64 seconds
Started Aug 15 06:31:17 PM PDT 24
Finished Aug 15 06:31:19 PM PDT 24
Peak memory 211500 kb
Host smart-734827a3-b6ae-4e6a-b141-c48cfd650ddc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794093886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.794093886
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2054787234
Short name T973
Test name
Test status
Simulation time 191586298 ps
CPU time 1.43 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 218256 kb
Host smart-69f54a78-cd88-4892-a05e-2607d3c9e94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205478
7234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2054787234
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1245938699
Short name T906
Test name
Test status
Simulation time 119637665 ps
CPU time 1.34 seconds
Started Aug 15 06:31:20 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 209816 kb
Host smart-838e8ff4-d067-41a3-ac32-9926964fd48b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245938699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1245938699
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2692431567
Short name T988
Test name
Test status
Simulation time 30448985 ps
CPU time 0.97 seconds
Started Aug 15 06:31:20 PM PDT 24
Finished Aug 15 06:31:21 PM PDT 24
Peak memory 209956 kb
Host smart-de2c7cc0-d00c-40ea-a2ec-c5a8668ca4fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692431567 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2692431567
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3452915682
Short name T105
Test name
Test status
Simulation time 72758085 ps
CPU time 1.46 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 209996 kb
Host smart-33ec177f-40ce-4018-bd68-e88182b7dd50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452915682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3452915682
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.518062520
Short name T889
Test name
Test status
Simulation time 386879173 ps
CPU time 4.16 seconds
Started Aug 15 06:31:20 PM PDT 24
Finished Aug 15 06:31:24 PM PDT 24
Peak memory 218140 kb
Host smart-9a155957-8d20-41a0-9303-00e526607d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518062520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.518062520
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2711050540
Short name T943
Test name
Test status
Simulation time 34878025 ps
CPU time 1.26 seconds
Started Aug 15 06:31:26 PM PDT 24
Finished Aug 15 06:31:28 PM PDT 24
Peak memory 209936 kb
Host smart-4b2b8fb7-6b5d-4813-893b-f8ca8430cd2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711050540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2711050540
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3161282800
Short name T183
Test name
Test status
Simulation time 163346270 ps
CPU time 1.98 seconds
Started Aug 15 06:31:26 PM PDT 24
Finished Aug 15 06:31:28 PM PDT 24
Peak memory 209884 kb
Host smart-b940d6d1-9bd2-4690-8a12-eafea525a72f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161282800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3161282800
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.233140114
Short name T932
Test name
Test status
Simulation time 39394898 ps
CPU time 1.22 seconds
Started Aug 15 06:31:27 PM PDT 24
Finished Aug 15 06:31:29 PM PDT 24
Peak memory 212248 kb
Host smart-9506ac1f-06a4-413a-8dba-59dd92328f61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233140114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.233140114
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4180302671
Short name T962
Test name
Test status
Simulation time 48740509 ps
CPU time 1.22 seconds
Started Aug 15 06:31:24 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 222708 kb
Host smart-3abcde1d-ef82-4544-bae1-ec98d4ebecc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180302671 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.4180302671
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1512877264
Short name T172
Test name
Test status
Simulation time 12979591 ps
CPU time 1 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 209712 kb
Host smart-8e00cb41-8743-408a-a731-405249c2e154
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512877264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1512877264
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.278179734
Short name T928
Test name
Test status
Simulation time 420535548 ps
CPU time 1.06 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 209796 kb
Host smart-7cfb2924-15c9-4174-bbcc-b2026109c05f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278179734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.278179734
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3086559561
Short name T886
Test name
Test status
Simulation time 190836572 ps
CPU time 5.23 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 209696 kb
Host smart-aaf45bed-edc2-4b0a-ab53-47ea4222c319
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086559561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3086559561
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2014454635
Short name T881
Test name
Test status
Simulation time 2785492160 ps
CPU time 7.85 seconds
Started Aug 15 06:31:26 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 209920 kb
Host smart-a690ef42-753f-4a5b-b2c0-2a4aae73725b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014454635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2014454635
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2213114709
Short name T930
Test name
Test status
Simulation time 73642861 ps
CPU time 1.47 seconds
Started Aug 15 06:31:18 PM PDT 24
Finished Aug 15 06:31:20 PM PDT 24
Peak memory 211268 kb
Host smart-9d771d5b-8826-4134-be22-206bbb4028b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213114709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2213114709
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1448567961
Short name T888
Test name
Test status
Simulation time 63822014 ps
CPU time 1.51 seconds
Started Aug 15 06:31:26 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 219344 kb
Host smart-d5ab4427-1111-4536-82ac-f026f5323a35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144856
7961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1448567961
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1416856551
Short name T910
Test name
Test status
Simulation time 66420572 ps
CPU time 1 seconds
Started Aug 15 06:31:24 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 209796 kb
Host smart-206f9b49-5977-4b89-8cfc-d5278ffbca03
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416856551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1416856551
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1784077512
Short name T188
Test name
Test status
Simulation time 77877803 ps
CPU time 1.02 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 209968 kb
Host smart-95d6004f-e36f-4c6a-9811-f492d19f558c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784077512 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1784077512
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.760573827
Short name T901
Test name
Test status
Simulation time 58506473 ps
CPU time 1.32 seconds
Started Aug 15 06:31:28 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 209892 kb
Host smart-87910ac9-a111-415a-b13e-ea3dcd5f9859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760573827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.760573827
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2404218409
Short name T914
Test name
Test status
Simulation time 52568193 ps
CPU time 1.58 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 218288 kb
Host smart-43fa58a7-e566-44b1-a2e7-b80db12e1e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404218409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2404218409
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4175624210
Short name T120
Test name
Test status
Simulation time 79792477 ps
CPU time 1.96 seconds
Started Aug 15 06:31:28 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 222176 kb
Host smart-b0d073c3-441e-49a8-aa06-da1cdd7fa706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175624210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4175624210
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.915115975
Short name T972
Test name
Test status
Simulation time 35811718 ps
CPU time 1.74 seconds
Started Aug 15 06:31:24 PM PDT 24
Finished Aug 15 06:31:25 PM PDT 24
Peak memory 218436 kb
Host smart-e2190a9d-02e3-4676-b4b3-7390b026a075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915115975 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.915115975
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.579018669
Short name T177
Test name
Test status
Simulation time 20477652 ps
CPU time 0.82 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 209736 kb
Host smart-53b26b41-06de-4e92-9aa3-126debdc4dc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579018669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.579018669
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2430910632
Short name T924
Test name
Test status
Simulation time 228447431 ps
CPU time 1.8 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 208656 kb
Host smart-a368f44a-42d8-43cf-8df0-00b2056b35d8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430910632 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2430910632
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1385020647
Short name T129
Test name
Test status
Simulation time 2499165105 ps
CPU time 5.84 seconds
Started Aug 15 06:31:26 PM PDT 24
Finished Aug 15 06:31:32 PM PDT 24
Peak memory 209928 kb
Host smart-35706a98-ee41-4312-b6b3-f54962958d86
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385020647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1385020647
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3026351035
Short name T965
Test name
Test status
Simulation time 2485272974 ps
CPU time 15.29 seconds
Started Aug 15 06:31:27 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 209884 kb
Host smart-31347f78-1816-4c49-a3aa-75c837f859a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026351035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3026351035
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2341661516
Short name T925
Test name
Test status
Simulation time 94917006 ps
CPU time 3.05 seconds
Started Aug 15 06:31:27 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 211648 kb
Host smart-ccc9be7c-a026-4f00-9289-3efe59878314
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341661516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2341661516
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1068863723
Short name T968
Test name
Test status
Simulation time 116491262 ps
CPU time 2.24 seconds
Started Aug 15 06:31:25 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 218904 kb
Host smart-9e646a1c-df5c-4d05-b92a-a621ae25f866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106886
3723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1068863723
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.805458575
Short name T876
Test name
Test status
Simulation time 135455790 ps
CPU time 1.57 seconds
Started Aug 15 06:31:24 PM PDT 24
Finished Aug 15 06:31:26 PM PDT 24
Peak memory 209804 kb
Host smart-a5265866-d45b-4e6a-9a47-5e6f3fa6fe1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805458575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.805458575
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1247916635
Short name T940
Test name
Test status
Simulation time 72360937 ps
CPU time 1.82 seconds
Started Aug 15 06:31:28 PM PDT 24
Finished Aug 15 06:31:30 PM PDT 24
Peak memory 218024 kb
Host smart-b728cbdf-ffa8-4194-95a2-d4f3bb98a524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247916635 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1247916635
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1290290497
Short name T140
Test name
Test status
Simulation time 187237631 ps
CPU time 1.44 seconds
Started Aug 15 06:31:26 PM PDT 24
Finished Aug 15 06:31:28 PM PDT 24
Peak memory 211992 kb
Host smart-86522883-ac15-437c-967b-0b7b2093ebe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290290497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1290290497
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3223505128
Short name T913
Test name
Test status
Simulation time 654469356 ps
CPU time 5.1 seconds
Started Aug 15 06:31:27 PM PDT 24
Finished Aug 15 06:31:32 PM PDT 24
Peak memory 218140 kb
Host smart-3464ef7e-2863-492d-9413-a731ec12f62a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223505128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3223505128
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1311556931
Short name T935
Test name
Test status
Simulation time 188579788 ps
CPU time 5.11 seconds
Started Aug 15 06:31:29 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 218168 kb
Host smart-0d4d6073-fef8-44f6-bc23-903024beb1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311556931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1311556931
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1294728933
Short name T995
Test name
Test status
Simulation time 56703845 ps
CPU time 1.15 seconds
Started Aug 15 06:31:33 PM PDT 24
Finished Aug 15 06:31:35 PM PDT 24
Peak memory 219252 kb
Host smart-67a8a3ed-21b7-4424-9672-dec43451e716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294728933 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1294728933
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.118706870
Short name T948
Test name
Test status
Simulation time 13793012 ps
CPU time 1.04 seconds
Started Aug 15 06:31:31 PM PDT 24
Finished Aug 15 06:31:32 PM PDT 24
Peak memory 209708 kb
Host smart-eece40ca-03b0-49d3-8304-a9a4f3c1f6d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118706870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.118706870
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2861184311
Short name T877
Test name
Test status
Simulation time 110718034 ps
CPU time 1.19 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 209804 kb
Host smart-1aa37057-5526-44b9-8105-acc20622e8bf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861184311 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2861184311
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3284855672
Short name T998
Test name
Test status
Simulation time 518688132 ps
CPU time 5.22 seconds
Started Aug 15 06:31:33 PM PDT 24
Finished Aug 15 06:31:39 PM PDT 24
Peak memory 209712 kb
Host smart-85933ae8-787b-429f-bd48-e94e6fca24de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284855672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3284855672
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3314668460
Short name T916
Test name
Test status
Simulation time 352742398 ps
CPU time 9.19 seconds
Started Aug 15 06:31:26 PM PDT 24
Finished Aug 15 06:31:35 PM PDT 24
Peak memory 209672 kb
Host smart-2a9bccd8-e45e-4c89-8419-7939210a8e77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314668460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3314668460
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1101832872
Short name T109
Test name
Test status
Simulation time 81239621 ps
CPU time 2.63 seconds
Started Aug 15 06:31:24 PM PDT 24
Finished Aug 15 06:31:27 PM PDT 24
Peak memory 211704 kb
Host smart-2672f2e3-0580-4f96-bb47-e4e83c3dcdc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101832872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1101832872
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4051196457
Short name T899
Test name
Test status
Simulation time 2383764664 ps
CPU time 2.66 seconds
Started Aug 15 06:31:38 PM PDT 24
Finished Aug 15 06:31:40 PM PDT 24
Peak memory 218368 kb
Host smart-3e5b6414-3a1b-4cf5-b79c-45af386a203d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405119
6457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4051196457
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1360041408
Short name T131
Test name
Test status
Simulation time 324994068 ps
CPU time 1.61 seconds
Started Aug 15 06:31:27 PM PDT 24
Finished Aug 15 06:31:28 PM PDT 24
Peak memory 209860 kb
Host smart-bc51ac5f-7825-4794-a02e-2cab4abac08a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360041408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1360041408
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.160493922
Short name T912
Test name
Test status
Simulation time 126353019 ps
CPU time 1.39 seconds
Started Aug 15 06:31:31 PM PDT 24
Finished Aug 15 06:31:33 PM PDT 24
Peak memory 211980 kb
Host smart-7ff5e421-fd36-4266-8c76-56b3d3e3f9cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160493922 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.160493922
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2688910017
Short name T977
Test name
Test status
Simulation time 179161596 ps
CPU time 1.5 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 211876 kb
Host smart-b28cfbac-ab5d-4576-bf28-36f6b8149fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688910017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2688910017
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1088917335
Short name T941
Test name
Test status
Simulation time 612347152 ps
CPU time 4.23 seconds
Started Aug 15 06:31:34 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 218128 kb
Host smart-dcf35200-86ab-4f18-a06a-e7ddb6b1ea57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088917335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1088917335
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.902873151
Short name T944
Test name
Test status
Simulation time 17515538 ps
CPU time 1.19 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:33 PM PDT 24
Peak memory 218404 kb
Host smart-d7082cdf-9f08-49a3-813a-ef1fccf7b8bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902873151 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.902873151
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4254811158
Short name T103
Test name
Test status
Simulation time 14463851 ps
CPU time 1.03 seconds
Started Aug 15 06:31:37 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 209952 kb
Host smart-b30e8b88-c865-499a-8ffc-568e4478e062
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254811158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4254811158
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1318932798
Short name T960
Test name
Test status
Simulation time 107202908 ps
CPU time 0.97 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:33 PM PDT 24
Peak memory 208480 kb
Host smart-b551bae0-7350-4941-8a1d-2aa3d79d5e67
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318932798 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1318932798
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.236058885
Short name T911
Test name
Test status
Simulation time 264467946 ps
CPU time 6.95 seconds
Started Aug 15 06:31:34 PM PDT 24
Finished Aug 15 06:31:41 PM PDT 24
Peak memory 209700 kb
Host smart-0af64d09-6f02-4792-88d9-40d6c8234957
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236058885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.236058885
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1293993927
Short name T921
Test name
Test status
Simulation time 2358819310 ps
CPU time 24.21 seconds
Started Aug 15 06:31:31 PM PDT 24
Finished Aug 15 06:31:55 PM PDT 24
Peak memory 209208 kb
Host smart-b7bdefe0-4128-4829-b148-40b88bf6fba7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293993927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1293993927
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2120107874
Short name T992
Test name
Test status
Simulation time 301676807 ps
CPU time 2.37 seconds
Started Aug 15 06:31:37 PM PDT 24
Finished Aug 15 06:31:39 PM PDT 24
Peak memory 211420 kb
Host smart-18b67b19-b4ee-43f2-a37b-79ca1d62947f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120107874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2120107874
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.684720643
Short name T165
Test name
Test status
Simulation time 237820781 ps
CPU time 2.49 seconds
Started Aug 15 06:31:31 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 218144 kb
Host smart-d58d9e56-c962-43b5-a26f-ff8799929175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684720
643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.684720643
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1909693975
Short name T945
Test name
Test status
Simulation time 287178488 ps
CPU time 3.78 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:36 PM PDT 24
Peak memory 209860 kb
Host smart-f396c13a-9530-40cd-ad21-ca99d5a923e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909693975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1909693975
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1935399525
Short name T917
Test name
Test status
Simulation time 151337303 ps
CPU time 1.25 seconds
Started Aug 15 06:31:34 PM PDT 24
Finished Aug 15 06:31:36 PM PDT 24
Peak memory 209908 kb
Host smart-690546d1-b1ec-42e1-8815-e366e0de2d6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935399525 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1935399525
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2574408380
Short name T946
Test name
Test status
Simulation time 17184968 ps
CPU time 1.21 seconds
Started Aug 15 06:31:37 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 209960 kb
Host smart-9a5b4d75-bbf4-4575-b1f8-e22c07ef87ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574408380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2574408380
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1400052022
Short name T971
Test name
Test status
Simulation time 78564928 ps
CPU time 3.04 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:35 PM PDT 24
Peak memory 218532 kb
Host smart-23c383ae-715c-4d4e-9728-9947450d27c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400052022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1400052022
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3980468418
Short name T124
Test name
Test status
Simulation time 200320233 ps
CPU time 3.36 seconds
Started Aug 15 06:31:33 PM PDT 24
Finished Aug 15 06:31:37 PM PDT 24
Peak memory 214032 kb
Host smart-4fe45cea-e445-48ae-99a6-9151fb9b935b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980468418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3980468418
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.32330075
Short name T957
Test name
Test status
Simulation time 57173597 ps
CPU time 1.42 seconds
Started Aug 15 06:31:42 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 219888 kb
Host smart-3ecbeb38-5483-4b4f-9c4c-c14c9022aec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32330075 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.32330075
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3065144084
Short name T185
Test name
Test status
Simulation time 67871966 ps
CPU time 0.8 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 209092 kb
Host smart-ee053dec-1c6a-4897-8d30-f67116b9b247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065144084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3065144084
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1130557249
Short name T880
Test name
Test status
Simulation time 112226842 ps
CPU time 0.94 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:33 PM PDT 24
Peak memory 209820 kb
Host smart-0b71016f-af30-4947-a827-b745944f0197
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130557249 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1130557249
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1308259568
Short name T950
Test name
Test status
Simulation time 1906150945 ps
CPU time 6.76 seconds
Started Aug 15 06:31:31 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 209700 kb
Host smart-dd608686-5380-4796-9c42-164520aae616
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308259568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1308259568
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3562419093
Short name T981
Test name
Test status
Simulation time 3047869647 ps
CPU time 18.03 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:50 PM PDT 24
Peak memory 209868 kb
Host smart-5c51aeac-c312-4f88-97e5-daf96900b226
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562419093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3562419093
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2728173254
Short name T987
Test name
Test status
Simulation time 110066711 ps
CPU time 3.22 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:36 PM PDT 24
Peak memory 211604 kb
Host smart-5ab069fc-2637-47bf-b153-5cbfd1119c63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728173254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2728173254
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2685892036
Short name T897
Test name
Test status
Simulation time 581361654 ps
CPU time 2.34 seconds
Started Aug 15 06:31:31 PM PDT 24
Finished Aug 15 06:31:34 PM PDT 24
Peak memory 218200 kb
Host smart-193ea5c8-785f-4106-ba28-c61f1c254947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268589
2036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2685892036
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2256506993
Short name T983
Test name
Test status
Simulation time 138923977 ps
CPU time 2.08 seconds
Started Aug 15 06:31:32 PM PDT 24
Finished Aug 15 06:31:35 PM PDT 24
Peak memory 209776 kb
Host smart-ed882278-ab64-4138-bd9a-f75f2df841d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256506993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2256506993
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3203945945
Short name T920
Test name
Test status
Simulation time 103971476 ps
CPU time 1.43 seconds
Started Aug 15 06:31:34 PM PDT 24
Finished Aug 15 06:31:36 PM PDT 24
Peak memory 218220 kb
Host smart-bde6fc22-fad2-41c0-8442-fb2b93a68714
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203945945 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3203945945
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3483498367
Short name T902
Test name
Test status
Simulation time 216992817 ps
CPU time 1.08 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:43 PM PDT 24
Peak memory 209948 kb
Host smart-d07498e9-764e-47c3-83c7-ce1267a3bacc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483498367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3483498367
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.181036370
Short name T986
Test name
Test status
Simulation time 168719020 ps
CPU time 3.41 seconds
Started Aug 15 06:31:34 PM PDT 24
Finished Aug 15 06:31:38 PM PDT 24
Peak memory 219120 kb
Host smart-beb9911c-1e42-4b91-a7be-3250d87454b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181036370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.181036370
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2652022514
Short name T181
Test name
Test status
Simulation time 39576874 ps
CPU time 0.92 seconds
Started Aug 15 06:31:42 PM PDT 24
Finished Aug 15 06:31:43 PM PDT 24
Peak memory 209948 kb
Host smart-46edcfde-f130-4029-a470-b0ba4c9f9992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652022514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2652022514
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2430334389
Short name T892
Test name
Test status
Simulation time 348774451 ps
CPU time 1.46 seconds
Started Aug 15 06:31:40 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 209860 kb
Host smart-20a37647-5fb9-409f-9778-4d9a329bddf2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430334389 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2430334389
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2129402711
Short name T989
Test name
Test status
Simulation time 805068400 ps
CPU time 5.02 seconds
Started Aug 15 06:31:42 PM PDT 24
Finished Aug 15 06:31:47 PM PDT 24
Peak memory 209208 kb
Host smart-ccaa5ab1-38cf-42b1-89d1-425e4816d910
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129402711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2129402711
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1640845924
Short name T884
Test name
Test status
Simulation time 2613782911 ps
CPU time 13.22 seconds
Started Aug 15 06:31:39 PM PDT 24
Finished Aug 15 06:31:53 PM PDT 24
Peak memory 209912 kb
Host smart-dad6c863-b12b-4d4e-b495-c03b79e661e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640845924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1640845924
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1462140538
Short name T879
Test name
Test status
Simulation time 291949616 ps
CPU time 3.21 seconds
Started Aug 15 06:31:39 PM PDT 24
Finished Aug 15 06:31:43 PM PDT 24
Peak memory 211548 kb
Host smart-fe659039-981f-4f85-b996-01786bd3729c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462140538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1462140538
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.372407505
Short name T982
Test name
Test status
Simulation time 1017926000 ps
CPU time 6.12 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:48 PM PDT 24
Peak memory 222860 kb
Host smart-5db71840-d71a-4a85-af93-b31845f3cfb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372407
505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.372407505
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3034478301
Short name T942
Test name
Test status
Simulation time 301934084 ps
CPU time 1.19 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:43 PM PDT 24
Peak memory 209832 kb
Host smart-84c53bec-531d-486f-bf4f-aeaa4cf2b62f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034478301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3034478301
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2847910421
Short name T139
Test name
Test status
Simulation time 379878275 ps
CPU time 1.87 seconds
Started Aug 15 06:31:42 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 210236 kb
Host smart-4831959c-865c-4538-b710-e3b44372a2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847910421 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2847910421
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3653887293
Short name T947
Test name
Test status
Simulation time 26843385 ps
CPU time 0.99 seconds
Started Aug 15 06:31:40 PM PDT 24
Finished Aug 15 06:31:42 PM PDT 24
Peak memory 209924 kb
Host smart-0816ca2e-59c5-47d1-afa0-142c3822b708
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653887293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3653887293
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1459462047
Short name T915
Test name
Test status
Simulation time 277763795 ps
CPU time 2.45 seconds
Started Aug 15 06:31:41 PM PDT 24
Finished Aug 15 06:31:44 PM PDT 24
Peak memory 218132 kb
Host smart-e56fbe35-75e1-42bf-8052-6cb327fd32e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459462047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1459462047
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3917601606
Short name T489
Test name
Test status
Simulation time 20736226 ps
CPU time 0.93 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:05:59 PM PDT 24
Peak memory 208800 kb
Host smart-7a9235c4-61e4-4adf-8ee6-4ba5719a3b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917601606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3917601606
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.287815060
Short name T291
Test name
Test status
Simulation time 898493955 ps
CPU time 19.23 seconds
Started Aug 15 06:05:43 PM PDT 24
Finished Aug 15 06:06:03 PM PDT 24
Peak memory 218160 kb
Host smart-1784f909-3724-42be-a85b-89e4bf3c0805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287815060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.287815060
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1518222048
Short name T514
Test name
Test status
Simulation time 2570795557 ps
CPU time 7.38 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:15 PM PDT 24
Peak memory 217472 kb
Host smart-b6167099-55bc-4ef9-ab89-ea12845938e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518222048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1518222048
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.411245139
Short name T441
Test name
Test status
Simulation time 3618115142 ps
CPU time 41.36 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:45 PM PDT 24
Peak memory 218884 kb
Host smart-feff21ed-c1e5-47d6-b1b4-ac0388ba04c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411245139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.411245139
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.695506857
Short name T750
Test name
Test status
Simulation time 444673818 ps
CPU time 11.13 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 217340 kb
Host smart-fa33c562-dc78-453e-bb7d-8f948168b4c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695506857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.695506857
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2856384452
Short name T245
Test name
Test status
Simulation time 2760625664 ps
CPU time 10.99 seconds
Started Aug 15 06:05:50 PM PDT 24
Finished Aug 15 06:06:02 PM PDT 24
Peak memory 218296 kb
Host smart-3af790af-3fd8-405c-b2a5-da25c2a4c90b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856384452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2856384452
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.246163668
Short name T63
Test name
Test status
Simulation time 4790819574 ps
CPU time 17.66 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:19 PM PDT 24
Peak memory 217628 kb
Host smart-d7824720-ff04-4919-a7a8-fc4396b593fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246163668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.246163668
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3461094922
Short name T160
Test name
Test status
Simulation time 402038872 ps
CPU time 6.69 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:59 PM PDT 24
Peak memory 217580 kb
Host smart-45b7a1c2-d5c7-4597-a131-8a4b06901182
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461094922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3461094922
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.413931009
Short name T497
Test name
Test status
Simulation time 6343219530 ps
CPU time 57.9 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:06:54 PM PDT 24
Peak memory 253676 kb
Host smart-2cf2cd7e-bbe2-4c8c-9b37-3dd252aedb57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413931009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.413931009
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1401513913
Short name T658
Test name
Test status
Simulation time 2091101546 ps
CPU time 18.82 seconds
Started Aug 15 06:05:50 PM PDT 24
Finished Aug 15 06:06:09 PM PDT 24
Peak memory 247580 kb
Host smart-2612ad9e-ae57-45b2-b3cd-cc71396a1ed6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401513913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1401513913
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.514660250
Short name T694
Test name
Test status
Simulation time 461437678 ps
CPU time 3.53 seconds
Started Aug 15 06:05:59 PM PDT 24
Finished Aug 15 06:06:02 PM PDT 24
Peak memory 218284 kb
Host smart-6bc2326a-4257-4ac3-ba4a-d18216d2adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514660250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.514660250
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1670721997
Short name T359
Test name
Test status
Simulation time 795024442 ps
CPU time 5.52 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:06:02 PM PDT 24
Peak memory 217620 kb
Host smart-2f99ded4-da9b-46a3-886d-8d5bf7c25a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670721997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1670721997
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3958458511
Short name T709
Test name
Test status
Simulation time 2596312074 ps
CPU time 16.6 seconds
Started Aug 15 06:05:54 PM PDT 24
Finished Aug 15 06:06:10 PM PDT 24
Peak memory 219280 kb
Host smart-d55c9415-efdd-47ee-b631-de43a31e41ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958458511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3958458511
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2126238316
Short name T296
Test name
Test status
Simulation time 867732183 ps
CPU time 9.66 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 226164 kb
Host smart-c34be272-83bc-4b0a-8ede-9863c6cdac60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126238316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2126238316
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1309014150
Short name T360
Test name
Test status
Simulation time 925471208 ps
CPU time 8.03 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:06:05 PM PDT 24
Peak memory 218236 kb
Host smart-b023c53c-1639-4746-935a-6f894a9ea00f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309014150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
309014150
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.198864653
Short name T492
Test name
Test status
Simulation time 871416061 ps
CPU time 7.87 seconds
Started Aug 15 06:06:00 PM PDT 24
Finished Aug 15 06:06:08 PM PDT 24
Peak memory 225700 kb
Host smart-ab53cb50-3657-4b69-a753-1a1b94b0bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198864653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.198864653
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3259059322
Short name T502
Test name
Test status
Simulation time 102201007 ps
CPU time 1.92 seconds
Started Aug 15 06:06:14 PM PDT 24
Finished Aug 15 06:06:16 PM PDT 24
Peak memory 217584 kb
Host smart-70e5f5f5-676a-4945-9a99-4b38e7c2f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259059322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3259059322
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.305319866
Short name T405
Test name
Test status
Simulation time 310196003 ps
CPU time 30.67 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 250828 kb
Host smart-80942faa-1a2d-4c5a-9702-fdd0b76365af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305319866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.305319866
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3137099740
Short name T396
Test name
Test status
Simulation time 73286061 ps
CPU time 8.4 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:22 PM PDT 24
Peak memory 250844 kb
Host smart-3f33329e-3405-4691-a15c-1fd568382e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137099740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3137099740
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2682104551
Short name T570
Test name
Test status
Simulation time 7557990406 ps
CPU time 296.55 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:10:48 PM PDT 24
Peak memory 275776 kb
Host smart-192e6122-e451-43a1-96a9-237756ff0dac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682104551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2682104551
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4008913300
Short name T135
Test name
Test status
Simulation time 18937137223 ps
CPU time 82.38 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 259152 kb
Host smart-21ac70b2-9a43-448e-af35-e655ecb3012e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4008913300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.4008913300
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3144770457
Short name T205
Test name
Test status
Simulation time 28402794 ps
CPU time 0.88 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 208808 kb
Host smart-57a5066c-fdca-4cd8-a11b-8ac80d07a239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144770457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3144770457
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2637159341
Short name T594
Test name
Test status
Simulation time 38736379 ps
CPU time 0.92 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 208720 kb
Host smart-c09d405c-cdc4-47d1-b18a-aa0bd0b76ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637159341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2637159341
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.189484439
Short name T300
Test name
Test status
Simulation time 217392775 ps
CPU time 8.49 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:19 PM PDT 24
Peak memory 218152 kb
Host smart-45f009df-817b-4507-838b-38ce2bc09b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189484439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.189484439
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4082180637
Short name T149
Test name
Test status
Simulation time 343631671 ps
CPU time 6.62 seconds
Started Aug 15 06:05:55 PM PDT 24
Finished Aug 15 06:06:02 PM PDT 24
Peak memory 217104 kb
Host smart-045a4a4f-931b-414b-8da2-7898ad5d941c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082180637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4082180637
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2893442674
Short name T670
Test name
Test status
Simulation time 21081550391 ps
CPU time 92.44 seconds
Started Aug 15 06:06:02 PM PDT 24
Finished Aug 15 06:07:35 PM PDT 24
Peak memory 219876 kb
Host smart-2e2ab28a-ffcb-412e-ae77-61ce92bea9fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893442674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2893442674
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3922409997
Short name T577
Test name
Test status
Simulation time 8964037908 ps
CPU time 17.82 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:06:16 PM PDT 24
Peak memory 217776 kb
Host smart-980eb2bc-2b7a-46d8-86b6-64934af1f011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922409997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
922409997
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1780380570
Short name T544
Test name
Test status
Simulation time 554542397 ps
CPU time 8.2 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:06:00 PM PDT 24
Peak memory 218252 kb
Host smart-e55aa7d5-7520-4c1f-8049-b8ec337c3d2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780380570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1780380570
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1494425909
Short name T732
Test name
Test status
Simulation time 1034119788 ps
CPU time 21.49 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 217560 kb
Host smart-ba8f3778-38d4-45f9-9e31-a7084fff74d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494425909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1494425909
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4282173059
Short name T851
Test name
Test status
Simulation time 276824372 ps
CPU time 1.72 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 217552 kb
Host smart-98a47c59-cc18-4958-affd-2f69a9338429
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282173059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
4282173059
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3978197201
Short name T329
Test name
Test status
Simulation time 1650944297 ps
CPU time 40.67 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:06:39 PM PDT 24
Peak memory 267232 kb
Host smart-c64bc5c3-4688-4293-80e9-195ad6630fb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978197201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3978197201
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.243249214
Short name T772
Test name
Test status
Simulation time 1798540887 ps
CPU time 16.03 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:06:03 PM PDT 24
Peak memory 246188 kb
Host smart-0bc49d61-8129-45b5-a714-52ec4fe4e8c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243249214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.243249214
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.163581330
Short name T262
Test name
Test status
Simulation time 87430137 ps
CPU time 4.11 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:10 PM PDT 24
Peak memory 218280 kb
Host smart-3e1cc18a-3b59-4cd9-9a03-b5283d729ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163581330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.163581330
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1243550520
Short name T763
Test name
Test status
Simulation time 919275012 ps
CPU time 6.53 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 217628 kb
Host smart-7357e664-29fa-46bb-bcb3-0f6723e692ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243550520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1243550520
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3202125569
Short name T82
Test name
Test status
Simulation time 222419737 ps
CPU time 25.89 seconds
Started Aug 15 06:05:54 PM PDT 24
Finished Aug 15 06:06:20 PM PDT 24
Peak memory 269364 kb
Host smart-235c652c-f8cf-4fe2-8d7f-e338fa3c0611
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202125569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3202125569
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.802077401
Short name T388
Test name
Test status
Simulation time 1194808393 ps
CPU time 15.84 seconds
Started Aug 15 06:05:59 PM PDT 24
Finished Aug 15 06:06:15 PM PDT 24
Peak memory 226060 kb
Host smart-a51a303b-8d0b-4435-afb5-30ba7d0c8adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802077401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.802077401
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.405329743
Short name T653
Test name
Test status
Simulation time 2473395520 ps
CPU time 14.63 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:22 PM PDT 24
Peak memory 226004 kb
Host smart-3e3f7448-1a70-4484-863d-10197d6737a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405329743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.405329743
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1809651970
Short name T487
Test name
Test status
Simulation time 303404919 ps
CPU time 12.21 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:06:06 PM PDT 24
Peak memory 218148 kb
Host smart-5c28f980-1909-4c42-9e09-68a8d384480b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809651970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
809651970
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3117823586
Short name T335
Test name
Test status
Simulation time 548291646 ps
CPU time 10.09 seconds
Started Aug 15 06:05:55 PM PDT 24
Finished Aug 15 06:06:05 PM PDT 24
Peak memory 226024 kb
Host smart-1fd9141b-7149-40fc-b9d2-308a0d3ffc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117823586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3117823586
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3129721495
Short name T848
Test name
Test status
Simulation time 94794339 ps
CPU time 3.11 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:19 PM PDT 24
Peak memory 217616 kb
Host smart-a1274ee3-ffa5-425d-b769-779981aff8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129721495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3129721495
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1179229390
Short name T827
Test name
Test status
Simulation time 319476145 ps
CPU time 30.23 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:06:27 PM PDT 24
Peak memory 250928 kb
Host smart-470d46fe-77c4-404d-b9d9-5bc4ce013351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179229390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1179229390
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1058516776
Short name T822
Test name
Test status
Simulation time 57028754 ps
CPU time 7.18 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:17 PM PDT 24
Peak memory 243320 kb
Host smart-f8cb8f7c-8570-4f44-a689-41fdbb7e7218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058516776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1058516776
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3499817157
Short name T475
Test name
Test status
Simulation time 41702189430 ps
CPU time 91.16 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 253096 kb
Host smart-147a6f72-d769-4b50-944c-ac3acb8e75fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499817157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3499817157
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2837783137
Short name T859
Test name
Test status
Simulation time 25813891675 ps
CPU time 105.48 seconds
Started Aug 15 06:06:08 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 281752 kb
Host smart-9cea6b56-2fc4-41d3-a47f-bd0d3686292b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2837783137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2837783137
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1562057366
Short name T584
Test name
Test status
Simulation time 17131883 ps
CPU time 0.89 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:07 PM PDT 24
Peak memory 211920 kb
Host smart-489b69da-20a0-483e-b644-38f2850e2d4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562057366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1562057366
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.4033750559
Short name T301
Test name
Test status
Simulation time 18529629 ps
CPU time 0.98 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:06:34 PM PDT 24
Peak memory 208860 kb
Host smart-53afdc9d-1457-45fb-8544-791d57180af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033750559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4033750559
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.83456647
Short name T520
Test name
Test status
Simulation time 2432251409 ps
CPU time 14.16 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 218336 kb
Host smart-c79ff2cb-d52b-468a-9442-9d91748f4ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83456647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.83456647
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1130267804
Short name T674
Test name
Test status
Simulation time 103856363 ps
CPU time 1.75 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:27 PM PDT 24
Peak memory 217624 kb
Host smart-da338542-6874-4aa6-8cdf-379f2d7d6f28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130267804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1130267804
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1381324617
Short name T6
Test name
Test status
Simulation time 2869429002 ps
CPU time 49.89 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 218924 kb
Host smart-9b6a54df-e99d-4065-85ef-ba995710a755
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381324617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1381324617
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1728125280
Short name T835
Test name
Test status
Simulation time 481150483 ps
CPU time 7.1 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 218184 kb
Host smart-3b959f29-0617-4100-9c6e-3331cf4a2124
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728125280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1728125280
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.266469995
Short name T337
Test name
Test status
Simulation time 139172386 ps
CPU time 3.04 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 217560 kb
Host smart-0f566545-1cdc-4bca-9669-1a935a8c5765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266469995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
266469995
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3470533136
Short name T792
Test name
Test status
Simulation time 5489399087 ps
CPU time 55.85 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 253640 kb
Host smart-f23f7000-eac2-4ff3-be95-5e2d82361c14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470533136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3470533136
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3996289499
Short name T513
Test name
Test status
Simulation time 1509998435 ps
CPU time 11.6 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:06:45 PM PDT 24
Peak memory 250420 kb
Host smart-fe5d5ea8-7a99-4126-85fb-61afe2e08813
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996289499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3996289499
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1070907652
Short name T559
Test name
Test status
Simulation time 109359902 ps
CPU time 4.52 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 218236 kb
Host smart-feddba05-27ba-4259-8dfa-514edcabc038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070907652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1070907652
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3766302308
Short name T471
Test name
Test status
Simulation time 192482973 ps
CPU time 8.14 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 226076 kb
Host smart-9a353c17-1510-46fb-8dd6-f8511fdd7784
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766302308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3766302308
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.940007822
Short name T767
Test name
Test status
Simulation time 6540625212 ps
CPU time 19.75 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 226092 kb
Host smart-ccf6bf71-69e4-4183-934b-2c1c8c29ec0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940007822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.940007822
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.425818919
Short name T611
Test name
Test status
Simulation time 201526174 ps
CPU time 6.16 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:28 PM PDT 24
Peak memory 218204 kb
Host smart-3cd47d25-b94d-4885-bff7-4c855c2b7599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425818919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.425818919
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1726682603
Short name T51
Test name
Test status
Simulation time 311348400 ps
CPU time 8.79 seconds
Started Aug 15 06:06:16 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 226024 kb
Host smart-3a2f1b5f-f1bd-40c1-83c5-93dcd69ccd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726682603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1726682603
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3185432882
Short name T840
Test name
Test status
Simulation time 164523977 ps
CPU time 2.73 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:06:33 PM PDT 24
Peak memory 214752 kb
Host smart-7b9aa4d8-3155-44ab-8338-d38eed050b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185432882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3185432882
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1572736209
Short name T144
Test name
Test status
Simulation time 369843337 ps
CPU time 25.69 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:54 PM PDT 24
Peak memory 250904 kb
Host smart-04760c52-1417-4b4b-936a-46813b5d407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572736209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1572736209
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1672876790
Short name T311
Test name
Test status
Simulation time 129235899 ps
CPU time 3.14 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 218160 kb
Host smart-ca8e3d35-67a4-43ac-b787-bb7fd8ec82fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672876790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1672876790
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.461208316
Short name T640
Test name
Test status
Simulation time 23628835 ps
CPU time 0.97 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 211908 kb
Host smart-9e42aabd-2905-4701-8e25-379cf8c9e0e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461208316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.461208316
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.894065949
Short name T208
Test name
Test status
Simulation time 37579447 ps
CPU time 0.94 seconds
Started Aug 15 06:06:34 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 208884 kb
Host smart-28ab3d1c-101c-4d37-850d-703ea468c344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894065949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.894065949
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.682859980
Short name T749
Test name
Test status
Simulation time 1524046119 ps
CPU time 12.41 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:39 PM PDT 24
Peak memory 217928 kb
Host smart-5fef3d70-acb8-4cc4-88c1-4894cdf3b169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682859980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.682859980
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3307108055
Short name T601
Test name
Test status
Simulation time 772252207 ps
CPU time 5.5 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 217436 kb
Host smart-2658487c-8f15-4c4e-b7a6-8c1d54f6934c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307108055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3307108055
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.563287942
Short name T731
Test name
Test status
Simulation time 45650760097 ps
CPU time 50.59 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 218624 kb
Host smart-59695cd4-f286-4c60-9bb4-7a1292056a6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563287942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.563287942
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1601802533
Short name T298
Test name
Test status
Simulation time 265475497 ps
CPU time 3.02 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 218180 kb
Host smart-5eafee50-44cf-45a9-b0da-278ebbdd9b32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601802533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1601802533
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1410393427
Short name T572
Test name
Test status
Simulation time 338818713 ps
CPU time 5.13 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 217584 kb
Host smart-3814e178-b985-4ff6-953e-ff0376d1bb6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410393427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1410393427
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3372171066
Short name T201
Test name
Test status
Simulation time 5917722026 ps
CPU time 58.27 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 275468 kb
Host smart-4c0fb578-1c88-41c9-ac27-16dc5ac90b94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372171066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3372171066
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3722669602
Short name T813
Test name
Test status
Simulation time 2733294786 ps
CPU time 25.18 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 247372 kb
Host smart-96abf5b3-8a6d-4d3e-b924-0c78b6fd941d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722669602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3722669602
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3076895684
Short name T565
Test name
Test status
Simulation time 107390144 ps
CPU time 3.4 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 218412 kb
Host smart-6c6a9514-1ed6-43a7-9943-b5a4b91f3a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076895684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3076895684
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3178339063
Short name T214
Test name
Test status
Simulation time 793781053 ps
CPU time 8.99 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:33 PM PDT 24
Peak memory 218940 kb
Host smart-d2df9f5b-bf88-4491-a6fe-518ce1ddaa56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178339063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3178339063
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1093584387
Short name T712
Test name
Test status
Simulation time 1396202118 ps
CPU time 10.29 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:40 PM PDT 24
Peak memory 226028 kb
Host smart-5a2a8c0d-f002-4ecd-a980-25e9a19c5334
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093584387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1093584387
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2059595441
Short name T313
Test name
Test status
Simulation time 548805938 ps
CPU time 11.36 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:40 PM PDT 24
Peak memory 226016 kb
Host smart-416d3e28-da49-4f6d-8111-c0df8d1ee07d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059595441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2059595441
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.149168657
Short name T716
Test name
Test status
Simulation time 99761202 ps
CPU time 10.07 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 250856 kb
Host smart-8ebea9a4-50a7-4654-8dad-658f8591e367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149168657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.149168657
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2883866628
Short name T440
Test name
Test status
Simulation time 13001772652 ps
CPU time 88.45 seconds
Started Aug 15 06:06:38 PM PDT 24
Finished Aug 15 06:08:07 PM PDT 24
Peak memory 271104 kb
Host smart-09721894-ae2b-47ec-a0a1-34380814c8aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883866628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2883866628
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2778042939
Short name T155
Test name
Test status
Simulation time 13580452792 ps
CPU time 129.29 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:08:35 PM PDT 24
Peak memory 278384 kb
Host smart-6fb28f13-df0b-41eb-98aa-daf6a828398c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2778042939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2778042939
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.306465607
Short name T455
Test name
Test status
Simulation time 43100461 ps
CPU time 0.83 seconds
Started Aug 15 06:06:43 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 211896 kb
Host smart-1ff96bf6-b428-4ca6-9569-02c9de948eb3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306465607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.306465607
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.861615630
Short name T436
Test name
Test status
Simulation time 17220270 ps
CPU time 1.08 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 208948 kb
Host smart-08419c0f-ad2c-4297-bb75-ef34bcf5045a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861615630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.861615630
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1029867164
Short name T536
Test name
Test status
Simulation time 737315087 ps
CPU time 8.98 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 218284 kb
Host smart-904c17cf-2f55-41dd-a8ab-a60e7d0dab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029867164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1029867164
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1333707341
Short name T838
Test name
Test status
Simulation time 244448961 ps
CPU time 6.72 seconds
Started Aug 15 06:06:16 PM PDT 24
Finished Aug 15 06:06:23 PM PDT 24
Peak memory 217264 kb
Host smart-9060de85-22a1-45a1-a6f0-980dd2d9b461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333707341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1333707341
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3129029989
Short name T569
Test name
Test status
Simulation time 3177513926 ps
CPU time 49.25 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:07:20 PM PDT 24
Peak memory 218268 kb
Host smart-7715d42b-18e5-4ee4-a175-83f3c1641689
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129029989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3129029989
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3985702674
Short name T215
Test name
Test status
Simulation time 222641331 ps
CPU time 7.27 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 218256 kb
Host smart-f99e6e4c-5a71-485e-8d6d-3d09aaf6e596
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985702674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3985702674
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2800725307
Short name T610
Test name
Test status
Simulation time 691283627 ps
CPU time 10.54 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 217556 kb
Host smart-8604ac77-b6da-4650-9b8f-ded8be746b31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800725307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2800725307
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1002109363
Short name T238
Test name
Test status
Simulation time 4238038650 ps
CPU time 78.04 seconds
Started Aug 15 06:06:35 PM PDT 24
Finished Aug 15 06:07:53 PM PDT 24
Peak memory 276444 kb
Host smart-4b6f6ad2-15ad-413e-9df1-ae13365c3afa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002109363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1002109363
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.388988561
Short name T789
Test name
Test status
Simulation time 508991396 ps
CPU time 18.63 seconds
Started Aug 15 06:06:31 PM PDT 24
Finished Aug 15 06:06:50 PM PDT 24
Peak memory 246400 kb
Host smart-2aee991d-5960-482a-b881-c34d4e150562
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388988561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.388988561
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.865482642
Short name T711
Test name
Test status
Simulation time 65025110 ps
CPU time 1.57 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:28 PM PDT 24
Peak memory 218268 kb
Host smart-e264b199-b1c0-4de9-ae8a-6775c46fc652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865482642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.865482642
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.692021999
Short name T485
Test name
Test status
Simulation time 263003045 ps
CPU time 12.99 seconds
Started Aug 15 06:06:39 PM PDT 24
Finished Aug 15 06:06:52 PM PDT 24
Peak memory 226032 kb
Host smart-8069c9b0-548e-4751-a660-f7d4b2ad032b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692021999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.692021999
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1240649319
Short name T406
Test name
Test status
Simulation time 6556097821 ps
CPU time 13.69 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 226016 kb
Host smart-14a79c0a-c21a-4813-bd4f-e850a81235de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240649319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1240649319
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1346153676
Short name T690
Test name
Test status
Simulation time 430407341 ps
CPU time 8.71 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 218108 kb
Host smart-c062ee3c-d68f-4882-97e4-8fb9110a51d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346153676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1346153676
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3099048098
Short name T608
Test name
Test status
Simulation time 589279491 ps
CPU time 11.59 seconds
Started Aug 15 06:06:21 PM PDT 24
Finished Aug 15 06:06:32 PM PDT 24
Peak memory 225048 kb
Host smart-0b685c8c-6804-4b7a-aa9d-883818f99d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099048098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3099048098
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3912294121
Short name T244
Test name
Test status
Simulation time 44942878 ps
CPU time 1.23 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 222044 kb
Host smart-d024623b-5871-4ee7-81b3-6c6c823c5635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912294121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3912294121
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1679914311
Short name T746
Test name
Test status
Simulation time 311910451 ps
CPU time 28.48 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 250812 kb
Host smart-6807810d-2248-442e-9887-6d2f894a654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679914311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1679914311
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2424118204
Short name T744
Test name
Test status
Simulation time 222280221 ps
CPU time 2.77 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 218224 kb
Host smart-f9470e8b-bb71-424f-a354-ecd35b783a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424118204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2424118204
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.852516967
Short name T167
Test name
Test status
Simulation time 7425530914 ps
CPU time 93.07 seconds
Started Aug 15 06:07:00 PM PDT 24
Finished Aug 15 06:08:33 PM PDT 24
Peak memory 267320 kb
Host smart-d89dfdf1-caaf-4120-913d-9aac3e2f0e78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852516967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.852516967
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2167686959
Short name T557
Test name
Test status
Simulation time 6697161540 ps
CPU time 107.36 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:08:21 PM PDT 24
Peak memory 283756 kb
Host smart-88378920-3671-4259-94f0-535aae7d1652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2167686959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2167686959
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1968770480
Short name T692
Test name
Test status
Simulation time 37170299 ps
CPU time 0.87 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 211852 kb
Host smart-d8f05b37-42d3-474a-9fae-87c7984abd72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968770480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1968770480
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.755033547
Short name T545
Test name
Test status
Simulation time 257499007 ps
CPU time 0.89 seconds
Started Aug 15 06:06:36 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 208948 kb
Host smart-e5911233-3a48-4f17-b70c-d01cb907e831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755033547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.755033547
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.217347819
Short name T718
Test name
Test status
Simulation time 1356563581 ps
CPU time 12.46 seconds
Started Aug 15 06:06:31 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 218272 kb
Host smart-991078ae-fe02-4ae0-aea7-b43e05e05a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217347819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.217347819
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.650075531
Short name T348
Test name
Test status
Simulation time 287475420 ps
CPU time 2.57 seconds
Started Aug 15 06:06:43 PM PDT 24
Finished Aug 15 06:06:45 PM PDT 24
Peak memory 217640 kb
Host smart-1dae7524-435e-4458-85e3-c78e56e65449
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650075531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.650075531
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3470493026
Short name T818
Test name
Test status
Simulation time 5402551237 ps
CPU time 33.53 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 218920 kb
Host smart-dbd8a39a-9e58-4bd7-90b6-13c7d1ab20aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470493026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3470493026
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1902152676
Short name T297
Test name
Test status
Simulation time 296776353 ps
CPU time 5.49 seconds
Started Aug 15 06:06:54 PM PDT 24
Finished Aug 15 06:06:59 PM PDT 24
Peak memory 218180 kb
Host smart-5bb8a6bf-565a-46c4-a26f-ff8e419e046f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902152676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1902152676
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1298468558
Short name T75
Test name
Test status
Simulation time 324123897 ps
CPU time 3.37 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 217552 kb
Host smart-999e5d6a-f695-423c-9784-fb07e1a4409d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298468558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1298468558
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.166135439
Short name T324
Test name
Test status
Simulation time 1216692793 ps
CPU time 53.1 seconds
Started Aug 15 06:06:41 PM PDT 24
Finished Aug 15 06:07:34 PM PDT 24
Peak memory 267260 kb
Host smart-7187e960-95a0-44fc-8ca2-736f9d56d5dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166135439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.166135439
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.183852079
Short name T794
Test name
Test status
Simulation time 1543266863 ps
CPU time 12.03 seconds
Started Aug 15 06:06:36 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 250632 kb
Host smart-19d74578-4e5f-4aa9-8b82-ada4f1258c16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183852079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.183852079
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3508573139
Short name T454
Test name
Test status
Simulation time 95119398 ps
CPU time 1.93 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 218444 kb
Host smart-a5ea11f0-0753-49cc-ba40-1035013365a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508573139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3508573139
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.428025681
Short name T758
Test name
Test status
Simulation time 3727015017 ps
CPU time 20.21 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:06:53 PM PDT 24
Peak memory 226020 kb
Host smart-6ee0571e-fe7a-474f-b0b5-9941403d7a91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428025681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.428025681
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1144875513
Short name T459
Test name
Test status
Simulation time 1075115122 ps
CPU time 9.2 seconds
Started Aug 15 06:06:31 PM PDT 24
Finished Aug 15 06:06:40 PM PDT 24
Peak memory 226016 kb
Host smart-1219da76-4a06-4e81-869f-ce32b3732f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144875513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1144875513
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.970251647
Short name T385
Test name
Test status
Simulation time 791689190 ps
CPU time 13.81 seconds
Started Aug 15 06:06:31 PM PDT 24
Finished Aug 15 06:06:45 PM PDT 24
Peak memory 218256 kb
Host smart-447d828d-5964-4e85-88eb-f16aaed49128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970251647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.970251647
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.494758937
Short name T395
Test name
Test status
Simulation time 7663907613 ps
CPU time 10.67 seconds
Started Aug 15 06:06:50 PM PDT 24
Finished Aug 15 06:07:00 PM PDT 24
Peak memory 226128 kb
Host smart-2472887e-1115-4df6-ac5f-503dc836b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494758937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.494758937
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1792998355
Short name T861
Test name
Test status
Simulation time 103081162 ps
CPU time 2.24 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:06:32 PM PDT 24
Peak memory 217640 kb
Host smart-0dbae810-1e82-4ff7-91d1-fe4b6911204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792998355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1792998355
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1565462185
Short name T465
Test name
Test status
Simulation time 1316412466 ps
CPU time 23.55 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:07:09 PM PDT 24
Peak memory 245184 kb
Host smart-e9261262-1539-4163-8994-7f7dfd6078c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565462185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1565462185
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2715514413
Short name T264
Test name
Test status
Simulation time 127496872 ps
CPU time 6.22 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 247016 kb
Host smart-f264e4ba-7b1a-4d1d-bae7-2651a948d768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715514413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2715514413
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.249584001
Short name T634
Test name
Test status
Simulation time 8527289585 ps
CPU time 142.88 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:09:08 PM PDT 24
Peak memory 277112 kb
Host smart-3890661c-e657-4381-baf3-b6231bb502db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249584001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.249584001
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2410172225
Short name T229
Test name
Test status
Simulation time 10263621 ps
CPU time 0.88 seconds
Started Aug 15 06:06:41 PM PDT 24
Finished Aug 15 06:06:42 PM PDT 24
Peak memory 208136 kb
Host smart-1c375ce1-e939-4b9c-837a-492d718ad208
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410172225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2410172225
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1550186909
Short name T457
Test name
Test status
Simulation time 16526374 ps
CPU time 1.09 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 208980 kb
Host smart-aaf60a35-29c5-418c-a51a-4b5ab3396bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550186909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1550186909
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3583421742
Short name T563
Test name
Test status
Simulation time 306316815 ps
CPU time 11.31 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 218264 kb
Host smart-8db8ffa0-f63c-4ece-bac0-29bd8fb59d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583421742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3583421742
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2448163210
Short name T33
Test name
Test status
Simulation time 1612707054 ps
CPU time 4.63 seconds
Started Aug 15 06:06:32 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 217140 kb
Host smart-18e0e2ec-1a86-443a-9f61-3040e8ffae28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448163210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2448163210
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.420861438
Short name T266
Test name
Test status
Simulation time 14905083967 ps
CPU time 57.73 seconds
Started Aug 15 06:06:32 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 219932 kb
Host smart-a29af3f2-8fbb-4d26-9c32-e043ba3d0810
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420861438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.420861438
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3703199978
Short name T272
Test name
Test status
Simulation time 405236818 ps
CPU time 7.23 seconds
Started Aug 15 06:06:32 PM PDT 24
Finished Aug 15 06:06:39 PM PDT 24
Peak memory 218228 kb
Host smart-49987cbe-238c-446b-9d79-6cb05f5f606b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703199978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3703199978
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.191609761
Short name T764
Test name
Test status
Simulation time 887053098 ps
CPU time 4.14 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 217512 kb
Host smart-d7aab248-fbb8-41e3-963e-0ea13a19b9ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191609761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
191609761
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.888911790
Short name T853
Test name
Test status
Simulation time 2564335968 ps
CPU time 49.33 seconds
Started Aug 15 06:06:35 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 275496 kb
Host smart-119e04a4-f85d-4f5c-b795-e7a7ee2d551c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888911790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.888911790
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3465051707
Short name T366
Test name
Test status
Simulation time 780396781 ps
CPU time 14.28 seconds
Started Aug 15 06:06:37 PM PDT 24
Finished Aug 15 06:06:52 PM PDT 24
Peak memory 250856 kb
Host smart-dfccfcb4-5590-4c49-b128-c62fc76f8e66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465051707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3465051707
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.165207498
Short name T146
Test name
Test status
Simulation time 134968811 ps
CPU time 2.3 seconds
Started Aug 15 06:06:40 PM PDT 24
Finished Aug 15 06:06:42 PM PDT 24
Peak memory 218220 kb
Host smart-e648325c-daca-48e0-9706-5aea7dc8a94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165207498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.165207498
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.4110397139
Short name T219
Test name
Test status
Simulation time 286135760 ps
CPU time 12.5 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:59 PM PDT 24
Peak memory 218940 kb
Host smart-a09bbfdb-6c32-4d9f-900c-1924b6977086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110397139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4110397139
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3742811839
Short name T858
Test name
Test status
Simulation time 6535063243 ps
CPU time 18.69 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:47 PM PDT 24
Peak memory 226076 kb
Host smart-c8b30a6b-32b5-4c57-b619-0e81f600265f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742811839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3742811839
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2232177680
Short name T522
Test name
Test status
Simulation time 2350934054 ps
CPU time 11.87 seconds
Started Aug 15 06:06:38 PM PDT 24
Finished Aug 15 06:06:50 PM PDT 24
Peak memory 226052 kb
Host smart-bceaa938-17d9-4eb1-bebf-8dec8a1c627f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232177680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2232177680
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4215906645
Short name T740
Test name
Test status
Simulation time 1239370542 ps
CPU time 7.85 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:53 PM PDT 24
Peak memory 218352 kb
Host smart-7b39c1a3-1902-496e-885b-1b58238d2e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215906645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4215906645
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.928944575
Short name T61
Test name
Test status
Simulation time 100392523 ps
CPU time 1.86 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 214348 kb
Host smart-17334424-ea6e-41ec-ad76-1e16af76d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928944575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.928944575
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1755455465
Short name T87
Test name
Test status
Simulation time 373964095 ps
CPU time 22.78 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 250876 kb
Host smart-f415c0e9-148e-41f5-b3b8-7b108878ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755455465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1755455465
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1925578256
Short name T364
Test name
Test status
Simulation time 1167790893 ps
CPU time 6.77 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 250508 kb
Host smart-76dba8da-5c63-4b9e-ae8f-8d4f729619ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925578256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1925578256
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1188684773
Short name T280
Test name
Test status
Simulation time 22682564409 ps
CPU time 282.92 seconds
Started Aug 15 06:06:34 PM PDT 24
Finished Aug 15 06:11:17 PM PDT 24
Peak memory 270740 kb
Host smart-9b10b7bb-0ea4-4cfc-b866-b818058c4f45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188684773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1188684773
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2283117500
Short name T606
Test name
Test status
Simulation time 12163542 ps
CPU time 0.84 seconds
Started Aug 15 06:06:41 PM PDT 24
Finished Aug 15 06:06:42 PM PDT 24
Peak memory 211872 kb
Host smart-6a6fb53b-3953-4cae-88d3-0f9883434f97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283117500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2283117500
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2048738943
Short name T278
Test name
Test status
Simulation time 28426607 ps
CPU time 0.85 seconds
Started Aug 15 06:06:35 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 208844 kb
Host smart-0173b152-4777-43b2-a5bb-142d283d68f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048738943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2048738943
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4166474290
Short name T636
Test name
Test status
Simulation time 3315851935 ps
CPU time 14.47 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:07:08 PM PDT 24
Peak memory 218936 kb
Host smart-ce3de38d-d2a3-4399-9bc7-42a9d7a6f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166474290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4166474290
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3276780629
Short name T806
Test name
Test status
Simulation time 257737251 ps
CPU time 3.44 seconds
Started Aug 15 06:06:36 PM PDT 24
Finished Aug 15 06:06:39 PM PDT 24
Peak memory 215672 kb
Host smart-b73587fe-cd80-44a3-b08b-dc954134f084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276780629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3276780629
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4147448490
Short name T575
Test name
Test status
Simulation time 2725274139 ps
CPU time 69.16 seconds
Started Aug 15 06:06:42 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 218896 kb
Host smart-a8b5466c-423f-4680-8c9b-4d2bc4a360e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147448490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4147448490
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3898039861
Short name T327
Test name
Test status
Simulation time 137433236 ps
CPU time 2.98 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:48 PM PDT 24
Peak memory 221740 kb
Host smart-929892bb-8cff-41b8-91e0-3e9486cbcead
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898039861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3898039861
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2814050125
Short name T552
Test name
Test status
Simulation time 210708617 ps
CPU time 5.81 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:06:59 PM PDT 24
Peak memory 217580 kb
Host smart-4119f37b-1629-4925-8b06-315b06211dbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814050125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2814050125
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3870352731
Short name T538
Test name
Test status
Simulation time 3414370168 ps
CPU time 39.7 seconds
Started Aug 15 06:06:35 PM PDT 24
Finished Aug 15 06:07:15 PM PDT 24
Peak memory 268440 kb
Host smart-3c544eb9-3062-4baf-8f80-11953b9a4d4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870352731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3870352731
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.785257597
Short name T701
Test name
Test status
Simulation time 317860587 ps
CPU time 10.86 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 250932 kb
Host smart-79f75a5a-8087-4ea5-a256-c3953367a5f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785257597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.785257597
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2027834316
Short name T293
Test name
Test status
Simulation time 129592520 ps
CPU time 3.57 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 222232 kb
Host smart-c2a6d97c-bc20-4302-aeda-617d99b7e11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027834316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2027834316
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3785126989
Short name T582
Test name
Test status
Simulation time 456821167 ps
CPU time 11.3 seconds
Started Aug 15 06:06:44 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 226028 kb
Host smart-f85baa97-c91c-466c-b251-171da7b52b63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785126989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3785126989
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1350935073
Short name T393
Test name
Test status
Simulation time 1259074285 ps
CPU time 13.44 seconds
Started Aug 15 06:06:36 PM PDT 24
Finished Aug 15 06:06:50 PM PDT 24
Peak memory 226016 kb
Host smart-10a99d7e-3145-40c4-b8de-a0bb428e273c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350935073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1350935073
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2796641171
Short name T846
Test name
Test status
Simulation time 780680050 ps
CPU time 13.07 seconds
Started Aug 15 06:06:44 PM PDT 24
Finished Aug 15 06:06:57 PM PDT 24
Peak memory 218216 kb
Host smart-53c058d1-b234-46ba-adbf-78f3b4278a2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796641171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2796641171
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.721234576
Short name T321
Test name
Test status
Simulation time 1002483853 ps
CPU time 9.88 seconds
Started Aug 15 06:06:48 PM PDT 24
Finished Aug 15 06:06:58 PM PDT 24
Peak memory 225688 kb
Host smart-5274681b-0ddd-4bf6-bf94-1a63533ee393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721234576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.721234576
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.887069490
Short name T603
Test name
Test status
Simulation time 228489087 ps
CPU time 2.59 seconds
Started Aug 15 06:06:41 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 214708 kb
Host smart-973d77b0-8326-49f1-ae0e-f49fcc127e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887069490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.887069490
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.994666218
Short name T422
Test name
Test status
Simulation time 509940431 ps
CPU time 29.24 seconds
Started Aug 15 06:06:49 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 250896 kb
Host smart-72b648c3-3fce-44b4-b8b2-288d8d27f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994666218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.994666218
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3162890951
Short name T530
Test name
Test status
Simulation time 171820578 ps
CPU time 6.01 seconds
Started Aug 15 06:06:43 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 247024 kb
Host smart-6f4ffdc0-ca2e-4c01-aa80-869a74dd7421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162890951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3162890951
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3118701240
Short name T550
Test name
Test status
Simulation time 23611122402 ps
CPU time 341.71 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:12:33 PM PDT 24
Peak memory 316660 kb
Host smart-b539e510-40e6-4328-8278-19196888c6c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118701240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3118701240
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1312639068
Short name T558
Test name
Test status
Simulation time 2988183721 ps
CPU time 55.27 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 267584 kb
Host smart-6861679f-3e04-4e17-bdb6-e0b229e3967b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1312639068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1312639068
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1102165773
Short name T548
Test name
Test status
Simulation time 14911538 ps
CPU time 1.06 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:48 PM PDT 24
Peak memory 211136 kb
Host smart-6720571e-4315-4663-9bd1-1f225b1abb52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102165773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1102165773
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1516947069
Short name T521
Test name
Test status
Simulation time 29811863 ps
CPU time 0.93 seconds
Started Aug 15 06:06:48 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 208892 kb
Host smart-f2039f1c-2aaf-441c-9b04-ff591dbbc471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516947069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1516947069
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.68568206
Short name T619
Test name
Test status
Simulation time 1169986990 ps
CPU time 10.68 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 218276 kb
Host smart-98379f42-8900-422f-9279-32d5510f360a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68568206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.68568206
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2642820988
Short name T407
Test name
Test status
Simulation time 94077217 ps
CPU time 3.13 seconds
Started Aug 15 06:06:41 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 216968 kb
Host smart-98b296cb-3573-4c9f-81e3-ec7f4c5e0928
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642820988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2642820988
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.4098389570
Short name T235
Test name
Test status
Simulation time 9702328298 ps
CPU time 32.59 seconds
Started Aug 15 06:06:54 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 218860 kb
Host smart-456f972e-32a8-4026-ac95-a27514330cff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098389570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.4098389570
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3019165636
Short name T221
Test name
Test status
Simulation time 1028326046 ps
CPU time 9.37 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 218208 kb
Host smart-23665ea4-5612-4d50-958b-3ad9ca9d2cc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019165636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3019165636
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1844577326
Short name T494
Test name
Test status
Simulation time 990156701 ps
CPU time 3.86 seconds
Started Aug 15 06:07:01 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 217552 kb
Host smart-6a192dbe-1ba1-44e1-8883-3d83ba13c763
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844577326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1844577326
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.957822910
Short name T281
Test name
Test status
Simulation time 2386924339 ps
CPU time 75.87 seconds
Started Aug 15 06:06:35 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 279528 kb
Host smart-f2952a64-7f2b-4aca-bb9a-f1f162eeaa30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957822910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.957822910
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3049850633
Short name T353
Test name
Test status
Simulation time 448553754 ps
CPU time 17.56 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 250076 kb
Host smart-0ae978c2-7d8a-4705-a81c-f8c7920dc4f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049850633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3049850633
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2005635054
Short name T630
Test name
Test status
Simulation time 79846493 ps
CPU time 3.87 seconds
Started Aug 15 06:06:31 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 222516 kb
Host smart-8655385a-8f16-45c3-8fb4-5882b8e94532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005635054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2005635054
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3585365930
Short name T508
Test name
Test status
Simulation time 353884447 ps
CPU time 11.45 seconds
Started Aug 15 06:06:41 PM PDT 24
Finished Aug 15 06:06:53 PM PDT 24
Peak memory 218924 kb
Host smart-1800b248-dbfa-499b-8e0a-aac06b1e2efe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585365930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3585365930
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2298030882
Short name T525
Test name
Test status
Simulation time 1605362771 ps
CPU time 9.54 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 226024 kb
Host smart-ed3c9c80-7a67-4c4b-8c95-0ca63874d287
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298030882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2298030882
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4218649410
Short name T443
Test name
Test status
Simulation time 4432143511 ps
CPU time 7.32 seconds
Started Aug 15 06:07:01 PM PDT 24
Finished Aug 15 06:07:09 PM PDT 24
Peak memory 218276 kb
Host smart-506ddbf3-f280-48ea-b74f-de28d6303041
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218649410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4218649410
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1025363665
Short name T705
Test name
Test status
Simulation time 2000568341 ps
CPU time 19.26 seconds
Started Aug 15 06:06:38 PM PDT 24
Finished Aug 15 06:06:57 PM PDT 24
Peak memory 218324 kb
Host smart-4090f217-2607-4a14-a1d6-322cfc5cecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025363665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1025363665
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3642057043
Short name T791
Test name
Test status
Simulation time 48934470 ps
CPU time 1.16 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:48 PM PDT 24
Peak memory 217644 kb
Host smart-170e3891-759b-46d5-8d9d-2ac6c23bcb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642057043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3642057043
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2515061684
Short name T783
Test name
Test status
Simulation time 1010056080 ps
CPU time 23.67 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:07:11 PM PDT 24
Peak memory 245332 kb
Host smart-2559158a-3a45-4314-bfdb-4bb554b968ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515061684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2515061684
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3165811711
Short name T735
Test name
Test status
Simulation time 128198116 ps
CPU time 2.79 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 218284 kb
Host smart-9eb1674c-ca15-4e76-9406-d76b395562d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165811711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3165811711
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1681437292
Short name T738
Test name
Test status
Simulation time 17838330459 ps
CPU time 197.28 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:10:10 PM PDT 24
Peak memory 250916 kb
Host smart-002eca13-45c3-4887-9534-2289d6f09ff9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681437292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1681437292
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1732132508
Short name T81
Test name
Test status
Simulation time 4553463270 ps
CPU time 74.95 seconds
Started Aug 15 06:07:02 PM PDT 24
Finished Aug 15 06:08:17 PM PDT 24
Peak memory 269400 kb
Host smart-8b918970-6be5-4a54-9b91-56f40e79eb19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1732132508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1732132508
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.160774044
Short name T574
Test name
Test status
Simulation time 13288419 ps
CPU time 0.88 seconds
Started Aug 15 06:06:44 PM PDT 24
Finished Aug 15 06:06:45 PM PDT 24
Peak memory 210564 kb
Host smart-3836430d-2d7f-4c4a-9117-be8360d76181
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160774044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.160774044
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2625468780
Short name T331
Test name
Test status
Simulation time 46713037 ps
CPU time 1.26 seconds
Started Aug 15 06:06:50 PM PDT 24
Finished Aug 15 06:06:51 PM PDT 24
Peak memory 208988 kb
Host smart-2b971b1c-db92-40e0-b869-6d2e4a948775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625468780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2625468780
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1699537378
Short name T14
Test name
Test status
Simulation time 540093906 ps
CPU time 8.55 seconds
Started Aug 15 06:06:34 PM PDT 24
Finished Aug 15 06:06:42 PM PDT 24
Peak memory 218260 kb
Host smart-3b32df7b-11a7-4e36-b87a-d7f356d2939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699537378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1699537378
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.462876797
Short name T392
Test name
Test status
Simulation time 223732568 ps
CPU time 3.13 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:48 PM PDT 24
Peak memory 217152 kb
Host smart-8900c538-0a7d-4f62-8466-6f2e6263e8fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462876797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.462876797
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1740945981
Short name T626
Test name
Test status
Simulation time 2774052560 ps
CPU time 26.15 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 218892 kb
Host smart-663e9a43-0b23-4bb5-9903-19c7417b4f81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740945981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1740945981
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2937256652
Short name T704
Test name
Test status
Simulation time 751163526 ps
CPU time 10.76 seconds
Started Aug 15 06:06:59 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 225144 kb
Host smart-6e520947-e725-4e8a-bebf-8a650fcf6723
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937256652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2937256652
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.831120466
Short name T251
Test name
Test status
Simulation time 1425567197 ps
CPU time 10.18 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 217544 kb
Host smart-55076d29-73c5-4d4d-9631-5b86bec54f9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831120466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
831120466
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.961014813
Short name T26
Test name
Test status
Simulation time 3992028771 ps
CPU time 27.02 seconds
Started Aug 15 06:06:56 PM PDT 24
Finished Aug 15 06:07:23 PM PDT 24
Peak memory 275412 kb
Host smart-209bbf80-2c39-4954-bf85-342df6f60eb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961014813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.961014813
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.203610265
Short name T685
Test name
Test status
Simulation time 326751602 ps
CPU time 10.34 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 250288 kb
Host smart-a3d362fd-9233-4127-9da0-3fa6a17c6b82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203610265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.203610265
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2657659968
Short name T444
Test name
Test status
Simulation time 65416734 ps
CPU time 2.01 seconds
Started Aug 15 06:06:48 PM PDT 24
Finished Aug 15 06:06:50 PM PDT 24
Peak memory 218220 kb
Host smart-0fb5ec72-5f81-483a-9a2b-02b01af7f431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657659968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2657659968
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2297683103
Short name T649
Test name
Test status
Simulation time 1179888459 ps
CPU time 10.05 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:57 PM PDT 24
Peak memory 218076 kb
Host smart-9ddf46a4-6e2a-4a79-b566-d2d741e6d06c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297683103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2297683103
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1606745184
Short name T743
Test name
Test status
Simulation time 334976268 ps
CPU time 10.63 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:06:58 PM PDT 24
Peak memory 226000 kb
Host smart-7697bd5b-7b97-4251-9cb7-32040b5b3919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606745184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1606745184
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2798539343
Short name T805
Test name
Test status
Simulation time 1235655161 ps
CPU time 9.18 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 218220 kb
Host smart-83293751-fe53-45ca-b8bb-bcc533cf9694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798539343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2798539343
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2439864443
Short name T591
Test name
Test status
Simulation time 583719287 ps
CPU time 11.66 seconds
Started Aug 15 06:06:50 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 218408 kb
Host smart-88caa9fd-fb93-4672-a053-b9f45b06b623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439864443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2439864443
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2659865779
Short name T760
Test name
Test status
Simulation time 81364359 ps
CPU time 3.12 seconds
Started Aug 15 06:06:38 PM PDT 24
Finished Aug 15 06:06:41 PM PDT 24
Peak memory 217604 kb
Host smart-79ad5ee4-4425-4df1-b3c6-5420dedcf59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659865779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2659865779
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4091756202
Short name T234
Test name
Test status
Simulation time 651319071 ps
CPU time 23.2 seconds
Started Aug 15 06:06:59 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 250864 kb
Host smart-6242e0af-2926-44ef-bd22-cdee7f43cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091756202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4091756202
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2228244131
Short name T468
Test name
Test status
Simulation time 964706223 ps
CPU time 3.89 seconds
Started Aug 15 06:06:34 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 222520 kb
Host smart-d1d38922-59c1-4f58-a410-2906f57b6913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228244131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2228244131
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3539955393
Short name T793
Test name
Test status
Simulation time 14687080887 ps
CPU time 244.66 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:10:58 PM PDT 24
Peak memory 274384 kb
Host smart-9714dbcb-c524-4447-a3fc-119427989dfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539955393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3539955393
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1027801899
Short name T761
Test name
Test status
Simulation time 12930780 ps
CPU time 1.12 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 217688 kb
Host smart-6bfd3ace-81cd-423c-9bd9-8e22d3e5216d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027801899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1027801899
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1594674447
Short name T766
Test name
Test status
Simulation time 63926856 ps
CPU time 1.12 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:06:52 PM PDT 24
Peak memory 208960 kb
Host smart-421e839b-c1ce-4d4e-96c8-0e20ecf88bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594674447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1594674447
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1325686251
Short name T553
Test name
Test status
Simulation time 1927786570 ps
CPU time 14.36 seconds
Started Aug 15 06:06:37 PM PDT 24
Finished Aug 15 06:06:51 PM PDT 24
Peak memory 226068 kb
Host smart-3270deda-d1eb-4a05-a799-21ab435141a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325686251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1325686251
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2389953129
Short name T627
Test name
Test status
Simulation time 127432416 ps
CPU time 1.14 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:06:54 PM PDT 24
Peak memory 216996 kb
Host smart-a8fb704a-8a16-4c05-8d3d-c5aaf1b5e1e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389953129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2389953129
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1643095971
Short name T411
Test name
Test status
Simulation time 2031994029 ps
CPU time 39.76 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 218136 kb
Host smart-b22ae8d5-b126-4491-94e3-a9899545e147
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643095971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1643095971
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.546934692
Short name T830
Test name
Test status
Simulation time 2039184220 ps
CPU time 9.31 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:07:02 PM PDT 24
Peak memory 218192 kb
Host smart-5c202f66-2d98-49d3-827c-9e2147a03eda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546934692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.546934692
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3039834432
Short name T83
Test name
Test status
Simulation time 1345196831 ps
CPU time 16.65 seconds
Started Aug 15 06:06:36 PM PDT 24
Finished Aug 15 06:06:52 PM PDT 24
Peak memory 217576 kb
Host smart-d8f10975-241a-47b4-bb70-78517dd38f78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039834432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3039834432
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2551253848
Short name T217
Test name
Test status
Simulation time 1464389002 ps
CPU time 45.56 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:07:32 PM PDT 24
Peak memory 267260 kb
Host smart-f85a4778-55a7-401b-9a7f-4e0be8dd5493
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551253848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2551253848
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3854842016
Short name T686
Test name
Test status
Simulation time 594415009 ps
CPU time 23.02 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 250728 kb
Host smart-cc766d55-a3a4-4d9c-8177-db90d17b79c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854842016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3854842016
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.731064001
Short name T381
Test name
Test status
Simulation time 650302594 ps
CPU time 3.19 seconds
Started Aug 15 06:07:02 PM PDT 24
Finished Aug 15 06:07:06 PM PDT 24
Peak memory 218260 kb
Host smart-6f551814-fce6-4cb1-b3b4-321d03d8a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731064001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.731064001
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.200101225
Short name T505
Test name
Test status
Simulation time 11775508258 ps
CPU time 17.43 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:07:02 PM PDT 24
Peak memory 220048 kb
Host smart-d23606b2-e33a-4ecd-badb-9427c766a227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200101225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.200101225
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.42993104
Short name T573
Test name
Test status
Simulation time 163509521 ps
CPU time 7.99 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 226012 kb
Host smart-4c81701c-56c5-4f05-8231-28f03e7f607a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42993104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_dig
est.42993104
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1542842403
Short name T433
Test name
Test status
Simulation time 246315707 ps
CPU time 7.73 seconds
Started Aug 15 06:06:46 PM PDT 24
Finished Aug 15 06:06:54 PM PDT 24
Peak memory 218224 kb
Host smart-ed59b18d-7758-4a1d-af96-34e63c83b212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542842403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1542842403
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.616767444
Short name T541
Test name
Test status
Simulation time 1256013076 ps
CPU time 6.95 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:06:59 PM PDT 24
Peak memory 226088 kb
Host smart-08f5f244-bd05-4f47-907a-3bda8d0f77e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616767444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.616767444
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2448857020
Short name T812
Test name
Test status
Simulation time 471969648 ps
CPU time 1.97 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:07:00 PM PDT 24
Peak memory 217600 kb
Host smart-0c402b22-cbb8-4946-8fba-4cfefc416f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448857020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2448857020
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2725222934
Short name T320
Test name
Test status
Simulation time 1786097904 ps
CPU time 19.91 seconds
Started Aug 15 06:07:06 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 250992 kb
Host smart-4eab3bbc-e67c-48d1-bff0-c5a838821311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725222934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2725222934
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3288490924
Short name T446
Test name
Test status
Simulation time 391906233 ps
CPU time 6.44 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:07:00 PM PDT 24
Peak memory 246992 kb
Host smart-d7a9c7a3-e47f-4f65-a76b-509740fbe8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288490924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3288490924
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.549600887
Short name T788
Test name
Test status
Simulation time 3322160103 ps
CPU time 62.69 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 251052 kb
Host smart-91b839c3-8d5f-4d1c-9aa9-8ddbadf36624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=549600887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.549600887
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.76451942
Short name T429
Test name
Test status
Simulation time 41841529 ps
CPU time 0.9 seconds
Started Aug 15 06:06:43 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 212984 kb
Host smart-704f69a4-9edf-4222-8899-0d43eb79931a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76451942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_volatile_unlock_smoke.76451942
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.232902649
Short name T662
Test name
Test status
Simulation time 33851638 ps
CPU time 0.79 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:06:52 PM PDT 24
Peak memory 209080 kb
Host smart-4c3fb617-9e30-4e5d-ab79-53eed6ca9a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232902649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.232902649
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2986367722
Short name T161
Test name
Test status
Simulation time 3177928298 ps
CPU time 21.71 seconds
Started Aug 15 06:06:50 PM PDT 24
Finished Aug 15 06:07:12 PM PDT 24
Peak memory 219376 kb
Host smart-97858b63-85c1-4e8b-b006-4888c3a73bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986367722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2986367722
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.4102555179
Short name T624
Test name
Test status
Simulation time 1133821174 ps
CPU time 26.14 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 217364 kb
Host smart-7171868f-206c-410d-9d2f-bdb36d5e179e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102555179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.4102555179
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.846305384
Short name T849
Test name
Test status
Simulation time 9904276850 ps
CPU time 70.57 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:08:03 PM PDT 24
Peak memory 218844 kb
Host smart-9568b9dc-5edf-47eb-bc0d-e80ebedddc8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846305384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.846305384
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3943061887
Short name T25
Test name
Test status
Simulation time 725908833 ps
CPU time 6.23 seconds
Started Aug 15 06:06:54 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 218176 kb
Host smart-fec2456e-cff9-46f1-a704-188e991caff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943061887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3943061887
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1830689581
Short name T752
Test name
Test status
Simulation time 2096066227 ps
CPU time 6.73 seconds
Started Aug 15 06:06:48 PM PDT 24
Finished Aug 15 06:06:54 PM PDT 24
Peak memory 217568 kb
Host smart-407da0c7-1667-41e2-aa58-eecec4b1aaaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830689581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1830689581
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.486197314
Short name T458
Test name
Test status
Simulation time 6873667910 ps
CPU time 43.48 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:07:38 PM PDT 24
Peak memory 277512 kb
Host smart-96b9495c-d563-4e34-81a6-6aefdf4eb2ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486197314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.486197314
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1940608757
Short name T614
Test name
Test status
Simulation time 579232871 ps
CPU time 15.34 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:07:13 PM PDT 24
Peak memory 250836 kb
Host smart-2db92658-b14f-438a-a8ed-de593d8db17d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940608757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1940608757
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.249084704
Short name T409
Test name
Test status
Simulation time 78722743 ps
CPU time 3.24 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 218280 kb
Host smart-506b08a2-2f06-43b2-88be-b0f3fd499311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249084704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.249084704
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1391142947
Short name T680
Test name
Test status
Simulation time 5190524036 ps
CPU time 12.83 seconds
Started Aug 15 06:07:02 PM PDT 24
Finished Aug 15 06:07:15 PM PDT 24
Peak memory 220112 kb
Host smart-ce4c7432-db76-4232-a053-782d63dbcf71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391142947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1391142947
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1333054512
Short name T741
Test name
Test status
Simulation time 365230865 ps
CPU time 15.46 seconds
Started Aug 15 06:06:56 PM PDT 24
Finished Aug 15 06:07:11 PM PDT 24
Peak memory 226012 kb
Host smart-c4cc512b-7ffc-4b39-a2ab-afa05158637c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333054512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1333054512
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.318955878
Short name T503
Test name
Test status
Simulation time 1097026382 ps
CPU time 8.3 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:54 PM PDT 24
Peak memory 226024 kb
Host smart-58654309-7ed0-44ca-9185-62c691421852
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318955878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.318955878
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.811049410
Short name T198
Test name
Test status
Simulation time 2186169429 ps
CPU time 11.52 seconds
Started Aug 15 06:06:49 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 225932 kb
Host smart-f97453df-38e1-419a-bc8a-644dafa4a600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811049410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.811049410
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2851506484
Short name T74
Test name
Test status
Simulation time 227957060 ps
CPU time 2.62 seconds
Started Aug 15 06:06:49 PM PDT 24
Finished Aug 15 06:06:52 PM PDT 24
Peak memory 214200 kb
Host smart-68d43ed2-7e04-47c6-aced-3581b5e00d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851506484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2851506484
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3034292983
Short name T754
Test name
Test status
Simulation time 3685656958 ps
CPU time 33.03 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 250960 kb
Host smart-0ded0a8c-4c92-484f-ab80-9e08eee2a073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034292983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3034292983
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1223293925
Short name T316
Test name
Test status
Simulation time 187824713 ps
CPU time 7.87 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:53 PM PDT 24
Peak memory 250424 kb
Host smart-f84ca98f-476d-4260-ab36-0aded82d754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223293925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1223293925
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3037329329
Short name T276
Test name
Test status
Simulation time 1836593003 ps
CPU time 48.33 seconds
Started Aug 15 06:06:50 PM PDT 24
Finished Aug 15 06:07:38 PM PDT 24
Peak memory 267312 kb
Host smart-b3c35dd9-ccbf-42ac-86ff-0958d0074bb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037329329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3037329329
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1912657667
Short name T333
Test name
Test status
Simulation time 10442988 ps
CPU time 1 seconds
Started Aug 15 06:06:49 PM PDT 24
Finished Aug 15 06:06:51 PM PDT 24
Peak memory 211876 kb
Host smart-3b4eb148-46ec-4242-b31a-4144b42e76da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912657667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1912657667
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.455916998
Short name T524
Test name
Test status
Simulation time 51605569 ps
CPU time 0.94 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:05:59 PM PDT 24
Peak memory 208876 kb
Host smart-d215e19b-dd43-4cfb-948d-144e55d4330e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455916998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.455916998
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.860737255
Short name T867
Test name
Test status
Simulation time 2086862364 ps
CPU time 13.68 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:17 PM PDT 24
Peak memory 226076 kb
Host smart-cc51dfd4-6245-400d-9c00-2670980c88ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860737255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.860737255
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1815183707
Short name T218
Test name
Test status
Simulation time 26539311196 ps
CPU time 90.18 seconds
Started Aug 15 06:06:16 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 219848 kb
Host smart-ac057a6e-8052-40cb-bcb4-a526703182f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815183707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1815183707
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3862413530
Short name T802
Test name
Test status
Simulation time 2046227026 ps
CPU time 46.65 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 217644 kb
Host smart-be06f710-cea6-4428-88be-208300246771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862413530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
862413530
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2958496542
Short name T256
Test name
Test status
Simulation time 621686761 ps
CPU time 16.36 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 218212 kb
Host smart-d1ac0a95-7961-454d-a1ba-fd60a944de6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958496542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2958496542
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.748111324
Short name T654
Test name
Test status
Simulation time 9742447360 ps
CPU time 36.33 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:42 PM PDT 24
Peak memory 217632 kb
Host smart-61415185-e17e-40f7-b72d-64ac6dc7afb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748111324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.748111324
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3677210419
Short name T62
Test name
Test status
Simulation time 427994647 ps
CPU time 6.74 seconds
Started Aug 15 06:06:21 PM PDT 24
Finished Aug 15 06:06:27 PM PDT 24
Peak memory 217552 kb
Host smart-434e8064-7359-4163-ab2c-14ae91a3137c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677210419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3677210419
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.854732906
Short name T453
Test name
Test status
Simulation time 12897919137 ps
CPU time 97.74 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:07:35 PM PDT 24
Peak memory 280492 kb
Host smart-0065624a-f61a-4ed5-96e7-6de02b83436f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854732906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.854732906
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1011395828
Short name T412
Test name
Test status
Simulation time 1117046572 ps
CPU time 21.39 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 250960 kb
Host smart-abb8f996-9c34-4d94-8c06-6621813f00fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011395828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1011395828
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1416617602
Short name T349
Test name
Test status
Simulation time 16325623 ps
CPU time 1.47 seconds
Started Aug 15 06:06:11 PM PDT 24
Finished Aug 15 06:06:13 PM PDT 24
Peak memory 218272 kb
Host smart-3388c40b-3a17-4385-9c79-e07639d3e3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416617602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1416617602
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1977838080
Short name T864
Test name
Test status
Simulation time 2609911885 ps
CPU time 9.62 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 214696 kb
Host smart-f7254ced-d770-446d-bb33-2ea35eee3f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977838080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1977838080
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2031456587
Short name T79
Test name
Test status
Simulation time 870783762 ps
CPU time 34.06 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 270644 kb
Host smart-78bcb907-cf8c-47f8-98b2-a9028b7fd618
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031456587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2031456587
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.97876114
Short name T713
Test name
Test status
Simulation time 1424522356 ps
CPU time 27.26 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 218912 kb
Host smart-2ae2ec75-0345-42fc-b163-835336281e4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97876114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.97876114
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3036020370
Short name T202
Test name
Test status
Simulation time 750423912 ps
CPU time 9.93 seconds
Started Aug 15 06:06:00 PM PDT 24
Finished Aug 15 06:06:10 PM PDT 24
Peak memory 225956 kb
Host smart-4c260929-081a-4bbd-a768-64b42ab02edb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036020370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3036020370
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.199582513
Short name T579
Test name
Test status
Simulation time 1644214768 ps
CPU time 10.88 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:18 PM PDT 24
Peak memory 218228 kb
Host smart-ac535675-33d4-48ae-9883-cda32253e70a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199582513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.199582513
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2855877831
Short name T448
Test name
Test status
Simulation time 601854154 ps
CPU time 13.74 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:21 PM PDT 24
Peak memory 226088 kb
Host smart-f47e59da-3f37-4ca5-9bdd-101fbbe880a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855877831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2855877831
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1848516300
Short name T268
Test name
Test status
Simulation time 48649413 ps
CPU time 2.1 seconds
Started Aug 15 06:06:11 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 217608 kb
Host smart-a19a1843-6752-4b05-85a7-388ee40e9e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848516300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1848516300
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1752228511
Short name T451
Test name
Test status
Simulation time 1022425916 ps
CPU time 33.94 seconds
Started Aug 15 06:06:02 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 250848 kb
Host smart-ac60a5b7-2466-4302-abad-4cdc27598303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752228511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1752228511
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.880226333
Short name T156
Test name
Test status
Simulation time 160904588 ps
CPU time 7.15 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:21 PM PDT 24
Peak memory 243300 kb
Host smart-5f7de197-532c-492e-a81f-2ab6a4ff7559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880226333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.880226333
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2684029059
Short name T133
Test name
Test status
Simulation time 2268509400 ps
CPU time 60.87 seconds
Started Aug 15 06:06:08 PM PDT 24
Finished Aug 15 06:07:09 PM PDT 24
Peak memory 251120 kb
Host smart-517ffa0f-2cef-45e7-8bd0-bc6ff91efdac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2684029059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2684029059
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4141501639
Short name T695
Test name
Test status
Simulation time 47343139 ps
CPU time 0.99 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:05 PM PDT 24
Peak memory 211824 kb
Host smart-6444a6fd-9be4-4094-a420-7e4a63bee31c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141501639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4141501639
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2734518871
Short name T260
Test name
Test status
Simulation time 51144691 ps
CPU time 0.87 seconds
Started Aug 15 06:06:54 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 208864 kb
Host smart-46876c93-4a70-455d-b08d-0b03a859106f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734518871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2734518871
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1358177473
Short name T228
Test name
Test status
Simulation time 1257944567 ps
CPU time 13.58 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:24 PM PDT 24
Peak memory 218148 kb
Host smart-6dc11cf6-69c8-4c46-a5af-ffb19ec8e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358177473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1358177473
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3509523299
Short name T340
Test name
Test status
Simulation time 447919901 ps
CPU time 5.86 seconds
Started Aug 15 06:07:04 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 217188 kb
Host smart-4da17490-341e-43dc-9044-b0eaf75f95c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509523299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3509523299
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3936512162
Short name T756
Test name
Test status
Simulation time 206495579 ps
CPU time 10.4 seconds
Started Aug 15 06:06:57 PM PDT 24
Finished Aug 15 06:07:08 PM PDT 24
Peak memory 218368 kb
Host smart-7923fd32-ec3b-48d2-b499-f32d297ae91b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936512162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3936512162
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2526340871
Short name T855
Test name
Test status
Simulation time 229969941 ps
CPU time 8.49 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 226040 kb
Host smart-c4462e0f-eb32-41c7-aa88-ee3a29abd607
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526340871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2526340871
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1025108267
Short name T270
Test name
Test status
Simulation time 1895490859 ps
CPU time 7.04 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 225956 kb
Host smart-7fc1b580-14f7-4a7e-bd26-ef6a0839f91a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025108267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1025108267
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2708934275
Short name T729
Test name
Test status
Simulation time 364939069 ps
CPU time 9.9 seconds
Started Aug 15 06:07:01 PM PDT 24
Finished Aug 15 06:07:11 PM PDT 24
Peak memory 218216 kb
Host smart-1cca462b-4410-4bdb-a499-cdda19c9ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708934275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2708934275
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1316463962
Short name T68
Test name
Test status
Simulation time 28813508 ps
CPU time 1.21 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:06:48 PM PDT 24
Peak memory 217784 kb
Host smart-6def527c-45f2-459f-81eb-d3257d554c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316463962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1316463962
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.109551076
Short name T656
Test name
Test status
Simulation time 1063188156 ps
CPU time 24.77 seconds
Started Aug 15 06:06:47 PM PDT 24
Finished Aug 15 06:07:12 PM PDT 24
Peak memory 250900 kb
Host smart-5dfb3ff1-40df-40a0-aa12-7c136b877bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109551076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.109551076
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2392618115
Short name T801
Test name
Test status
Simulation time 69764295 ps
CPU time 3.71 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:06:59 PM PDT 24
Peak memory 226344 kb
Host smart-71715033-f6e5-4172-94df-d809460ac53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392618115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2392618115
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3249274107
Short name T145
Test name
Test status
Simulation time 2232850145 ps
CPU time 55.67 seconds
Started Aug 15 06:06:49 PM PDT 24
Finished Aug 15 06:07:45 PM PDT 24
Peak memory 251076 kb
Host smart-81544503-d94e-4661-a7bb-8d00df86312c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3249274107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3249274107
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.636723234
Short name T423
Test name
Test status
Simulation time 15687260 ps
CPU time 0.92 seconds
Started Aug 15 06:06:49 PM PDT 24
Finished Aug 15 06:06:50 PM PDT 24
Peak memory 212900 kb
Host smart-6dd8ba68-4d17-490d-8753-a0b0190dfec3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636723234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.636723234
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2841743258
Short name T346
Test name
Test status
Simulation time 39888218 ps
CPU time 1.01 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:06:53 PM PDT 24
Peak memory 208940 kb
Host smart-03188dff-08a1-43e8-9ce4-5015c9adf086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841743258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2841743258
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.156322873
Short name T294
Test name
Test status
Simulation time 933458277 ps
CPU time 14.28 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 226076 kb
Host smart-7f3a3a77-e23e-4d05-bdc5-e6465f446e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156322873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.156322873
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3917840944
Short name T31
Test name
Test status
Simulation time 385044339 ps
CPU time 10.25 seconds
Started Aug 15 06:07:04 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 217268 kb
Host smart-8d0b721a-9b85-48a3-ac08-cf24586ed2c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917840944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3917840944
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1021936387
Short name T633
Test name
Test status
Simulation time 66657357 ps
CPU time 1.62 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 221968 kb
Host smart-a1c05596-25e7-4dd3-a1f3-9e584e921bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021936387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1021936387
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1765639565
Short name T724
Test name
Test status
Simulation time 1943781170 ps
CPU time 14.8 seconds
Started Aug 15 06:07:00 PM PDT 24
Finished Aug 15 06:07:15 PM PDT 24
Peak memory 226064 kb
Host smart-a4c697f2-32d8-4dbd-b4b2-6b6420920df8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765639565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1765639565
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.476013458
Short name T869
Test name
Test status
Simulation time 1070345192 ps
CPU time 13.08 seconds
Started Aug 15 06:07:03 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 225820 kb
Host smart-7dda194a-87a1-49a1-af12-42bad0ccfde5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476013458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.476013458
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1716875941
Short name T347
Test name
Test status
Simulation time 1167229687 ps
CPU time 10.74 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:07:03 PM PDT 24
Peak memory 218160 kb
Host smart-f6f7e047-4c6f-47b1-8154-c488e0c1129c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716875941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1716875941
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3836532219
Short name T46
Test name
Test status
Simulation time 347100485 ps
CPU time 8.21 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 225080 kb
Host smart-aa61a9e2-3a24-4c98-8841-12d01b80bca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836532219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3836532219
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2701486958
Short name T507
Test name
Test status
Simulation time 150858192 ps
CPU time 2 seconds
Started Aug 15 06:07:03 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 214092 kb
Host smart-9a4a70ac-28b2-4445-89fb-91c6ed24340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701486958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2701486958
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3880489269
Short name T342
Test name
Test status
Simulation time 698935356 ps
CPU time 25.23 seconds
Started Aug 15 06:06:49 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 245956 kb
Host smart-6f368b35-2a05-4d7d-843b-b5bb3a18c646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880489269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3880489269
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.938534878
Short name T498
Test name
Test status
Simulation time 159902897 ps
CPU time 6.47 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:06:58 PM PDT 24
Peak memory 242696 kb
Host smart-78909265-056b-439b-bacf-1bb6a0ad1d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938534878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.938534878
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1627824798
Short name T715
Test name
Test status
Simulation time 12415565239 ps
CPU time 223.53 seconds
Started Aug 15 06:07:04 PM PDT 24
Finished Aug 15 06:10:48 PM PDT 24
Peak memory 316432 kb
Host smart-21737fe1-4a80-4394-a9d6-e7531283fa87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627824798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1627824798
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1801585931
Short name T676
Test name
Test status
Simulation time 23705486 ps
CPU time 0.94 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 213028 kb
Host smart-b5474c8d-6e49-4b57-bfa1-2b98105f1968
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801585931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1801585931
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3245218922
Short name T546
Test name
Test status
Simulation time 22095428 ps
CPU time 0.87 seconds
Started Aug 15 06:06:54 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 208708 kb
Host smart-f0f76331-74a5-4a6a-81db-0c3fed858e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245218922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3245218922
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1637846814
Short name T571
Test name
Test status
Simulation time 2422810891 ps
CPU time 11.79 seconds
Started Aug 15 06:06:50 PM PDT 24
Finished Aug 15 06:07:03 PM PDT 24
Peak memory 226136 kb
Host smart-d7b979ac-b192-44fe-b769-f8b6f0f3f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637846814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1637846814
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1996303260
Short name T821
Test name
Test status
Simulation time 189949639 ps
CPU time 1.27 seconds
Started Aug 15 06:07:11 PM PDT 24
Finished Aug 15 06:07:12 PM PDT 24
Peak memory 216948 kb
Host smart-cd2286fe-e31c-420a-ad35-694793ca8fcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996303260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1996303260
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3677814593
Short name T516
Test name
Test status
Simulation time 47161558 ps
CPU time 2.32 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 222452 kb
Host smart-f60f9d67-9211-4f3b-9a2b-fd8b949f7016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677814593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3677814593
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2576032321
Short name T831
Test name
Test status
Simulation time 493747007 ps
CPU time 11.33 seconds
Started Aug 15 06:07:06 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 218344 kb
Host smart-2e18346c-ea6d-427c-b24b-b9a1382b5769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576032321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2576032321
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3647090761
Short name T689
Test name
Test status
Simulation time 263676685 ps
CPU time 11.41 seconds
Started Aug 15 06:07:04 PM PDT 24
Finished Aug 15 06:07:15 PM PDT 24
Peak memory 226000 kb
Host smart-c974386f-f162-4515-b327-0bdcce833112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647090761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3647090761
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3148279751
Short name T856
Test name
Test status
Simulation time 349683357 ps
CPU time 8.07 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 218160 kb
Host smart-6e8aa1ed-b50e-473f-af7d-af4cf96925e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148279751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3148279751
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1121738819
Short name T823
Test name
Test status
Simulation time 529892703 ps
CPU time 9.57 seconds
Started Aug 15 06:07:03 PM PDT 24
Finished Aug 15 06:07:13 PM PDT 24
Peak memory 226060 kb
Host smart-56e6e031-e376-46ae-b527-5363f9eeb4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121738819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1121738819
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.604373154
Short name T770
Test name
Test status
Simulation time 1459812862 ps
CPU time 5.31 seconds
Started Aug 15 06:07:02 PM PDT 24
Finished Aug 15 06:07:07 PM PDT 24
Peak memory 217504 kb
Host smart-96817464-8e20-47dc-a3d5-a633c5f76052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604373154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.604373154
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1065568298
Short name T598
Test name
Test status
Simulation time 665307433 ps
CPU time 30.68 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:07:29 PM PDT 24
Peak memory 246760 kb
Host smart-e3229905-6465-4a5f-b576-26a7cad5dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065568298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1065568298
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2550285959
Short name T142
Test name
Test status
Simulation time 252095656 ps
CPU time 7.54 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:06:58 PM PDT 24
Peak memory 250908 kb
Host smart-5dd2b8b2-a47f-4c40-b475-4a873a9f56c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550285959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2550285959
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3717908372
Short name T92
Test name
Test status
Simulation time 59520505093 ps
CPU time 222.38 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:10:36 PM PDT 24
Peak memory 300116 kb
Host smart-44cd2475-6e0d-4ef9-b96f-5a1605abbca5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717908372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3717908372
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2521464172
Short name T17
Test name
Test status
Simulation time 68624578075 ps
CPU time 80.16 seconds
Started Aug 15 06:06:59 PM PDT 24
Finished Aug 15 06:08:19 PM PDT 24
Peak memory 259308 kb
Host smart-3eeaf180-2b19-4756-b6ba-ed1740d19f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2521464172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2521464172
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2662604930
Short name T456
Test name
Test status
Simulation time 29171765 ps
CPU time 0.9 seconds
Started Aug 15 06:07:14 PM PDT 24
Finished Aug 15 06:07:15 PM PDT 24
Peak memory 211828 kb
Host smart-be120c3a-ff5b-4f1f-be4b-09929326629b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662604930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2662604930
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.238556059
Short name T523
Test name
Test status
Simulation time 46298120 ps
CPU time 0.92 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:06:54 PM PDT 24
Peak memory 208980 kb
Host smart-d164d7a4-a1d6-4da3-bea1-b73c9d35107e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238556059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.238556059
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2161649836
Short name T699
Test name
Test status
Simulation time 211165048 ps
CPU time 8.56 seconds
Started Aug 15 06:06:52 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 226104 kb
Host smart-70f5ab29-d5ee-40e3-88fb-563d6d8541a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161649836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2161649836
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3890773516
Short name T168
Test name
Test status
Simulation time 2410350297 ps
CPU time 2.75 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:06:58 PM PDT 24
Peak memory 217152 kb
Host smart-ebef9602-fa1d-4ceb-8f04-e50b1d32bf01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890773516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3890773516
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.792026693
Short name T726
Test name
Test status
Simulation time 46169021 ps
CPU time 1.7 seconds
Started Aug 15 06:07:13 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 222040 kb
Host smart-412fc78e-0816-486e-b56e-dccc5125f0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792026693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.792026693
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4164002265
Short name T580
Test name
Test status
Simulation time 1488630036 ps
CPU time 14.86 seconds
Started Aug 15 06:06:54 PM PDT 24
Finished Aug 15 06:07:09 PM PDT 24
Peak memory 219000 kb
Host smart-dc25a2bf-e42c-41ee-99d5-1be7257b6e2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164002265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4164002265
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1381496137
Short name T490
Test name
Test status
Simulation time 1001831160 ps
CPU time 12.39 seconds
Started Aug 15 06:07:00 PM PDT 24
Finished Aug 15 06:07:12 PM PDT 24
Peak memory 226016 kb
Host smart-2f2a4fb3-25c0-44c3-aad1-8a0e76b0fe5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381496137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1381496137
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1423246091
Short name T688
Test name
Test status
Simulation time 1680968616 ps
CPU time 15.18 seconds
Started Aug 15 06:07:04 PM PDT 24
Finished Aug 15 06:07:19 PM PDT 24
Peak memory 218212 kb
Host smart-f86b742a-7552-4521-ace3-5d1b23922f10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423246091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1423246091
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1127895806
Short name T21
Test name
Test status
Simulation time 722883931 ps
CPU time 9.04 seconds
Started Aug 15 06:07:01 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 225036 kb
Host smart-73f5b9e1-29f8-47b3-b241-2433d1b82689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127895806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1127895806
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.602935433
Short name T445
Test name
Test status
Simulation time 29472046 ps
CPU time 1.6 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:06:52 PM PDT 24
Peak memory 213716 kb
Host smart-adcc5c38-f2a7-4abc-855e-5db081ce66bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602935433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.602935433
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.877524407
Short name T774
Test name
Test status
Simulation time 260265859 ps
CPU time 34.82 seconds
Started Aug 15 06:07:11 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 250984 kb
Host smart-abb4db56-c019-4add-9e8e-2b5ec7b32ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877524407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.877524407
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.457625786
Short name T404
Test name
Test status
Simulation time 164915835 ps
CPU time 3.48 seconds
Started Aug 15 06:07:13 PM PDT 24
Finished Aug 15 06:07:16 PM PDT 24
Peak memory 226304 kb
Host smart-3db5f9aa-d3bd-4062-9dc0-a98fc83c8ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457625786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.457625786
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1658745144
Short name T506
Test name
Test status
Simulation time 31009791211 ps
CPU time 255.67 seconds
Started Aug 15 06:07:00 PM PDT 24
Finished Aug 15 06:11:16 PM PDT 24
Peak memory 250364 kb
Host smart-a04c879f-bce3-459e-ac56-ff25b8aa0cb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658745144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1658745144
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3557596701
Short name T130
Test name
Test status
Simulation time 2216273424 ps
CPU time 60.75 seconds
Started Aug 15 06:06:59 PM PDT 24
Finished Aug 15 06:08:00 PM PDT 24
Peak memory 269092 kb
Host smart-a67f412e-6ea3-44bc-94a6-0d4cfa54bc0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3557596701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3557596701
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.52541436
Short name T158
Test name
Test status
Simulation time 24479188 ps
CPU time 1.01 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:06:59 PM PDT 24
Peak memory 211828 kb
Host smart-f89666f4-5487-47f9-aa05-5e3880c7e180
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52541436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctr
l_volatile_unlock_smoke.52541436
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4230857235
Short name T797
Test name
Test status
Simulation time 51954914 ps
CPU time 1.32 seconds
Started Aug 15 06:07:09 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 209008 kb
Host smart-2a61360a-bdcc-4a8f-8e2a-0260e836240f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230857235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4230857235
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.204435276
Short name T369
Test name
Test status
Simulation time 765443675 ps
CPU time 26.1 seconds
Started Aug 15 06:07:06 PM PDT 24
Finished Aug 15 06:07:32 PM PDT 24
Peak memory 218148 kb
Host smart-c71b8e13-0ec9-4123-ad6f-9d0a02d93703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204435276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.204435276
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2317412974
Short name T727
Test name
Test status
Simulation time 666780570 ps
CPU time 4.78 seconds
Started Aug 15 06:06:51 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 217136 kb
Host smart-213de952-bc68-475c-bdaf-6be301e17b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317412974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2317412974
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2334711596
Short name T796
Test name
Test status
Simulation time 64969589 ps
CPU time 3.06 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:06:57 PM PDT 24
Peak memory 222476 kb
Host smart-d79f9a6b-c25a-42ab-9154-4f69b3e63191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334711596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2334711596
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.966727537
Short name T39
Test name
Test status
Simulation time 241527121 ps
CPU time 10.3 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 226064 kb
Host smart-db386678-004f-4ffd-8e2b-d3658e5f985c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966727537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.966727537
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.536068848
Short name T472
Test name
Test status
Simulation time 3508561758 ps
CPU time 14.78 seconds
Started Aug 15 06:07:12 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 218960 kb
Host smart-92d923cf-f1c7-45ec-b51b-cec039826532
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536068848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.536068848
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3015355402
Short name T860
Test name
Test status
Simulation time 243100792 ps
CPU time 6.64 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 218232 kb
Host smart-2f4c2008-caad-4e94-9c87-55debb8983f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015355402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3015355402
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3613663741
Short name T768
Test name
Test status
Simulation time 268424369 ps
CPU time 7.14 seconds
Started Aug 15 06:06:56 PM PDT 24
Finished Aug 15 06:07:03 PM PDT 24
Peak memory 224776 kb
Host smart-f1b6c4d6-2cba-4ade-ad1e-699cd9ac6441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613663741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3613663741
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1964006826
Short name T650
Test name
Test status
Simulation time 426920112 ps
CPU time 8.59 seconds
Started Aug 15 06:06:54 PM PDT 24
Finished Aug 15 06:07:03 PM PDT 24
Peak memory 217648 kb
Host smart-fc441b13-5322-431f-86c5-9d4cad1fad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964006826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1964006826
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2293692004
Short name T410
Test name
Test status
Simulation time 924936414 ps
CPU time 18.27 seconds
Started Aug 15 06:06:53 PM PDT 24
Finished Aug 15 06:07:11 PM PDT 24
Peak memory 250712 kb
Host smart-6147cf4e-e80c-4028-8a9a-8a8e2c72bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293692004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2293692004
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2475865253
Short name T578
Test name
Test status
Simulation time 143584028 ps
CPU time 6.92 seconds
Started Aug 15 06:07:05 PM PDT 24
Finished Aug 15 06:07:12 PM PDT 24
Peak memory 247356 kb
Host smart-77373100-7af2-4c05-9ac7-2dfc10319757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475865253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2475865253
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.116357437
Short name T259
Test name
Test status
Simulation time 65472944816 ps
CPU time 497.33 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:15:32 PM PDT 24
Peak memory 270912 kb
Host smart-8ed0bbd7-b3b5-456f-ae33-a675241fe5eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116357437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.116357437
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.2662411247
Short name T710
Test name
Test status
Simulation time 4676079624 ps
CPU time 100.26 seconds
Started Aug 15 06:07:14 PM PDT 24
Finished Aug 15 06:08:55 PM PDT 24
Peak memory 275156 kb
Host smart-c3814304-375e-4948-8937-872406c92cb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2662411247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.2662411247
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1649055816
Short name T540
Test name
Test status
Simulation time 12686586 ps
CPU time 1.14 seconds
Started Aug 15 06:06:55 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 211876 kb
Host smart-b6bbe2e1-9bed-4106-baa3-7ec8b41269c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649055816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1649055816
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3230697475
Short name T336
Test name
Test status
Simulation time 12764239 ps
CPU time 0.85 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:16 PM PDT 24
Peak memory 208612 kb
Host smart-86415a1b-f43d-48d4-89a9-0ef67a0a9092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230697475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3230697475
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3070301828
Short name T847
Test name
Test status
Simulation time 1357131534 ps
CPU time 12.79 seconds
Started Aug 15 06:07:05 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 218272 kb
Host smart-928b1b54-2622-49c1-a28d-b81a7422fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070301828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3070301828
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2879899226
Short name T163
Test name
Test status
Simulation time 454780222 ps
CPU time 7.88 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:23 PM PDT 24
Peak memory 217332 kb
Host smart-a67d155d-c37c-4de6-a908-25c56d3c4278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879899226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2879899226
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3186794414
Short name T700
Test name
Test status
Simulation time 29399361 ps
CPU time 2.12 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:12 PM PDT 24
Peak memory 218296 kb
Host smart-6b5de728-4897-480d-bf98-326541e5f764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186794414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3186794414
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3829317278
Short name T682
Test name
Test status
Simulation time 2047724311 ps
CPU time 16.49 seconds
Started Aug 15 06:07:11 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 226096 kb
Host smart-10353429-84c8-49c5-8562-8e37272e6f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829317278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3829317278
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.729332693
Short name T639
Test name
Test status
Simulation time 3127192461 ps
CPU time 14.69 seconds
Started Aug 15 06:06:59 PM PDT 24
Finished Aug 15 06:07:19 PM PDT 24
Peak memory 226060 kb
Host smart-32ddd2c7-ae40-4423-8faa-e54e5c9118fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729332693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.729332693
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.521518747
Short name T698
Test name
Test status
Simulation time 398571626 ps
CPU time 9.92 seconds
Started Aug 15 06:07:14 PM PDT 24
Finished Aug 15 06:07:24 PM PDT 24
Peak memory 218212 kb
Host smart-19b5bece-b708-486e-80a3-600c84bbd3c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521518747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.521518747
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.388753816
Short name T199
Test name
Test status
Simulation time 1169178131 ps
CPU time 7.74 seconds
Started Aug 15 06:06:57 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 224724 kb
Host smart-e75509c8-d855-4555-a1a4-3c3f64991a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388753816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.388753816
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2319077259
Short name T618
Test name
Test status
Simulation time 252820823 ps
CPU time 3.95 seconds
Started Aug 15 06:07:06 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 223304 kb
Host smart-7c6d7579-161a-4ef1-baad-18904488b0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319077259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2319077259
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3376821367
Short name T531
Test name
Test status
Simulation time 475959232 ps
CPU time 21.06 seconds
Started Aug 15 06:07:05 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 246672 kb
Host smart-38b1e7f7-795b-400d-8852-2524ce638583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376821367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3376821367
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3836011030
Short name T814
Test name
Test status
Simulation time 75091617 ps
CPU time 9.32 seconds
Started Aug 15 06:07:14 PM PDT 24
Finished Aug 15 06:07:24 PM PDT 24
Peak memory 250876 kb
Host smart-b26a75bd-5d3c-452e-b314-0f8628d908f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836011030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3836011030
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2378380436
Short name T808
Test name
Test status
Simulation time 43352806466 ps
CPU time 114.01 seconds
Started Aug 15 06:06:58 PM PDT 24
Finished Aug 15 06:08:52 PM PDT 24
Peak memory 251368 kb
Host smart-bd5b09fb-3f41-4d81-9364-b659b67ce985
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378380436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2378380436
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1306784971
Short name T197
Test name
Test status
Simulation time 74172565 ps
CPU time 1.06 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:11 PM PDT 24
Peak memory 217688 kb
Host smart-8357ec69-e974-411d-9868-4bb4ce5d52c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306784971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1306784971
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1111838817
Short name T361
Test name
Test status
Simulation time 268256159 ps
CPU time 0.92 seconds
Started Aug 15 06:07:14 PM PDT 24
Finished Aug 15 06:07:15 PM PDT 24
Peak memory 209048 kb
Host smart-684925da-da2c-4b63-9d1c-7888a05d7090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111838817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1111838817
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.719176618
Short name T488
Test name
Test status
Simulation time 2823347587 ps
CPU time 16.62 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:32 PM PDT 24
Peak memory 226124 kb
Host smart-abad4d2e-c099-451c-816c-e31247f943fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719176618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.719176618
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1385728292
Short name T30
Test name
Test status
Simulation time 217162551 ps
CPU time 2.86 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:13 PM PDT 24
Peak memory 217104 kb
Host smart-3ae52e83-199e-4b75-8c3a-1ce3c13b02a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385728292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1385728292
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.4061232694
Short name T854
Test name
Test status
Simulation time 245058445 ps
CPU time 2.64 seconds
Started Aug 15 06:07:11 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 218264 kb
Host smart-7eab6292-8073-44d7-aaff-2e7d898f1825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061232694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.4061232694
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2488837517
Short name T504
Test name
Test status
Simulation time 682270035 ps
CPU time 14.03 seconds
Started Aug 15 06:07:06 PM PDT 24
Finished Aug 15 06:07:20 PM PDT 24
Peak memory 218240 kb
Host smart-199deb67-eeb4-4d1a-b9f7-998e6ecf2c96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488837517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2488837517
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2083060462
Short name T870
Test name
Test status
Simulation time 1537471411 ps
CPU time 14.53 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 225968 kb
Host smart-811b2ded-ba2c-4c8c-8577-79dfc0952aca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083060462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2083060462
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1753358915
Short name T825
Test name
Test status
Simulation time 1218642629 ps
CPU time 12.34 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 218204 kb
Host smart-0c747e10-d117-4539-9e1f-c3e2796bd344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753358915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1753358915
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2299137305
Short name T872
Test name
Test status
Simulation time 1001766470 ps
CPU time 6.88 seconds
Started Aug 15 06:07:04 PM PDT 24
Finished Aug 15 06:07:11 PM PDT 24
Peak memory 224500 kb
Host smart-fbd5cd67-3b5b-476d-830e-a6fa20515258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299137305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2299137305
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3503329494
Short name T394
Test name
Test status
Simulation time 118093958 ps
CPU time 2.49 seconds
Started Aug 15 06:07:11 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 214284 kb
Host smart-7156ec71-1e5f-4970-8c7b-476c125af0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503329494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3503329494
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3579667827
Short name T220
Test name
Test status
Simulation time 648723744 ps
CPU time 18.12 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 250924 kb
Host smart-6925464f-ab9d-41a8-a7c7-0a0ce2572dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579667827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3579667827
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.947646886
Short name T862
Test name
Test status
Simulation time 314647270 ps
CPU time 7.62 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:24 PM PDT 24
Peak memory 250492 kb
Host smart-c1c12260-65da-4406-ad62-221e2ef490b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947646886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.947646886
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.962178667
Short name T425
Test name
Test status
Simulation time 4748852347 ps
CPU time 57.63 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:08:08 PM PDT 24
Peak memory 267356 kb
Host smart-107d21a6-70bb-467e-9cae-8d05024beb6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962178667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.962178667
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3027359847
Short name T134
Test name
Test status
Simulation time 18686616333 ps
CPU time 97.28 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:08:47 PM PDT 24
Peak memory 279524 kb
Host smart-5107a825-3842-49df-92ba-de6a3180d88a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3027359847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3027359847
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3912085358
Short name T207
Test name
Test status
Simulation time 50517759 ps
CPU time 0.96 seconds
Started Aug 15 06:07:12 PM PDT 24
Finished Aug 15 06:07:13 PM PDT 24
Peak memory 211932 kb
Host smart-e31e5745-c9c5-45bd-93bd-f8167e21516e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912085358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3912085358
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3502603825
Short name T203
Test name
Test status
Simulation time 19555902 ps
CPU time 1.24 seconds
Started Aug 15 06:07:01 PM PDT 24
Finished Aug 15 06:07:02 PM PDT 24
Peak memory 209000 kb
Host smart-f9e23b17-68ec-4110-911f-adb2e7c3bde2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502603825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3502603825
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.839150563
Short name T759
Test name
Test status
Simulation time 697786379 ps
CPU time 10.48 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 218452 kb
Host smart-8aafda5f-3fa1-4084-8353-e355c248a4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839150563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.839150563
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.427155156
Short name T568
Test name
Test status
Simulation time 942712696 ps
CPU time 3.46 seconds
Started Aug 15 06:06:57 PM PDT 24
Finished Aug 15 06:07:01 PM PDT 24
Peak memory 217036 kb
Host smart-428ca69c-2ea7-4087-9c1f-c458f46efac6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427155156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.427155156
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.479120922
Short name T809
Test name
Test status
Simulation time 108750740 ps
CPU time 2.88 seconds
Started Aug 15 06:07:01 PM PDT 24
Finished Aug 15 06:07:04 PM PDT 24
Peak memory 218244 kb
Host smart-250572e3-5cc1-4a81-9e4c-6519e615c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479120922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.479120922
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1597548163
Short name T537
Test name
Test status
Simulation time 504750497 ps
CPU time 21.27 seconds
Started Aug 15 06:07:04 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 226056 kb
Host smart-9d783adc-d45d-4489-92d3-32b345725141
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597548163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1597548163
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3215650396
Short name T292
Test name
Test status
Simulation time 416001163 ps
CPU time 16.15 seconds
Started Aug 15 06:07:11 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 225972 kb
Host smart-2425b242-62f6-418a-b470-2c02e6f7b6a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215650396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3215650396
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2353906753
Short name T476
Test name
Test status
Simulation time 2062197611 ps
CPU time 13.68 seconds
Started Aug 15 06:07:07 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 226024 kb
Host smart-d48c2054-ded4-4078-92f2-51f912a22d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353906753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2353906753
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2590953031
Short name T765
Test name
Test status
Simulation time 638379154 ps
CPU time 11.74 seconds
Started Aug 15 06:07:06 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 226040 kb
Host smart-27fa49ee-7c4d-4cfe-a2fc-44da1bb0cac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590953031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2590953031
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.4106807280
Short name T811
Test name
Test status
Simulation time 51785412 ps
CPU time 3.95 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 217660 kb
Host smart-2ecb9101-f2e6-4c39-a9cd-0ec6eec9f0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106807280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4106807280
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.249327593
Short name T824
Test name
Test status
Simulation time 252479325 ps
CPU time 30.26 seconds
Started Aug 15 06:07:00 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 250920 kb
Host smart-872d7c7e-ad1f-4102-b0c8-747802aad405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249327593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.249327593
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3630419125
Short name T442
Test name
Test status
Simulation time 179473480 ps
CPU time 3.59 seconds
Started Aug 15 06:07:02 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 226256 kb
Host smart-77058f13-ef95-460a-bba7-28d0f6f97925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630419125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3630419125
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.252075164
Short name T583
Test name
Test status
Simulation time 6751008948 ps
CPU time 198.22 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:10:35 PM PDT 24
Peak memory 495888 kb
Host smart-6220a144-82b2-4a4c-b33d-1f2ade0ed661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252075164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.252075164
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4270948855
Short name T595
Test name
Test status
Simulation time 100861268 ps
CPU time 0.79 seconds
Started Aug 15 06:07:02 PM PDT 24
Finished Aug 15 06:07:03 PM PDT 24
Peak memory 211876 kb
Host smart-fe98e6c5-12cc-4c34-91fb-19c3a1189717
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270948855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4270948855
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1840975266
Short name T482
Test name
Test status
Simulation time 20826815 ps
CPU time 1.21 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 208976 kb
Host smart-21c4c13a-c1a1-44a5-a687-af3c20ae421d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840975266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1840975266
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2854125916
Short name T325
Test name
Test status
Simulation time 122021788 ps
CPU time 1.98 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 216964 kb
Host smart-32a55dd3-9380-4484-8e4c-68e2436326aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854125916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2854125916
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2438592257
Short name T556
Test name
Test status
Simulation time 1653347313 ps
CPU time 3.09 seconds
Started Aug 15 06:07:13 PM PDT 24
Finished Aug 15 06:07:16 PM PDT 24
Peak memory 218240 kb
Host smart-99ed3ee0-6e1b-4879-bc9b-cb4d885c4a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438592257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2438592257
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.348805784
Short name T742
Test name
Test status
Simulation time 1505594951 ps
CPU time 14.75 seconds
Started Aug 15 06:07:14 PM PDT 24
Finished Aug 15 06:07:29 PM PDT 24
Peak memory 226096 kb
Host smart-bc3608ce-68ea-4ab4-bb8a-f0b7380668c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348805784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.348805784
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2386334478
Short name T413
Test name
Test status
Simulation time 425697433 ps
CPU time 11.68 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 225728 kb
Host smart-064fb9ac-5e5b-40b7-a07e-dc1077c04c9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386334478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2386334478
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3261384556
Short name T829
Test name
Test status
Simulation time 699387603 ps
CPU time 10.23 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 226016 kb
Host smart-68aaa43f-30a3-4b58-a7dc-aca59332d912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261384556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3261384556
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1119138797
Short name T48
Test name
Test status
Simulation time 1313724898 ps
CPU time 12.4 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 218336 kb
Host smart-9400d44a-2a46-4e37-b317-c8bc05f41207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119138797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1119138797
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2525542380
Short name T73
Test name
Test status
Simulation time 49409909 ps
CPU time 2.49 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 214136 kb
Host smart-11d1d6ce-0d4b-4dc8-b8ea-be0927596dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525542380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2525542380
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3070870970
Short name T529
Test name
Test status
Simulation time 258229068 ps
CPU time 24.84 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:40 PM PDT 24
Peak memory 250876 kb
Host smart-0d8438e1-e647-435a-af9e-8e2536626b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070870970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3070870970
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2100539152
Short name T551
Test name
Test status
Simulation time 248144213 ps
CPU time 10.07 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 250888 kb
Host smart-227622d2-551f-4dec-9b29-6c73fd379de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100539152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2100539152
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3436971915
Short name T496
Test name
Test status
Simulation time 8624030657 ps
CPU time 163.1 seconds
Started Aug 15 06:07:14 PM PDT 24
Finished Aug 15 06:09:57 PM PDT 24
Peak memory 269444 kb
Host smart-201e01b7-3593-4a4f-ad3e-ceb90b1bf306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436971915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3436971915
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.425686848
Short name T586
Test name
Test status
Simulation time 16740642 ps
CPU time 0.88 seconds
Started Aug 15 06:07:08 PM PDT 24
Finished Aug 15 06:07:09 PM PDT 24
Peak memory 211944 kb
Host smart-12a1c763-86b3-4c9e-a76e-fb7823d976f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425686848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.425686848
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3840968712
Short name T250
Test name
Test status
Simulation time 12556905 ps
CPU time 0.95 seconds
Started Aug 15 06:07:13 PM PDT 24
Finished Aug 15 06:07:14 PM PDT 24
Peak memory 208820 kb
Host smart-b1436ff6-c40e-4730-9eac-ae7933987e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840968712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3840968712
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.639859583
Short name T240
Test name
Test status
Simulation time 543340207 ps
CPU time 13.79 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:37 PM PDT 24
Peak memory 218260 kb
Host smart-c83cd422-5ce6-4d89-8746-ddf767d2b144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639859583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.639859583
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2361954164
Short name T605
Test name
Test status
Simulation time 198174591 ps
CPU time 1.44 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 216960 kb
Host smart-73961d1d-19db-413e-ad6b-bda4bf2d2e89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361954164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2361954164
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.664733220
Short name T666
Test name
Test status
Simulation time 286336088 ps
CPU time 3.04 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 218308 kb
Host smart-0d755e4b-cffd-4285-9b73-cad2417a8b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664733220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.664733220
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1410271133
Short name T419
Test name
Test status
Simulation time 383737897 ps
CPU time 14.2 seconds
Started Aug 15 06:07:12 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 226072 kb
Host smart-6a0ce634-290e-45ae-81b5-2a5c3595ebf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410271133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1410271133
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2452909110
Short name T345
Test name
Test status
Simulation time 360142575 ps
CPU time 10.68 seconds
Started Aug 15 06:07:20 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 225992 kb
Host smart-e926f12b-80c3-43b7-bcf8-e4e7dc549331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452909110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2452909110
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1041798674
Short name T588
Test name
Test status
Simulation time 3815106571 ps
CPU time 13.83 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:33 PM PDT 24
Peak memory 218280 kb
Host smart-01500f7e-07e0-4032-ac76-371b6b366277
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041798674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1041798674
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3281051201
Short name T696
Test name
Test status
Simulation time 392814036 ps
CPU time 8.99 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 225200 kb
Host smart-2043f51c-0edb-4755-aa9c-b6b791ef8e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281051201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3281051201
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.157212990
Short name T730
Test name
Test status
Simulation time 58724490 ps
CPU time 2.41 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 217640 kb
Host smart-4aa5fce1-723c-471f-9f23-e65f68e3782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157212990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.157212990
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3318521951
Short name T663
Test name
Test status
Simulation time 1323798926 ps
CPU time 26.56 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:42 PM PDT 24
Peak memory 250916 kb
Host smart-2d41b19b-2de6-4783-890d-b137f6ca63d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318521951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3318521951
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3261133321
Short name T22
Test name
Test status
Simulation time 84860637 ps
CPU time 3.49 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:19 PM PDT 24
Peak memory 221696 kb
Host smart-b9262206-2c4c-41dc-a680-51ccef9f532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261133321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3261133321
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1122875039
Short name T817
Test name
Test status
Simulation time 14000115 ps
CPU time 0.88 seconds
Started Aug 15 06:07:09 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 211900 kb
Host smart-deb631bf-05b4-4d1c-85b7-e17b1718ae5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122875039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1122875039
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2922261248
Short name T295
Test name
Test status
Simulation time 151807175 ps
CPU time 0.85 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:04 PM PDT 24
Peak memory 208700 kb
Host smart-8bd3de0b-95bb-4896-a334-73bbec8c0bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922261248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2922261248
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1710852887
Short name T196
Test name
Test status
Simulation time 149000208 ps
CPU time 0.88 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:07 PM PDT 24
Peak memory 208732 kb
Host smart-b403f1c1-30aa-4a39-bad1-4c75a59f8152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710852887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1710852887
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2689994609
Short name T697
Test name
Test status
Simulation time 7082514828 ps
CPU time 14.62 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:33 PM PDT 24
Peak memory 217676 kb
Host smart-770eca67-0253-4860-9fff-a85e4c1ed1b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689994609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2689994609
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.238140487
Short name T643
Test name
Test status
Simulation time 1683996075 ps
CPU time 50.74 seconds
Started Aug 15 06:06:00 PM PDT 24
Finished Aug 15 06:06:51 PM PDT 24
Peak memory 218816 kb
Host smart-e68cbf00-8d74-40e3-9bd5-42fd31c8e4aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238140487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.238140487
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2560439387
Short name T501
Test name
Test status
Simulation time 534058808 ps
CPU time 2.3 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:04 PM PDT 24
Peak memory 217408 kb
Host smart-84246277-ade1-48a8-8c65-f3c4b2e47dd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560439387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
560439387
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2356162593
Short name T439
Test name
Test status
Simulation time 1871936466 ps
CPU time 14.37 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:06:10 PM PDT 24
Peak memory 218216 kb
Host smart-ce505990-4e2e-4d9f-b474-65310755d4d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356162593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2356162593
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3069554687
Short name T655
Test name
Test status
Simulation time 1033654714 ps
CPU time 30.97 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 217532 kb
Host smart-0a2c669d-61e3-4b69-902f-50ebf847f449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069554687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3069554687
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3144905389
Short name T447
Test name
Test status
Simulation time 105329184 ps
CPU time 2.27 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:10 PM PDT 24
Peak memory 217540 kb
Host smart-ac3e71f2-47be-47c2-a450-c63d6c2394f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144905389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3144905389
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3642099864
Short name T148
Test name
Test status
Simulation time 2230833504 ps
CPU time 37.51 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:44 PM PDT 24
Peak memory 267252 kb
Host smart-c54fe5d3-3b45-4e9b-9600-94213437599d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642099864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3642099864
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1345616327
Short name T255
Test name
Test status
Simulation time 1478513315 ps
CPU time 11.94 seconds
Started Aug 15 06:06:02 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 250712 kb
Host smart-6bfa1c8f-7538-4c47-b623-1ededb22a26a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345616327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1345616327
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2996693192
Short name T16
Test name
Test status
Simulation time 456817258 ps
CPU time 4.89 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 218216 kb
Host smart-c108b5ac-bf89-471c-813f-9b1117cc1631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996693192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2996693192
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1404224148
Short name T467
Test name
Test status
Simulation time 1213205557 ps
CPU time 7.55 seconds
Started Aug 15 06:06:02 PM PDT 24
Finished Aug 15 06:06:10 PM PDT 24
Peak memory 214556 kb
Host smart-10006128-9056-4480-9add-b69dda01f3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404224148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1404224148
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1097710894
Short name T50
Test name
Test status
Simulation time 483409511 ps
CPU time 40.05 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:41 PM PDT 24
Peak memory 269884 kb
Host smart-ca09cb2c-db0f-44d9-b57f-f3883a8560b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097710894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1097710894
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3333735043
Short name T543
Test name
Test status
Simulation time 259532405 ps
CPU time 12.75 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:06:06 PM PDT 24
Peak memory 226020 kb
Host smart-3c30db37-02f8-469a-ba72-c4b04778c9b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333735043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3333735043
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2650352029
Short name T597
Test name
Test status
Simulation time 3239760447 ps
CPU time 7.26 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:17 PM PDT 24
Peak memory 218260 kb
Host smart-401bdbf2-e9a8-4b63-827d-597bb0b15ca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650352029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
650352029
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.740951701
Short name T486
Test name
Test status
Simulation time 170549679 ps
CPU time 6.66 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 225152 kb
Host smart-a30c57fd-f249-425d-a7cf-960ec4bb4e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740951701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.740951701
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4044622385
Short name T55
Test name
Test status
Simulation time 108902002 ps
CPU time 3.24 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:13 PM PDT 24
Peak memory 217500 kb
Host smart-ef6336d8-7727-4de3-8bc9-141fcbddbe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044622385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4044622385
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3760077617
Short name T790
Test name
Test status
Simulation time 1309519338 ps
CPU time 30.84 seconds
Started Aug 15 06:06:16 PM PDT 24
Finished Aug 15 06:06:47 PM PDT 24
Peak memory 250740 kb
Host smart-6082b4ad-be2c-4de4-b906-83fe7234eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760077617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3760077617
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2188560857
Short name T779
Test name
Test status
Simulation time 2174562803 ps
CPU time 3.68 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 226096 kb
Host smart-7ca25dcd-e2ed-402e-a3a7-cfabbf974785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188560857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2188560857
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.236588647
Short name T725
Test name
Test status
Simulation time 10719515790 ps
CPU time 51.99 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:06:48 PM PDT 24
Peak memory 250700 kb
Host smart-0706e993-77ea-4e3e-93df-7e5bc656bf83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236588647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.236588647
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2197714161
Short name T191
Test name
Test status
Simulation time 1863899180 ps
CPU time 59.03 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:07:02 PM PDT 24
Peak memory 268120 kb
Host smart-f28ddf0b-57c0-4da6-ae0c-810ca462f627
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2197714161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2197714161
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.533180469
Short name T418
Test name
Test status
Simulation time 13704942 ps
CPU time 0.96 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 211880 kb
Host smart-fb06f467-4c5a-40e5-97fc-59df614fe989
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533180469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.533180469
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1212168226
Short name T527
Test name
Test status
Simulation time 53332966 ps
CPU time 0.96 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 208888 kb
Host smart-5fcf8bac-8331-4e8d-ac7b-6b2578272766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212168226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1212168226
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1738452497
Short name T703
Test name
Test status
Simulation time 330923847 ps
CPU time 14.07 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 218284 kb
Host smart-b13311b2-5aa5-4f2f-8cfb-4dbaf60a84c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738452497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1738452497
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1350904046
Short name T9
Test name
Test status
Simulation time 5634431716 ps
CPU time 6 seconds
Started Aug 15 06:07:10 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 217624 kb
Host smart-fd29190f-3e6c-4bb3-9a18-7a40ea0869a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350904046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1350904046
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2175418029
Short name T339
Test name
Test status
Simulation time 395282805 ps
CPU time 3.68 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 218216 kb
Host smart-8b9d7ae2-6c79-4a3e-9305-e8886616b36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175418029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2175418029
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1820842735
Short name T249
Test name
Test status
Simulation time 797062654 ps
CPU time 28.41 seconds
Started Aug 15 06:07:24 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 226080 kb
Host smart-bf31df15-3e13-419e-ad3b-faa13caac274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820842735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1820842735
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1458201102
Short name T495
Test name
Test status
Simulation time 1817989403 ps
CPU time 8.57 seconds
Started Aug 15 06:07:13 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 226016 kb
Host smart-a85283f7-2635-4d23-a4cd-468f700f62d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458201102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1458201102
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.68271675
Short name T399
Test name
Test status
Simulation time 2661468214 ps
CPU time 13.12 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:35 PM PDT 24
Peak memory 226068 kb
Host smart-03b60929-a214-40b9-a10c-a5099dd4fe3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68271675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.68271675
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4055498909
Short name T539
Test name
Test status
Simulation time 385240209 ps
CPU time 9.59 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 225004 kb
Host smart-5e5581c0-4ebb-409b-94dd-4f1faa2f27c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055498909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4055498909
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.4157112520
Short name T66
Test name
Test status
Simulation time 121945118 ps
CPU time 4.16 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 217624 kb
Host smart-41cdd139-1201-41ef-8836-dcc66d2c9d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157112520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.4157112520
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2200241944
Short name T263
Test name
Test status
Simulation time 758681401 ps
CPU time 27.09 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 250876 kb
Host smart-ff0d3780-16b3-4662-9e0a-9a3bbbb0a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200241944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2200241944
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.4029671333
Short name T593
Test name
Test status
Simulation time 57912075 ps
CPU time 8.72 seconds
Started Aug 15 06:07:11 PM PDT 24
Finished Aug 15 06:07:20 PM PDT 24
Peak memory 250860 kb
Host smart-ef8f3d87-ac22-46a1-8ebf-df6572748967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029671333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.4029671333
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3022357220
Short name T757
Test name
Test status
Simulation time 1265770598 ps
CPU time 14.01 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:38 PM PDT 24
Peak memory 245696 kb
Host smart-b1c1336a-98f8-49a0-a8bc-f5f55f1aabe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022357220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3022357220
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1648165456
Short name T414
Test name
Test status
Simulation time 34497936 ps
CPU time 0.96 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 211892 kb
Host smart-91c037ba-2f99-4b5a-8cf1-3aa2695774af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648165456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1648165456
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1950811635
Short name T576
Test name
Test status
Simulation time 56031032 ps
CPU time 1 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:19 PM PDT 24
Peak memory 208912 kb
Host smart-6f63a62f-c15f-41ec-bd8e-2de5d5307123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950811635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1950811635
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2165135423
Short name T233
Test name
Test status
Simulation time 1172203530 ps
CPU time 14.23 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:07:37 PM PDT 24
Peak memory 218280 kb
Host smart-a33e6d6b-07db-472f-bfe7-46f04e61d0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165135423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2165135423
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.416632849
Short name T8
Test name
Test status
Simulation time 5461565127 ps
CPU time 9.88 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 217684 kb
Host smart-e1a0c333-69e9-44cd-90e4-7700ecb57e2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416632849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.416632849
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2870122796
Short name T745
Test name
Test status
Simulation time 120714449 ps
CPU time 2.73 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 218260 kb
Host smart-7dde4872-bf6c-4bcb-8a0a-114cefdfef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870122796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2870122796
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4126420013
Short name T243
Test name
Test status
Simulation time 367764123 ps
CPU time 8.46 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 226084 kb
Host smart-1886d889-846d-4b9e-8365-e70ff4340140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126420013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4126420013
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1415684004
Short name T804
Test name
Test status
Simulation time 1541250773 ps
CPU time 11.91 seconds
Started Aug 15 06:07:13 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 226004 kb
Host smart-1d66d6f7-d9ee-426c-9a28-148b4b5997f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415684004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1415684004
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.528539689
Short name T780
Test name
Test status
Simulation time 1318773617 ps
CPU time 8.31 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:25 PM PDT 24
Peak memory 218092 kb
Host smart-0841af89-453d-4fb1-ba3f-9b5528a08386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528539689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.528539689
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.4057225345
Short name T314
Test name
Test status
Simulation time 316624171 ps
CPU time 9.68 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 218336 kb
Host smart-ec86091d-ab99-4468-9b79-95a6875f1f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057225345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.4057225345
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3759874164
Short name T65
Test name
Test status
Simulation time 390315219 ps
CPU time 2.29 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 214144 kb
Host smart-c59a5b06-4e13-49d1-895b-fc4c2a4bc850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759874164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3759874164
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1247847396
Short name T837
Test name
Test status
Simulation time 173002194 ps
CPU time 24.3 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:39 PM PDT 24
Peak memory 250652 kb
Host smart-fa89798e-0280-473d-8648-7880c0ffe7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247847396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1247847396
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3383579646
Short name T564
Test name
Test status
Simulation time 114794196 ps
CPU time 6.97 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 250476 kb
Host smart-6f0a7616-a60a-4d53-880d-e0dae59b352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383579646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3383579646
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1720667503
Short name T599
Test name
Test status
Simulation time 11703251648 ps
CPU time 199.04 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:10:36 PM PDT 24
Peak memory 283784 kb
Host smart-9c227d63-bcbb-456f-ab9e-cfa57677b615
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720667503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1720667503
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3230941257
Short name T358
Test name
Test status
Simulation time 15670442 ps
CPU time 1.15 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 213000 kb
Host smart-cef37ffa-2168-4ae5-a870-7785e2e037df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230941257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3230941257
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4164190020
Short name T474
Test name
Test status
Simulation time 41352357 ps
CPU time 0.86 seconds
Started Aug 15 06:07:21 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 208696 kb
Host smart-8ce704cc-b9d8-405d-99fb-26ab5dc30c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164190020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4164190020
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1132254111
Short name T668
Test name
Test status
Simulation time 6636341653 ps
CPU time 15.94 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:33 PM PDT 24
Peak memory 218460 kb
Host smart-fbb50891-5d43-4f06-9199-7400a909857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132254111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1132254111
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.4144095253
Short name T554
Test name
Test status
Simulation time 138122974 ps
CPU time 2.48 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:20 PM PDT 24
Peak memory 217572 kb
Host smart-ae53b112-d548-4ce7-8ba4-d0fa46d0bae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144095253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.4144095253
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2265818119
Short name T657
Test name
Test status
Simulation time 71574113 ps
CPU time 1.56 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:19 PM PDT 24
Peak memory 222104 kb
Host smart-f78adaed-6133-47f4-9085-67ca1b02cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265818119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2265818119
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1847400791
Short name T721
Test name
Test status
Simulation time 490126232 ps
CPU time 13.44 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 218948 kb
Host smart-ebd1566d-9a5a-4747-b3e2-d7ffda61adeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847400791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1847400791
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2993811573
Short name T151
Test name
Test status
Simulation time 863835951 ps
CPU time 12.08 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 225992 kb
Host smart-22438a23-63c4-4166-b797-25207bf1ea08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993811573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2993811573
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.363172638
Short name T59
Test name
Test status
Simulation time 1215694503 ps
CPU time 12.66 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 226176 kb
Host smart-265a6d3f-f868-4914-ab2a-beaedd6e9c5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363172638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.363172638
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4276163342
Short name T810
Test name
Test status
Simulation time 282232208 ps
CPU time 11.42 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:35 PM PDT 24
Peak memory 218304 kb
Host smart-8dd08d3e-cdf0-4806-b3d8-7c18f1970fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276163342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4276163342
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.55461574
Short name T613
Test name
Test status
Simulation time 77666534 ps
CPU time 2.46 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 222700 kb
Host smart-5e9fed6f-56f4-45c2-9c35-12e0c24623f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55461574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.55461574
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1311854253
Short name T302
Test name
Test status
Simulation time 638714165 ps
CPU time 26.12 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 250896 kb
Host smart-9418fcc2-956d-4901-ad9d-b69d823802f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311854253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1311854253
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3631010749
Short name T305
Test name
Test status
Simulation time 310611257 ps
CPU time 8.61 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:24 PM PDT 24
Peak memory 250848 kb
Host smart-e38f35fe-5552-4924-8d6d-e7e141be3525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631010749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3631010749
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2004172234
Short name T169
Test name
Test status
Simulation time 2689653410 ps
CPU time 9.29 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 226136 kb
Host smart-d6f85dce-cc43-44a1-bb4e-d8b30acc57f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004172234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2004172234
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1664869317
Short name T380
Test name
Test status
Simulation time 136025302 ps
CPU time 0.99 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:17 PM PDT 24
Peak memory 211804 kb
Host smart-598e0be1-796e-4923-aab6-f86e7d385597
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664869317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1664869317
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1090564329
Short name T500
Test name
Test status
Simulation time 37801779 ps
CPU time 0.93 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:07:48 PM PDT 24
Peak memory 208864 kb
Host smart-62e72820-2580-4dd8-aac9-74d355b8c6ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090564329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1090564329
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2935177396
Short name T566
Test name
Test status
Simulation time 814735373 ps
CPU time 7.44 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 218236 kb
Host smart-1f4e1709-f8f2-4fb4-aaac-fdddd93b19ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935177396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2935177396
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4154145078
Short name T717
Test name
Test status
Simulation time 40736562 ps
CPU time 1.22 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:20 PM PDT 24
Peak memory 216900 kb
Host smart-56df492a-d37e-4f5c-a130-987534e632d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154145078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.4154145078
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1025995790
Short name T328
Test name
Test status
Simulation time 284530845 ps
CPU time 2.58 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 222400 kb
Host smart-4fc9a56a-d1ce-4d3c-90c9-6f77a725c0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025995790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1025995790
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2958215015
Short name T374
Test name
Test status
Simulation time 1434640122 ps
CPU time 18.41 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 219984 kb
Host smart-bb7c1919-8990-4b5d-a8c9-6ea5bf9aee3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958215015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2958215015
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1229459137
Short name T669
Test name
Test status
Simulation time 5147919923 ps
CPU time 11.16 seconds
Started Aug 15 06:07:22 PM PDT 24
Finished Aug 15 06:07:33 PM PDT 24
Peak memory 226052 kb
Host smart-ab262dff-2da0-450e-9367-18c6460a008a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229459137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1229459137
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3120441470
Short name T230
Test name
Test status
Simulation time 571535572 ps
CPU time 12.26 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 226004 kb
Host smart-d2621493-26e3-4a67-9697-b77697bbb5dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120441470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3120441470
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.379317722
Short name T284
Test name
Test status
Simulation time 240541062 ps
CPU time 9.31 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:38 PM PDT 24
Peak memory 226072 kb
Host smart-33754c69-8e4d-4d35-9f7f-14b69b109ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379317722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.379317722
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4072664538
Short name T323
Test name
Test status
Simulation time 93716918 ps
CPU time 3.44 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:07:36 PM PDT 24
Peak memory 214952 kb
Host smart-560d247b-38fe-40b9-95e1-227e80ce9d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072664538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4072664538
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1429652758
Short name T590
Test name
Test status
Simulation time 226444970 ps
CPU time 27.64 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:08:06 PM PDT 24
Peak memory 250888 kb
Host smart-16aab9ea-2042-477b-972d-ab9b9e1ff748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429652758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1429652758
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3315660094
Short name T714
Test name
Test status
Simulation time 46582836 ps
CPU time 6.01 seconds
Started Aug 15 06:07:20 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 246616 kb
Host smart-4f008bfe-8d60-492a-8d73-62517a2975d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315660094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3315660094
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3530732816
Short name T132
Test name
Test status
Simulation time 36123787915 ps
CPU time 48.5 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:08:06 PM PDT 24
Peak memory 226264 kb
Host smart-73fdaaaf-4046-4683-b784-ef6c7fa929bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3530732816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3530732816
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4116011969
Short name T585
Test name
Test status
Simulation time 164998681 ps
CPU time 0.97 seconds
Started Aug 15 06:07:43 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 211904 kb
Host smart-37f5cf17-7840-421f-8031-eb21c60756d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116011969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.4116011969
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.598269634
Short name T307
Test name
Test status
Simulation time 26456595 ps
CPU time 1.29 seconds
Started Aug 15 06:07:21 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 209016 kb
Host smart-ee7f2e6c-b4b5-4434-bf77-bbf702c028f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598269634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.598269634
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2302560349
Short name T785
Test name
Test status
Simulation time 3712273270 ps
CPU time 10.11 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 226112 kb
Host smart-f513be2b-c0c9-439f-8d6b-58537355702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302560349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2302560349
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1990570431
Short name T833
Test name
Test status
Simulation time 795167833 ps
CPU time 1.64 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 216988 kb
Host smart-758f0d59-68f1-4930-ae0d-7ef3df64886b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990570431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1990570431
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.28604970
Short name T652
Test name
Test status
Simulation time 199266270 ps
CPU time 3.36 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 218220 kb
Host smart-3ba7d395-bf4f-4115-b214-3914b08eb1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28604970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.28604970
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2148690074
Short name T737
Test name
Test status
Simulation time 359057156 ps
CPU time 11.14 seconds
Started Aug 15 06:07:21 PM PDT 24
Finished Aug 15 06:07:32 PM PDT 24
Peak memory 226096 kb
Host smart-ead4cf11-673b-417f-9c8d-d6382ccdd3ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148690074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2148690074
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3045668128
Short name T20
Test name
Test status
Simulation time 325987019 ps
CPU time 13.58 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:07:45 PM PDT 24
Peak memory 225980 kb
Host smart-2a5593a0-6e22-4cdd-838d-be454b75ec88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045668128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3045668128
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2980543694
Short name T58
Test name
Test status
Simulation time 1528355420 ps
CPU time 7.9 seconds
Started Aug 15 06:07:45 PM PDT 24
Finished Aug 15 06:07:53 PM PDT 24
Peak memory 225960 kb
Host smart-f8032625-df02-4556-b8ef-4e207431e9ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980543694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2980543694
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1172603275
Short name T90
Test name
Test status
Simulation time 1183803789 ps
CPU time 12.23 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 218452 kb
Host smart-5aea8bdb-b8cc-4ba2-bea0-acd81ef02f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172603275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1172603275
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2841141928
Short name T71
Test name
Test status
Simulation time 29690636 ps
CPU time 1.07 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 212160 kb
Host smart-a366571a-b032-4cf5-8602-90566f56e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841141928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2841141928
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.539830572
Short name T483
Test name
Test status
Simulation time 908194150 ps
CPU time 29.49 seconds
Started Aug 15 06:07:39 PM PDT 24
Finished Aug 15 06:08:09 PM PDT 24
Peak memory 250908 kb
Host smart-fb609b4e-f0fc-43af-94a2-76812e5fcd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539830572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.539830572
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2342775152
Short name T645
Test name
Test status
Simulation time 256358825 ps
CPU time 7.6 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:36 PM PDT 24
Peak memory 250472 kb
Host smart-783737dd-1f52-403d-a41c-92aa4f2f57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342775152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2342775152
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1532802772
Short name T326
Test name
Test status
Simulation time 5878435240 ps
CPU time 79.19 seconds
Started Aug 15 06:07:39 PM PDT 24
Finished Aug 15 06:08:58 PM PDT 24
Peak memory 283684 kb
Host smart-5cf9088f-bf9d-4eba-9d27-94d9f9062a96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532802772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1532802772
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1252070705
Short name T678
Test name
Test status
Simulation time 41389525 ps
CPU time 0.84 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 211832 kb
Host smart-a9702fce-ab9f-439f-b886-c510d5dcea04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252070705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1252070705
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.334387262
Short name T204
Test name
Test status
Simulation time 55163330 ps
CPU time 0.91 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:20 PM PDT 24
Peak memory 208816 kb
Host smart-92eb2c4f-39a6-4827-94b7-aabe9d4d8b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334387262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.334387262
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.495795414
Short name T224
Test name
Test status
Simulation time 278241930 ps
CPU time 12.13 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 218260 kb
Host smart-e5c40e56-e90b-4f79-9436-a7fff3b67aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495795414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.495795414
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.290537352
Short name T671
Test name
Test status
Simulation time 1091708229 ps
CPU time 5.54 seconds
Started Aug 15 06:07:22 PM PDT 24
Finished Aug 15 06:07:27 PM PDT 24
Peak memory 217084 kb
Host smart-faae211a-76be-4289-9758-b8f2f1127525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290537352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.290537352
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.812597061
Short name T820
Test name
Test status
Simulation time 311810656 ps
CPU time 3.81 seconds
Started Aug 15 06:07:55 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 218212 kb
Host smart-c41a3c98-e6b7-4f5c-a31a-b024a7eb44d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812597061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.812597061
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.859627896
Short name T354
Test name
Test status
Simulation time 3573836362 ps
CPU time 20.25 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:37 PM PDT 24
Peak memory 226124 kb
Host smart-7a46fb6e-431c-4d79-9ac4-e977ecf0782e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859627896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.859627896
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4253965992
Short name T631
Test name
Test status
Simulation time 2053514838 ps
CPU time 21.99 seconds
Started Aug 15 06:07:17 PM PDT 24
Finished Aug 15 06:07:39 PM PDT 24
Peak memory 218196 kb
Host smart-a5576c58-f824-4a82-a898-7edaad63f1e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253965992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4253965992
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.346165228
Short name T469
Test name
Test status
Simulation time 222928402 ps
CPU time 7.63 seconds
Started Aug 15 06:07:23 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 218240 kb
Host smart-e64e74d9-63e6-4e5d-a06a-079cd286785e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346165228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.346165228
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2618756371
Short name T535
Test name
Test status
Simulation time 364497671 ps
CPU time 14.64 seconds
Started Aug 15 06:07:32 PM PDT 24
Finished Aug 15 06:07:47 PM PDT 24
Peak memory 218336 kb
Host smart-de129eed-03e2-444f-8197-074b13ddfa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618756371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2618756371
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4150879874
Short name T843
Test name
Test status
Simulation time 90940962 ps
CPU time 2.58 seconds
Started Aug 15 06:07:15 PM PDT 24
Finished Aug 15 06:07:18 PM PDT 24
Peak memory 217732 kb
Host smart-6808b008-51d9-4c55-b7e9-ba38dc4bc2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150879874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4150879874
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1663394849
Short name T786
Test name
Test status
Simulation time 586477994 ps
CPU time 27.47 seconds
Started Aug 15 06:07:16 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 250892 kb
Host smart-05f5961e-629e-485d-8d64-d8ef40a629e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663394849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1663394849
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.779513740
Short name T384
Test name
Test status
Simulation time 225471777 ps
CPU time 9.95 seconds
Started Aug 15 06:07:26 PM PDT 24
Finished Aug 15 06:07:36 PM PDT 24
Peak memory 250832 kb
Host smart-540b91e2-6b25-4a6e-956e-046c19bcba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779513740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.779513740
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3928309009
Short name T164
Test name
Test status
Simulation time 20402762483 ps
CPU time 124.34 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:09:23 PM PDT 24
Peak memory 222320 kb
Host smart-250a4bb0-9974-4a75-a0a1-3fd79f694289
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928309009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3928309009
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3647695127
Short name T707
Test name
Test status
Simulation time 114130655 ps
CPU time 0.86 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:39 PM PDT 24
Peak memory 212964 kb
Host smart-3ff772da-8aae-4ccc-913a-321fc74c7659
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647695127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3647695127
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3552700421
Short name T10
Test name
Test status
Simulation time 39683147 ps
CPU time 1.24 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 208996 kb
Host smart-e38c847f-bc41-4d25-a9ea-d0b53be8b651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552700421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3552700421
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1221413737
Short name T279
Test name
Test status
Simulation time 309005961 ps
CPU time 10.1 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 218232 kb
Host smart-42278f31-14d5-46be-9fc1-62c86d03b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221413737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1221413737
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3820661440
Short name T478
Test name
Test status
Simulation time 311670361 ps
CPU time 4.49 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:07:38 PM PDT 24
Peak memory 217168 kb
Host smart-c36f2c4b-441c-4086-8add-f0b4e453e993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820661440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3820661440
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3943692033
Short name T275
Test name
Test status
Simulation time 83904732 ps
CPU time 3.12 seconds
Started Aug 15 06:07:25 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 218360 kb
Host smart-faf685d8-369a-4e68-ad8f-0e9bf619fe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943692033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3943692033
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3096531874
Short name T379
Test name
Test status
Simulation time 3126972590 ps
CPU time 12.71 seconds
Started Aug 15 06:07:32 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 219636 kb
Host smart-5cc05975-4e06-466b-a508-54236ea90ea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096531874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3096531874
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.8169024
Short name T239
Test name
Test status
Simulation time 722042342 ps
CPU time 8.93 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 218208 kb
Host smart-5bcc3427-2ec0-418e-adb8-261c4e2158da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8169024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_dige
st.8169024
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1201806397
Short name T728
Test name
Test status
Simulation time 236276337 ps
CPU time 6.86 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:45 PM PDT 24
Peak memory 218228 kb
Host smart-90e95c77-18a6-488f-ba08-4befe20ccc7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201806397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1201806397
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.46059419
Short name T52
Test name
Test status
Simulation time 358317870 ps
CPU time 13.96 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:07:47 PM PDT 24
Peak memory 218340 kb
Host smart-49569cf4-9430-48e7-a363-8730bb5b7cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46059419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.46059419
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.705740657
Short name T64
Test name
Test status
Simulation time 40255279 ps
CPU time 2.46 seconds
Started Aug 15 06:07:18 PM PDT 24
Finished Aug 15 06:07:20 PM PDT 24
Peak memory 217664 kb
Host smart-67241814-d5a4-4a04-b95b-100543fdf1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705740657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.705740657
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3475057567
Short name T227
Test name
Test status
Simulation time 1751967611 ps
CPU time 29.28 seconds
Started Aug 15 06:07:19 PM PDT 24
Finished Aug 15 06:07:48 PM PDT 24
Peak memory 246000 kb
Host smart-790e3b35-909c-4962-ab7b-90a7c3bd3eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475057567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3475057567
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3578160536
Short name T587
Test name
Test status
Simulation time 111478471 ps
CPU time 3.37 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 226336 kb
Host smart-c0bd27dc-d211-4217-858d-11ab68ba8389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578160536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3578160536
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3244351381
Short name T560
Test name
Test status
Simulation time 176930600 ps
CPU time 0.98 seconds
Started Aug 15 06:07:25 PM PDT 24
Finished Aug 15 06:07:26 PM PDT 24
Peak memory 217648 kb
Host smart-07b1a615-dec7-4766-896f-0a2f1957e044
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244351381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3244351381
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1657564460
Short name T308
Test name
Test status
Simulation time 20362576 ps
CPU time 1.19 seconds
Started Aug 15 06:07:30 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 208920 kb
Host smart-55513179-0531-4cee-8d6b-34b7a242f6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657564460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1657564460
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.768944170
Short name T159
Test name
Test status
Simulation time 221436304 ps
CPU time 9.62 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 218296 kb
Host smart-b80d2e0f-29ce-44ca-9473-e82aec96cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768944170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.768944170
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3997998129
Short name T170
Test name
Test status
Simulation time 424575067 ps
CPU time 1.39 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:07:48 PM PDT 24
Peak memory 216972 kb
Host smart-5a94b3ed-9ce8-48e9-86f3-0b48d4583c86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997998129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3997998129
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.509811095
Short name T4
Test name
Test status
Simulation time 44077665 ps
CPU time 1.71 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 222024 kb
Host smart-b1ad5860-fb06-45b8-b097-b2c91e4d2191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509811095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.509811095
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1766630920
Short name T625
Test name
Test status
Simulation time 2565543030 ps
CPU time 23.98 seconds
Started Aug 15 06:07:30 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 220316 kb
Host smart-753b1fe4-8537-423a-836c-efbb0bd6b4b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766630920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1766630920
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2217800513
Short name T309
Test name
Test status
Simulation time 1850676439 ps
CPU time 15.88 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:08:03 PM PDT 24
Peak memory 225988 kb
Host smart-ff28a872-4544-424a-aaf0-1643e0a9d369
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217800513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2217800513
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.422961646
Short name T473
Test name
Test status
Simulation time 380134721 ps
CPU time 12.37 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 218228 kb
Host smart-d81838ae-c411-4dd2-b4d8-5715d1009b10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422961646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.422961646
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3331568155
Short name T532
Test name
Test status
Simulation time 2674492006 ps
CPU time 9.87 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:08:01 PM PDT 24
Peak memory 225264 kb
Host smart-8d940bdd-1ef4-41ba-ae8a-2ce1d04c9b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331568155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3331568155
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2446304356
Short name T798
Test name
Test status
Simulation time 1041674776 ps
CPU time 5.88 seconds
Started Aug 15 06:07:43 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 217648 kb
Host smart-81717d85-e553-4f50-bbf3-e12f7a717ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446304356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2446304356
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2333932171
Short name T450
Test name
Test status
Simulation time 858834337 ps
CPU time 21.48 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 250856 kb
Host smart-86309bd7-a594-4281-8f1d-9ed0ea0123ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333932171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2333932171
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.248047093
Short name T277
Test name
Test status
Simulation time 283710915 ps
CPU time 6.31 seconds
Started Aug 15 06:07:28 PM PDT 24
Finished Aug 15 06:07:35 PM PDT 24
Peak memory 243048 kb
Host smart-9d1d8f51-9f5a-410f-8dbb-a450f22ccb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248047093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.248047093
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.462402804
Short name T362
Test name
Test status
Simulation time 19994103 ps
CPU time 0.83 seconds
Started Aug 15 06:07:45 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 211852 kb
Host smart-060c8cb4-0c0b-4b12-8e60-eea3d23d6d33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462402804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.462402804
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.178320661
Short name T27
Test name
Test status
Simulation time 24793021 ps
CPU time 1.31 seconds
Started Aug 15 06:07:28 PM PDT 24
Finished Aug 15 06:07:29 PM PDT 24
Peak memory 208936 kb
Host smart-e68dd5a5-5279-44d4-a010-ba2b557d7701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178320661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.178320661
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2832646840
Short name T43
Test name
Test status
Simulation time 1447076094 ps
CPU time 18.56 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 218284 kb
Host smart-db7d79d6-26b2-44ce-95b4-1786dad7d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832646840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2832646840
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1766215312
Short name T845
Test name
Test status
Simulation time 957346880 ps
CPU time 5.34 seconds
Started Aug 15 06:07:41 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 217004 kb
Host smart-62b144fc-8d05-48ce-b918-1e8a3b69dcd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766215312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1766215312
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1369800355
Short name T515
Test name
Test status
Simulation time 442255158 ps
CPU time 2.04 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:31 PM PDT 24
Peak memory 218308 kb
Host smart-b044ef77-8ba7-4605-9039-d8ad7ac5d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369800355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1369800355
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2850291816
Short name T604
Test name
Test status
Simulation time 1106857915 ps
CPU time 10.73 seconds
Started Aug 15 06:07:35 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 226064 kb
Host smart-84e22351-491d-4b34-b0c4-fa22aa997630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850291816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2850291816
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3068639719
Short name T315
Test name
Test status
Simulation time 355251591 ps
CPU time 14.15 seconds
Started Aug 15 06:07:28 PM PDT 24
Finished Aug 15 06:07:42 PM PDT 24
Peak memory 225984 kb
Host smart-1420ce9e-b778-47e6-b8fb-7ad3c2696d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068639719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3068639719
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.227369263
Short name T237
Test name
Test status
Simulation time 2304009575 ps
CPU time 7.45 seconds
Started Aug 15 06:07:27 PM PDT 24
Finished Aug 15 06:07:35 PM PDT 24
Peak memory 218264 kb
Host smart-2c5d095e-9ef2-42a5-885e-39934d21fb95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227369263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.227369263
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1396420194
Short name T480
Test name
Test status
Simulation time 38728803 ps
CPU time 1.36 seconds
Started Aug 15 06:07:35 PM PDT 24
Finished Aug 15 06:07:36 PM PDT 24
Peak memory 213924 kb
Host smart-b29025d9-5bba-43ff-9506-50f4ceb5a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396420194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1396420194
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1573349948
Short name T479
Test name
Test status
Simulation time 710279011 ps
CPU time 19.72 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:07:56 PM PDT 24
Peak memory 251000 kb
Host smart-b601d872-8b78-4d01-8aa4-91568f6a7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573349948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1573349948
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2299273445
Short name T428
Test name
Test status
Simulation time 175220202 ps
CPU time 7 seconds
Started Aug 15 06:07:27 PM PDT 24
Finished Aug 15 06:07:35 PM PDT 24
Peak memory 247064 kb
Host smart-d46752cc-0ca8-4032-9a2d-d75b21b9d810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299273445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2299273445
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3836398685
Short name T673
Test name
Test status
Simulation time 6218133746 ps
CPU time 41.37 seconds
Started Aug 15 06:07:49 PM PDT 24
Finished Aug 15 06:08:31 PM PDT 24
Peak memory 217932 kb
Host smart-999f4a25-1261-4aad-b4b9-6e473b46cffd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836398685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3836398685
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.263369429
Short name T304
Test name
Test status
Simulation time 12552314 ps
CPU time 0.88 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 208180 kb
Host smart-ba8ebdc2-aa18-4d74-8d60-a50ac07f49d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263369429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.263369429
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.664637085
Short name T273
Test name
Test status
Simulation time 26352452 ps
CPU time 1.02 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:07:33 PM PDT 24
Peak memory 208888 kb
Host smart-942e7040-87dd-4499-9706-274357864270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664637085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.664637085
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3079302158
Short name T841
Test name
Test status
Simulation time 1645665577 ps
CPU time 11.62 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 218276 kb
Host smart-ef16354e-2ae2-4c01-b457-664fe3023e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079302158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3079302158
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3314711757
Short name T341
Test name
Test status
Simulation time 477120717 ps
CPU time 5.27 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 217064 kb
Host smart-a6731a80-8b91-423b-b4be-bc9549e8e03f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314711757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3314711757
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1742000733
Short name T344
Test name
Test status
Simulation time 91816662 ps
CPU time 3.43 seconds
Started Aug 15 06:07:30 PM PDT 24
Finished Aug 15 06:07:33 PM PDT 24
Peak memory 218240 kb
Host smart-fb7d867b-afed-4477-a4fe-54a83625f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742000733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1742000733
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3836007665
Short name T850
Test name
Test status
Simulation time 817163742 ps
CPU time 13.76 seconds
Started Aug 15 06:07:45 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 219952 kb
Host smart-7840efe2-9cef-4b17-b95b-eb6ea2bbc124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836007665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3836007665
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2842750547
Short name T638
Test name
Test status
Simulation time 890728862 ps
CPU time 10 seconds
Started Aug 15 06:07:34 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 226000 kb
Host smart-931c3a30-3e21-496f-b0df-a244951f806a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842750547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2842750547
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3690880982
Short name T254
Test name
Test status
Simulation time 252143326 ps
CPU time 7.05 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 218208 kb
Host smart-057c04f7-4300-4c4a-8c4f-17f650765e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690880982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3690880982
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3367640142
Short name T437
Test name
Test status
Simulation time 485603421 ps
CPU time 7.06 seconds
Started Aug 15 06:07:53 PM PDT 24
Finished Aug 15 06:08:00 PM PDT 24
Peak memory 224468 kb
Host smart-a76bf214-18f6-435b-a67f-9b35c6570ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367640142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3367640142
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3662762990
Short name T424
Test name
Test status
Simulation time 528628342 ps
CPU time 4.4 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 217660 kb
Host smart-edc2c56d-0365-4f0d-bb4c-51821b72b8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662762990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3662762990
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.31022988
Short name T427
Test name
Test status
Simulation time 385421781 ps
CPU time 22.02 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 251044 kb
Host smart-00063cc5-4766-4f3b-af58-1104941cb51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31022988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.31022988
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1557855312
Short name T147
Test name
Test status
Simulation time 173133937 ps
CPU time 7.15 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 250348 kb
Host smart-c636b44b-837c-4ad5-a611-59ddf966d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557855312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1557855312
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3512922100
Short name T784
Test name
Test status
Simulation time 23342506949 ps
CPU time 128.52 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:09:49 PM PDT 24
Peak memory 278224 kb
Host smart-08b8c7db-6bf9-4784-81c0-e98cee2f9d04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512922100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3512922100
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3724261129
Short name T137
Test name
Test status
Simulation time 2728489317 ps
CPU time 57.78 seconds
Started Aug 15 06:07:32 PM PDT 24
Finished Aug 15 06:08:30 PM PDT 24
Peak memory 273260 kb
Host smart-d759d06d-fd08-4822-87db-7a7d2e3284d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3724261129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3724261129
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2894954091
Short name T868
Test name
Test status
Simulation time 30586903 ps
CPU time 0.7 seconds
Started Aug 15 06:07:27 PM PDT 24
Finished Aug 15 06:07:28 PM PDT 24
Peak memory 206984 kb
Host smart-7dda6a2c-df91-41a7-ab8e-02bcd0e8564e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894954091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2894954091
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2059297482
Short name T600
Test name
Test status
Simulation time 84158526 ps
CPU time 1.18 seconds
Started Aug 15 06:06:17 PM PDT 24
Finished Aug 15 06:06:19 PM PDT 24
Peak memory 208916 kb
Host smart-767caf49-3e1e-437a-b8e7-e1fa953d9bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059297482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2059297482
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2779750999
Short name T675
Test name
Test status
Simulation time 32300790 ps
CPU time 0.78 seconds
Started Aug 15 06:05:48 PM PDT 24
Finished Aug 15 06:05:49 PM PDT 24
Peak memory 208876 kb
Host smart-f76fe7e7-b529-4c50-901c-f27cf1586e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779750999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2779750999
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2999447242
Short name T357
Test name
Test status
Simulation time 1776435751 ps
CPU time 11.76 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:18 PM PDT 24
Peak memory 218292 kb
Host smart-1fb53e00-3736-4875-9d34-a829486c1c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999447242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2999447242
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1163135253
Short name T651
Test name
Test status
Simulation time 78963240 ps
CPU time 1.47 seconds
Started Aug 15 06:06:21 PM PDT 24
Finished Aug 15 06:06:23 PM PDT 24
Peak memory 217656 kb
Host smart-cce9d01c-d266-40d0-98e4-6b7ff5923dc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163135253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1163135253
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1505946712
Short name T706
Test name
Test status
Simulation time 5299826684 ps
CPU time 41.84 seconds
Started Aug 15 06:06:08 PM PDT 24
Finished Aug 15 06:06:50 PM PDT 24
Peak memory 218164 kb
Host smart-1d846b4b-d69d-49b6-b93b-5fece5f97c1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505946712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1505946712
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3093126892
Short name T832
Test name
Test status
Simulation time 144885318 ps
CPU time 4.44 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 217704 kb
Host smart-bf226c4a-10b4-449f-9113-ff3ef25222e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093126892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
093126892
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.93981941
Short name T225
Test name
Test status
Simulation time 187629399 ps
CPU time 3.01 seconds
Started Aug 15 06:06:17 PM PDT 24
Finished Aug 15 06:06:20 PM PDT 24
Peak memory 218224 kb
Host smart-f7e6cb18-e180-4f1e-a9db-71a613e50c31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93981941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_p
rog_failure.93981941
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3867742972
Short name T365
Test name
Test status
Simulation time 10406751753 ps
CPU time 26.63 seconds
Started Aug 15 06:06:11 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 217784 kb
Host smart-06bc9e42-f08a-4639-ac25-1aaa73ebcb76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867742972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3867742972
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2560944574
Short name T267
Test name
Test status
Simulation time 1888824145 ps
CPU time 5.41 seconds
Started Aug 15 06:06:05 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 217548 kb
Host smart-7d8badf7-8059-4fd5-9b1a-5b921c78f920
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560944574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2560944574
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3842483852
Short name T383
Test name
Test status
Simulation time 6767881199 ps
CPU time 42.72 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:47 PM PDT 24
Peak memory 250832 kb
Host smart-22ed9225-9cd2-4b56-a866-3ec1dd5703c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842483852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3842483852
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.17717481
Short name T803
Test name
Test status
Simulation time 2099566069 ps
CPU time 21.24 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 250808 kb
Host smart-fadcbe8d-9d45-4198-ade8-19c970a89958
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17717481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt
ag_state_post_trans.17717481
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4198252406
Short name T265
Test name
Test status
Simulation time 171863240 ps
CPU time 2.09 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:15 PM PDT 24
Peak memory 218136 kb
Host smart-a58e2fec-e8a8-442c-b471-4fe2dacf15b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198252406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4198252406
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1435453083
Short name T722
Test name
Test status
Simulation time 1282257137 ps
CPU time 17.72 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:21 PM PDT 24
Peak memory 214680 kb
Host smart-45f26c96-b14f-4fca-be03-078e9f99e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435453083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1435453083
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.86425102
Short name T78
Test name
Test status
Simulation time 435650097 ps
CPU time 23.31 seconds
Started Aug 15 06:06:07 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 281164 kb
Host smart-302c3040-a5ed-44f3-81f8-96b6e7c31bc5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86425102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.86425102
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.609684294
Short name T212
Test name
Test status
Simulation time 309107724 ps
CPU time 10.17 seconds
Started Aug 15 06:06:19 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 218276 kb
Host smart-4e31775d-6be9-4a24-aa60-d2cb9e81ad2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609684294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.609684294
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3267809373
Short name T481
Test name
Test status
Simulation time 1378707746 ps
CPU time 14.58 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 226004 kb
Host smart-482a2699-2aae-47ee-aada-f29eb2afb4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267809373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3267809373
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1881821835
Short name T637
Test name
Test status
Simulation time 1967113099 ps
CPU time 16.36 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:21 PM PDT 24
Peak memory 218228 kb
Host smart-2f8d8c34-a4dc-4d92-9012-fa8486dddb51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881821835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
881821835
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4267729941
Short name T338
Test name
Test status
Simulation time 664220725 ps
CPU time 14.38 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:06:07 PM PDT 24
Peak memory 218372 kb
Host smart-d0378cef-1187-4dd8-b059-60cd8fb90961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267729941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4267729941
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.900671658
Short name T289
Test name
Test status
Simulation time 221718875 ps
CPU time 2.36 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:03 PM PDT 24
Peak memory 214160 kb
Host smart-e530211b-2a30-4543-bbfe-1869bd2223aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900671658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.900671658
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1060053804
Short name T751
Test name
Test status
Simulation time 874412542 ps
CPU time 15.96 seconds
Started Aug 15 06:05:59 PM PDT 24
Finished Aug 15 06:06:15 PM PDT 24
Peak memory 250740 kb
Host smart-eef3d30c-1a93-481f-b611-46d1b61db955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060053804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1060053804
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2804851444
Short name T646
Test name
Test status
Simulation time 580678864 ps
CPU time 6.09 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:28 PM PDT 24
Peak memory 244484 kb
Host smart-f68524ac-135b-4f98-8d48-53f26f33762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804851444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2804851444
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2955965002
Short name T596
Test name
Test status
Simulation time 62112805101 ps
CPU time 572.24 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:15:36 PM PDT 24
Peak memory 283724 kb
Host smart-c51a34c9-e4a6-4826-94f2-dd773b527dfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955965002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2955965002
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1096420927
Short name T319
Test name
Test status
Simulation time 14294198 ps
CPU time 1.07 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:02 PM PDT 24
Peak memory 211868 kb
Host smart-40816fa8-6aae-44c5-862e-abd6c2681fc1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096420927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1096420927
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3507415217
Short name T213
Test name
Test status
Simulation time 122110312 ps
CPU time 1.14 seconds
Started Aug 15 06:07:32 PM PDT 24
Finished Aug 15 06:07:33 PM PDT 24
Peak memory 209072 kb
Host smart-ef027611-7212-463e-9922-dc842830ef17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507415217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3507415217
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1770057479
Short name T247
Test name
Test status
Simulation time 315787454 ps
CPU time 8.82 seconds
Started Aug 15 06:07:53 PM PDT 24
Finished Aug 15 06:08:02 PM PDT 24
Peak memory 218272 kb
Host smart-b56d3f98-0c38-4b2e-9452-4e432b1ea2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770057479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1770057479
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.824137009
Short name T153
Test name
Test status
Simulation time 82304752 ps
CPU time 2.86 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:07:40 PM PDT 24
Peak memory 217100 kb
Host smart-a6bb488d-3ab5-4755-8ab1-601749f9abb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824137009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.824137009
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2069309411
Short name T562
Test name
Test status
Simulation time 116561618 ps
CPU time 2.36 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:07:36 PM PDT 24
Peak memory 218216 kb
Host smart-6d249f48-817e-445f-a064-abec97691fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069309411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2069309411
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.136062784
Short name T408
Test name
Test status
Simulation time 191934188 ps
CPU time 9.77 seconds
Started Aug 15 06:07:34 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 218288 kb
Host smart-03b7fd00-2d34-417d-ba28-0a61da6a5fba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136062784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.136062784
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2379157850
Short name T747
Test name
Test status
Simulation time 902115653 ps
CPU time 8.19 seconds
Started Aug 15 06:07:32 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 226028 kb
Host smart-50eb20de-39ed-4336-9422-f5c22f511ebc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379157850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2379157850
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3418344703
Short name T852
Test name
Test status
Simulation time 1329395009 ps
CPU time 11.31 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 225968 kb
Host smart-bc79760a-dbba-4b81-9821-5e5b52fb12db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418344703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3418344703
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2166756336
Short name T288
Test name
Test status
Simulation time 2368247764 ps
CPU time 11.4 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:50 PM PDT 24
Peak memory 218408 kb
Host smart-4058ee22-29c2-4511-85a9-6048d49f44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166756336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2166756336
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1058678552
Short name T795
Test name
Test status
Simulation time 75956940 ps
CPU time 2.92 seconds
Started Aug 15 06:07:57 PM PDT 24
Finished Aug 15 06:08:00 PM PDT 24
Peak memory 214660 kb
Host smart-5af7ad18-224e-4c6a-a74e-59424017ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058678552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1058678552
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.986632496
Short name T615
Test name
Test status
Simulation time 195120886 ps
CPU time 18.49 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:08:09 PM PDT 24
Peak memory 250916 kb
Host smart-ca496ca4-eb4e-4c81-854b-b241a3522318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986632496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.986632496
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3918308047
Short name T378
Test name
Test status
Simulation time 206044000 ps
CPU time 2.8 seconds
Started Aug 15 06:07:27 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 222356 kb
Host smart-a443aad8-709c-459d-8f4f-91ffa7e70b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918308047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3918308047
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.145270056
Short name T299
Test name
Test status
Simulation time 15944146278 ps
CPU time 142.59 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:09:59 PM PDT 24
Peak memory 316584 kb
Host smart-e4c91d42-68a4-4bda-820b-b8e702f49f05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145270056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.145270056
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1295939613
Short name T136
Test name
Test status
Simulation time 3916007116 ps
CPU time 39.43 seconds
Started Aug 15 06:07:39 PM PDT 24
Finished Aug 15 06:08:19 PM PDT 24
Peak memory 251476 kb
Host smart-983020fb-13ac-42e0-9395-1252178f212c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1295939613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1295939613
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4246034127
Short name T3
Test name
Test status
Simulation time 23047268 ps
CPU time 0.88 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 211916 kb
Host smart-9475793e-41db-4896-b2d4-d6d677adb5c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246034127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.4246034127
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1918357410
Short name T382
Test name
Test status
Simulation time 2328288419 ps
CPU time 14.97 seconds
Started Aug 15 06:07:39 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 226124 kb
Host smart-74967f2a-3b0d-4988-8243-2bbcc5419d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918357410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1918357410
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1583129689
Short name T29
Test name
Test status
Simulation time 948232484 ps
CPU time 8.47 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 217264 kb
Host smart-ff154f30-92b0-4428-95cc-69f5f306d8bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583129689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1583129689
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.908961896
Short name T863
Test name
Test status
Simulation time 82354985 ps
CPU time 3.91 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:42 PM PDT 24
Peak memory 218244 kb
Host smart-144706cb-bd01-451b-ba27-5cc1206f02d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908961896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.908961896
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.754774226
Short name T241
Test name
Test status
Simulation time 478417492 ps
CPU time 18.59 seconds
Started Aug 15 06:07:37 PM PDT 24
Finished Aug 15 06:07:56 PM PDT 24
Peak memory 219980 kb
Host smart-622c9e19-f11f-4f1c-b79f-cb71ea88f13a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754774226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.754774226
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1473398395
Short name T143
Test name
Test status
Simulation time 341858651 ps
CPU time 12.84 seconds
Started Aug 15 06:07:39 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 225976 kb
Host smart-1738ceae-718d-4b89-83d7-e000af18a883
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473398395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1473398395
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1978248756
Short name T519
Test name
Test status
Simulation time 1561641351 ps
CPU time 9.2 seconds
Started Aug 15 06:07:35 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 218300 kb
Host smart-510ed456-45de-485e-911a-73bc99d25a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978248756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1978248756
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1983315572
Short name T47
Test name
Test status
Simulation time 239376147 ps
CPU time 8.69 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:07:45 PM PDT 24
Peak memory 224728 kb
Host smart-0ff9ae7d-d11c-455c-bbeb-b7bc6393c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983315572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1983315572
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.183234182
Short name T628
Test name
Test status
Simulation time 146721166 ps
CPU time 1.89 seconds
Started Aug 15 06:07:52 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 214068 kb
Host smart-085bd825-e380-4320-ba2a-f2cbdf8b4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183234182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.183234182
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.285598915
Short name T246
Test name
Test status
Simulation time 254487825 ps
CPU time 31.25 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:08:13 PM PDT 24
Peak memory 250896 kb
Host smart-d9a2d411-da3b-4b88-973d-6c1cd75f5e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285598915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.285598915
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.645342575
Short name T681
Test name
Test status
Simulation time 238994889 ps
CPU time 3.05 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:07:53 PM PDT 24
Peak memory 222144 kb
Host smart-b9b5b38c-b061-448e-916e-86764b775b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645342575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.645342575
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2243058423
Short name T466
Test name
Test status
Simulation time 21420710935 ps
CPU time 397.82 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:14:18 PM PDT 24
Peak memory 268688 kb
Host smart-5352162e-3945-4017-b24e-864eae370f89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243058423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2243058423
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3015835190
Short name T98
Test name
Test status
Simulation time 8349988151 ps
CPU time 103.36 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:09:22 PM PDT 24
Peak memory 270340 kb
Host smart-27244746-af41-4b5c-94c0-e3a16b18c56f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3015835190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3015835190
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2676510300
Short name T312
Test name
Test status
Simulation time 23305284 ps
CPU time 0.92 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 211840 kb
Host smart-4a383383-9439-4281-a3ec-65a05c3b3be7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676510300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2676510300
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2108229854
Short name T778
Test name
Test status
Simulation time 70198907 ps
CPU time 0.92 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:39 PM PDT 24
Peak memory 208920 kb
Host smart-1fbed239-4b89-4812-9ac4-2d72a15d99f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108229854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2108229854
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.444434355
Short name T828
Test name
Test status
Simulation time 1937659372 ps
CPU time 13.9 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 218332 kb
Host smart-23fe7a5b-7844-4b9d-b720-922b3e59754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444434355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.444434355
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.320747206
Short name T691
Test name
Test status
Simulation time 431440582 ps
CPU time 2.78 seconds
Started Aug 15 06:07:39 PM PDT 24
Finished Aug 15 06:07:42 PM PDT 24
Peak memory 217092 kb
Host smart-0135bfc3-ea34-4398-a477-885431ccbb4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320747206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.320747206
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1801444201
Short name T567
Test name
Test status
Simulation time 802294949 ps
CPU time 3.48 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 222632 kb
Host smart-02d4550c-0adf-4d91-8b60-6c1bc3b9ad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801444201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1801444201
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1304454820
Short name T834
Test name
Test status
Simulation time 466925029 ps
CPU time 8.71 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:07:40 PM PDT 24
Peak memory 225956 kb
Host smart-ca3468bc-4b5f-46d5-906e-88dbad83992a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304454820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1304454820
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3785202699
Short name T607
Test name
Test status
Simulation time 221061588 ps
CPU time 8.47 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 226024 kb
Host smart-22bc38c7-9ea5-4b1a-b8a0-ed3c3467a9b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785202699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3785202699
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3749262876
Short name T842
Test name
Test status
Simulation time 307771159 ps
CPU time 7.44 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 226104 kb
Host smart-f25adbad-a4be-4160-bd41-7bbc955c398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749262876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3749262876
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3709976405
Short name T67
Test name
Test status
Simulation time 102428007 ps
CPU time 1.77 seconds
Started Aug 15 06:07:30 PM PDT 24
Finished Aug 15 06:07:32 PM PDT 24
Peak memory 217648 kb
Host smart-37e20244-5e30-4ca9-a96b-5d0e4e0bfa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709976405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3709976405
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2102906413
Short name T617
Test name
Test status
Simulation time 969453071 ps
CPU time 19.86 seconds
Started Aug 15 06:07:36 PM PDT 24
Finished Aug 15 06:07:56 PM PDT 24
Peak memory 251000 kb
Host smart-ae666aff-f866-4c04-a78b-7a4347a95df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102906413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2102906413
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3161595379
Short name T317
Test name
Test status
Simulation time 77788009 ps
CPU time 8.21 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:47 PM PDT 24
Peak memory 250916 kb
Host smart-b2afaa2d-5122-42ca-90a3-9f67b5a12184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161595379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3161595379
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.4093613346
Short name T94
Test name
Test status
Simulation time 4788441186 ps
CPU time 94.08 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:09:12 PM PDT 24
Peak memory 283764 kb
Host smart-c9fc3e77-c5cc-402b-8741-cc0818b0cd83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093613346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.4093613346
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.50180490
Short name T773
Test name
Test status
Simulation time 11027119344 ps
CPU time 89.48 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:09:01 PM PDT 24
Peak memory 250280 kb
Host smart-462c47bf-2275-4a62-8528-dfdee4202a4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=50180490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.50180490
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4121657394
Short name T491
Test name
Test status
Simulation time 47659293 ps
CPU time 0.84 seconds
Started Aug 15 06:07:45 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 211908 kb
Host smart-160e728a-e05c-404c-8786-f115bd2c057d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121657394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4121657394
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1133359616
Short name T683
Test name
Test status
Simulation time 46945766 ps
CPU time 0.84 seconds
Started Aug 15 06:07:41 PM PDT 24
Finished Aug 15 06:07:42 PM PDT 24
Peak memory 208644 kb
Host smart-41365f08-e8ba-4a97-80ca-bb1e1b2f9b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133359616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1133359616
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2720543675
Short name T41
Test name
Test status
Simulation time 263695800 ps
CPU time 13.06 seconds
Started Aug 15 06:07:35 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 218300 kb
Host smart-4ce83168-077f-43a0-b025-82359d8e6e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720543675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2720543675
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.700664421
Short name T34
Test name
Test status
Simulation time 818196517 ps
CPU time 4.47 seconds
Started Aug 15 06:07:34 PM PDT 24
Finished Aug 15 06:07:38 PM PDT 24
Peak memory 217344 kb
Host smart-3ef57722-96ab-4687-8455-34219ee82f34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700664421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.700664421
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3961695972
Short name T816
Test name
Test status
Simulation time 46156620 ps
CPU time 2.38 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 222176 kb
Host smart-fa516d75-1f50-4dd0-b3ff-fbe4ddc39fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961695972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3961695972
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.634404268
Short name T526
Test name
Test status
Simulation time 2438205279 ps
CPU time 18.76 seconds
Started Aug 15 06:07:56 PM PDT 24
Finished Aug 15 06:08:15 PM PDT 24
Peak memory 226144 kb
Host smart-149a3182-64a6-4abe-96a6-451a6020e1c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634404268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.634404268
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2052751364
Short name T511
Test name
Test status
Simulation time 174662905 ps
CPU time 7.98 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:48 PM PDT 24
Peak memory 218204 kb
Host smart-9e3bfffe-ac9e-4173-9955-b85ecd6d65b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052751364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2052751364
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2919120848
Short name T431
Test name
Test status
Simulation time 273132090 ps
CPU time 11.27 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:53 PM PDT 24
Peak memory 225984 kb
Host smart-58cbdfc9-c855-466b-a123-5923fc14ad84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919120848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2919120848
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3379147146
Short name T150
Test name
Test status
Simulation time 1681248213 ps
CPU time 14.68 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:08:02 PM PDT 24
Peak memory 226056 kb
Host smart-10370fa3-9b44-4bdf-9cd9-427e3eebce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379147146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3379147146
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2560880300
Short name T36
Test name
Test status
Simulation time 64626623 ps
CPU time 1.03 seconds
Started Aug 15 06:07:38 PM PDT 24
Finished Aug 15 06:07:39 PM PDT 24
Peak memory 217608 kb
Host smart-3b5d4b23-7475-4c3a-9f44-88271925dd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560880300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2560880300
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.832453667
Short name T787
Test name
Test status
Simulation time 167777631 ps
CPU time 21.38 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:08:09 PM PDT 24
Peak memory 251008 kb
Host smart-785c1eba-e3aa-433e-82a7-291b8b7ad2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832453667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.832453667
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1540044091
Short name T261
Test name
Test status
Simulation time 574486428 ps
CPU time 4.1 seconds
Started Aug 15 06:07:33 PM PDT 24
Finished Aug 15 06:07:37 PM PDT 24
Peak memory 226348 kb
Host smart-2163628e-f5f9-4f04-a98f-99ffdbc45fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540044091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1540044091
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3937935313
Short name T857
Test name
Test status
Simulation time 15369757087 ps
CPU time 15.08 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:08:07 PM PDT 24
Peak memory 220112 kb
Host smart-a375b36b-128f-423f-b405-1e7a41440e37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937935313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3937935313
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3437220943
Short name T464
Test name
Test status
Simulation time 2826472674 ps
CPU time 62.19 seconds
Started Aug 15 06:07:31 PM PDT 24
Finished Aug 15 06:08:33 PM PDT 24
Peak memory 251008 kb
Host smart-621b87b6-9d02-4fd2-b66c-b65732dfbe3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3437220943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3437220943
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.767713034
Short name T330
Test name
Test status
Simulation time 24504710 ps
CPU time 0.91 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:30 PM PDT 24
Peak memory 211892 kb
Host smart-95a9b420-0270-402b-95e2-061721510e23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767713034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.767713034
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4011505194
Short name T84
Test name
Test status
Simulation time 46782378 ps
CPU time 0.89 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:07:52 PM PDT 24
Peak memory 208808 kb
Host smart-feb2ba37-0c96-49c6-bae9-d3916b342589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011505194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4011505194
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.58882895
Short name T642
Test name
Test status
Simulation time 1041122025 ps
CPU time 12.99 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 226096 kb
Host smart-aa0be668-c33e-4e15-85d9-b5b777c609fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58882895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.58882895
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3674255605
Short name T771
Test name
Test status
Simulation time 405878646 ps
CPU time 5.96 seconds
Started Aug 15 06:07:41 PM PDT 24
Finished Aug 15 06:07:48 PM PDT 24
Peak memory 217060 kb
Host smart-f8ebfdeb-c8c4-4d81-84da-8e9cd131adf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674255605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3674255605
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1493630089
Short name T368
Test name
Test status
Simulation time 114718874 ps
CPU time 1.89 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 218216 kb
Host smart-ff9c07f7-1371-4a3a-9337-0ba9367eb7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493630089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1493630089
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1383997919
Short name T19
Test name
Test status
Simulation time 914768453 ps
CPU time 10.31 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:08:02 PM PDT 24
Peak memory 226092 kb
Host smart-f9f2350c-9918-4b56-9178-bbb8c2f3b6f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383997919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1383997919
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3928088910
Short name T753
Test name
Test status
Simulation time 2262997126 ps
CPU time 16.81 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 226096 kb
Host smart-3adf9951-f4c9-4f58-9ee9-8e66936148cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928088910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3928088910
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1339297028
Short name T635
Test name
Test status
Simulation time 1499918513 ps
CPU time 13.44 seconds
Started Aug 15 06:07:44 PM PDT 24
Finished Aug 15 06:07:57 PM PDT 24
Peak memory 218224 kb
Host smart-efc9af4f-ade0-472c-abbf-c9657ebdffa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339297028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1339297028
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2247425030
Short name T549
Test name
Test status
Simulation time 290877690 ps
CPU time 8.47 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 225996 kb
Host smart-543c043f-4729-4be6-ba50-aeccb4e64d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247425030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2247425030
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.843734318
Short name T375
Test name
Test status
Simulation time 224253936 ps
CPU time 2.28 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:07:53 PM PDT 24
Peak memory 214340 kb
Host smart-3f9dd330-368f-4bef-8d99-bb22578af4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843734318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.843734318
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2114307112
Short name T363
Test name
Test status
Simulation time 1514159595 ps
CPU time 22.07 seconds
Started Aug 15 06:07:29 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 250904 kb
Host smart-b6f8960a-b22f-4092-91c7-670b824293ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114307112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2114307112
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3634550692
Short name T157
Test name
Test status
Simulation time 87115168 ps
CPU time 7.37 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 250788 kb
Host smart-ade4a507-637e-4faa-bc0d-d4fd3812e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634550692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3634550692
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.975138285
Short name T430
Test name
Test status
Simulation time 2778540923 ps
CPU time 48.9 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:08:40 PM PDT 24
Peak memory 250184 kb
Host smart-58ba790d-df67-4928-bd65-b55a5ae9ed52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975138285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.975138285
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2089600093
Short name T781
Test name
Test status
Simulation time 45072281 ps
CPU time 0.81 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 211944 kb
Host smart-fe25070b-edd1-4c31-87ac-237ecfa8771d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089600093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2089600093
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2347410768
Short name T866
Test name
Test status
Simulation time 15586086 ps
CPU time 0.9 seconds
Started Aug 15 06:07:56 PM PDT 24
Finished Aug 15 06:07:57 PM PDT 24
Peak memory 208824 kb
Host smart-cba8683d-5881-4407-8496-8ccdcfcf356a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347410768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2347410768
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.304781967
Short name T420
Test name
Test status
Simulation time 237508085 ps
CPU time 10.59 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:08:02 PM PDT 24
Peak memory 218292 kb
Host smart-17e3ed56-0f1e-45bc-a6b7-c970655907a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304781967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.304781967
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4204793158
Short name T462
Test name
Test status
Simulation time 671957908 ps
CPU time 7 seconds
Started Aug 15 06:07:41 PM PDT 24
Finished Aug 15 06:07:48 PM PDT 24
Peak memory 217116 kb
Host smart-0f6087d0-eb3c-4d8a-9336-85837c36a9b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204793158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.4204793158
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2735726602
Short name T389
Test name
Test status
Simulation time 87448983 ps
CPU time 3.88 seconds
Started Aug 15 06:07:41 PM PDT 24
Finished Aug 15 06:07:45 PM PDT 24
Peak memory 222572 kb
Host smart-8c32b6b4-a6df-4ca2-ac1f-96d62e7e2162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735726602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2735726602
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3032961599
Short name T800
Test name
Test status
Simulation time 514696187 ps
CPU time 11.49 seconds
Started Aug 15 06:07:54 PM PDT 24
Finished Aug 15 06:08:06 PM PDT 24
Peak memory 225788 kb
Host smart-c592e27f-db05-4213-9bc0-43106b27c2e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032961599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3032961599
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.931413946
Short name T667
Test name
Test status
Simulation time 574889804 ps
CPU time 13.22 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:56 PM PDT 24
Peak memory 225992 kb
Host smart-529c49f9-c1ed-4168-8a5b-416438807334
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931413946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.931413946
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1767959992
Short name T533
Test name
Test status
Simulation time 330828021 ps
CPU time 10.36 seconds
Started Aug 15 06:07:44 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 226048 kb
Host smart-d31a2c68-97b8-46b5-a1c6-853680c1d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767959992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1767959992
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2990699563
Short name T154
Test name
Test status
Simulation time 53530146 ps
CPU time 4.01 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 215216 kb
Host smart-6ac35124-c193-45e1-9b99-02744cb9cf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990699563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2990699563
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1184621132
Short name T836
Test name
Test status
Simulation time 188990889 ps
CPU time 31.85 seconds
Started Aug 15 06:08:05 PM PDT 24
Finished Aug 15 06:08:37 PM PDT 24
Peak memory 250988 kb
Host smart-15d95e7a-677c-483e-ae58-d820569f3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184621132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1184621132
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2661724189
Short name T387
Test name
Test status
Simulation time 93802667 ps
CPU time 7.8 seconds
Started Aug 15 06:07:58 PM PDT 24
Finished Aug 15 06:08:06 PM PDT 24
Peak memory 247340 kb
Host smart-2a700e1c-d564-40af-bd09-ab9f04c6c6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661724189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2661724189
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3443910640
Short name T463
Test name
Test status
Simulation time 19959710344 ps
CPU time 130.02 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:10:02 PM PDT 24
Peak memory 283716 kb
Host smart-194a7d0e-813f-430e-b8ec-18ca5da3a35f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443910640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3443910640
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2437621753
Short name T282
Test name
Test status
Simulation time 77397739 ps
CPU time 0.82 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 211880 kb
Host smart-1ace2381-8e7f-41e1-ac4a-8c98b25623b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437621753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2437621753
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.440677241
Short name T623
Test name
Test status
Simulation time 21238747 ps
CPU time 0.92 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 208892 kb
Host smart-e9938592-7d77-40eb-ace2-5de56c8c01d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440677241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.440677241
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1099177255
Short name T44
Test name
Test status
Simulation time 1067079796 ps
CPU time 15.67 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:08:06 PM PDT 24
Peak memory 218232 kb
Host smart-1fa3fd30-b4b4-46fe-9283-ec417e7ee32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099177255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1099177255
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.33962674
Short name T621
Test name
Test status
Simulation time 436697634 ps
CPU time 4.92 seconds
Started Aug 15 06:08:06 PM PDT 24
Finished Aug 15 06:08:11 PM PDT 24
Peak memory 217116 kb
Host smart-70664111-f518-43c0-a1eb-af36b6fa65a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33962674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.33962674
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1114614390
Short name T398
Test name
Test status
Simulation time 290818249 ps
CPU time 3.7 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 222532 kb
Host smart-edfba5cb-73a7-49f2-9286-26594658244d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114614390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1114614390
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.4221606181
Short name T253
Test name
Test status
Simulation time 252786710 ps
CPU time 11.8 seconds
Started Aug 15 06:08:05 PM PDT 24
Finished Aug 15 06:08:17 PM PDT 24
Peak memory 226100 kb
Host smart-557942fd-be9e-4d76-9fef-0467a5b797f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221606181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.4221606181
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3456924842
Short name T209
Test name
Test status
Simulation time 987584353 ps
CPU time 20.93 seconds
Started Aug 15 06:07:52 PM PDT 24
Finished Aug 15 06:08:13 PM PDT 24
Peak memory 225972 kb
Host smart-f46be90a-5df1-4831-8d28-be17f236e1bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456924842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3456924842
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3557666795
Short name T248
Test name
Test status
Simulation time 480069513 ps
CPU time 7.53 seconds
Started Aug 15 06:07:39 PM PDT 24
Finished Aug 15 06:07:47 PM PDT 24
Peak memory 218220 kb
Host smart-dae13f7b-a1da-4a45-9bc4-f84b9c266fa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557666795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3557666795
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4062045881
Short name T401
Test name
Test status
Simulation time 1147695838 ps
CPU time 7.54 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:50 PM PDT 24
Peak memory 225220 kb
Host smart-bd93f16e-cea3-42c6-aa68-cfadcfaf12c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062045881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4062045881
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2906127918
Short name T285
Test name
Test status
Simulation time 95482360 ps
CPU time 2.31 seconds
Started Aug 15 06:08:02 PM PDT 24
Finished Aug 15 06:08:04 PM PDT 24
Peak memory 222632 kb
Host smart-72fb9817-35d4-4196-a4b2-5f11d96c28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906127918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2906127918
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3387239181
Short name T477
Test name
Test status
Simulation time 1094854657 ps
CPU time 30.37 seconds
Started Aug 15 06:07:58 PM PDT 24
Finished Aug 15 06:08:29 PM PDT 24
Peak memory 250888 kb
Host smart-25380f89-d2e5-44eb-bd03-e63031ba643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387239181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3387239181
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3750959618
Short name T684
Test name
Test status
Simulation time 296242222 ps
CPU time 3.05 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:43 PM PDT 24
Peak memory 222676 kb
Host smart-4eabe656-a621-4249-881c-7e3cd760b917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750959618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3750959618
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3255580345
Short name T390
Test name
Test status
Simulation time 1546704622 ps
CPU time 50.32 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:08:41 PM PDT 24
Peak memory 219112 kb
Host smart-c87ba08b-7f38-462b-8a4f-d863008d4943
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255580345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3255580345
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1200082672
Short name T352
Test name
Test status
Simulation time 30740676 ps
CPU time 0.95 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 217704 kb
Host smart-59f7e9aa-e27e-4c8f-bca8-206b8afae191
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200082672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1200082672
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3567445160
Short name T88
Test name
Test status
Simulation time 11614757 ps
CPU time 0.96 seconds
Started Aug 15 06:07:54 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 208880 kb
Host smart-d64718d2-cb2a-4696-82c8-90c1497dae99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567445160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3567445160
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.217449397
Short name T499
Test name
Test status
Simulation time 2091163471 ps
CPU time 11.51 seconds
Started Aug 15 06:07:42 PM PDT 24
Finished Aug 15 06:07:54 PM PDT 24
Peak memory 218300 kb
Host smart-6294df9c-0058-4342-8027-405963d0d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217449397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.217449397
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3589770708
Short name T23
Test name
Test status
Simulation time 279173677 ps
CPU time 4.61 seconds
Started Aug 15 06:08:02 PM PDT 24
Finished Aug 15 06:08:06 PM PDT 24
Peak memory 217084 kb
Host smart-8aa63e88-59e2-4d5e-95f1-4991886f50da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589770708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3589770708
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.232553832
Short name T216
Test name
Test status
Simulation time 225525640 ps
CPU time 2.13 seconds
Started Aug 15 06:07:59 PM PDT 24
Finished Aug 15 06:08:01 PM PDT 24
Peak memory 218252 kb
Host smart-9ac56ae4-8b71-4649-9eb0-4b9d91e4c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232553832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.232553832
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.472897577
Short name T355
Test name
Test status
Simulation time 482638679 ps
CPU time 13.1 seconds
Started Aug 15 06:08:04 PM PDT 24
Finished Aug 15 06:08:17 PM PDT 24
Peak memory 226096 kb
Host smart-54d5f7f4-8ce9-493b-8a57-127297f08f01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472897577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.472897577
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4117468549
Short name T648
Test name
Test status
Simulation time 474214333 ps
CPU time 10.21 seconds
Started Aug 15 06:08:04 PM PDT 24
Finished Aug 15 06:08:14 PM PDT 24
Peak memory 225972 kb
Host smart-410f6356-8d32-422e-9d94-649f2f7efd15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117468549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4117468549
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2639213187
Short name T484
Test name
Test status
Simulation time 3851073766 ps
CPU time 7.94 seconds
Started Aug 15 06:07:47 PM PDT 24
Finished Aug 15 06:07:55 PM PDT 24
Peak memory 218252 kb
Host smart-4f9cf9ef-e232-4cdf-8fb2-4f15cbd1fca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639213187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2639213187
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.382697338
Short name T271
Test name
Test status
Simulation time 401423820 ps
CPU time 7.05 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:07:58 PM PDT 24
Peak memory 218348 kb
Host smart-397d03b7-1f8f-45b3-a850-a105ee8fea24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382697338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.382697338
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1179758350
Short name T612
Test name
Test status
Simulation time 53084388 ps
CPU time 2.37 seconds
Started Aug 15 06:07:45 PM PDT 24
Finished Aug 15 06:07:47 PM PDT 24
Peak memory 214428 kb
Host smart-e4ae4beb-eafa-4bdd-a579-48fe0fc08721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179758350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1179758350
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3826386562
Short name T231
Test name
Test status
Simulation time 1139136232 ps
CPU time 33.68 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:08:24 PM PDT 24
Peak memory 250872 kb
Host smart-899581d7-f0d7-450f-8933-9140fd27c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826386562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3826386562
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2808806972
Short name T152
Test name
Test status
Simulation time 348704337 ps
CPU time 3.47 seconds
Started Aug 15 06:07:45 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 222628 kb
Host smart-93ede790-7490-4705-a9bd-b42a0a5525b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808806972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2808806972
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1515184187
Short name T60
Test name
Test status
Simulation time 974951536 ps
CPU time 37.73 seconds
Started Aug 15 06:07:50 PM PDT 24
Finished Aug 15 06:08:28 PM PDT 24
Peak memory 267244 kb
Host smart-7bb4146a-88e9-45a7-8440-ef9f81e84ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515184187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1515184187
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.225729305
Short name T493
Test name
Test status
Simulation time 13607255 ps
CPU time 0.93 seconds
Started Aug 15 06:07:40 PM PDT 24
Finished Aug 15 06:07:41 PM PDT 24
Peak memory 212076 kb
Host smart-b0efebd2-d48c-4966-be9e-d303343c6e15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225729305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.225729305
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1497851531
Short name T258
Test name
Test status
Simulation time 57585491 ps
CPU time 1.05 seconds
Started Aug 15 06:08:10 PM PDT 24
Finished Aug 15 06:08:11 PM PDT 24
Peak memory 208896 kb
Host smart-aff46fe0-0fb2-4705-9f21-9337c0777bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497851531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1497851531
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.989256130
Short name T269
Test name
Test status
Simulation time 1484777582 ps
CPU time 12.34 seconds
Started Aug 15 06:07:53 PM PDT 24
Finished Aug 15 06:08:05 PM PDT 24
Peak memory 218268 kb
Host smart-63c43678-1b3b-4c2d-8a9f-d3f9d6a11a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989256130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.989256130
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2076486504
Short name T733
Test name
Test status
Simulation time 334532517 ps
CPU time 5.34 seconds
Started Aug 15 06:07:58 PM PDT 24
Finished Aug 15 06:08:04 PM PDT 24
Peak memory 217172 kb
Host smart-4f9918e6-54ab-4f42-ab24-6aaafc851565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076486504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2076486504
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.511483166
Short name T371
Test name
Test status
Simulation time 28457141 ps
CPU time 2.12 seconds
Started Aug 15 06:08:03 PM PDT 24
Finished Aug 15 06:08:05 PM PDT 24
Peak memory 218244 kb
Host smart-8a87a80c-75dd-4c62-b4b7-89eb22b6d167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511483166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.511483166
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2547343449
Short name T799
Test name
Test status
Simulation time 753651632 ps
CPU time 13.19 seconds
Started Aug 15 06:07:57 PM PDT 24
Finished Aug 15 06:08:10 PM PDT 24
Peak memory 226076 kb
Host smart-046e9749-41a8-4006-82c0-a096eefdf569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547343449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2547343449
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.772917285
Short name T647
Test name
Test status
Simulation time 233771536 ps
CPU time 7.95 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 226020 kb
Host smart-e957fac0-b699-43c0-9348-aa1e6a30833c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772917285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.772917285
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1657159002
Short name T736
Test name
Test status
Simulation time 977692956 ps
CPU time 9.92 seconds
Started Aug 15 06:08:05 PM PDT 24
Finished Aug 15 06:08:15 PM PDT 24
Peak memory 226044 kb
Host smart-86853dc8-87c3-454c-a222-359905b711a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657159002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1657159002
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.65552659
Short name T386
Test name
Test status
Simulation time 941047159 ps
CPU time 6.86 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 218364 kb
Host smart-d4f9e845-3b75-4be0-a5c1-7356844f91da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65552659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.65552659
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2652981523
Short name T417
Test name
Test status
Simulation time 54281163 ps
CPU time 2.34 seconds
Started Aug 15 06:07:57 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 222564 kb
Host smart-53f634c8-c67a-4bac-8041-d7e1aaf39838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652981523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2652981523
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3451825155
Short name T777
Test name
Test status
Simulation time 377746283 ps
CPU time 23.66 seconds
Started Aug 15 06:07:51 PM PDT 24
Finished Aug 15 06:08:15 PM PDT 24
Peak memory 250864 kb
Host smart-7d19a44a-7929-4979-9cd1-d96866a838ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451825155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3451825155
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.473438244
Short name T343
Test name
Test status
Simulation time 160989282 ps
CPU time 7.26 seconds
Started Aug 15 06:07:57 PM PDT 24
Finished Aug 15 06:08:04 PM PDT 24
Peak memory 244496 kb
Host smart-4a1b16fa-50cf-40cd-b866-6f0e753f233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473438244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.473438244
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.461448746
Short name T826
Test name
Test status
Simulation time 1310396280 ps
CPU time 44.54 seconds
Started Aug 15 06:08:04 PM PDT 24
Finished Aug 15 06:08:49 PM PDT 24
Peak memory 248808 kb
Host smart-ad99aa59-16ec-4097-9c65-ccf4f563028c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461448746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.461448746
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2021418224
Short name T679
Test name
Test status
Simulation time 2706057851 ps
CPU time 102.11 seconds
Started Aug 15 06:08:00 PM PDT 24
Finished Aug 15 06:09:42 PM PDT 24
Peak memory 251044 kb
Host smart-1bc1f9b6-a0f7-477e-b33c-58ee1722317c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2021418224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2021418224
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2829668540
Short name T782
Test name
Test status
Simulation time 13421800 ps
CPU time 1.06 seconds
Started Aug 15 06:07:45 PM PDT 24
Finished Aug 15 06:07:47 PM PDT 24
Peak memory 211972 kb
Host smart-0733cc33-e97f-48d7-bbd8-8e7b2985af39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829668540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2829668540
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2341512011
Short name T211
Test name
Test status
Simulation time 13143390 ps
CPU time 0.96 seconds
Started Aug 15 06:08:04 PM PDT 24
Finished Aug 15 06:08:05 PM PDT 24
Peak memory 208872 kb
Host smart-a235d293-43bf-47a8-899d-eba8e0ceca28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341512011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2341512011
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3988637678
Short name T739
Test name
Test status
Simulation time 757862519 ps
CPU time 11.79 seconds
Started Aug 15 06:08:02 PM PDT 24
Finished Aug 15 06:08:14 PM PDT 24
Peak memory 226072 kb
Host smart-8330f308-3c05-42b3-8926-b481bc382808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988637678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3988637678
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2281424838
Short name T874
Test name
Test status
Simulation time 3005579338 ps
CPU time 8.32 seconds
Started Aug 15 06:08:02 PM PDT 24
Finished Aug 15 06:08:10 PM PDT 24
Peak memory 217484 kb
Host smart-0c1379f6-5354-48e3-87cc-af3249823cae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281424838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2281424838
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2089399987
Short name T85
Test name
Test status
Simulation time 403829899 ps
CPU time 4.58 seconds
Started Aug 15 06:08:03 PM PDT 24
Finished Aug 15 06:08:08 PM PDT 24
Peak memory 218276 kb
Host smart-81a221e7-9691-41bc-a5f0-e71faf5ee95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089399987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2089399987
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.771905399
Short name T528
Test name
Test status
Simulation time 285061933 ps
CPU time 12.56 seconds
Started Aug 15 06:08:09 PM PDT 24
Finished Aug 15 06:08:21 PM PDT 24
Peak memory 224720 kb
Host smart-c2b5bb07-095c-4f58-9219-e29ff5e47ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771905399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.771905399
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.608790453
Short name T660
Test name
Test status
Simulation time 1133170249 ps
CPU time 7.3 seconds
Started Aug 15 06:08:10 PM PDT 24
Finished Aug 15 06:08:18 PM PDT 24
Peak memory 224648 kb
Host smart-56aec74a-e712-4994-a1ad-4c2dcdf5ab3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608790453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.608790453
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.161234914
Short name T693
Test name
Test status
Simulation time 302046037 ps
CPU time 8.8 seconds
Started Aug 15 06:08:07 PM PDT 24
Finished Aug 15 06:08:16 PM PDT 24
Peak memory 226032 kb
Host smart-4d755251-5d4a-492e-ac66-7f31d6145c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161234914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.161234914
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.422701791
Short name T776
Test name
Test status
Simulation time 2311206532 ps
CPU time 13.48 seconds
Started Aug 15 06:08:13 PM PDT 24
Finished Aug 15 06:08:27 PM PDT 24
Peak memory 226004 kb
Host smart-53c6f85b-d08e-4283-aa95-f392478099a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422701791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.422701791
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2419439678
Short name T620
Test name
Test status
Simulation time 27280388 ps
CPU time 1.77 seconds
Started Aug 15 06:08:02 PM PDT 24
Finished Aug 15 06:08:04 PM PDT 24
Peak memory 217600 kb
Host smart-8646da8d-d079-4b9d-8ae7-1cf4ca6c9b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419439678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2419439678
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.18237441
Short name T734
Test name
Test status
Simulation time 953190406 ps
CPU time 21.05 seconds
Started Aug 15 06:08:00 PM PDT 24
Finished Aug 15 06:08:21 PM PDT 24
Peak memory 250852 kb
Host smart-c9a8f18c-05f1-4353-a5bd-263b01c68bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18237441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.18237441
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1357672318
Short name T438
Test name
Test status
Simulation time 46020881 ps
CPU time 6.25 seconds
Started Aug 15 06:08:06 PM PDT 24
Finished Aug 15 06:08:12 PM PDT 24
Peak memory 246928 kb
Host smart-36cc8a80-8536-401e-8ba7-004415abde68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357672318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1357672318
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3214919407
Short name T661
Test name
Test status
Simulation time 13838621 ps
CPU time 0.87 seconds
Started Aug 15 06:08:07 PM PDT 24
Finished Aug 15 06:08:08 PM PDT 24
Peak memory 211872 kb
Host smart-4b917021-3ed5-4c98-9953-53ee2c96a50d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214919407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3214919407
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2927328236
Short name T602
Test name
Test status
Simulation time 172512142 ps
CPU time 1.03 seconds
Started Aug 15 06:06:16 PM PDT 24
Finished Aug 15 06:06:17 PM PDT 24
Peak memory 208888 kb
Host smart-592ec079-6140-44e8-95a0-d204591df72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927328236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2927328236
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2185226575
Short name T461
Test name
Test status
Simulation time 22207339 ps
CPU time 0.84 seconds
Started Aug 15 06:06:14 PM PDT 24
Finished Aug 15 06:06:15 PM PDT 24
Peak memory 208540 kb
Host smart-aaaf4991-066e-48c7-9e24-85fffd6abc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185226575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2185226575
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4041737420
Short name T332
Test name
Test status
Simulation time 318783519 ps
CPU time 11.4 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 218428 kb
Host smart-3af8ba7d-79ff-4ecb-af9e-fffae51cb1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041737420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4041737420
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1155843811
Short name T32
Test name
Test status
Simulation time 3770828545 ps
CPU time 22.47 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:41 PM PDT 24
Peak memory 217692 kb
Host smart-94289afc-ddf9-4d27-b84d-b4394f8a36f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155843811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1155843811
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1492771482
Short name T290
Test name
Test status
Simulation time 1460905601 ps
CPU time 26.39 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 218868 kb
Host smart-1ecbe713-d95f-42d4-8f45-fc8c88c7840f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492771482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1492771482
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2540296408
Short name T512
Test name
Test status
Simulation time 263149227 ps
CPU time 7.17 seconds
Started Aug 15 06:06:21 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 217460 kb
Host smart-33e63d33-a578-47f6-b692-1b6c12a583a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540296408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
540296408
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3826007429
Short name T581
Test name
Test status
Simulation time 553067993 ps
CPU time 16.74 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:06:13 PM PDT 24
Peak memory 218248 kb
Host smart-997bf747-3977-434a-b532-f52b3e07fcb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826007429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3826007429
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.213044173
Short name T283
Test name
Test status
Simulation time 5750208784 ps
CPU time 35.93 seconds
Started Aug 15 06:06:21 PM PDT 24
Finished Aug 15 06:06:57 PM PDT 24
Peak memory 217584 kb
Host smart-63c236d4-32d9-4137-82bf-bbf402404864
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213044173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.213044173
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4159285330
Short name T89
Test name
Test status
Simulation time 598737564 ps
CPU time 4.34 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 217552 kb
Host smart-f02751c3-3a6e-4337-a74a-09a65de4ddc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159285330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4159285330
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1524196068
Short name T257
Test name
Test status
Simulation time 1606741083 ps
CPU time 58.9 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 267252 kb
Host smart-18d66352-428d-4d27-966d-eca6789d6211
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524196068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1524196068
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3346375073
Short name T435
Test name
Test status
Simulation time 627601098 ps
CPU time 16.36 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:41 PM PDT 24
Peak memory 250840 kb
Host smart-2bf57d0e-f1b9-4f0d-9fbe-d27cd90b285d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346375073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3346375073
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1308992663
Short name T310
Test name
Test status
Simulation time 329831618 ps
CPU time 4.33 seconds
Started Aug 15 06:06:17 PM PDT 24
Finished Aug 15 06:06:22 PM PDT 24
Peak memory 218224 kb
Host smart-5685a228-ee7a-49c7-b0ab-f6e25a9d7c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308992663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1308992663
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1223498623
Short name T819
Test name
Test status
Simulation time 423209918 ps
CPU time 5.87 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:24 PM PDT 24
Peak memory 214384 kb
Host smart-a9ecbf78-c984-4bbb-bb69-b1bfeb00baf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223498623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1223498623
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3501304620
Short name T76
Test name
Test status
Simulation time 1511594909 ps
CPU time 8.3 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:18 PM PDT 24
Peak memory 218320 kb
Host smart-dbf67f09-794d-4eff-a3d7-598622a8e2be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501304620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3501304620
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2630884259
Short name T372
Test name
Test status
Simulation time 801034153 ps
CPU time 10.15 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:17 PM PDT 24
Peak memory 225984 kb
Host smart-8803f985-6460-4771-8984-07657ead0e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630884259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2630884259
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2948201978
Short name T708
Test name
Test status
Simulation time 626647664 ps
CPU time 10.55 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:21 PM PDT 24
Peak memory 226008 kb
Host smart-e4f81d33-0258-40a9-a930-57e116a3122e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948201978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
948201978
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.70285080
Short name T719
Test name
Test status
Simulation time 247330710 ps
CPU time 10.4 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 226068 kb
Host smart-f217cdd6-9973-4134-b4a6-643cce5e08e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70285080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.70285080
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2539810748
Short name T226
Test name
Test status
Simulation time 54947394 ps
CPU time 2.7 seconds
Started Aug 15 06:06:08 PM PDT 24
Finished Aug 15 06:06:11 PM PDT 24
Peak memory 217624 kb
Host smart-2c4878f7-ec9e-4843-88b5-e0294f05dcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539810748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2539810748
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3915009929
Short name T432
Test name
Test status
Simulation time 1270488016 ps
CPU time 25.83 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:27 PM PDT 24
Peak memory 250864 kb
Host smart-859a432d-ef18-425d-b798-ea5b15be95d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915009929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3915009929
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.348959424
Short name T592
Test name
Test status
Simulation time 181730271 ps
CPU time 3.62 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:12 PM PDT 24
Peak memory 226500 kb
Host smart-13f11569-1e9e-4dde-a235-a961c6ac3a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348959424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.348959424
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1776923595
Short name T460
Test name
Test status
Simulation time 2352610186 ps
CPU time 18.87 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 218048 kb
Host smart-ec568349-c320-4152-a54f-51011304650d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776923595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1776923595
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1129644050
Short name T252
Test name
Test status
Simulation time 10798844 ps
CPU time 0.92 seconds
Started Aug 15 06:06:05 PM PDT 24
Finished Aug 15 06:06:06 PM PDT 24
Peak memory 211828 kb
Host smart-8cd75620-44f0-4c59-a93e-6fafd939d421
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129644050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1129644050
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3084228123
Short name T517
Test name
Test status
Simulation time 45820849 ps
CPU time 0.95 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:06:16 PM PDT 24
Peak memory 208828 kb
Host smart-4ff24758-9796-45d0-ac04-c10672289d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084228123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3084228123
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2596922898
Short name T195
Test name
Test status
Simulation time 30247600 ps
CPU time 0.8 seconds
Started Aug 15 06:06:10 PM PDT 24
Finished Aug 15 06:06:16 PM PDT 24
Peak memory 208908 kb
Host smart-cf1e8103-b1d4-41c2-8e13-f9b83bc6278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596922898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2596922898
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2217429927
Short name T373
Test name
Test status
Simulation time 747828486 ps
CPU time 7.83 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:12 PM PDT 24
Peak memory 218304 kb
Host smart-9dda63e2-dd97-4e47-83ca-992c3fe4d7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217429927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2217429927
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.483547054
Short name T720
Test name
Test status
Simulation time 350881719 ps
CPU time 9.8 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:35 PM PDT 24
Peak memory 217604 kb
Host smart-5a66db8b-507e-467b-b891-15807af3717e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483547054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.483547054
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1459441851
Short name T38
Test name
Test status
Simulation time 10049251056 ps
CPU time 69.99 seconds
Started Aug 15 06:06:11 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 218932 kb
Host smart-c7f3bc03-f650-4099-afff-9ec926d950ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459441851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1459441851
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.4248181246
Short name T470
Test name
Test status
Simulation time 5199515297 ps
CPU time 12.81 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 217752 kb
Host smart-0889932e-b7c7-45d8-8016-9d3a87d20c16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248181246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4
248181246
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2558240265
Short name T518
Test name
Test status
Simulation time 2413682804 ps
CPU time 3.71 seconds
Started Aug 15 06:06:17 PM PDT 24
Finished Aug 15 06:06:21 PM PDT 24
Peak memory 218292 kb
Host smart-078f89a7-e38c-4f80-b6aa-317143130243
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558240265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2558240265
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2002616929
Short name T223
Test name
Test status
Simulation time 898612228 ps
CPU time 27.38 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:40 PM PDT 24
Peak memory 217540 kb
Host smart-09269e84-dc66-46ac-a0b0-bdb9bb5266c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002616929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2002616929
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3902088069
Short name T416
Test name
Test status
Simulation time 1036118685 ps
CPU time 9.38 seconds
Started Aug 15 06:06:17 PM PDT 24
Finished Aug 15 06:06:27 PM PDT 24
Peak memory 217544 kb
Host smart-deb29032-5e85-4f29-8f2d-c385217fcc2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902088069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3902088069
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.418627426
Short name T242
Test name
Test status
Simulation time 5011135715 ps
CPU time 87.84 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:07:50 PM PDT 24
Peak memory 283680 kb
Host smart-3975e994-b055-441e-b1e2-cc05cdde835e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418627426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.418627426
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1845072
Short name T236
Test name
Test status
Simulation time 3681265068 ps
CPU time 16.74 seconds
Started Aug 15 06:06:19 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 247364 kb
Host smart-379a86cd-04ed-401a-970b-c60c03571533
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_post_trans.1845072
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1199108079
Short name T542
Test name
Test status
Simulation time 238181226 ps
CPU time 3.18 seconds
Started Aug 15 06:06:05 PM PDT 24
Finished Aug 15 06:06:09 PM PDT 24
Peak memory 218268 kb
Host smart-25d93ee8-7ea1-4589-a176-532f2913b9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199108079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1199108079
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2901996572
Short name T287
Test name
Test status
Simulation time 164925854 ps
CPU time 10.71 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:24 PM PDT 24
Peak memory 213912 kb
Host smart-7500cca5-1e51-4f85-a5bb-56e99709f8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901996572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2901996572
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1640463277
Short name T510
Test name
Test status
Simulation time 1155453609 ps
CPU time 14.26 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 218904 kb
Host smart-a11ef9b8-f996-44a1-a2d3-51f18d0ad8b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640463277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1640463277
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2526512315
Short name T232
Test name
Test status
Simulation time 932537491 ps
CPU time 8.39 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 226036 kb
Host smart-5eced7e0-7628-45a9-b6cf-1b0fee53653c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526512315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2526512315
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3470898336
Short name T644
Test name
Test status
Simulation time 217614029 ps
CPU time 8.6 seconds
Started Aug 15 06:06:16 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 218232 kb
Host smart-c5b967a5-d767-4992-bcd8-57b6e36b3adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470898336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
470898336
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2512446691
Short name T370
Test name
Test status
Simulation time 698580968 ps
CPU time 10.59 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:20 PM PDT 24
Peak memory 226060 kb
Host smart-7cd2896a-65ce-4536-845e-8f1f58a0cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512446691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2512446691
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.896827538
Short name T421
Test name
Test status
Simulation time 56343197 ps
CPU time 3.67 seconds
Started Aug 15 06:06:09 PM PDT 24
Finished Aug 15 06:06:12 PM PDT 24
Peak memory 215040 kb
Host smart-73a6bae4-7b67-4177-a386-bf8de6b64040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896827538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.896827538
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2019916394
Short name T35
Test name
Test status
Simulation time 429283873 ps
CPU time 29.43 seconds
Started Aug 15 06:06:08 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 250884 kb
Host smart-95843953-85c3-41a7-af11-499bb54abb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019916394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2019916394
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.102196722
Short name T77
Test name
Test status
Simulation time 298938875 ps
CPU time 8.05 seconds
Started Aug 15 06:06:20 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 250908 kb
Host smart-51b519c8-f9ef-44aa-85d8-610cbe321b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102196722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.102196722
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3936475768
Short name T286
Test name
Test status
Simulation time 98048990145 ps
CPU time 836.11 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:20:12 PM PDT 24
Peak memory 259256 kb
Host smart-c317becc-f509-492f-93e9-5702ebb6bd57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936475768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3936475768
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1926797508
Short name T91
Test name
Test status
Simulation time 38161676701 ps
CPU time 77.74 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:07:45 PM PDT 24
Peak memory 274400 kb
Host smart-6d2533cf-d684-4c86-b80c-9f968a8a2289
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1926797508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1926797508
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3446993902
Short name T449
Test name
Test status
Simulation time 12960201 ps
CPU time 1.04 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 211916 kb
Host smart-15295f4d-82c4-4a98-9938-8d6c618e7e1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446993902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3446993902
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1069850341
Short name T377
Test name
Test status
Simulation time 36915709 ps
CPU time 1.17 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:19 PM PDT 24
Peak memory 209084 kb
Host smart-57ca8e5a-ff58-459b-ab43-2e824cc38f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069850341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1069850341
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3873912972
Short name T844
Test name
Test status
Simulation time 529025472 ps
CPU time 12.48 seconds
Started Aug 15 06:06:17 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 218252 kb
Host smart-d3cb0d35-0572-4547-a5e3-3e521cdfc37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873912972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3873912972
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3303607629
Short name T367
Test name
Test status
Simulation time 129339577 ps
CPU time 1.59 seconds
Started Aug 15 06:06:12 PM PDT 24
Finished Aug 15 06:06:14 PM PDT 24
Peak memory 217028 kb
Host smart-ea0eb7f1-9e93-44e4-a01f-7b4c043259f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303607629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3303607629
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1989546611
Short name T723
Test name
Test status
Simulation time 1697290340 ps
CPU time 28.98 seconds
Started Aug 15 06:06:19 PM PDT 24
Finished Aug 15 06:06:48 PM PDT 24
Peak memory 218248 kb
Host smart-5de0a708-5341-4428-8557-a20ae66ae761
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989546611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1989546611
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2271923547
Short name T755
Test name
Test status
Simulation time 1737987566 ps
CPU time 6.45 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:33 PM PDT 24
Peak memory 217660 kb
Host smart-50b8ea4a-e8bc-4ad5-a387-88ad42fda7b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271923547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
271923547
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1337143683
Short name T322
Test name
Test status
Simulation time 2793447107 ps
CPU time 10.21 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:28 PM PDT 24
Peak memory 225572 kb
Host smart-b0092041-4520-4a3b-877a-d700535a3270
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337143683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1337143683
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.879010502
Short name T434
Test name
Test status
Simulation time 5533125780 ps
CPU time 18.6 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:42 PM PDT 24
Peak memory 217600 kb
Host smart-619974ba-7ac5-4a4c-8299-c183085699ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879010502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.879010502
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3080375586
Short name T72
Test name
Test status
Simulation time 1483011998 ps
CPU time 15.58 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:41 PM PDT 24
Peak memory 217552 kb
Host smart-bf5e4183-1a62-4af9-a397-bfab59b47d1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080375586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3080375586
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.278534020
Short name T748
Test name
Test status
Simulation time 1026760304 ps
CPU time 42.82 seconds
Started Aug 15 06:06:21 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 250788 kb
Host smart-559bd7da-7719-4672-a9d8-0f76ad40c268
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278534020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.278534020
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1340600824
Short name T672
Test name
Test status
Simulation time 456306190 ps
CPU time 20.39 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:43 PM PDT 24
Peak memory 250752 kb
Host smart-e7e25b91-6cd9-4acb-82d0-ebc4a9890761
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340600824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1340600824
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2886031151
Short name T815
Test name
Test status
Simulation time 161642501 ps
CPU time 2.46 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:27 PM PDT 24
Peak memory 218276 kb
Host smart-9ffbfe96-b968-47ba-8ffb-a849c199c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886031151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2886031151
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3360317189
Short name T166
Test name
Test status
Simulation time 892655714 ps
CPU time 6.15 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:06:22 PM PDT 24
Peak memory 217652 kb
Host smart-6f385083-6d05-404a-ad40-d0eae658aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360317189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3360317189
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1959118851
Short name T664
Test name
Test status
Simulation time 463161160 ps
CPU time 18.14 seconds
Started Aug 15 06:06:13 PM PDT 24
Finished Aug 15 06:06:33 PM PDT 24
Peak memory 218896 kb
Host smart-ef0b2610-f49a-4a67-b190-6fcd0d5c5f55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959118851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1959118851
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3984722435
Short name T659
Test name
Test status
Simulation time 1418977550 ps
CPU time 9.96 seconds
Started Aug 15 06:06:12 PM PDT 24
Finished Aug 15 06:06:22 PM PDT 24
Peak memory 226008 kb
Host smart-4f9fe4ee-d495-42d4-a756-129f81306034
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984722435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3984722435
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2939026643
Short name T356
Test name
Test status
Simulation time 388899590 ps
CPU time 9.14 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:06:24 PM PDT 24
Peak memory 218220 kb
Host smart-879c2778-13ca-441b-a9b1-9f0ea23ffc17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939026643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
939026643
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.563440780
Short name T1
Test name
Test status
Simulation time 2091538923 ps
CPU time 6.37 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 224872 kb
Host smart-13465348-87f6-41ce-bc0c-4387b816e134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563440780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.563440780
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1040412831
Short name T56
Test name
Test status
Simulation time 58771179 ps
CPU time 3.37 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 217660 kb
Host smart-7ddc2c30-487c-4b14-a64b-d54ef7a21963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040412831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1040412831
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3851693915
Short name T397
Test name
Test status
Simulation time 1395109228 ps
CPU time 32.46 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:56 PM PDT 24
Peak memory 250896 kb
Host smart-a9d2dab4-39cb-42bd-bd5f-82d04f3133c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851693915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3851693915
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.314128591
Short name T702
Test name
Test status
Simulation time 72374754 ps
CPU time 6.19 seconds
Started Aug 15 06:06:18 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 246248 kb
Host smart-679481ef-a226-4a08-aa9e-dabfedf32868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314128591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.314128591
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.80595718
Short name T24
Test name
Test status
Simulation time 4074868663 ps
CPU time 55.97 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:07:22 PM PDT 24
Peak memory 267376 kb
Host smart-98d4bb14-7165-4790-a677-e77d5695f2e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80595718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.lc_ctrl_stress_all.80595718
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1832935577
Short name T274
Test name
Test status
Simulation time 29464472 ps
CPU time 0.91 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 217748 kb
Host smart-353ff9f7-660f-4247-a456-2f28d8bb08fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832935577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1832935577
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.365457159
Short name T306
Test name
Test status
Simulation time 355122505 ps
CPU time 0.89 seconds
Started Aug 15 06:06:40 PM PDT 24
Finished Aug 15 06:06:41 PM PDT 24
Peak memory 208856 kb
Host smart-293e765b-6761-4580-8dcb-cbe375f4c8ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365457159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.365457159
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.762897482
Short name T622
Test name
Test status
Simulation time 10946277 ps
CPU time 0.83 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 208536 kb
Host smart-7e728787-239c-4dc4-b0c5-d2760fc500b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762897482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.762897482
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3326262205
Short name T555
Test name
Test status
Simulation time 1056166334 ps
CPU time 16.62 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:39 PM PDT 24
Peak memory 218232 kb
Host smart-1e5d0d5b-838d-4b4a-8a33-d1ba8eb6ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326262205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3326262205
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.608251924
Short name T534
Test name
Test status
Simulation time 242941896 ps
CPU time 6.19 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 217016 kb
Host smart-fcc5c94b-34d2-4c89-871e-2c952854f402
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608251924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.608251924
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.126000331
Short name T303
Test name
Test status
Simulation time 5452418351 ps
CPU time 23.75 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:46 PM PDT 24
Peak memory 218656 kb
Host smart-a811ed2e-140a-4f61-b09e-a59009747eb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126000331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.126000331
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2967493276
Short name T351
Test name
Test status
Simulation time 597227476 ps
CPU time 5.63 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:33 PM PDT 24
Peak memory 217440 kb
Host smart-aac0b573-d040-47c6-a2de-2914b43cc687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967493276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
967493276
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3463131291
Short name T162
Test name
Test status
Simulation time 1166237126 ps
CPU time 5.85 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:34 PM PDT 24
Peak memory 218252 kb
Host smart-c3a882b5-112e-4e8e-be13-42db5b64ffb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463131291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3463131291
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.902105944
Short name T403
Test name
Test status
Simulation time 10507598260 ps
CPU time 36.61 seconds
Started Aug 15 06:06:42 PM PDT 24
Finished Aug 15 06:07:19 PM PDT 24
Peak memory 217656 kb
Host smart-99a7f810-3747-45cf-a66a-d53cbff22476
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902105944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.902105944
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1285859685
Short name T70
Test name
Test status
Simulation time 1249712097 ps
CPU time 5.18 seconds
Started Aug 15 06:06:14 PM PDT 24
Finished Aug 15 06:06:21 PM PDT 24
Peak memory 217580 kb
Host smart-418ab169-895e-4871-903c-34ca20c910a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285859685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1285859685
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2340506056
Short name T210
Test name
Test status
Simulation time 1236114555 ps
CPU time 51.63 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:07:16 PM PDT 24
Peak memory 251556 kb
Host smart-24cce503-fa9e-49dd-a8b1-b9ea2181fe8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340506056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2340506056
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2231825348
Short name T509
Test name
Test status
Simulation time 1918605854 ps
CPU time 9.72 seconds
Started Aug 15 06:06:21 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 223912 kb
Host smart-a89d679a-c48d-4f60-ac60-e5dac504b1e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231825348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2231825348
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2810422029
Short name T318
Test name
Test status
Simulation time 77574341 ps
CPU time 1.77 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:28 PM PDT 24
Peak memory 218264 kb
Host smart-f08c89c5-8c02-4eee-a899-25a559648edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810422029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2810422029
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2347546168
Short name T400
Test name
Test status
Simulation time 697583402 ps
CPU time 21.04 seconds
Started Aug 15 06:06:16 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 223128 kb
Host smart-c72e3734-ab2b-4cc6-93a6-01882d727e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347546168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2347546168
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1805730190
Short name T222
Test name
Test status
Simulation time 1486626719 ps
CPU time 17.48 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:07:02 PM PDT 24
Peak memory 218944 kb
Host smart-031c631b-d4c3-4425-bcab-7a0a6793fb3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805730190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1805730190
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1879337529
Short name T86
Test name
Test status
Simulation time 1219839975 ps
CPU time 10.85 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:06:41 PM PDT 24
Peak memory 218204 kb
Host smart-90289cdb-8388-4d35-ab67-d3ac9b3191df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879337529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1879337529
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1104609880
Short name T775
Test name
Test status
Simulation time 374861985 ps
CPU time 5.77 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:31 PM PDT 24
Peak memory 218232 kb
Host smart-83254af3-7e32-4417-8963-148728295cb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104609880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
104609880
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3684229559
Short name T807
Test name
Test status
Simulation time 256118155 ps
CPU time 7.91 seconds
Started Aug 15 06:06:12 PM PDT 24
Finished Aug 15 06:06:20 PM PDT 24
Peak memory 218336 kb
Host smart-ea2e3520-1b49-4993-b278-2f856e2ffa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684229559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3684229559
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3930645033
Short name T350
Test name
Test status
Simulation time 65871826 ps
CPU time 1.41 seconds
Started Aug 15 06:06:05 PM PDT 24
Finished Aug 15 06:06:06 PM PDT 24
Peak memory 213932 kb
Host smart-80dc2d9c-ff4c-4f11-9fd3-7624e1b2eff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930645033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3930645033
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2442163178
Short name T609
Test name
Test status
Simulation time 231521152 ps
CPU time 26.21 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:06:57 PM PDT 24
Peak memory 250904 kb
Host smart-3f638982-73f2-4d32-967a-053acfe27941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442163178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2442163178
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2460899747
Short name T632
Test name
Test status
Simulation time 93240998 ps
CPU time 9.14 seconds
Started Aug 15 06:06:17 PM PDT 24
Finished Aug 15 06:06:26 PM PDT 24
Peak memory 250880 kb
Host smart-698c9ad5-b184-4b35-8950-5dd7d54cfd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460899747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2460899747
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3585325012
Short name T402
Test name
Test status
Simulation time 67880509359 ps
CPU time 154.41 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:09:00 PM PDT 24
Peak memory 283688 kb
Host smart-e3b9f346-976f-4a55-a873-fbfe08bfcc60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585325012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3585325012
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1122291229
Short name T452
Test name
Test status
Simulation time 26148567863 ps
CPU time 139.58 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:08:48 PM PDT 24
Peak memory 279736 kb
Host smart-62164415-ce8c-4878-9af6-7ed3c8905fb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1122291229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1122291229
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.828108145
Short name T426
Test name
Test status
Simulation time 24082576 ps
CPU time 0.89 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 211864 kb
Host smart-a9262107-77d1-48e8-9550-ed5ce7d5217c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828108145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.828108145
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3179256580
Short name T547
Test name
Test status
Simulation time 33022090 ps
CPU time 1.1 seconds
Started Aug 15 06:06:44 PM PDT 24
Finished Aug 15 06:06:45 PM PDT 24
Peak memory 209116 kb
Host smart-cccae0d0-8570-432c-8e4d-79d62a549b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179256580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3179256580
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1697601787
Short name T665
Test name
Test status
Simulation time 38275452 ps
CPU time 0.93 seconds
Started Aug 15 06:06:41 PM PDT 24
Finished Aug 15 06:06:42 PM PDT 24
Peak memory 208708 kb
Host smart-3e79ea67-c81f-4de1-bafb-d5be1e70b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697601787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1697601787
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.868488333
Short name T37
Test name
Test status
Simulation time 206692451 ps
CPU time 9.51 seconds
Started Aug 15 06:06:26 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 218288 kb
Host smart-01e05c6b-3f67-4c9f-a561-956f5f953e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868488333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.868488333
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1529963831
Short name T589
Test name
Test status
Simulation time 586881093 ps
CPU time 3.29 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:33 PM PDT 24
Peak memory 217600 kb
Host smart-2a4e307e-62d2-4b79-bbae-4d9bc179b364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529963831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1529963831
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1200720438
Short name T762
Test name
Test status
Simulation time 1947600262 ps
CPU time 28.87 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:06:59 PM PDT 24
Peak memory 218864 kb
Host smart-d9c9e520-c1c3-4001-981b-fa1e77d23818
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200720438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1200720438
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3624200601
Short name T769
Test name
Test status
Simulation time 659465005 ps
CPU time 4.69 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:27 PM PDT 24
Peak memory 217684 kb
Host smart-4d29652c-3128-4f8a-8124-ebda2ad2af0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624200601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
624200601
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3403192319
Short name T839
Test name
Test status
Simulation time 1491943043 ps
CPU time 11.89 seconds
Started Aug 15 06:06:25 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 223424 kb
Host smart-c98e746f-a7c1-4666-989a-3921ea591b1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403192319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3403192319
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.806108531
Short name T376
Test name
Test status
Simulation time 5618500619 ps
CPU time 34.17 seconds
Started Aug 15 06:06:30 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 217624 kb
Host smart-bf144601-66bb-45ee-8531-1e02f067e173
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806108531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.806108531
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3830699303
Short name T69
Test name
Test status
Simulation time 2263239900 ps
CPU time 14.13 seconds
Started Aug 15 06:06:22 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 217604 kb
Host smart-6af894ed-51f9-40db-813f-790885d62fcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830699303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3830699303
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3581152377
Short name T871
Test name
Test status
Simulation time 7578044819 ps
CPU time 33.55 seconds
Started Aug 15 06:06:24 PM PDT 24
Finished Aug 15 06:06:58 PM PDT 24
Peak memory 275676 kb
Host smart-f4ea23ef-8de9-4507-b7ac-72443c7119ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581152377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3581152377
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2519836301
Short name T415
Test name
Test status
Simulation time 295116773 ps
CPU time 11.3 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:39 PM PDT 24
Peak memory 250652 kb
Host smart-76a12782-da9b-4ebb-8e9e-c72e7253dd71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519836301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2519836301
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3305441884
Short name T641
Test name
Test status
Simulation time 363987048 ps
CPU time 3.38 seconds
Started Aug 15 06:06:33 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 222732 kb
Host smart-2ad7932a-e5ba-469b-88e3-ebc7fe7c9f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305441884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3305441884
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.607468681
Short name T334
Test name
Test status
Simulation time 298762855 ps
CPU time 16.18 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:45 PM PDT 24
Peak memory 217624 kb
Host smart-2c304ee7-fd00-42e1-9b41-cdcefd754949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607468681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.607468681
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.720923669
Short name T677
Test name
Test status
Simulation time 333247745 ps
CPU time 15.22 seconds
Started Aug 15 06:06:35 PM PDT 24
Finished Aug 15 06:06:51 PM PDT 24
Peak memory 226084 kb
Host smart-90743d93-c563-48e7-b9b5-d8d0c44c4477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720923669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.720923669
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.587601929
Short name T629
Test name
Test status
Simulation time 590998896 ps
CPU time 9.1 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 226004 kb
Host smart-36c77312-db9a-4095-9cdc-0416dccb14cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587601929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.587601929
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2096793427
Short name T561
Test name
Test status
Simulation time 228891499 ps
CPU time 9.2 seconds
Started Aug 15 06:06:28 PM PDT 24
Finished Aug 15 06:06:38 PM PDT 24
Peak memory 218244 kb
Host smart-8e3f11e1-3273-4efb-9f5b-54c182a75d6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096793427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
096793427
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1707342980
Short name T865
Test name
Test status
Simulation time 3717726749 ps
CPU time 9.01 seconds
Started Aug 15 06:06:27 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 226132 kb
Host smart-e0501bf1-72f3-4b61-8259-8e7774d5b77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707342980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1707342980
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.401230635
Short name T687
Test name
Test status
Simulation time 32851807 ps
CPU time 2.26 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:25 PM PDT 24
Peak memory 214360 kb
Host smart-7eb44090-486d-4ef2-adda-49aa57545eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401230635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.401230635
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2914879601
Short name T391
Test name
Test status
Simulation time 221134772 ps
CPU time 25.59 seconds
Started Aug 15 06:06:23 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 245236 kb
Host smart-1c85a56e-8309-4fae-873a-30fcb16a6c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914879601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2914879601
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1090514840
Short name T873
Test name
Test status
Simulation time 149720141 ps
CPU time 9.53 seconds
Started Aug 15 06:06:45 PM PDT 24
Finished Aug 15 06:06:55 PM PDT 24
Peak memory 247120 kb
Host smart-277d2db1-ce18-40a0-82b6-e05b064313a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090514840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1090514840
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1415188956
Short name T616
Test name
Test status
Simulation time 20341460020 ps
CPU time 82.43 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:07:51 PM PDT 24
Peak memory 250696 kb
Host smart-ff197619-3908-4293-b6df-cf200d55f28a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415188956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1415188956
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.704762703
Short name T875
Test name
Test status
Simulation time 35366469 ps
CPU time 0.88 seconds
Started Aug 15 06:06:29 PM PDT 24
Finished Aug 15 06:06:30 PM PDT 24
Peak memory 211812 kb
Host smart-c07c3fc8-27cc-47d0-84fc-c2e34d4a246d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704762703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.704762703
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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