Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39807 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
48 |
auto[1] |
1251 |
1 |
|
|
T3 |
11 |
|
T14 |
13 |
|
T15 |
15 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40276 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
782 |
1 |
|
|
T18 |
13 |
|
T20 |
13 |
|
T57 |
16 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39703 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1355 |
1 |
|
|
T10 |
9 |
|
T4 |
1 |
|
T16 |
16 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39795 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1263 |
1 |
|
|
T10 |
6 |
|
T16 |
25 |
|
T77 |
10 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39711 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1347 |
1 |
|
|
T10 |
11 |
|
T16 |
25 |
|
T77 |
11 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
38031 |
1 |
|
|
T2 |
85 |
|
T3 |
59 |
|
T10 |
78 |
no_err_inj |
3027 |
1 |
|
|
T1 |
10 |
|
T10 |
6 |
|
T4 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39844 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
52 |
auto[1] |
1214 |
1 |
|
|
T3 |
7 |
|
T14 |
10 |
|
T15 |
15 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40305 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
753 |
1 |
|
|
T18 |
11 |
|
T20 |
20 |
|
T57 |
9 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31791 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
9267 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39796 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1262 |
1 |
|
|
T10 |
6 |
|
T4 |
2 |
|
T16 |
30 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39798 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1260 |
1 |
|
|
T10 |
5 |
|
T16 |
22 |
|
T77 |
12 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39704 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1354 |
1 |
|
|
T10 |
5 |
|
T4 |
1 |
|
T16 |
17 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39830 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
51 |
auto[1] |
1228 |
1 |
|
|
T3 |
8 |
|
T14 |
4 |
|
T15 |
9 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39570 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1488 |
1 |
|
|
T25 |
15 |
|
T54 |
19 |
|
T55 |
4 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40336 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
722 |
1 |
|
|
T18 |
16 |
|
T20 |
14 |
|
T57 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40265 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
793 |
1 |
|
|
T18 |
12 |
|
T20 |
15 |
|
T57 |
21 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40256 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
802 |
1 |
|
|
T18 |
11 |
|
T20 |
21 |
|
T57 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39113 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1945 |
1 |
|
|
T4 |
10 |
|
T16 |
24 |
|
T27 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37390 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
3668 |
1 |
|
|
T46 |
83 |
|
T43 |
71 |
|
T47 |
59 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39746 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1312 |
1 |
|
|
T10 |
14 |
|
T16 |
20 |
|
T77 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39742 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1316 |
1 |
|
|
T10 |
12 |
|
T16 |
21 |
|
T77 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39748 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
1310 |
1 |
|
|
T10 |
10 |
|
T4 |
1 |
|
T16 |
22 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39826 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
56 |
auto[1] |
1232 |
1 |
|
|
T3 |
3 |
|
T14 |
4 |
|
T15 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36122 |
1 |
|
|
T1 |
10 |
|
T3 |
50 |
|
T10 |
84 |
auto[1] |
4936 |
1 |
|
|
T2 |
85 |
|
T3 |
9 |
|
T14 |
10 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37338 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[1] |
3720 |
1 |
|
|
T17 |
85 |
|
T22 |
74 |
|
T56 |
64 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41058 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39863 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
51 |
auto[1] |
1195 |
1 |
|
|
T3 |
8 |
|
T14 |
7 |
|
T15 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39850 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
50 |
auto[1] |
1208 |
1 |
|
|
T3 |
9 |
|
T14 |
9 |
|
T15 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39798 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
55 |
auto[1] |
1260 |
1 |
|
|
T3 |
4 |
|
T14 |
6 |
|
T15 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
37025 |
1 |
|
|
T2 |
85 |
|
T3 |
59 |
|
T10 |
78 |
auto[0] |
no_err_inj |
2088 |
1 |
|
|
T1 |
10 |
|
T10 |
6 |
|
T5 |
5 |
auto[1] |
err_inj |
1006 |
1 |
|
|
T4 |
5 |
|
T16 |
15 |
|
T27 |
8 |
auto[1] |
no_err_inj |
939 |
1 |
|
|
T4 |
5 |
|
T16 |
9 |
|
T27 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37911 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
1202 |
1 |
|
|
T10 |
12 |
|
T16 |
19 |
|
T77 |
6 |
auto[1] |
auto[0] |
1831 |
1 |
|
|
T4 |
10 |
|
T16 |
22 |
|
T27 |
14 |
auto[1] |
auto[1] |
114 |
1 |
|
|
T16 |
2 |
|
T75 |
1 |
|
T81 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37967 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
1146 |
1 |
|
|
T10 |
5 |
|
T16 |
22 |
|
T77 |
12 |
auto[1] |
auto[0] |
1831 |
1 |
|
|
T4 |
10 |
|
T16 |
24 |
|
T27 |
13 |
auto[1] |
auto[1] |
114 |
1 |
|
|
T27 |
1 |
|
T200 |
4 |
|
T81 |
5 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37909 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
1204 |
1 |
|
|
T10 |
10 |
|
T16 |
22 |
|
T77 |
6 |
auto[1] |
auto[0] |
1839 |
1 |
|
|
T4 |
9 |
|
T16 |
24 |
|
T27 |
14 |
auto[1] |
auto[1] |
106 |
1 |
|
|
T4 |
1 |
|
T200 |
1 |
|
T81 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37945 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
1168 |
1 |
|
|
T10 |
6 |
|
T16 |
25 |
|
T77 |
10 |
auto[1] |
auto[0] |
1850 |
1 |
|
|
T4 |
10 |
|
T16 |
24 |
|
T27 |
13 |
auto[1] |
auto[1] |
95 |
1 |
|
|
T27 |
1 |
|
T81 |
2 |
|
T88 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37883 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
1230 |
1 |
|
|
T10 |
11 |
|
T16 |
24 |
|
T77 |
11 |
auto[1] |
auto[0] |
1828 |
1 |
|
|
T4 |
10 |
|
T16 |
23 |
|
T27 |
12 |
auto[1] |
auto[1] |
117 |
1 |
|
|
T16 |
1 |
|
T27 |
2 |
|
T81 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37871 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T10 |
9 |
|
T16 |
14 |
|
T77 |
4 |
auto[1] |
auto[0] |
1832 |
1 |
|
|
T4 |
9 |
|
T16 |
22 |
|
T27 |
13 |
auto[1] |
auto[1] |
113 |
1 |
|
|
T4 |
1 |
|
T16 |
2 |
|
T27 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31004 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
48 |
auto[0] |
auto[1] |
787 |
1 |
|
|
T3 |
11 |
|
T14 |
13 |
|
T15 |
15 |
auto[1] |
auto[0] |
8803 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
464 |
1 |
|
|
T36 |
11 |
|
T42 |
22 |
|
T201 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31021 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
52 |
auto[0] |
auto[1] |
770 |
1 |
|
|
T3 |
7 |
|
T14 |
10 |
|
T15 |
15 |
auto[1] |
auto[0] |
8823 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
444 |
1 |
|
|
T81 |
1 |
|
T36 |
11 |
|
T42 |
27 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30810 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
981 |
1 |
|
|
T54 |
19 |
|
T142 |
14 |
|
T202 |
11 |
auto[1] |
auto[0] |
8760 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
507 |
1 |
|
|
T25 |
15 |
|
T55 |
4 |
|
T75 |
7 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31013 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
51 |
auto[0] |
auto[1] |
778 |
1 |
|
|
T3 |
8 |
|
T14 |
4 |
|
T15 |
9 |
auto[1] |
auto[0] |
8817 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
450 |
1 |
|
|
T81 |
1 |
|
T36 |
14 |
|
T42 |
20 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
27336 |
1 |
|
|
T1 |
10 |
|
T3 |
50 |
|
T10 |
84 |
auto[0] |
auto[1] |
4455 |
1 |
|
|
T2 |
85 |
|
T3 |
9 |
|
T14 |
10 |
auto[1] |
auto[0] |
8786 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
481 |
1 |
|
|
T36 |
10 |
|
T42 |
19 |
|
T201 |
19 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30926 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
865 |
1 |
|
|
T10 |
12 |
|
T16 |
2 |
|
T77 |
6 |
auto[1] |
auto[0] |
8816 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
451 |
1 |
|
|
T16 |
19 |
|
T75 |
1 |
|
T81 |
4 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30889 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
902 |
1 |
|
|
T10 |
14 |
|
T16 |
1 |
|
T77 |
8 |
auto[1] |
auto[0] |
8857 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
410 |
1 |
|
|
T16 |
19 |
|
T27 |
2 |
|
T81 |
4 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30943 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
848 |
1 |
|
|
T10 |
5 |
|
T77 |
12 |
|
T78 |
15 |
auto[1] |
auto[0] |
8855 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
412 |
1 |
|
|
T16 |
22 |
|
T27 |
1 |
|
T81 |
5 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30967 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
824 |
1 |
|
|
T10 |
6 |
|
T16 |
5 |
|
T77 |
9 |
auto[1] |
auto[0] |
8829 |
1 |
|
|
T4 |
8 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
438 |
1 |
|
|
T4 |
2 |
|
T16 |
25 |
|
T81 |
2 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30942 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
849 |
1 |
|
|
T10 |
6 |
|
T77 |
10 |
|
T78 |
8 |
auto[1] |
auto[0] |
8853 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
414 |
1 |
|
|
T16 |
25 |
|
T27 |
1 |
|
T81 |
3 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30903 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
888 |
1 |
|
|
T10 |
9 |
|
T16 |
2 |
|
T77 |
4 |
auto[1] |
auto[0] |
8800 |
1 |
|
|
T4 |
9 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
467 |
1 |
|
|
T4 |
1 |
|
T16 |
14 |
|
T27 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31027 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
55 |
auto[0] |
auto[1] |
764 |
1 |
|
|
T3 |
4 |
|
T14 |
6 |
|
T15 |
9 |
auto[1] |
auto[0] |
8771 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
496 |
1 |
|
|
T81 |
1 |
|
T36 |
9 |
|
T42 |
24 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31004 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
50 |
auto[0] |
auto[1] |
787 |
1 |
|
|
T3 |
9 |
|
T14 |
9 |
|
T15 |
9 |
auto[1] |
auto[0] |
8846 |
1 |
|
|
T4 |
10 |
|
T5 |
5 |
|
T24 |
8 |
auto[1] |
auto[1] |
421 |
1 |
|
|
T81 |
1 |
|
T36 |
3 |
|
T42 |
20 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30498 |
1 |
|
|
T1 |
10 |
|
T2 |
85 |
|
T3 |
59 |
auto[0] |
auto[1] |
1293 |
1 |
|
|
T16 |
24 |
|
T200 |
14 |
|
T81 |
15 |
auto[1] |
auto[0] |
8615 |
1 |
|
|
T5 |
5 |
|
T24 |
8 |
|
T16 |
192 |
auto[1] |
auto[1] |
652 |
1 |
|
|
T4 |
10 |
|
T27 |
14 |
|
T75 |
7 |