Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58112827

1

T1

31010

T2

36274

T3

24789

auto[1]

1126936

1

T3

594

T10

3762

T18

1584

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58120491

1

T1

31010

T2

36274

T3

24888

auto[1]

1119272

1

T3

495

T10

2475

T4

294

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5344937	1			T1	939		T2	7628		T3	5473
auto[IdleSt]	15489016	1			T1	797		T2	10349		T3	7298
auto[ClkMuxSt]	28131	1			T1	8		T2	85		T3	59
auto[CntIncrSt]	27952	1			T1	8		T2	85		T3	59
auto[CntProgSt]	1460512	1			T1	16		T2	762		T3	89
auto[TransCheckSt]	22107	1			T1	8		T2	85		T3	39
auto[TokenHashSt]	16392126	1			T1	28468		T2	926		T3	706
auto[FlashRmaSt]	28029	1			T1	34		T3	60		T10	6
auto[TokenCheck0St]	9777	1			T1	8		T3	15		T10	6
auto[TokenCheck1St]	7001	1			T1	8		T3	8		T10	6
auto[TransProgSt]	341240	1			T1	16		T3	16		T10	96
auto[PostTransSt]	8550816	1			T1	648		T2	16354		T3	9996
auto[ScrapSt]	115629	1			T1	52		T13	15		T35	563
auto[EscalateSt]	4509649	1			T3	1565		T10	8060		T4	6803
auto[InvalidSt]	6911508	1			T10	4695		T4	6212		T18	915

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1333	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6911508	1			T10	4695		T4	6212		T18	915
EscalateSt	4509649	1			T3	1565		T10	8060		T4	6803
ScrapSt	115629	1			T1	52		T13	15		T35	563
PostTransSt	8550816	1			T1	648		T2	16354		T3	9996
TransProgSt	341240	1			T1	16		T3	16		T10	96
TokenCheck1St	7001	1			T1	8		T3	8		T10	6
TokenCheck0St	9777	1			T1	8		T3	15		T10	6
FlashRmaSt	28029	1			T1	34		T3	60		T10	6
TokenHashSt	16392126	1			T1	28468		T2	926		T3	706
TransCheckSt	22107	1			T1	8		T2	85		T3	39
CntProgSt	1460512	1			T1	16		T2	762		T3	89
CntIncrSt	27952	1			T1	8		T2	85		T3	59
ClkMuxSt	28131	1			T1	8		T2	85		T3	59
IdleSt	15489016	1			T1	797		T2	10349		T3	7298
ResetSt	5344937	1			T1	939		T2	7628		T3	5473
arcs[ResetSt=>IdleSt]	41619	1			T1	10		T2	86		T3	60
arcs[IdleSt=>ScrapSt]	227	1			T1	2		T13	1		T35	4
arcs[IdleSt=>ClkMuxSt]	27989	1			T1	8		T2	85		T3	59
arcs[ClkMuxSt=>CntIncrSt]	27952	1			T1	8		T2	85		T3	59
arcs[CntIncrSt=>PostTransSt]	1212	1			T3	9		T14	9		T15	9
arcs[CntIncrSt=>CntProgSt]	26680	1			T1	8		T2	85		T3	50
arcs[CntProgSt=>PostTransSt]	3525	1			T3	11		T18	13		T14	13
arcs[CntProgSt=>TransCheckSt]	22107	1			T1	8		T2	85		T3	39
arcs[TransCheckSt=>PostTransSt]	3122	1			T3	4		T17	42		T14	6
arcs[TransCheckSt=>TokenHashSt]	18892	1			T1	8		T2	85		T3	35
arcs[TokenHashSt=>PostTransSt]	8289	1			T2	85		T3	20		T19	1
arcs[TokenHashSt=>FlashRmaSt]	9816	1			T1	8		T3	15		T10	6
arcs[FlashRmaSt=>TokenCheck0St]	9777	1			T1	8		T3	15		T10	6
arcs[TokenCheck0St=>PostTransSt]	2716	1			T3	7		T17	19		T18	11
arcs[TokenCheck0St=>TokenCheck1St]	7001	1			T1	8		T3	8		T10	6
arcs[TokenCheck1St=>PostTransSt]	639	1			T17	15		T14	3		T20	2
arcs[TransProgSt=>PostTransSt]	5596	1			T1	8		T3	8		T10	6
arcs[IdleSt=>EscalateSt]	166	1			T43	6		T47	7		T44	6
arcs[ClkMuxSt=>EscalateSt]	37	1			T43	2		T44	2		T45	1
arcs[CntIncrSt=>EscalateSt]	60	1			T46	2		T43	1		T47	1
arcs[CntProgSt=>EscalateSt]	1048	1			T46	11		T43	6		T47	9
arcs[TransCheckSt=>EscalateSt]	93	1			T46	5		T43	2		T47	2
arcs[TokenHashSt=>EscalateSt]	787	1			T46	36		T43	29		T47	12
arcs[FlashRmaSt=>EscalateSt]	39	1			T43	1		T47	1		T45	1
arcs[TokenCheck0St=>EscalateSt]	60	1			T47	1		T44	2		T45	1
arcs[TokenCheck1St=>EscalateSt]	35	1			T46	2		T43	2		T49	1
arcs[TransProgSt=>EscalateSt]	731	1			T46	8		T43	3		T47	10
arcs[PostTransSt=>EscalateSt]	3805	1			T3	11		T18	13		T14	13
arcs[InvalidSt=>EscalateSt]	9928	1			T10	63		T4	3		T18	12

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5344743	1			T1	939		T2	7628		T3	5473
auto[0]	auto[IdleSt]	15488912	1			T1	797		T2	10349		T3	7298
auto[0]	auto[ClkMuxSt]	28109	1			T1	8		T2	85		T3	59
auto[0]	auto[CntIncrSt]	27916	1			T1	8		T2	85		T3	59
auto[0]	auto[CntProgSt]	1459821	1			T1	16		T2	762		T3	89
auto[0]	auto[TransCheckSt]	22050	1			T1	8		T2	85		T3	39
auto[0]	auto[TokenHashSt]	16391589	1			T1	28468		T2	926		T3	706
auto[0]	auto[FlashRmaSt]	28006	1			T1	34		T3	60		T10	6
auto[0]	auto[TokenCheck0St]	9738	1			T1	8		T3	15		T10	6
auto[0]	auto[TokenCheck1St]	6975	1			T1	8		T3	8		T10	6
auto[0]	auto[TransProgSt]	340756	1			T1	16		T3	16		T10	96
auto[0]	auto[PostTransSt]	8548884	1			T1	648		T2	16354		T3	9990
auto[0]	auto[ScrapSt]	115587	1			T1	52		T13	15		T35	563
auto[0]	auto[EscalateSt]	3391907	1			T3	977		T10	4336		T4	6803
auto[0]	auto[InvalidSt]	6906501	1			T10	4657		T4	6212		T18	907
auto[1]	auto[ResetSt]	194	1			T46	4		T43	2		T47	1
auto[1]	auto[IdleSt]	104	1			T43	3		T47	3		T44	4
auto[1]	auto[ClkMuxSt]	22	1			T45	1		T197	1		T198	1
auto[1]	auto[CntIncrSt]	36	1			T46	1		T43	1		T47	1
auto[1]	auto[CntProgSt]	691	1			T46	6		T43	2		T47	4
auto[1]	auto[TransCheckSt]	57	1			T46	2		T43	2		T49	2
auto[1]	auto[TokenHashSt]	537	1			T46	25		T43	22		T47	8
auto[1]	auto[FlashRmaSt]	23	1			T47	1		T45	1		T198	1
auto[1]	auto[TokenCheck0St]	39	1			T45	1		T198	2		T49	2
auto[1]	auto[TokenCheck1St]	26	1			T46	2		T43	1		T199	2
auto[1]	auto[TransProgSt]	484	1			T46	6		T43	1		T47	7
auto[1]	auto[PostTransSt]	1932	1			T3	6		T18	8		T14	7
auto[1]	auto[ScrapSt]	42	1			T44	1		T45	1		T198	1
auto[1]	auto[EscalateSt]	1117742	1			T3	588		T10	3724		T18	1568
auto[1]	auto[InvalidSt]	5007	1			T10	38		T18	8		T20	9

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5344749	1			T1	939		T2	7628		T3	5473
auto[0]	auto[IdleSt]	15488908	1			T1	797		T2	10349		T3	7298
auto[0]	auto[ClkMuxSt]	28108	1			T1	8		T2	85		T3	59
auto[0]	auto[CntIncrSt]	27906	1			T1	8		T2	85		T3	59
auto[0]	auto[CntProgSt]	1459826	1			T1	16		T2	762		T3	89
auto[0]	auto[TransCheckSt]	22047	1			T1	8		T2	85		T3	39
auto[0]	auto[TokenHashSt]	16391616	1			T1	28468		T2	926		T3	706
auto[0]	auto[FlashRmaSt]	28004	1			T1	34		T3	60		T10	6
auto[0]	auto[TokenCheck0St]	9732	1			T1	8		T3	15		T10	6
auto[0]	auto[TokenCheck1St]	6983	1			T1	8		T3	8		T10	6
auto[0]	auto[TransProgSt]	340743	1			T1	16		T3	16		T10	96
auto[0]	auto[PostTransSt]	8548855	1			T1	648		T2	16354		T3	9991
auto[0]	auto[ScrapSt]	115593	1			T1	52		T13	15		T35	563
auto[0]	auto[EscalateSt]	3399501	1			T3	1075		T10	5610		T4	6512
auto[0]	auto[InvalidSt]	6906587	1			T10	4670		T4	6209		T18	911
auto[1]	auto[ResetSt]	188	1			T46	6		T47	2		T44	6
auto[1]	auto[IdleSt]	108	1			T43	4		T47	5		T44	4
auto[1]	auto[ClkMuxSt]	23	1			T43	2		T44	2		T197	1
auto[1]	auto[CntIncrSt]	46	1			T46	1		T43	1		T47	1
auto[1]	auto[CntProgSt]	686	1			T46	10		T43	5		T47	6
auto[1]	auto[TransCheckSt]	60	1			T46	4		T43	1		T47	2
auto[1]	auto[TokenHashSt]	510	1			T46	22		T43	22		T47	8
auto[1]	auto[FlashRmaSt]	25	1			T43	1		T47	1		T45	1
auto[1]	auto[TokenCheck0St]	45	1			T47	1		T44	2		T45	1
auto[1]	auto[TokenCheck1St]	18	1			T43	2		T49	1		T50	1
auto[1]	auto[TransProgSt]	497	1			T46	7		T43	2		T47	6
auto[1]	auto[PostTransSt]	1961	1			T3	5		T18	5		T14	6
auto[1]	auto[ScrapSt]	36	1			T43	1		T47	1		T45	1
auto[1]	auto[EscalateSt]	1110148	1			T3	490		T10	2450		T4	291
auto[1]	auto[InvalidSt]	4921	1			T10	25		T4	3		T18	4