Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58579286

1

T1

10283

T2

25521

T3

7176

auto[1]

1071387

1

T3

594

T14

2871

T4

196

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58551248

1

T1

10283

T2

25521

T3

7572

auto[1]

1099425

1

T3

198

T14

3069

T4

294

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5043732	1			T1	5550		T2	6746		T3	1093
auto[IdleSt]	17016573	1			T1	2101		T2	6241		T3	1159
auto[ClkMuxSt]	28750	1			T2	74		T3	1		T11	7
auto[CntIncrSt]	28598	1			T2	74		T3	1		T11	7
auto[CntProgSt]	1424671	1			T2	285		T3	745		T11	1641
auto[TransCheckSt]	22473	1			T2	74		T3	1		T11	7
auto[TokenHashSt]	15032566	1			T2	390		T3	257		T11	149
auto[FlashRmaSt]	27248	1			T2	28		T3	1		T11	7
auto[TokenCheck0St]	9846	1			T2	28		T3	1		T11	7
auto[TokenCheck1St]	7061	1			T2	11		T3	1		T11	7
auto[TransProgSt]	361770	1			T3	474		T11	1069		T12	6
auto[PostTransSt]	9709263	1			T2	11570		T3	321		T11	671
auto[ScrapSt]	301768	1			T1	5		T12	44		T24	8
auto[EscalateSt]	4407443	1			T3	2221		T14	8523		T4	7070
auto[InvalidSt]	6227609	1			T1	2617		T3	1494		T14	10719

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1302	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6227609	1			T1	2617		T3	1494		T14	10719
EscalateSt	4407443	1			T3	2221		T14	8523		T4	7070
ScrapSt	301768	1			T1	5		T12	44		T24	8
PostTransSt	9709263	1			T2	11570		T3	321		T11	671
TransProgSt	361770	1			T3	474		T11	1069		T12	6
TokenCheck1St	7061	1			T2	11		T3	1		T11	7
TokenCheck0St	9846	1			T2	28		T3	1		T11	7
FlashRmaSt	27248	1			T2	28		T3	1		T11	7
TokenHashSt	15032566	1			T2	390		T3	257		T11	149
TransCheckSt	22473	1			T2	74		T3	1		T11	7
CntProgSt	1424671	1			T2	285		T3	745		T11	1641
CntIncrSt	28598	1			T2	74		T3	1		T11	7
ClkMuxSt	28750	1			T2	74		T3	1		T11	7
IdleSt	17016573	1			T1	2101		T2	6241		T3	1159
ResetSt	5043732	1			T1	5550		T2	6746		T3	1093
arcs[ResetSt=>IdleSt]	41545	1			T1	61		T2	75		T3	11
arcs[IdleSt=>ScrapSt]	202	1			T1	3		T12	1		T24	2
arcs[IdleSt=>ClkMuxSt]	28631	1			T2	74		T3	1		T11	7
arcs[ClkMuxSt=>CntIncrSt]	28598	1			T2	74		T3	1		T11	7
arcs[CntIncrSt=>PostTransSt]	1362	1			T17	9		T6	11		T18	6
arcs[CntIncrSt=>CntProgSt]	27176	1			T2	74		T3	1		T11	7
arcs[CntProgSt=>PostTransSt]	3821	1			T23	10		T19	19		T17	13
arcs[CntProgSt=>TransCheckSt]	22473	1			T2	74		T3	1		T11	7
arcs[TransCheckSt=>PostTransSt]	3229	1			T2	39		T15	33		T17	12
arcs[TransCheckSt=>TokenHashSt]	19132	1			T2	35		T3	1		T11	7
arcs[TokenHashSt=>PostTransSt]	8397	1			T2	7		T15	6		T21	82
arcs[TokenHashSt=>FlashRmaSt]	9875	1			T2	28		T3	1		T11	7
arcs[FlashRmaSt=>TokenCheck0St]	9846	1			T2	28		T3	1		T11	7
arcs[TokenCheck0St=>PostTransSt]	2738	1			T2	17		T15	16		T23	7
arcs[TokenCheck0St=>TokenCheck1St]	7061	1			T2	11		T3	1		T11	7
arcs[TokenCheck1St=>PostTransSt]	619	1			T2	11		T15	6		T23	1
arcs[TransProgSt=>PostTransSt]	5704	1			T3	1		T11	7		T12	3
arcs[IdleSt=>EscalateSt]	151	1			T24	5		T44	3		T49	6
arcs[ClkMuxSt=>EscalateSt]	33	1			T24	1		T49	2		T50	1
arcs[CntIncrSt=>EscalateSt]	60	1			T51	3		T44	1		T52	2
arcs[CntProgSt=>EscalateSt]	882	1			T24	22		T51	25		T44	10
arcs[TransCheckSt=>EscalateSt]	112	1			T24	1		T44	7		T57	1
arcs[TokenHashSt=>EscalateSt]	860	1			T24	12		T51	3		T44	18
arcs[FlashRmaSt=>EscalateSt]	29	1			T24	1		T52	1		T53	1
arcs[TokenCheck0St=>EscalateSt]	47	1			T24	1		T51	1		T49	2
arcs[TokenCheck1St=>EscalateSt]	27	1			T44	1		T49	1		T50	1
arcs[TransProgSt=>EscalateSt]	711	1			T24	18		T51	12		T44	6
arcs[PostTransSt=>EscalateSt]	4195	1			T24	2		T23	10		T19	19
arcs[InvalidSt=>EscalateSt]	9339	1			T3	8		T14	60		T4	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5043561	1			T1	5550		T2	6746		T3	1093
auto[0]	auto[IdleSt]	17016479	1			T1	2101		T2	6241		T3	1159
auto[0]	auto[ClkMuxSt]	28729	1			T2	74		T3	1		T11	7
auto[0]	auto[CntIncrSt]	28556	1			T2	74		T3	1		T11	7
auto[0]	auto[CntProgSt]	1424106	1			T2	285		T3	745		T11	1641
auto[0]	auto[TransCheckSt]	22394	1			T2	74		T3	1		T11	7
auto[0]	auto[TokenHashSt]	15031982	1			T2	390		T3	257		T11	149
auto[0]	auto[FlashRmaSt]	27230	1			T2	28		T3	1		T11	7
auto[0]	auto[TokenCheck0St]	9815	1			T2	28		T3	1		T11	7
auto[0]	auto[TokenCheck1St]	7043	1			T2	11		T3	1		T11	7
auto[0]	auto[TransProgSt]	361308	1			T3	474		T11	1069		T12	6
auto[0]	auto[PostTransSt]	9707135	1			T2	11570		T3	321		T11	671
auto[0]	auto[ScrapSt]	301733	1			T1	5		T12	44		T24	7
auto[0]	auto[EscalateSt]	3344863	1			T3	1633		T14	5681		T4	6876
auto[0]	auto[InvalidSt]	6223050	1			T1	2617		T3	1488		T14	10690
auto[1]	auto[ResetSt]	171	1			T24	4		T51	4		T44	7
auto[1]	auto[IdleSt]	94	1			T24	3		T44	2		T49	5
auto[1]	auto[ClkMuxSt]	21	1			T50	1		T151	1		T193	1
auto[1]	auto[CntIncrSt]	42	1			T51	1		T44	1		T52	1
auto[1]	auto[CntProgSt]	565	1			T24	14		T51	17		T44	6
auto[1]	auto[TransCheckSt]	79	1			T24	1		T44	4		T194	4
auto[1]	auto[TokenHashSt]	584	1			T24	8		T51	2		T44	9
auto[1]	auto[FlashRmaSt]	18	1			T52	1		T195	1		T196	1
auto[1]	auto[TokenCheck0St]	31	1			T24	1		T49	1		T57	1
auto[1]	auto[TokenCheck1St]	18	1			T50	1		T197	1		T53	1
auto[1]	auto[TransProgSt]	462	1			T24	10		T51	4		T44	5
auto[1]	auto[PostTransSt]	2128	1			T24	1		T23	6		T19	8
auto[1]	auto[ScrapSt]	35	1			T24	1		T51	1		T49	2
auto[1]	auto[EscalateSt]	1062580	1			T3	588		T14	2842		T4	194
auto[1]	auto[InvalidSt]	4559	1			T3	6		T14	29		T4	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5043563	1			T1	5550		T2	6746		T3	1093
auto[0]	auto[IdleSt]	17016471	1			T1	2101		T2	6241		T3	1159
auto[0]	auto[ClkMuxSt]	28727	1			T2	74		T3	1		T11	7
auto[0]	auto[CntIncrSt]	28557	1			T2	74		T3	1		T11	7
auto[0]	auto[CntProgSt]	1424079	1			T2	285		T3	745		T11	1641
auto[0]	auto[TransCheckSt]	22398	1			T2	74		T3	1		T11	7
auto[0]	auto[TokenHashSt]	15032016	1			T2	390		T3	257		T11	149
auto[0]	auto[FlashRmaSt]	27225	1			T2	28		T3	1		T11	7
auto[0]	auto[TokenCheck0St]	9813	1			T2	28		T3	1		T11	7
auto[0]	auto[TokenCheck1St]	7044	1			T2	11		T3	1		T11	7
auto[0]	auto[TransProgSt]	361296	1			T3	474		T11	1069		T12	6
auto[0]	auto[PostTransSt]	9707093	1			T2	11570		T3	321		T11	671
auto[0]	auto[ScrapSt]	301728	1			T1	5		T12	44		T24	7
auto[0]	auto[EscalateSt]	3317107	1			T3	2025		T14	5485		T4	6779
auto[0]	auto[InvalidSt]	6222829	1			T1	2617		T3	1492		T14	10688
auto[1]	auto[ResetSt]	169	1			T24	6		T51	7		T44	6
auto[1]	auto[IdleSt]	102	1			T24	3		T44	2		T49	3
auto[1]	auto[ClkMuxSt]	23	1			T24	1		T49	2		T50	1
auto[1]	auto[CntIncrSt]	41	1			T51	3		T44	1		T52	1
auto[1]	auto[CntProgSt]	592	1			T24	14		T51	21		T44	7
auto[1]	auto[TransCheckSt]	75	1			T24	1		T44	3		T57	1
auto[1]	auto[TokenHashSt]	550	1			T24	7		T51	2		T44	12
auto[1]	auto[FlashRmaSt]	23	1			T24	1		T52	1		T53	1
auto[1]	auto[TokenCheck0St]	33	1			T24	1		T51	1		T49	1
auto[1]	auto[TokenCheck1St]	17	1			T44	1		T49	1		T53	1
auto[1]	auto[TransProgSt]	474	1			T24	16		T51	11		T44	2
auto[1]	auto[PostTransSt]	2170	1			T24	1		T23	4		T19	11
auto[1]	auto[ScrapSt]	40	1			T24	1		T51	1		T44	1
auto[1]	auto[EscalateSt]	1090336	1			T3	196		T14	3038		T4	291
auto[1]	auto[InvalidSt]	4780	1			T3	2		T14	31		T4	3