Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41275 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1200 |
1 |
|
|
T4 |
9 |
|
T15 |
10 |
|
T16 |
3 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41692 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
783 |
1 |
|
|
T63 |
19 |
|
T64 |
19 |
|
T65 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41114 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1361 |
1 |
|
|
T10 |
14 |
|
T13 |
1 |
|
T51 |
2 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41189 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1286 |
1 |
|
|
T10 |
14 |
|
T13 |
2 |
|
T51 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41132 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1343 |
1 |
|
|
T10 |
3 |
|
T40 |
10 |
|
T16 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
39013 |
1 |
|
|
T1 |
17 |
|
T2 |
98 |
|
T3 |
10 |
no_err_inj |
3462 |
1 |
|
|
T1 |
9 |
|
T12 |
18 |
|
T13 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41295 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1180 |
1 |
|
|
T4 |
6 |
|
T15 |
9 |
|
T16 |
15 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41703 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
772 |
1 |
|
|
T63 |
25 |
|
T64 |
8 |
|
T65 |
25 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31523 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[1] |
10952 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41143 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1332 |
1 |
|
|
T10 |
6 |
|
T13 |
1 |
|
T51 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41189 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1286 |
1 |
|
|
T10 |
11 |
|
T13 |
1 |
|
T51 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41125 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1350 |
1 |
|
|
T10 |
7 |
|
T40 |
5 |
|
T41 |
7 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41190 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1285 |
1 |
|
|
T4 |
6 |
|
T15 |
10 |
|
T16 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40549 |
1 |
|
|
T1 |
9 |
|
T2 |
98 |
|
T10 |
82 |
auto[1] |
1926 |
1 |
|
|
T1 |
17 |
|
T3 |
10 |
|
T16 |
15 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41695 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
780 |
1 |
|
|
T63 |
20 |
|
T64 |
17 |
|
T65 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41771 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
704 |
1 |
|
|
T63 |
16 |
|
T64 |
11 |
|
T65 |
11 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41700 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
775 |
1 |
|
|
T63 |
17 |
|
T64 |
17 |
|
T65 |
20 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40436 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
2039 |
1 |
|
|
T13 |
13 |
|
T51 |
15 |
|
T16 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38427 |
1 |
|
|
T1 |
26 |
|
T3 |
10 |
|
T10 |
82 |
auto[1] |
4048 |
1 |
|
|
T2 |
98 |
|
T52 |
92 |
|
T38 |
90 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41099 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1376 |
1 |
|
|
T10 |
12 |
|
T40 |
6 |
|
T16 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41135 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1340 |
1 |
|
|
T10 |
8 |
|
T40 |
8 |
|
T16 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41140 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1335 |
1 |
|
|
T10 |
7 |
|
T13 |
2 |
|
T40 |
6 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41281 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1194 |
1 |
|
|
T4 |
9 |
|
T15 |
14 |
|
T16 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37541 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
4934 |
1 |
|
|
T4 |
8 |
|
T15 |
13 |
|
T78 |
60 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38713 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
3762 |
1 |
|
|
T20 |
59 |
|
T19 |
87 |
|
T62 |
79 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42475 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41282 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1193 |
1 |
|
|
T4 |
7 |
|
T15 |
17 |
|
T16 |
14 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41204 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1271 |
1 |
|
|
T4 |
11 |
|
T15 |
11 |
|
T16 |
6 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41278 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[1] |
1197 |
1 |
|
|
T4 |
4 |
|
T15 |
11 |
|
T16 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
38020 |
1 |
|
|
T1 |
17 |
|
T2 |
98 |
|
T3 |
10 |
auto[0] |
no_err_inj |
2416 |
1 |
|
|
T1 |
9 |
|
T12 |
18 |
|
T16 |
9 |
auto[1] |
err_inj |
993 |
1 |
|
|
T13 |
7 |
|
T51 |
6 |
|
T16 |
7 |
auto[1] |
no_err_inj |
1046 |
1 |
|
|
T13 |
6 |
|
T51 |
9 |
|
T16 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39204 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[0] |
auto[1] |
1232 |
1 |
|
|
T10 |
8 |
|
T40 |
8 |
|
T41 |
10 |
auto[1] |
auto[0] |
1931 |
1 |
|
|
T13 |
13 |
|
T51 |
15 |
|
T16 |
11 |
auto[1] |
auto[1] |
108 |
1 |
|
|
T16 |
1 |
|
T75 |
1 |
|
T76 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39266 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[0] |
auto[1] |
1170 |
1 |
|
|
T10 |
11 |
|
T40 |
6 |
|
T41 |
7 |
auto[1] |
auto[0] |
1923 |
1 |
|
|
T13 |
12 |
|
T51 |
13 |
|
T16 |
12 |
auto[1] |
auto[1] |
116 |
1 |
|
|
T13 |
1 |
|
T51 |
2 |
|
T75 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39215 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[0] |
auto[1] |
1221 |
1 |
|
|
T10 |
7 |
|
T40 |
6 |
|
T41 |
7 |
auto[1] |
auto[0] |
1925 |
1 |
|
|
T13 |
11 |
|
T51 |
15 |
|
T16 |
12 |
auto[1] |
auto[1] |
114 |
1 |
|
|
T13 |
2 |
|
T75 |
3 |
|
T76 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39271 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[0] |
auto[1] |
1165 |
1 |
|
|
T10 |
14 |
|
T40 |
16 |
|
T41 |
3 |
auto[1] |
auto[0] |
1918 |
1 |
|
|
T13 |
11 |
|
T51 |
14 |
|
T16 |
12 |
auto[1] |
auto[1] |
121 |
1 |
|
|
T13 |
2 |
|
T51 |
1 |
|
T75 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39194 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T10 |
3 |
|
T40 |
10 |
|
T41 |
7 |
auto[1] |
auto[0] |
1938 |
1 |
|
|
T13 |
13 |
|
T51 |
15 |
|
T16 |
11 |
auto[1] |
auto[1] |
101 |
1 |
|
|
T16 |
1 |
|
T23 |
1 |
|
T24 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39190 |
1 |
|
|
T1 |
26 |
|
T2 |
98 |
|
T3 |
10 |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T10 |
14 |
|
T40 |
7 |
|
T41 |
6 |
auto[1] |
auto[0] |
1924 |
1 |
|
|
T13 |
12 |
|
T51 |
13 |
|
T16 |
11 |
auto[1] |
auto[1] |
115 |
1 |
|
|
T13 |
1 |
|
T51 |
2 |
|
T16 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30827 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
696 |
1 |
|
|
T15 |
10 |
|
T21 |
8 |
|
T77 |
11 |
auto[1] |
auto[0] |
10448 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
51 |
auto[1] |
auto[1] |
504 |
1 |
|
|
T4 |
9 |
|
T16 |
3 |
|
T24 |
7 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30902 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
621 |
1 |
|
|
T15 |
9 |
|
T21 |
8 |
|
T77 |
8 |
auto[1] |
auto[0] |
10393 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
54 |
auto[1] |
auto[1] |
559 |
1 |
|
|
T4 |
6 |
|
T16 |
15 |
|
T24 |
5 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30456 |
1 |
|
|
T1 |
9 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
1067 |
1 |
|
|
T1 |
5 |
|
T206 |
4 |
|
T23 |
26 |
auto[1] |
auto[0] |
10093 |
1 |
|
|
T4 |
60 |
|
T13 |
13 |
|
T16 |
79 |
auto[1] |
auto[1] |
859 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T16 |
15 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30824 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
699 |
1 |
|
|
T15 |
10 |
|
T21 |
10 |
|
T77 |
4 |
auto[1] |
auto[0] |
10366 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
54 |
auto[1] |
auto[1] |
586 |
1 |
|
|
T4 |
6 |
|
T16 |
11 |
|
T24 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
27127 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
4396 |
1 |
|
|
T15 |
13 |
|
T78 |
60 |
|
T207 |
57 |
auto[1] |
auto[0] |
10414 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
52 |
auto[1] |
auto[1] |
538 |
1 |
|
|
T4 |
8 |
|
T16 |
15 |
|
T24 |
5 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30654 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
74 |
auto[0] |
auto[1] |
869 |
1 |
|
|
T10 |
8 |
|
T40 |
8 |
|
T16 |
1 |
auto[1] |
auto[0] |
10481 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
auto[1] |
auto[1] |
471 |
1 |
|
|
T22 |
5 |
|
T24 |
9 |
|
T17 |
6 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30648 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
70 |
auto[0] |
auto[1] |
875 |
1 |
|
|
T10 |
12 |
|
T40 |
6 |
|
T16 |
1 |
auto[1] |
auto[0] |
10451 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
auto[1] |
auto[1] |
501 |
1 |
|
|
T22 |
12 |
|
T24 |
13 |
|
T17 |
9 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30703 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
71 |
auto[0] |
auto[1] |
820 |
1 |
|
|
T10 |
11 |
|
T51 |
2 |
|
T40 |
6 |
auto[1] |
auto[0] |
10486 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
auto[1] |
auto[1] |
466 |
1 |
|
|
T13 |
1 |
|
T22 |
4 |
|
T24 |
4 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30650 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
76 |
auto[0] |
auto[1] |
873 |
1 |
|
|
T10 |
6 |
|
T51 |
1 |
|
T40 |
8 |
auto[1] |
auto[0] |
10493 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
auto[1] |
auto[1] |
459 |
1 |
|
|
T13 |
1 |
|
T22 |
7 |
|
T24 |
10 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30719 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
68 |
auto[0] |
auto[1] |
804 |
1 |
|
|
T10 |
14 |
|
T51 |
1 |
|
T40 |
16 |
auto[1] |
auto[0] |
10470 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
auto[1] |
auto[1] |
482 |
1 |
|
|
T13 |
2 |
|
T22 |
11 |
|
T23 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30632 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
68 |
auto[0] |
auto[1] |
891 |
1 |
|
|
T10 |
14 |
|
T51 |
2 |
|
T40 |
7 |
auto[1] |
auto[0] |
10482 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
auto[1] |
auto[1] |
470 |
1 |
|
|
T13 |
1 |
|
T22 |
7 |
|
T24 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30854 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
669 |
1 |
|
|
T15 |
11 |
|
T21 |
7 |
|
T77 |
9 |
auto[1] |
auto[0] |
10424 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
56 |
auto[1] |
auto[1] |
528 |
1 |
|
|
T4 |
4 |
|
T16 |
9 |
|
T24 |
3 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30833 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
690 |
1 |
|
|
T15 |
11 |
|
T21 |
11 |
|
T77 |
3 |
auto[1] |
auto[0] |
10371 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
49 |
auto[1] |
auto[1] |
581 |
1 |
|
|
T4 |
11 |
|
T16 |
6 |
|
T24 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30323 |
1 |
|
|
T1 |
14 |
|
T2 |
98 |
|
T10 |
82 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T51 |
15 |
|
T16 |
12 |
|
T75 |
12 |
auto[1] |
auto[0] |
10113 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
60 |
auto[1] |
auto[1] |
839 |
1 |
|
|
T13 |
13 |
|
T23 |
8 |
|
T24 |
19 |