Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66600997

1

T1

71591

T2

25232

T3

21673

auto[1]

1182802

1

T1

590

T2

12286

T3

392

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66587017

1

T1

71100

T2

28056

T3

21477

auto[1]

1196782

1

T1

1081

T2

9462

T3

588

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5518953	1			T1	2564		T2	8616		T3	960
auto[IdleSt]	17010006	1			T1	16593		T2	2759		T3	12257
auto[ClkMuxSt]	29470	1			T1	26		T2	91		T3	10
auto[CntIncrSt]	29240	1			T1	26		T2	91		T3	10
auto[CntProgSt]	1526611	1			T1	52		T2	9096		T3	389
auto[TransCheckSt]	22848	1			T1	9		T2	43		T11	1
auto[TokenHashSt]	21220131	1			T1	38927		T2	394		T11	16
auto[FlashRmaSt]	30269	1			T1	9		T2	32		T4	12
auto[TokenCheck0St]	10568	1			T1	9		T2	32		T4	12
auto[TokenCheck1St]	7750	1			T1	9		T2	30		T4	8
auto[TransProgSt]	330319	1			T1	18		T2	101		T4	513
auto[PostTransSt]	9743682	1			T1	8299		T3	4456		T11	646
auto[ScrapSt]	92464	1			T12	10		T42	24		T24	1025
auto[EscalateSt]	4918343	1			T1	5640		T2	16233		T3	3983
auto[InvalidSt]	7291762	1			T10	9233		T13	10502		T51	803

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1383	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7291762	1			T10	9233		T13	10502		T51	803
EscalateSt	4918343	1			T1	5640		T2	16233		T3	3983
ScrapSt	92464	1			T12	10		T42	24		T24	1025
PostTransSt	9743682	1			T1	8299		T3	4456		T11	646
TransProgSt	330319	1			T1	18		T2	101		T4	513
TokenCheck1St	7750	1			T1	9		T2	30		T4	8
TokenCheck0St	10568	1			T1	9		T2	32		T4	12
FlashRmaSt	30269	1			T1	9		T2	32		T4	12
TokenHashSt	21220131	1			T1	38927		T2	394		T11	16
TransCheckSt	22848	1			T1	9		T2	43		T11	1
CntProgSt	1526611	1			T1	52		T2	9096		T3	389
CntIncrSt	29240	1			T1	26		T2	91		T3	10
ClkMuxSt	29470	1			T1	26		T2	91		T3	10
IdleSt	17010006	1			T1	16593		T2	2759		T3	12257
ResetSt	5518953	1			T1	2564		T2	8616		T3	960
arcs[ResetSt=>IdleSt]	43325	1			T1	29		T2	92		T3	11
arcs[IdleSt=>ScrapSt]	231	1			T12	1		T42	2		T24	1
arcs[IdleSt=>ClkMuxSt]	29279	1			T1	26		T2	91		T3	10
arcs[ClkMuxSt=>CntIncrSt]	29240	1			T1	26		T2	91		T3	10
arcs[CntIncrSt=>PostTransSt]	1272	1			T4	11		T15	11		T16	6
arcs[CntIncrSt=>CntProgSt]	27900	1			T1	26		T2	91		T3	10
arcs[CntProgSt=>PostTransSt]	3914	1			T1	17		T3	10		T4	9
arcs[CntProgSt=>TransCheckSt]	22848	1			T1	9		T2	43		T11	1
arcs[TransCheckSt=>PostTransSt]	3043	1			T4	4		T20	28		T15	11
arcs[TransCheckSt=>TokenHashSt]	19694	1			T1	9		T2	43		T11	1
arcs[TokenHashSt=>PostTransSt]	8238	1			T11	1		T4	24		T14	1
arcs[TokenHashSt=>FlashRmaSt]	10616	1			T1	9		T2	32		T4	12
arcs[FlashRmaSt=>TokenCheck0St]	10568	1			T1	9		T2	32		T4	12
arcs[TokenCheck0St=>PostTransSt]	2750	1			T4	4		T20	15		T15	9
arcs[TokenCheck0St=>TokenCheck1St]	7750	1			T1	9		T2	30		T4	8
arcs[TokenCheck1St=>PostTransSt]	638	1			T4	2		T20	6		T19	14
arcs[TransProgSt=>PostTransSt]	6264	1			T1	9		T4	6		T12	17
arcs[IdleSt=>EscalateSt]	174	1			T52	10		T38	7		T53	7
arcs[ClkMuxSt=>EscalateSt]	39	1			T52	5		T38	2		T53	2
arcs[CntIncrSt=>EscalateSt]	68	1			T52	2		T38	1		T54	2
arcs[CntProgSt=>EscalateSt]	1138	1			T2	48		T52	26		T38	37
arcs[TransCheckSt=>EscalateSt]	111	1			T52	1		T53	3		T54	3
arcs[TokenHashSt=>EscalateSt]	840	1			T2	11		T52	13		T38	11
arcs[FlashRmaSt=>EscalateSt]	48	1			T52	1		T38	1		T54	1
arcs[TokenCheck0St=>EscalateSt]	68	1			T2	2		T52	5		T53	1
arcs[TokenCheck1St=>EscalateSt]	37	1			T2	1		T38	1		T53	1
arcs[TransProgSt=>EscalateSt]	811	1			T2	29		T52	20		T38	22
arcs[PostTransSt=>EscalateSt]	4313	1			T1	17		T3	10		T4	9
arcs[InvalidSt=>EscalateSt]	10069	1			T10	68		T13	5		T51	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5518783	1			T1	2564		T2	8611		T3	960
auto[0]	auto[IdleSt]	17009892	1			T1	16593		T2	2759		T3	12257
auto[0]	auto[ClkMuxSt]	29444	1			T1	26		T2	91		T3	10
auto[0]	auto[CntIncrSt]	29194	1			T1	26		T2	91		T3	10
auto[0]	auto[CntProgSt]	1525857	1			T1	52		T2	9058		T3	389
auto[0]	auto[TransCheckSt]	22769	1			T1	9		T2	43		T11	1
auto[0]	auto[TokenHashSt]	21219568	1			T1	38927		T2	386		T11	16
auto[0]	auto[FlashRmaSt]	30240	1			T1	9		T2	32		T4	12
auto[0]	auto[TokenCheck0St]	10519	1			T1	9		T2	30		T4	12
auto[0]	auto[TokenCheck1St]	7725	1			T1	9		T2	29		T4	8
auto[0]	auto[TransProgSt]	329766	1			T1	18		T2	81		T4	513
auto[0]	auto[PostTransSt]	9741425	1			T1	8293		T3	4452		T11	646
auto[0]	auto[ScrapSt]	92412	1			T12	10		T42	24		T24	1025
auto[0]	auto[EscalateSt]	3745203	1			T1	5056		T2	4021		T3	3595
auto[0]	auto[InvalidSt]	7286817	1			T10	9198		T13	10499		T51	799
auto[1]	auto[ResetSt]	170	1			T2	5		T52	3		T38	4
auto[1]	auto[IdleSt]	114	1			T52	10		T38	5		T53	4
auto[1]	auto[ClkMuxSt]	26	1			T52	4		T38	1		T53	2
auto[1]	auto[CntIncrSt]	46	1			T52	2		T54	1		T203	1
auto[1]	auto[CntProgSt]	754	1			T2	38		T52	17		T38	22
auto[1]	auto[TransCheckSt]	79	1			T52	1		T53	2		T54	2
auto[1]	auto[TokenHashSt]	563	1			T2	8		T52	9		T38	9
auto[1]	auto[FlashRmaSt]	29	1			T52	1		T203	1		T204	2
auto[1]	auto[TokenCheck0St]	49	1			T2	2		T52	3		T53	1
auto[1]	auto[TokenCheck1St]	25	1			T2	1		T38	1		T53	1
auto[1]	auto[TransProgSt]	553	1			T2	20		T52	14		T38	14
auto[1]	auto[PostTransSt]	2257	1			T1	6		T3	4		T4	6
auto[1]	auto[ScrapSt]	52	1			T53	2		T54	2		T203	2
auto[1]	auto[EscalateSt]	1173140	1			T1	584		T2	12212		T3	388
auto[1]	auto[InvalidSt]	4945	1			T10	35		T13	3		T51	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5518776	1			T1	2564		T2	8614		T3	960
auto[0]	auto[IdleSt]	17009882	1			T1	16593		T2	2759		T3	12257
auto[0]	auto[ClkMuxSt]	29439	1			T1	26		T2	91		T3	10
auto[0]	auto[CntIncrSt]	29195	1			T1	26		T2	91		T3	10
auto[0]	auto[CntProgSt]	1525840	1			T1	52		T2	9067		T3	389
auto[0]	auto[TransCheckSt]	22770	1			T1	9		T2	43		T11	1
auto[0]	auto[TokenHashSt]	21219585	1			T1	38927		T2	387		T11	16
auto[0]	auto[FlashRmaSt]	30233	1			T1	9		T2	32		T4	12
auto[0]	auto[TokenCheck0St]	10526	1			T1	9		T2	32		T4	12
auto[0]	auto[TokenCheck1St]	7723	1			T1	9		T2	29		T4	8
auto[0]	auto[TransProgSt]	329774	1			T1	18		T2	83		T4	513
auto[0]	auto[PostTransSt]	9741500	1			T1	8288		T3	4450		T11	646
auto[0]	auto[ScrapSt]	92422	1			T12	10		T42	24		T24	1025
auto[0]	auto[EscalateSt]	3731331	1			T1	4570		T2	6828		T3	3401
auto[0]	auto[InvalidSt]	7286638	1			T10	9200		T13	10500		T51	801
auto[1]	auto[ResetSt]	177	1			T2	2		T52	4		T38	3
auto[1]	auto[IdleSt]	124	1			T52	5		T38	5		T53	4
auto[1]	auto[ClkMuxSt]	31	1			T52	4		T38	2		T53	1
auto[1]	auto[CntIncrSt]	45	1			T52	1		T38	1		T54	2
auto[1]	auto[CntProgSt]	771	1			T2	29		T52	21		T38	22
auto[1]	auto[TransCheckSt]	78	1			T52	1		T53	2		T54	2
auto[1]	auto[TokenHashSt]	546	1			T2	7		T52	8		T38	10
auto[1]	auto[FlashRmaSt]	36	1			T38	1		T54	1		T205	1
auto[1]	auto[TokenCheck0St]	42	1			T52	4		T53	1		T203	1
auto[1]	auto[TokenCheck1St]	27	1			T2	1		T38	1		T205	2
auto[1]	auto[TransProgSt]	545	1			T2	18		T52	10		T38	17
auto[1]	auto[PostTransSt]	2182	1			T1	11		T3	6		T4	3
auto[1]	auto[ScrapSt]	42	1			T38	1		T53	1		T205	1
auto[1]	auto[EscalateSt]	1187012	1			T1	1070		T2	9405		T3	582
auto[1]	auto[InvalidSt]	5124	1			T10	33		T13	2		T51	2