Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39624 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
1251 |
1 |
|
|
T14 |
9 |
|
T15 |
7 |
|
T24 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40128 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
747 |
1 |
|
|
T10 |
17 |
|
T16 |
14 |
|
T64 |
9 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39618 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
61 |
auto[1] |
1257 |
1 |
|
|
T4 |
9 |
|
T25 |
8 |
|
T26 |
4 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39604 |
1 |
|
|
T1 |
13 |
|
T2 |
9 |
|
T4 |
61 |
auto[1] |
1271 |
1 |
|
|
T1 |
2 |
|
T4 |
9 |
|
T25 |
6 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39579 |
1 |
|
|
T1 |
14 |
|
T2 |
9 |
|
T4 |
60 |
auto[1] |
1296 |
1 |
|
|
T1 |
1 |
|
T4 |
10 |
|
T25 |
12 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
37854 |
1 |
|
|
T1 |
8 |
|
T2 |
9 |
|
T4 |
70 |
no_err_inj |
3021 |
1 |
|
|
T1 |
7 |
|
T6 |
16 |
|
T78 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39629 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
1246 |
1 |
|
|
T14 |
13 |
|
T15 |
12 |
|
T24 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40137 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
738 |
1 |
|
|
T10 |
13 |
|
T16 |
13 |
|
T64 |
15 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31259 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
9616 |
1 |
|
|
T6 |
9 |
|
T26 |
54 |
|
T27 |
99 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39638 |
1 |
|
|
T1 |
14 |
|
T2 |
9 |
|
T4 |
60 |
auto[1] |
1237 |
1 |
|
|
T1 |
1 |
|
T4 |
10 |
|
T25 |
10 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39626 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
61 |
auto[1] |
1249 |
1 |
|
|
T4 |
9 |
|
T25 |
13 |
|
T26 |
5 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39587 |
1 |
|
|
T1 |
13 |
|
T2 |
9 |
|
T4 |
64 |
auto[1] |
1288 |
1 |
|
|
T1 |
2 |
|
T4 |
6 |
|
T25 |
6 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39660 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
1215 |
1 |
|
|
T14 |
10 |
|
T15 |
10 |
|
T24 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39305 |
1 |
|
|
T1 |
15 |
|
T4 |
70 |
|
T10 |
81 |
auto[1] |
1570 |
1 |
|
|
T2 |
9 |
|
T13 |
8 |
|
T6 |
3 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40172 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
703 |
1 |
|
|
T10 |
15 |
|
T16 |
17 |
|
T64 |
8 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40128 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
747 |
1 |
|
|
T10 |
14 |
|
T16 |
12 |
|
T64 |
11 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40152 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
723 |
1 |
|
|
T10 |
22 |
|
T16 |
12 |
|
T64 |
10 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38954 |
1 |
|
|
T2 |
9 |
|
T4 |
70 |
|
T10 |
81 |
auto[1] |
1921 |
1 |
|
|
T1 |
15 |
|
T91 |
15 |
|
T209 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37090 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
3785 |
1 |
|
|
T12 |
76 |
|
T22 |
65 |
|
T51 |
61 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39674 |
1 |
|
|
T1 |
14 |
|
T2 |
9 |
|
T4 |
64 |
auto[1] |
1201 |
1 |
|
|
T1 |
1 |
|
T4 |
6 |
|
T25 |
12 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39592 |
1 |
|
|
T1 |
14 |
|
T2 |
9 |
|
T4 |
66 |
auto[1] |
1283 |
1 |
|
|
T1 |
1 |
|
T4 |
4 |
|
T25 |
10 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39586 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
63 |
auto[1] |
1289 |
1 |
|
|
T4 |
7 |
|
T25 |
7 |
|
T26 |
4 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39676 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
1199 |
1 |
|
|
T14 |
13 |
|
T15 |
6 |
|
T24 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35658 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
5217 |
1 |
|
|
T11 |
81 |
|
T14 |
4 |
|
T23 |
89 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37220 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
3655 |
1 |
|
|
T19 |
83 |
|
T63 |
51 |
|
T21 |
69 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40875 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39624 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
1251 |
1 |
|
|
T14 |
8 |
|
T6 |
1 |
|
T15 |
8 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39670 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
1205 |
1 |
|
|
T14 |
13 |
|
T6 |
2 |
|
T15 |
15 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39644 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[1] |
1231 |
1 |
|
|
T14 |
4 |
|
T6 |
3 |
|
T15 |
10 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
36873 |
1 |
|
|
T2 |
9 |
|
T4 |
70 |
|
T10 |
81 |
auto[0] |
no_err_inj |
2081 |
1 |
|
|
T6 |
16 |
|
T78 |
5 |
|
T39 |
8 |
auto[1] |
err_inj |
981 |
1 |
|
|
T1 |
8 |
|
T91 |
8 |
|
T209 |
4 |
auto[1] |
no_err_inj |
940 |
1 |
|
|
T1 |
7 |
|
T91 |
7 |
|
T209 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37753 |
1 |
|
|
T2 |
9 |
|
T4 |
66 |
|
T10 |
81 |
auto[0] |
auto[1] |
1201 |
1 |
|
|
T4 |
4 |
|
T25 |
10 |
|
T26 |
4 |
auto[1] |
auto[0] |
1839 |
1 |
|
|
T1 |
14 |
|
T91 |
14 |
|
T209 |
11 |
auto[1] |
auto[1] |
82 |
1 |
|
|
T1 |
1 |
|
T91 |
1 |
|
T210 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37807 |
1 |
|
|
T2 |
9 |
|
T4 |
61 |
|
T10 |
81 |
auto[0] |
auto[1] |
1147 |
1 |
|
|
T4 |
9 |
|
T25 |
13 |
|
T26 |
5 |
auto[1] |
auto[0] |
1819 |
1 |
|
|
T1 |
15 |
|
T91 |
15 |
|
T209 |
10 |
auto[1] |
auto[1] |
102 |
1 |
|
|
T209 |
1 |
|
T211 |
1 |
|
T212 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37791 |
1 |
|
|
T2 |
9 |
|
T4 |
63 |
|
T10 |
81 |
auto[0] |
auto[1] |
1163 |
1 |
|
|
T4 |
7 |
|
T25 |
7 |
|
T26 |
4 |
auto[1] |
auto[0] |
1795 |
1 |
|
|
T1 |
15 |
|
T91 |
14 |
|
T209 |
11 |
auto[1] |
auto[1] |
126 |
1 |
|
|
T91 |
1 |
|
T213 |
3 |
|
T211 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37797 |
1 |
|
|
T2 |
9 |
|
T4 |
61 |
|
T10 |
81 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T4 |
9 |
|
T25 |
6 |
|
T26 |
9 |
auto[1] |
auto[0] |
1807 |
1 |
|
|
T1 |
13 |
|
T91 |
15 |
|
T209 |
11 |
auto[1] |
auto[1] |
114 |
1 |
|
|
T1 |
2 |
|
T210 |
1 |
|
T212 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37770 |
1 |
|
|
T2 |
9 |
|
T4 |
60 |
|
T10 |
81 |
auto[0] |
auto[1] |
1184 |
1 |
|
|
T4 |
10 |
|
T25 |
12 |
|
T26 |
9 |
auto[1] |
auto[0] |
1809 |
1 |
|
|
T1 |
14 |
|
T91 |
13 |
|
T209 |
11 |
auto[1] |
auto[1] |
112 |
1 |
|
|
T1 |
1 |
|
T91 |
2 |
|
T65 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37785 |
1 |
|
|
T2 |
9 |
|
T4 |
61 |
|
T10 |
81 |
auto[0] |
auto[1] |
1169 |
1 |
|
|
T4 |
9 |
|
T25 |
8 |
|
T26 |
4 |
auto[1] |
auto[0] |
1833 |
1 |
|
|
T1 |
15 |
|
T91 |
13 |
|
T209 |
9 |
auto[1] |
auto[1] |
88 |
1 |
|
|
T91 |
2 |
|
T209 |
2 |
|
T211 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30510 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[0] |
auto[1] |
749 |
1 |
|
|
T14 |
9 |
|
T15 |
7 |
|
T24 |
9 |
auto[1] |
auto[0] |
9114 |
1 |
|
|
T6 |
9 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
502 |
1 |
|
|
T29 |
5 |
|
T42 |
25 |
|
T88 |
9 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30520 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[0] |
auto[1] |
739 |
1 |
|
|
T14 |
13 |
|
T15 |
12 |
|
T24 |
9 |
auto[1] |
auto[0] |
9109 |
1 |
|
|
T6 |
9 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
507 |
1 |
|
|
T29 |
10 |
|
T42 |
26 |
|
T88 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30219 |
1 |
|
|
T1 |
15 |
|
T4 |
70 |
|
T10 |
81 |
auto[0] |
auto[1] |
1040 |
1 |
|
|
T2 |
9 |
|
T13 |
8 |
|
T6 |
3 |
auto[1] |
auto[0] |
9086 |
1 |
|
|
T6 |
9 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
530 |
1 |
|
|
T214 |
7 |
|
T215 |
16 |
|
T216 |
19 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30547 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[0] |
auto[1] |
712 |
1 |
|
|
T14 |
10 |
|
T15 |
10 |
|
T24 |
10 |
auto[1] |
auto[0] |
9113 |
1 |
|
|
T6 |
9 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
503 |
1 |
|
|
T29 |
10 |
|
T42 |
30 |
|
T88 |
15 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
26553 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[0] |
auto[1] |
4706 |
1 |
|
|
T11 |
81 |
|
T14 |
4 |
|
T23 |
89 |
auto[1] |
auto[0] |
9105 |
1 |
|
|
T6 |
9 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
511 |
1 |
|
|
T29 |
12 |
|
T42 |
36 |
|
T88 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30386 |
1 |
|
|
T1 |
14 |
|
T2 |
9 |
|
T4 |
66 |
auto[0] |
auto[1] |
873 |
1 |
|
|
T1 |
1 |
|
T4 |
4 |
|
T25 |
10 |
auto[1] |
auto[0] |
9206 |
1 |
|
|
T6 |
9 |
|
T26 |
50 |
|
T27 |
90 |
auto[1] |
auto[1] |
410 |
1 |
|
|
T26 |
4 |
|
T27 |
9 |
|
T28 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30445 |
1 |
|
|
T1 |
14 |
|
T2 |
9 |
|
T4 |
64 |
auto[0] |
auto[1] |
814 |
1 |
|
|
T1 |
1 |
|
T4 |
6 |
|
T25 |
12 |
auto[1] |
auto[0] |
9229 |
1 |
|
|
T6 |
9 |
|
T26 |
49 |
|
T27 |
91 |
auto[1] |
auto[1] |
387 |
1 |
|
|
T26 |
5 |
|
T27 |
8 |
|
T28 |
13 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30421 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
61 |
auto[0] |
auto[1] |
838 |
1 |
|
|
T4 |
9 |
|
T25 |
13 |
|
T209 |
1 |
auto[1] |
auto[0] |
9205 |
1 |
|
|
T6 |
9 |
|
T26 |
49 |
|
T27 |
84 |
auto[1] |
auto[1] |
411 |
1 |
|
|
T26 |
5 |
|
T27 |
15 |
|
T28 |
11 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30426 |
1 |
|
|
T1 |
14 |
|
T2 |
9 |
|
T4 |
60 |
auto[0] |
auto[1] |
833 |
1 |
|
|
T1 |
1 |
|
T4 |
10 |
|
T25 |
10 |
auto[1] |
auto[0] |
9212 |
1 |
|
|
T6 |
9 |
|
T26 |
48 |
|
T27 |
85 |
auto[1] |
auto[1] |
404 |
1 |
|
|
T26 |
6 |
|
T27 |
14 |
|
T28 |
9 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30415 |
1 |
|
|
T1 |
13 |
|
T2 |
9 |
|
T4 |
61 |
auto[0] |
auto[1] |
844 |
1 |
|
|
T1 |
2 |
|
T4 |
9 |
|
T25 |
6 |
auto[1] |
auto[0] |
9189 |
1 |
|
|
T6 |
9 |
|
T26 |
45 |
|
T27 |
82 |
auto[1] |
auto[1] |
427 |
1 |
|
|
T26 |
9 |
|
T27 |
17 |
|
T28 |
16 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30408 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
61 |
auto[0] |
auto[1] |
851 |
1 |
|
|
T4 |
9 |
|
T25 |
8 |
|
T209 |
2 |
auto[1] |
auto[0] |
9210 |
1 |
|
|
T6 |
9 |
|
T26 |
50 |
|
T27 |
94 |
auto[1] |
auto[1] |
406 |
1 |
|
|
T26 |
4 |
|
T27 |
5 |
|
T28 |
14 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30562 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[0] |
auto[1] |
697 |
1 |
|
|
T14 |
4 |
|
T15 |
10 |
|
T24 |
9 |
auto[1] |
auto[0] |
9082 |
1 |
|
|
T6 |
6 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
534 |
1 |
|
|
T6 |
3 |
|
T29 |
13 |
|
T42 |
24 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30519 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T4 |
70 |
auto[0] |
auto[1] |
740 |
1 |
|
|
T14 |
13 |
|
T15 |
15 |
|
T24 |
9 |
auto[1] |
auto[0] |
9151 |
1 |
|
|
T6 |
7 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
465 |
1 |
|
|
T6 |
2 |
|
T29 |
5 |
|
T42 |
28 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30040 |
1 |
|
|
T2 |
9 |
|
T4 |
70 |
|
T10 |
81 |
auto[0] |
auto[1] |
1219 |
1 |
|
|
T1 |
15 |
|
T209 |
11 |
|
T210 |
13 |
auto[1] |
auto[0] |
8914 |
1 |
|
|
T6 |
9 |
|
T26 |
54 |
|
T27 |
99 |
auto[1] |
auto[1] |
702 |
1 |
|
|
T91 |
15 |
|
T65 |
14 |
|
T211 |
12 |