Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59517231

1

T1

9864

T2

3717

T3

76870

auto[1]

1126364

1

T1

198

T2

396

T4

2475

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59529181

1

T1

9666

T2

3618

T3

76870

auto[1]

1114414

1

T1

396

T2

495

T4

3168

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5350167	1			T1	1676		T2	809		T3	79
auto[IdleSt]	15802243	1			T1	1564		T2	1094		T3	76791
auto[ClkMuxSt]	28367	1			T1	7		T2	9		T10	67
auto[CntIncrSt]	28211	1			T1	7		T2	9		T10	67
auto[CntProgSt]	1280414	1			T1	1311		T2	492		T10	117
auto[TransCheckSt]	22345	1			T1	7		T10	50		T11	81
auto[TokenHashSt]	16267839	1			T1	80		T10	36749		T11	1748
auto[FlashRmaSt]	28123	1			T1	45		T10	125		T12	64
auto[TokenCheck0St]	9733	1			T1	7		T10	42		T12	27
auto[TokenCheck1St]	7010	1			T1	7		T10	30		T12	25
auto[TransProgSt]	339593	1			T1	1320		T10	58		T12	48
auto[PostTransSt]	9272945	1			T1	1718		T2	532		T10	8677
auto[ScrapSt]	312166	1			T6	7		T39	29		T40	1124
auto[EscalateSt]	4678365	1			T1	1450		T2	1168		T4	7076
auto[InvalidSt]	7214732	1			T1	863		T4	4276		T10	1113

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1342	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7214732	1			T1	863		T4	4276		T10	1113
EscalateSt	4678365	1			T1	1450		T2	1168		T4	7076
ScrapSt	312166	1			T6	7		T39	29		T40	1124
PostTransSt	9272945	1			T1	1718		T2	532		T10	8677
TransProgSt	339593	1			T1	1320		T10	58		T12	48
TokenCheck1St	7010	1			T1	7		T10	30		T12	25
TokenCheck0St	9733	1			T1	7		T10	42		T12	27
FlashRmaSt	28123	1			T1	45		T10	125		T12	64
TokenHashSt	16267839	1			T1	80		T10	36749		T11	1748
TransCheckSt	22345	1			T1	7		T10	50		T11	81
CntProgSt	1280414	1			T1	1311		T2	492		T10	117
CntIncrSt	28211	1			T1	7		T2	9		T10	67
ClkMuxSt	28367	1			T1	7		T2	9		T10	67
IdleSt	15802243	1			T1	1564		T2	1094		T3	76791
ResetSt	5350167	1			T1	1676		T2	809		T3	79
arcs[ResetSt=>IdleSt]	41595	1			T1	14		T2	10		T3	1
arcs[IdleSt=>ScrapSt]	216	1			T6	1		T39	2		T40	1
arcs[IdleSt=>ClkMuxSt]	28261	1			T1	7		T2	9		T10	67
arcs[ClkMuxSt=>CntIncrSt]	28211	1			T1	7		T2	9		T10	67
arcs[CntIncrSt=>PostTransSt]	1207	1			T14	13		T6	2		T15	15
arcs[CntIncrSt=>CntProgSt]	26954	1			T1	7		T2	9		T10	67
arcs[CntProgSt=>PostTransSt]	3560	1			T2	9		T10	17		T13	8
arcs[CntProgSt=>TransCheckSt]	22345	1			T1	7		T10	50		T11	81
arcs[TransCheckSt=>PostTransSt]	3086	1			T14	4		T6	3		T15	10
arcs[TransCheckSt=>TokenHashSt]	19163	1			T1	7		T10	50		T11	81
arcs[TokenHashSt=>PostTransSt]	8610	1			T10	8		T11	81		T14	25
arcs[TokenHashSt=>FlashRmaSt]	9774	1			T1	7		T10	42		T12	28
arcs[FlashRmaSt=>TokenCheck0St]	9733	1			T1	7		T10	42		T12	27
arcs[TokenCheck0St=>PostTransSt]	2662	1			T10	12		T14	11		T15	12
arcs[TokenCheck0St=>TokenCheck1St]	7010	1			T1	7		T10	30		T12	25
arcs[TokenCheck1St=>PostTransSt]	594	1			T10	1		T14	2		T16	1
arcs[TransProgSt=>PostTransSt]	5575	1			T1	7		T10	29		T12	19
arcs[IdleSt=>EscalateSt]	177	1			T12	6		T22	5		T51	1
arcs[ClkMuxSt=>EscalateSt]	50	1			T12	1		T22	2		T50	1
arcs[CntIncrSt=>EscalateSt]	50	1			T12	3		T22	3		T51	1
arcs[CntProgSt=>EscalateSt]	1049	1			T12	4		T22	4		T51	23
arcs[TransCheckSt=>EscalateSt]	96	1			T12	6		T22	4		T50	6
arcs[TokenHashSt=>EscalateSt]	779	1			T12	22		T22	26		T51	12
arcs[FlashRmaSt=>EscalateSt]	41	1			T12	1		T22	1		T52	1
arcs[TokenCheck0St=>EscalateSt]	61	1			T12	2		T22	2		T51	1
arcs[TokenCheck1St=>EscalateSt]	20	1			T53	1		T58	1		T59	1
arcs[TransProgSt=>EscalateSt]	821	1			T12	6		T22	2		T51	18
arcs[PostTransSt=>EscalateSt]	3911	1			T2	9		T10	17		T12	19
arcs[InvalidSt=>EscalateSt]	9561	1			T1	6		T4	57		T10	14

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5349996	1			T1	1676		T2	809		T3	79
auto[0]	auto[IdleSt]	15802125	1			T1	1564		T2	1094		T3	76791
auto[0]	auto[ClkMuxSt]	28333	1			T1	7		T2	9		T10	67
auto[0]	auto[CntIncrSt]	28177	1			T1	7		T2	9		T10	67
auto[0]	auto[CntProgSt]	1279699	1			T1	1311		T2	492		T10	117
auto[0]	auto[TransCheckSt]	22283	1			T1	7		T10	50		T11	81
auto[0]	auto[TokenHashSt]	16267338	1			T1	80		T10	36749		T11	1748
auto[0]	auto[FlashRmaSt]	28093	1			T1	45		T10	125		T12	64
auto[0]	auto[TokenCheck0St]	9691	1			T1	7		T10	42		T12	25
auto[0]	auto[TokenCheck1St]	6994	1			T1	7		T10	30		T12	25
auto[0]	auto[TransProgSt]	339031	1			T1	1320		T10	58		T12	45
auto[0]	auto[PostTransSt]	9270947	1			T1	1718		T2	528		T10	8667
auto[0]	auto[ScrapSt]	312131	1			T6	7		T39	29		T40	1124
auto[0]	auto[EscalateSt]	3561128	1			T1	1254		T2	776		T4	4626
auto[0]	auto[InvalidSt]	7209923	1			T1	861		T4	4251		T10	1109
auto[1]	auto[ResetSt]	171	1			T12	3		T22	2		T51	3
auto[1]	auto[IdleSt]	118	1			T12	2		T22	4		T51	1
auto[1]	auto[ClkMuxSt]	34	1			T12	1		T22	1		T87	2
auto[1]	auto[CntIncrSt]	34	1			T12	3		T22	1		T50	1
auto[1]	auto[CntProgSt]	715	1			T12	4		T22	2		T51	16
auto[1]	auto[TransCheckSt]	62	1			T12	6		T50	5		T53	1
auto[1]	auto[TokenHashSt]	501	1			T12	17		T22	19		T51	4
auto[1]	auto[FlashRmaSt]	30	1			T22	1		T87	1		T207	2
auto[1]	auto[TokenCheck0St]	42	1			T12	2		T22	1		T53	1
auto[1]	auto[TokenCheck1St]	16	1			T53	1		T58	1		T59	1
auto[1]	auto[TransProgSt]	562	1			T12	3		T22	1		T51	13
auto[1]	auto[PostTransSt]	1998	1			T2	4		T10	10		T12	14
auto[1]	auto[ScrapSt]	35	1			T53	1		T52	1		T54	1
auto[1]	auto[EscalateSt]	1117237	1			T1	196		T2	392		T4	2450
auto[1]	auto[InvalidSt]	4809	1			T1	2		T4	25		T10	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5349995	1			T1	1676		T2	809		T3	79
auto[0]	auto[IdleSt]	15802128	1			T1	1564		T2	1094		T3	76791
auto[0]	auto[ClkMuxSt]	28332	1			T1	7		T2	9		T10	67
auto[0]	auto[CntIncrSt]	28174	1			T1	7		T2	9		T10	67
auto[0]	auto[CntProgSt]	1279722	1			T1	1311		T2	492		T10	117
auto[0]	auto[TransCheckSt]	22275	1			T1	7		T10	50		T11	81
auto[0]	auto[TokenHashSt]	16267325	1			T1	80		T10	36749		T11	1748
auto[0]	auto[FlashRmaSt]	28099	1			T1	45		T10	125		T12	63
auto[0]	auto[TokenCheck0St]	9689	1			T1	7		T10	42		T12	25
auto[0]	auto[TokenCheck1St]	6999	1			T1	7		T10	30		T12	25
auto[0]	auto[TransProgSt]	339069	1			T1	1320		T10	58		T12	43
auto[0]	auto[PostTransSt]	9270922	1			T1	1718		T2	527		T10	8670
auto[0]	auto[ScrapSt]	312125	1			T6	7		T39	29		T40	1124
auto[0]	auto[EscalateSt]	3573005	1			T1	1058		T2	678		T4	3940
auto[0]	auto[InvalidSt]	7209980	1			T1	859		T4	4244		T10	1103
auto[1]	auto[ResetSt]	172	1			T12	5		T22	3		T51	1
auto[1]	auto[IdleSt]	115	1			T12	6		T22	3		T51	1
auto[1]	auto[ClkMuxSt]	35	1			T12	1		T22	2		T50	1
auto[1]	auto[CntIncrSt]	37	1			T12	1		T22	3		T51	1
auto[1]	auto[CntProgSt]	692	1			T12	1		T22	3		T51	17
auto[1]	auto[TransCheckSt]	70	1			T12	3		T22	4		T50	4
auto[1]	auto[TokenHashSt]	514	1			T12	16		T22	10		T51	10
auto[1]	auto[FlashRmaSt]	24	1			T12	1		T22	1		T52	1
auto[1]	auto[TokenCheck0St]	44	1			T12	2		T22	1		T51	1
auto[1]	auto[TokenCheck1St]	11	1			T58	1		T207	1		T208	1
auto[1]	auto[TransProgSt]	524	1			T12	5		T22	1		T51	12
auto[1]	auto[PostTransSt]	2023	1			T2	5		T10	7		T12	13
auto[1]	auto[ScrapSt]	41	1			T52	1		T54	1		T87	2
auto[1]	auto[EscalateSt]	1105360	1			T1	392		T2	490		T4	3136
auto[1]	auto[InvalidSt]	4752	1			T1	4		T4	32		T10	10