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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.82 97.92 95.66 93.40 97.62 98.31 98.76 96.11


Total test records in report: 999
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T814 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1171275879 Aug 19 05:58:06 PM PDT 24 Aug 19 05:58:10 PM PDT 24 374436402 ps
T99 /workspace/coverage/default/3.lc_ctrl_sec_cm.292365867 Aug 19 05:58:06 PM PDT 24 Aug 19 05:58:40 PM PDT 24 221002597 ps
T815 /workspace/coverage/default/27.lc_ctrl_prog_failure.3664897190 Aug 19 06:00:33 PM PDT 24 Aug 19 06:00:36 PM PDT 24 250513469 ps
T151 /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3728861864 Aug 19 06:01:43 PM PDT 24 Aug 19 06:03:33 PM PDT 24 2898097788 ps
T816 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3731160777 Aug 19 06:01:46 PM PDT 24 Aug 19 06:01:56 PM PDT 24 639851128 ps
T817 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.575883899 Aug 19 06:00:39 PM PDT 24 Aug 19 06:00:47 PM PDT 24 571243981 ps
T818 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.230446397 Aug 19 05:58:14 PM PDT 24 Aug 19 05:58:25 PM PDT 24 786583723 ps
T819 /workspace/coverage/default/41.lc_ctrl_alert_test.2291253979 Aug 19 06:01:27 PM PDT 24 Aug 19 06:01:29 PM PDT 24 28011958 ps
T820 /workspace/coverage/default/44.lc_ctrl_stress_all.898916812 Aug 19 06:01:39 PM PDT 24 Aug 19 06:02:19 PM PDT 24 2635906374 ps
T821 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2450085319 Aug 19 05:59:40 PM PDT 24 Aug 19 05:59:46 PM PDT 24 185707366 ps
T822 /workspace/coverage/default/5.lc_ctrl_jtag_access.3383403300 Aug 19 05:58:25 PM PDT 24 Aug 19 05:58:31 PM PDT 24 966586309 ps
T823 /workspace/coverage/default/39.lc_ctrl_stress_all.2600851848 Aug 19 06:01:17 PM PDT 24 Aug 19 06:03:30 PM PDT 24 31827465230 ps
T824 /workspace/coverage/default/9.lc_ctrl_security_escalation.3284381712 Aug 19 05:59:02 PM PDT 24 Aug 19 05:59:11 PM PDT 24 886297611 ps
T825 /workspace/coverage/default/8.lc_ctrl_state_post_trans.3098061850 Aug 19 05:58:53 PM PDT 24 Aug 19 05:59:02 PM PDT 24 239659600 ps
T826 /workspace/coverage/default/27.lc_ctrl_alert_test.2814647071 Aug 19 06:00:41 PM PDT 24 Aug 19 06:00:42 PM PDT 24 48762633 ps
T827 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1705510352 Aug 19 05:58:06 PM PDT 24 Aug 19 05:58:13 PM PDT 24 2218641957 ps
T828 /workspace/coverage/default/27.lc_ctrl_state_failure.3662494542 Aug 19 06:00:30 PM PDT 24 Aug 19 06:00:50 PM PDT 24 840077485 ps
T829 /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3986347293 Aug 19 06:00:51 PM PDT 24 Aug 19 06:00:52 PM PDT 24 14697061 ps
T830 /workspace/coverage/default/47.lc_ctrl_security_escalation.4008943256 Aug 19 06:01:45 PM PDT 24 Aug 19 06:01:52 PM PDT 24 456311154 ps
T831 /workspace/coverage/default/24.lc_ctrl_alert_test.3965054682 Aug 19 06:00:29 PM PDT 24 Aug 19 06:00:30 PM PDT 24 21829226 ps
T832 /workspace/coverage/default/40.lc_ctrl_stress_all.1619391897 Aug 19 06:01:28 PM PDT 24 Aug 19 06:06:11 PM PDT 24 39698966501 ps
T833 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.183811571 Aug 19 05:58:25 PM PDT 24 Aug 19 05:58:51 PM PDT 24 3291790392 ps
T834 /workspace/coverage/default/27.lc_ctrl_smoke.2373420178 Aug 19 06:00:32 PM PDT 24 Aug 19 06:00:35 PM PDT 24 85702318 ps
T835 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1562427078 Aug 19 05:59:24 PM PDT 24 Aug 19 05:59:36 PM PDT 24 9633381410 ps
T836 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.4139830344 Aug 19 05:57:32 PM PDT 24 Aug 19 05:58:31 PM PDT 24 6558827442 ps
T837 /workspace/coverage/default/28.lc_ctrl_errors.1176381812 Aug 19 06:00:44 PM PDT 24 Aug 19 06:01:03 PM PDT 24 1996814053 ps
T838 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.534630361 Aug 19 06:00:30 PM PDT 24 Aug 19 06:00:38 PM PDT 24 326252838 ps
T839 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1556343578 Aug 19 05:59:25 PM PDT 24 Aug 19 05:59:30 PM PDT 24 1328036674 ps
T840 /workspace/coverage/default/19.lc_ctrl_sec_mubi.3801042219 Aug 19 06:00:12 PM PDT 24 Aug 19 06:00:24 PM PDT 24 557353945 ps
T841 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1260339822 Aug 19 05:59:24 PM PDT 24 Aug 19 05:59:33 PM PDT 24 270051516 ps
T842 /workspace/coverage/default/29.lc_ctrl_errors.202329080 Aug 19 06:00:40 PM PDT 24 Aug 19 06:00:48 PM PDT 24 489534337 ps
T843 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1675043611 Aug 19 05:59:58 PM PDT 24 Aug 19 06:00:09 PM PDT 24 831126671 ps
T844 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3078735627 Aug 19 05:59:23 PM PDT 24 Aug 19 05:59:31 PM PDT 24 220913818 ps
T845 /workspace/coverage/default/18.lc_ctrl_stress_all.2866349767 Aug 19 06:00:17 PM PDT 24 Aug 19 06:01:10 PM PDT 24 7421721544 ps
T846 /workspace/coverage/default/46.lc_ctrl_errors.4270320461 Aug 19 06:01:39 PM PDT 24 Aug 19 06:01:55 PM PDT 24 409199888 ps
T847 /workspace/coverage/default/32.lc_ctrl_security_escalation.686556248 Aug 19 06:00:56 PM PDT 24 Aug 19 06:01:07 PM PDT 24 1074547392 ps
T848 /workspace/coverage/default/22.lc_ctrl_stress_all.3656562910 Aug 19 06:00:31 PM PDT 24 Aug 19 06:02:59 PM PDT 24 8783783795 ps
T849 /workspace/coverage/default/49.lc_ctrl_sec_mubi.1082680693 Aug 19 06:01:55 PM PDT 24 Aug 19 06:02:08 PM PDT 24 365012541 ps
T850 /workspace/coverage/default/31.lc_ctrl_errors.2566795106 Aug 19 06:00:51 PM PDT 24 Aug 19 06:01:05 PM PDT 24 327202572 ps
T851 /workspace/coverage/default/0.lc_ctrl_jtag_errors.2011825807 Aug 19 05:57:31 PM PDT 24 Aug 19 05:57:55 PM PDT 24 1614963136 ps
T852 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2721696406 Aug 19 06:00:58 PM PDT 24 Aug 19 06:01:07 PM PDT 24 217874035 ps
T853 /workspace/coverage/default/7.lc_ctrl_alert_test.981959611 Aug 19 05:59:00 PM PDT 24 Aug 19 05:59:01 PM PDT 24 16313808 ps
T854 /workspace/coverage/default/18.lc_ctrl_smoke.378134587 Aug 19 05:59:58 PM PDT 24 Aug 19 06:00:04 PM PDT 24 204781668 ps
T855 /workspace/coverage/default/4.lc_ctrl_jtag_access.1090289831 Aug 19 05:58:14 PM PDT 24 Aug 19 05:58:18 PM PDT 24 96357683 ps
T856 /workspace/coverage/default/2.lc_ctrl_smoke.2876706604 Aug 19 05:57:41 PM PDT 24 Aug 19 05:57:43 PM PDT 24 53529983 ps
T85 /workspace/coverage/default/13.lc_ctrl_smoke.3286912783 Aug 19 05:59:33 PM PDT 24 Aug 19 05:59:35 PM PDT 24 26252827 ps
T857 /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2391214527 Aug 19 05:58:33 PM PDT 24 Aug 19 05:58:35 PM PDT 24 110423224 ps
T858 /workspace/coverage/default/39.lc_ctrl_sec_mubi.312356604 Aug 19 06:01:24 PM PDT 24 Aug 19 06:01:40 PM PDT 24 2623173019 ps
T859 /workspace/coverage/default/16.lc_ctrl_state_failure.3201143194 Aug 19 05:59:44 PM PDT 24 Aug 19 06:00:11 PM PDT 24 1174456381 ps
T860 /workspace/coverage/default/24.lc_ctrl_jtag_access.3773101699 Aug 19 06:00:21 PM PDT 24 Aug 19 06:00:27 PM PDT 24 430798214 ps
T861 /workspace/coverage/default/47.lc_ctrl_prog_failure.3237962356 Aug 19 06:01:39 PM PDT 24 Aug 19 06:01:43 PM PDT 24 308584073 ps
T862 /workspace/coverage/default/43.lc_ctrl_smoke.3884715921 Aug 19 06:01:28 PM PDT 24 Aug 19 06:01:30 PM PDT 24 125567304 ps
T863 /workspace/coverage/default/18.lc_ctrl_jtag_access.3434463715 Aug 19 06:00:14 PM PDT 24 Aug 19 06:00:31 PM PDT 24 4591801478 ps
T864 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2678082494 Aug 19 05:57:39 PM PDT 24 Aug 19 05:57:40 PM PDT 24 32693109 ps
T865 /workspace/coverage/default/33.lc_ctrl_sec_mubi.1372352150 Aug 19 06:00:58 PM PDT 24 Aug 19 06:01:14 PM PDT 24 585495508 ps
T866 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2219038879 Aug 19 05:59:13 PM PDT 24 Aug 19 05:59:19 PM PDT 24 1149177368 ps
T165 /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3542023324 Aug 19 06:00:51 PM PDT 24 Aug 19 06:02:31 PM PDT 24 12328878385 ps
T867 /workspace/coverage/default/32.lc_ctrl_jtag_access.2396772199 Aug 19 06:00:56 PM PDT 24 Aug 19 06:01:01 PM PDT 24 1405617726 ps
T868 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.311086591 Aug 19 05:57:29 PM PDT 24 Aug 19 05:57:42 PM PDT 24 3412319992 ps
T869 /workspace/coverage/default/5.lc_ctrl_smoke.2959363281 Aug 19 05:58:14 PM PDT 24 Aug 19 05:58:17 PM PDT 24 109304016 ps
T870 /workspace/coverage/default/4.lc_ctrl_sec_mubi.1249351233 Aug 19 05:58:16 PM PDT 24 Aug 19 05:58:34 PM PDT 24 3226904468 ps
T871 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3919324478 Aug 19 06:00:12 PM PDT 24 Aug 19 06:00:27 PM PDT 24 569742938 ps
T872 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.820246720 Aug 19 05:58:16 PM PDT 24 Aug 19 05:58:39 PM PDT 24 2832997880 ps
T873 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2089782569 Aug 19 05:57:44 PM PDT 24 Aug 19 05:58:03 PM PDT 24 5575091963 ps
T119 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1424547785 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:41 PM PDT 24 272983082 ps
T111 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1920690661 Aug 19 05:10:58 PM PDT 24 Aug 19 05:11:01 PM PDT 24 71162319 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.304346854 Aug 19 05:10:18 PM PDT 24 Aug 19 05:10:19 PM PDT 24 19503386 ps
T112 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.896355334 Aug 19 05:10:43 PM PDT 24 Aug 19 05:10:45 PM PDT 24 102281744 ps
T113 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1386097307 Aug 19 05:10:51 PM PDT 24 Aug 19 05:10:53 PM PDT 24 126916242 ps
T189 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1292586724 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:46 PM PDT 24 17195910 ps
T145 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.470211042 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:41 PM PDT 24 63957954 ps
T141 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2542211291 Aug 19 05:10:56 PM PDT 24 Aug 19 05:10:58 PM PDT 24 81423553 ps
T152 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3765648863 Aug 19 05:10:55 PM PDT 24 Aug 19 05:10:56 PM PDT 24 35541959 ps
T142 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2766255307 Aug 19 05:10:34 PM PDT 24 Aug 19 05:10:36 PM PDT 24 65835012 ps
T118 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4000232655 Aug 19 05:10:53 PM PDT 24 Aug 19 05:10:55 PM PDT 24 25265666 ps
T176 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2737726127 Aug 19 05:10:48 PM PDT 24 Aug 19 05:10:49 PM PDT 24 31886998 ps
T874 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2264786941 Aug 19 05:10:51 PM PDT 24 Aug 19 05:10:52 PM PDT 24 32660202 ps
T115 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1257490846 Aug 19 05:10:28 PM PDT 24 Aug 19 05:10:33 PM PDT 24 257445408 ps
T153 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3060600044 Aug 19 05:10:57 PM PDT 24 Aug 19 05:10:59 PM PDT 24 77123945 ps
T116 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3511080434 Aug 19 05:10:33 PM PDT 24 Aug 19 05:10:34 PM PDT 24 88375381 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.356023189 Aug 19 05:10:21 PM PDT 24 Aug 19 05:10:27 PM PDT 24 225869331 ps
T875 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3359523864 Aug 19 05:10:35 PM PDT 24 Aug 19 05:10:36 PM PDT 24 12738254 ps
T190 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2994797077 Aug 19 05:10:14 PM PDT 24 Aug 19 05:10:15 PM PDT 24 76619105 ps
T199 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4254133399 Aug 19 05:10:34 PM PDT 24 Aug 19 05:10:59 PM PDT 24 12192349349 ps
T876 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.869465590 Aug 19 05:10:29 PM PDT 24 Aug 19 05:10:38 PM PDT 24 1418448698 ps
T117 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4212189814 Aug 19 05:10:29 PM PDT 24 Aug 19 05:10:32 PM PDT 24 80244852 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.917364334 Aug 19 05:10:38 PM PDT 24 Aug 19 05:10:46 PM PDT 24 304941546 ps
T878 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3559031157 Aug 19 05:10:33 PM PDT 24 Aug 19 05:10:36 PM PDT 24 69748655 ps
T139 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2012358205 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:52 PM PDT 24 62308329 ps
T191 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.659722669 Aug 19 05:10:40 PM PDT 24 Aug 19 05:10:42 PM PDT 24 36966606 ps
T192 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.626578228 Aug 19 05:10:44 PM PDT 24 Aug 19 05:10:46 PM PDT 24 148295422 ps
T143 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2105011727 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:54 PM PDT 24 1104172417 ps
T193 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2031234363 Aug 19 05:10:32 PM PDT 24 Aug 19 05:10:33 PM PDT 24 136931556 ps
T194 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2479219075 Aug 19 05:10:49 PM PDT 24 Aug 19 05:10:50 PM PDT 24 94138799 ps
T195 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.587944657 Aug 19 05:10:46 PM PDT 24 Aug 19 05:10:48 PM PDT 24 44698290 ps
T196 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.486259657 Aug 19 05:10:54 PM PDT 24 Aug 19 05:10:55 PM PDT 24 41857738 ps
T133 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2261907255 Aug 19 05:10:44 PM PDT 24 Aug 19 05:10:46 PM PDT 24 33733014 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1812853062 Aug 19 05:10:30 PM PDT 24 Aug 19 05:10:31 PM PDT 24 83152470 ps
T128 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1214032635 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:52 PM PDT 24 323728063 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.515030228 Aug 19 05:10:23 PM PDT 24 Aug 19 05:10:24 PM PDT 24 52647065 ps
T125 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.545176544 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:46 PM PDT 24 73317383 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3599051006 Aug 19 05:10:40 PM PDT 24 Aug 19 05:10:45 PM PDT 24 614828904 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1397007763 Aug 19 05:10:38 PM PDT 24 Aug 19 05:10:39 PM PDT 24 145696583 ps
T177 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4003978150 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:47 PM PDT 24 18208386 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3023012323 Aug 19 05:10:43 PM PDT 24 Aug 19 05:10:45 PM PDT 24 34569430 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.898596526 Aug 19 05:10:40 PM PDT 24 Aug 19 05:10:41 PM PDT 24 30409757 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.693084916 Aug 19 05:10:42 PM PDT 24 Aug 19 05:10:54 PM PDT 24 915136405 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1947999299 Aug 19 05:10:23 PM PDT 24 Aug 19 05:10:27 PM PDT 24 6360491143 ps
T887 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3090348845 Aug 19 05:10:36 PM PDT 24 Aug 19 05:10:44 PM PDT 24 655419427 ps
T888 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4016019164 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:47 PM PDT 24 48744133 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1158900729 Aug 19 05:10:46 PM PDT 24 Aug 19 05:10:47 PM PDT 24 29066785 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2947083829 Aug 19 05:10:36 PM PDT 24 Aug 19 05:10:37 PM PDT 24 64477605 ps
T186 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1396147092 Aug 19 05:10:29 PM PDT 24 Aug 19 05:10:31 PM PDT 24 176907111 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3421556030 Aug 19 05:10:41 PM PDT 24 Aug 19 05:10:44 PM PDT 24 230896492 ps
T892 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2605673320 Aug 19 05:10:35 PM PDT 24 Aug 19 05:10:37 PM PDT 24 95761210 ps
T120 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.904991544 Aug 19 05:10:46 PM PDT 24 Aug 19 05:10:48 PM PDT 24 64640499 ps
T893 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.679246139 Aug 19 05:10:51 PM PDT 24 Aug 19 05:10:55 PM PDT 24 826176544 ps
T121 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.863645743 Aug 19 05:10:48 PM PDT 24 Aug 19 05:10:51 PM PDT 24 87082098 ps
T206 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.671269424 Aug 19 05:10:41 PM PDT 24 Aug 19 05:10:43 PM PDT 24 61837984 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2026334073 Aug 19 05:10:32 PM PDT 24 Aug 19 05:10:35 PM PDT 24 128983897 ps
T135 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2489199913 Aug 19 05:10:35 PM PDT 24 Aug 19 05:10:39 PM PDT 24 620032624 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2177735865 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:41 PM PDT 24 81721866 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3855444805 Aug 19 05:10:27 PM PDT 24 Aug 19 05:10:28 PM PDT 24 117321908 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.967917341 Aug 19 05:10:37 PM PDT 24 Aug 19 05:10:39 PM PDT 24 36397048 ps
T178 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1745636032 Aug 19 05:10:27 PM PDT 24 Aug 19 05:10:28 PM PDT 24 24969135 ps
T179 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1185877887 Aug 19 05:10:22 PM PDT 24 Aug 19 05:10:23 PM PDT 24 54096591 ps
T130 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1439765113 Aug 19 05:10:29 PM PDT 24 Aug 19 05:10:31 PM PDT 24 57495247 ps
T897 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3550268971 Aug 19 05:10:48 PM PDT 24 Aug 19 05:10:50 PM PDT 24 140353993 ps
T898 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1232275105 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:40 PM PDT 24 186467705 ps
T899 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1399114169 Aug 19 05:10:49 PM PDT 24 Aug 19 05:10:51 PM PDT 24 226304193 ps
T900 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.850174546 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:52 PM PDT 24 25295678 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3051969762 Aug 19 05:10:13 PM PDT 24 Aug 19 05:10:15 PM PDT 24 18587629 ps
T902 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1233535142 Aug 19 05:10:31 PM PDT 24 Aug 19 05:10:33 PM PDT 24 130351323 ps
T903 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.566957248 Aug 19 05:10:42 PM PDT 24 Aug 19 05:10:43 PM PDT 24 348475920 ps
T904 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2155958491 Aug 19 05:10:44 PM PDT 24 Aug 19 05:10:45 PM PDT 24 15609394 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2376157198 Aug 19 05:10:46 PM PDT 24 Aug 19 05:10:47 PM PDT 24 21710787 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2202750099 Aug 19 05:10:29 PM PDT 24 Aug 19 05:10:31 PM PDT 24 28079421 ps
T126 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.157175624 Aug 19 05:11:01 PM PDT 24 Aug 19 05:11:03 PM PDT 24 118203941 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1283244922 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:48 PM PDT 24 49933455 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3723307045 Aug 19 05:10:17 PM PDT 24 Aug 19 05:10:18 PM PDT 24 288073119 ps
T909 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3729577091 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:52 PM PDT 24 441793080 ps
T910 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1820255648 Aug 19 05:10:21 PM PDT 24 Aug 19 05:10:23 PM PDT 24 27095229 ps
T911 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2146563277 Aug 19 05:11:01 PM PDT 24 Aug 19 05:11:02 PM PDT 24 43930023 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3712267514 Aug 19 05:10:15 PM PDT 24 Aug 19 05:10:21 PM PDT 24 231364084 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4117502439 Aug 19 05:10:33 PM PDT 24 Aug 19 05:10:35 PM PDT 24 48479361 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.122089843 Aug 19 05:10:31 PM PDT 24 Aug 19 05:10:33 PM PDT 24 564920512 ps
T915 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2241035531 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:50 PM PDT 24 2142657511 ps
T916 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1004012332 Aug 19 05:10:44 PM PDT 24 Aug 19 05:10:52 PM PDT 24 296429094 ps
T917 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3735686043 Aug 19 05:10:48 PM PDT 24 Aug 19 05:10:49 PM PDT 24 141755676 ps
T918 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4292850050 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:53 PM PDT 24 182538967 ps
T919 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.736880747 Aug 19 05:10:33 PM PDT 24 Aug 19 05:10:35 PM PDT 24 29946133 ps
T920 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3304286956 Aug 19 05:10:21 PM PDT 24 Aug 19 05:10:23 PM PDT 24 242646566 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4159251728 Aug 19 05:10:35 PM PDT 24 Aug 19 05:10:41 PM PDT 24 451860919 ps
T922 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1591574810 Aug 19 05:10:29 PM PDT 24 Aug 19 05:10:30 PM PDT 24 32465527 ps
T923 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3565144939 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:48 PM PDT 24 17690574 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3511378027 Aug 19 05:10:27 PM PDT 24 Aug 19 05:10:35 PM PDT 24 42219956 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2394872076 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:41 PM PDT 24 114349710 ps
T926 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.773714875 Aug 19 05:10:43 PM PDT 24 Aug 19 05:10:47 PM PDT 24 1098850167 ps
T137 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3431169717 Aug 19 05:10:49 PM PDT 24 Aug 19 05:10:52 PM PDT 24 75401044 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4134911704 Aug 19 05:10:25 PM PDT 24 Aug 19 05:10:27 PM PDT 24 70842860 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1410638768 Aug 19 05:10:14 PM PDT 24 Aug 19 05:10:17 PM PDT 24 492686327 ps
T129 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1882355802 Aug 19 05:10:34 PM PDT 24 Aug 19 05:10:37 PM PDT 24 571708578 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2531526899 Aug 19 05:10:23 PM PDT 24 Aug 19 05:10:24 PM PDT 24 17679647 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.319618936 Aug 19 05:10:20 PM PDT 24 Aug 19 05:10:21 PM PDT 24 167454776 ps
T931 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.684239876 Aug 19 05:10:46 PM PDT 24 Aug 19 05:10:47 PM PDT 24 51188621 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2193719186 Aug 19 05:10:36 PM PDT 24 Aug 19 05:11:08 PM PDT 24 2625817374 ps
T134 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3087348642 Aug 19 05:10:55 PM PDT 24 Aug 19 05:10:58 PM PDT 24 114771446 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4081246195 Aug 19 05:10:42 PM PDT 24 Aug 19 05:10:45 PM PDT 24 269736627 ps
T934 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1348884778 Aug 19 05:10:22 PM PDT 24 Aug 19 05:10:23 PM PDT 24 138223600 ps
T935 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.484463927 Aug 19 05:10:40 PM PDT 24 Aug 19 05:10:41 PM PDT 24 16951748 ps
T936 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1058624081 Aug 19 05:10:43 PM PDT 24 Aug 19 05:10:44 PM PDT 24 29924922 ps
T138 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2747359083 Aug 19 05:10:53 PM PDT 24 Aug 19 05:10:56 PM PDT 24 261883630 ps
T127 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.787469939 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:47 PM PDT 24 47407106 ps
T937 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3585789665 Aug 19 05:10:46 PM PDT 24 Aug 19 05:10:49 PM PDT 24 179173523 ps
T938 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2407173118 Aug 19 05:10:51 PM PDT 24 Aug 19 05:10:52 PM PDT 24 49431649 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2910369071 Aug 19 05:10:46 PM PDT 24 Aug 19 05:10:49 PM PDT 24 98717932 ps
T940 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3968045801 Aug 19 05:10:35 PM PDT 24 Aug 19 05:10:38 PM PDT 24 45399536 ps
T136 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2163206663 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:53 PM PDT 24 54777291 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4197323163 Aug 19 05:10:23 PM PDT 24 Aug 19 05:10:24 PM PDT 24 26529509 ps
T942 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1478389364 Aug 19 05:10:36 PM PDT 24 Aug 19 05:10:48 PM PDT 24 482923254 ps
T943 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.329812102 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:49 PM PDT 24 75327539 ps
T944 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2625878936 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:49 PM PDT 24 55143174 ps
T945 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1428092800 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:48 PM PDT 24 15561660 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1441879215 Aug 19 05:10:18 PM PDT 24 Aug 19 05:10:20 PM PDT 24 52633097 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2446404900 Aug 19 05:10:15 PM PDT 24 Aug 19 05:10:18 PM PDT 24 138773455 ps
T948 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2381443092 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:52 PM PDT 24 25138500 ps
T949 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.731625480 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:48 PM PDT 24 456987073 ps
T180 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1520825253 Aug 19 05:10:15 PM PDT 24 Aug 19 05:10:16 PM PDT 24 37489843 ps
T950 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2661489152 Aug 19 05:10:33 PM PDT 24 Aug 19 05:10:35 PM PDT 24 21837809 ps
T951 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4277437177 Aug 19 05:10:30 PM PDT 24 Aug 19 05:10:32 PM PDT 24 32298479 ps
T952 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2481130608 Aug 19 05:10:15 PM PDT 24 Aug 19 05:10:16 PM PDT 24 64686072 ps
T953 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2381104659 Aug 19 05:10:37 PM PDT 24 Aug 19 05:10:39 PM PDT 24 66822807 ps
T954 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3024671291 Aug 19 05:10:32 PM PDT 24 Aug 19 05:10:33 PM PDT 24 271035077 ps
T181 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2329610543 Aug 19 05:10:21 PM PDT 24 Aug 19 05:10:22 PM PDT 24 71488046 ps
T955 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.889634332 Aug 19 05:10:15 PM PDT 24 Aug 19 05:10:17 PM PDT 24 1201538725 ps
T956 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4150131724 Aug 19 05:10:52 PM PDT 24 Aug 19 05:10:54 PM PDT 24 161887223 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2703926073 Aug 19 05:10:36 PM PDT 24 Aug 19 05:10:38 PM PDT 24 34370868 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.364551078 Aug 19 05:10:53 PM PDT 24 Aug 19 05:11:09 PM PDT 24 2517928342 ps
T959 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3103478079 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:40 PM PDT 24 19917447 ps
T960 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1376623426 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:51 PM PDT 24 185054409 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4122672609 Aug 19 05:10:47 PM PDT 24 Aug 19 05:11:10 PM PDT 24 1921355388 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3434480643 Aug 19 05:10:28 PM PDT 24 Aug 19 05:10:40 PM PDT 24 1815380832 ps
T963 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.110594915 Aug 19 05:10:28 PM PDT 24 Aug 19 05:10:29 PM PDT 24 79906554 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.598867978 Aug 19 05:10:12 PM PDT 24 Aug 19 05:10:23 PM PDT 24 17104895105 ps
T965 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3128015079 Aug 19 05:10:36 PM PDT 24 Aug 19 05:10:38 PM PDT 24 51448879 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.612362704 Aug 19 05:10:40 PM PDT 24 Aug 19 05:10:41 PM PDT 24 35665267 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2950042020 Aug 19 05:10:32 PM PDT 24 Aug 19 05:10:34 PM PDT 24 118842816 ps
T968 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1216287976 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:54 PM PDT 24 1031351952 ps
T132 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2931531386 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:53 PM PDT 24 126405368 ps
T969 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3730325276 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:51 PM PDT 24 65778773 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4086070288 Aug 19 05:10:22 PM PDT 24 Aug 19 05:10:30 PM PDT 24 3059962518 ps
T971 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3314351734 Aug 19 05:10:08 PM PDT 24 Aug 19 05:10:27 PM PDT 24 699891476 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1823366253 Aug 19 05:10:34 PM PDT 24 Aug 19 05:10:36 PM PDT 24 164289012 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1853726601 Aug 19 05:10:32 PM PDT 24 Aug 19 05:10:35 PM PDT 24 112457680 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.681195343 Aug 19 05:10:31 PM PDT 24 Aug 19 05:10:32 PM PDT 24 63984539 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4006568283 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:40 PM PDT 24 102675804 ps
T182 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.18622052 Aug 19 05:10:30 PM PDT 24 Aug 19 05:10:31 PM PDT 24 65985906 ps
T183 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2482170396 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:48 PM PDT 24 15064555 ps
T184 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3770941871 Aug 19 05:10:48 PM PDT 24 Aug 19 05:10:48 PM PDT 24 46222509 ps
T976 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.289193285 Aug 19 05:10:33 PM PDT 24 Aug 19 05:10:34 PM PDT 24 53270208 ps
T977 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3847669147 Aug 19 05:10:45 PM PDT 24 Aug 19 05:10:47 PM PDT 24 25363780 ps
T978 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3829162713 Aug 19 05:10:36 PM PDT 24 Aug 19 05:10:37 PM PDT 24 216628845 ps
T979 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1678574255 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:51 PM PDT 24 159462528 ps
T185 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2639359949 Aug 19 05:10:59 PM PDT 24 Aug 19 05:11:01 PM PDT 24 26424535 ps
T980 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.845592130 Aug 19 05:10:50 PM PDT 24 Aug 19 05:10:51 PM PDT 24 15948851 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1087778918 Aug 19 05:10:28 PM PDT 24 Aug 19 05:10:30 PM PDT 24 129367232 ps
T982 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3232993271 Aug 19 05:10:31 PM PDT 24 Aug 19 05:10:32 PM PDT 24 26094796 ps
T983 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4125294437 Aug 19 05:10:35 PM PDT 24 Aug 19 05:10:37 PM PDT 24 167261857 ps
T984 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2517540658 Aug 19 05:10:49 PM PDT 24 Aug 19 05:10:52 PM PDT 24 126595774 ps
T985 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3299961335 Aug 19 05:10:15 PM PDT 24 Aug 19 05:10:19 PM PDT 24 742727837 ps
T986 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3969836044 Aug 19 05:10:39 PM PDT 24 Aug 19 05:10:40 PM PDT 24 66287090 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2897492644 Aug 19 05:10:48 PM PDT 24 Aug 19 05:10:49 PM PDT 24 206600095 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.195974779 Aug 19 05:10:21 PM PDT 24 Aug 19 05:10:22 PM PDT 24 110214370 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.797367180 Aug 19 05:10:37 PM PDT 24 Aug 19 05:10:41 PM PDT 24 165965252 ps
T990 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.62416157 Aug 19 05:10:42 PM PDT 24 Aug 19 05:10:45 PM PDT 24 87070848 ps
T991 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.10088990 Aug 19 05:10:37 PM PDT 24 Aug 19 05:10:39 PM PDT 24 1335265116 ps
T992 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1075299547 Aug 19 05:11:00 PM PDT 24 Aug 19 05:11:02 PM PDT 24 28021823 ps
T187 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.886705411 Aug 19 05:10:38 PM PDT 24 Aug 19 05:10:39 PM PDT 24 53202145 ps
T993 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946174004 Aug 19 05:10:37 PM PDT 24 Aug 19 05:10:40 PM PDT 24 101431410 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1018436541 Aug 19 05:10:38 PM PDT 24 Aug 19 05:10:48 PM PDT 24 425485620 ps
T995 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.494307231 Aug 19 05:10:19 PM PDT 24 Aug 19 05:10:23 PM PDT 24 400591050 ps
T996 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.749157506 Aug 19 05:10:43 PM PDT 24 Aug 19 05:10:45 PM PDT 24 127803811 ps
T188 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.228247271 Aug 19 05:10:35 PM PDT 24 Aug 19 05:10:38 PM PDT 24 169525972 ps
T140 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2561995488 Aug 19 05:10:22 PM PDT 24 Aug 19 05:10:26 PM PDT 24 108863424 ps
T122 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2609805450 Aug 19 05:10:47 PM PDT 24 Aug 19 05:10:52 PM PDT 24 520084345 ps
T997 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.477236762 Aug 19 05:10:11 PM PDT 24 Aug 19 05:10:13 PM PDT 24 47930729 ps
T998 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3405291228 Aug 19 05:10:31 PM PDT 24 Aug 19 05:10:33 PM PDT 24 56298412 ps
T123 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.100816337 Aug 19 05:10:33 PM PDT 24 Aug 19 05:10:37 PM PDT 24 116795357 ps
T999 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1779988444 Aug 19 05:10:40 PM PDT 24 Aug 19 05:10:41 PM PDT 24 21230364 ps

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2450249949
Short name T12
Test name
Test status
Simulation time 650962561 ps
CPU time 8.43 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 226088 kb
Host smart-5d047e87-01f3-4383-baac-82b5d60868a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450249949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2450249949
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2125147585
Short name T6
Test name
Test status
Simulation time 6380205381 ps
CPU time 60 seconds
Started Aug 19 06:01:06 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 226260 kb
Host smart-24c71706-14d0-48cb-94a5-a33ddda1e3b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2125147585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2125147585
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1959435833
Short name T10
Test name
Test status
Simulation time 613343690 ps
CPU time 18.5 seconds
Started Aug 19 06:01:30 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 219040 kb
Host smart-7f0840bf-87ba-44ec-85b3-4061b26f4be7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959435833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1959435833
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3468712791
Short name T42
Test name
Test status
Simulation time 19770529135 ps
CPU time 373.31 seconds
Started Aug 19 05:59:46 PM PDT 24
Finished Aug 19 06:05:59 PM PDT 24
Peak memory 283408 kb
Host smart-3d142311-1887-43b2-b6e8-4952030596fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468712791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3468712791
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1386097307
Short name T113
Test name
Test status
Simulation time 126916242 ps
CPU time 1.88 seconds
Started Aug 19 05:10:51 PM PDT 24
Finished Aug 19 05:10:53 PM PDT 24
Peak memory 221956 kb
Host smart-32c22639-5b3a-4125-8047-073918d15e90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386097307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1386097307
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.198303702
Short name T53
Test name
Test status
Simulation time 1740671304 ps
CPU time 8.19 seconds
Started Aug 19 06:01:17 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 218244 kb
Host smart-ded15340-4747-4351-a7ba-0eb3c322ac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198303702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.198303702
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2442592002
Short name T28
Test name
Test status
Simulation time 15974147387 ps
CPU time 76.09 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:59:32 PM PDT 24
Peak memory 283688 kb
Host smart-70ba457e-36fe-446b-82eb-94fb3971b286
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442592002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2442592002
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3189523418
Short name T55
Test name
Test status
Simulation time 224376553 ps
CPU time 32.96 seconds
Started Aug 19 05:57:39 PM PDT 24
Finished Aug 19 05:58:13 PM PDT 24
Peak memory 269424 kb
Host smart-8ef0e941-3f3f-48b7-89ba-9428ed87325f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189523418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3189523418
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2846098349
Short name T3
Test name
Test status
Simulation time 1921778112 ps
CPU time 19.3 seconds
Started Aug 19 06:01:41 PM PDT 24
Finished Aug 19 06:02:00 PM PDT 24
Peak memory 217340 kb
Host smart-6b0e0417-48af-4fff-98b1-28c15402d40c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846098349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2846098349
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1257490846
Short name T115
Test name
Test status
Simulation time 257445408 ps
CPU time 4.91 seconds
Started Aug 19 05:10:28 PM PDT 24
Finished Aug 19 05:10:33 PM PDT 24
Peak memory 218228 kb
Host smart-21301a6b-245b-433b-897a-802533c9b322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257490846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1257490846
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.8271524
Short name T61
Test name
Test status
Simulation time 3411832776 ps
CPU time 82.69 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:02:37 PM PDT 24
Peak memory 251120 kb
Host smart-82703543-4eff-4f35-8057-add58f1d2f0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8271524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.lc_ctrl_stress_all.8271524
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2991192302
Short name T110
Test name
Test status
Simulation time 1618618771 ps
CPU time 11.47 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:01:03 PM PDT 24
Peak memory 226048 kb
Host smart-aaded41b-493c-45b1-9ca4-4f74714ef487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991192302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2991192302
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2019635164
Short name T19
Test name
Test status
Simulation time 302665247 ps
CPU time 10.46 seconds
Started Aug 19 05:57:31 PM PDT 24
Finished Aug 19 05:57:42 PM PDT 24
Peak memory 218248 kb
Host smart-a7b2713c-e05d-4775-b162-a20d0eb3d1e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019635164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
019635164
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3896632239
Short name T89
Test name
Test status
Simulation time 60806650 ps
CPU time 0.88 seconds
Started Aug 19 05:59:46 PM PDT 24
Finished Aug 19 05:59:47 PM PDT 24
Peak memory 208872 kb
Host smart-4a5dfeb7-9a7f-46b2-b04d-898856faf9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896632239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3896632239
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1831637860
Short name T88
Test name
Test status
Simulation time 3373788706 ps
CPU time 92.78 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:02:48 PM PDT 24
Peak memory 275684 kb
Host smart-6c8b109f-fc3a-4f02-8908-af4aaede448d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831637860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1831637860
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2737726127
Short name T176
Test name
Test status
Simulation time 31886998 ps
CPU time 0.95 seconds
Started Aug 19 05:10:48 PM PDT 24
Finished Aug 19 05:10:49 PM PDT 24
Peak memory 209912 kb
Host smart-10d7fbc8-b871-442e-9c4d-c7c4d33e0389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737726127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2737726127
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2020038199
Short name T15
Test name
Test status
Simulation time 418982367 ps
CPU time 12.08 seconds
Started Aug 19 05:57:41 PM PDT 24
Finished Aug 19 05:57:53 PM PDT 24
Peak memory 226128 kb
Host smart-6367e43e-74de-492a-a542-051c8c296b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020038199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2020038199
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2766255307
Short name T142
Test name
Test status
Simulation time 65835012 ps
CPU time 2.34 seconds
Started Aug 19 05:10:34 PM PDT 24
Finished Aug 19 05:10:36 PM PDT 24
Peak memory 209972 kb
Host smart-db68819a-f8d6-432f-802b-987a3c3af254
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766255307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2766255307
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3087348642
Short name T134
Test name
Test status
Simulation time 114771446 ps
CPU time 2.86 seconds
Started Aug 19 05:10:55 PM PDT 24
Finished Aug 19 05:10:58 PM PDT 24
Peak memory 222732 kb
Host smart-e175bf25-c825-4c89-97d3-48805ddf7c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087348642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3087348642
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1773538904
Short name T46
Test name
Test status
Simulation time 64539687448 ps
CPU time 158.6 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 06:01:40 PM PDT 24
Peak memory 270436 kb
Host smart-0c4c3249-b836-444a-a190-504ee3273128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773538904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1773538904
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4212189814
Short name T117
Test name
Test status
Simulation time 80244852 ps
CPU time 2.79 seconds
Started Aug 19 05:10:29 PM PDT 24
Finished Aug 19 05:10:32 PM PDT 24
Peak memory 222920 kb
Host smart-c706141a-39ea-4715-85a4-de04c463e0fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212189814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4212189814
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3378704114
Short name T25
Test name
Test status
Simulation time 1467357668 ps
CPU time 29.68 seconds
Started Aug 19 06:00:38 PM PDT 24
Finished Aug 19 06:01:08 PM PDT 24
Peak memory 246992 kb
Host smart-576327f3-8470-4047-b441-dd5f28bcedd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378704114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3378704114
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2163206663
Short name T136
Test name
Test status
Simulation time 54777291 ps
CPU time 2.62 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:53 PM PDT 24
Peak memory 218148 kb
Host smart-398c3c0b-4bc5-470d-bd3e-9716080ff5be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163206663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2163206663
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2079303554
Short name T350
Test name
Test status
Simulation time 4727816613 ps
CPU time 8.86 seconds
Started Aug 19 06:00:29 PM PDT 24
Finished Aug 19 06:00:38 PM PDT 24
Peak memory 218404 kb
Host smart-e3859b0b-8645-4357-97f8-95044ca2ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079303554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2079303554
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2092927362
Short name T18
Test name
Test status
Simulation time 46240910 ps
CPU time 0.89 seconds
Started Aug 19 05:59:36 PM PDT 24
Finished Aug 19 05:59:37 PM PDT 24
Peak memory 211956 kb
Host smart-d33463cb-6632-4560-ad98-17d7db9a656d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092927362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2092927362
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4292850050
Short name T918
Test name
Test status
Simulation time 182538967 ps
CPU time 2.96 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:53 PM PDT 24
Peak memory 218156 kb
Host smart-42691d24-85b1-4859-8461-b6d8618afcf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292850050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4292850050
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1920690661
Short name T111
Test name
Test status
Simulation time 71162319 ps
CPU time 2.94 seconds
Started Aug 19 05:10:58 PM PDT 24
Finished Aug 19 05:11:01 PM PDT 24
Peak memory 218232 kb
Host smart-8e156dd9-f3a9-4d54-965e-610f488ff9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920690661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1920690661
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3431169717
Short name T137
Test name
Test status
Simulation time 75401044 ps
CPU time 2.72 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 222844 kb
Host smart-0a08f654-5da5-45b4-8b2b-374c7a0f4e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431169717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3431169717
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2931531386
Short name T132
Test name
Test status
Simulation time 126405368 ps
CPU time 3.17 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:53 PM PDT 24
Peak memory 223100 kb
Host smart-5a7bad78-d9ed-4924-b13d-76d75a1e8849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931531386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2931531386
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1882355802
Short name T129
Test name
Test status
Simulation time 571708578 ps
CPU time 3.16 seconds
Started Aug 19 05:10:34 PM PDT 24
Finished Aug 19 05:10:37 PM PDT 24
Peak memory 222900 kb
Host smart-8f2e7480-3be8-4338-939b-18c582667184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882355802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1882355802
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.4218260619
Short name T202
Test name
Test status
Simulation time 12914814 ps
CPU time 1 seconds
Started Aug 19 05:58:07 PM PDT 24
Finished Aug 19 05:58:08 PM PDT 24
Peak memory 208756 kb
Host smart-9aad53c4-06de-457e-b54d-508c23876c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218260619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.4218260619
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3477724618
Short name T201
Test name
Test status
Simulation time 13468624 ps
CPU time 0.79 seconds
Started Aug 19 05:58:24 PM PDT 24
Finished Aug 19 05:58:25 PM PDT 24
Peak memory 208580 kb
Host smart-3898d219-5eba-471b-bc97-6b5e95975338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477724618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3477724618
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3032359942
Short name T203
Test name
Test status
Simulation time 11195441 ps
CPU time 0.95 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:12 PM PDT 24
Peak memory 208788 kb
Host smart-9451dbac-9b4c-442c-8bd5-29195304ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032359942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3032359942
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2609805450
Short name T122
Test name
Test status
Simulation time 520084345 ps
CPU time 4.08 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 218160 kb
Host smart-43000878-56a0-49a4-9d8b-84b1fb142111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609805450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2609805450
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2561995488
Short name T140
Test name
Test status
Simulation time 108863424 ps
CPU time 3.66 seconds
Started Aug 19 05:10:22 PM PDT 24
Finished Aug 19 05:10:26 PM PDT 24
Peak memory 218352 kb
Host smart-1893599c-2dfc-4c2e-b550-9ab027ced1db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561995488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2561995488
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1439765113
Short name T130
Test name
Test status
Simulation time 57495247 ps
CPU time 2.37 seconds
Started Aug 19 05:10:29 PM PDT 24
Finished Aug 19 05:10:31 PM PDT 24
Peak memory 218244 kb
Host smart-e655fc4e-c3d9-4193-a0cd-63fbbb339647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439765113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1439765113
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2694592254
Short name T48
Test name
Test status
Simulation time 2709228975 ps
CPU time 63.25 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 06:00:36 PM PDT 24
Peak memory 268556 kb
Host smart-f1c7d460-2286-4e6f-83ae-c3ff30cd2e54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2694592254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2694592254
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1587864919
Short name T90
Test name
Test status
Simulation time 201590985 ps
CPU time 3.16 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:17 PM PDT 24
Peak memory 222536 kb
Host smart-9a4edfc6-1fe0-454f-bb48-943498948556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587864919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1587864919
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1520825253
Short name T180
Test name
Test status
Simulation time 37489843 ps
CPU time 1.04 seconds
Started Aug 19 05:10:15 PM PDT 24
Finished Aug 19 05:10:16 PM PDT 24
Peak memory 210048 kb
Host smart-51f2a3f4-5667-4c74-84c2-d6cf356edd27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520825253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1520825253
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3299961335
Short name T985
Test name
Test status
Simulation time 742727837 ps
CPU time 3.32 seconds
Started Aug 19 05:10:15 PM PDT 24
Finished Aug 19 05:10:19 PM PDT 24
Peak memory 209972 kb
Host smart-5c5900cd-1004-4365-98b1-8be87effe360
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299961335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3299961335
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.304346854
Short name T124
Test name
Test status
Simulation time 19503386 ps
CPU time 1.26 seconds
Started Aug 19 05:10:18 PM PDT 24
Finished Aug 19 05:10:19 PM PDT 24
Peak memory 212300 kb
Host smart-43962d00-3111-4c65-8094-54c9f642406a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304346854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.304346854
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4197323163
Short name T941
Test name
Test status
Simulation time 26529509 ps
CPU time 1.07 seconds
Started Aug 19 05:10:23 PM PDT 24
Finished Aug 19 05:10:24 PM PDT 24
Peak memory 220264 kb
Host smart-b2eac0df-b4ed-4d2b-811a-28957b292c82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197323163 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4197323163
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1745636032
Short name T178
Test name
Test status
Simulation time 24969135 ps
CPU time 1.06 seconds
Started Aug 19 05:10:27 PM PDT 24
Finished Aug 19 05:10:28 PM PDT 24
Peak memory 209832 kb
Host smart-b5493164-bb12-4946-a53d-c6c2895de433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745636032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1745636032
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1820255648
Short name T910
Test name
Test status
Simulation time 27095229 ps
CPU time 1.33 seconds
Started Aug 19 05:10:21 PM PDT 24
Finished Aug 19 05:10:23 PM PDT 24
Peak memory 209856 kb
Host smart-cdc5dbfd-882d-48b2-9319-3ea38daa86e1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820255648 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1820255648
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.598867978
Short name T964
Test name
Test status
Simulation time 17104895105 ps
CPU time 11.42 seconds
Started Aug 19 05:10:12 PM PDT 24
Finished Aug 19 05:10:23 PM PDT 24
Peak memory 209956 kb
Host smart-b80fd3d0-94f1-490f-aed4-83d1f1cb1cf1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598867978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.598867978
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3314351734
Short name T971
Test name
Test status
Simulation time 699891476 ps
CPU time 18.62 seconds
Started Aug 19 05:10:08 PM PDT 24
Finished Aug 19 05:10:27 PM PDT 24
Peak memory 209736 kb
Host smart-f07030aa-15b7-4bc1-a5bf-23cf504cc253
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314351734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3314351734
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3712267514
Short name T912
Test name
Test status
Simulation time 231364084 ps
CPU time 5.57 seconds
Started Aug 19 05:10:15 PM PDT 24
Finished Aug 19 05:10:21 PM PDT 24
Peak memory 211560 kb
Host smart-4173b1f1-d3a4-403e-8455-f25e2b720de0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712267514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3712267514
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2446404900
Short name T947
Test name
Test status
Simulation time 138773455 ps
CPU time 3.68 seconds
Started Aug 19 05:10:15 PM PDT 24
Finished Aug 19 05:10:18 PM PDT 24
Peak memory 219732 kb
Host smart-9ea9fb65-575b-4604-a97c-1713d0117140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244640
4900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2446404900
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3723307045
Short name T908
Test name
Test status
Simulation time 288073119 ps
CPU time 1.49 seconds
Started Aug 19 05:10:17 PM PDT 24
Finished Aug 19 05:10:18 PM PDT 24
Peak memory 209804 kb
Host smart-f84fa956-792a-411f-9c7d-221b36213b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723307045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3723307045
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2994797077
Short name T190
Test name
Test status
Simulation time 76619105 ps
CPU time 1.25 seconds
Started Aug 19 05:10:14 PM PDT 24
Finished Aug 19 05:10:15 PM PDT 24
Peak memory 212060 kb
Host smart-e15e72ef-a17e-4f9d-bca6-5d6e81966a8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994797077 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2994797077
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4277437177
Short name T951
Test name
Test status
Simulation time 32298479 ps
CPU time 1.23 seconds
Started Aug 19 05:10:30 PM PDT 24
Finished Aug 19 05:10:32 PM PDT 24
Peak memory 210112 kb
Host smart-0c272eb9-40b1-498e-81a7-8346fce80ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277437177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4277437177
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1410638768
Short name T928
Test name
Test status
Simulation time 492686327 ps
CPU time 3.3 seconds
Started Aug 19 05:10:14 PM PDT 24
Finished Aug 19 05:10:17 PM PDT 24
Peak memory 218284 kb
Host smart-a5be311d-70fa-48a0-b958-ada57acfad26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410638768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1410638768
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.100816337
Short name T123
Test name
Test status
Simulation time 116795357 ps
CPU time 3.12 seconds
Started Aug 19 05:10:33 PM PDT 24
Finished Aug 19 05:10:37 PM PDT 24
Peak memory 222920 kb
Host smart-286b590e-ccb8-4ec3-8c6e-dfda7e4d6263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100816337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.100816337
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.886705411
Short name T187
Test name
Test status
Simulation time 53202145 ps
CPU time 1.27 seconds
Started Aug 19 05:10:38 PM PDT 24
Finished Aug 19 05:10:39 PM PDT 24
Peak memory 209984 kb
Host smart-4266bea6-aaab-435c-a986-668c80fb6103
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886705411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.886705411
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3559031157
Short name T878
Test name
Test status
Simulation time 69748655 ps
CPU time 2.74 seconds
Started Aug 19 05:10:33 PM PDT 24
Finished Aug 19 05:10:36 PM PDT 24
Peak memory 209928 kb
Host smart-48affbb2-d6eb-40b2-80c9-1055e57ac720
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559031157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3559031157
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2481130608
Short name T952
Test name
Test status
Simulation time 64686072 ps
CPU time 0.91 seconds
Started Aug 19 05:10:15 PM PDT 24
Finished Aug 19 05:10:16 PM PDT 24
Peak memory 210296 kb
Host smart-eaeae64c-15fa-493d-bbfe-ea350cf51429
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481130608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2481130608
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2661489152
Short name T950
Test name
Test status
Simulation time 21837809 ps
CPU time 1.28 seconds
Started Aug 19 05:10:33 PM PDT 24
Finished Aug 19 05:10:35 PM PDT 24
Peak memory 218176 kb
Host smart-45865db7-930d-40bf-a673-9d1da8d894ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661489152 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2661489152
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1185877887
Short name T179
Test name
Test status
Simulation time 54096591 ps
CPU time 0.81 seconds
Started Aug 19 05:10:22 PM PDT 24
Finished Aug 19 05:10:23 PM PDT 24
Peak memory 209736 kb
Host smart-9fbbf767-1b0a-4549-aa31-12cab50022d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185877887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1185877887
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2381104659
Short name T953
Test name
Test status
Simulation time 66822807 ps
CPU time 2.27 seconds
Started Aug 19 05:10:37 PM PDT 24
Finished Aug 19 05:10:39 PM PDT 24
Peak memory 208520 kb
Host smart-a9edd238-bbd6-4c89-8c1f-4ae4f68c4e62
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381104659 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2381104659
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.356023189
Short name T144
Test name
Test status
Simulation time 225869331 ps
CPU time 6.12 seconds
Started Aug 19 05:10:21 PM PDT 24
Finished Aug 19 05:10:27 PM PDT 24
Peak memory 209728 kb
Host smart-fe24674e-aae8-42a5-beb8-65e8af7fa265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356023189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.356023189
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4254133399
Short name T199
Test name
Test status
Simulation time 12192349349 ps
CPU time 25.16 seconds
Started Aug 19 05:10:34 PM PDT 24
Finished Aug 19 05:10:59 PM PDT 24
Peak memory 209860 kb
Host smart-4e27528c-eb85-411c-a197-48a69d76a61e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254133399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4254133399
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.477236762
Short name T997
Test name
Test status
Simulation time 47930729 ps
CPU time 1.31 seconds
Started Aug 19 05:10:11 PM PDT 24
Finished Aug 19 05:10:13 PM PDT 24
Peak memory 211384 kb
Host smart-32e58d5a-fd01-4564-945e-2613db3a51d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477236762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.477236762
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.889634332
Short name T955
Test name
Test status
Simulation time 1201538725 ps
CPU time 2.19 seconds
Started Aug 19 05:10:15 PM PDT 24
Finished Aug 19 05:10:17 PM PDT 24
Peak memory 218368 kb
Host smart-1be774c4-f539-4d87-abc5-6288b295a58d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889634
332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.889634332
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2394872076
Short name T925
Test name
Test status
Simulation time 114349710 ps
CPU time 2.31 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 209724 kb
Host smart-3e90a115-ec34-472a-b1f4-32eb35f94df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394872076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2394872076
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3969836044
Short name T986
Test name
Test status
Simulation time 66287090 ps
CPU time 1.31 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:40 PM PDT 24
Peak memory 209820 kb
Host smart-0665ca0b-c32e-4a1b-b902-a8d8c2fc824f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969836044 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3969836044
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3051969762
Short name T901
Test name
Test status
Simulation time 18587629 ps
CPU time 1.22 seconds
Started Aug 19 05:10:13 PM PDT 24
Finished Aug 19 05:10:15 PM PDT 24
Peak memory 210020 kb
Host smart-87f35876-d24b-4d11-abfe-559b4b663de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051969762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3051969762
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4117502439
Short name T913
Test name
Test status
Simulation time 48479361 ps
CPU time 1.97 seconds
Started Aug 19 05:10:33 PM PDT 24
Finished Aug 19 05:10:35 PM PDT 24
Peak memory 222596 kb
Host smart-46f24f81-383a-4060-8910-d142d2c9b278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117502439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4117502439
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.329812102
Short name T943
Test name
Test status
Simulation time 75327539 ps
CPU time 1.53 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:49 PM PDT 24
Peak memory 220048 kb
Host smart-c1c81b14-caa8-40c7-b68a-8d62ec3da2e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329812102 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.329812102
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2381443092
Short name T948
Test name
Test status
Simulation time 25138500 ps
CPU time 1.41 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 209952 kb
Host smart-018d89b5-adbc-4fac-a0f5-dab0ea573b02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381443092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2381443092
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3968045801
Short name T940
Test name
Test status
Simulation time 45399536 ps
CPU time 3.31 seconds
Started Aug 19 05:10:35 PM PDT 24
Finished Aug 19 05:10:38 PM PDT 24
Peak memory 219188 kb
Host smart-935ec9dc-f28a-4f3a-98b4-f62c3a274ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968045801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3968045801
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4125294437
Short name T983
Test name
Test status
Simulation time 167261857 ps
CPU time 2.08 seconds
Started Aug 19 05:10:35 PM PDT 24
Finished Aug 19 05:10:37 PM PDT 24
Peak memory 222876 kb
Host smart-e72da218-5b20-45db-8b0d-6721e089bf38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125294437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4125294437
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.566957248
Short name T903
Test name
Test status
Simulation time 348475920 ps
CPU time 1.25 seconds
Started Aug 19 05:10:42 PM PDT 24
Finished Aug 19 05:10:43 PM PDT 24
Peak memory 218204 kb
Host smart-7f3a86c1-512b-4f15-87bd-d7f0e342d299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566957248 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.566957248
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3565144939
Short name T923
Test name
Test status
Simulation time 17690574 ps
CPU time 1.15 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 209948 kb
Host smart-a9cb9fdf-31e7-4e9e-9053-b4e0483c1605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565144939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3565144939
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2479219075
Short name T194
Test name
Test status
Simulation time 94138799 ps
CPU time 1.36 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:10:50 PM PDT 24
Peak memory 209916 kb
Host smart-3c7ba243-bf64-482a-94a9-efae0bbcbd7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479219075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2479219075
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2407173118
Short name T938
Test name
Test status
Simulation time 49431649 ps
CPU time 0.98 seconds
Started Aug 19 05:10:51 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 219632 kb
Host smart-be2a6ec5-e09c-4213-8d8c-9cc3f52ec58f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407173118 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2407173118
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1428092800
Short name T945
Test name
Test status
Simulation time 15561660 ps
CPU time 1.03 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 209876 kb
Host smart-20dc1e07-1485-4d93-bb24-01f39873a1b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428092800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1428092800
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1678574255
Short name T979
Test name
Test status
Simulation time 159462528 ps
CPU time 1.38 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:51 PM PDT 24
Peak memory 212008 kb
Host smart-a98fb923-8906-4f03-9b3f-9907e42cb3ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678574255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1678574255
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4150131724
Short name T956
Test name
Test status
Simulation time 161887223 ps
CPU time 2.61 seconds
Started Aug 19 05:10:52 PM PDT 24
Finished Aug 19 05:10:54 PM PDT 24
Peak memory 218144 kb
Host smart-05b0f476-3a51-4853-9c7f-41dc95a44e03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150131724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4150131724
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.850174546
Short name T900
Test name
Test status
Simulation time 25295678 ps
CPU time 1.51 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 222304 kb
Host smart-24e301d4-60c1-44e0-a374-fe245c8ff42c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850174546 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.850174546
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4003978150
Short name T177
Test name
Test status
Simulation time 18208386 ps
CPU time 1.09 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 210024 kb
Host smart-30f91871-bc8d-42d4-8b18-20fc04e7f866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003978150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4003978150
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.845592130
Short name T980
Test name
Test status
Simulation time 15948851 ps
CPU time 1.27 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:51 PM PDT 24
Peak memory 209912 kb
Host smart-7c78f295-4b73-40e3-bd5a-2dff7c1ab984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845592130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.845592130
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3847669147
Short name T977
Test name
Test status
Simulation time 25363780 ps
CPU time 2.03 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 219444 kb
Host smart-0c0b7680-8538-4b24-b593-64de50e46503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847669147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3847669147
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4000232655
Short name T118
Test name
Test status
Simulation time 25265666 ps
CPU time 1.13 seconds
Started Aug 19 05:10:53 PM PDT 24
Finished Aug 19 05:10:55 PM PDT 24
Peak memory 219224 kb
Host smart-1489b4bd-6cf7-4d3d-984a-df5f0364041b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000232655 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4000232655
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.684239876
Short name T931
Test name
Test status
Simulation time 51188621 ps
CPU time 0.89 seconds
Started Aug 19 05:10:46 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 209632 kb
Host smart-3e80ad14-ef81-4217-bab5-c52ce15bc1bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684239876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.684239876
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.731625480
Short name T949
Test name
Test status
Simulation time 456987073 ps
CPU time 1.38 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 211980 kb
Host smart-2ebb83a7-84a4-4da4-9405-6911f4acdf11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731625480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.731625480
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.863645743
Short name T121
Test name
Test status
Simulation time 87082098 ps
CPU time 2.65 seconds
Started Aug 19 05:10:48 PM PDT 24
Finished Aug 19 05:10:51 PM PDT 24
Peak memory 218156 kb
Host smart-c3169d8a-924d-4ee4-95a4-e1e5ddeaf310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863645743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.863645743
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.157175624
Short name T126
Test name
Test status
Simulation time 118203941 ps
CPU time 2.05 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:11:03 PM PDT 24
Peak memory 222764 kb
Host smart-e8ddaa91-3dac-412e-9fb9-36c402c67bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157175624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.157175624
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3729577091
Short name T909
Test name
Test status
Simulation time 441793080 ps
CPU time 1.67 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 218212 kb
Host smart-a764c908-1810-49dd-adf5-2591bbba00cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729577091 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3729577091
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1292586724
Short name T189
Test name
Test status
Simulation time 17195910 ps
CPU time 0.82 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:46 PM PDT 24
Peak memory 209788 kb
Host smart-51fd179b-2214-4e19-9da4-cd37b6fdb77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292586724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1292586724
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.587944657
Short name T195
Test name
Test status
Simulation time 44698290 ps
CPU time 1.92 seconds
Started Aug 19 05:10:46 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 210148 kb
Host smart-c586a044-51d6-405d-b4cf-20f296e2ac5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587944657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.587944657
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1214032635
Short name T128
Test name
Test status
Simulation time 323728063 ps
CPU time 2 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 218128 kb
Host smart-023008b6-f1b4-447c-8b72-cf83639e2f11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214032635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1214032635
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2747359083
Short name T138
Test name
Test status
Simulation time 261883630 ps
CPU time 2.83 seconds
Started Aug 19 05:10:53 PM PDT 24
Finished Aug 19 05:10:56 PM PDT 24
Peak memory 218224 kb
Host smart-4781cc47-c071-479c-b5ae-d47458a85e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747359083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2747359083
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3060600044
Short name T153
Test name
Test status
Simulation time 77123945 ps
CPU time 1.16 seconds
Started Aug 19 05:10:57 PM PDT 24
Finished Aug 19 05:10:59 PM PDT 24
Peak memory 222400 kb
Host smart-7be528ce-a482-431d-9ff0-10d725c2163c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060600044 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3060600044
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2639359949
Short name T185
Test name
Test status
Simulation time 26424535 ps
CPU time 1.01 seconds
Started Aug 19 05:10:59 PM PDT 24
Finished Aug 19 05:11:01 PM PDT 24
Peak memory 209936 kb
Host smart-e65dfe08-9f1c-4797-9fac-57f3ca4b307d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639359949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2639359949
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2542211291
Short name T141
Test name
Test status
Simulation time 81423553 ps
CPU time 1.37 seconds
Started Aug 19 05:10:56 PM PDT 24
Finished Aug 19 05:10:58 PM PDT 24
Peak memory 209940 kb
Host smart-930991f6-61a5-4ea4-91b0-a078ae7c6711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542211291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2542211291
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3585789665
Short name T937
Test name
Test status
Simulation time 179173523 ps
CPU time 3.58 seconds
Started Aug 19 05:10:46 PM PDT 24
Finished Aug 19 05:10:49 PM PDT 24
Peak memory 218144 kb
Host smart-30d0dcf3-bae4-4d85-94cc-2a77e40e24e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585789665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3585789665
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1075299547
Short name T992
Test name
Test status
Simulation time 28021823 ps
CPU time 1.2 seconds
Started Aug 19 05:11:00 PM PDT 24
Finished Aug 19 05:11:02 PM PDT 24
Peak memory 218208 kb
Host smart-5ca7ee64-e438-43bb-ba5a-21dd9a14249d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075299547 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1075299547
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3770941871
Short name T184
Test name
Test status
Simulation time 46222509 ps
CPU time 0.84 seconds
Started Aug 19 05:10:48 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 209360 kb
Host smart-1cec9c82-b7c4-4800-9630-da554c372a23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770941871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3770941871
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4016019164
Short name T888
Test name
Test status
Simulation time 48744133 ps
CPU time 1.34 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 209876 kb
Host smart-dd2eb134-bd76-4982-90fc-4040e09364e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016019164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.4016019164
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1376623426
Short name T960
Test name
Test status
Simulation time 185054409 ps
CPU time 3.92 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:51 PM PDT 24
Peak memory 218140 kb
Host smart-4e82de48-1acc-4485-9cdd-9532182f41b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376623426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1376623426
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3765648863
Short name T152
Test name
Test status
Simulation time 35541959 ps
CPU time 1.1 seconds
Started Aug 19 05:10:55 PM PDT 24
Finished Aug 19 05:10:56 PM PDT 24
Peak memory 219360 kb
Host smart-8c191b4a-76be-4989-8e92-7defce17da8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765648863 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3765648863
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3730325276
Short name T969
Test name
Test status
Simulation time 65778773 ps
CPU time 0.86 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:51 PM PDT 24
Peak memory 209776 kb
Host smart-fce1ad78-4a68-4284-b2a7-7c0bcab5ecf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730325276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3730325276
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3735686043
Short name T917
Test name
Test status
Simulation time 141755676 ps
CPU time 1.42 seconds
Started Aug 19 05:10:48 PM PDT 24
Finished Aug 19 05:10:49 PM PDT 24
Peak memory 212180 kb
Host smart-7926130f-467b-4e99-a0b2-6935bdeb0636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735686043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3735686043
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2241035531
Short name T915
Test name
Test status
Simulation time 2142657511 ps
CPU time 2.94 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:50 PM PDT 24
Peak memory 218548 kb
Host smart-5701180f-e61a-493f-9b05-361484b20d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241035531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2241035531
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2012358205
Short name T139
Test name
Test status
Simulation time 62308329 ps
CPU time 2.02 seconds
Started Aug 19 05:10:50 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 222244 kb
Host smart-e4a8efe9-cb17-4e0c-a932-629aaad56824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012358205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2012358205
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2261907255
Short name T133
Test name
Test status
Simulation time 33733014 ps
CPU time 1.71 seconds
Started Aug 19 05:10:44 PM PDT 24
Finished Aug 19 05:10:46 PM PDT 24
Peak memory 218276 kb
Host smart-658c5090-98e9-413a-b20e-7df2dacd1956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261907255 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2261907255
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2146563277
Short name T911
Test name
Test status
Simulation time 43930023 ps
CPU time 0.85 seconds
Started Aug 19 05:11:01 PM PDT 24
Finished Aug 19 05:11:02 PM PDT 24
Peak memory 209732 kb
Host smart-d19095a9-3a16-4c57-99b7-be4130c09ae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146563277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2146563277
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3550268971
Short name T897
Test name
Test status
Simulation time 140353993 ps
CPU time 1.78 seconds
Started Aug 19 05:10:48 PM PDT 24
Finished Aug 19 05:10:50 PM PDT 24
Peak memory 210016 kb
Host smart-15971f7c-8e38-49a2-aab6-5b8f8217b6e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550268971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3550268971
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1399114169
Short name T899
Test name
Test status
Simulation time 226304193 ps
CPU time 1.87 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:10:51 PM PDT 24
Peak memory 218116 kb
Host smart-0447e0cc-10dd-4dca-9b76-49f3255fe8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399114169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1399114169
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1779988444
Short name T999
Test name
Test status
Simulation time 21230364 ps
CPU time 1.07 seconds
Started Aug 19 05:10:40 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 210016 kb
Host smart-2a46399f-968a-4a2b-8b94-211dfb377be8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779988444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1779988444
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1396147092
Short name T186
Test name
Test status
Simulation time 176907111 ps
CPU time 1.95 seconds
Started Aug 19 05:10:29 PM PDT 24
Finished Aug 19 05:10:31 PM PDT 24
Peak memory 209908 kb
Host smart-9a8c7718-eb7d-48e3-b52f-b3497fa360a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396147092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1396147092
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3359523864
Short name T875
Test name
Test status
Simulation time 12738254 ps
CPU time 1.02 seconds
Started Aug 19 05:10:35 PM PDT 24
Finished Aug 19 05:10:36 PM PDT 24
Peak memory 210676 kb
Host smart-8159b918-061c-4c6f-b14c-dc1e826cf897
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359523864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3359523864
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2202750099
Short name T906
Test name
Test status
Simulation time 28079421 ps
CPU time 1.68 seconds
Started Aug 19 05:10:29 PM PDT 24
Finished Aug 19 05:10:31 PM PDT 24
Peak memory 223976 kb
Host smart-917ae58e-f1e9-4814-af48-357329dc5696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202750099 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2202750099
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.612362704
Short name T966
Test name
Test status
Simulation time 35665267 ps
CPU time 0.82 seconds
Started Aug 19 05:10:40 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 209800 kb
Host smart-bfdcc063-a91f-4a94-9d7a-8a2a891e068c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612362704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.612362704
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.967917341
Short name T896
Test name
Test status
Simulation time 36397048 ps
CPU time 1.59 seconds
Started Aug 19 05:10:37 PM PDT 24
Finished Aug 19 05:10:39 PM PDT 24
Peak memory 209904 kb
Host smart-d380f75a-47e4-42b9-acc8-b416cfc89bd1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967917341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.967917341
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4159251728
Short name T921
Test name
Test status
Simulation time 451860919 ps
CPU time 6.06 seconds
Started Aug 19 05:10:35 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 209144 kb
Host smart-068cc9a4-0106-4cea-a94b-a148fc70f9e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159251728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4159251728
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1018436541
Short name T994
Test name
Test status
Simulation time 425485620 ps
CPU time 10.01 seconds
Started Aug 19 05:10:38 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 209760 kb
Host smart-de3946bc-597f-45ba-83d8-61bab78b84cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018436541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1018436541
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2177735865
Short name T894
Test name
Test status
Simulation time 81721866 ps
CPU time 1.74 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 211344 kb
Host smart-6b62dda5-1fe6-4778-a163-376db3de9fef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177735865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2177735865
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1812853062
Short name T879
Test name
Test status
Simulation time 83152470 ps
CPU time 1.48 seconds
Started Aug 19 05:10:30 PM PDT 24
Finished Aug 19 05:10:31 PM PDT 24
Peak memory 218368 kb
Host smart-08a35e1e-9d19-4c73-a57a-018956cb1e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181285
3062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1812853062
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2947083829
Short name T890
Test name
Test status
Simulation time 64477605 ps
CPU time 1.35 seconds
Started Aug 19 05:10:36 PM PDT 24
Finished Aug 19 05:10:37 PM PDT 24
Peak memory 209876 kb
Host smart-a0681de5-ee9f-4925-9d43-0840f4910d25
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947083829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2947083829
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1348884778
Short name T934
Test name
Test status
Simulation time 138223600 ps
CPU time 1.21 seconds
Started Aug 19 05:10:22 PM PDT 24
Finished Aug 19 05:10:23 PM PDT 24
Peak memory 210136 kb
Host smart-c6b23b38-e2db-48f2-9ded-c46cc8562af7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348884778 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1348884778
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.898596526
Short name T884
Test name
Test status
Simulation time 30409757 ps
CPU time 1.27 seconds
Started Aug 19 05:10:40 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 209956 kb
Host smart-74fdda07-6da6-4c5d-a609-f4996d656ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898596526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.898596526
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1441879215
Short name T946
Test name
Test status
Simulation time 52633097 ps
CPU time 1.79 seconds
Started Aug 19 05:10:18 PM PDT 24
Finished Aug 19 05:10:20 PM PDT 24
Peak memory 218444 kb
Host smart-a0e71782-8b3a-4b59-b05d-d70476c0f6ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441879215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1441879215
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2531526899
Short name T929
Test name
Test status
Simulation time 17679647 ps
CPU time 1.27 seconds
Started Aug 19 05:10:23 PM PDT 24
Finished Aug 19 05:10:24 PM PDT 24
Peak memory 209520 kb
Host smart-036238d2-e1de-47df-9cbe-0c0e46ffa9d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531526899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2531526899
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.228247271
Short name T188
Test name
Test status
Simulation time 169525972 ps
CPU time 2.92 seconds
Started Aug 19 05:10:35 PM PDT 24
Finished Aug 19 05:10:38 PM PDT 24
Peak memory 209196 kb
Host smart-392157a2-4ea3-4a7f-9463-a678175d4b53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228247271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.228247271
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2329610543
Short name T181
Test name
Test status
Simulation time 71488046 ps
CPU time 1.11 seconds
Started Aug 19 05:10:21 PM PDT 24
Finished Aug 19 05:10:22 PM PDT 24
Peak memory 212244 kb
Host smart-22a32b70-5dc1-40a8-8587-bef1297abe03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329610543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2329610543
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.319618936
Short name T930
Test name
Test status
Simulation time 167454776 ps
CPU time 1.08 seconds
Started Aug 19 05:10:20 PM PDT 24
Finished Aug 19 05:10:21 PM PDT 24
Peak memory 218236 kb
Host smart-ddac4e5b-eaf8-4e76-ab7a-909d14529510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319618936 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.319618936
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3024671291
Short name T954
Test name
Test status
Simulation time 271035077 ps
CPU time 0.9 seconds
Started Aug 19 05:10:32 PM PDT 24
Finished Aug 19 05:10:33 PM PDT 24
Peak memory 209940 kb
Host smart-46ed0a57-1d8e-44ee-abc5-63309dfe15b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024671291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3024671291
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1233535142
Short name T902
Test name
Test status
Simulation time 130351323 ps
CPU time 2.3 seconds
Started Aug 19 05:10:31 PM PDT 24
Finished Aug 19 05:10:33 PM PDT 24
Peak memory 209824 kb
Host smart-582b2a72-919d-44e4-ae9b-19364415f9b1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233535142 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1233535142
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1947999299
Short name T886
Test name
Test status
Simulation time 6360491143 ps
CPU time 3.73 seconds
Started Aug 19 05:10:23 PM PDT 24
Finished Aug 19 05:10:27 PM PDT 24
Peak memory 209872 kb
Host smart-eaf5abd7-ca46-4a0f-8113-f12f121eef0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947999299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1947999299
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4086070288
Short name T970
Test name
Test status
Simulation time 3059962518 ps
CPU time 8.33 seconds
Started Aug 19 05:10:22 PM PDT 24
Finished Aug 19 05:10:30 PM PDT 24
Peak memory 209012 kb
Host smart-d4edb5a6-f0ea-4dbb-bb11-f37e804e48a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086070288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4086070288
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3599051006
Short name T881
Test name
Test status
Simulation time 614828904 ps
CPU time 5.26 seconds
Started Aug 19 05:10:40 PM PDT 24
Finished Aug 19 05:10:45 PM PDT 24
Peak memory 211668 kb
Host smart-36d2ae22-dd50-4e36-bc31-1d6d79ef748f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599051006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3599051006
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.494307231
Short name T995
Test name
Test status
Simulation time 400591050 ps
CPU time 3.27 seconds
Started Aug 19 05:10:19 PM PDT 24
Finished Aug 19 05:10:23 PM PDT 24
Peak memory 218224 kb
Host smart-e6d3774b-102b-443e-9572-59aec7a01e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494307
231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.494307231
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2950042020
Short name T967
Test name
Test status
Simulation time 118842816 ps
CPU time 1.46 seconds
Started Aug 19 05:10:32 PM PDT 24
Finished Aug 19 05:10:34 PM PDT 24
Peak memory 209908 kb
Host smart-76b348f1-a173-4bad-9773-b116a8d3b265
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950042020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2950042020
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3405291228
Short name T998
Test name
Test status
Simulation time 56298412 ps
CPU time 1 seconds
Started Aug 19 05:10:31 PM PDT 24
Finished Aug 19 05:10:33 PM PDT 24
Peak memory 209928 kb
Host smart-57f4611a-89bd-4f69-8ec2-7019336f0a44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405291228 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3405291228
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.515030228
Short name T880
Test name
Test status
Simulation time 52647065 ps
CPU time 1.05 seconds
Started Aug 19 05:10:23 PM PDT 24
Finished Aug 19 05:10:24 PM PDT 24
Peak memory 209944 kb
Host smart-59c8a280-2d4f-47d7-9838-cfb34c713522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515030228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.515030228
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3511378027
Short name T924
Test name
Test status
Simulation time 42219956 ps
CPU time 3.2 seconds
Started Aug 19 05:10:27 PM PDT 24
Finished Aug 19 05:10:35 PM PDT 24
Peak memory 218204 kb
Host smart-835faaf6-77d6-4d00-a8ed-1003ca2018d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511378027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3511378027
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.18622052
Short name T182
Test name
Test status
Simulation time 65985906 ps
CPU time 1.29 seconds
Started Aug 19 05:10:30 PM PDT 24
Finished Aug 19 05:10:31 PM PDT 24
Peak memory 210008 kb
Host smart-cc22e908-c494-4ca7-9496-437733ac10e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18622052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing.18622052
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1087778918
Short name T981
Test name
Test status
Simulation time 129367232 ps
CPU time 1.83 seconds
Started Aug 19 05:10:28 PM PDT 24
Finished Aug 19 05:10:30 PM PDT 24
Peak memory 209912 kb
Host smart-954a223c-26bd-4bc3-a7bc-5276bf97adb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087778918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1087778918
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.681195343
Short name T974
Test name
Test status
Simulation time 63984539 ps
CPU time 0.97 seconds
Started Aug 19 05:10:31 PM PDT 24
Finished Aug 19 05:10:32 PM PDT 24
Peak memory 210532 kb
Host smart-1f2dcf4b-e661-4fc6-b853-68d8437e55d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681195343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.681195343
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3855444805
Short name T895
Test name
Test status
Simulation time 117321908 ps
CPU time 1.3 seconds
Started Aug 19 05:10:27 PM PDT 24
Finished Aug 19 05:10:28 PM PDT 24
Peak memory 219728 kb
Host smart-81c51ae3-6584-4977-8e64-5f3edc0e1a88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855444805 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3855444805
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3232993271
Short name T982
Test name
Test status
Simulation time 26094796 ps
CPU time 1 seconds
Started Aug 19 05:10:31 PM PDT 24
Finished Aug 19 05:10:32 PM PDT 24
Peak memory 209920 kb
Host smart-e4ac0221-e7f9-4331-8572-2e58730b755a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232993271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3232993271
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.110594915
Short name T963
Test name
Test status
Simulation time 79906554 ps
CPU time 1.17 seconds
Started Aug 19 05:10:28 PM PDT 24
Finished Aug 19 05:10:29 PM PDT 24
Peak memory 208656 kb
Host smart-ba666ea7-ab3e-4e1e-8964-3a6868c8001a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110594915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.110594915
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.869465590
Short name T876
Test name
Test status
Simulation time 1418448698 ps
CPU time 9.57 seconds
Started Aug 19 05:10:29 PM PDT 24
Finished Aug 19 05:10:38 PM PDT 24
Peak memory 209724 kb
Host smart-a910afa7-bf4a-42b7-8b03-c5cdcab60f97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869465590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.869465590
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3434480643
Short name T962
Test name
Test status
Simulation time 1815380832 ps
CPU time 12.14 seconds
Started Aug 19 05:10:28 PM PDT 24
Finished Aug 19 05:10:40 PM PDT 24
Peak memory 209868 kb
Host smart-f0d2c560-3300-435b-8d79-d0baf3f66a57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434480643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3434480643
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1853726601
Short name T973
Test name
Test status
Simulation time 112457680 ps
CPU time 2.15 seconds
Started Aug 19 05:10:32 PM PDT 24
Finished Aug 19 05:10:35 PM PDT 24
Peak memory 211372 kb
Host smart-a59de45f-026e-4c82-ab7f-9fbc829b6207
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853726601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1853726601
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3304286956
Short name T920
Test name
Test status
Simulation time 242646566 ps
CPU time 2.42 seconds
Started Aug 19 05:10:21 PM PDT 24
Finished Aug 19 05:10:23 PM PDT 24
Peak memory 222488 kb
Host smart-88373294-4dd3-42fd-acb0-4ed274d6a268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330428
6956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3304286956
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4134911704
Short name T927
Test name
Test status
Simulation time 70842860 ps
CPU time 1.79 seconds
Started Aug 19 05:10:25 PM PDT 24
Finished Aug 19 05:10:27 PM PDT 24
Peak memory 218124 kb
Host smart-d899e862-2c8a-4b87-975b-24fee0d87c1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134911704 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4134911704
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1591574810
Short name T922
Test name
Test status
Simulation time 32465527 ps
CPU time 1.15 seconds
Started Aug 19 05:10:29 PM PDT 24
Finished Aug 19 05:10:30 PM PDT 24
Peak memory 209960 kb
Host smart-3c48a108-a587-4833-a8b1-fb9ae4abb9cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591574810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1591574810
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3511080434
Short name T116
Test name
Test status
Simulation time 88375381 ps
CPU time 1.64 seconds
Started Aug 19 05:10:33 PM PDT 24
Finished Aug 19 05:10:34 PM PDT 24
Peak memory 218100 kb
Host smart-7049e5ca-a4c6-4a70-b0e6-5da6a21b156c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511080434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3511080434
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2703926073
Short name T957
Test name
Test status
Simulation time 34370868 ps
CPU time 1.77 seconds
Started Aug 19 05:10:36 PM PDT 24
Finished Aug 19 05:10:38 PM PDT 24
Peak memory 219256 kb
Host smart-604fa966-4e1c-4bb2-8b5e-5b4a1a5137e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703926073 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2703926073
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2376157198
Short name T905
Test name
Test status
Simulation time 21710787 ps
CPU time 0.99 seconds
Started Aug 19 05:10:46 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 209360 kb
Host smart-605e0e24-8510-4c6c-93fb-626d774d9ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376157198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2376157198
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1823366253
Short name T972
Test name
Test status
Simulation time 164289012 ps
CPU time 1.14 seconds
Started Aug 19 05:10:34 PM PDT 24
Finished Aug 19 05:10:36 PM PDT 24
Peak memory 208556 kb
Host smart-7b759bc1-00b0-4b94-8972-4ae4d9b78df9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823366253 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1823366253
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3090348845
Short name T887
Test name
Test status
Simulation time 655419427 ps
CPU time 7.02 seconds
Started Aug 19 05:10:36 PM PDT 24
Finished Aug 19 05:10:44 PM PDT 24
Peak memory 209536 kb
Host smart-67e5d953-82b9-4428-a98c-ed6a5b91b082
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090348845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3090348845
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.693084916
Short name T885
Test name
Test status
Simulation time 915136405 ps
CPU time 11.33 seconds
Started Aug 19 05:10:42 PM PDT 24
Finished Aug 19 05:10:54 PM PDT 24
Peak memory 209128 kb
Host smart-79b99269-6d96-4df2-afa5-b727ee407c95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693084916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.693084916
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1397007763
Short name T882
Test name
Test status
Simulation time 145696583 ps
CPU time 1.6 seconds
Started Aug 19 05:10:38 PM PDT 24
Finished Aug 19 05:10:39 PM PDT 24
Peak memory 211340 kb
Host smart-8f37eb9c-998a-4003-9833-443576f7223a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397007763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1397007763
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3829162713
Short name T978
Test name
Test status
Simulation time 216628845 ps
CPU time 1.64 seconds
Started Aug 19 05:10:36 PM PDT 24
Finished Aug 19 05:10:37 PM PDT 24
Peak memory 219528 kb
Host smart-6f0788b2-1f3e-4bed-b266-2fcc46641673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382916
2713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3829162713
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.195974779
Short name T988
Test name
Test status
Simulation time 110214370 ps
CPU time 1.38 seconds
Started Aug 19 05:10:21 PM PDT 24
Finished Aug 19 05:10:22 PM PDT 24
Peak memory 209812 kb
Host smart-cb6b5b9d-9946-4a57-a29f-c8b74cd44953
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195974779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.195974779
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.659722669
Short name T191
Test name
Test status
Simulation time 36966606 ps
CPU time 1.34 seconds
Started Aug 19 05:10:40 PM PDT 24
Finished Aug 19 05:10:42 PM PDT 24
Peak memory 209888 kb
Host smart-8cc0174a-5a78-4ebc-9524-f620eb3bcab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659722669 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.659722669
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2031234363
Short name T193
Test name
Test status
Simulation time 136931556 ps
CPU time 1.4 seconds
Started Aug 19 05:10:32 PM PDT 24
Finished Aug 19 05:10:33 PM PDT 24
Peak memory 209976 kb
Host smart-6f12e5ab-ed84-4728-9900-b290b4ca8672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031234363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2031234363
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.797367180
Short name T989
Test name
Test status
Simulation time 165965252 ps
CPU time 3.44 seconds
Started Aug 19 05:10:37 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 218308 kb
Host smart-ead3804d-d864-4f9a-91a8-2b1920d17aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797367180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.797367180
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.896355334
Short name T112
Test name
Test status
Simulation time 102281744 ps
CPU time 1.69 seconds
Started Aug 19 05:10:43 PM PDT 24
Finished Aug 19 05:10:45 PM PDT 24
Peak memory 220048 kb
Host smart-3ea0101f-27e0-4ba8-97c5-cac27f4c1256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896355334 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.896355334
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.484463927
Short name T935
Test name
Test status
Simulation time 16951748 ps
CPU time 0.93 seconds
Started Aug 19 05:10:40 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 209944 kb
Host smart-975c798b-44af-4d9e-8587-33529720b3f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484463927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.484463927
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.470211042
Short name T145
Test name
Test status
Simulation time 63957954 ps
CPU time 2.22 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 209868 kb
Host smart-a6eca841-10b5-4d27-8229-fdba704f4e59
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470211042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.470211042
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1478389364
Short name T942
Test name
Test status
Simulation time 482923254 ps
CPU time 11.62 seconds
Started Aug 19 05:10:36 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 209868 kb
Host smart-46eba609-60aa-4870-aad5-2b62fbb5b89f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478389364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1478389364
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2193719186
Short name T932
Test name
Test status
Simulation time 2625817374 ps
CPU time 31.52 seconds
Started Aug 19 05:10:36 PM PDT 24
Finished Aug 19 05:11:08 PM PDT 24
Peak memory 209932 kb
Host smart-267dd2dd-3435-4664-909a-e15747970642
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193719186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2193719186
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.122089843
Short name T914
Test name
Test status
Simulation time 564920512 ps
CPU time 2.1 seconds
Started Aug 19 05:10:31 PM PDT 24
Finished Aug 19 05:10:33 PM PDT 24
Peak memory 211432 kb
Host smart-51564ad8-ce52-4acc-82a4-75ed964fbb3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122089843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.122089843
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2910369071
Short name T939
Test name
Test status
Simulation time 98717932 ps
CPU time 1.97 seconds
Started Aug 19 05:10:46 PM PDT 24
Finished Aug 19 05:10:49 PM PDT 24
Peak memory 222840 kb
Host smart-f80087a5-3ed6-4245-9ec4-53ee980c4d1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291036
9071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2910369071
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2605673320
Short name T892
Test name
Test status
Simulation time 95761210 ps
CPU time 1.38 seconds
Started Aug 19 05:10:35 PM PDT 24
Finished Aug 19 05:10:37 PM PDT 24
Peak memory 209872 kb
Host smart-33f04a88-4895-4b5a-9fe3-e9444124e97d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605673320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2605673320
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3128015079
Short name T965
Test name
Test status
Simulation time 51448879 ps
CPU time 2.08 seconds
Started Aug 19 05:10:36 PM PDT 24
Finished Aug 19 05:10:38 PM PDT 24
Peak memory 212052 kb
Host smart-c30de4a6-6238-40fb-9050-ee96e6a4dc2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128015079 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3128015079
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4006568283
Short name T975
Test name
Test status
Simulation time 102675804 ps
CPU time 1.15 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:40 PM PDT 24
Peak memory 209724 kb
Host smart-d917af36-4a99-4c1f-93fb-464923fb14e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006568283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4006568283
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2026334073
Short name T131
Test name
Test status
Simulation time 128983897 ps
CPU time 2.31 seconds
Started Aug 19 05:10:32 PM PDT 24
Finished Aug 19 05:10:35 PM PDT 24
Peak memory 218256 kb
Host smart-da05b945-a652-4555-a2ea-a2a0eaef0448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026334073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2026334073
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.671269424
Short name T206
Test name
Test status
Simulation time 61837984 ps
CPU time 2.07 seconds
Started Aug 19 05:10:41 PM PDT 24
Finished Aug 19 05:10:43 PM PDT 24
Peak memory 222632 kb
Host smart-b74a8beb-b042-48c8-892e-ddbf68b00fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671269424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.671269424
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.736880747
Short name T919
Test name
Test status
Simulation time 29946133 ps
CPU time 1.3 seconds
Started Aug 19 05:10:33 PM PDT 24
Finished Aug 19 05:10:35 PM PDT 24
Peak memory 219356 kb
Host smart-e02c6642-3716-46f1-92f5-eac2352d3364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736880747 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.736880747
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1232275105
Short name T898
Test name
Test status
Simulation time 186467705 ps
CPU time 0.87 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:40 PM PDT 24
Peak memory 209784 kb
Host smart-1b9ea160-f96b-4c32-8283-297fea50abef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232275105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1232275105
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2264786941
Short name T874
Test name
Test status
Simulation time 32660202 ps
CPU time 1.38 seconds
Started Aug 19 05:10:51 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 209876 kb
Host smart-428850d3-b540-4f47-a342-80fe19858230
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264786941 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2264786941
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.917364334
Short name T877
Test name
Test status
Simulation time 304941546 ps
CPU time 7.74 seconds
Started Aug 19 05:10:38 PM PDT 24
Finished Aug 19 05:10:46 PM PDT 24
Peak memory 209720 kb
Host smart-32049124-5406-4061-9144-77f0227df383
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917364334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.917364334
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4122672609
Short name T961
Test name
Test status
Simulation time 1921355388 ps
CPU time 22.78 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:11:10 PM PDT 24
Peak memory 209888 kb
Host smart-9160fa2f-29ec-4403-93bd-c814d709ba84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122672609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.4122672609
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3421556030
Short name T891
Test name
Test status
Simulation time 230896492 ps
CPU time 2.85 seconds
Started Aug 19 05:10:41 PM PDT 24
Finished Aug 19 05:10:44 PM PDT 24
Peak memory 211648 kb
Host smart-a54927f9-f3d8-42f2-b297-0380411577e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421556030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3421556030
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.773714875
Short name T926
Test name
Test status
Simulation time 1098850167 ps
CPU time 4.68 seconds
Started Aug 19 05:10:43 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 218284 kb
Host smart-faf4e5c0-8f9b-47d4-a4d4-2512cc598f6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773714
875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.773714875
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2897492644
Short name T987
Test name
Test status
Simulation time 206600095 ps
CPU time 1.13 seconds
Started Aug 19 05:10:48 PM PDT 24
Finished Aug 19 05:10:49 PM PDT 24
Peak memory 209884 kb
Host smart-3ed756a2-a81a-4013-951e-59930220fb3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897492644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2897492644
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1283244922
Short name T907
Test name
Test status
Simulation time 49933455 ps
CPU time 1.22 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 209964 kb
Host smart-a750cbdb-bc7e-4cd1-8338-e5ac9c0bd9ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283244922 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1283244922
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.486259657
Short name T196
Test name
Test status
Simulation time 41857738 ps
CPU time 1.41 seconds
Started Aug 19 05:10:54 PM PDT 24
Finished Aug 19 05:10:55 PM PDT 24
Peak memory 209696 kb
Host smart-0db66a85-2af4-425f-bc66-f7482ebf6674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486259657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.486259657
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.904991544
Short name T120
Test name
Test status
Simulation time 64640499 ps
CPU time 1.77 seconds
Started Aug 19 05:10:46 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 218096 kb
Host smart-92b9d3ef-45f6-4035-a461-07a16820dbad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904991544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.904991544
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.787469939
Short name T127
Test name
Test status
Simulation time 47407106 ps
CPU time 2.03 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 218252 kb
Host smart-a6856488-f06e-4a3d-aee3-682ddfb32b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787469939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.787469939
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.545176544
Short name T125
Test name
Test status
Simulation time 73317383 ps
CPU time 1.65 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:46 PM PDT 24
Peak memory 218340 kb
Host smart-c0ee3f65-1f40-4073-bca7-14a715158541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545176544 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.545176544
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1058624081
Short name T936
Test name
Test status
Simulation time 29924922 ps
CPU time 0.83 seconds
Started Aug 19 05:10:43 PM PDT 24
Finished Aug 19 05:10:44 PM PDT 24
Peak memory 209756 kb
Host smart-a6dd7bb2-983f-40ae-8630-49929a268e47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058624081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1058624081
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2625878936
Short name T944
Test name
Test status
Simulation time 55143174 ps
CPU time 1.85 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:49 PM PDT 24
Peak memory 209840 kb
Host smart-bfec32ba-b5a7-4202-bd06-896a9389f92f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625878936 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2625878936
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1004012332
Short name T916
Test name
Test status
Simulation time 296429094 ps
CPU time 7.93 seconds
Started Aug 19 05:10:44 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 209116 kb
Host smart-a4935f27-70ab-4962-b8ca-85e2a2a84fb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004012332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1004012332
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.364551078
Short name T958
Test name
Test status
Simulation time 2517928342 ps
CPU time 16.17 seconds
Started Aug 19 05:10:53 PM PDT 24
Finished Aug 19 05:11:09 PM PDT 24
Peak memory 209900 kb
Host smart-71fb8bb5-a8e4-4b04-ad88-6d7451e7bf3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364551078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.364551078
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2517540658
Short name T984
Test name
Test status
Simulation time 126595774 ps
CPU time 2.3 seconds
Started Aug 19 05:10:49 PM PDT 24
Finished Aug 19 05:10:52 PM PDT 24
Peak memory 211020 kb
Host smart-889d1ec9-0e05-41e8-a5ab-f2f325d14a30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517540658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2517540658
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.679246139
Short name T893
Test name
Test status
Simulation time 826176544 ps
CPU time 3.7 seconds
Started Aug 19 05:10:51 PM PDT 24
Finished Aug 19 05:10:55 PM PDT 24
Peak memory 218304 kb
Host smart-53dd9881-ca33-4219-a5d1-26b3bda036d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679246
139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.679246139
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3023012323
Short name T883
Test name
Test status
Simulation time 34569430 ps
CPU time 1.53 seconds
Started Aug 19 05:10:43 PM PDT 24
Finished Aug 19 05:10:45 PM PDT 24
Peak memory 209892 kb
Host smart-38576e16-a64f-4a27-9edf-28fec659046c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023012323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3023012323
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.626578228
Short name T192
Test name
Test status
Simulation time 148295422 ps
CPU time 1.46 seconds
Started Aug 19 05:10:44 PM PDT 24
Finished Aug 19 05:10:46 PM PDT 24
Peak memory 209352 kb
Host smart-c10a5074-bab2-4ceb-ad1d-f8fbb8bd7206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626578228 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.626578228
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2155958491
Short name T904
Test name
Test status
Simulation time 15609394 ps
CPU time 1.02 seconds
Started Aug 19 05:10:44 PM PDT 24
Finished Aug 19 05:10:45 PM PDT 24
Peak memory 209976 kb
Host smart-56e49e34-29ca-4700-b3b7-152e7094dd18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155958491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2155958491
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.10088990
Short name T991
Test name
Test status
Simulation time 1335265116 ps
CPU time 2.31 seconds
Started Aug 19 05:10:37 PM PDT 24
Finished Aug 19 05:10:39 PM PDT 24
Peak memory 218828 kb
Host smart-ae6e448a-a87a-457b-a508-38f3b8e8800d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10088990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.10088990
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2489199913
Short name T135
Test name
Test status
Simulation time 620032624 ps
CPU time 3.99 seconds
Started Aug 19 05:10:35 PM PDT 24
Finished Aug 19 05:10:39 PM PDT 24
Peak memory 218148 kb
Host smart-805a1ab8-34c1-42c5-b0af-4ea7545501de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489199913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2489199913
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3103478079
Short name T959
Test name
Test status
Simulation time 19917447 ps
CPU time 1.39 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:40 PM PDT 24
Peak memory 218936 kb
Host smart-661d2559-f3f3-4bf8-972e-e5e5c4beba81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103478079 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3103478079
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2482170396
Short name T183
Test name
Test status
Simulation time 15064555 ps
CPU time 1.01 seconds
Started Aug 19 05:10:47 PM PDT 24
Finished Aug 19 05:10:48 PM PDT 24
Peak memory 209788 kb
Host smart-152cf8b0-8ce9-4328-8201-7e00e4e69584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482170396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2482170396
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4081246195
Short name T933
Test name
Test status
Simulation time 269736627 ps
CPU time 2.16 seconds
Started Aug 19 05:10:42 PM PDT 24
Finished Aug 19 05:10:45 PM PDT 24
Peak memory 209896 kb
Host smart-12439bac-f21f-4329-a92a-f4bff84e578f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081246195 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4081246195
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2105011727
Short name T143
Test name
Test status
Simulation time 1104172417 ps
CPU time 8.83 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:54 PM PDT 24
Peak memory 209148 kb
Host smart-3eef75bd-03dc-4f0e-ac0b-11134b71756b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105011727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2105011727
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1216287976
Short name T968
Test name
Test status
Simulation time 1031351952 ps
CPU time 8.59 seconds
Started Aug 19 05:10:45 PM PDT 24
Finished Aug 19 05:10:54 PM PDT 24
Peak memory 209688 kb
Host smart-7d83cf14-464f-48db-ae89-4ccb52a0bbee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216287976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1216287976
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1424547785
Short name T119
Test name
Test status
Simulation time 272983082 ps
CPU time 1.8 seconds
Started Aug 19 05:10:39 PM PDT 24
Finished Aug 19 05:10:41 PM PDT 24
Peak memory 209840 kb
Host smart-eab2c61b-7304-42c4-bdf9-cb6ddcf911c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424547785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1424547785
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946174004
Short name T993
Test name
Test status
Simulation time 101431410 ps
CPU time 2.11 seconds
Started Aug 19 05:10:37 PM PDT 24
Finished Aug 19 05:10:40 PM PDT 24
Peak memory 219328 kb
Host smart-6d8aad47-dd30-484b-95c8-7451fe5a2aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394617
4004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946174004
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.749157506
Short name T996
Test name
Test status
Simulation time 127803811 ps
CPU time 1.45 seconds
Started Aug 19 05:10:43 PM PDT 24
Finished Aug 19 05:10:45 PM PDT 24
Peak memory 209924 kb
Host smart-60984b98-ee69-437f-8650-e5ecf01bff99
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749157506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.749157506
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1158900729
Short name T889
Test name
Test status
Simulation time 29066785 ps
CPU time 0.97 seconds
Started Aug 19 05:10:46 PM PDT 24
Finished Aug 19 05:10:47 PM PDT 24
Peak memory 209900 kb
Host smart-42985ec1-ff83-4bf4-a597-da202ccdd33e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158900729 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1158900729
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.289193285
Short name T976
Test name
Test status
Simulation time 53270208 ps
CPU time 1.51 seconds
Started Aug 19 05:10:33 PM PDT 24
Finished Aug 19 05:10:34 PM PDT 24
Peak memory 209944 kb
Host smart-e9d866e2-4826-43f7-b8af-de930066a969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289193285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.289193285
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.62416157
Short name T990
Test name
Test status
Simulation time 87070848 ps
CPU time 2.36 seconds
Started Aug 19 05:10:42 PM PDT 24
Finished Aug 19 05:10:45 PM PDT 24
Peak memory 218552 kb
Host smart-ef9ba7cf-9064-43df-9a30-b0d807b1ff9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62416157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.62416157
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2442172702
Short name T429
Test name
Test status
Simulation time 13354055 ps
CPU time 0.88 seconds
Started Aug 19 05:57:33 PM PDT 24
Finished Aug 19 05:57:34 PM PDT 24
Peak memory 208836 kb
Host smart-a61c73a4-8748-4cab-a48a-ee980097dbe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442172702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2442172702
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.781310739
Short name T535
Test name
Test status
Simulation time 12415717 ps
CPU time 0.79 seconds
Started Aug 19 05:57:24 PM PDT 24
Finished Aug 19 05:57:24 PM PDT 24
Peak memory 208544 kb
Host smart-0b43fd34-5de4-46f8-83b9-1ccab0c8ca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781310739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.781310739
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3256556122
Short name T14
Test name
Test status
Simulation time 239242773 ps
CPU time 12.21 seconds
Started Aug 19 05:57:25 PM PDT 24
Finished Aug 19 05:57:38 PM PDT 24
Peak memory 218320 kb
Host smart-e53c9f39-dfec-4ffe-ac32-d41524f9c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256556122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3256556122
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1909065594
Short name T454
Test name
Test status
Simulation time 1371370402 ps
CPU time 15.69 seconds
Started Aug 19 05:57:33 PM PDT 24
Finished Aug 19 05:57:49 PM PDT 24
Peak memory 217420 kb
Host smart-b33d6dba-5701-4e1f-9f37-6297f3557bd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909065594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1909065594
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2011825807
Short name T851
Test name
Test status
Simulation time 1614963136 ps
CPU time 24.02 seconds
Started Aug 19 05:57:31 PM PDT 24
Finished Aug 19 05:57:55 PM PDT 24
Peak memory 218260 kb
Host smart-8f55a8f2-3d16-472c-af9b-1497b9615a64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011825807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2011825807
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1648017402
Short name T402
Test name
Test status
Simulation time 468098784 ps
CPU time 2.16 seconds
Started Aug 19 05:57:28 PM PDT 24
Finished Aug 19 05:57:30 PM PDT 24
Peak memory 217628 kb
Host smart-e0c21ab3-f50b-4292-9364-7d219c4e057e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648017402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
648017402
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.569283572
Short name T449
Test name
Test status
Simulation time 2899306669 ps
CPU time 7.82 seconds
Started Aug 19 05:57:32 PM PDT 24
Finished Aug 19 05:57:40 PM PDT 24
Peak memory 218304 kb
Host smart-4981e351-0ca6-483f-9ca0-e3b704936b8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569283572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.569283572
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1461590921
Short name T80
Test name
Test status
Simulation time 8031367089 ps
CPU time 23.31 seconds
Started Aug 19 05:57:39 PM PDT 24
Finished Aug 19 05:58:02 PM PDT 24
Peak memory 217656 kb
Host smart-19ec7879-dec7-40ad-a9ea-aa6da8feb941
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461590921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1461590921
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3771669437
Short name T752
Test name
Test status
Simulation time 1092406766 ps
CPU time 8.5 seconds
Started Aug 19 05:57:27 PM PDT 24
Finished Aug 19 05:57:36 PM PDT 24
Peak memory 217592 kb
Host smart-6e9dfcbc-50f7-4348-b5be-52a47da240f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771669437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3771669437
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3236192950
Short name T291
Test name
Test status
Simulation time 5137929208 ps
CPU time 35.35 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 05:57:57 PM PDT 24
Peak memory 268224 kb
Host smart-bb36cfc0-a0d0-48b9-801c-a6220b7c6503
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236192950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3236192950
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.311086591
Short name T868
Test name
Test status
Simulation time 3412319992 ps
CPU time 12.64 seconds
Started Aug 19 05:57:29 PM PDT 24
Finished Aug 19 05:57:42 PM PDT 24
Peak memory 223152 kb
Host smart-40d1033f-b020-4efa-a4ee-cb0f879e7bf5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311086591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.311086591
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1448047592
Short name T313
Test name
Test status
Simulation time 71158672 ps
CPU time 3.74 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 05:57:25 PM PDT 24
Peak memory 218324 kb
Host smart-f5bd3148-6e7a-488e-90f8-ccbb2776fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448047592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1448047592
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3006635276
Short name T438
Test name
Test status
Simulation time 302018686 ps
CPU time 11.15 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 05:57:33 PM PDT 24
Peak memory 217756 kb
Host smart-5bab8804-b0ab-4259-a5a5-ff82a8d997c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006635276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3006635276
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3490008120
Short name T56
Test name
Test status
Simulation time 509643436 ps
CPU time 35.87 seconds
Started Aug 19 05:57:38 PM PDT 24
Finished Aug 19 05:58:14 PM PDT 24
Peak memory 269992 kb
Host smart-ce105eca-b180-4560-958d-f83c9c8e076e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490008120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3490008120
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.103930189
Short name T507
Test name
Test status
Simulation time 668118467 ps
CPU time 10.59 seconds
Started Aug 19 05:57:29 PM PDT 24
Finished Aug 19 05:57:40 PM PDT 24
Peak memory 225560 kb
Host smart-277c0832-c751-425d-aa94-af2cef66e0b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103930189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.103930189
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.978812577
Short name T221
Test name
Test status
Simulation time 647238357 ps
CPU time 10.18 seconds
Started Aug 19 05:57:31 PM PDT 24
Finished Aug 19 05:57:41 PM PDT 24
Peak memory 226044 kb
Host smart-aaf24ada-601e-4b00-9344-c97346c684c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978812577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.978812577
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3819844161
Short name T52
Test name
Test status
Simulation time 3077789432 ps
CPU time 13.48 seconds
Started Aug 19 05:57:22 PM PDT 24
Finished Aug 19 05:57:36 PM PDT 24
Peak memory 226144 kb
Host smart-bff5cad0-bf16-496c-8761-ddf1ad3b574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819844161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3819844161
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2622619092
Short name T505
Test name
Test status
Simulation time 28607261 ps
CPU time 2.22 seconds
Started Aug 19 05:57:22 PM PDT 24
Finished Aug 19 05:57:24 PM PDT 24
Peak memory 214304 kb
Host smart-67cd8bba-56cf-412b-8cef-30a033a18169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622619092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2622619092
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.951744456
Short name T348
Test name
Test status
Simulation time 619052421 ps
CPU time 19.61 seconds
Started Aug 19 05:57:21 PM PDT 24
Finished Aug 19 05:57:41 PM PDT 24
Peak memory 251052 kb
Host smart-c508792d-dd25-4ba9-a050-2a5da2238293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951744456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.951744456
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.419961659
Short name T427
Test name
Test status
Simulation time 212381114 ps
CPU time 7.82 seconds
Started Aug 19 05:57:26 PM PDT 24
Finished Aug 19 05:57:34 PM PDT 24
Peak memory 250940 kb
Host smart-c8b6d35c-f8f8-4152-9cde-11da88b17848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419961659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.419961659
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3336248057
Short name T416
Test name
Test status
Simulation time 55992957800 ps
CPU time 281.69 seconds
Started Aug 19 05:57:29 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 272136 kb
Host smart-6fb5832d-fb68-4865-85a4-858ebc73b96c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336248057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3336248057
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1836934828
Short name T687
Test name
Test status
Simulation time 8869584819 ps
CPU time 50.13 seconds
Started Aug 19 05:57:31 PM PDT 24
Finished Aug 19 05:58:21 PM PDT 24
Peak memory 269528 kb
Host smart-47778f59-dac6-4e09-a125-0a8df6374595
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1836934828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.1836934828
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3374827303
Short name T774
Test name
Test status
Simulation time 51157624 ps
CPU time 0.93 seconds
Started Aug 19 05:57:18 PM PDT 24
Finished Aug 19 05:57:19 PM PDT 24
Peak memory 211876 kb
Host smart-1b36a0cd-0400-4a99-b457-c631541e5206
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374827303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3374827303
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1771116170
Short name T741
Test name
Test status
Simulation time 45169373 ps
CPU time 0.93 seconds
Started Aug 19 05:57:42 PM PDT 24
Finished Aug 19 05:57:43 PM PDT 24
Peak memory 208904 kb
Host smart-bec3813f-b871-41bb-ae00-b595c14acb4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771116170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1771116170
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1452676283
Short name T266
Test name
Test status
Simulation time 22369488 ps
CPU time 0.78 seconds
Started Aug 19 05:57:30 PM PDT 24
Finished Aug 19 05:57:31 PM PDT 24
Peak memory 208596 kb
Host smart-e994292c-2a50-4965-8736-6c806973a8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452676283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1452676283
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2814252915
Short name T551
Test name
Test status
Simulation time 605202950 ps
CPU time 9.75 seconds
Started Aug 19 05:57:33 PM PDT 24
Finished Aug 19 05:57:43 PM PDT 24
Peak memory 218296 kb
Host smart-3cb69c8a-40f1-4c00-9f82-368aa78beabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814252915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2814252915
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.86473672
Short name T197
Test name
Test status
Simulation time 111341745 ps
CPU time 2.59 seconds
Started Aug 19 05:57:42 PM PDT 24
Finished Aug 19 05:57:44 PM PDT 24
Peak memory 217120 kb
Host smart-a1db83e9-e3e8-4ff2-93d2-b4224359cb20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86473672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.86473672
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2579213316
Short name T257
Test name
Test status
Simulation time 16317679747 ps
CPU time 58.14 seconds
Started Aug 19 05:57:30 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 219596 kb
Host smart-77af1e13-f2fe-49d9-9d3a-2e806057511c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579213316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2579213316
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1685507790
Short name T30
Test name
Test status
Simulation time 246294455 ps
CPU time 3.75 seconds
Started Aug 19 05:57:42 PM PDT 24
Finished Aug 19 05:57:46 PM PDT 24
Peak memory 217672 kb
Host smart-140ceef3-c256-48d3-b7ea-995659ed621e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685507790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
685507790
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2781041038
Short name T216
Test name
Test status
Simulation time 1447634846 ps
CPU time 6.84 seconds
Started Aug 19 05:57:38 PM PDT 24
Finished Aug 19 05:57:45 PM PDT 24
Peak memory 218252 kb
Host smart-a298fb26-e3cd-4448-a24d-48c3278d5b4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781041038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2781041038
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2089782569
Short name T873
Test name
Test status
Simulation time 5575091963 ps
CPU time 18.56 seconds
Started Aug 19 05:57:44 PM PDT 24
Finished Aug 19 05:58:03 PM PDT 24
Peak memory 217652 kb
Host smart-c8bb2ad3-2834-490d-8f64-50d6ec611213
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089782569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2089782569
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3221240519
Short name T629
Test name
Test status
Simulation time 76389015 ps
CPU time 1.55 seconds
Started Aug 19 05:57:30 PM PDT 24
Finished Aug 19 05:57:31 PM PDT 24
Peak memory 217604 kb
Host smart-aba3b8f9-03ec-4ddb-9823-44ae7b3dfe76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221240519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3221240519
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.4139830344
Short name T836
Test name
Test status
Simulation time 6558827442 ps
CPU time 58.55 seconds
Started Aug 19 05:57:32 PM PDT 24
Finished Aug 19 05:58:31 PM PDT 24
Peak memory 275532 kb
Host smart-959b3c14-4a3e-4e2f-9c0f-31ff35ea8acc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139830344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.4139830344
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2828447799
Short name T479
Test name
Test status
Simulation time 318270274 ps
CPU time 11.86 seconds
Started Aug 19 05:57:38 PM PDT 24
Finished Aug 19 05:57:50 PM PDT 24
Peak memory 250880 kb
Host smart-3444768f-2058-4eb3-bfe2-430241421072
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828447799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2828447799
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4163750020
Short name T693
Test name
Test status
Simulation time 290995847 ps
CPU time 2.53 seconds
Started Aug 19 05:57:33 PM PDT 24
Finished Aug 19 05:57:36 PM PDT 24
Peak memory 218316 kb
Host smart-9b1434ba-6bba-4872-817d-753db6efbea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163750020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4163750020
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2912565612
Short name T296
Test name
Test status
Simulation time 286693107 ps
CPU time 7.27 seconds
Started Aug 19 05:57:30 PM PDT 24
Finished Aug 19 05:57:37 PM PDT 24
Peak memory 217772 kb
Host smart-a20fc84c-d523-4bea-87b4-d8db1744dea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912565612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2912565612
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1046715546
Short name T641
Test name
Test status
Simulation time 1141018989 ps
CPU time 13.23 seconds
Started Aug 19 05:57:44 PM PDT 24
Finished Aug 19 05:57:57 PM PDT 24
Peak memory 218436 kb
Host smart-eba97570-478e-473d-b7c4-909fc1142e15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046715546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1046715546
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1734662307
Short name T320
Test name
Test status
Simulation time 583792798 ps
CPU time 12.59 seconds
Started Aug 19 05:57:40 PM PDT 24
Finished Aug 19 05:57:53 PM PDT 24
Peak memory 226056 kb
Host smart-626fbf15-0981-44da-b286-d700c57c5db5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734662307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1734662307
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3285621072
Short name T228
Test name
Test status
Simulation time 303340185 ps
CPU time 11.66 seconds
Started Aug 19 05:57:41 PM PDT 24
Finished Aug 19 05:57:53 PM PDT 24
Peak memory 218276 kb
Host smart-dda42388-4861-49f7-962e-a602ec1d9bd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285621072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
285621072
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2126853590
Short name T764
Test name
Test status
Simulation time 1311301184 ps
CPU time 13.33 seconds
Started Aug 19 05:57:30 PM PDT 24
Finished Aug 19 05:57:43 PM PDT 24
Peak memory 226120 kb
Host smart-08ea95f7-4b75-4a8f-8939-8da60f4ab7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126853590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2126853590
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1443535663
Short name T557
Test name
Test status
Simulation time 198729622 ps
CPU time 2.77 seconds
Started Aug 19 05:57:32 PM PDT 24
Finished Aug 19 05:57:35 PM PDT 24
Peak memory 217644 kb
Host smart-74d3dc75-38cd-49af-a6a0-4cdc2c4c65f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443535663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1443535663
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1689200776
Short name T392
Test name
Test status
Simulation time 143764667 ps
CPU time 21.52 seconds
Started Aug 19 05:57:30 PM PDT 24
Finished Aug 19 05:57:52 PM PDT 24
Peak memory 251016 kb
Host smart-e5bef9b6-c848-4735-8e1e-f04755abf962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689200776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1689200776
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4191182524
Short name T210
Test name
Test status
Simulation time 97875956 ps
CPU time 3.47 seconds
Started Aug 19 05:57:31 PM PDT 24
Finished Aug 19 05:57:34 PM PDT 24
Peak memory 226376 kb
Host smart-b02681cc-abad-4907-aede-7369a8eed99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191182524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4191182524
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3149923309
Short name T556
Test name
Test status
Simulation time 8687184759 ps
CPU time 184.68 seconds
Started Aug 19 05:57:42 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 268628 kb
Host smart-95147069-59e5-4951-8a0f-ac00756a9990
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149923309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3149923309
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3087875856
Short name T403
Test name
Test status
Simulation time 34258611 ps
CPU time 0.98 seconds
Started Aug 19 05:57:30 PM PDT 24
Finished Aug 19 05:57:31 PM PDT 24
Peak memory 211920 kb
Host smart-7def30c5-552a-45d8-ac86-a46b91984dae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087875856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3087875856
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.901706840
Short name T299
Test name
Test status
Simulation time 25020306 ps
CPU time 0.97 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:14 PM PDT 24
Peak memory 208856 kb
Host smart-fa3da790-24fc-4468-abb9-0bbff0b24ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901706840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.901706840
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.986510374
Short name T683
Test name
Test status
Simulation time 691015543 ps
CPU time 21.06 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:32 PM PDT 24
Peak memory 218256 kb
Host smart-443f91ea-ced3-4e1c-89d8-9651ca386001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986510374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.986510374
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2694533198
Short name T607
Test name
Test status
Simulation time 881739883 ps
CPU time 19.73 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:33 PM PDT 24
Peak memory 216748 kb
Host smart-9fe7d5a3-c35e-4d75-80ca-5aaf4783fb8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694533198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2694533198
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.563380497
Short name T272
Test name
Test status
Simulation time 1506430844 ps
CPU time 48.16 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 06:00:00 PM PDT 24
Peak memory 218864 kb
Host smart-a4b3e863-d7fb-4844-b570-025451474d69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563380497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.563380497
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2219038879
Short name T866
Test name
Test status
Simulation time 1149177368 ps
CPU time 5.99 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:19 PM PDT 24
Peak memory 218236 kb
Host smart-ed8f3150-5e68-4816-b725-eb2c9a5f6461
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219038879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2219038879
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1782682081
Short name T530
Test name
Test status
Simulation time 591055955 ps
CPU time 2.58 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:15 PM PDT 24
Peak memory 217596 kb
Host smart-12cebdde-152a-4c31-a94f-a3901a3deaa2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782682081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1782682081
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2315970095
Short name T472
Test name
Test status
Simulation time 15486203378 ps
CPU time 123.79 seconds
Started Aug 19 05:59:10 PM PDT 24
Finished Aug 19 06:01:14 PM PDT 24
Peak memory 283640 kb
Host smart-5117b94a-d0c2-4fb3-b69d-0ad32058ca4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315970095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2315970095
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3692960321
Short name T769
Test name
Test status
Simulation time 3210274038 ps
CPU time 13.89 seconds
Started Aug 19 05:59:08 PM PDT 24
Finished Aug 19 05:59:22 PM PDT 24
Peak memory 224888 kb
Host smart-3fc5012f-5ad1-4597-9e90-4c2ac94749e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692960321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3692960321
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.903027920
Short name T442
Test name
Test status
Simulation time 119705113 ps
CPU time 3.11 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:03 PM PDT 24
Peak memory 218304 kb
Host smart-f58f8c6c-313a-4701-9308-07533448699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903027920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.903027920
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2588921867
Short name T645
Test name
Test status
Simulation time 834066676 ps
CPU time 17.56 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:31 PM PDT 24
Peak memory 218464 kb
Host smart-2e1961d7-64fb-4267-8b60-47c8fac15e76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588921867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2588921867
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2940204356
Short name T297
Test name
Test status
Simulation time 362830035 ps
CPU time 11.16 seconds
Started Aug 19 05:59:09 PM PDT 24
Finished Aug 19 05:59:20 PM PDT 24
Peak memory 226052 kb
Host smart-ad021070-5aaa-4782-a14f-207c752ecd20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940204356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2940204356
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.526876712
Short name T63
Test name
Test status
Simulation time 556335408 ps
CPU time 5.91 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:17 PM PDT 24
Peak memory 218240 kb
Host smart-19dc02aa-4896-4931-a42f-abcfaa5a74de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526876712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.526876712
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.365462968
Short name T207
Test name
Test status
Simulation time 1642429548 ps
CPU time 7.94 seconds
Started Aug 19 05:59:09 PM PDT 24
Finished Aug 19 05:59:17 PM PDT 24
Peak memory 226108 kb
Host smart-3efa1d97-d79f-4e73-8240-2403b99e6b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365462968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.365462968
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3698892286
Short name T220
Test name
Test status
Simulation time 21224827 ps
CPU time 1.49 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:12 PM PDT 24
Peak memory 214052 kb
Host smart-65bdb487-d32e-46ad-9bd1-1eb9e8ae49a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698892286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3698892286
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1896161517
Short name T456
Test name
Test status
Simulation time 530589709 ps
CPU time 24.31 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:36 PM PDT 24
Peak memory 250852 kb
Host smart-a76b54a1-b6a0-4b22-beae-ac3e629b55a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896161517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1896161517
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2966641325
Short name T711
Test name
Test status
Simulation time 352574431 ps
CPU time 4.65 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 05:59:06 PM PDT 24
Peak memory 226376 kb
Host smart-5b738752-1c2e-417d-9297-a3fab7ae950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966641325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2966641325
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.147606386
Short name T339
Test name
Test status
Simulation time 1187663588 ps
CPU time 18.02 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:29 PM PDT 24
Peak memory 226136 kb
Host smart-659b3881-64b0-476d-b4f1-54b4f210bbc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147606386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.147606386
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1226341801
Short name T521
Test name
Test status
Simulation time 18691933 ps
CPU time 1.07 seconds
Started Aug 19 05:59:02 PM PDT 24
Finished Aug 19 05:59:03 PM PDT 24
Peak memory 212996 kb
Host smart-261667f7-6a2b-47c5-bac9-5dfa74b22524
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226341801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1226341801
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4220996521
Short name T372
Test name
Test status
Simulation time 48558753 ps
CPU time 0.97 seconds
Started Aug 19 05:59:22 PM PDT 24
Finished Aug 19 05:59:23 PM PDT 24
Peak memory 208916 kb
Host smart-2cdb97aa-c7f9-4006-b637-b46c3bd93586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220996521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4220996521
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1831300127
Short name T368
Test name
Test status
Simulation time 589837823 ps
CPU time 14.64 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:28 PM PDT 24
Peak memory 218300 kb
Host smart-c826a9f0-5249-4b65-9ad0-e74ae2372071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831300127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1831300127
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3468065
Short name T67
Test name
Test status
Simulation time 107247082 ps
CPU time 3.32 seconds
Started Aug 19 05:59:09 PM PDT 24
Finished Aug 19 05:59:12 PM PDT 24
Peak memory 217048 kb
Host smart-6de6c98b-b41e-49ba-b544-93731e3a130f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3468065
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3674528888
Short name T533
Test name
Test status
Simulation time 1767616874 ps
CPU time 31.87 seconds
Started Aug 19 05:59:10 PM PDT 24
Finished Aug 19 05:59:42 PM PDT 24
Peak memory 218264 kb
Host smart-89e516c2-4b0e-4a7f-9493-b2a3168449ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674528888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3674528888
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2036405271
Short name T734
Test name
Test status
Simulation time 589875101 ps
CPU time 5.46 seconds
Started Aug 19 05:59:09 PM PDT 24
Finished Aug 19 05:59:15 PM PDT 24
Peak memory 218256 kb
Host smart-e7c53110-d236-47c1-8eaf-ffd0ae60242e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036405271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2036405271
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3694374438
Short name T367
Test name
Test status
Simulation time 1038094359 ps
CPU time 7.4 seconds
Started Aug 19 05:59:08 PM PDT 24
Finished Aug 19 05:59:15 PM PDT 24
Peak memory 217612 kb
Host smart-bbf2be0d-ce43-4a73-8cda-5bf0a5698114
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694374438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3694374438
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.701913900
Short name T717
Test name
Test status
Simulation time 1464065641 ps
CPU time 46.18 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:59 PM PDT 24
Peak memory 276104 kb
Host smart-c84ffacd-7145-4a9f-8b4c-a69f5fe2905a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701913900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.701913900
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2433508800
Short name T247
Test name
Test status
Simulation time 332533809 ps
CPU time 17.06 seconds
Started Aug 19 05:59:10 PM PDT 24
Finished Aug 19 05:59:27 PM PDT 24
Peak memory 250880 kb
Host smart-9555d8e8-de0b-45b9-8d4d-cb614d76a145
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433508800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2433508800
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3212310349
Short name T605
Test name
Test status
Simulation time 192994899 ps
CPU time 3.31 seconds
Started Aug 19 05:59:08 PM PDT 24
Finished Aug 19 05:59:12 PM PDT 24
Peak memory 218296 kb
Host smart-99df0a57-ad16-4562-b5b3-4e9760f3429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212310349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3212310349
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3154492031
Short name T702
Test name
Test status
Simulation time 1444467779 ps
CPU time 14.78 seconds
Started Aug 19 05:59:13 PM PDT 24
Finished Aug 19 05:59:28 PM PDT 24
Peak memory 226216 kb
Host smart-93768d18-a99f-4c5a-9211-a75d07161bb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154492031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3154492031
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2163177119
Short name T512
Test name
Test status
Simulation time 745512218 ps
CPU time 15.84 seconds
Started Aug 19 05:59:09 PM PDT 24
Finished Aug 19 05:59:25 PM PDT 24
Peak memory 226048 kb
Host smart-189ea98e-3b74-4692-a120-4f4b79259775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163177119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2163177119
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3651057655
Short name T802
Test name
Test status
Simulation time 380397917 ps
CPU time 7.7 seconds
Started Aug 19 05:59:07 PM PDT 24
Finished Aug 19 05:59:14 PM PDT 24
Peak memory 226156 kb
Host smart-2c31b1cf-6805-4fbc-859d-a5e37dc81aec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651057655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3651057655
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3868614538
Short name T51
Test name
Test status
Simulation time 561764413 ps
CPU time 10.48 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:22 PM PDT 24
Peak memory 218444 kb
Host smart-d76ca918-3b35-41b6-8f5a-6ed678511166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868614538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3868614538
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2457492304
Short name T74
Test name
Test status
Simulation time 48248913 ps
CPU time 1.29 seconds
Started Aug 19 05:59:07 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 217732 kb
Host smart-3c01d3f3-e41a-4c9b-87ac-4008e7a77bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457492304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2457492304
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2875877771
Short name T468
Test name
Test status
Simulation time 315592940 ps
CPU time 29.4 seconds
Started Aug 19 05:59:12 PM PDT 24
Finished Aug 19 05:59:42 PM PDT 24
Peak memory 250960 kb
Host smart-ab8fa382-4723-4c7a-94ed-42510a6e5a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875877771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2875877771
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4210808161
Short name T527
Test name
Test status
Simulation time 274141756 ps
CPU time 5.99 seconds
Started Aug 19 05:59:10 PM PDT 24
Finished Aug 19 05:59:16 PM PDT 24
Peak memory 247272 kb
Host smart-c002c6d4-3daa-4e3c-82ba-4879111157ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210808161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4210808161
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.788171355
Short name T160
Test name
Test status
Simulation time 771897399 ps
CPU time 17.63 seconds
Started Aug 19 05:59:15 PM PDT 24
Finished Aug 19 05:59:33 PM PDT 24
Peak memory 226100 kb
Host smart-961ba9df-8df5-4740-bceb-54b13b0ed6f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788171355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.788171355
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2197983590
Short name T421
Test name
Test status
Simulation time 44191977 ps
CPU time 0.95 seconds
Started Aug 19 05:59:10 PM PDT 24
Finished Aug 19 05:59:11 PM PDT 24
Peak memory 211876 kb
Host smart-0698477e-2551-4da4-becd-cdc5bd329757
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197983590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2197983590
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1995128815
Short name T636
Test name
Test status
Simulation time 190071417 ps
CPU time 0.98 seconds
Started Aug 19 05:59:34 PM PDT 24
Finished Aug 19 05:59:35 PM PDT 24
Peak memory 208944 kb
Host smart-4bfedcb9-09b1-4072-8387-c9e561077fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995128815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1995128815
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.507858042
Short name T47
Test name
Test status
Simulation time 1306707951 ps
CPU time 11.79 seconds
Started Aug 19 05:59:23 PM PDT 24
Finished Aug 19 05:59:35 PM PDT 24
Peak memory 218224 kb
Host smart-9a925879-a834-4378-88bc-4fac078bb61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507858042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.507858042
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.499014501
Short name T672
Test name
Test status
Simulation time 304012448 ps
CPU time 4.7 seconds
Started Aug 19 05:59:25 PM PDT 24
Finished Aug 19 05:59:30 PM PDT 24
Peak memory 217032 kb
Host smart-9cd93e2d-d985-46c8-8959-3c7c85f77cf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499014501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.499014501
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1101623186
Short name T489
Test name
Test status
Simulation time 5650168767 ps
CPU time 74 seconds
Started Aug 19 05:59:24 PM PDT 24
Finished Aug 19 06:00:38 PM PDT 24
Peak memory 218952 kb
Host smart-c0f9877e-608b-45f2-bcd6-c8b4e9e27862
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101623186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1101623186
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1562427078
Short name T835
Test name
Test status
Simulation time 9633381410 ps
CPU time 12.03 seconds
Started Aug 19 05:59:24 PM PDT 24
Finished Aug 19 05:59:36 PM PDT 24
Peak memory 225808 kb
Host smart-9f66dcdd-b474-4685-8030-dd286c8cf553
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562427078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1562427078
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1556343578
Short name T839
Test name
Test status
Simulation time 1328036674 ps
CPU time 4.8 seconds
Started Aug 19 05:59:25 PM PDT 24
Finished Aug 19 05:59:30 PM PDT 24
Peak memory 217572 kb
Host smart-f3b7d6a1-7555-42fc-90b7-ab84f36e01c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556343578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1556343578
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3171740093
Short name T27
Test name
Test status
Simulation time 6516925720 ps
CPU time 42.1 seconds
Started Aug 19 05:59:25 PM PDT 24
Finished Aug 19 06:00:07 PM PDT 24
Peak memory 267428 kb
Host smart-78f79ff6-aa93-451d-ad37-4d9493aeedf2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171740093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3171740093
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2297194602
Short name T91
Test name
Test status
Simulation time 1387512336 ps
CPU time 11.48 seconds
Started Aug 19 05:59:24 PM PDT 24
Finished Aug 19 05:59:36 PM PDT 24
Peak memory 250408 kb
Host smart-5bc02700-274b-439f-9e9b-387cac546b88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297194602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2297194602
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.829802279
Short name T696
Test name
Test status
Simulation time 65585891 ps
CPU time 2.44 seconds
Started Aug 19 05:59:24 PM PDT 24
Finished Aug 19 05:59:26 PM PDT 24
Peak memory 218284 kb
Host smart-fec47681-64ab-4f51-8ab4-307352be88ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829802279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.829802279
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3603222130
Short name T540
Test name
Test status
Simulation time 292810642 ps
CPU time 8.53 seconds
Started Aug 19 05:59:23 PM PDT 24
Finished Aug 19 05:59:32 PM PDT 24
Peak memory 226064 kb
Host smart-ea430789-4845-43ee-8b3d-94802091af86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603222130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3603222130
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3078735627
Short name T844
Test name
Test status
Simulation time 220913818 ps
CPU time 8.5 seconds
Started Aug 19 05:59:23 PM PDT 24
Finished Aug 19 05:59:31 PM PDT 24
Peak memory 226096 kb
Host smart-e237858e-346a-47a1-880a-e06c58002217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078735627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3078735627
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1260339822
Short name T841
Test name
Test status
Simulation time 270051516 ps
CPU time 8.84 seconds
Started Aug 19 05:59:24 PM PDT 24
Finished Aug 19 05:59:33 PM PDT 24
Peak memory 218236 kb
Host smart-9a6c99f6-5e5e-4a2c-9645-33d31fab3e99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260339822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1260339822
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2241505557
Short name T22
Test name
Test status
Simulation time 283663122 ps
CPU time 7.45 seconds
Started Aug 19 05:59:24 PM PDT 24
Finished Aug 19 05:59:31 PM PDT 24
Peak memory 226088 kb
Host smart-8951ab41-ee91-475b-b3d0-79784f0673c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241505557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2241505557
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.4249523113
Short name T76
Test name
Test status
Simulation time 221275562 ps
CPU time 3.57 seconds
Started Aug 19 05:59:25 PM PDT 24
Finished Aug 19 05:59:29 PM PDT 24
Peak memory 222928 kb
Host smart-86ee34ac-20e1-49d8-be67-cd511f8b483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249523113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.4249523113
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1884314719
Short name T657
Test name
Test status
Simulation time 730550397 ps
CPU time 32.4 seconds
Started Aug 19 05:59:23 PM PDT 24
Finished Aug 19 05:59:55 PM PDT 24
Peak memory 250924 kb
Host smart-9025a713-68e8-4a1a-8591-56a6b7a04efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884314719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1884314719
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1588742187
Short name T783
Test name
Test status
Simulation time 91556152 ps
CPU time 3.3 seconds
Started Aug 19 05:59:23 PM PDT 24
Finished Aug 19 05:59:26 PM PDT 24
Peak memory 226344 kb
Host smart-9ff0d9df-964c-45c0-880a-fdfbddcfeb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588742187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1588742187
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.813884822
Short name T391
Test name
Test status
Simulation time 10194420702 ps
CPU time 199.12 seconds
Started Aug 19 05:59:22 PM PDT 24
Finished Aug 19 06:02:42 PM PDT 24
Peak memory 254272 kb
Host smart-eb588b1f-9644-4c22-a9f8-598c48664d52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813884822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.813884822
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3069197349
Short name T675
Test name
Test status
Simulation time 14632685 ps
CPU time 1.09 seconds
Started Aug 19 05:59:24 PM PDT 24
Finished Aug 19 05:59:25 PM PDT 24
Peak memory 211864 kb
Host smart-c404473b-a916-485c-a53c-c3589e00bb07
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069197349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3069197349
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3084439931
Short name T475
Test name
Test status
Simulation time 36671396 ps
CPU time 0.91 seconds
Started Aug 19 05:59:38 PM PDT 24
Finished Aug 19 05:59:39 PM PDT 24
Peak memory 208876 kb
Host smart-6e92e022-d69f-4a2f-97e3-62364f000687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084439931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3084439931
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3664591819
Short name T255
Test name
Test status
Simulation time 1588361549 ps
CPU time 16.62 seconds
Started Aug 19 05:59:34 PM PDT 24
Finished Aug 19 05:59:51 PM PDT 24
Peak memory 226128 kb
Host smart-23dc4679-c17d-4f08-8011-1630ae15c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664591819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3664591819
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4284821314
Short name T624
Test name
Test status
Simulation time 3266516840 ps
CPU time 19.17 seconds
Started Aug 19 05:59:39 PM PDT 24
Finished Aug 19 05:59:59 PM PDT 24
Peak memory 217708 kb
Host smart-18239400-0075-48a3-b8a6-c4ef936faf52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284821314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4284821314
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.4286330815
Short name T670
Test name
Test status
Simulation time 2271100959 ps
CPU time 63.55 seconds
Started Aug 19 05:59:30 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 218424 kb
Host smart-9380be15-ecf4-43b6-b56a-d95207ae7aab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286330815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.4286330815
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3514962946
Short name T739
Test name
Test status
Simulation time 2521490551 ps
CPU time 18.77 seconds
Started Aug 19 05:59:32 PM PDT 24
Finished Aug 19 05:59:51 PM PDT 24
Peak memory 225452 kb
Host smart-2db047b7-aa1d-4cf0-87dd-140d861939c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514962946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3514962946
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.644281588
Short name T315
Test name
Test status
Simulation time 185824321 ps
CPU time 5.6 seconds
Started Aug 19 05:59:36 PM PDT 24
Finished Aug 19 05:59:42 PM PDT 24
Peak memory 217584 kb
Host smart-82c688c7-2bd0-4c16-837c-ca9806914407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644281588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
644281588
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1459394580
Short name T418
Test name
Test status
Simulation time 950985311 ps
CPU time 24.88 seconds
Started Aug 19 05:59:38 PM PDT 24
Finished Aug 19 06:00:03 PM PDT 24
Peak memory 250864 kb
Host smart-82728846-e1d8-49e3-93ec-2dbabb500ba3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459394580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1459394580
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3808697829
Short name T579
Test name
Test status
Simulation time 2143927972 ps
CPU time 30.81 seconds
Started Aug 19 05:59:32 PM PDT 24
Finished Aug 19 06:00:03 PM PDT 24
Peak memory 245988 kb
Host smart-33aea174-fa34-42e6-a057-e1849fe1f5bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808697829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3808697829
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2350989516
Short name T748
Test name
Test status
Simulation time 29501750 ps
CPU time 1.67 seconds
Started Aug 19 05:59:35 PM PDT 24
Finished Aug 19 05:59:37 PM PDT 24
Peak memory 218284 kb
Host smart-35373c74-b60f-4d69-ab4d-5d08e6c0c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350989516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2350989516
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2262469555
Short name T614
Test name
Test status
Simulation time 1299402843 ps
CPU time 8.16 seconds
Started Aug 19 05:59:36 PM PDT 24
Finished Aug 19 05:59:45 PM PDT 24
Peak memory 225792 kb
Host smart-3231983f-b0ba-4965-9d99-1f9ac441c7a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262469555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2262469555
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4240701320
Short name T478
Test name
Test status
Simulation time 969115763 ps
CPU time 11.55 seconds
Started Aug 19 05:59:32 PM PDT 24
Finished Aug 19 05:59:43 PM PDT 24
Peak memory 226052 kb
Host smart-5fdcdfac-e578-47dd-bd3c-efe37452c50f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240701320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4240701320
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3285839701
Short name T554
Test name
Test status
Simulation time 307753403 ps
CPU time 7.67 seconds
Started Aug 19 05:59:31 PM PDT 24
Finished Aug 19 05:59:38 PM PDT 24
Peak memory 218240 kb
Host smart-b377bd24-29ca-4f51-8f76-24fdff6f1cb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285839701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3285839701
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.603894554
Short name T781
Test name
Test status
Simulation time 537229847 ps
CPU time 12.04 seconds
Started Aug 19 05:59:35 PM PDT 24
Finished Aug 19 05:59:48 PM PDT 24
Peak memory 218360 kb
Host smart-425d2422-4bd0-4122-bd0a-0df5a1678b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603894554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.603894554
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3286912783
Short name T85
Test name
Test status
Simulation time 26252827 ps
CPU time 1.83 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:35 PM PDT 24
Peak memory 217616 kb
Host smart-64dc92e3-f1ed-4c6c-b09c-094191fb0370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286912783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3286912783
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1949052018
Short name T389
Test name
Test status
Simulation time 314336919 ps
CPU time 28.37 seconds
Started Aug 19 05:59:32 PM PDT 24
Finished Aug 19 06:00:01 PM PDT 24
Peak memory 250972 kb
Host smart-40480bf5-84c7-41a3-850a-05b5066777e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949052018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1949052018
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3525919198
Short name T250
Test name
Test status
Simulation time 391393808 ps
CPU time 8.18 seconds
Started Aug 19 05:59:34 PM PDT 24
Finished Aug 19 05:59:42 PM PDT 24
Peak memory 250780 kb
Host smart-c97ac86e-3df9-4fd9-9cb8-ae03a6ee0aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525919198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3525919198
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3116080011
Short name T356
Test name
Test status
Simulation time 5941095098 ps
CPU time 111.61 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 279668 kb
Host smart-6cf9740e-5130-4964-9c98-32c5baada9ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116080011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3116080011
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1341251236
Short name T562
Test name
Test status
Simulation time 15340847 ps
CPU time 0.99 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:34 PM PDT 24
Peak memory 211748 kb
Host smart-a15aa96e-7822-423d-bf1b-44b8a22f4a50
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341251236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1341251236
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1084710595
Short name T543
Test name
Test status
Simulation time 16070143 ps
CPU time 1.15 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:34 PM PDT 24
Peak memory 208980 kb
Host smart-ef120ab9-c678-400c-a436-c75a6a1bc493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084710595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1084710595
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.549173487
Short name T447
Test name
Test status
Simulation time 705754985 ps
CPU time 15.26 seconds
Started Aug 19 05:59:32 PM PDT 24
Finished Aug 19 05:59:47 PM PDT 24
Peak memory 218280 kb
Host smart-eab7ebd1-20cb-4462-a3b9-3c0401ca443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549173487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.549173487
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.575065890
Short name T761
Test name
Test status
Simulation time 959160819 ps
CPU time 11.36 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:45 PM PDT 24
Peak memory 217504 kb
Host smart-5b278551-51ec-4552-94cd-581b1535642d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575065890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.575065890
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.480510068
Short name T349
Test name
Test status
Simulation time 8729695616 ps
CPU time 65.79 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 06:00:39 PM PDT 24
Peak memory 219036 kb
Host smart-8055e7b1-8746-4ced-a0f8-56ee8279b9b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480510068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.480510068
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2142831237
Short name T156
Test name
Test status
Simulation time 628989245 ps
CPU time 16.36 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:50 PM PDT 24
Peak memory 218228 kb
Host smart-4de904ea-c011-4bd8-874a-5ed69d430f14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142831237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2142831237
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3124966105
Short name T264
Test name
Test status
Simulation time 545604787 ps
CPU time 2.92 seconds
Started Aug 19 05:59:37 PM PDT 24
Finished Aug 19 05:59:40 PM PDT 24
Peak memory 217584 kb
Host smart-8b52f99f-b372-4db7-8a90-60835d85c4be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124966105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3124966105
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.276507886
Short name T357
Test name
Test status
Simulation time 2940132159 ps
CPU time 92.22 seconds
Started Aug 19 05:59:32 PM PDT 24
Finished Aug 19 06:01:05 PM PDT 24
Peak memory 276872 kb
Host smart-6bca43f6-beef-4170-aea7-1e4cc4072b08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276507886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.276507886
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2566903893
Short name T694
Test name
Test status
Simulation time 4096322681 ps
CPU time 15.87 seconds
Started Aug 19 05:59:36 PM PDT 24
Finished Aug 19 05:59:52 PM PDT 24
Peak memory 226876 kb
Host smart-f1218110-975d-4ddc-a72c-971ba87040c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566903893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2566903893
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.226147627
Short name T254
Test name
Test status
Simulation time 62820441 ps
CPU time 3.16 seconds
Started Aug 19 05:59:31 PM PDT 24
Finished Aug 19 05:59:35 PM PDT 24
Peak memory 218292 kb
Host smart-a718cc2e-a264-4812-83fd-11281a3f21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226147627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.226147627
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.178795436
Short name T446
Test name
Test status
Simulation time 1267573927 ps
CPU time 14.26 seconds
Started Aug 19 05:59:39 PM PDT 24
Finished Aug 19 05:59:54 PM PDT 24
Peak memory 218952 kb
Host smart-663b6c34-66e2-409f-afb5-60c6e53f6f14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178795436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.178795436
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.747616593
Short name T808
Test name
Test status
Simulation time 1766370407 ps
CPU time 16.16 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:49 PM PDT 24
Peak memory 226052 kb
Host smart-ad1dc63b-d8d7-450d-abe6-4a787b3859d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747616593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.747616593
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1939654933
Short name T225
Test name
Test status
Simulation time 331098075 ps
CPU time 11.29 seconds
Started Aug 19 05:59:35 PM PDT 24
Finished Aug 19 05:59:47 PM PDT 24
Peak memory 218268 kb
Host smart-5e97aaa5-5372-4d26-a74b-d5afaae404ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939654933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1939654933
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3776399425
Short name T410
Test name
Test status
Simulation time 411979028 ps
CPU time 5.19 seconds
Started Aug 19 05:59:31 PM PDT 24
Finished Aug 19 05:59:37 PM PDT 24
Peak memory 218368 kb
Host smart-a48ecaf4-13a2-4d26-ba52-5777682b0b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776399425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3776399425
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.862041957
Short name T600
Test name
Test status
Simulation time 738602361 ps
CPU time 9.47 seconds
Started Aug 19 05:59:36 PM PDT 24
Finished Aug 19 05:59:46 PM PDT 24
Peak memory 217644 kb
Host smart-02497216-7696-4a3a-ad23-1efa390887ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862041957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.862041957
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.918050579
Short name T252
Test name
Test status
Simulation time 326661043 ps
CPU time 29.52 seconds
Started Aug 19 05:59:31 PM PDT 24
Finished Aug 19 06:00:01 PM PDT 24
Peak memory 250952 kb
Host smart-8f89f5be-587b-4f20-a23d-7780cd2ebbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918050579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.918050579
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4106479610
Short name T271
Test name
Test status
Simulation time 83845723 ps
CPU time 6.61 seconds
Started Aug 19 05:59:32 PM PDT 24
Finished Aug 19 05:59:38 PM PDT 24
Peak memory 250876 kb
Host smart-dc54c1b6-359e-45d3-88fa-a38bfb6bb322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106479610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4106479610
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3538114555
Short name T618
Test name
Test status
Simulation time 764233392 ps
CPU time 15.83 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:49 PM PDT 24
Peak memory 215896 kb
Host smart-4b3007f4-5d9d-43fd-93a2-55d1b319d8a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538114555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3538114555
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.84057317
Short name T411
Test name
Test status
Simulation time 380373454 ps
CPU time 16.64 seconds
Started Aug 19 05:59:39 PM PDT 24
Finished Aug 19 05:59:56 PM PDT 24
Peak memory 226084 kb
Host smart-b375b525-872c-4727-9776-34e50f9c94b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84057317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.84057317
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1226030935
Short name T525
Test name
Test status
Simulation time 448384598 ps
CPU time 4.73 seconds
Started Aug 19 05:59:41 PM PDT 24
Finished Aug 19 05:59:46 PM PDT 24
Peak memory 217024 kb
Host smart-cd0a0d2e-1118-4860-8169-a25a54ca92cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226030935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1226030935
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.516656656
Short name T588
Test name
Test status
Simulation time 2165448799 ps
CPU time 62.7 seconds
Started Aug 19 05:59:41 PM PDT 24
Finished Aug 19 06:00:44 PM PDT 24
Peak memory 218280 kb
Host smart-6feaf349-f88f-457c-bd90-bc9402e03781
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516656656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.516656656
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2269390457
Short name T697
Test name
Test status
Simulation time 1779857644 ps
CPU time 12.05 seconds
Started Aug 19 05:59:42 PM PDT 24
Finished Aug 19 05:59:54 PM PDT 24
Peak memory 218256 kb
Host smart-7a729c03-f9ff-4f51-83c4-468e31819799
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269390457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2269390457
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2613085386
Short name T725
Test name
Test status
Simulation time 430971341 ps
CPU time 5.18 seconds
Started Aug 19 05:59:45 PM PDT 24
Finished Aug 19 05:59:51 PM PDT 24
Peak memory 217592 kb
Host smart-ca6f986f-1a6e-4d6a-a548-cb7c26583682
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613085386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2613085386
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1106980688
Short name T541
Test name
Test status
Simulation time 1185370958 ps
CPU time 50.06 seconds
Started Aug 19 05:59:44 PM PDT 24
Finished Aug 19 06:00:35 PM PDT 24
Peak memory 251804 kb
Host smart-ff6fb3a5-1c44-4073-873a-110b3ffc75db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106980688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1106980688
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2883537364
Short name T592
Test name
Test status
Simulation time 518129482 ps
CPU time 21.17 seconds
Started Aug 19 05:59:41 PM PDT 24
Finished Aug 19 06:00:02 PM PDT 24
Peak memory 243444 kb
Host smart-e2c71920-7bbc-494b-afae-6863d1697e86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883537364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2883537364
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2034532951
Short name T529
Test name
Test status
Simulation time 74622731 ps
CPU time 2.88 seconds
Started Aug 19 05:59:40 PM PDT 24
Finished Aug 19 05:59:43 PM PDT 24
Peak memory 218320 kb
Host smart-dd7e5aa6-6bbd-471b-97c1-e246a0595a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034532951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2034532951
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.971081554
Short name T423
Test name
Test status
Simulation time 1260565625 ps
CPU time 17.66 seconds
Started Aug 19 05:59:41 PM PDT 24
Finished Aug 19 05:59:59 PM PDT 24
Peak memory 218388 kb
Host smart-2faca702-6a23-42cb-a630-fd510559b263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971081554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.971081554
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2450085319
Short name T821
Test name
Test status
Simulation time 185707366 ps
CPU time 6.39 seconds
Started Aug 19 05:59:40 PM PDT 24
Finished Aug 19 05:59:46 PM PDT 24
Peak memory 226060 kb
Host smart-de699f7d-c796-4c12-ac5f-6a453957c1ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450085319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2450085319
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.701933855
Short name T656
Test name
Test status
Simulation time 445722924 ps
CPU time 11.25 seconds
Started Aug 19 05:59:41 PM PDT 24
Finished Aug 19 05:59:53 PM PDT 24
Peak memory 218248 kb
Host smart-b9da4c3d-f630-4645-af15-19b87c814994
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701933855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.701933855
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2121677472
Short name T643
Test name
Test status
Simulation time 5228759328 ps
CPU time 11.9 seconds
Started Aug 19 05:59:42 PM PDT 24
Finished Aug 19 05:59:54 PM PDT 24
Peak memory 218436 kb
Host smart-f4295113-fd2e-4ce2-8c8c-fc4056877cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121677472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2121677472
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1777215054
Short name T331
Test name
Test status
Simulation time 137002621 ps
CPU time 2.78 seconds
Started Aug 19 06:01:21 PM PDT 24
Finished Aug 19 06:01:24 PM PDT 24
Peak memory 214640 kb
Host smart-5daff5ad-9f8d-460f-a756-dd1da218ce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777215054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1777215054
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3228096777
Short name T445
Test name
Test status
Simulation time 1256277451 ps
CPU time 33.16 seconds
Started Aug 19 05:59:34 PM PDT 24
Finished Aug 19 06:00:07 PM PDT 24
Peak memory 250948 kb
Host smart-5732cfa5-7311-4d8e-8209-d075e9a6f4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228096777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3228096777
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3212312832
Short name T583
Test name
Test status
Simulation time 57071542 ps
CPU time 5.88 seconds
Started Aug 19 05:59:33 PM PDT 24
Finished Aug 19 05:59:39 PM PDT 24
Peak memory 246600 kb
Host smart-69b3ed5d-cee5-4249-a94c-0b767f8aaa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212312832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3212312832
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2912070058
Short name T496
Test name
Test status
Simulation time 2571634372 ps
CPU time 87.8 seconds
Started Aug 19 05:59:46 PM PDT 24
Finished Aug 19 06:01:14 PM PDT 24
Peak memory 268144 kb
Host smart-4df52143-2246-4649-bb53-61b454ebf698
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2912070058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2912070058
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2762380151
Short name T470
Test name
Test status
Simulation time 20012332 ps
CPU time 0.97 seconds
Started Aug 19 05:59:34 PM PDT 24
Finished Aug 19 05:59:35 PM PDT 24
Peak memory 211944 kb
Host smart-dddecfc1-e257-42fb-8a6b-f61a8a35c107
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762380151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2762380151
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.488232677
Short name T92
Test name
Test status
Simulation time 67905489 ps
CPU time 1.18 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:00 PM PDT 24
Peak memory 208992 kb
Host smart-60ae7234-7c39-42d9-8112-8b4c05071d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488232677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.488232677
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3317290874
Short name T431
Test name
Test status
Simulation time 477028743 ps
CPU time 11.89 seconds
Started Aug 19 05:59:44 PM PDT 24
Finished Aug 19 05:59:56 PM PDT 24
Peak memory 218292 kb
Host smart-c5454c15-0b50-4b8e-a43d-3dc7622e3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317290874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3317290874
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2018351458
Short name T37
Test name
Test status
Simulation time 1362325877 ps
CPU time 4.04 seconds
Started Aug 19 05:59:45 PM PDT 24
Finished Aug 19 05:59:49 PM PDT 24
Peak memory 217588 kb
Host smart-29c71e7a-a290-4168-bfdb-59e4fe21ec7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018351458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2018351458
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1268904153
Short name T409
Test name
Test status
Simulation time 2727450810 ps
CPU time 34.59 seconds
Started Aug 19 05:59:40 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 219044 kb
Host smart-9f6f851f-545e-4285-865a-ba5bccb35f9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268904153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1268904153
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1374957221
Short name T589
Test name
Test status
Simulation time 224613589 ps
CPU time 5.22 seconds
Started Aug 19 05:59:44 PM PDT 24
Finished Aug 19 05:59:49 PM PDT 24
Peak memory 218232 kb
Host smart-0ef85c7e-493c-421b-ab8b-e02b51072350
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374957221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1374957221
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3375662674
Short name T727
Test name
Test status
Simulation time 91594468 ps
CPU time 1.77 seconds
Started Aug 19 05:59:46 PM PDT 24
Finished Aug 19 05:59:48 PM PDT 24
Peak memory 217692 kb
Host smart-55acd851-8bec-4f3a-8284-c0813cf4fa60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375662674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3375662674
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2044129431
Short name T376
Test name
Test status
Simulation time 16901560095 ps
CPU time 44.83 seconds
Started Aug 19 05:59:42 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 270748 kb
Host smart-96344cd3-691a-4ddb-b5e4-3bce2a514c85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044129431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2044129431
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3835717560
Short name T796
Test name
Test status
Simulation time 535469773 ps
CPU time 15.43 seconds
Started Aug 19 05:59:43 PM PDT 24
Finished Aug 19 05:59:58 PM PDT 24
Peak memory 250756 kb
Host smart-f7b8bd78-edad-4e5a-a703-cfc5d5a5b647
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835717560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3835717560
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.4186350294
Short name T797
Test name
Test status
Simulation time 105069910 ps
CPU time 3.09 seconds
Started Aug 19 05:59:45 PM PDT 24
Finished Aug 19 05:59:48 PM PDT 24
Peak memory 218300 kb
Host smart-6bf9304f-f34a-46e4-acce-d5c7dd6dae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186350294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.4186350294
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2235186749
Short name T16
Test name
Test status
Simulation time 663095369 ps
CPU time 9.97 seconds
Started Aug 19 05:59:45 PM PDT 24
Finished Aug 19 05:59:55 PM PDT 24
Peak memory 226108 kb
Host smart-67592814-0cc2-4111-9614-f04f0db22993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235186749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2235186749
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3188377442
Short name T281
Test name
Test status
Simulation time 444372213 ps
CPU time 9.78 seconds
Started Aug 19 05:59:45 PM PDT 24
Finished Aug 19 05:59:55 PM PDT 24
Peak memory 226044 kb
Host smart-3119ae09-6051-42b2-b5dc-354b85da62ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188377442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3188377442
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2573766928
Short name T597
Test name
Test status
Simulation time 380761293 ps
CPU time 13.51 seconds
Started Aug 19 05:59:45 PM PDT 24
Finished Aug 19 05:59:59 PM PDT 24
Peak memory 226056 kb
Host smart-5ed7859d-0c9f-4e43-9170-4139c53683a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573766928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2573766928
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2505001801
Short name T208
Test name
Test status
Simulation time 1610890136 ps
CPU time 7.4 seconds
Started Aug 19 05:59:40 PM PDT 24
Finished Aug 19 05:59:48 PM PDT 24
Peak memory 225344 kb
Host smart-38eeef41-bc20-43fc-a48f-9f0b338aebac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505001801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2505001801
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3990737386
Short name T62
Test name
Test status
Simulation time 98358900 ps
CPU time 6.31 seconds
Started Aug 19 05:59:44 PM PDT 24
Finished Aug 19 05:59:51 PM PDT 24
Peak memory 217648 kb
Host smart-026e7649-e039-4c9a-b1ef-7f7a18565f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990737386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3990737386
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3201143194
Short name T859
Test name
Test status
Simulation time 1174456381 ps
CPU time 26.39 seconds
Started Aug 19 05:59:44 PM PDT 24
Finished Aug 19 06:00:11 PM PDT 24
Peak memory 246204 kb
Host smart-e9501bc5-2856-4bf0-bd7b-6291924585fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201143194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3201143194
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.37289643
Short name T742
Test name
Test status
Simulation time 69420839 ps
CPU time 7.72 seconds
Started Aug 19 05:59:44 PM PDT 24
Finished Aug 19 05:59:52 PM PDT 24
Peak memory 250912 kb
Host smart-f17be790-c170-401b-8fa6-af427839d441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37289643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.37289643
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2146022327
Short name T770
Test name
Test status
Simulation time 12508984151 ps
CPU time 209.27 seconds
Started Aug 19 05:59:42 PM PDT 24
Finished Aug 19 06:03:12 PM PDT 24
Peak memory 283828 kb
Host smart-b9c96aaa-c7e4-4ef8-bfa1-8accb50c7cb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146022327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2146022327
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1710562210
Short name T329
Test name
Test status
Simulation time 11365953 ps
CPU time 0.98 seconds
Started Aug 19 05:59:42 PM PDT 24
Finished Aug 19 05:59:43 PM PDT 24
Peak memory 211888 kb
Host smart-b921f0d8-6d0d-4f7e-b54b-40b2a03b0a37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710562210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1710562210
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.962872285
Short name T443
Test name
Test status
Simulation time 19878483 ps
CPU time 0.97 seconds
Started Aug 19 06:00:01 PM PDT 24
Finished Aug 19 06:00:02 PM PDT 24
Peak memory 208872 kb
Host smart-4946a9c5-5bcf-4bb1-b28b-6497cd65f780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962872285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.962872285
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3361469953
Short name T384
Test name
Test status
Simulation time 297733118 ps
CPU time 8.69 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:08 PM PDT 24
Peak memory 226088 kb
Host smart-91dbd114-ae07-4306-951c-cf136e099dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361469953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3361469953
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1395541714
Short name T35
Test name
Test status
Simulation time 383118015 ps
CPU time 4.65 seconds
Started Aug 19 05:59:57 PM PDT 24
Finished Aug 19 06:00:02 PM PDT 24
Peak memory 217296 kb
Host smart-3b08500a-774c-42fd-913a-d00d0d966100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395541714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1395541714
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1639076320
Short name T104
Test name
Test status
Simulation time 4530651271 ps
CPU time 46.03 seconds
Started Aug 19 05:59:57 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 218920 kb
Host smart-cb8c15fe-d9d2-4620-92df-1fbbcca32c7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639076320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1639076320
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.974363798
Short name T326
Test name
Test status
Simulation time 205105237 ps
CPU time 3.86 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:03 PM PDT 24
Peak memory 218268 kb
Host smart-35e8615c-44de-41ed-a7f1-6698f6d9d5c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974363798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.974363798
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3772717990
Short name T77
Test name
Test status
Simulation time 339163386 ps
CPU time 6.02 seconds
Started Aug 19 05:59:57 PM PDT 24
Finished Aug 19 06:00:03 PM PDT 24
Peak memory 217584 kb
Host smart-05840e81-d598-4c85-9c26-d9173de25fd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772717990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3772717990
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.889887181
Short name T26
Test name
Test status
Simulation time 9245420986 ps
CPU time 25.93 seconds
Started Aug 19 05:59:57 PM PDT 24
Finished Aug 19 06:00:23 PM PDT 24
Peak memory 250936 kb
Host smart-c9e6d09c-8597-40fc-a641-959af7d44a6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889887181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.889887181
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2834251053
Short name T244
Test name
Test status
Simulation time 4076384492 ps
CPU time 15.38 seconds
Started Aug 19 05:59:56 PM PDT 24
Finished Aug 19 06:00:12 PM PDT 24
Peak memory 226356 kb
Host smart-28a3fcaf-e381-4e2e-bd92-4781a2ad9a0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834251053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2834251053
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2631248561
Short name T759
Test name
Test status
Simulation time 269601218 ps
CPU time 2.91 seconds
Started Aug 19 06:00:01 PM PDT 24
Finished Aug 19 06:00:04 PM PDT 24
Peak memory 218248 kb
Host smart-f8f6ed00-0a48-40d1-8e35-6350be3d001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631248561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2631248561
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4042066181
Short name T360
Test name
Test status
Simulation time 1140239975 ps
CPU time 17.29 seconds
Started Aug 19 05:59:55 PM PDT 24
Finished Aug 19 06:00:12 PM PDT 24
Peak memory 226140 kb
Host smart-1ef2fc4e-3204-4cc6-8cbd-ef1e09b75e24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042066181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4042066181
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2758024917
Short name T364
Test name
Test status
Simulation time 652694319 ps
CPU time 12.68 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:11 PM PDT 24
Peak memory 225996 kb
Host smart-e0123534-6782-4a9e-b445-3065609175c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758024917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2758024917
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3893779503
Short name T21
Test name
Test status
Simulation time 1112283813 ps
CPU time 10.65 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:09 PM PDT 24
Peak memory 218272 kb
Host smart-0da690a3-87e9-4e0c-a81f-1a3f2f87fe33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893779503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3893779503
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3612331941
Short name T398
Test name
Test status
Simulation time 289969271 ps
CPU time 10.88 seconds
Started Aug 19 05:59:55 PM PDT 24
Finished Aug 19 06:00:06 PM PDT 24
Peak memory 218376 kb
Host smart-33f95edc-219e-49f7-83b3-bd9191348eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612331941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3612331941
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3549994324
Short name T644
Test name
Test status
Simulation time 690342140 ps
CPU time 3.75 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:03 PM PDT 24
Peak memory 217644 kb
Host smart-b0f3aeb6-4586-42da-a6d8-ce215ca40447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549994324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3549994324
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3261347988
Short name T353
Test name
Test status
Simulation time 748945625 ps
CPU time 21.92 seconds
Started Aug 19 06:00:00 PM PDT 24
Finished Aug 19 06:00:22 PM PDT 24
Peak memory 250900 kb
Host smart-1c841275-b424-4c81-b1a4-6e8fde0a8960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261347988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3261347988
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2161725989
Short name T374
Test name
Test status
Simulation time 201208691 ps
CPU time 7.08 seconds
Started Aug 19 05:59:57 PM PDT 24
Finished Aug 19 06:00:04 PM PDT 24
Peak memory 250924 kb
Host smart-0770f74a-c016-4cee-9d40-0b65eef9743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161725989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2161725989
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.187917361
Short name T149
Test name
Test status
Simulation time 1849465389 ps
CPU time 49.33 seconds
Started Aug 19 05:59:58 PM PDT 24
Finished Aug 19 06:00:47 PM PDT 24
Peak memory 261140 kb
Host smart-412e84e0-1db5-4930-a2e1-9da9851e5e1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=187917361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.187917361
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1416289060
Short name T628
Test name
Test status
Simulation time 28678091 ps
CPU time 0.81 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:00 PM PDT 24
Peak memory 211924 kb
Host smart-9bcd6253-0216-4378-8010-b47ee856734b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416289060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1416289060
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.53083812
Short name T218
Test name
Test status
Simulation time 20108727 ps
CPU time 1.15 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:13 PM PDT 24
Peak memory 208856 kb
Host smart-c91fd414-17b1-499a-b4d7-5b6fb581a073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53083812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.53083812
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.4201849170
Short name T102
Test name
Test status
Simulation time 678695464 ps
CPU time 10.56 seconds
Started Aug 19 05:59:58 PM PDT 24
Finished Aug 19 06:00:09 PM PDT 24
Peak memory 218168 kb
Host smart-c15774e4-9570-4cf5-870f-dff7a8a90136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201849170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.4201849170
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3434463715
Short name T863
Test name
Test status
Simulation time 4591801478 ps
CPU time 17.04 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:31 PM PDT 24
Peak memory 217696 kb
Host smart-87b7a842-fee2-4078-8fbb-309f19318362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434463715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3434463715
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.4286870120
Short name T43
Test name
Test status
Simulation time 5170207701 ps
CPU time 21.68 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 218972 kb
Host smart-3183d5f0-3e98-4886-b146-cf8ea0034487
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286870120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.4286870120
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3355130159
Short name T681
Test name
Test status
Simulation time 724618086 ps
CPU time 10.37 seconds
Started Aug 19 06:00:01 PM PDT 24
Finished Aug 19 06:00:11 PM PDT 24
Peak memory 218252 kb
Host smart-c189a524-a827-4842-b6a4-09f7b32d88fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355130159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3355130159
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2751483647
Short name T649
Test name
Test status
Simulation time 1037397550 ps
CPU time 7.41 seconds
Started Aug 19 05:59:58 PM PDT 24
Finished Aug 19 06:00:06 PM PDT 24
Peak memory 217564 kb
Host smart-fc6cc079-9ee7-4972-84d5-11c1ce1c18cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751483647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2751483647
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.662273123
Short name T31
Test name
Test status
Simulation time 4881249429 ps
CPU time 55.98 seconds
Started Aug 19 06:00:00 PM PDT 24
Finished Aug 19 06:00:56 PM PDT 24
Peak memory 268960 kb
Host smart-0c39f5ee-cb5c-4579-897f-7732588b6faa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662273123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.662273123
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1675043611
Short name T843
Test name
Test status
Simulation time 831126671 ps
CPU time 11.17 seconds
Started Aug 19 05:59:58 PM PDT 24
Finished Aug 19 06:00:09 PM PDT 24
Peak memory 245964 kb
Host smart-0d71ff4b-5614-4da2-91e3-605c3fba622a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675043611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1675043611
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3109785114
Short name T386
Test name
Test status
Simulation time 35060685 ps
CPU time 1.86 seconds
Started Aug 19 05:59:58 PM PDT 24
Finished Aug 19 06:00:00 PM PDT 24
Peak memory 218320 kb
Host smart-40f92a9a-46dd-4e50-8c9d-8f2be284d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109785114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3109785114
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3665621809
Short name T44
Test name
Test status
Simulation time 4839921989 ps
CPU time 13.53 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:25 PM PDT 24
Peak memory 226152 kb
Host smart-4fc82eda-64fc-48d3-b2ae-6ce00e67873e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665621809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3665621809
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3983320351
Short name T526
Test name
Test status
Simulation time 397741474 ps
CPU time 12.15 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:24 PM PDT 24
Peak memory 226152 kb
Host smart-9dd45dd5-3426-4643-9fce-20e9ac53ff77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983320351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3983320351
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3633786334
Short name T439
Test name
Test status
Simulation time 1762120351 ps
CPU time 9.82 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:21 PM PDT 24
Peak memory 218224 kb
Host smart-f93b2486-2e6e-45f1-85e3-9eb7d530809c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633786334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3633786334
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3787379002
Short name T325
Test name
Test status
Simulation time 2335041747 ps
CPU time 11.52 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:10 PM PDT 24
Peak memory 218488 kb
Host smart-bd9bffa2-4bf3-4f0d-a55e-60385d85c151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787379002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3787379002
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.378134587
Short name T854
Test name
Test status
Simulation time 204781668 ps
CPU time 5.44 seconds
Started Aug 19 05:59:58 PM PDT 24
Finished Aug 19 06:00:04 PM PDT 24
Peak memory 223284 kb
Host smart-d2972531-e238-41b3-975b-100fdeba3846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378134587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.378134587
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.462065482
Short name T811
Test name
Test status
Simulation time 788552609 ps
CPU time 31.92 seconds
Started Aug 19 06:00:01 PM PDT 24
Finished Aug 19 06:00:33 PM PDT 24
Peak memory 250940 kb
Host smart-0af809fa-6656-4a41-a8d6-d76c82da2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462065482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.462065482
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1864436367
Short name T481
Test name
Test status
Simulation time 260373544 ps
CPU time 6.54 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:06 PM PDT 24
Peak memory 247164 kb
Host smart-44d6588e-73fe-4c67-b16d-9398aaa79b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864436367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1864436367
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2866349767
Short name T845
Test name
Test status
Simulation time 7421721544 ps
CPU time 52.02 seconds
Started Aug 19 06:00:17 PM PDT 24
Finished Aug 19 06:01:10 PM PDT 24
Peak memory 248300 kb
Host smart-868924b2-c3c2-42b5-ba96-a111e9bd3e57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866349767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2866349767
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3930984578
Short name T347
Test name
Test status
Simulation time 15566352 ps
CPU time 0.73 seconds
Started Aug 19 05:59:59 PM PDT 24
Finished Aug 19 06:00:00 PM PDT 24
Peak memory 207424 kb
Host smart-3111e66c-54a8-42dc-9ae2-b1881efb7613
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930984578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3930984578
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.297128837
Short name T198
Test name
Test status
Simulation time 54097645 ps
CPU time 0.86 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 208876 kb
Host smart-b106db6a-22bd-4385-9c8d-6b46da9cc8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297128837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.297128837
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2767902307
Short name T626
Test name
Test status
Simulation time 627170474 ps
CPU time 15.36 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 218328 kb
Host smart-6a8fe914-35b4-49fc-9f96-710565d03256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767902307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2767902307
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2646402034
Short name T638
Test name
Test status
Simulation time 29244967 ps
CPU time 1.08 seconds
Started Aug 19 06:00:10 PM PDT 24
Finished Aug 19 06:00:12 PM PDT 24
Peak memory 217116 kb
Host smart-e2deaf2e-f448-4137-9929-b6bc9c02f50a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646402034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2646402034
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2120409884
Short name T658
Test name
Test status
Simulation time 9353499632 ps
CPU time 35.48 seconds
Started Aug 19 06:00:10 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 218292 kb
Host smart-2f7e5763-e68c-4fd6-a235-7b91c8d24424
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120409884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2120409884
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.826357474
Short name T448
Test name
Test status
Simulation time 422831464 ps
CPU time 6.29 seconds
Started Aug 19 06:00:17 PM PDT 24
Finished Aug 19 06:00:24 PM PDT 24
Peak memory 218136 kb
Host smart-e3fa0226-11cf-4ecf-9595-a0ca6ee49290
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826357474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.826357474
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3919324478
Short name T871
Test name
Test status
Simulation time 569742938 ps
CPU time 14.76 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 217588 kb
Host smart-6082a97c-2534-4c25-8647-6bf047fc4699
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919324478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3919324478
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.149689356
Short name T674
Test name
Test status
Simulation time 27773646762 ps
CPU time 34.2 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:00:47 PM PDT 24
Peak memory 275704 kb
Host smart-142faaf4-0c68-4115-b99b-8c0f23c522bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149689356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.149689356
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4010953065
Short name T340
Test name
Test status
Simulation time 672280476 ps
CPU time 19.77 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:32 PM PDT 24
Peak memory 223212 kb
Host smart-66ff576a-ae63-4c5e-a0bd-e6b324b7e7ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010953065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4010953065
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3941346707
Short name T749
Test name
Test status
Simulation time 77017183 ps
CPU time 2.56 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:14 PM PDT 24
Peak memory 222172 kb
Host smart-d6b3ed6f-6a23-438e-b802-2ca5940ded03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941346707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3941346707
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3801042219
Short name T840
Test name
Test status
Simulation time 557353945 ps
CPU time 11.84 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:24 PM PDT 24
Peak memory 218948 kb
Host smart-1dd83eb3-80be-4734-a2f6-f72f5ab8d749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801042219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3801042219
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.938874541
Short name T267
Test name
Test status
Simulation time 434156898 ps
CPU time 13.07 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:25 PM PDT 24
Peak memory 226048 kb
Host smart-befa41c1-1c62-4e14-998d-43af614333d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938874541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.938874541
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3776123297
Short name T341
Test name
Test status
Simulation time 1757529380 ps
CPU time 7.15 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:21 PM PDT 24
Peak memory 218288 kb
Host smart-d0d92eb9-99a7-493e-ba6c-8819dd265992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776123297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3776123297
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3589239202
Short name T587
Test name
Test status
Simulation time 3701354173 ps
CPU time 17.63 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:29 PM PDT 24
Peak memory 226164 kb
Host smart-7effa997-7ddb-42b1-ae80-3f5b7ebf0458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589239202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3589239202
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2766087794
Short name T81
Test name
Test status
Simulation time 102000077 ps
CPU time 3.34 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 217680 kb
Host smart-3bfab3e4-0123-46f8-b267-83c8483fcd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766087794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2766087794
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1834224492
Short name T430
Test name
Test status
Simulation time 1207098213 ps
CPU time 27.07 seconds
Started Aug 19 06:00:15 PM PDT 24
Finished Aug 19 06:00:42 PM PDT 24
Peak memory 250920 kb
Host smart-363f021c-1b2b-434a-a336-7b00956a55ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834224492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1834224492
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.818276173
Short name T455
Test name
Test status
Simulation time 269354305 ps
CPU time 3.47 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 226380 kb
Host smart-607a9d1c-1b89-4671-8d05-a92bdc098a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818276173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.818276173
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4270777180
Short name T420
Test name
Test status
Simulation time 23019629838 ps
CPU time 728.42 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:12:21 PM PDT 24
Peak memory 315492 kb
Host smart-3be85ace-87e8-4ff8-823a-2bcab76cf961
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270777180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4270777180
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3162181162
Short name T733
Test name
Test status
Simulation time 1606597152 ps
CPU time 16.37 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:00:29 PM PDT 24
Peak memory 249192 kb
Host smart-e677165f-a5e1-4b7d-95f0-08507601cc11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3162181162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3162181162
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.251935462
Short name T436
Test name
Test status
Simulation time 38495642 ps
CPU time 0.83 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:12 PM PDT 24
Peak memory 212032 kb
Host smart-a1091b31-f01f-42ab-bfe5-83b5e52b0508
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251935462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.251935462
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2255240979
Short name T236
Test name
Test status
Simulation time 266699257 ps
CPU time 1.01 seconds
Started Aug 19 05:57:57 PM PDT 24
Finished Aug 19 05:57:58 PM PDT 24
Peak memory 208932 kb
Host smart-0b1c85ee-7933-44e4-a43c-c984471ca02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255240979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2255240979
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3256456361
Short name T619
Test name
Test status
Simulation time 30881267 ps
CPU time 0.9 seconds
Started Aug 19 05:57:51 PM PDT 24
Finished Aug 19 05:57:52 PM PDT 24
Peak memory 208752 kb
Host smart-68d73e71-e673-468d-8158-8a4d952455d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256456361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3256456361
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3048213755
Short name T615
Test name
Test status
Simulation time 807670694 ps
CPU time 8.94 seconds
Started Aug 19 05:57:56 PM PDT 24
Finished Aug 19 05:58:05 PM PDT 24
Peak memory 217368 kb
Host smart-e4560412-09b3-48c1-87f6-97bd09947875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048213755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3048213755
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.506448851
Short name T157
Test name
Test status
Simulation time 5912364059 ps
CPU time 34.65 seconds
Started Aug 19 05:57:48 PM PDT 24
Finished Aug 19 05:58:23 PM PDT 24
Peak memory 218228 kb
Host smart-0df58534-eb77-4bc3-bb82-e8a9c60a8aae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506448851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.506448851
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1228059679
Short name T8
Test name
Test status
Simulation time 4319716909 ps
CPU time 8.12 seconds
Started Aug 19 05:57:53 PM PDT 24
Finished Aug 19 05:58:01 PM PDT 24
Peak memory 217768 kb
Host smart-3ade1156-a0cc-47b9-baeb-d42f2c91a752
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228059679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
228059679
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2383485434
Short name T335
Test name
Test status
Simulation time 5575169585 ps
CPU time 9.27 seconds
Started Aug 19 05:57:47 PM PDT 24
Finished Aug 19 05:57:57 PM PDT 24
Peak memory 218304 kb
Host smart-000b24bf-d36d-4879-8234-e0bcde10cc57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383485434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2383485434
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1534406259
Short name T799
Test name
Test status
Simulation time 1383780743 ps
CPU time 11.58 seconds
Started Aug 19 05:57:59 PM PDT 24
Finished Aug 19 05:58:10 PM PDT 24
Peak memory 217584 kb
Host smart-78e3134c-7134-4b1d-bb51-f571534cec52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534406259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1534406259
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.874830182
Short name T106
Test name
Test status
Simulation time 1283288862 ps
CPU time 8.44 seconds
Started Aug 19 05:57:51 PM PDT 24
Finished Aug 19 05:57:59 PM PDT 24
Peak memory 217600 kb
Host smart-435b9025-6662-4fdb-a13c-5cc741ad2bd4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874830182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.874830182
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.35356966
Short name T97
Test name
Test status
Simulation time 10862537020 ps
CPU time 100.59 seconds
Started Aug 19 05:57:46 PM PDT 24
Finished Aug 19 05:59:27 PM PDT 24
Peak memory 267304 kb
Host smart-bba75927-9930-4b79-a4c5-1c672677e43e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35356966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
state_failure.35356966
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1152693171
Short name T798
Test name
Test status
Simulation time 526857685 ps
CPU time 16.21 seconds
Started Aug 19 05:57:47 PM PDT 24
Finished Aug 19 05:58:03 PM PDT 24
Peak memory 223284 kb
Host smart-aa879b19-e1c2-4e77-b8bf-eb5fcd4986fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152693171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1152693171
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.392914004
Short name T691
Test name
Test status
Simulation time 378173566 ps
CPU time 3.47 seconds
Started Aug 19 05:57:42 PM PDT 24
Finished Aug 19 05:57:45 PM PDT 24
Peak memory 218308 kb
Host smart-10f4f25a-a028-472e-82c4-257b4762981c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392914004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.392914004
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1470370663
Short name T813
Test name
Test status
Simulation time 1254222263 ps
CPU time 9.05 seconds
Started Aug 19 05:57:47 PM PDT 24
Finished Aug 19 05:57:56 PM PDT 24
Peak memory 217672 kb
Host smart-51a7cd41-081e-4ca7-9a78-b661f0c940d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470370663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1470370663
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3915127219
Short name T57
Test name
Test status
Simulation time 943669217 ps
CPU time 36.24 seconds
Started Aug 19 05:57:55 PM PDT 24
Finished Aug 19 05:58:31 PM PDT 24
Peak memory 269944 kb
Host smart-06b236f5-3409-44b9-9fa1-ff146e39d472
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915127219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3915127219
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1018179167
Short name T809
Test name
Test status
Simulation time 307247149 ps
CPU time 14.89 seconds
Started Aug 19 05:57:58 PM PDT 24
Finished Aug 19 05:58:13 PM PDT 24
Peak memory 226080 kb
Host smart-0de2010b-a2fb-4d03-b22d-aee9b7622276
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018179167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1018179167
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3987412038
Short name T471
Test name
Test status
Simulation time 862513744 ps
CPU time 9.94 seconds
Started Aug 19 05:58:00 PM PDT 24
Finished Aug 19 05:58:10 PM PDT 24
Peak memory 226020 kb
Host smart-a8da8b71-f438-4fda-b98c-9fb4bae05a49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987412038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3987412038
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3531053
Short name T503
Test name
Test status
Simulation time 368503333 ps
CPU time 8.65 seconds
Started Aug 19 05:57:57 PM PDT 24
Finished Aug 19 05:58:05 PM PDT 24
Peak memory 218236 kb
Host smart-126cb06d-d524-45f1-a4f5-0a361e56c47f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3531053
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3103299159
Short name T780
Test name
Test status
Simulation time 274085994 ps
CPU time 10.11 seconds
Started Aug 19 05:57:46 PM PDT 24
Finished Aug 19 05:57:56 PM PDT 24
Peak memory 218360 kb
Host smart-f0d39816-0751-4892-9d36-fa3c644610e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103299159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3103299159
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2876706604
Short name T856
Test name
Test status
Simulation time 53529983 ps
CPU time 1.88 seconds
Started Aug 19 05:57:41 PM PDT 24
Finished Aug 19 05:57:43 PM PDT 24
Peak memory 217660 kb
Host smart-c320bd45-6ead-4e19-8bc5-faf35f9fb5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876706604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2876706604
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2018292906
Short name T284
Test name
Test status
Simulation time 1181423855 ps
CPU time 25.64 seconds
Started Aug 19 05:57:40 PM PDT 24
Finished Aug 19 05:58:06 PM PDT 24
Peak memory 250656 kb
Host smart-30a80377-fb85-4c05-9958-e970460c7bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018292906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2018292906
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.828380619
Short name T166
Test name
Test status
Simulation time 49886408 ps
CPU time 6.96 seconds
Started Aug 19 05:57:42 PM PDT 24
Finished Aug 19 05:57:49 PM PDT 24
Peak memory 250924 kb
Host smart-fab29e49-ed0d-4c65-bb77-7d589f74736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828380619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.828380619
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3119221917
Short name T555
Test name
Test status
Simulation time 4844520956 ps
CPU time 36.16 seconds
Started Aug 19 05:57:52 PM PDT 24
Finished Aug 19 05:58:29 PM PDT 24
Peak memory 250980 kb
Host smart-e01186ae-f885-46c9-bf1c-cbff5242d94a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119221917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3119221917
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1618041856
Short name T150
Test name
Test status
Simulation time 32544573478 ps
CPU time 114.21 seconds
Started Aug 19 05:57:55 PM PDT 24
Finished Aug 19 05:59:50 PM PDT 24
Peak memory 282960 kb
Host smart-aa134ac4-9545-48ab-b03d-008d59b0a794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1618041856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.1618041856
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2678082494
Short name T864
Test name
Test status
Simulation time 32693109 ps
CPU time 0.94 seconds
Started Aug 19 05:57:39 PM PDT 24
Finished Aug 19 05:57:40 PM PDT 24
Peak memory 211924 kb
Host smart-3f3b3958-99f9-4842-9635-3389043722ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678082494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2678082494
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.586471794
Short name T75
Test name
Test status
Simulation time 61771063 ps
CPU time 1.04 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:12 PM PDT 24
Peak memory 208996 kb
Host smart-2d5dfc58-b4c8-42ce-b605-6e8f69365c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586471794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.586471794
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1835893767
Short name T601
Test name
Test status
Simulation time 2075626689 ps
CPU time 14.11 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:28 PM PDT 24
Peak memory 226088 kb
Host smart-b0892d16-89ed-4e62-9a76-a622b33be07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835893767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1835893767
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3560977641
Short name T594
Test name
Test status
Simulation time 2317871449 ps
CPU time 6.03 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:20 PM PDT 24
Peak memory 217472 kb
Host smart-10c3e3f3-1595-4930-95e1-d58eee79b05c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560977641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3560977641
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.392540937
Short name T217
Test name
Test status
Simulation time 112577754 ps
CPU time 2.97 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 218284 kb
Host smart-c07736b1-4cba-4237-90a0-4b9344cc8120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392540937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.392540937
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.417047874
Short name T375
Test name
Test status
Simulation time 1323577722 ps
CPU time 14.77 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:26 PM PDT 24
Peak memory 219992 kb
Host smart-e49601f1-0404-47e1-9da4-940bf478c182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417047874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.417047874
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1812143188
Short name T253
Test name
Test status
Simulation time 4232523757 ps
CPU time 21.9 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 226076 kb
Host smart-5dda9ea3-ab64-4157-96a4-4c5b5bf3fd85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812143188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1812143188
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2969526248
Short name T504
Test name
Test status
Simulation time 1469364964 ps
CPU time 13.4 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:28 PM PDT 24
Peak memory 218228 kb
Host smart-a7b2f9a8-4336-4713-a643-0ebf0b5142e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969526248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2969526248
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4262817401
Short name T59
Test name
Test status
Simulation time 1812203992 ps
CPU time 9.14 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:00:22 PM PDT 24
Peak memory 226116 kb
Host smart-d208b5b8-24aa-4c42-9466-1f015316afc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262817401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4262817401
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3460368693
Short name T737
Test name
Test status
Simulation time 71381811 ps
CPU time 1.31 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:13 PM PDT 24
Peak memory 213572 kb
Host smart-fd08284c-a41b-4ca1-9e38-7f8671a7c63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460368693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3460368693
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3064833021
Short name T500
Test name
Test status
Simulation time 220083196 ps
CPU time 27.2 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:40 PM PDT 24
Peak memory 246376 kb
Host smart-27e98d3a-fa94-4e8b-bb6e-4a59ac5ca452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064833021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3064833021
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.236165804
Short name T474
Test name
Test status
Simulation time 406591020 ps
CPU time 3.62 seconds
Started Aug 19 06:00:11 PM PDT 24
Finished Aug 19 06:00:15 PM PDT 24
Peak memory 222784 kb
Host smart-4df59db2-6a6b-44ed-865a-d2e13d30f95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236165804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.236165804
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1767907727
Short name T582
Test name
Test status
Simulation time 3040884236 ps
CPU time 94.69 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 283596 kb
Host smart-524b1ffb-a837-43c1-a3b9-40d4fe5f6dc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767907727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1767907727
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2768085110
Short name T731
Test name
Test status
Simulation time 32122998 ps
CPU time 1.09 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:00:14 PM PDT 24
Peak memory 217912 kb
Host smart-6e05f0e9-7283-4582-aff3-3dec098f7880
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768085110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2768085110
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1080887865
Short name T532
Test name
Test status
Simulation time 18575622 ps
CPU time 0.94 seconds
Started Aug 19 06:00:28 PM PDT 24
Finished Aug 19 06:00:29 PM PDT 24
Peak memory 208856 kb
Host smart-18f6616e-a551-4252-af10-91eacde43376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080887865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1080887865
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.304011591
Short name T699
Test name
Test status
Simulation time 1668249384 ps
CPU time 8.68 seconds
Started Aug 19 06:00:15 PM PDT 24
Finished Aug 19 06:00:23 PM PDT 24
Peak memory 218312 kb
Host smart-95e48130-3578-4177-8312-8f98716568c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304011591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.304011591
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.692211588
Short name T459
Test name
Test status
Simulation time 55827970 ps
CPU time 1.41 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:14 PM PDT 24
Peak memory 216988 kb
Host smart-5dda3e34-3005-40fc-814a-e2644aba20f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692211588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.692211588
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.965145031
Short name T20
Test name
Test status
Simulation time 823522824 ps
CPU time 16.4 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:30 PM PDT 24
Peak memory 220000 kb
Host smart-ebb81a00-7a16-4d57-bb55-5c3888610248
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965145031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.965145031
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1016880483
Short name T766
Test name
Test status
Simulation time 641352103 ps
CPU time 12.47 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 226020 kb
Host smart-3ea787b6-fc70-4b55-a34f-7aa6cf435d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016880483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1016880483
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3264458003
Short name T274
Test name
Test status
Simulation time 2051616646 ps
CPU time 9.03 seconds
Started Aug 19 06:00:17 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 218008 kb
Host smart-1b206d6f-bc63-4d6c-a8cb-5093f836d1d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264458003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3264458003
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2652946584
Short name T50
Test name
Test status
Simulation time 789551369 ps
CPU time 6.44 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:00:19 PM PDT 24
Peak memory 225176 kb
Host smart-30263985-d9f2-4f98-a4cb-c1ca8019a882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652946584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2652946584
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1951705156
Short name T490
Test name
Test status
Simulation time 989980916 ps
CPU time 8.73 seconds
Started Aug 19 06:00:12 PM PDT 24
Finished Aug 19 06:00:21 PM PDT 24
Peak memory 217632 kb
Host smart-cc2ccc42-666c-416f-b572-3385e773e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951705156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1951705156
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.883371952
Short name T155
Test name
Test status
Simulation time 776481702 ps
CPU time 21.7 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 251020 kb
Host smart-621709cf-3ac1-46bc-95c5-be37878a7000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883371952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.883371952
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.558008867
Short name T603
Test name
Test status
Simulation time 836375089 ps
CPU time 6.91 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:00:20 PM PDT 24
Peak memory 250528 kb
Host smart-af6fb8ec-db8f-4daa-aa62-c0ff1696eadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558008867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.558008867
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3393703723
Short name T810
Test name
Test status
Simulation time 3456995220 ps
CPU time 71.96 seconds
Started Aug 19 06:00:14 PM PDT 24
Finished Aug 19 06:01:26 PM PDT 24
Peak memory 272416 kb
Host smart-ae736a9d-4552-4991-965f-6b6f97fb5dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393703723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3393703723
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2347163107
Short name T108
Test name
Test status
Simulation time 13596041800 ps
CPU time 87.68 seconds
Started Aug 19 06:00:13 PM PDT 24
Finished Aug 19 06:01:41 PM PDT 24
Peak memory 283824 kb
Host smart-2fba3d0b-a121-447a-8d29-ea99bdd8d997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2347163107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2347163107
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1381052121
Short name T243
Test name
Test status
Simulation time 25670685 ps
CPU time 1.02 seconds
Started Aug 19 06:00:17 PM PDT 24
Finished Aug 19 06:00:18 PM PDT 24
Peak memory 217808 kb
Host smart-ea3e35f9-9520-450a-95d9-35fe717c309a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381052121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1381052121
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4050071819
Short name T238
Test name
Test status
Simulation time 47525594 ps
CPU time 0.85 seconds
Started Aug 19 06:00:28 PM PDT 24
Finished Aug 19 06:00:29 PM PDT 24
Peak memory 208832 kb
Host smart-725ad37b-a1c1-452d-8602-4fedeee6c6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050071819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4050071819
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3486840678
Short name T390
Test name
Test status
Simulation time 354680009 ps
CPU time 15.81 seconds
Started Aug 19 06:00:21 PM PDT 24
Finished Aug 19 06:00:37 PM PDT 24
Peak memory 218292 kb
Host smart-1ff36d03-7af7-4865-95b1-0bad9f5c9881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486840678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3486840678
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.705575027
Short name T337
Test name
Test status
Simulation time 101781722 ps
CPU time 2.96 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:00:29 PM PDT 24
Peak memory 217128 kb
Host smart-0550138f-edcf-4da1-b029-6b8919898063
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705575027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.705575027
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.730771756
Short name T351
Test name
Test status
Simulation time 25461916 ps
CPU time 1.71 seconds
Started Aug 19 06:00:22 PM PDT 24
Finished Aug 19 06:00:24 PM PDT 24
Peak memory 218328 kb
Host smart-121b8974-3074-4a2c-9759-7c9b3e3eebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730771756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.730771756
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3150954391
Short name T495
Test name
Test status
Simulation time 252280564 ps
CPU time 8.09 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 226212 kb
Host smart-e34c0e2d-f84f-44e7-a9d0-b848db13ce9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150954391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3150954391
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2631894024
Short name T222
Test name
Test status
Simulation time 1087296215 ps
CPU time 23.64 seconds
Started Aug 19 06:00:22 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 226016 kb
Host smart-5bf76415-4426-4041-9023-9ba13efba99b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631894024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2631894024
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2307994780
Short name T413
Test name
Test status
Simulation time 969225145 ps
CPU time 8.41 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:00:35 PM PDT 24
Peak memory 218228 kb
Host smart-0818bd42-b751-4d1f-8687-1d78c0129af5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307994780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2307994780
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.733014629
Short name T491
Test name
Test status
Simulation time 1148034008 ps
CPU time 11.24 seconds
Started Aug 19 06:00:27 PM PDT 24
Finished Aug 19 06:00:38 PM PDT 24
Peak memory 226092 kb
Host smart-077d5644-8026-4d12-b91c-13bfb11cd53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733014629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.733014629
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.805502784
Short name T567
Test name
Test status
Simulation time 62891666 ps
CPU time 1.5 seconds
Started Aug 19 06:00:31 PM PDT 24
Finished Aug 19 06:00:32 PM PDT 24
Peak memory 213876 kb
Host smart-6a1d15af-a0cb-4a67-80b3-be382fe299b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805502784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.805502784
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.408976759
Short name T338
Test name
Test status
Simulation time 277396868 ps
CPU time 23.24 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:00:44 PM PDT 24
Peak memory 247348 kb
Host smart-9feb4599-2d0c-417a-97bb-f4a078dae296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408976759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.408976759
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4255198922
Short name T522
Test name
Test status
Simulation time 91041035 ps
CPU time 3.23 seconds
Started Aug 19 06:00:21 PM PDT 24
Finished Aug 19 06:00:25 PM PDT 24
Peak memory 218228 kb
Host smart-abd872e7-2d74-4c49-ac47-bd05282d3b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255198922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4255198922
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3656562910
Short name T848
Test name
Test status
Simulation time 8783783795 ps
CPU time 148.69 seconds
Started Aug 19 06:00:31 PM PDT 24
Finished Aug 19 06:02:59 PM PDT 24
Peak memory 250980 kb
Host smart-bd21b0df-c1b5-47ee-98a1-d07c022ff1f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656562910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3656562910
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3578763891
Short name T461
Test name
Test status
Simulation time 13035755 ps
CPU time 0.87 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:00:21 PM PDT 24
Peak memory 211912 kb
Host smart-f22eae30-631d-4b50-aff4-319f32f19cc7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578763891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3578763891
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1663626826
Short name T404
Test name
Test status
Simulation time 19084627 ps
CPU time 0.9 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 208836 kb
Host smart-f6fd16db-3a7d-4981-b90a-cb1a0865c50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663626826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1663626826
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3536774004
Short name T684
Test name
Test status
Simulation time 1012950050 ps
CPU time 11.81 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:00:38 PM PDT 24
Peak memory 226164 kb
Host smart-5881d73f-7078-41a5-add6-2012e978d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536774004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3536774004
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2870538954
Short name T242
Test name
Test status
Simulation time 119774803 ps
CPU time 1.25 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:00:22 PM PDT 24
Peak memory 217044 kb
Host smart-48e209a3-cc54-446e-b10e-d93574824e04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870538954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2870538954
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3359694230
Short name T233
Test name
Test status
Simulation time 166675453 ps
CPU time 3.06 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:00:24 PM PDT 24
Peak memory 222424 kb
Host smart-d4429732-c596-48f0-b730-5ccf139efb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359694230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3359694230
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4193490716
Short name T782
Test name
Test status
Simulation time 288427139 ps
CPU time 9.96 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:00:30 PM PDT 24
Peak memory 226108 kb
Host smart-c20628af-6865-4faf-be48-c156f5d260e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193490716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4193490716
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1971402746
Short name T591
Test name
Test status
Simulation time 3133358583 ps
CPU time 12.05 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:00:32 PM PDT 24
Peak memory 226112 kb
Host smart-0fa613e6-8c98-440e-aafd-e9df0eabdb9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971402746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1971402746
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.333680676
Short name T487
Test name
Test status
Simulation time 1917326241 ps
CPU time 11.14 seconds
Started Aug 19 06:00:21 PM PDT 24
Finished Aug 19 06:00:32 PM PDT 24
Peak memory 218236 kb
Host smart-265838af-9783-4dae-9671-b636bf6d4338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333680676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.333680676
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2011579199
Short name T477
Test name
Test status
Simulation time 414559717 ps
CPU time 13.74 seconds
Started Aug 19 06:00:21 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 225316 kb
Host smart-274aff8a-bcd7-4929-9929-203c95fd7361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011579199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2011579199
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.717412332
Short name T344
Test name
Test status
Simulation time 29695382 ps
CPU time 2.03 seconds
Started Aug 19 06:00:21 PM PDT 24
Finished Aug 19 06:00:23 PM PDT 24
Peak memory 213920 kb
Host smart-fc39ad7b-581b-4cf7-931b-5516b6e7163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717412332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.717412332
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1748392320
Short name T536
Test name
Test status
Simulation time 314711027 ps
CPU time 29.24 seconds
Started Aug 19 06:00:31 PM PDT 24
Finished Aug 19 06:01:00 PM PDT 24
Peak memory 250936 kb
Host smart-77a2c54f-a87b-455b-8165-01c6be15ef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748392320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1748392320
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.952498224
Short name T762
Test name
Test status
Simulation time 63697506 ps
CPU time 9.04 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:00:35 PM PDT 24
Peak memory 250924 kb
Host smart-3c3bc23c-b3de-4078-bf8b-a8e4b2e5219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952498224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.952498224
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3455277168
Short name T305
Test name
Test status
Simulation time 11580867654 ps
CPU time 163.68 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:03:04 PM PDT 24
Peak memory 251212 kb
Host smart-9434aed0-d70c-4e04-932a-7348c3076ff9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455277168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3455277168
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1883072577
Short name T100
Test name
Test status
Simulation time 4455036259 ps
CPU time 132.73 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:02:39 PM PDT 24
Peak memory 267468 kb
Host smart-c29b8853-38cf-45fb-9aa6-179db5b53d71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1883072577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1883072577
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.282413858
Short name T728
Test name
Test status
Simulation time 75577914 ps
CPU time 0.81 seconds
Started Aug 19 06:00:17 PM PDT 24
Finished Aug 19 06:00:18 PM PDT 24
Peak memory 211896 kb
Host smart-69fe3f89-8d94-45c7-a947-3b611c055060
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282413858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.282413858
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3965054682
Short name T831
Test name
Test status
Simulation time 21829226 ps
CPU time 1.19 seconds
Started Aug 19 06:00:29 PM PDT 24
Finished Aug 19 06:00:30 PM PDT 24
Peak memory 208920 kb
Host smart-45db97dc-f845-44a0-8ba6-27acddda9d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965054682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3965054682
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.588274452
Short name T679
Test name
Test status
Simulation time 2002272734 ps
CPU time 15.28 seconds
Started Aug 19 06:00:21 PM PDT 24
Finished Aug 19 06:00:36 PM PDT 24
Peak memory 226096 kb
Host smart-025694c4-25bb-4007-acd3-770010579c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588274452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.588274452
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3773101699
Short name T860
Test name
Test status
Simulation time 430798214 ps
CPU time 5.11 seconds
Started Aug 19 06:00:21 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 217288 kb
Host smart-88322ca3-5a0e-4527-829e-c8ecc51cf0e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773101699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3773101699
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1455147957
Short name T722
Test name
Test status
Simulation time 407545639 ps
CPU time 2.14 seconds
Started Aug 19 06:00:28 PM PDT 24
Finished Aug 19 06:00:30 PM PDT 24
Peak memory 222176 kb
Host smart-9dc990f0-bcf1-4582-aa2e-091b185b5047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455147957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1455147957
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3320967835
Short name T259
Test name
Test status
Simulation time 882618056 ps
CPU time 7.6 seconds
Started Aug 19 06:00:25 PM PDT 24
Finished Aug 19 06:00:33 PM PDT 24
Peak memory 218328 kb
Host smart-c1e7000a-f790-403b-95e2-c4ee19156e6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320967835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3320967835
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.142291339
Short name T768
Test name
Test status
Simulation time 1420636712 ps
CPU time 18.71 seconds
Started Aug 19 06:00:28 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 226024 kb
Host smart-d53767ad-1b43-4f3c-b045-2171f3330847
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142291339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.142291339
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3900392435
Short name T292
Test name
Test status
Simulation time 1385302224 ps
CPU time 9.08 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:39 PM PDT 24
Peak memory 218280 kb
Host smart-3fb18453-2dcb-445f-9bd0-4d924af742d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900392435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3900392435
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2255354147
Short name T327
Test name
Test status
Simulation time 501745203 ps
CPU time 6.7 seconds
Started Aug 19 06:00:22 PM PDT 24
Finished Aug 19 06:00:29 PM PDT 24
Peak memory 224476 kb
Host smart-f6b26fcd-7a5b-4b19-8484-7f63d9cc5bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255354147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2255354147
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1603150637
Short name T40
Test name
Test status
Simulation time 36798855 ps
CPU time 2.53 seconds
Started Aug 19 06:00:29 PM PDT 24
Finished Aug 19 06:00:32 PM PDT 24
Peak memory 223644 kb
Host smart-d8d96e9f-04d3-46c1-bde1-bc6941691a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603150637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1603150637
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3200873542
Short name T779
Test name
Test status
Simulation time 2946008085 ps
CPU time 32.43 seconds
Started Aug 19 06:00:20 PM PDT 24
Finished Aug 19 06:00:52 PM PDT 24
Peak memory 248340 kb
Host smart-2c536982-7662-446a-acc1-9319e5dc58b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200873542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3200873542
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1711805297
Short name T608
Test name
Test status
Simulation time 266657166 ps
CPU time 6.66 seconds
Started Aug 19 06:00:19 PM PDT 24
Finished Aug 19 06:00:25 PM PDT 24
Peak memory 250496 kb
Host smart-71be4d50-8ddd-4c9b-8b9d-69dcef2313d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711805297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1711805297
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.695891227
Short name T801
Test name
Test status
Simulation time 1263541991 ps
CPU time 19.48 seconds
Started Aug 19 06:00:27 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 226172 kb
Host smart-d3494dfd-93b4-4da5-b9b6-45c5fd5771c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695891227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.695891227
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.769675688
Short name T94
Test name
Test status
Simulation time 3941262094 ps
CPU time 192.65 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:03:39 PM PDT 24
Peak memory 273940 kb
Host smart-2946a83c-2198-46f8-99c9-f487a8786392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=769675688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.769675688
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1211114722
Short name T640
Test name
Test status
Simulation time 24826066 ps
CPU time 0.98 seconds
Started Aug 19 06:00:26 PM PDT 24
Finished Aug 19 06:00:27 PM PDT 24
Peak memory 211916 kb
Host smart-fcde38ca-66c1-4a1c-9332-ea17cc2fed48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211114722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1211114722
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.625827636
Short name T227
Test name
Test status
Simulation time 29399790 ps
CPU time 0.87 seconds
Started Aug 19 06:00:29 PM PDT 24
Finished Aug 19 06:00:30 PM PDT 24
Peak memory 208816 kb
Host smart-6ecabad6-3476-455b-9310-722dad7b6006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625827636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.625827636
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.4238464319
Short name T170
Test name
Test status
Simulation time 1580252029 ps
CPU time 12.79 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 226120 kb
Host smart-3ba1974f-1a1a-4689-b1c6-a27dbb46cd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238464319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4238464319
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.789321892
Short name T634
Test name
Test status
Simulation time 298782921 ps
CPU time 2.5 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:33 PM PDT 24
Peak memory 217044 kb
Host smart-24ac9ad7-5503-438d-acf0-2cffade0008a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789321892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.789321892
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3486770528
Short name T2
Test name
Test status
Simulation time 56371359 ps
CPU time 2.62 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:33 PM PDT 24
Peak memory 218316 kb
Host smart-0b2f4613-7cb8-4e4f-b4ab-9c96d48b8917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486770528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3486770528
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.217243471
Short name T486
Test name
Test status
Simulation time 1222156930 ps
CPU time 12.58 seconds
Started Aug 19 06:00:31 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 226120 kb
Host smart-0b448425-725a-45f5-bcea-c1e87d58dec4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217243471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.217243471
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3041121381
Short name T285
Test name
Test status
Simulation time 432149516 ps
CPU time 10.48 seconds
Started Aug 19 06:00:35 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 226008 kb
Host smart-67c538ef-cfc9-4078-b281-d44c3c6d344a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041121381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3041121381
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3468475160
Short name T595
Test name
Test status
Simulation time 1079678962 ps
CPU time 10.92 seconds
Started Aug 19 06:00:29 PM PDT 24
Finished Aug 19 06:00:40 PM PDT 24
Peak memory 226020 kb
Host smart-19746501-bf4d-4898-9e51-a972cedf2d50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468475160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3468475160
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.731802826
Short name T58
Test name
Test status
Simulation time 1039449765 ps
CPU time 8.33 seconds
Started Aug 19 06:00:28 PM PDT 24
Finished Aug 19 06:00:36 PM PDT 24
Peak memory 225124 kb
Host smart-a0ff6da7-cbfc-46d1-a1ca-9a9a4b0d2d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731802826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.731802826
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1924323023
Short name T83
Test name
Test status
Simulation time 15190011 ps
CPU time 1.09 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:31 PM PDT 24
Peak memory 221752 kb
Host smart-40536e17-0ba3-47c4-a80f-b3738e2109a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924323023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1924323023
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1409929553
Short name T4
Test name
Test status
Simulation time 789448209 ps
CPU time 20.68 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:51 PM PDT 24
Peak memory 250896 kb
Host smart-fa77c9d7-8b58-45d6-aea7-ea7063e32d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409929553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1409929553
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2084749685
Short name T1
Test name
Test status
Simulation time 105929847 ps
CPU time 7.89 seconds
Started Aug 19 06:00:29 PM PDT 24
Finished Aug 19 06:00:37 PM PDT 24
Peak memory 246472 kb
Host smart-8ff758c0-5d64-4880-a647-69cbcaf1a45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084749685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2084749685
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.630011011
Short name T279
Test name
Test status
Simulation time 17247336491 ps
CPU time 560.2 seconds
Started Aug 19 06:00:34 PM PDT 24
Finished Aug 19 06:09:54 PM PDT 24
Peak memory 267372 kb
Host smart-834a5b5a-0301-42f0-8a83-c0981ae6a25f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630011011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.630011011
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.696697570
Short name T307
Test name
Test status
Simulation time 12853515 ps
CPU time 1.04 seconds
Started Aug 19 06:00:23 PM PDT 24
Finished Aug 19 06:00:24 PM PDT 24
Peak memory 211860 kb
Host smart-c2e152ca-3894-4c79-874a-7a8d98428464
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696697570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.696697570
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2368619257
Short name T219
Test name
Test status
Simulation time 22213801 ps
CPU time 0.96 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:31 PM PDT 24
Peak memory 208948 kb
Host smart-ac5413b7-1452-4fd5-8cc9-792d153c66aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368619257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2368619257
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.538113491
Short name T330
Test name
Test status
Simulation time 465531635 ps
CPU time 16.2 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 226096 kb
Host smart-9b4c1bb0-f006-4468-b49f-fddd15105316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538113491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.538113491
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2865047055
Short name T34
Test name
Test status
Simulation time 1799480891 ps
CPU time 12.12 seconds
Started Aug 19 06:01:08 PM PDT 24
Finished Aug 19 06:01:21 PM PDT 24
Peak memory 217360 kb
Host smart-8406428a-b820-40ce-8410-50537a72bafc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865047055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2865047055
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3145923438
Short name T232
Test name
Test status
Simulation time 49403875 ps
CPU time 3.05 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 218284 kb
Host smart-8cd057f0-1f48-448e-a7bd-e61dc00d5e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145923438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3145923438
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2053756547
Short name T498
Test name
Test status
Simulation time 625008506 ps
CPU time 15.09 seconds
Started Aug 19 06:00:32 PM PDT 24
Finished Aug 19 06:00:47 PM PDT 24
Peak memory 219076 kb
Host smart-e9c0c5f0-8471-47e3-b2cf-355fcd0a9f8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053756547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2053756547
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.534630361
Short name T838
Test name
Test status
Simulation time 326252838 ps
CPU time 8.29 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:38 PM PDT 24
Peak memory 226032 kb
Host smart-aa2e0e1f-8786-4aa6-8e13-0ce7fa880647
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534630361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.534630361
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2448598108
Short name T563
Test name
Test status
Simulation time 471267572 ps
CPU time 6.32 seconds
Started Aug 19 06:00:33 PM PDT 24
Finished Aug 19 06:00:39 PM PDT 24
Peak memory 225012 kb
Host smart-82ec7ced-4135-43f5-a329-2674aafaa467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448598108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2448598108
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1179354572
Short name T434
Test name
Test status
Simulation time 82284139 ps
CPU time 1.18 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:31 PM PDT 24
Peak memory 213560 kb
Host smart-51d2cdbd-126c-42de-b3df-280c943e2645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179354572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1179354572
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1842870722
Short name T523
Test name
Test status
Simulation time 1087896558 ps
CPU time 25.25 seconds
Started Aug 19 06:00:32 PM PDT 24
Finished Aug 19 06:00:57 PM PDT 24
Peak memory 246860 kb
Host smart-49a1f8dd-9da8-4475-bc50-7a1645ae0834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842870722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1842870722
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4185571282
Short name T560
Test name
Test status
Simulation time 69683703 ps
CPU time 6.58 seconds
Started Aug 19 06:00:33 PM PDT 24
Finished Aug 19 06:00:40 PM PDT 24
Peak memory 246564 kb
Host smart-bc078f70-c546-47ef-8a9d-afd7a237aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185571282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4185571282
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3107089416
Short name T457
Test name
Test status
Simulation time 7641770813 ps
CPU time 227.96 seconds
Started Aug 19 06:00:31 PM PDT 24
Finished Aug 19 06:04:19 PM PDT 24
Peak memory 250932 kb
Host smart-0e1f33fc-9c8a-4723-93a4-9768a4bfb223
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107089416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3107089416
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2952985574
Short name T159
Test name
Test status
Simulation time 13269975 ps
CPU time 1.02 seconds
Started Aug 19 06:00:29 PM PDT 24
Finished Aug 19 06:00:30 PM PDT 24
Peak memory 211932 kb
Host smart-6c4817d2-dc99-49bb-a6dc-669088f8c091
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952985574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2952985574
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2814647071
Short name T826
Test name
Test status
Simulation time 48762633 ps
CPU time 0.84 seconds
Started Aug 19 06:00:41 PM PDT 24
Finished Aug 19 06:00:42 PM PDT 24
Peak memory 208708 kb
Host smart-023a18cf-fde4-4d38-8ebc-0edb163fe3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814647071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2814647071
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3775069869
Short name T248
Test name
Test status
Simulation time 303744359 ps
CPU time 9.84 seconds
Started Aug 19 06:00:35 PM PDT 24
Finished Aug 19 06:00:45 PM PDT 24
Peak memory 226084 kb
Host smart-ba78a8f8-2165-49ee-8a70-24a5747ba286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775069869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3775069869
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1370010671
Short name T33
Test name
Test status
Simulation time 340215045 ps
CPU time 9.02 seconds
Started Aug 19 06:00:33 PM PDT 24
Finished Aug 19 06:00:42 PM PDT 24
Peak memory 217336 kb
Host smart-88222113-1f6c-419c-9f02-b433d785943a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370010671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1370010671
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3664897190
Short name T815
Test name
Test status
Simulation time 250513469 ps
CPU time 2.95 seconds
Started Aug 19 06:00:33 PM PDT 24
Finished Aug 19 06:00:36 PM PDT 24
Peak memory 222280 kb
Host smart-55a93d2c-93e3-45a6-9937-1c51bd3e0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664897190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3664897190
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2383392728
Short name T169
Test name
Test status
Simulation time 1192634340 ps
CPU time 11.81 seconds
Started Aug 19 06:00:41 PM PDT 24
Finished Aug 19 06:00:53 PM PDT 24
Peak memory 218948 kb
Host smart-dcb02a61-e32c-4798-a3a2-1f01da8cd5cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383392728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2383392728
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.832226342
Short name T494
Test name
Test status
Simulation time 334433915 ps
CPU time 10.85 seconds
Started Aug 19 06:00:43 PM PDT 24
Finished Aug 19 06:00:54 PM PDT 24
Peak memory 226016 kb
Host smart-3b57f7f2-3acb-4239-9d64-776ccd13c740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832226342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.832226342
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1534872639
Short name T558
Test name
Test status
Simulation time 228967931 ps
CPU time 6.87 seconds
Started Aug 19 06:00:40 PM PDT 24
Finished Aug 19 06:00:47 PM PDT 24
Peak memory 218220 kb
Host smart-5abbebda-62c0-4e3b-a8e1-b9743a2a6390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534872639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1534872639
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3193262803
Short name T662
Test name
Test status
Simulation time 370982674 ps
CPU time 14.46 seconds
Started Aug 19 06:00:33 PM PDT 24
Finished Aug 19 06:00:47 PM PDT 24
Peak memory 218360 kb
Host smart-ef911fde-9ff9-45bf-81e6-bb91b4cbeb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193262803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3193262803
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2373420178
Short name T834
Test name
Test status
Simulation time 85702318 ps
CPU time 2.52 seconds
Started Aug 19 06:00:32 PM PDT 24
Finished Aug 19 06:00:35 PM PDT 24
Peak memory 217628 kb
Host smart-97632156-1317-4b29-9aa2-a26f4e05d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373420178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2373420178
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3662494542
Short name T828
Test name
Test status
Simulation time 840077485 ps
CPU time 19.66 seconds
Started Aug 19 06:00:30 PM PDT 24
Finished Aug 19 06:00:50 PM PDT 24
Peak memory 250948 kb
Host smart-7749868b-1f51-40d4-a366-d49096eb3859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662494542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3662494542
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.629545580
Short name T408
Test name
Test status
Simulation time 323145054 ps
CPU time 6.01 seconds
Started Aug 19 06:00:33 PM PDT 24
Finished Aug 19 06:00:39 PM PDT 24
Peak memory 246876 kb
Host smart-62ea1f44-94b6-45c8-ad8d-61d2d4f2f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629545580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.629545580
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.778332371
Short name T577
Test name
Test status
Simulation time 24691140704 ps
CPU time 186.85 seconds
Started Aug 19 06:02:15 PM PDT 24
Finished Aug 19 06:05:22 PM PDT 24
Peak memory 222032 kb
Host smart-0aa45481-0e2c-46b4-a112-887d6552accd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778332371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.778332371
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2398204612
Short name T647
Test name
Test status
Simulation time 33955357 ps
CPU time 0.9 seconds
Started Aug 19 06:00:33 PM PDT 24
Finished Aug 19 06:00:34 PM PDT 24
Peak memory 211908 kb
Host smart-1c2576b8-4df6-4051-be98-574ae1d4fa22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398204612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2398204612
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3981936971
Short name T787
Test name
Test status
Simulation time 49599414 ps
CPU time 0.96 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:00:45 PM PDT 24
Peak memory 208920 kb
Host smart-74e348d5-300b-4aad-a48b-1eae437c8ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981936971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3981936971
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1176381812
Short name T837
Test name
Test status
Simulation time 1996814053 ps
CPU time 18.75 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:01:03 PM PDT 24
Peak memory 218288 kb
Host smart-bf406682-b900-4f21-b4c8-4a123627cc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176381812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1176381812
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3060038049
Short name T642
Test name
Test status
Simulation time 147991197 ps
CPU time 1.56 seconds
Started Aug 19 06:00:40 PM PDT 24
Finished Aug 19 06:00:42 PM PDT 24
Peak memory 217080 kb
Host smart-67f71a46-a8e4-4de2-a717-1d88e81297a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060038049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3060038049
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.645766903
Short name T623
Test name
Test status
Simulation time 166292298 ps
CPU time 2.3 seconds
Started Aug 19 06:00:41 PM PDT 24
Finished Aug 19 06:00:43 PM PDT 24
Peak memory 218280 kb
Host smart-15ea422b-a440-42c9-a86a-05eb0d3b8830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645766903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.645766903
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.323718113
Short name T294
Test name
Test status
Simulation time 667504491 ps
CPU time 10.75 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:00:55 PM PDT 24
Peak memory 218940 kb
Host smart-3464cebc-f42a-4d6c-b668-beb2953e6e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323718113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.323718113
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.194208403
Short name T466
Test name
Test status
Simulation time 1519451863 ps
CPU time 9.55 seconds
Started Aug 19 06:00:38 PM PDT 24
Finished Aug 19 06:00:47 PM PDT 24
Peak memory 226036 kb
Host smart-3c3bc560-e5b2-4e4e-93e2-f7c2e8945431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194208403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.194208403
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.575883899
Short name T817
Test name
Test status
Simulation time 571243981 ps
CPU time 7.8 seconds
Started Aug 19 06:00:39 PM PDT 24
Finished Aug 19 06:00:47 PM PDT 24
Peak memory 225352 kb
Host smart-0af0692d-136e-49ca-857a-b6032a2805ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575883899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.575883899
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2099270495
Short name T371
Test name
Test status
Simulation time 1961978274 ps
CPU time 7.28 seconds
Started Aug 19 06:00:43 PM PDT 24
Finished Aug 19 06:00:50 PM PDT 24
Peak memory 226228 kb
Host smart-a248e8c2-0e26-4b23-8ee6-3a3522925e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099270495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2099270495
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2341888954
Short name T482
Test name
Test status
Simulation time 161307020 ps
CPU time 2.25 seconds
Started Aug 19 06:00:38 PM PDT 24
Finished Aug 19 06:00:41 PM PDT 24
Peak memory 214248 kb
Host smart-d335e5c0-98a8-4850-9292-bfbe84aa2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341888954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2341888954
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1492717723
Short name T550
Test name
Test status
Simulation time 263153984 ps
CPU time 29.24 seconds
Started Aug 19 06:00:42 PM PDT 24
Finished Aug 19 06:01:11 PM PDT 24
Peak memory 250908 kb
Host smart-6bd28b5e-f1c3-447f-8465-cb271325a6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492717723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1492717723
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.4058665823
Short name T704
Test name
Test status
Simulation time 213832581 ps
CPU time 6.02 seconds
Started Aug 19 06:00:40 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 242820 kb
Host smart-138e8ba9-d1d5-4fb4-b358-a32f8131b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058665823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4058665823
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1348743485
Short name T45
Test name
Test status
Simulation time 44230668156 ps
CPU time 162.61 seconds
Started Aug 19 06:00:41 PM PDT 24
Finished Aug 19 06:03:24 PM PDT 24
Peak memory 250592 kb
Host smart-5e4d38d1-ad59-4f60-8c7d-4301fb825577
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348743485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1348743485
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3232613990
Short name T709
Test name
Test status
Simulation time 15336053 ps
CPU time 1.05 seconds
Started Aug 19 06:00:41 PM PDT 24
Finished Aug 19 06:00:42 PM PDT 24
Peak memory 211872 kb
Host smart-dd7b5392-738a-42d6-b71d-f60895f6ddb1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232613990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3232613990
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2450337896
Short name T751
Test name
Test status
Simulation time 51588549 ps
CPU time 1.05 seconds
Started Aug 19 06:00:50 PM PDT 24
Finished Aug 19 06:00:51 PM PDT 24
Peak memory 208824 kb
Host smart-17c3fc16-59e0-4bf0-9160-69098a94e288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450337896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2450337896
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.202329080
Short name T842
Test name
Test status
Simulation time 489534337 ps
CPU time 7.7 seconds
Started Aug 19 06:00:40 PM PDT 24
Finished Aug 19 06:00:48 PM PDT 24
Peak memory 226104 kb
Host smart-ef7a1bdc-87e3-4828-805a-05e5cb050d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202329080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.202329080
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.794443831
Short name T440
Test name
Test status
Simulation time 375515049 ps
CPU time 5.08 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:00:49 PM PDT 24
Peak memory 217268 kb
Host smart-0f88c33b-943b-47f4-92ee-cfc05955fb75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794443831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.794443831
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4271801047
Short name T13
Test name
Test status
Simulation time 331279926 ps
CPU time 2.74 seconds
Started Aug 19 06:00:39 PM PDT 24
Finished Aug 19 06:00:42 PM PDT 24
Peak memory 218256 kb
Host smart-d907da88-2baa-48fa-8ccc-ea1161576e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271801047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4271801047
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3327161696
Short name T426
Test name
Test status
Simulation time 413877977 ps
CPU time 17.41 seconds
Started Aug 19 06:00:43 PM PDT 24
Finished Aug 19 06:01:01 PM PDT 24
Peak memory 218520 kb
Host smart-c150cfc5-e749-46a3-9bd8-4ba64b77d915
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327161696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3327161696
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3943643090
Short name T342
Test name
Test status
Simulation time 829449780 ps
CPU time 20.29 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:01:04 PM PDT 24
Peak memory 226016 kb
Host smart-e2cab996-db72-4581-bb9a-66afe2509e86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943643090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3943643090
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3723717441
Short name T757
Test name
Test status
Simulation time 3063047314 ps
CPU time 8.47 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:00:53 PM PDT 24
Peak memory 226080 kb
Host smart-9da72002-e7e4-4c0c-b740-6095f91a7cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723717441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3723717441
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.126833956
Short name T788
Test name
Test status
Simulation time 1538650794 ps
CPU time 12.26 seconds
Started Aug 19 06:00:39 PM PDT 24
Finished Aug 19 06:00:52 PM PDT 24
Peak memory 226076 kb
Host smart-edf098bc-b53e-48bf-a4fa-14a6ed9e018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126833956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.126833956
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1024172817
Short name T167
Test name
Test status
Simulation time 420781886 ps
CPU time 2.21 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:00:46 PM PDT 24
Peak memory 217656 kb
Host smart-79939478-d325-44f3-9a3f-a81e5087306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024172817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1024172817
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3042656875
Short name T807
Test name
Test status
Simulation time 95482373 ps
CPU time 9.69 seconds
Started Aug 19 06:00:41 PM PDT 24
Finished Aug 19 06:00:51 PM PDT 24
Peak memory 250928 kb
Host smart-6f87afab-2305-43db-b82a-438d47fae545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042656875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3042656875
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1379226021
Short name T333
Test name
Test status
Simulation time 8911640292 ps
CPU time 34.22 seconds
Started Aug 19 06:00:44 PM PDT 24
Finished Aug 19 06:01:18 PM PDT 24
Peak memory 269872 kb
Host smart-d53d3550-a233-45ce-81cc-b824b0c9fe76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379226021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1379226021
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3336698073
Short name T396
Test name
Test status
Simulation time 2345595855 ps
CPU time 80.27 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:02:13 PM PDT 24
Peak memory 254240 kb
Host smart-0603ae72-0da3-4d14-9fd0-59c50423595b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3336698073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3336698073
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2932416266
Short name T205
Test name
Test status
Simulation time 46583741 ps
CPU time 1.05 seconds
Started Aug 19 06:00:40 PM PDT 24
Finished Aug 19 06:00:41 PM PDT 24
Peak memory 213052 kb
Host smart-a0edaff7-392b-499c-907e-ee99775dab80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932416266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2932416266
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2914236674
Short name T451
Test name
Test status
Simulation time 88982864 ps
CPU time 1.43 seconds
Started Aug 19 05:58:14 PM PDT 24
Finished Aug 19 05:58:15 PM PDT 24
Peak memory 208952 kb
Host smart-f4e11de2-a1c8-410f-bc47-0fb567717737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914236674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2914236674
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2411120803
Short name T387
Test name
Test status
Simulation time 810189259 ps
CPU time 10.61 seconds
Started Aug 19 05:58:05 PM PDT 24
Finished Aug 19 05:58:16 PM PDT 24
Peak memory 218300 kb
Host smart-2da85db1-6c7f-4564-ba1e-a15013c32b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411120803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2411120803
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1211675558
Short name T773
Test name
Test status
Simulation time 331756321 ps
CPU time 2.7 seconds
Started Aug 19 05:58:06 PM PDT 24
Finished Aug 19 05:58:09 PM PDT 24
Peak memory 216976 kb
Host smart-db3da00e-bccc-47cc-8d1f-ff2c61133eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211675558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1211675558
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3009015246
Short name T800
Test name
Test status
Simulation time 6060337748 ps
CPU time 41.13 seconds
Started Aug 19 05:58:05 PM PDT 24
Finished Aug 19 05:58:47 PM PDT 24
Peak memory 218292 kb
Host smart-246b3813-f9a0-47a2-9b20-cc77cb704eda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009015246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3009015246
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4017857887
Short name T5
Test name
Test status
Simulation time 204645286 ps
CPU time 2.94 seconds
Started Aug 19 05:58:06 PM PDT 24
Finished Aug 19 05:58:09 PM PDT 24
Peak memory 217692 kb
Host smart-dd5f21c6-001c-48f2-adef-292273521d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017857887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
017857887
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3760503977
Short name T215
Test name
Test status
Simulation time 6816325085 ps
CPU time 7.37 seconds
Started Aug 19 05:58:05 PM PDT 24
Finished Aug 19 05:58:13 PM PDT 24
Peak memory 218312 kb
Host smart-2d7f813d-93b3-45b8-abc3-4f29d7b9cea5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760503977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3760503977
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1220268774
Short name T68
Test name
Test status
Simulation time 2552147170 ps
CPU time 9.58 seconds
Started Aug 19 05:58:08 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 217640 kb
Host smart-fe88c593-7340-461e-8df1-2a02b51db604
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220268774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1220268774
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1171275879
Short name T814
Test name
Test status
Simulation time 374436402 ps
CPU time 4.09 seconds
Started Aug 19 05:58:06 PM PDT 24
Finished Aug 19 05:58:10 PM PDT 24
Peak memory 217604 kb
Host smart-8f019703-c505-420f-abf9-d02c2ec5a1a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171275879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1171275879
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2574703367
Short name T361
Test name
Test status
Simulation time 2587633954 ps
CPU time 26.88 seconds
Started Aug 19 05:58:05 PM PDT 24
Finished Aug 19 05:58:32 PM PDT 24
Peak memory 250916 kb
Host smart-6514bfca-eec1-4bf4-b5b2-48186ed8160e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574703367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2574703367
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.657326824
Short name T673
Test name
Test status
Simulation time 962313130 ps
CPU time 9.86 seconds
Started Aug 19 05:58:05 PM PDT 24
Finished Aug 19 05:58:15 PM PDT 24
Peak memory 226308 kb
Host smart-814fed06-6874-4c49-affd-57c8ee791ca4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657326824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.657326824
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3707158760
Short name T223
Test name
Test status
Simulation time 31062828 ps
CPU time 1.71 seconds
Started Aug 19 05:58:06 PM PDT 24
Finished Aug 19 05:58:08 PM PDT 24
Peak memory 218264 kb
Host smart-9b6c8eab-aa27-4fe6-b1b3-dd877e7885f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707158760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3707158760
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2269819461
Short name T484
Test name
Test status
Simulation time 895949136 ps
CPU time 6.31 seconds
Started Aug 19 05:58:03 PM PDT 24
Finished Aug 19 05:58:10 PM PDT 24
Peak memory 217672 kb
Host smart-22f1a219-daca-4b02-b4ac-e11ac2605a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269819461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2269819461
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.292365867
Short name T99
Test name
Test status
Simulation time 221002597 ps
CPU time 33.86 seconds
Started Aug 19 05:58:06 PM PDT 24
Finished Aug 19 05:58:40 PM PDT 24
Peak memory 269672 kb
Host smart-cf924d36-3910-49fb-89af-c7d22221d993
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292365867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.292365867
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1958091891
Short name T596
Test name
Test status
Simulation time 683809026 ps
CPU time 14.38 seconds
Started Aug 19 05:58:05 PM PDT 24
Finished Aug 19 05:58:19 PM PDT 24
Peak memory 226084 kb
Host smart-d0a00fd6-8c59-4f87-89c5-b9a00c8e51c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958091891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1958091891
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3204780681
Short name T718
Test name
Test status
Simulation time 421591836 ps
CPU time 11.74 seconds
Started Aug 19 05:58:09 PM PDT 24
Finished Aug 19 05:58:21 PM PDT 24
Peak memory 226056 kb
Host smart-2ff8d519-ae7e-4509-a2e4-c02eab9ca862
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204780681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3204780681
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1705510352
Short name T827
Test name
Test status
Simulation time 2218641957 ps
CPU time 6.83 seconds
Started Aug 19 05:58:06 PM PDT 24
Finished Aug 19 05:58:13 PM PDT 24
Peak memory 218296 kb
Host smart-2d14de21-b404-4a6a-b9d0-f554762d820a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705510352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
705510352
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1573763307
Short name T598
Test name
Test status
Simulation time 417015626 ps
CPU time 9.35 seconds
Started Aug 19 05:58:07 PM PDT 24
Finished Aug 19 05:58:16 PM PDT 24
Peak memory 226104 kb
Host smart-a87c2b34-5551-4991-81dd-63854bc858cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573763307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1573763307
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1503631967
Short name T660
Test name
Test status
Simulation time 22775049 ps
CPU time 1.79 seconds
Started Aug 19 05:57:57 PM PDT 24
Finished Aug 19 05:57:59 PM PDT 24
Peak memory 223456 kb
Host smart-69631168-4fe5-49e8-8df4-99f4aa561943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503631967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1503631967
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2733371708
Short name T369
Test name
Test status
Simulation time 268877936 ps
CPU time 29.35 seconds
Started Aug 19 05:57:55 PM PDT 24
Finished Aug 19 05:58:24 PM PDT 24
Peak memory 250924 kb
Host smart-26008cd1-6a04-45dd-b578-eb11f097f9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733371708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2733371708
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3415155767
Short name T400
Test name
Test status
Simulation time 125184292 ps
CPU time 3.97 seconds
Started Aug 19 05:57:59 PM PDT 24
Finished Aug 19 05:58:03 PM PDT 24
Peak memory 223048 kb
Host smart-19b5754f-a3f8-492e-a270-cffc8dc44995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415155767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3415155767
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3852548317
Short name T547
Test name
Test status
Simulation time 7228196071 ps
CPU time 122.94 seconds
Started Aug 19 05:58:07 PM PDT 24
Finished Aug 19 06:00:10 PM PDT 24
Peak memory 283724 kb
Host smart-7fccf592-9cd2-4771-8f2d-d1c917c0ffd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852548317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3852548317
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1915200921
Short name T280
Test name
Test status
Simulation time 16705172 ps
CPU time 0.82 seconds
Started Aug 19 05:57:56 PM PDT 24
Finished Aug 19 05:57:57 PM PDT 24
Peak memory 211980 kb
Host smart-c65bb57f-a8f7-487e-b6ed-92aaf6f4d787
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915200921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1915200921
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3602271102
Short name T352
Test name
Test status
Simulation time 14428491 ps
CPU time 0.86 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:00:54 PM PDT 24
Peak memory 208796 kb
Host smart-60c42c32-03f6-44ca-9979-e0c4983e57fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602271102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3602271102
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2995868668
Short name T24
Test name
Test status
Simulation time 1190479132 ps
CPU time 9.61 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:01:01 PM PDT 24
Peak memory 218316 kb
Host smart-3ea8c745-8c30-48ce-9b5e-cdb583b48115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995868668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2995868668
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1773400254
Short name T38
Test name
Test status
Simulation time 281457816 ps
CPU time 3.34 seconds
Started Aug 19 06:00:50 PM PDT 24
Finished Aug 19 06:00:53 PM PDT 24
Peak memory 217620 kb
Host smart-a6351428-45ef-4666-80c8-f7ea30037305
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773400254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1773400254
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3329664698
Short name T729
Test name
Test status
Simulation time 19468200 ps
CPU time 1.44 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:00:53 PM PDT 24
Peak memory 218292 kb
Host smart-0be680cf-1203-4d31-bbba-95f3e7974953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329664698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3329664698
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.61606266
Short name T262
Test name
Test status
Simulation time 193828547 ps
CPU time 7.38 seconds
Started Aug 19 06:00:48 PM PDT 24
Finished Aug 19 06:00:55 PM PDT 24
Peak memory 218376 kb
Host smart-2a20cb0f-1699-42de-9bdc-3f08e6718497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61606266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.61606266
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.391566138
Short name T298
Test name
Test status
Simulation time 1077881928 ps
CPU time 11.6 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:01:04 PM PDT 24
Peak memory 226056 kb
Host smart-46122ad6-7f37-4657-a23d-d05dbfac3f49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391566138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.391566138
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.272520544
Short name T379
Test name
Test status
Simulation time 397526096 ps
CPU time 9.12 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:01:01 PM PDT 24
Peak memory 218252 kb
Host smart-a65ff874-1c59-4aca-a76f-64e1fc9e6ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272520544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.272520544
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1235397701
Short name T654
Test name
Test status
Simulation time 3523410719 ps
CPU time 7.66 seconds
Started Aug 19 06:01:00 PM PDT 24
Finished Aug 19 06:01:07 PM PDT 24
Peak memory 226048 kb
Host smart-46a25d85-d7de-4df4-b5da-8a7a98fd59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235397701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1235397701
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3661041581
Short name T441
Test name
Test status
Simulation time 129509539 ps
CPU time 3.16 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:00:56 PM PDT 24
Peak memory 217660 kb
Host smart-a04ca60b-30e9-43bb-9c2c-7a38bd1b0ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661041581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3661041581
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3177729506
Short name T383
Test name
Test status
Simulation time 211772926 ps
CPU time 24.94 seconds
Started Aug 19 06:00:50 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 250984 kb
Host smart-81b770b3-bde8-4eb9-9e8d-47ccefe9cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177729506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3177729506
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1067538990
Short name T308
Test name
Test status
Simulation time 199354804 ps
CPU time 3 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:00:54 PM PDT 24
Peak memory 225456 kb
Host smart-b3ad3d5d-d11c-409c-a45b-a1a3781fc513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067538990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1067538990
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2106872313
Short name T405
Test name
Test status
Simulation time 6431809574 ps
CPU time 78.75 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:02:09 PM PDT 24
Peak memory 279336 kb
Host smart-8b94f200-deac-4f7e-b8ca-ce111e919747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106872313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2106872313
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2498403878
Short name T516
Test name
Test status
Simulation time 27833143 ps
CPU time 0.9 seconds
Started Aug 19 06:00:54 PM PDT 24
Finished Aug 19 06:00:55 PM PDT 24
Peak memory 217712 kb
Host smart-f3e74f0d-bd3e-4236-b071-bd74b5c1e61f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498403878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2498403878
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1463041916
Short name T756
Test name
Test status
Simulation time 89765659 ps
CPU time 0.98 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:00:54 PM PDT 24
Peak memory 208968 kb
Host smart-ba71ebba-799b-4d45-a4a4-6f4f7235a3de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463041916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1463041916
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2566795106
Short name T850
Test name
Test status
Simulation time 327202572 ps
CPU time 13.85 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:01:05 PM PDT 24
Peak memory 226096 kb
Host smart-8e88daaa-abeb-4e56-8441-04f8aaf3240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566795106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2566795106
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3111728607
Short name T174
Test name
Test status
Simulation time 83289770 ps
CPU time 1.96 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:00:54 PM PDT 24
Peak memory 217204 kb
Host smart-baff81be-ba2c-43ec-82f9-a45ebcbaa7af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111728607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3111728607
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2629492854
Short name T316
Test name
Test status
Simulation time 765637555 ps
CPU time 2.66 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:00:55 PM PDT 24
Peak memory 218292 kb
Host smart-9251b4bf-9f42-4a47-a316-88007eaabc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629492854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2629492854
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2872571984
Short name T755
Test name
Test status
Simulation time 728915741 ps
CPU time 15.44 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:01:08 PM PDT 24
Peak memory 226104 kb
Host smart-e10a6356-f6a2-445e-9ab8-e5a01fd5195d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872571984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2872571984
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4018492464
Short name T435
Test name
Test status
Simulation time 350082843 ps
CPU time 9.4 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:01:01 PM PDT 24
Peak memory 225992 kb
Host smart-ae6f8887-d816-4a74-bce3-c56648042d61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018492464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.4018492464
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.603056516
Short name T686
Test name
Test status
Simulation time 626360051 ps
CPU time 9.27 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:01:02 PM PDT 24
Peak memory 218216 kb
Host smart-635abcfb-da4a-449f-a0d0-65f52ef1fe27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603056516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.603056516
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3993736677
Short name T39
Test name
Test status
Simulation time 37744205 ps
CPU time 1.78 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:00:53 PM PDT 24
Peak memory 213796 kb
Host smart-7877d090-9d46-4ad2-930e-e8dd246a0516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993736677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3993736677
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.869215676
Short name T260
Test name
Test status
Simulation time 722367321 ps
CPU time 21.01 seconds
Started Aug 19 06:00:57 PM PDT 24
Finished Aug 19 06:01:18 PM PDT 24
Peak memory 250928 kb
Host smart-8a3b4bf4-7875-43c1-ae51-a93fc79087e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869215676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.869215676
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1325094720
Short name T464
Test name
Test status
Simulation time 47849752 ps
CPU time 6.92 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:00:59 PM PDT 24
Peak memory 250908 kb
Host smart-eb6817b4-8944-4973-8b58-9862ddbe87a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325094720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1325094720
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1680764018
Short name T473
Test name
Test status
Simulation time 16396407973 ps
CPU time 524.92 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:09:37 PM PDT 24
Peak memory 278648 kb
Host smart-353d7d99-01c2-4fb4-94cb-abe005c70873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680764018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1680764018
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3542023324
Short name T165
Test name
Test status
Simulation time 12328878385 ps
CPU time 100.57 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:02:31 PM PDT 24
Peak memory 283880 kb
Host smart-fea82465-7d37-4acc-99a4-ec15c8a37cc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3542023324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3542023324
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2405196711
Short name T616
Test name
Test status
Simulation time 18142597 ps
CPU time 1.05 seconds
Started Aug 19 06:00:53 PM PDT 24
Finished Aug 19 06:00:54 PM PDT 24
Peak memory 211916 kb
Host smart-9012b3d0-4872-48af-8f26-e7a3f389ee52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405196711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2405196711
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.194864687
Short name T705
Test name
Test status
Simulation time 62114298 ps
CPU time 0.9 seconds
Started Aug 19 06:01:01 PM PDT 24
Finished Aug 19 06:01:02 PM PDT 24
Peak memory 208900 kb
Host smart-aa3b0319-1963-4b92-86d4-a6d9e98989b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194864687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.194864687
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.714173299
Short name T593
Test name
Test status
Simulation time 321728974 ps
CPU time 16.23 seconds
Started Aug 19 06:00:57 PM PDT 24
Finished Aug 19 06:01:13 PM PDT 24
Peak memory 218308 kb
Host smart-96666a84-ac16-45d4-9638-697fceb38a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714173299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.714173299
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2396772199
Short name T867
Test name
Test status
Simulation time 1405617726 ps
CPU time 4.59 seconds
Started Aug 19 06:00:56 PM PDT 24
Finished Aug 19 06:01:01 PM PDT 24
Peak memory 217232 kb
Host smart-a8fba8d2-14dd-4e1c-aac8-75d6751ce5cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396772199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2396772199
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3396974938
Short name T289
Test name
Test status
Simulation time 94335030 ps
CPU time 3.03 seconds
Started Aug 19 06:00:57 PM PDT 24
Finished Aug 19 06:01:00 PM PDT 24
Peak memory 218216 kb
Host smart-6eb74754-3503-41aa-90b1-44a97aed9781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396974938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3396974938
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3332149871
Short name T793
Test name
Test status
Simulation time 307459360 ps
CPU time 12.84 seconds
Started Aug 19 06:01:00 PM PDT 24
Finished Aug 19 06:01:14 PM PDT 24
Peak memory 218340 kb
Host smart-451532e3-3284-464c-91d9-b8bb00c72bec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332149871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3332149871
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3828848818
Short name T676
Test name
Test status
Simulation time 2559861015 ps
CPU time 12.51 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:10 PM PDT 24
Peak memory 226120 kb
Host smart-543630fe-3404-4f20-bfd7-05c3e461857b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828848818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3828848818
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2667623254
Short name T735
Test name
Test status
Simulation time 383448975 ps
CPU time 9.47 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:07 PM PDT 24
Peak memory 226052 kb
Host smart-8ad9c563-2c51-4dc7-ba72-92c4eafc828f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667623254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2667623254
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.686556248
Short name T847
Test name
Test status
Simulation time 1074547392 ps
CPU time 10.08 seconds
Started Aug 19 06:00:56 PM PDT 24
Finished Aug 19 06:01:07 PM PDT 24
Peak memory 225028 kb
Host smart-4196c3ee-d834-4949-914c-049fe2dad622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686556248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.686556248
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3466410327
Short name T241
Test name
Test status
Simulation time 132742413 ps
CPU time 1.78 seconds
Started Aug 19 06:00:52 PM PDT 24
Finished Aug 19 06:00:54 PM PDT 24
Peak memory 214164 kb
Host smart-8b7ef211-e0d0-4d87-9d01-51f25555c7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466410327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3466410327
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.182647955
Short name T777
Test name
Test status
Simulation time 1303991799 ps
CPU time 40.29 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:01:32 PM PDT 24
Peak memory 250904 kb
Host smart-1454f9e1-e57a-43cc-8b67-cfba79bb3558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182647955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.182647955
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1479962987
Short name T311
Test name
Test status
Simulation time 147994353 ps
CPU time 4.06 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:00:55 PM PDT 24
Peak memory 218292 kb
Host smart-32ca02c3-b5e1-47d2-bb10-fecdbd98107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479962987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1479962987
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1445569049
Short name T467
Test name
Test status
Simulation time 1888147378 ps
CPU time 28.14 seconds
Started Aug 19 06:00:56 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 250892 kb
Host smart-2b08cb2f-73fb-4550-a250-9bdfb4307891
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445569049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1445569049
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3986347293
Short name T829
Test name
Test status
Simulation time 14697061 ps
CPU time 0.92 seconds
Started Aug 19 06:00:51 PM PDT 24
Finished Aug 19 06:00:52 PM PDT 24
Peak memory 211960 kb
Host smart-43b366ce-6ad3-48a2-bb55-2adbfdedd01f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986347293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3986347293
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3456391672
Short name T258
Test name
Test status
Simulation time 84708712 ps
CPU time 1.18 seconds
Started Aug 19 06:00:57 PM PDT 24
Finished Aug 19 06:00:59 PM PDT 24
Peak memory 208996 kb
Host smart-a57f4d1c-ea7a-4727-8e14-d37ea1a44790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456391672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3456391672
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1617977345
Short name T309
Test name
Test status
Simulation time 360969915 ps
CPU time 10.72 seconds
Started Aug 19 06:00:59 PM PDT 24
Finished Aug 19 06:01:10 PM PDT 24
Peak memory 226132 kb
Host smart-4e80a10e-ad0d-4eb7-8487-8b86cf8b6ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617977345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1617977345
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.910708740
Short name T437
Test name
Test status
Simulation time 168118486 ps
CPU time 4.54 seconds
Started Aug 19 06:00:57 PM PDT 24
Finished Aug 19 06:01:02 PM PDT 24
Peak memory 217020 kb
Host smart-c9211f31-a422-465b-8193-00c4dc4664c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910708740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.910708740
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2838737046
Short name T154
Test name
Test status
Simulation time 61431106 ps
CPU time 1.51 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:00 PM PDT 24
Peak memory 218248 kb
Host smart-fd724e5d-cadb-4528-ae85-f8ce5a494a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838737046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2838737046
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1372352150
Short name T865
Test name
Test status
Simulation time 585495508 ps
CPU time 15.31 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:14 PM PDT 24
Peak memory 218896 kb
Host smart-c46a7de5-b595-4b05-ba37-adda7664210f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372352150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1372352150
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1809682699
Short name T224
Test name
Test status
Simulation time 422975031 ps
CPU time 11.08 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:09 PM PDT 24
Peak memory 218180 kb
Host smart-411ae53a-c9c5-4584-a2d3-4561f40d9cb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809682699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1809682699
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2721696406
Short name T852
Test name
Test status
Simulation time 217874035 ps
CPU time 8.69 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:07 PM PDT 24
Peak memory 226044 kb
Host smart-09594be5-17b4-4ff6-8d30-9d758b2f4710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721696406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2721696406
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4151202188
Short name T531
Test name
Test status
Simulation time 290061318 ps
CPU time 7.78 seconds
Started Aug 19 06:00:56 PM PDT 24
Finished Aug 19 06:01:04 PM PDT 24
Peak memory 225192 kb
Host smart-8621af50-f775-4458-8b63-0c3858235962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151202188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4151202188
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1368145847
Short name T17
Test name
Test status
Simulation time 57857968 ps
CPU time 2.8 seconds
Started Aug 19 06:00:57 PM PDT 24
Finished Aug 19 06:01:00 PM PDT 24
Peak memory 214788 kb
Host smart-bd28a012-877b-4c3e-a8ac-7df2a3b76640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368145847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1368145847
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1672705251
Short name T746
Test name
Test status
Simulation time 287075988 ps
CPU time 26.78 seconds
Started Aug 19 06:00:56 PM PDT 24
Finished Aug 19 06:01:23 PM PDT 24
Peak memory 250920 kb
Host smart-dcc931e9-cd41-4432-ac31-10565cd1e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672705251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1672705251
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3054648997
Short name T414
Test name
Test status
Simulation time 412619917 ps
CPU time 6.74 seconds
Started Aug 19 06:00:56 PM PDT 24
Finished Aug 19 06:01:03 PM PDT 24
Peak memory 250336 kb
Host smart-44dc810e-01f4-490c-b01f-a2d69411058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054648997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3054648997
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4092142135
Short name T576
Test name
Test status
Simulation time 24422669402 ps
CPU time 151.72 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:03:30 PM PDT 24
Peak memory 251004 kb
Host smart-92970b4c-573a-4c41-ab3a-325a5fc444d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092142135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4092142135
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1134905785
Short name T803
Test name
Test status
Simulation time 32346251 ps
CPU time 0.8 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:00:59 PM PDT 24
Peak memory 211928 kb
Host smart-2d11035c-33fb-418a-9190-c5ec189f6088
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134905785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1134905785
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1471416885
Short name T637
Test name
Test status
Simulation time 80342701 ps
CPU time 0.92 seconds
Started Aug 19 06:01:06 PM PDT 24
Finished Aug 19 06:01:07 PM PDT 24
Peak memory 209060 kb
Host smart-b42165ef-d302-4850-a6cf-8b8a9b31a0d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471416885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1471416885
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2428609588
Short name T366
Test name
Test status
Simulation time 524743949 ps
CPU time 21.19 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:20 PM PDT 24
Peak memory 218104 kb
Host smart-50692d7f-ab93-4752-a5ec-6da5aee7af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428609588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2428609588
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.596055481
Short name T246
Test name
Test status
Simulation time 75171304 ps
CPU time 1.42 seconds
Started Aug 19 06:00:55 PM PDT 24
Finished Aug 19 06:00:57 PM PDT 24
Peak memory 217084 kb
Host smart-dbed8005-0d96-4846-bb18-1ea377fdda19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596055481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.596055481
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2517704266
Short name T265
Test name
Test status
Simulation time 325645113 ps
CPU time 2.61 seconds
Started Aug 19 06:00:54 PM PDT 24
Finished Aug 19 06:00:57 PM PDT 24
Peak memory 218252 kb
Host smart-5ff631e7-f399-4c71-88c4-73aad448c94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517704266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2517704266
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2455301549
Short name T269
Test name
Test status
Simulation time 3974249349 ps
CPU time 14.67 seconds
Started Aug 19 06:00:59 PM PDT 24
Finished Aug 19 06:01:14 PM PDT 24
Peak memory 219136 kb
Host smart-9045d640-1afc-4208-9b1a-413bee8256a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455301549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2455301549
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2214136505
Short name T730
Test name
Test status
Simulation time 3672322987 ps
CPU time 11.27 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 226116 kb
Host smart-1d6c771e-c1a6-4fc1-a26e-9d8f74785a9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214136505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2214136505
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1337403367
Short name T237
Test name
Test status
Simulation time 312318131 ps
CPU time 11.03 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 218192 kb
Host smart-fdc962cb-68da-48c8-b885-b6f840588b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337403367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1337403367
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.42372801
Short name T417
Test name
Test status
Simulation time 404957897 ps
CPU time 10.78 seconds
Started Aug 19 06:00:57 PM PDT 24
Finished Aug 19 06:01:08 PM PDT 24
Peak memory 226132 kb
Host smart-418c8cfc-73dd-47c6-b2d2-d66a4efba206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42372801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.42372801
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1426673714
Short name T612
Test name
Test status
Simulation time 117741052 ps
CPU time 1.98 seconds
Started Aug 19 06:00:55 PM PDT 24
Finished Aug 19 06:00:57 PM PDT 24
Peak memory 217616 kb
Host smart-fd202b1b-c5df-42cc-aae1-8ba556d4dc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426673714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1426673714
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1539501428
Short name T268
Test name
Test status
Simulation time 258600273 ps
CPU time 27.27 seconds
Started Aug 19 06:00:58 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 250856 kb
Host smart-943486d6-4eeb-46b0-b0e9-fedccf166664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539501428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1539501428
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3317752898
Short name T290
Test name
Test status
Simulation time 81043919 ps
CPU time 4.35 seconds
Started Aug 19 06:01:02 PM PDT 24
Finished Aug 19 06:01:06 PM PDT 24
Peak memory 222808 kb
Host smart-c540e732-5e11-4fb0-885c-827fc13cf4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317752898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3317752898
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3174484695
Short name T96
Test name
Test status
Simulation time 6247879188 ps
CPU time 135.58 seconds
Started Aug 19 06:01:07 PM PDT 24
Finished Aug 19 06:03:23 PM PDT 24
Peak memory 253356 kb
Host smart-424425f9-dc53-41ad-9b6f-1889f8d4fe49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174484695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3174484695
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.55420861
Short name T732
Test name
Test status
Simulation time 21936211 ps
CPU time 0.99 seconds
Started Aug 19 06:00:55 PM PDT 24
Finished Aug 19 06:00:56 PM PDT 24
Peak memory 211852 kb
Host smart-1e458d85-ec13-478c-9c66-8dfcd86af031
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55420861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctr
l_volatile_unlock_smoke.55420861
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1411162142
Short name T71
Test name
Test status
Simulation time 31443681 ps
CPU time 1.08 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:05 PM PDT 24
Peak memory 209100 kb
Host smart-148509fc-2822-484b-a084-34b26d708ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411162142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1411162142
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1316599237
Short name T665
Test name
Test status
Simulation time 1762071539 ps
CPU time 13.34 seconds
Started Aug 19 06:01:11 PM PDT 24
Finished Aug 19 06:01:24 PM PDT 24
Peak memory 218396 kb
Host smart-7b7fd715-b12d-4d66-8918-db0a3d64077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316599237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1316599237
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2526834079
Short name T388
Test name
Test status
Simulation time 787832044 ps
CPU time 7.67 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:12 PM PDT 24
Peak memory 217384 kb
Host smart-7da2ad0f-6742-479e-88c1-0c3aa983ca75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526834079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2526834079
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3653754041
Short name T544
Test name
Test status
Simulation time 61965729 ps
CPU time 2.46 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:07 PM PDT 24
Peak memory 222336 kb
Host smart-2ddafaef-ee7e-4b78-8051-ec8093a46154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653754041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3653754041
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4201652872
Short name T288
Test name
Test status
Simulation time 539571481 ps
CPU time 10.81 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 218932 kb
Host smart-20a80241-4bf8-4c74-907f-f2db84fed6f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201652872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4201652872
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2541259213
Short name T60
Test name
Test status
Simulation time 424986538 ps
CPU time 12.03 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 225996 kb
Host smart-769a0294-3626-48e9-ad10-bb0601dc1a58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541259213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2541259213
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3553175338
Short name T546
Test name
Test status
Simulation time 487164955 ps
CPU time 9.43 seconds
Started Aug 19 06:01:05 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 226032 kb
Host smart-20e509f4-0240-4796-97b3-317b1de4d7e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553175338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3553175338
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1522497486
Short name T380
Test name
Test status
Simulation time 2664610142 ps
CPU time 9.92 seconds
Started Aug 19 06:01:03 PM PDT 24
Finished Aug 19 06:01:13 PM PDT 24
Peak memory 226152 kb
Host smart-355dd3c4-29bf-47a9-83f5-b3523d8cfdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522497486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1522497486
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2793466419
Short name T744
Test name
Test status
Simulation time 512700286 ps
CPU time 3.57 seconds
Started Aug 19 06:01:08 PM PDT 24
Finished Aug 19 06:01:11 PM PDT 24
Peak memory 217672 kb
Host smart-8d9dc6a0-5bce-4d68-9adf-f2d6e1b0683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793466419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2793466419
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2442531734
Short name T680
Test name
Test status
Simulation time 214869251 ps
CPU time 24.51 seconds
Started Aug 19 06:01:10 PM PDT 24
Finished Aug 19 06:01:35 PM PDT 24
Peak memory 250960 kb
Host smart-08b8367e-28f0-4beb-ba4f-f95201b6762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442531734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2442531734
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.633626236
Short name T302
Test name
Test status
Simulation time 235462248 ps
CPU time 7.74 seconds
Started Aug 19 06:01:07 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 243440 kb
Host smart-cdeec74b-96ce-44ef-9ab1-831bf5ae7a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633626236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.633626236
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1781601876
Short name T381
Test name
Test status
Simulation time 19257422965 ps
CPU time 75.25 seconds
Started Aug 19 06:01:03 PM PDT 24
Finished Aug 19 06:02:19 PM PDT 24
Peak memory 238764 kb
Host smart-6a091bf8-11ca-495d-8240-e9d0bbd0549f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781601876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1781601876
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2896974665
Short name T669
Test name
Test status
Simulation time 17484648 ps
CPU time 0.84 seconds
Started Aug 19 06:01:03 PM PDT 24
Finished Aug 19 06:01:04 PM PDT 24
Peak memory 211968 kb
Host smart-8b4ef65f-73cd-452f-b04f-c7fe53b1c90c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896974665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2896974665
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1804121132
Short name T753
Test name
Test status
Simulation time 17590545 ps
CPU time 0.87 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:05 PM PDT 24
Peak memory 208868 kb
Host smart-75cee3c3-e43b-4cfd-bd20-d27aa5cba637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804121132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1804121132
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2844695267
Short name T548
Test name
Test status
Simulation time 1697461011 ps
CPU time 21.01 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 218296 kb
Host smart-71c10349-9d54-497b-b4a4-051aca0aef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844695267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2844695267
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3680133178
Short name T465
Test name
Test status
Simulation time 204808331 ps
CPU time 5.93 seconds
Started Aug 19 06:01:05 PM PDT 24
Finished Aug 19 06:01:11 PM PDT 24
Peak memory 217276 kb
Host smart-e7cd0a78-3e5d-4a02-a42c-ac725f21a120
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680133178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3680133178
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2908534067
Short name T519
Test name
Test status
Simulation time 65303905 ps
CPU time 3.44 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:07 PM PDT 24
Peak memory 222612 kb
Host smart-b37143be-5ca6-4395-8169-6d03c77b4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908534067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2908534067
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1201010436
Short name T422
Test name
Test status
Simulation time 371411514 ps
CPU time 15.4 seconds
Started Aug 19 06:01:07 PM PDT 24
Finished Aug 19 06:01:23 PM PDT 24
Peak memory 226284 kb
Host smart-228ea20a-d162-4979-a892-90451cef47af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201010436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1201010436
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2195744024
Short name T745
Test name
Test status
Simulation time 260369083 ps
CPU time 12.06 seconds
Started Aug 19 06:01:08 PM PDT 24
Finished Aug 19 06:01:20 PM PDT 24
Peak memory 226064 kb
Host smart-2e048021-d953-4065-8f89-5abbae115563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195744024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2195744024
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3976141953
Short name T784
Test name
Test status
Simulation time 310636715 ps
CPU time 9.69 seconds
Started Aug 19 06:01:05 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 218336 kb
Host smart-34d29c12-bc37-44ae-b720-ece97f89f252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976141953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3976141953
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.287168840
Short name T599
Test name
Test status
Simulation time 366005274 ps
CPU time 10 seconds
Started Aug 19 06:01:05 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 218364 kb
Host smart-7fbbceec-08d7-41e8-bfda-d69dbf925845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287168840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.287168840
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2777626228
Short name T82
Test name
Test status
Simulation time 87949586 ps
CPU time 1.49 seconds
Started Aug 19 06:01:04 PM PDT 24
Finished Aug 19 06:01:05 PM PDT 24
Peak memory 217656 kb
Host smart-4e13abfa-e1ee-4bab-aa26-0f74de6e885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777626228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2777626228
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.811816158
Short name T765
Test name
Test status
Simulation time 314736588 ps
CPU time 31.67 seconds
Started Aug 19 06:01:03 PM PDT 24
Finished Aug 19 06:01:35 PM PDT 24
Peak memory 250920 kb
Host smart-22daf99b-32e9-4208-821e-0f65be1bdbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811816158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.811816158
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1959428827
Short name T631
Test name
Test status
Simulation time 78109485 ps
CPU time 8.48 seconds
Started Aug 19 06:01:05 PM PDT 24
Finished Aug 19 06:01:14 PM PDT 24
Peak memory 250932 kb
Host smart-5b4a3c89-10e5-4c3d-b6d2-8346fb57b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959428827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1959428827
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1237656494
Short name T653
Test name
Test status
Simulation time 3728295916 ps
CPU time 42.25 seconds
Started Aug 19 06:01:03 PM PDT 24
Finished Aug 19 06:01:46 PM PDT 24
Peak memory 228048 kb
Host smart-eaf233a3-448d-4641-a558-7651d02f8415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237656494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1237656494
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2903520271
Short name T663
Test name
Test status
Simulation time 88368300 ps
CPU time 0.9 seconds
Started Aug 19 06:01:05 PM PDT 24
Finished Aug 19 06:01:06 PM PDT 24
Peak memory 211908 kb
Host smart-ef55e209-abe3-4d31-8c68-f6259c178b7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903520271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2903520271
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1052757732
Short name T93
Test name
Test status
Simulation time 85266138 ps
CPU time 0.83 seconds
Started Aug 19 06:01:23 PM PDT 24
Finished Aug 19 06:01:24 PM PDT 24
Peak memory 208692 kb
Host smart-8d887f9f-17cc-4a9c-b60f-f4fd1afbc2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052757732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1052757732
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.18448917
Short name T7
Test name
Test status
Simulation time 289844915 ps
CPU time 3.31 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:17 PM PDT 24
Peak memory 217032 kb
Host smart-a2a045d2-2373-433f-ae6e-00d37d92af16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.18448917
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.70657453
Short name T407
Test name
Test status
Simulation time 18967585 ps
CPU time 1.56 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:15 PM PDT 24
Peak memory 218384 kb
Host smart-b8b45241-00ce-4a66-a288-54cfb129b847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70657453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.70657453
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3660055683
Short name T64
Test name
Test status
Simulation time 518187197 ps
CPU time 7.98 seconds
Started Aug 19 06:01:12 PM PDT 24
Finished Aug 19 06:01:20 PM PDT 24
Peak memory 226096 kb
Host smart-61c91fbc-331e-46d6-bf54-71a6ff7aa560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660055683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3660055683
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.392612670
Short name T249
Test name
Test status
Simulation time 338507770 ps
CPU time 10.19 seconds
Started Aug 19 06:01:23 PM PDT 24
Finished Aug 19 06:01:33 PM PDT 24
Peak memory 226048 kb
Host smart-306c3a41-0d4c-4701-99e0-cfb26f2662ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392612670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.392612670
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3923209272
Short name T566
Test name
Test status
Simulation time 823823515 ps
CPU time 8.26 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:23 PM PDT 24
Peak memory 218240 kb
Host smart-d7eb5157-97dc-4bdf-a5c0-b55bc17ea689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923209272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3923209272
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3649602276
Short name T277
Test name
Test status
Simulation time 639638932 ps
CPU time 8.04 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:22 PM PDT 24
Peak memory 226088 kb
Host smart-2f110304-6d68-4cad-9817-e85b9bd12c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649602276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3649602276
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.273602100
Short name T685
Test name
Test status
Simulation time 100143555 ps
CPU time 1.36 seconds
Started Aug 19 06:01:10 PM PDT 24
Finished Aug 19 06:01:12 PM PDT 24
Peak memory 222008 kb
Host smart-34ea8c2b-b9cc-42d1-baae-532b4b2bd190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273602100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.273602100
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1293187778
Short name T278
Test name
Test status
Simulation time 2353143356 ps
CPU time 19.56 seconds
Started Aug 19 06:01:03 PM PDT 24
Finished Aug 19 06:01:23 PM PDT 24
Peak memory 250932 kb
Host smart-16f66052-394c-42ca-bce2-e3c6493a6a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293187778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1293187778
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.58697061
Short name T240
Test name
Test status
Simulation time 148779409 ps
CPU time 10.69 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 250908 kb
Host smart-449161b1-98d5-4ebd-9fa1-5e7608e7fba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58697061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.58697061
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2954733211
Short name T163
Test name
Test status
Simulation time 3485184626 ps
CPU time 35.88 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 250936 kb
Host smart-86d673f4-3254-480e-9aa6-b6cb972967a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2954733211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2954733211
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.4006588710
Short name T261
Test name
Test status
Simulation time 26310000 ps
CPU time 0.88 seconds
Started Aug 19 06:01:05 PM PDT 24
Finished Aug 19 06:01:06 PM PDT 24
Peak memory 211952 kb
Host smart-47ace457-ffe8-4ea9-a4f9-56f767a45056
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006588710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.4006588710
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.72082679
Short name T229
Test name
Test status
Simulation time 91766950 ps
CPU time 1.24 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 209064 kb
Host smart-528b95d8-7c4b-4baf-9fc6-350d1972012b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72082679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.72082679
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3518836811
Short name T571
Test name
Test status
Simulation time 2047598586 ps
CPU time 14.48 seconds
Started Aug 19 06:01:24 PM PDT 24
Finished Aug 19 06:01:38 PM PDT 24
Peak memory 226108 kb
Host smart-3ec50dc4-855c-41ee-b874-6ca47f6e2493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518836811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3518836811
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1599806676
Short name T534
Test name
Test status
Simulation time 269980439 ps
CPU time 2.31 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 217004 kb
Host smart-9e5fb7a5-7833-4ae0-8935-83a2a0b8e764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599806676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1599806676
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3637946340
Short name T270
Test name
Test status
Simulation time 61685352 ps
CPU time 3.24 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 218316 kb
Host smart-2842cb4b-2a7b-49b4-b753-1968ee00a6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637946340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3637946340
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3467063518
Short name T514
Test name
Test status
Simulation time 445558049 ps
CPU time 13.03 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:26 PM PDT 24
Peak memory 226084 kb
Host smart-66127fc9-1313-4c47-80a7-23e001b0bcb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467063518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3467063518
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1140148505
Short name T812
Test name
Test status
Simulation time 598123282 ps
CPU time 14.64 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:29 PM PDT 24
Peak memory 225924 kb
Host smart-903c0425-7105-4431-8f1e-19223170a0c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140148505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1140148505
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2440720036
Short name T701
Test name
Test status
Simulation time 743014452 ps
CPU time 8.36 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:22 PM PDT 24
Peak memory 218316 kb
Host smart-53aa38d1-4a4b-4204-866a-75e83a46a0fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440720036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2440720036
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2691938540
Short name T515
Test name
Test status
Simulation time 37571476 ps
CPU time 2 seconds
Started Aug 19 06:01:16 PM PDT 24
Finished Aug 19 06:01:18 PM PDT 24
Peak memory 214216 kb
Host smart-8c1a4496-50af-4412-bf71-3afbac7b3333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691938540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2691938540
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.976154820
Short name T286
Test name
Test status
Simulation time 281726190 ps
CPU time 25.62 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:38 PM PDT 24
Peak memory 250916 kb
Host smart-dd78d162-9152-44cb-8248-f1d9b1ae83ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976154820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.976154820
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1553837453
Short name T650
Test name
Test status
Simulation time 339123390 ps
CPU time 8.79 seconds
Started Aug 19 06:01:18 PM PDT 24
Finished Aug 19 06:01:27 PM PDT 24
Peak memory 250756 kb
Host smart-c617c443-cb9b-43c8-b127-a33e2ebd8e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553837453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1553837453
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3725503005
Short name T767
Test name
Test status
Simulation time 13150397 ps
CPU time 1.03 seconds
Started Aug 19 06:01:24 PM PDT 24
Finished Aug 19 06:01:25 PM PDT 24
Peak memory 211996 kb
Host smart-75143f1b-0c8b-49ff-b16d-f84bcba2a284
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725503005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3725503005
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3385345345
Short name T690
Test name
Test status
Simulation time 16011240 ps
CPU time 0.89 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 208832 kb
Host smart-96e274e2-f86f-4ed4-afed-dcefaeea5b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385345345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3385345345
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1485038419
Short name T604
Test name
Test status
Simulation time 316715072 ps
CPU time 11.27 seconds
Started Aug 19 06:01:17 PM PDT 24
Finished Aug 19 06:01:28 PM PDT 24
Peak memory 226128 kb
Host smart-5d77c2b6-4bdd-4e51-b5e0-d96c88d3eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485038419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1485038419
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1794530735
Short name T322
Test name
Test status
Simulation time 1809596316 ps
CPU time 5.62 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:20 PM PDT 24
Peak memory 217264 kb
Host smart-994da4d2-4a71-414f-bbf2-0938f13d1784
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794530735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1794530735
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2470338422
Short name T358
Test name
Test status
Simulation time 25190983 ps
CPU time 1.71 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:01:17 PM PDT 24
Peak memory 218284 kb
Host smart-7b9364ab-0421-489c-beaa-6f798890f93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470338422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2470338422
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.312356604
Short name T858
Test name
Test status
Simulation time 2623173019 ps
CPU time 16.17 seconds
Started Aug 19 06:01:24 PM PDT 24
Finished Aug 19 06:01:40 PM PDT 24
Peak memory 226176 kb
Host smart-d93090d4-40bd-4f79-9672-6cb01f5ec576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312356604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.312356604
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2396264919
Short name T109
Test name
Test status
Simulation time 703135286 ps
CPU time 13.36 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:28 PM PDT 24
Peak memory 226032 kb
Host smart-05c0b93e-7a3a-4399-a7f1-72811af1198e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396264919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2396264919
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3768321042
Short name T499
Test name
Test status
Simulation time 4405672239 ps
CPU time 8.26 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:01:24 PM PDT 24
Peak memory 226084 kb
Host smart-de110682-ca73-42bd-aa2a-09718429a974
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768321042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3768321042
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2383649602
Short name T786
Test name
Test status
Simulation time 1633668784 ps
CPU time 7.72 seconds
Started Aug 19 06:01:24 PM PDT 24
Finished Aug 19 06:01:32 PM PDT 24
Peak memory 224708 kb
Host smart-d6093e12-22a6-4e11-8695-1ceee08ce17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383649602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2383649602
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.4257752964
Short name T590
Test name
Test status
Simulation time 111301786 ps
CPU time 2.35 seconds
Started Aug 19 06:01:16 PM PDT 24
Finished Aug 19 06:01:18 PM PDT 24
Peak memory 214292 kb
Host smart-1c3c5f2c-a388-4d2a-b27c-c0a244ccb688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257752964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.4257752964
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2243593775
Short name T172
Test name
Test status
Simulation time 204193212 ps
CPU time 19.79 seconds
Started Aug 19 06:01:16 PM PDT 24
Finished Aug 19 06:01:36 PM PDT 24
Peak memory 250828 kb
Host smart-5504a7c0-3e90-45b9-bbb4-7b6dc35e74a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243593775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2243593775
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.929001458
Short name T209
Test name
Test status
Simulation time 198294483 ps
CPU time 7.42 seconds
Started Aug 19 06:01:17 PM PDT 24
Finished Aug 19 06:01:24 PM PDT 24
Peak memory 250956 kb
Host smart-83b584e9-8666-43a6-b714-257b6b1b3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929001458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.929001458
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2600851848
Short name T823
Test name
Test status
Simulation time 31827465230 ps
CPU time 132.9 seconds
Started Aug 19 06:01:17 PM PDT 24
Finished Aug 19 06:03:30 PM PDT 24
Peak memory 242636 kb
Host smart-4387f991-5f17-4192-8a9c-73dfda5ceb53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600851848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2600851848
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3114884658
Short name T575
Test name
Test status
Simulation time 4901009029 ps
CPU time 64.33 seconds
Started Aug 19 06:01:23 PM PDT 24
Finished Aug 19 06:02:27 PM PDT 24
Peak memory 270240 kb
Host smart-8ff4f40f-f021-4d60-8eba-02afd4b36802
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3114884658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3114884658
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.816215740
Short name T508
Test name
Test status
Simulation time 15501441 ps
CPU time 0.87 seconds
Started Aug 19 06:01:11 PM PDT 24
Finished Aug 19 06:01:12 PM PDT 24
Peak memory 211904 kb
Host smart-c79554d2-4264-46ab-8ece-329c78eff324
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816215740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.816215740
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3686984909
Short name T584
Test name
Test status
Simulation time 23169981 ps
CPU time 0.99 seconds
Started Aug 19 05:58:15 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 208892 kb
Host smart-e9d6cee4-dbf7-4b12-9ee2-e2595e3ac548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686984909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3686984909
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.526077591
Short name T323
Test name
Test status
Simulation time 10421337 ps
CPU time 0.83 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 208612 kb
Host smart-6ac443bc-7e31-4475-805c-5f4ad5d764c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526077591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.526077591
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2624589887
Short name T771
Test name
Test status
Simulation time 590011445 ps
CPU time 12.53 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 218324 kb
Host smart-6ba2128f-2794-4a8f-bc5d-628cb8b5573d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624589887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2624589887
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1090289831
Short name T855
Test name
Test status
Simulation time 96357683 ps
CPU time 3.09 seconds
Started Aug 19 05:58:14 PM PDT 24
Finished Aug 19 05:58:18 PM PDT 24
Peak memory 217064 kb
Host smart-32101e17-d1ef-4c8b-aa92-d4719f8e2e89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090289831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1090289831
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3085645869
Short name T324
Test name
Test status
Simulation time 9953442644 ps
CPU time 33.18 seconds
Started Aug 19 05:58:15 PM PDT 24
Finished Aug 19 05:58:48 PM PDT 24
Peak memory 218940 kb
Host smart-6e5a0d3d-04ca-45f2-8183-bc662afb801f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085645869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3085645869
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2698824386
Short name T49
Test name
Test status
Simulation time 15352564214 ps
CPU time 11.06 seconds
Started Aug 19 05:58:17 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 217792 kb
Host smart-23501e4d-7094-4e28-be38-a1aef57a3671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698824386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
698824386
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.230446397
Short name T818
Test name
Test status
Simulation time 786583723 ps
CPU time 10.81 seconds
Started Aug 19 05:58:14 PM PDT 24
Finished Aug 19 05:58:25 PM PDT 24
Peak memory 225480 kb
Host smart-d3642342-375b-4183-bb8c-ed51744e0cbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230446397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.230446397
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4040585738
Short name T79
Test name
Test status
Simulation time 3065740885 ps
CPU time 18.09 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:58:34 PM PDT 24
Peak memory 217624 kb
Host smart-ae2e6518-5c5a-4551-9359-dbcfa26f595c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040585738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.4040585738
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2673207299
Short name T617
Test name
Test status
Simulation time 1443626557 ps
CPU time 7.04 seconds
Started Aug 19 05:58:14 PM PDT 24
Finished Aug 19 05:58:21 PM PDT 24
Peak memory 217580 kb
Host smart-cd7d7242-58fb-4987-84ab-d92193b7ced0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673207299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2673207299
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.820246720
Short name T872
Test name
Test status
Simulation time 2832997880 ps
CPU time 22.86 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:58:39 PM PDT 24
Peak memory 250928 kb
Host smart-5e71d38e-a288-42fb-af0f-d4fe25f66895
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820246720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.820246720
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1173225844
Short name T719
Test name
Test status
Simulation time 25477629 ps
CPU time 1.76 seconds
Started Aug 19 05:58:17 PM PDT 24
Finished Aug 19 05:58:19 PM PDT 24
Peak memory 218284 kb
Host smart-90af71db-6742-47b7-b91c-ac00f628c4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173225844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1173225844
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.307079980
Short name T86
Test name
Test status
Simulation time 237368235 ps
CPU time 12.7 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:58:29 PM PDT 24
Peak memory 217792 kb
Host smart-312b2e09-8147-41f3-bce0-218f4afcb8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307079980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.307079980
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3162903983
Short name T98
Test name
Test status
Simulation time 290137316 ps
CPU time 21.4 seconds
Started Aug 19 05:58:15 PM PDT 24
Finished Aug 19 05:58:37 PM PDT 24
Peak memory 282264 kb
Host smart-3752d626-99f2-4337-b611-5709f540af3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162903983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3162903983
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1249351233
Short name T870
Test name
Test status
Simulation time 3226904468 ps
CPU time 18.35 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:58:34 PM PDT 24
Peak memory 219040 kb
Host smart-d705e415-39b9-4772-a4e6-c54231735dc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249351233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1249351233
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2847434438
Short name T559
Test name
Test status
Simulation time 294620063 ps
CPU time 11.96 seconds
Started Aug 19 05:58:16 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 226016 kb
Host smart-32faa5f8-a08b-4989-bc87-0ada94d558a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847434438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2847434438
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.723029423
Short name T578
Test name
Test status
Simulation time 319934742 ps
CPU time 10.92 seconds
Started Aug 19 05:58:15 PM PDT 24
Finished Aug 19 05:58:26 PM PDT 24
Peak memory 218268 kb
Host smart-a529407d-8b7e-493e-b21f-a501357b31b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723029423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.723029423
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3467492326
Short name T518
Test name
Test status
Simulation time 387937901 ps
CPU time 8.87 seconds
Started Aug 19 05:58:15 PM PDT 24
Finished Aug 19 05:58:24 PM PDT 24
Peak memory 226080 kb
Host smart-161627ce-ef85-4395-88f0-1b396271ab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467492326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3467492326
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1835507010
Short name T460
Test name
Test status
Simulation time 107932248 ps
CPU time 2.32 seconds
Started Aug 19 05:58:15 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 217728 kb
Host smart-035279b2-2f20-4d7c-801e-496fe0954427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835507010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1835507010
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3443118635
Short name T452
Test name
Test status
Simulation time 542657402 ps
CPU time 22.52 seconds
Started Aug 19 05:58:14 PM PDT 24
Finished Aug 19 05:58:37 PM PDT 24
Peak memory 247096 kb
Host smart-764510d4-841b-4158-928b-d26029535b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443118635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3443118635
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2773310478
Short name T212
Test name
Test status
Simulation time 144080593 ps
CPU time 3.04 seconds
Started Aug 19 05:58:14 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 226340 kb
Host smart-66e5a19f-710d-4d10-af11-d56ab34b3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773310478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2773310478
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3882309815
Short name T609
Test name
Test status
Simulation time 10942490161 ps
CPU time 39.31 seconds
Started Aug 19 05:58:13 PM PDT 24
Finished Aug 19 05:58:52 PM PDT 24
Peak memory 251028 kb
Host smart-34288ca4-e73f-4fff-98b0-a29442ac9045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882309815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3882309815
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1614388899
Short name T539
Test name
Test status
Simulation time 74148826 ps
CPU time 0.84 seconds
Started Aug 19 05:58:17 PM PDT 24
Finished Aug 19 05:58:18 PM PDT 24
Peak memory 211984 kb
Host smart-012d1930-b353-45dd-9219-0b8bc4ffaf8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614388899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1614388899
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.704173185
Short name T469
Test name
Test status
Simulation time 22166428 ps
CPU time 1.24 seconds
Started Aug 19 06:01:30 PM PDT 24
Finished Aug 19 06:01:32 PM PDT 24
Peak memory 209096 kb
Host smart-69ef7507-c888-41ba-a86c-da65fa026b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704173185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.704173185
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3875663470
Short name T740
Test name
Test status
Simulation time 368309861 ps
CPU time 11.36 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:26 PM PDT 24
Peak memory 226116 kb
Host smart-9967afb7-403f-4750-aadf-161b3f68b8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875663470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3875663470
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3963723581
Short name T9
Test name
Test status
Simulation time 226746556 ps
CPU time 2.2 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 217132 kb
Host smart-33d29d86-5225-4812-9e48-8adec11e3bbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963723581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3963723581
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2886792840
Short name T276
Test name
Test status
Simulation time 77810416 ps
CPU time 1.54 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:01:16 PM PDT 24
Peak memory 221896 kb
Host smart-fd6205d2-0ca5-4a80-a32b-6e7190eec46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886792840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2886792840
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3502440227
Short name T343
Test name
Test status
Simulation time 562364018 ps
CPU time 11.83 seconds
Started Aug 19 06:01:18 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 218692 kb
Host smart-dd2b942b-3dc7-4871-9c7e-417519d65674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502440227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3502440227
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1483284890
Short name T565
Test name
Test status
Simulation time 402841784 ps
CPU time 14.45 seconds
Started Aug 19 06:01:42 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 224800 kb
Host smart-c6915446-91aa-4e6e-a32d-a13c6042340a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483284890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1483284890
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1623397897
Short name T620
Test name
Test status
Simulation time 2753993218 ps
CPU time 7.06 seconds
Started Aug 19 06:01:14 PM PDT 24
Finished Aug 19 06:01:21 PM PDT 24
Peak memory 218304 kb
Host smart-9b69d87d-18d6-41dc-9a2c-5654a3954709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623397897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1623397897
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2199120032
Short name T87
Test name
Test status
Simulation time 2613833956 ps
CPU time 13.49 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:01:28 PM PDT 24
Peak memory 224916 kb
Host smart-93374e87-10ee-4041-b606-ef39b36c4937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199120032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2199120032
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3370431893
Short name T245
Test name
Test status
Simulation time 45172489 ps
CPU time 2.98 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:01:18 PM PDT 24
Peak memory 213416 kb
Host smart-97ae4a76-b20b-4270-b51e-efdc1cb5ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370431893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3370431893
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3282314539
Short name T501
Test name
Test status
Simulation time 1928513197 ps
CPU time 33.56 seconds
Started Aug 19 06:01:13 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 250924 kb
Host smart-bce807bf-2e08-4ac2-9481-fc2151cafc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282314539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3282314539
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2268138759
Short name T317
Test name
Test status
Simulation time 205438439 ps
CPU time 8.27 seconds
Started Aug 19 06:01:15 PM PDT 24
Finished Aug 19 06:01:24 PM PDT 24
Peak memory 250956 kb
Host smart-e7c9cc3f-53aa-448c-be5e-5b7b5bb44545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268138759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2268138759
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1619391897
Short name T832
Test name
Test status
Simulation time 39698966501 ps
CPU time 282.77 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 314904 kb
Host smart-8bebd47d-ff09-4b76-878c-c39341fe0816
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619391897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1619391897
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3107203681
Short name T716
Test name
Test status
Simulation time 60503439 ps
CPU time 0.8 seconds
Started Aug 19 06:01:16 PM PDT 24
Finished Aug 19 06:01:17 PM PDT 24
Peak memory 211880 kb
Host smart-682df182-3c77-4d9c-9e37-188cff49a6c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107203681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3107203681
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2291253979
Short name T819
Test name
Test status
Simulation time 28011958 ps
CPU time 1.28 seconds
Started Aug 19 06:01:27 PM PDT 24
Finished Aug 19 06:01:29 PM PDT 24
Peak memory 209040 kb
Host smart-538f0a5e-42a3-400e-afae-d97694608b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291253979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2291253979
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3429270530
Short name T806
Test name
Test status
Simulation time 1990022579 ps
CPU time 15.93 seconds
Started Aug 19 06:01:31 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 226080 kb
Host smart-1060b765-252e-4c37-a677-0f17d0a7c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429270530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3429270530
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3947441274
Short name T36
Test name
Test status
Simulation time 7194393874 ps
CPU time 6.22 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:35 PM PDT 24
Peak memory 217736 kb
Host smart-6ab08e57-913a-4099-a2b8-71b610f42a93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947441274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3947441274
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2056132985
Short name T334
Test name
Test status
Simulation time 125818716 ps
CPU time 1.89 seconds
Started Aug 19 06:01:32 PM PDT 24
Finished Aug 19 06:01:34 PM PDT 24
Peak memory 218184 kb
Host smart-2852918c-7cf9-4b5c-969a-8baed07b3a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056132985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2056132985
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1428063420
Short name T509
Test name
Test status
Simulation time 469699546 ps
CPU time 9.69 seconds
Started Aug 19 06:01:27 PM PDT 24
Finished Aug 19 06:01:37 PM PDT 24
Peak memory 226032 kb
Host smart-d0ae5c99-05d6-48ec-8a2d-438ecbfcbbab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428063420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1428063420
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2599360885
Short name T707
Test name
Test status
Simulation time 1923891841 ps
CPU time 12.69 seconds
Started Aug 19 06:01:29 PM PDT 24
Finished Aug 19 06:01:42 PM PDT 24
Peak memory 218244 kb
Host smart-a082535e-3331-4ea9-8cce-30164d6c1741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599360885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2599360885
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1670104338
Short name T692
Test name
Test status
Simulation time 454359947 ps
CPU time 5.87 seconds
Started Aug 19 06:01:30 PM PDT 24
Finished Aug 19 06:01:36 PM PDT 24
Peak memory 224868 kb
Host smart-53783b24-68e4-4d86-8bdd-248ce475aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670104338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1670104338
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.921859848
Short name T312
Test name
Test status
Simulation time 431371566 ps
CPU time 2.73 seconds
Started Aug 19 06:01:29 PM PDT 24
Finished Aug 19 06:01:32 PM PDT 24
Peak memory 222556 kb
Host smart-00488d2d-0f87-41a7-9b1b-8755bbbe3966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921859848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.921859848
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.544531806
Short name T328
Test name
Test status
Simulation time 1923403935 ps
CPU time 19.03 seconds
Started Aug 19 06:01:31 PM PDT 24
Finished Aug 19 06:01:50 PM PDT 24
Peak memory 250892 kb
Host smart-f7c46cfa-d29f-4502-95f6-c6999874ee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544531806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.544531806
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.420853351
Short name T213
Test name
Test status
Simulation time 244928693 ps
CPU time 7.86 seconds
Started Aug 19 06:01:27 PM PDT 24
Finished Aug 19 06:01:35 PM PDT 24
Peak memory 250916 kb
Host smart-98b85b84-138d-406b-8997-7e02ea5bda5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420853351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.420853351
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1988307303
Short name T103
Test name
Test status
Simulation time 517400856 ps
CPU time 28.67 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:57 PM PDT 24
Peak memory 250900 kb
Host smart-8db0f420-c930-4700-82bd-b4b265311256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988307303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1988307303
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3048627124
Short name T668
Test name
Test status
Simulation time 15268537 ps
CPU time 1.1 seconds
Started Aug 19 06:01:31 PM PDT 24
Finished Aug 19 06:01:32 PM PDT 24
Peak memory 212000 kb
Host smart-ad5500e6-52cc-4870-aa7b-a87bcf4de00f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048627124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3048627124
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1266172128
Short name T321
Test name
Test status
Simulation time 17945472 ps
CPU time 0.89 seconds
Started Aug 19 06:01:27 PM PDT 24
Finished Aug 19 06:01:28 PM PDT 24
Peak memory 208880 kb
Host smart-4f05bbeb-fcd3-4f3b-a83c-ffe63c122297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266172128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1266172128
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2667882542
Short name T659
Test name
Test status
Simulation time 1271121367 ps
CPU time 9.03 seconds
Started Aug 19 06:01:31 PM PDT 24
Finished Aug 19 06:01:40 PM PDT 24
Peak memory 226084 kb
Host smart-1e4bad39-107a-4155-be86-5841632daabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667882542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2667882542
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1192293110
Short name T747
Test name
Test status
Simulation time 1738925344 ps
CPU time 10.76 seconds
Started Aug 19 06:01:31 PM PDT 24
Finished Aug 19 06:01:41 PM PDT 24
Peak memory 217432 kb
Host smart-e0b3888b-0e72-4bb4-9507-15a31c3e6453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192293110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1192293110
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3302658745
Short name T688
Test name
Test status
Simulation time 24040412 ps
CPU time 1.61 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 218296 kb
Host smart-f46dfb06-69b1-49e2-ae59-055ca85b55d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302658745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3302658745
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1265056006
Short name T720
Test name
Test status
Simulation time 518687860 ps
CPU time 14.08 seconds
Started Aug 19 06:01:30 PM PDT 24
Finished Aug 19 06:01:44 PM PDT 24
Peak memory 218956 kb
Host smart-af15cc72-e7eb-442a-a1d0-43b3aecb5156
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265056006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1265056006
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3800793471
Short name T805
Test name
Test status
Simulation time 697522285 ps
CPU time 14.07 seconds
Started Aug 19 06:01:30 PM PDT 24
Finished Aug 19 06:01:45 PM PDT 24
Peak memory 226056 kb
Host smart-ae0672ab-1fff-4156-b975-b573925d927d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800793471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3800793471
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3201998117
Short name T275
Test name
Test status
Simulation time 355965107 ps
CPU time 11.56 seconds
Started Aug 19 06:01:29 PM PDT 24
Finished Aug 19 06:01:40 PM PDT 24
Peak memory 218208 kb
Host smart-b82776b3-d152-4104-88c8-9b3a083cbc6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201998117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3201998117
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.243754125
Short name T621
Test name
Test status
Simulation time 258807482 ps
CPU time 10.56 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:38 PM PDT 24
Peak memory 225008 kb
Host smart-d3987292-7c91-4157-9f9a-81bda604ee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243754125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.243754125
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3561996805
Short name T401
Test name
Test status
Simulation time 38849781 ps
CPU time 2.35 seconds
Started Aug 19 06:01:32 PM PDT 24
Finished Aug 19 06:01:34 PM PDT 24
Peak memory 217604 kb
Host smart-73c51187-540a-4d06-9432-f7dab557fcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561996805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3561996805
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1130522537
Short name T789
Test name
Test status
Simulation time 586676695 ps
CPU time 26.78 seconds
Started Aug 19 06:01:30 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 247320 kb
Host smart-499d0790-a5fd-4076-a913-e0514e6af026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130522537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1130522537
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2364431543
Short name T354
Test name
Test status
Simulation time 307010875 ps
CPU time 6.48 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:35 PM PDT 24
Peak memory 250404 kb
Host smart-eebef822-9d8b-4304-909d-dc62b43aa1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364431543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2364431543
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2201933678
Short name T648
Test name
Test status
Simulation time 5986905457 ps
CPU time 52.79 seconds
Started Aug 19 06:01:29 PM PDT 24
Finished Aug 19 06:02:21 PM PDT 24
Peak memory 250976 kb
Host smart-853b7063-bd7d-49e2-a8af-e134469c270f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201933678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2201933678
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2974108715
Short name T204
Test name
Test status
Simulation time 65805947 ps
CPU time 0.97 seconds
Started Aug 19 06:01:29 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 211972 kb
Host smart-9d1a4ca5-2aac-4c19-92ed-40155461bf5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974108715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2974108715
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1956550729
Short name T107
Test name
Test status
Simulation time 38897313 ps
CPU time 1.12 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:01:40 PM PDT 24
Peak memory 208972 kb
Host smart-b11f3153-258b-4e24-b514-4e52f810eaa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956550729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1956550729
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.193375732
Short name T483
Test name
Test status
Simulation time 1820298869 ps
CPU time 12.36 seconds
Started Aug 19 06:01:29 PM PDT 24
Finished Aug 19 06:01:41 PM PDT 24
Peak memory 218336 kb
Host smart-b0dfdac5-652b-4352-bb81-c45dda89736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193375732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.193375732
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2099666091
Short name T282
Test name
Test status
Simulation time 211909280 ps
CPU time 2.63 seconds
Started Aug 19 06:01:27 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 217044 kb
Host smart-a1f72f37-92e7-404c-a479-09fd7e66f342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099666091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2099666091
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2684377440
Short name T162
Test name
Test status
Simulation time 70870699 ps
CPU time 2.9 seconds
Started Aug 19 06:01:27 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 218272 kb
Host smart-59c89da7-95a4-4b1f-b273-2f033bb9ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684377440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2684377440
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.520611373
Short name T506
Test name
Test status
Simulation time 2810454665 ps
CPU time 13.48 seconds
Started Aug 19 06:01:27 PM PDT 24
Finished Aug 19 06:01:41 PM PDT 24
Peak memory 220040 kb
Host smart-764103e8-b8d1-41cb-a48a-44f1b4118170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520611373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.520611373
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1943413906
Short name T23
Test name
Test status
Simulation time 280407943 ps
CPU time 13 seconds
Started Aug 19 06:01:37 PM PDT 24
Finished Aug 19 06:01:51 PM PDT 24
Peak memory 226064 kb
Host smart-2dc9142d-836e-4648-ab7e-14ac0e060189
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943413906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1943413906
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3602062586
Short name T754
Test name
Test status
Simulation time 336760264 ps
CPU time 8.93 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 218236 kb
Host smart-63834773-ea5a-42b2-8fcd-4fddd50e7b75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602062586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3602062586
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1493166013
Short name T314
Test name
Test status
Simulation time 968146601 ps
CPU time 10.7 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:39 PM PDT 24
Peak memory 226084 kb
Host smart-12b1b315-74f2-4127-bb98-f906dbe016bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493166013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1493166013
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3884715921
Short name T862
Test name
Test status
Simulation time 125567304 ps
CPU time 1.82 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 217632 kb
Host smart-79a96818-9783-4822-8130-7da5300fc9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884715921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3884715921
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.261354134
Short name T695
Test name
Test status
Simulation time 1379967333 ps
CPU time 23.26 seconds
Started Aug 19 06:01:28 PM PDT 24
Finished Aug 19 06:01:51 PM PDT 24
Peak memory 247420 kb
Host smart-184a7b63-6ede-4b8b-a9ee-e836be64ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261354134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.261354134
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1029033640
Short name T520
Test name
Test status
Simulation time 161429511 ps
CPU time 2.52 seconds
Started Aug 19 06:01:30 PM PDT 24
Finished Aug 19 06:01:33 PM PDT 24
Peak memory 226468 kb
Host smart-60112421-99d9-4bb8-af8f-db552d8f0656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029033640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1029033640
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.105246648
Short name T804
Test name
Test status
Simulation time 26661740286 ps
CPU time 142.98 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 276328 kb
Host smart-1dfc56cf-0769-481d-9e15-ae24df21fb4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105246648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.105246648
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1481357335
Short name T148
Test name
Test status
Simulation time 4906090202 ps
CPU time 58.76 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:02:38 PM PDT 24
Peak memory 273008 kb
Host smart-ac0df57f-36e2-47f3-a8dd-ed8d26c15c88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1481357335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1481357335
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1189859434
Short name T428
Test name
Test status
Simulation time 31926112 ps
CPU time 0.84 seconds
Started Aug 19 06:01:29 PM PDT 24
Finished Aug 19 06:01:30 PM PDT 24
Peak memory 211968 kb
Host smart-7b943450-0d1d-4000-8ce8-c33c6e39325f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189859434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1189859434
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.664833341
Short name T415
Test name
Test status
Simulation time 19476664 ps
CPU time 0.9 seconds
Started Aug 19 06:01:42 PM PDT 24
Finished Aug 19 06:01:43 PM PDT 24
Peak memory 208860 kb
Host smart-ec12b9d1-221e-4950-a36d-60c62e61bc44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664833341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.664833341
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2116991792
Short name T171
Test name
Test status
Simulation time 831384464 ps
CPU time 18.02 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:01:57 PM PDT 24
Peak memory 218384 kb
Host smart-d563892e-b51f-4637-aee9-d0ae1ce55d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116991792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2116991792
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1013064917
Short name T610
Test name
Test status
Simulation time 337568422 ps
CPU time 4.61 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:01:44 PM PDT 24
Peak memory 217288 kb
Host smart-f240dde7-806c-4921-978f-316c2e78bc05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013064917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1013064917
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4066384857
Short name T785
Test name
Test status
Simulation time 319862750 ps
CPU time 2.92 seconds
Started Aug 19 06:01:37 PM PDT 24
Finished Aug 19 06:01:40 PM PDT 24
Peak memory 222412 kb
Host smart-ca12ce9b-02a1-4c5d-b867-d8a41a1b7f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066384857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4066384857
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1969835155
Short name T570
Test name
Test status
Simulation time 362738284 ps
CPU time 15.12 seconds
Started Aug 19 06:01:44 PM PDT 24
Finished Aug 19 06:01:59 PM PDT 24
Peak memory 226104 kb
Host smart-aa1f3922-03ee-42dd-850c-e46315fc956a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969835155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1969835155
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1009261459
Short name T678
Test name
Test status
Simulation time 690536770 ps
CPU time 23.09 seconds
Started Aug 19 06:01:37 PM PDT 24
Finished Aug 19 06:02:00 PM PDT 24
Peak memory 226012 kb
Host smart-86f46d8e-6568-47ad-8e3e-15462ccbeb85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009261459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1009261459
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3731160777
Short name T816
Test name
Test status
Simulation time 639851128 ps
CPU time 9.51 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 218240 kb
Host smart-a06de436-37f8-41b5-9e9e-ef7c25048840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731160777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3731160777
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1361392694
Short name T652
Test name
Test status
Simulation time 682494971 ps
CPU time 9.27 seconds
Started Aug 19 06:01:37 PM PDT 24
Finished Aug 19 06:01:46 PM PDT 24
Peak memory 226092 kb
Host smart-f4e20f20-594c-4909-ae43-f519cea842de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361392694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1361392694
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.518124535
Short name T318
Test name
Test status
Simulation time 61974537 ps
CPU time 2.62 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 217652 kb
Host smart-e79598d7-3d3c-4b10-b552-62c1b8ef0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518124535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.518124535
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3048820669
Short name T586
Test name
Test status
Simulation time 1189272244 ps
CPU time 27.95 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 250920 kb
Host smart-7f2580f7-98a6-40ab-8b68-cf620416a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048820669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3048820669
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3528745742
Short name T682
Test name
Test status
Simulation time 181232532 ps
CPU time 7.48 seconds
Started Aug 19 06:01:42 PM PDT 24
Finished Aug 19 06:01:50 PM PDT 24
Peak memory 246612 kb
Host smart-b63ff014-71ed-43cd-aa63-0483ffdda905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528745742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3528745742
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.898916812
Short name T820
Test name
Test status
Simulation time 2635906374 ps
CPU time 39.36 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:02:19 PM PDT 24
Peak memory 250940 kb
Host smart-b646e66f-7bf6-4d27-9233-6d5716a3dfd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898916812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.898916812
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1385025023
Short name T462
Test name
Test status
Simulation time 12519273 ps
CPU time 1.01 seconds
Started Aug 19 06:01:37 PM PDT 24
Finished Aug 19 06:01:38 PM PDT 24
Peak memory 211900 kb
Host smart-994f8a75-3368-4cf8-a3dc-63bf7f943468
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385025023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1385025023
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3310680558
Short name T72
Test name
Test status
Simulation time 65310786 ps
CPU time 0.88 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:01:39 PM PDT 24
Peak memory 208848 kb
Host smart-6e6cdc3f-3bc7-4298-8007-7ecb3761b7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310680558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3310680558
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2315592169
Short name T304
Test name
Test status
Simulation time 352577491 ps
CPU time 13.72 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:01:53 PM PDT 24
Peak memory 226120 kb
Host smart-b679caf3-5d96-4161-9501-b2bf0f514162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315592169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2315592169
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3807293313
Short name T561
Test name
Test status
Simulation time 70241667 ps
CPU time 3.15 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:01:44 PM PDT 24
Peak memory 218320 kb
Host smart-e9e1ef0b-f042-4fab-8b88-4c153b734314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807293313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3807293313
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.555783404
Short name T359
Test name
Test status
Simulation time 5460594686 ps
CPU time 11.59 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:57 PM PDT 24
Peak memory 226152 kb
Host smart-68cb5ef5-d71d-41d1-bbbf-ae3c96058702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555783404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.555783404
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3156802362
Short name T511
Test name
Test status
Simulation time 317584962 ps
CPU time 13.01 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:01:51 PM PDT 24
Peak memory 226064 kb
Host smart-ae3bed77-8a94-47b0-ac0f-81d826cb9d76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156802362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3156802362
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.433817004
Short name T528
Test name
Test status
Simulation time 2493496089 ps
CPU time 9.36 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 226152 kb
Host smart-4f2af69c-3e9a-478b-87b4-b39082e29ee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433817004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.433817004
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2546173964
Short name T513
Test name
Test status
Simulation time 733431945 ps
CPU time 9.38 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:01:48 PM PDT 24
Peak memory 225036 kb
Host smart-38f180cc-2e3b-4b27-b837-ba4cd1de5517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546173964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2546173964
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2393581670
Short name T574
Test name
Test status
Simulation time 1017712872 ps
CPU time 3.96 seconds
Started Aug 19 06:01:35 PM PDT 24
Finished Aug 19 06:01:39 PM PDT 24
Peak memory 217684 kb
Host smart-7bc001e6-ec10-47fc-a080-dffae3a7b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393581670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2393581670
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1393762137
Short name T303
Test name
Test status
Simulation time 734532227 ps
CPU time 27.02 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 245548 kb
Host smart-0dfe4b40-57de-4934-9558-77168bd6c3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393762137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1393762137
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.691984725
Short name T300
Test name
Test status
Simulation time 50369590 ps
CPU time 7.53 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:01:45 PM PDT 24
Peak memory 250964 kb
Host smart-7a21d6f8-6449-478e-a9bc-1242a57578b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691984725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.691984725
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3838210257
Short name T795
Test name
Test status
Simulation time 36100764408 ps
CPU time 144.75 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:04:02 PM PDT 24
Peak memory 283660 kb
Host smart-34124ca4-38cd-41c4-b6ee-a65a35a649a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838210257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3838210257
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.1892592027
Short name T147
Test name
Test status
Simulation time 1821263656 ps
CPU time 75.89 seconds
Started Aug 19 06:01:37 PM PDT 24
Finished Aug 19 06:02:53 PM PDT 24
Peak memory 275676 kb
Host smart-83c9bc97-c324-439a-8d67-451fe7eb8a18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1892592027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.1892592027
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1274079966
Short name T406
Test name
Test status
Simulation time 16093767 ps
CPU time 0.96 seconds
Started Aug 19 06:01:42 PM PDT 24
Finished Aug 19 06:01:43 PM PDT 24
Peak memory 211856 kb
Host smart-03170790-a6f8-48b4-a5cf-f3660698026b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274079966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1274079966
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1078197931
Short name T425
Test name
Test status
Simulation time 22091802 ps
CPU time 1.21 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:01:41 PM PDT 24
Peak memory 209056 kb
Host smart-ed1d3c15-4cd0-4f14-ae0c-7af97782d65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078197931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1078197931
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.4270320461
Short name T846
Test name
Test status
Simulation time 409199888 ps
CPU time 16.64 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 218260 kb
Host smart-bbdef707-d0d9-4982-8a86-0de88004a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270320461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.4270320461
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1707590151
Short name T736
Test name
Test status
Simulation time 199835362 ps
CPU time 2.2 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:01:41 PM PDT 24
Peak memory 217112 kb
Host smart-5e1e7ca9-ed92-4076-9c82-145e53e01291
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707590151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1707590151
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.535589083
Short name T625
Test name
Test status
Simulation time 123893870 ps
CPU time 4.18 seconds
Started Aug 19 06:01:41 PM PDT 24
Finished Aug 19 06:01:46 PM PDT 24
Peak memory 218292 kb
Host smart-400ed04c-3955-4ac9-aa8b-2d2629927cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535589083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.535589083
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.499175553
Short name T714
Test name
Test status
Simulation time 1254663866 ps
CPU time 17 seconds
Started Aug 19 06:01:37 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 226116 kb
Host smart-26bdf8ed-a325-407d-b66c-0924528d747f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499175553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.499175553
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1722053559
Short name T385
Test name
Test status
Simulation time 1496482684 ps
CPU time 13.77 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:01:59 PM PDT 24
Peak memory 226016 kb
Host smart-25b56cf7-72bf-4944-a24c-bb6ecfe9c28a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722053559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1722053559
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4088408258
Short name T293
Test name
Test status
Simulation time 310083957 ps
CPU time 7.13 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:01:53 PM PDT 24
Peak memory 218248 kb
Host smart-788f6c12-d9b2-4ff2-b428-292d25d6be1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088408258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4088408258
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2551555924
Short name T54
Test name
Test status
Simulation time 498012603 ps
CPU time 7.69 seconds
Started Aug 19 06:01:38 PM PDT 24
Finished Aug 19 06:01:46 PM PDT 24
Peak memory 224344 kb
Host smart-263981e1-6ee7-4e88-beb3-725ab69e1e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551555924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2551555924
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4117048968
Short name T363
Test name
Test status
Simulation time 169587131 ps
CPU time 1.59 seconds
Started Aug 19 06:01:36 PM PDT 24
Finished Aug 19 06:01:38 PM PDT 24
Peak memory 221908 kb
Host smart-add4f676-0ecd-4f98-bee5-7c6849ec227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117048968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4117048968
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.8046987
Short name T105
Test name
Test status
Simulation time 227194760 ps
CPU time 25.75 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 250920 kb
Host smart-5907c5f1-5032-4b8c-b7ca-5c366994894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8046987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.8046987
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3410123640
Short name T542
Test name
Test status
Simulation time 80866124 ps
CPU time 7.42 seconds
Started Aug 19 06:01:41 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 250796 kb
Host smart-ad909f69-71c5-42bc-9eb7-38eb7ae3c4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410123640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3410123640
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2196124248
Short name T569
Test name
Test status
Simulation time 9618639281 ps
CPU time 301.2 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:06:47 PM PDT 24
Peak memory 258388 kb
Host smart-156e6103-0f53-4790-9995-fbc9e84d7f03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196124248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2196124248
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.263355944
Short name T95
Test name
Test status
Simulation time 2812847889 ps
CPU time 76.82 seconds
Started Aug 19 06:01:41 PM PDT 24
Finished Aug 19 06:02:58 PM PDT 24
Peak memory 275824 kb
Host smart-443ec758-5c25-4d57-8c97-5441e82adf03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=263355944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.263355944
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4195031386
Short name T485
Test name
Test status
Simulation time 13460577 ps
CPU time 1.05 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 211932 kb
Host smart-cf2d10ae-d130-4d2b-95d9-b560e6f996a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195031386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4195031386
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3495090793
Short name T537
Test name
Test status
Simulation time 51619384 ps
CPU time 0.89 seconds
Started Aug 19 06:01:42 PM PDT 24
Finished Aug 19 06:01:43 PM PDT 24
Peak memory 208872 kb
Host smart-1a10f589-b3ba-41b0-940c-3303529d6f30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495090793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3495090793
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1551344117
Short name T301
Test name
Test status
Simulation time 916850577 ps
CPU time 17.33 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:02:03 PM PDT 24
Peak memory 218288 kb
Host smart-85fdee55-f060-4158-9f44-4194c3899ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551344117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1551344117
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.415417876
Short name T743
Test name
Test status
Simulation time 324110966 ps
CPU time 4.83 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:50 PM PDT 24
Peak memory 217308 kb
Host smart-3d70c144-7af9-4fad-92e9-ca62d24d9788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415417876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.415417876
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3237962356
Short name T861
Test name
Test status
Simulation time 308584073 ps
CPU time 3.41 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:01:43 PM PDT 24
Peak memory 218292 kb
Host smart-79a7e887-1654-4b86-b616-6ad31928e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237962356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3237962356
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2570117472
Short name T655
Test name
Test status
Simulation time 750702677 ps
CPU time 9.92 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 226064 kb
Host smart-480edaf3-279f-4c7e-9dd5-5f35616a571f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570117472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2570117472
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.263337617
Short name T622
Test name
Test status
Simulation time 553355195 ps
CPU time 12.15 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 225992 kb
Host smart-25784273-7bc3-4158-a560-cc7c82f75b97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263337617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.263337617
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2106976320
Short name T724
Test name
Test status
Simulation time 365995841 ps
CPU time 11.23 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:01:51 PM PDT 24
Peak memory 226140 kb
Host smart-ae86e00c-53dd-4fcd-89de-5614ca148e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106976320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2106976320
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4008943256
Short name T830
Test name
Test status
Simulation time 456311154 ps
CPU time 6.69 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:01:52 PM PDT 24
Peak memory 218324 kb
Host smart-db3e21e4-d1c5-4bfd-aca6-c0e6cd886f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008943256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4008943256
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.497903015
Short name T635
Test name
Test status
Simulation time 15313275 ps
CPU time 1.24 seconds
Started Aug 19 06:01:40 PM PDT 24
Finished Aug 19 06:01:41 PM PDT 24
Peak memory 217676 kb
Host smart-2b8a4155-b6f0-4dbb-9dfb-6e83754b35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497903015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.497903015
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.214805274
Short name T332
Test name
Test status
Simulation time 547874518 ps
CPU time 17.21 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:02:03 PM PDT 24
Peak memory 250884 kb
Host smart-502dfb26-9ae8-42b3-9c9a-afbdb7ed4867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214805274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.214805274
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.353236689
Short name T698
Test name
Test status
Simulation time 81179217 ps
CPU time 7.92 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 250936 kb
Host smart-983b93ac-9962-45c6-aa89-511ffed76879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353236689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.353236689
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.742592733
Short name T510
Test name
Test status
Simulation time 11087092299 ps
CPU time 26.94 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 258828 kb
Host smart-5ffd0f21-75b5-485b-b7f9-148ec83081eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742592733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.742592733
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3728861864
Short name T151
Test name
Test status
Simulation time 2898097788 ps
CPU time 109.2 seconds
Started Aug 19 06:01:43 PM PDT 24
Finished Aug 19 06:03:33 PM PDT 24
Peak memory 282284 kb
Host smart-a8f702b9-b6e5-4bda-af6e-281af29dd58b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3728861864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3728861864
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3267652080
Short name T488
Test name
Test status
Simulation time 23866789 ps
CPU time 1.02 seconds
Started Aug 19 06:01:42 PM PDT 24
Finished Aug 19 06:01:43 PM PDT 24
Peak memory 211928 kb
Host smart-f78b9e7c-7a17-46ea-8560-53b6c4964b09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267652080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3267652080
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3744721598
Short name T101
Test name
Test status
Simulation time 37682675 ps
CPU time 0.88 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:01:46 PM PDT 24
Peak memory 208700 kb
Host smart-3be9def6-8eae-4851-91f2-4b935e0fc7b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744721598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3744721598
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.933394404
Short name T775
Test name
Test status
Simulation time 184399591 ps
CPU time 9.87 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 226076 kb
Host smart-40fb2a1c-372f-453e-b9d4-40c781956324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933394404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.933394404
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3243322514
Short name T32
Test name
Test status
Simulation time 926773545 ps
CPU time 5.69 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:52 PM PDT 24
Peak memory 217036 kb
Host smart-3e3a04f2-5fa0-4491-9813-7640e04d8be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243322514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3243322514
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3507560275
Short name T633
Test name
Test status
Simulation time 146475300 ps
CPU time 3.2 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:50 PM PDT 24
Peak memory 222724 kb
Host smart-2d986414-ead4-4e39-bf40-e12d47d886ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507560275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3507560275
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.499569720
Short name T585
Test name
Test status
Simulation time 538299267 ps
CPU time 14.72 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:02:00 PM PDT 24
Peak memory 218984 kb
Host smart-2aedb721-c5e3-46bf-954f-f9169ea295c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499569720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.499569720
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1349947052
Short name T397
Test name
Test status
Simulation time 487645917 ps
CPU time 17.93 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:02:04 PM PDT 24
Peak memory 218224 kb
Host smart-a4ccb573-50c9-459c-a9e7-87086fa62f13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349947052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1349947052
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3560680461
Short name T613
Test name
Test status
Simulation time 4157987506 ps
CPU time 8.48 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 226212 kb
Host smart-df60cdb8-d8b8-4ee0-8530-97ce1c5b351d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560680461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3560680461
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4284622802
Short name T412
Test name
Test status
Simulation time 2922556782 ps
CPU time 10.39 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:01:59 PM PDT 24
Peak memory 226156 kb
Host smart-eb61a88e-fbe3-44e6-950e-2c56c002f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284622802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4284622802
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.4139235728
Short name T667
Test name
Test status
Simulation time 38675854 ps
CPU time 2.87 seconds
Started Aug 19 06:01:43 PM PDT 24
Finished Aug 19 06:01:45 PM PDT 24
Peak memory 214388 kb
Host smart-ee8f6377-3a4e-47b4-92b2-5815bde11f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139235728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4139235728
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1576150579
Short name T666
Test name
Test status
Simulation time 271616003 ps
CPU time 30.1 seconds
Started Aug 19 06:01:44 PM PDT 24
Finished Aug 19 06:02:14 PM PDT 24
Peak memory 250908 kb
Host smart-3708d348-eb96-4908-bf06-bf41841b5e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576150579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1576150579
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2687236509
Short name T689
Test name
Test status
Simulation time 214084615 ps
CPU time 7.91 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 250888 kb
Host smart-e49efe70-91fe-4c69-863b-213861cc234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687236509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2687236509
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2527811426
Short name T175
Test name
Test status
Simulation time 6500019391 ps
CPU time 77.79 seconds
Started Aug 19 06:01:50 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 267264 kb
Host smart-0c2ed878-1ec5-42bf-ad9e-2459fa7caaa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527811426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2527811426
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.602580787
Short name T114
Test name
Test status
Simulation time 2571217708 ps
CPU time 98.12 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:03:23 PM PDT 24
Peak memory 275796 kb
Host smart-23a12e43-595f-4413-9f30-ee442d1a84c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=602580787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.602580787
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1286110697
Short name T661
Test name
Test status
Simulation time 36674062 ps
CPU time 0.87 seconds
Started Aug 19 06:01:39 PM PDT 24
Finished Aug 19 06:01:40 PM PDT 24
Peak memory 211824 kb
Host smart-c85bd118-d82c-4897-8fff-19c1370d1aaa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286110697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1286110697
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4024691554
Short name T580
Test name
Test status
Simulation time 72855356 ps
CPU time 1.08 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 209040 kb
Host smart-c61cdf1c-75dd-49cb-8b27-c6745b6aa8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024691554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4024691554
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3290559493
Short name T41
Test name
Test status
Simulation time 1396240537 ps
CPU time 16.05 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:02:02 PM PDT 24
Peak memory 218300 kb
Host smart-78299b28-8135-4f3e-9192-2f0d5f53f68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290559493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3290559493
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2961127546
Short name T419
Test name
Test status
Simulation time 515415639 ps
CPU time 1.88 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:48 PM PDT 24
Peak memory 217012 kb
Host smart-c4cf89d9-9efb-42a5-a88d-eff4060e31f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961127546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2961127546
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2321734525
Short name T424
Test name
Test status
Simulation time 244520874 ps
CPU time 6.82 seconds
Started Aug 19 06:01:50 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 222936 kb
Host smart-7014670e-c211-44cc-a58a-964f0a48b90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321734525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2321734525
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1082680693
Short name T849
Test name
Test status
Simulation time 365012541 ps
CPU time 12.56 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 226100 kb
Host smart-3f7c3de3-a520-4c55-a134-10528c600724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082680693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1082680693
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.161687651
Short name T712
Test name
Test status
Simulation time 236468482 ps
CPU time 9.08 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 226120 kb
Host smart-5325f5c3-a628-4c43-b455-43bd0321ee55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161687651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.161687651
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.19535459
Short name T345
Test name
Test status
Simulation time 2003357098 ps
CPU time 11.14 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 226028 kb
Host smart-3f10671e-7614-47a7-b875-cdcc11424fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19535459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.19535459
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.190055730
Short name T606
Test name
Test status
Simulation time 348794471 ps
CPU time 3.22 seconds
Started Aug 19 06:01:50 PM PDT 24
Finished Aug 19 06:01:54 PM PDT 24
Peak memory 217684 kb
Host smart-f712c278-a3e3-4dc2-9397-fb85d08de96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190055730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.190055730
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2099364382
Short name T664
Test name
Test status
Simulation time 733668761 ps
CPU time 21.7 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 251012 kb
Host smart-38d1a65e-ad5f-4e17-953b-b19c8710fa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099364382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2099364382
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.656656247
Short name T713
Test name
Test status
Simulation time 141166947 ps
CPU time 2.94 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:01:51 PM PDT 24
Peak memory 226384 kb
Host smart-fc2ad463-f006-403b-9561-dce82e3f8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656656247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.656656247
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1715187794
Short name T73
Test name
Test status
Simulation time 7459479559 ps
CPU time 148.25 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 280228 kb
Host smart-8332412d-90b2-4a30-b21f-0da666aaea8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715187794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1715187794
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2672332022
Short name T646
Test name
Test status
Simulation time 13098141 ps
CPU time 0.87 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:01:48 PM PDT 24
Peak memory 211864 kb
Host smart-5b51ede1-31be-4355-9e4c-94218c29998e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672332022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2672332022
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.436813018
Short name T792
Test name
Test status
Simulation time 81542958 ps
CPU time 1.2 seconds
Started Aug 19 05:58:25 PM PDT 24
Finished Aug 19 05:58:26 PM PDT 24
Peak memory 209096 kb
Host smart-b1cfbd1c-011d-46b6-9e88-c0bb53c1a9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436813018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.436813018
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.476739758
Short name T231
Test name
Test status
Simulation time 509420579 ps
CPU time 13.42 seconds
Started Aug 19 05:58:25 PM PDT 24
Finished Aug 19 05:58:39 PM PDT 24
Peak memory 226096 kb
Host smart-92e6f5c7-4593-462a-964b-4c5236126903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476739758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.476739758
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3383403300
Short name T822
Test name
Test status
Simulation time 966586309 ps
CPU time 5.67 seconds
Started Aug 19 05:58:25 PM PDT 24
Finished Aug 19 05:58:31 PM PDT 24
Peak memory 217376 kb
Host smart-38aa2467-8e20-45e4-9ada-a14e600e6fc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383403300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3383403300
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.4107906981
Short name T29
Test name
Test status
Simulation time 2852668610 ps
CPU time 41.89 seconds
Started Aug 19 05:58:24 PM PDT 24
Finished Aug 19 05:59:06 PM PDT 24
Peak memory 219016 kb
Host smart-4c6d6206-716c-48b9-8773-d49eb4174e6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107906981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.4107906981
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.242454751
Short name T66
Test name
Test status
Simulation time 361331112 ps
CPU time 4.11 seconds
Started Aug 19 05:58:24 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 217720 kb
Host smart-d7159d0b-6fd4-43a4-baf8-086a69d34131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242454751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.242454751
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3407654853
Short name T776
Test name
Test status
Simulation time 1209077197 ps
CPU time 5.46 seconds
Started Aug 19 05:58:26 PM PDT 24
Finished Aug 19 05:58:31 PM PDT 24
Peak memory 218312 kb
Host smart-7a1ba2b4-633b-4107-bc4f-fb6fe0647aa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407654853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3407654853
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2634130772
Short name T84
Test name
Test status
Simulation time 6791974267 ps
CPU time 19.19 seconds
Started Aug 19 05:58:26 PM PDT 24
Finished Aug 19 05:58:45 PM PDT 24
Peak memory 217644 kb
Host smart-58044057-dd9e-4c5d-8eed-6b6732131a4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634130772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2634130772
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1317073016
Short name T602
Test name
Test status
Simulation time 284713918 ps
CPU time 4.87 seconds
Started Aug 19 05:58:24 PM PDT 24
Finished Aug 19 05:58:29 PM PDT 24
Peak memory 217604 kb
Host smart-4e9449cf-24c7-43d7-a87d-239d934681e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317073016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1317073016
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1846492891
Short name T671
Test name
Test status
Simulation time 3334819258 ps
CPU time 37.11 seconds
Started Aug 19 05:58:25 PM PDT 24
Finished Aug 19 05:59:02 PM PDT 24
Peak memory 276372 kb
Host smart-7d76a821-43b8-4632-9e4c-5988b5be2795
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846492891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1846492891
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.183811571
Short name T833
Test name
Test status
Simulation time 3291790392 ps
CPU time 26.21 seconds
Started Aug 19 05:58:25 PM PDT 24
Finished Aug 19 05:58:51 PM PDT 24
Peak memory 248572 kb
Host smart-d1458697-65cd-47cf-a02c-21866cea8f53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183811571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.183811571
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.4041466479
Short name T355
Test name
Test status
Simulation time 49016374 ps
CPU time 2.91 seconds
Started Aug 19 05:58:22 PM PDT 24
Finished Aug 19 05:58:25 PM PDT 24
Peak memory 222516 kb
Host smart-ed162221-153d-4c96-bd68-7f896de103f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041466479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4041466479
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.332612195
Short name T480
Test name
Test status
Simulation time 2321054502 ps
CPU time 9.51 seconds
Started Aug 19 05:58:23 PM PDT 24
Finished Aug 19 05:58:33 PM PDT 24
Peak memory 217780 kb
Host smart-e55dac9f-e0bc-43df-9361-8fbc7ad89ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332612195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.332612195
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2561806809
Short name T715
Test name
Test status
Simulation time 674399427 ps
CPU time 9.32 seconds
Started Aug 19 05:58:22 PM PDT 24
Finished Aug 19 05:58:31 PM PDT 24
Peak memory 218284 kb
Host smart-6e722b3f-2956-4941-a6f7-ea03ec65190b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561806809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2561806809
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1456554531
Short name T399
Test name
Test status
Simulation time 863160343 ps
CPU time 12.6 seconds
Started Aug 19 05:58:26 PM PDT 24
Finished Aug 19 05:58:38 PM PDT 24
Peak memory 226060 kb
Host smart-0b246c4f-8bc7-4b6c-8dcb-d0770db94a6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456554531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1456554531
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1739850311
Short name T630
Test name
Test status
Simulation time 247436413 ps
CPU time 9.52 seconds
Started Aug 19 05:58:24 PM PDT 24
Finished Aug 19 05:58:33 PM PDT 24
Peak memory 226016 kb
Host smart-55b144cc-6729-42ac-8ff2-eb8406d54b5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739850311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
739850311
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.866745073
Short name T362
Test name
Test status
Simulation time 756039809 ps
CPU time 6.04 seconds
Started Aug 19 05:58:23 PM PDT 24
Finished Aug 19 05:58:29 PM PDT 24
Peak memory 218348 kb
Host smart-43dc19a4-c6fc-4679-8c3e-dfda64fcbd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866745073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.866745073
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2959363281
Short name T869
Test name
Test status
Simulation time 109304016 ps
CPU time 3.22 seconds
Started Aug 19 05:58:14 PM PDT 24
Finished Aug 19 05:58:17 PM PDT 24
Peak memory 217632 kb
Host smart-87a7b384-da64-40f0-a4ff-14c86642772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959363281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2959363281
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2523168178
Short name T346
Test name
Test status
Simulation time 937684405 ps
CPU time 24.55 seconds
Started Aug 19 05:58:24 PM PDT 24
Finished Aug 19 05:58:49 PM PDT 24
Peak memory 250868 kb
Host smart-390b3b2c-bb91-4418-b599-4413a4972082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523168178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2523168178
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.580285449
Short name T492
Test name
Test status
Simulation time 229945753 ps
CPU time 6.02 seconds
Started Aug 19 05:58:22 PM PDT 24
Finished Aug 19 05:58:28 PM PDT 24
Peak memory 250312 kb
Host smart-32cf7340-ebc1-4851-b9ea-46011d760ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580285449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.580285449
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1273201203
Short name T65
Test name
Test status
Simulation time 2962664309 ps
CPU time 21.99 seconds
Started Aug 19 05:58:22 PM PDT 24
Finished Aug 19 05:58:44 PM PDT 24
Peak memory 225984 kb
Host smart-22f86aff-d802-497d-83b8-8c3fe4585669
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273201203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1273201203
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2807443192
Short name T164
Test name
Test status
Simulation time 7293557006 ps
CPU time 97.83 seconds
Started Aug 19 05:58:24 PM PDT 24
Finished Aug 19 06:00:02 PM PDT 24
Peak memory 273260 kb
Host smart-dfccfac7-7a2e-462a-b365-55791bb84bb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2807443192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2807443192
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3873248759
Short name T450
Test name
Test status
Simulation time 33840355 ps
CPU time 0.88 seconds
Started Aug 19 05:58:25 PM PDT 24
Finished Aug 19 05:58:26 PM PDT 24
Peak memory 212008 kb
Host smart-d7edc50a-46d8-48b8-a4e3-e926de9fcdde
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873248759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3873248759
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1905985752
Short name T791
Test name
Test status
Simulation time 38933580 ps
CPU time 1.18 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:58:45 PM PDT 24
Peak memory 209000 kb
Host smart-7b93313a-2a23-448c-917d-a92252243bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905985752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1905985752
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2775336318
Short name T161
Test name
Test status
Simulation time 13367227 ps
CPU time 0.81 seconds
Started Aug 19 05:58:32 PM PDT 24
Finished Aug 19 05:58:33 PM PDT 24
Peak memory 208500 kb
Host smart-53d4c209-97ba-4d4c-a967-6254e4505719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775336318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2775336318
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1737324241
Short name T453
Test name
Test status
Simulation time 1151754487 ps
CPU time 11.9 seconds
Started Aug 19 05:58:33 PM PDT 24
Finished Aug 19 05:58:45 PM PDT 24
Peak memory 218320 kb
Host smart-2e536b30-6e1d-4505-a2e2-d5a31f82d31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737324241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1737324241
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1778418762
Short name T758
Test name
Test status
Simulation time 4624245406 ps
CPU time 16.85 seconds
Started Aug 19 05:58:30 PM PDT 24
Finished Aug 19 05:58:47 PM PDT 24
Peak memory 217640 kb
Host smart-be69925f-23c6-40b4-b685-a54f9a53f233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778418762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1778418762
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1308526932
Short name T458
Test name
Test status
Simulation time 1491353814 ps
CPU time 27.66 seconds
Started Aug 19 05:58:33 PM PDT 24
Finished Aug 19 05:59:00 PM PDT 24
Peak memory 218304 kb
Host smart-d1ac6315-a84c-4e27-8dd0-f3b211b21133
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308526932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1308526932
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1258353574
Short name T173
Test name
Test status
Simulation time 286348281 ps
CPU time 3.77 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:58:48 PM PDT 24
Peak memory 217736 kb
Host smart-fe6be41e-9c23-4198-8c8a-40e8fadef20f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258353574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
258353574
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1989222044
Short name T703
Test name
Test status
Simulation time 189394994 ps
CPU time 4.11 seconds
Started Aug 19 05:58:32 PM PDT 24
Finished Aug 19 05:58:36 PM PDT 24
Peak memory 223012 kb
Host smart-fe8c9ce9-ac6f-4678-9e9d-16debeaa5b03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989222044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1989222044
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1409823781
Short name T549
Test name
Test status
Simulation time 17016792116 ps
CPU time 39.92 seconds
Started Aug 19 05:58:43 PM PDT 24
Finished Aug 19 05:59:23 PM PDT 24
Peak memory 217652 kb
Host smart-17aac178-99bd-4deb-9f18-a20e3cd2e0f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409823781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1409823781
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2391214527
Short name T857
Test name
Test status
Simulation time 110423224 ps
CPU time 2.07 seconds
Started Aug 19 05:58:33 PM PDT 24
Finished Aug 19 05:58:35 PM PDT 24
Peak memory 217620 kb
Host smart-ee68e9c7-3422-41e0-9f83-e18948b3171e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391214527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2391214527
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.558369174
Short name T230
Test name
Test status
Simulation time 4925094330 ps
CPU time 44.62 seconds
Started Aug 19 05:58:31 PM PDT 24
Finished Aug 19 05:59:16 PM PDT 24
Peak memory 253540 kb
Host smart-c84d06a8-9cd7-4048-809e-e9cb1449bfa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558369174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.558369174
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1570536939
Short name T710
Test name
Test status
Simulation time 2274078938 ps
CPU time 17.07 seconds
Started Aug 19 05:58:32 PM PDT 24
Finished Aug 19 05:58:49 PM PDT 24
Peak memory 222260 kb
Host smart-b2ee4ede-b1ce-4b5e-9fd9-5597933da39d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570536939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1570536939
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.119721995
Short name T760
Test name
Test status
Simulation time 405059431 ps
CPU time 3.57 seconds
Started Aug 19 05:58:31 PM PDT 24
Finished Aug 19 05:58:35 PM PDT 24
Peak memory 218348 kb
Host smart-3dc463ff-7966-4b62-89eb-7a477ce0800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119721995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.119721995
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1301164832
Short name T70
Test name
Test status
Simulation time 2676496796 ps
CPU time 19.44 seconds
Started Aug 19 05:58:29 PM PDT 24
Finished Aug 19 05:58:48 PM PDT 24
Peak memory 215308 kb
Host smart-71b65dde-5c35-4827-8df6-189429213abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301164832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1301164832
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.463364785
Short name T553
Test name
Test status
Simulation time 409580935 ps
CPU time 9.91 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:58:54 PM PDT 24
Peak memory 226116 kb
Host smart-8d2f3f48-f442-42da-8357-69e70a6f336a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463364785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.463364785
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2973384414
Short name T11
Test name
Test status
Simulation time 598908255 ps
CPU time 22.05 seconds
Started Aug 19 05:58:43 PM PDT 24
Finished Aug 19 05:59:05 PM PDT 24
Peak memory 225988 kb
Host smart-45686b75-40d6-46d5-a140-b16d5a6854ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973384414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2973384414
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2344032497
Short name T226
Test name
Test status
Simulation time 244859764 ps
CPU time 7.25 seconds
Started Aug 19 05:58:43 PM PDT 24
Finished Aug 19 05:58:50 PM PDT 24
Peak memory 218244 kb
Host smart-7865e25b-5abe-47d1-991d-ee018aeffcff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344032497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
344032497
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2640147765
Short name T677
Test name
Test status
Simulation time 434736657 ps
CPU time 10.24 seconds
Started Aug 19 05:58:33 PM PDT 24
Finished Aug 19 05:58:43 PM PDT 24
Peak memory 225788 kb
Host smart-9c531a9c-5251-4c66-842d-5fe8c97c61b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640147765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2640147765
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.728218250
Short name T283
Test name
Test status
Simulation time 172682559 ps
CPU time 3.09 seconds
Started Aug 19 05:58:32 PM PDT 24
Finished Aug 19 05:58:35 PM PDT 24
Peak memory 217740 kb
Host smart-d51ae247-126f-4649-95d9-4ad9de61fc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728218250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.728218250
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2104183472
Short name T306
Test name
Test status
Simulation time 942401370 ps
CPU time 27.58 seconds
Started Aug 19 05:58:31 PM PDT 24
Finished Aug 19 05:58:59 PM PDT 24
Peak memory 250856 kb
Host smart-5cf6eec1-0014-40ad-b6fe-97be97ab592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104183472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2104183472
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3475503940
Short name T651
Test name
Test status
Simulation time 47804109 ps
CPU time 6.92 seconds
Started Aug 19 05:58:33 PM PDT 24
Finished Aug 19 05:58:40 PM PDT 24
Peak memory 242772 kb
Host smart-411be6bb-6ed8-4cc6-97a2-80b8d78a92df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475503940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3475503940
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1499403176
Short name T365
Test name
Test status
Simulation time 43274111855 ps
CPU time 295.89 seconds
Started Aug 19 05:58:43 PM PDT 24
Finished Aug 19 06:03:39 PM PDT 24
Peak memory 226168 kb
Host smart-ac4c4901-90a9-491e-b856-73c674fa3bb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499403176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1499403176
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.231025031
Short name T256
Test name
Test status
Simulation time 13735993 ps
CPU time 1.09 seconds
Started Aug 19 05:58:31 PM PDT 24
Finished Aug 19 05:58:32 PM PDT 24
Peak memory 211868 kb
Host smart-43071060-cec6-48f4-9783-c92a79064738
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231025031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.231025031
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.981959611
Short name T853
Test name
Test status
Simulation time 16313808 ps
CPU time 1.08 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:01 PM PDT 24
Peak memory 209012 kb
Host smart-9b73f9ae-ade5-4495-aa35-e94dacf1acf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981959611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.981959611
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4107276249
Short name T572
Test name
Test status
Simulation time 12946403 ps
CPU time 0.82 seconds
Started Aug 19 05:58:42 PM PDT 24
Finished Aug 19 05:58:43 PM PDT 24
Peak memory 208516 kb
Host smart-ed33c8ab-354e-4468-85e2-8470fce9bf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107276249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4107276249
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.390879995
Short name T502
Test name
Test status
Simulation time 956207362 ps
CPU time 8.54 seconds
Started Aug 19 05:58:42 PM PDT 24
Finished Aug 19 05:58:50 PM PDT 24
Peak memory 218296 kb
Host smart-57cf82f1-35c0-4d58-a510-43a493051832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390879995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.390879995
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2160546997
Short name T639
Test name
Test status
Simulation time 800013398 ps
CPU time 5.49 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:58:56 PM PDT 24
Peak memory 217452 kb
Host smart-64d9d6cf-d4ca-4de5-be29-3f20b188eb90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160546997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2160546997
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2556826538
Short name T336
Test name
Test status
Simulation time 9574980654 ps
CPU time 72.59 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:59:56 PM PDT 24
Peak memory 218964 kb
Host smart-1a085334-f64e-44ac-b93e-4a4c61d08118
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556826538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2556826538
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.904605379
Short name T632
Test name
Test status
Simulation time 420524651 ps
CPU time 10.82 seconds
Started Aug 19 05:58:53 PM PDT 24
Finished Aug 19 05:59:04 PM PDT 24
Peak memory 217440 kb
Host smart-1f651211-82b5-4a82-a8b5-96425ecc6d36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904605379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.904605379
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3816193398
Short name T432
Test name
Test status
Simulation time 1931881285 ps
CPU time 7.35 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:58:51 PM PDT 24
Peak memory 218240 kb
Host smart-d07f2582-cfd5-4129-92d1-5bfb5f215677
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816193398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3816193398
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.937041117
Short name T763
Test name
Test status
Simulation time 4864447932 ps
CPU time 19.72 seconds
Started Aug 19 05:58:52 PM PDT 24
Finished Aug 19 05:59:12 PM PDT 24
Peak memory 217648 kb
Host smart-ce236572-83fb-40ca-9cc9-2ab6b418d659
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937041117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.937041117
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3546646375
Short name T69
Test name
Test status
Simulation time 204974255 ps
CPU time 3.97 seconds
Started Aug 19 05:58:45 PM PDT 24
Finished Aug 19 05:58:49 PM PDT 24
Peak memory 217604 kb
Host smart-824c52ae-1568-41fa-bb4d-7ebbb1ba716e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546646375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3546646375
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1886978389
Short name T564
Test name
Test status
Simulation time 745163796 ps
CPU time 26.57 seconds
Started Aug 19 05:58:45 PM PDT 24
Finished Aug 19 05:59:12 PM PDT 24
Peak memory 250868 kb
Host smart-db870e6d-9a40-40d2-af90-ae78c437deff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886978389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1886978389
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3517561938
Short name T319
Test name
Test status
Simulation time 308556978 ps
CPU time 7.98 seconds
Started Aug 19 05:58:43 PM PDT 24
Finished Aug 19 05:58:51 PM PDT 24
Peak memory 246400 kb
Host smart-94f742d5-c6ac-495a-9fa8-5f7c2c7abe64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517561938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3517561938
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.202111589
Short name T239
Test name
Test status
Simulation time 305559086 ps
CPU time 2.75 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:58:46 PM PDT 24
Peak memory 218308 kb
Host smart-0b288a10-76f5-4d4a-aeaa-ad2f26d8f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202111589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.202111589
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.873749894
Short name T78
Test name
Test status
Simulation time 841027461 ps
CPU time 5.98 seconds
Started Aug 19 05:58:46 PM PDT 24
Finished Aug 19 05:58:52 PM PDT 24
Peak memory 217656 kb
Host smart-fa4dc7b9-a0f7-4f54-bf51-b555e84e1ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873749894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.873749894
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2457553256
Short name T700
Test name
Test status
Simulation time 399113712 ps
CPU time 16.22 seconds
Started Aug 19 05:58:52 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 226084 kb
Host smart-d3e615bd-cb37-4ae8-b218-53ce139b292a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457553256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2457553256
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.680538988
Short name T611
Test name
Test status
Simulation time 680893367 ps
CPU time 10.57 seconds
Started Aug 19 05:58:54 PM PDT 24
Finished Aug 19 05:59:05 PM PDT 24
Peak memory 226048 kb
Host smart-07b89ed1-d6e6-4980-8a75-05553db53b97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680538988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.680538988
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2038496894
Short name T373
Test name
Test status
Simulation time 846210730 ps
CPU time 6.94 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:58:59 PM PDT 24
Peak memory 218208 kb
Host smart-ad4f0786-c8a3-4fa8-86c5-6bd71995cca4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038496894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
038496894
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2419736315
Short name T295
Test name
Test status
Simulation time 5861086790 ps
CPU time 14.16 seconds
Started Aug 19 05:58:41 PM PDT 24
Finished Aug 19 05:58:55 PM PDT 24
Peak memory 226156 kb
Host smart-db15cc62-4630-400e-8677-3d542c58a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419736315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2419736315
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2623263345
Short name T708
Test name
Test status
Simulation time 24822584 ps
CPU time 1.77 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:58:46 PM PDT 24
Peak memory 217648 kb
Host smart-1ed8a28d-505d-48a9-9f07-c6d007c4bcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623263345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2623263345
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2551659404
Short name T263
Test name
Test status
Simulation time 1634999150 ps
CPU time 32.43 seconds
Started Aug 19 05:58:45 PM PDT 24
Finished Aug 19 05:59:18 PM PDT 24
Peak memory 246144 kb
Host smart-57e78753-504b-4c6b-a700-a39ac6a2821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551659404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2551659404
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.441565178
Short name T750
Test name
Test status
Simulation time 230580041 ps
CPU time 5.68 seconds
Started Aug 19 05:58:42 PM PDT 24
Finished Aug 19 05:58:48 PM PDT 24
Peak memory 246672 kb
Host smart-49d50fe6-3867-4a30-a92a-d44a912fff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441565178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.441565178
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3178265881
Short name T158
Test name
Test status
Simulation time 29242402 ps
CPU time 1.09 seconds
Started Aug 19 05:58:44 PM PDT 24
Finished Aug 19 05:58:45 PM PDT 24
Peak memory 212956 kb
Host smart-88bd878e-199a-4238-89c8-1fd9d995008d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178265881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3178265881
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2462218895
Short name T552
Test name
Test status
Simulation time 25537234 ps
CPU time 1.28 seconds
Started Aug 19 05:59:03 PM PDT 24
Finished Aug 19 05:59:04 PM PDT 24
Peak memory 209040 kb
Host smart-3010da77-a24d-4219-be28-961b1057fbb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462218895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2462218895
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1862534414
Short name T200
Test name
Test status
Simulation time 72946289 ps
CPU time 0.89 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 05:59:02 PM PDT 24
Peak memory 208560 kb
Host smart-517f92d7-3e4e-44e6-bb8d-7a0ffa6b3d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862534414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1862534414
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.567222315
Short name T251
Test name
Test status
Simulation time 1590480475 ps
CPU time 13.45 seconds
Started Aug 19 05:58:56 PM PDT 24
Finished Aug 19 05:59:09 PM PDT 24
Peak memory 226148 kb
Host smart-93d04af9-eccd-4266-a66b-a73042844638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567222315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.567222315
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3046289627
Short name T235
Test name
Test status
Simulation time 117498811 ps
CPU time 2.26 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:58:54 PM PDT 24
Peak memory 217016 kb
Host smart-79b6e434-9e94-4aca-818b-7c303e917eaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046289627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3046289627
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.317760213
Short name T310
Test name
Test status
Simulation time 5266082938 ps
CPU time 22.1 seconds
Started Aug 19 05:58:56 PM PDT 24
Finished Aug 19 05:59:18 PM PDT 24
Peak memory 218352 kb
Host smart-2827a651-d518-491e-a1ab-d7a28370c4ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317760213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.317760213
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2907343593
Short name T234
Test name
Test status
Simulation time 1065300543 ps
CPU time 4.12 seconds
Started Aug 19 05:58:53 PM PDT 24
Finished Aug 19 05:58:57 PM PDT 24
Peak memory 217724 kb
Host smart-24250588-4e58-4a94-8d68-ecd63838813a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907343593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
907343593
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.228989551
Short name T627
Test name
Test status
Simulation time 1490798062 ps
CPU time 9.44 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:59:01 PM PDT 24
Peak memory 223136 kb
Host smart-5b395da3-7737-4b6d-a4d7-8cde817fb49e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228989551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.228989551
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3667212463
Short name T778
Test name
Test status
Simulation time 2636278829 ps
CPU time 19.62 seconds
Started Aug 19 05:58:55 PM PDT 24
Finished Aug 19 05:59:15 PM PDT 24
Peak memory 217644 kb
Host smart-9de0608c-bf4a-4716-8bed-4eead1ec933a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667212463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3667212463
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1490492646
Short name T493
Test name
Test status
Simulation time 258296666 ps
CPU time 4.55 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:58:55 PM PDT 24
Peak memory 217572 kb
Host smart-fa3870b7-9fbe-4df9-92bb-f7f4e526b950
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490492646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1490492646
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.124677883
Short name T738
Test name
Test status
Simulation time 3333463458 ps
CPU time 99.24 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 06:00:30 PM PDT 24
Peak memory 282948 kb
Host smart-9b04c117-ef89-4f10-bfa0-cc4b79f32df0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124677883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.124677883
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.508941139
Short name T772
Test name
Test status
Simulation time 3094572890 ps
CPU time 27.18 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 05:59:28 PM PDT 24
Peak memory 248504 kb
Host smart-8c0cfc2e-a826-48bb-81f3-0484446c4d49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508941139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.508941139
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4179255098
Short name T723
Test name
Test status
Simulation time 53878322 ps
CPU time 3.21 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 05:59:04 PM PDT 24
Peak memory 222348 kb
Host smart-704a0c3d-a5a8-4afe-bd23-65f4b462c551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179255098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4179255098
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1396770952
Short name T794
Test name
Test status
Simulation time 201588190 ps
CPU time 8.11 seconds
Started Aug 19 05:58:54 PM PDT 24
Finished Aug 19 05:59:02 PM PDT 24
Peak memory 217704 kb
Host smart-ee42e05b-4186-4dbc-9105-a8432cea3ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396770952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1396770952
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1666011810
Short name T463
Test name
Test status
Simulation time 824955131 ps
CPU time 8.21 seconds
Started Aug 19 05:58:52 PM PDT 24
Finished Aug 19 05:59:00 PM PDT 24
Peak memory 226076 kb
Host smart-1831d5a8-7430-4d8b-8a02-208e5954f96b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666011810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1666011810
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2952919356
Short name T568
Test name
Test status
Simulation time 310453551 ps
CPU time 13.67 seconds
Started Aug 19 05:58:54 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 226024 kb
Host smart-19174e93-e32d-4060-b183-b71b10498541
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952919356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2952919356
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2954233869
Short name T476
Test name
Test status
Simulation time 1011645902 ps
CPU time 9.71 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:59:01 PM PDT 24
Peak memory 217008 kb
Host smart-5ce42e3f-da8b-42cc-a345-fc6763c1f241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954233869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
954233869
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.470529610
Short name T790
Test name
Test status
Simulation time 440596650 ps
CPU time 14.96 seconds
Started Aug 19 05:58:50 PM PDT 24
Finished Aug 19 05:59:05 PM PDT 24
Peak memory 218396 kb
Host smart-6d5557b5-38c7-4ed6-94b4-1149e799bd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470529610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.470529610
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.25836660
Short name T524
Test name
Test status
Simulation time 17202892 ps
CPU time 0.96 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:58:52 PM PDT 24
Peak memory 212276 kb
Host smart-da9eb754-1d1a-457b-8653-41f924463403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25836660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.25836660
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2198513259
Short name T370
Test name
Test status
Simulation time 197625633 ps
CPU time 19.31 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 05:59:11 PM PDT 24
Peak memory 250976 kb
Host smart-2ba385d8-d6d1-4711-81cc-69f99f6559c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198513259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2198513259
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3098061850
Short name T825
Test name
Test status
Simulation time 239659600 ps
CPU time 9.07 seconds
Started Aug 19 05:58:53 PM PDT 24
Finished Aug 19 05:59:02 PM PDT 24
Peak memory 250944 kb
Host smart-24a4a0c9-206d-40f0-b22e-f411234320e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098061850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3098061850
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3171686775
Short name T538
Test name
Test status
Simulation time 5752598289 ps
CPU time 216.98 seconds
Started Aug 19 05:58:53 PM PDT 24
Finished Aug 19 06:02:30 PM PDT 24
Peak memory 283764 kb
Host smart-da1d6555-b2f7-45f3-9096-55920c3484ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171686775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3171686775
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.331202636
Short name T146
Test name
Test status
Simulation time 8379481844 ps
CPU time 79.84 seconds
Started Aug 19 05:58:51 PM PDT 24
Finished Aug 19 06:00:11 PM PDT 24
Peak memory 259736 kb
Host smart-e9ee3c20-76ac-4e9b-beb7-dfd040d412a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=331202636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.331202636
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3183078241
Short name T168
Test name
Test status
Simulation time 12616652 ps
CPU time 0.87 seconds
Started Aug 19 05:58:48 PM PDT 24
Finished Aug 19 05:58:49 PM PDT 24
Peak memory 211904 kb
Host smart-de81f6ac-9834-4e66-a44e-9ef98edee09f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183078241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3183078241
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.642079953
Short name T497
Test name
Test status
Simulation time 17498356 ps
CPU time 1.06 seconds
Started Aug 19 05:58:59 PM PDT 24
Finished Aug 19 05:59:01 PM PDT 24
Peak memory 208944 kb
Host smart-0671a089-bb08-4228-9fda-f1cf0066a4fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642079953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.642079953
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3976606105
Short name T395
Test name
Test status
Simulation time 221393279 ps
CPU time 10.19 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:11 PM PDT 24
Peak memory 226116 kb
Host smart-b16f33b1-ee00-4319-9a7e-635ee91cad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976606105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3976606105
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1380078170
Short name T394
Test name
Test status
Simulation time 1081533713 ps
CPU time 7.35 seconds
Started Aug 19 05:59:10 PM PDT 24
Finished Aug 19 05:59:18 PM PDT 24
Peak memory 217328 kb
Host smart-10855f16-af3a-4085-add5-12443977beb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380078170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1380078170
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1317910314
Short name T377
Test name
Test status
Simulation time 1049270900 ps
CPU time 26.34 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:26 PM PDT 24
Peak memory 218268 kb
Host smart-722e0977-5a88-43eb-9d1e-459b010a1b23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317910314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1317910314
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3204301971
Short name T545
Test name
Test status
Simulation time 385454125 ps
CPU time 4.73 seconds
Started Aug 19 05:59:03 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 217492 kb
Host smart-468d88fb-da40-4e80-a6ff-31290eb5ea2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204301971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
204301971
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3869091177
Short name T214
Test name
Test status
Simulation time 177448406 ps
CPU time 3.89 seconds
Started Aug 19 05:59:03 PM PDT 24
Finished Aug 19 05:59:07 PM PDT 24
Peak memory 218216 kb
Host smart-4dbd6b29-72d6-42d1-892b-49dd2fdf01d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869091177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3869091177
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1111836196
Short name T287
Test name
Test status
Simulation time 1068939446 ps
CPU time 9.75 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:21 PM PDT 24
Peak memory 217476 kb
Host smart-70010aa0-1a21-46b6-b6ec-6e6e4589702b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111836196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1111836196
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2642797601
Short name T273
Test name
Test status
Simulation time 628068806 ps
CPU time 5.24 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 05:59:06 PM PDT 24
Peak memory 217608 kb
Host smart-7f9af4f5-11b4-4b4b-9c41-e7e2519a2cbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642797601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2642797601
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3143935024
Short name T581
Test name
Test status
Simulation time 3177486721 ps
CPU time 66.33 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 06:00:08 PM PDT 24
Peak memory 275492 kb
Host smart-4f0ac3de-4d8d-41a9-bcc5-b3e720e366cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143935024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3143935024
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.425847408
Short name T211
Test name
Test status
Simulation time 4064375797 ps
CPU time 15.19 seconds
Started Aug 19 05:59:02 PM PDT 24
Finished Aug 19 05:59:17 PM PDT 24
Peak memory 249472 kb
Host smart-e87fb1bf-d304-42ce-815a-edab74432dd4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425847408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.425847408
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2420635724
Short name T393
Test name
Test status
Simulation time 59196527 ps
CPU time 2.73 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 05:59:04 PM PDT 24
Peak memory 222476 kb
Host smart-55e417c9-9df6-41b6-8985-11363999547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420635724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2420635724
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.394778244
Short name T706
Test name
Test status
Simulation time 1039697202 ps
CPU time 10.06 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:10 PM PDT 24
Peak memory 214020 kb
Host smart-a113bcde-7708-42b9-a4f4-2aa94cc18f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394778244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.394778244
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.573552282
Short name T382
Test name
Test status
Simulation time 1653349047 ps
CPU time 17.12 seconds
Started Aug 19 05:59:14 PM PDT 24
Finished Aug 19 05:59:31 PM PDT 24
Peak memory 219968 kb
Host smart-0d292cbd-6000-48eb-a88f-f5055b18acdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573552282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.573552282
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3458763970
Short name T517
Test name
Test status
Simulation time 709146479 ps
CPU time 9.16 seconds
Started Aug 19 05:58:59 PM PDT 24
Finished Aug 19 05:59:08 PM PDT 24
Peak memory 226032 kb
Host smart-610589a9-4845-443f-9f24-5b474ce6aa4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458763970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3458763970
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2193918026
Short name T721
Test name
Test status
Simulation time 933845650 ps
CPU time 7.22 seconds
Started Aug 19 05:59:11 PM PDT 24
Finished Aug 19 05:59:18 PM PDT 24
Peak memory 218300 kb
Host smart-d3e782d8-17d3-4b35-81ff-317ab6a93197
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193918026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
193918026
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3284381712
Short name T824
Test name
Test status
Simulation time 886297611 ps
CPU time 8.88 seconds
Started Aug 19 05:59:02 PM PDT 24
Finished Aug 19 05:59:11 PM PDT 24
Peak memory 226080 kb
Host smart-0f2367c0-b615-489a-9cd3-efd47094a6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284381712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3284381712
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.4211743434
Short name T444
Test name
Test status
Simulation time 144369675 ps
CPU time 2.15 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:02 PM PDT 24
Peak memory 213944 kb
Host smart-0e1f3f19-945c-474d-ab6a-b3d26c816efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211743434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.4211743434
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1076832110
Short name T378
Test name
Test status
Simulation time 1651678650 ps
CPU time 22.23 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:22 PM PDT 24
Peak memory 250888 kb
Host smart-7ab825ff-cbfe-4dbc-9c83-69be1584ebec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076832110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1076832110
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3257587256
Short name T573
Test name
Test status
Simulation time 882288813 ps
CPU time 7 seconds
Started Aug 19 05:59:00 PM PDT 24
Finished Aug 19 05:59:07 PM PDT 24
Peak memory 247096 kb
Host smart-91fff53e-3258-4561-b7de-f3e01f4f554c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257587256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3257587256
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.751877652
Short name T433
Test name
Test status
Simulation time 18065180347 ps
CPU time 300.84 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 314060 kb
Host smart-da58798b-ec4f-4b13-8b12-3c69977ad83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751877652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.751877652
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.45375165
Short name T726
Test name
Test status
Simulation time 29960480 ps
CPU time 0.83 seconds
Started Aug 19 05:59:01 PM PDT 24
Finished Aug 19 05:59:02 PM PDT 24
Peak memory 211968 kb
Host smart-3526b786-1d7c-41af-8486-cbeab758a53f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45375165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_volatile_unlock_smoke.45375165
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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