Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57624949

1

T1

1933

T2

1397

T3

4833

auto[1]

1093886

1

T3

297

T4

297

T18

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57637331

1

T1

1933

T2

1397

T3

4536

auto[1]

1081504

1

T3

594

T4

198

T18

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	4934814	1			T1	263		T2	93		T3	1018
auto[IdleSt]	16372398	1			T1	403		T2	63		T3	2017
auto[ClkMuxSt]	29302	1			T1	2		T2	1		T3	9
auto[CntIncrSt]	29114	1			T1	2		T2	1		T3	9
auto[CntProgSt]	1504657	1			T1	123		T2	190		T3	54
auto[TransCheckSt]	22785	1			T1	2		T2	1		T4	5
auto[TokenHashSt]	16486563	1			T1	24		T2	17		T4	138
auto[FlashRmaSt]	28927	1			T1	2		T4	5		T18	89
auto[TokenCheck0St]	9972	1			T1	2		T4	5		T18	18
auto[TokenCheck1St]	7140	1			T1	2		T4	5		T18	10
auto[TransProgSt]	315211	1			T1	132		T4	1208		T18	158
auto[PostTransSt]	8993611	1			T1	976		T2	1031		T3	715
auto[ScrapSt]	119298	1			T33	2		T27	381		T48	8
auto[EscalateSt]	4324503	1			T3	1308		T4	1232		T18	1007
auto[InvalidSt]	5539294	1			T4	707		T33	2795		T24	551

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1246	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	5539294	1			T4	707		T33	2795		T24	551
EscalateSt	4324503	1			T3	1308		T4	1232		T18	1007
ScrapSt	119298	1			T33	2		T27	381		T48	8
PostTransSt	8993611	1			T1	976		T2	1031		T3	715
TransProgSt	315211	1			T1	132		T4	1208		T18	158
TokenCheck1St	7140	1			T1	2		T4	5		T18	10
TokenCheck0St	9972	1			T1	2		T4	5		T18	18
FlashRmaSt	28927	1			T1	2		T4	5		T18	89
TokenHashSt	16486563	1			T1	24		T2	17		T4	138
TransCheckSt	22785	1			T1	2		T2	1		T4	5
CntProgSt	1504657	1			T1	123		T2	190		T3	54
CntIncrSt	29114	1			T1	2		T2	1		T3	9
ClkMuxSt	29302	1			T1	2		T2	1		T3	9
IdleSt	16372398	1			T1	403		T2	63		T3	2017
ResetSt	4934814	1			T1	263		T2	93		T3	1018
arcs[ResetSt=>IdleSt]	41335	1			T1	2		T2	1		T3	10
arcs[IdleSt=>ScrapSt]	193	1			T33	1		T27	1		T48	2
arcs[IdleSt=>ClkMuxSt]	29162	1			T1	2		T2	1		T3	9
arcs[ClkMuxSt=>CntIncrSt]	29114	1			T1	2		T2	1		T3	9
arcs[CntIncrSt=>PostTransSt]	1280	1			T18	10		T20	14		T32	12
arcs[CntIncrSt=>CntProgSt]	27763	1			T1	2		T2	1		T3	9
arcs[CntProgSt=>PostTransSt]	3881	1			T3	9		T18	7		T22	18
arcs[CntProgSt=>TransCheckSt]	22785	1			T1	2		T2	1		T4	5
arcs[TransCheckSt=>PostTransSt]	3114	1			T18	13		T23	27		T20	13
arcs[TransCheckSt=>TokenHashSt]	19558	1			T1	2		T2	1		T4	5
arcs[TokenHashSt=>PostTransSt]	8775	1			T2	1		T15	1		T18	26
arcs[TokenHashSt=>FlashRmaSt]	10007	1			T1	2		T4	5		T18	18
arcs[FlashRmaSt=>TokenCheck0St]	9972	1			T1	2		T4	5		T18	18
arcs[TokenCheck0St=>PostTransSt]	2777	1			T18	8		T23	12		T29	8
arcs[TokenCheck0St=>TokenCheck1St]	7140	1			T1	2		T4	5		T18	10
arcs[TokenCheck1St=>PostTransSt]	607	1			T18	1		T23	11		T29	1
arcs[TransProgSt=>PostTransSt]	5763	1			T1	2		T4	5		T18	9
arcs[IdleSt=>EscalateSt]	152	1			T31	4		T48	8		T67	2
arcs[ClkMuxSt=>EscalateSt]	48	1			T31	1		T48	1		T67	1
arcs[CntIncrSt=>EscalateSt]	71	1			T31	1		T48	1		T68	2
arcs[CntProgSt=>EscalateSt]	1097	1			T31	42		T48	27		T68	38
arcs[TransCheckSt=>EscalateSt]	113	1			T48	1		T68	1		T21	5
arcs[TokenHashSt=>EscalateSt]	776	1			T31	7		T48	14		T68	8
arcs[FlashRmaSt=>EscalateSt]	35	1			T68	1		T69	1		T70	1
arcs[TokenCheck0St=>EscalateSt]	55	1			T31	1		T48	1		T68	1
arcs[TokenCheck1St=>EscalateSt]	30	1			T48	1		T68	3		T74	1
arcs[TransProgSt=>EscalateSt]	740	1			T31	19		T48	17		T68	17
arcs[PostTransSt=>EscalateSt]	4203	1			T3	9		T18	7		T22	18
arcs[InvalidSt=>EscalateSt]	8731	1			T4	5		T24	3		T29	14

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	4934627	1			T1	263		T2	93		T3	1018
auto[0]	auto[IdleSt]	16372291	1			T1	403		T2	63		T3	2017
auto[0]	auto[ClkMuxSt]	29267	1			T1	2		T2	1		T3	9
auto[0]	auto[CntIncrSt]	29064	1			T1	2		T2	1		T3	9
auto[0]	auto[CntProgSt]	1503938	1			T1	123		T2	190		T3	54
auto[0]	auto[TransCheckSt]	22718	1			T1	2		T2	1		T4	5
auto[0]	auto[TokenHashSt]	16486036	1			T1	24		T2	17		T4	138
auto[0]	auto[FlashRmaSt]	28906	1			T1	2		T4	5		T18	89
auto[0]	auto[TokenCheck0St]	9935	1			T1	2		T4	5		T18	18
auto[0]	auto[TokenCheck1St]	7121	1			T1	2		T4	5		T18	10
auto[0]	auto[TransProgSt]	314712	1			T1	132		T4	1208		T18	158
auto[0]	auto[PostTransSt]	8991449	1			T1	976		T2	1031		T3	712
auto[0]	auto[ScrapSt]	119258	1			T33	2		T27	381		T48	6
auto[0]	auto[EscalateSt]	3239471	1			T3	1014		T4	938		T18	615
auto[0]	auto[InvalidSt]	5534910	1			T4	704		T33	2795		T24	548
auto[1]	auto[ResetSt]	187	1			T31	5		T48	4		T68	5
auto[1]	auto[IdleSt]	107	1			T31	3		T48	6		T67	2
auto[1]	auto[ClkMuxSt]	35	1			T31	1		T48	1		T67	1
auto[1]	auto[CntIncrSt]	50	1			T48	1		T68	1		T21	2
auto[1]	auto[CntProgSt]	719	1			T31	25		T48	20		T68	24
auto[1]	auto[TransCheckSt]	67	1			T48	1		T68	1		T21	1
auto[1]	auto[TokenHashSt]	527	1			T31	5		T48	9		T68	6
auto[1]	auto[FlashRmaSt]	21	1			T68	1		T69	1		T70	1
auto[1]	auto[TokenCheck0St]	37	1			T31	1		T68	1		T21	1
auto[1]	auto[TokenCheck1St]	19	1			T68	2		T74	1		T214	1
auto[1]	auto[TransProgSt]	499	1			T31	13		T48	10		T68	10
auto[1]	auto[PostTransSt]	2162	1			T3	3		T18	4		T22	8
auto[1]	auto[ScrapSt]	40	1			T48	2		T68	1		T21	1
auto[1]	auto[EscalateSt]	1085032	1			T3	294		T4	294		T18	392
auto[1]	auto[InvalidSt]	4384	1			T4	3		T24	3		T29	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	4934652	1			T1	263		T2	93		T3	1018
auto[0]	auto[IdleSt]	16372307	1			T1	403		T2	63		T3	2017
auto[0]	auto[ClkMuxSt]	29267	1			T1	2		T2	1		T3	9
auto[0]	auto[CntIncrSt]	29071	1			T1	2		T2	1		T3	9
auto[0]	auto[CntProgSt]	1503910	1			T1	123		T2	190		T3	54
auto[0]	auto[TransCheckSt]	22706	1			T1	2		T2	1		T4	5
auto[0]	auto[TokenHashSt]	16486029	1			T1	24		T2	17		T4	138
auto[0]	auto[FlashRmaSt]	28902	1			T1	2		T4	5		T18	89
auto[0]	auto[TokenCheck0St]	9934	1			T1	2		T4	5		T18	18
auto[0]	auto[TokenCheck1St]	7121	1			T1	2		T4	5		T18	10
auto[0]	auto[TransProgSt]	314725	1			T1	132		T4	1208		T18	158
auto[0]	auto[PostTransSt]	8991479	1			T1	976		T2	1031		T3	709
auto[0]	auto[ScrapSt]	119270	1			T33	2		T27	381		T48	8
auto[0]	auto[EscalateSt]	3251765	1			T3	720		T4	1036		T18	713
auto[0]	auto[InvalidSt]	5534947	1			T4	705		T33	2795		T24	551
auto[1]	auto[ResetSt]	162	1			T31	7		T48	2		T68	5
auto[1]	auto[IdleSt]	91	1			T31	3		T48	4		T67	1
auto[1]	auto[ClkMuxSt]	35	1			T31	1		T48	1		T67	1
auto[1]	auto[CntIncrSt]	43	1			T31	1		T68	2		T21	1
auto[1]	auto[CntProgSt]	747	1			T31	30		T48	18		T68	28
auto[1]	auto[TransCheckSt]	79	1			T68	1		T21	5		T74	3
auto[1]	auto[TokenHashSt]	534	1			T31	6		T48	8		T68	6
auto[1]	auto[FlashRmaSt]	25	1			T68	1		T70	1		T215	3
auto[1]	auto[TokenCheck0St]	38	1			T31	1		T48	1		T67	1
auto[1]	auto[TokenCheck1St]	19	1			T48	1		T68	2		T74	1
auto[1]	auto[TransProgSt]	486	1			T31	11		T48	14		T68	13
auto[1]	auto[PostTransSt]	2132	1			T3	6		T18	3		T22	10
auto[1]	auto[ScrapSt]	28	1			T68	1		T21	1		T67	1
auto[1]	auto[EscalateSt]	1072738	1			T3	588		T4	196		T18	294
auto[1]	auto[InvalidSt]	4347	1			T4	2		T29	9		T35	1