Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58564878

1

T1

1504

T2

1222

T3

3825

auto[1]

1144304

1

T4

495

T21

594

T19

7274

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58589613

1

T1

1504

T2

1222

T3

3825

auto[1]

1119569

1

T4

594

T5

396

T21

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5496503	1			T1	89		T2	111		T3	833
auto[IdleSt]	16232758	1			T1	65		T2	1111		T3	1396
auto[ClkMuxSt]	29586	1			T1	1		T3	10		T4	11
auto[CntIncrSt]	29449	1			T1	1		T3	10		T4	11
auto[CntProgSt]	1485374	1			T1	55		T3	20		T4	332
auto[TransCheckSt]	23351	1			T1	1		T3	10		T13	1
auto[TokenHashSt]	15660805	1			T1	44		T3	560		T13	367
auto[FlashRmaSt]	28742	1			T3	58		T15	28		T6	1
auto[TokenCheck0St]	10319	1			T3	10		T15	13		T6	1
auto[TokenCheck1St]	7390	1			T3	10		T15	13		T6	1
auto[TransProgSt]	319511	1			T3	20		T15	731		T6	11
auto[PostTransSt]	9101368	1			T1	1248		T3	888		T4	755
auto[ScrapSt]	69634	1			T15	17		T19	8		T27	93
auto[EscalateSt]	4490032	1			T4	1363		T5	566		T21	2115
auto[InvalidSt]	6722859	1			T21	1305		T23	414		T24	2929

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1501	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6722859	1			T21	1305		T23	414		T24	2929
EscalateSt	4490032	1			T4	1363		T5	566		T21	2115
ScrapSt	69634	1			T15	17		T19	8		T27	93
PostTransSt	9101368	1			T1	1248		T3	888		T4	755
TransProgSt	319511	1			T3	20		T15	731		T6	11
TokenCheck1St	7390	1			T3	10		T15	13		T6	1
TokenCheck0St	10319	1			T3	10		T15	13		T6	1
FlashRmaSt	28742	1			T3	58		T15	28		T6	1
TokenHashSt	15660805	1			T1	44		T3	560		T13	367
TransCheckSt	23351	1			T1	1		T3	10		T13	1
CntProgSt	1485374	1			T1	55		T3	20		T4	332
CntIncrSt	29449	1			T1	1		T3	10		T4	11
ClkMuxSt	29586	1			T1	1		T3	10		T4	11
IdleSt	16232758	1			T1	65		T2	1111		T3	1396
ResetSt	5496503	1			T1	89		T2	111		T3	833
arcs[ResetSt=>IdleSt]	43406	1			T1	1		T2	1		T3	10
arcs[IdleSt=>ScrapSt]	214	1			T15	2		T19	2		T27	3
arcs[IdleSt=>ClkMuxSt]	29472	1			T1	1		T3	10		T4	11
arcs[ClkMuxSt=>CntIncrSt]	29449	1			T1	1		T3	10		T4	11
arcs[CntIncrSt=>PostTransSt]	1410	1			T25	10		T28	7		T29	7
arcs[CntIncrSt=>CntProgSt]	27972	1			T1	1		T3	10		T4	11
arcs[CntProgSt=>PostTransSt]	3507	1			T4	11		T5	4		T24	8
arcs[CntProgSt=>TransCheckSt]	23351	1			T1	1		T3	10		T13	1
arcs[TransCheckSt=>PostTransSt]	3307	1			T20	25		T25	13		T28	11
arcs[TransCheckSt=>TokenHashSt]	19945	1			T1	1		T3	10		T13	1
arcs[TokenHashSt=>PostTransSt]	8861	1			T1	1		T13	1		T20	3
arcs[TokenHashSt=>FlashRmaSt]	10357	1			T3	10		T15	13		T6	1
arcs[FlashRmaSt=>TokenCheck0St]	10319	1			T3	10		T15	13		T6	1
arcs[TokenCheck0St=>PostTransSt]	2889	1			T20	31		T24	11		T25	9
arcs[TokenCheck0St=>TokenCheck1St]	7390	1			T3	10		T15	13		T6	1
arcs[TokenCheck1St=>PostTransSt]	667	1			T20	8		T24	1		T25	1
arcs[TransProgSt=>PostTransSt]	5848	1			T3	10		T15	13		T6	1
arcs[IdleSt=>EscalateSt]	150	1			T43	7		T16	4		T57	8
arcs[ClkMuxSt=>EscalateSt]	23	1			T43	2		T54	1		T55	1
arcs[CntIncrSt=>EscalateSt]	67	1			T19	1		T43	2		T16	1
arcs[CntProgSt=>EscalateSt]	1114	1			T19	24		T43	5		T16	9
arcs[TransCheckSt=>EscalateSt]	99	1			T19	1		T43	9		T16	3
arcs[TokenHashSt=>EscalateSt]	727	1			T19	7		T43	35		T16	15
arcs[FlashRmaSt=>EscalateSt]	38	1			T19	1		T43	1		T56	1
arcs[TokenCheck0St=>EscalateSt]	40	1			T19	2		T56	2		T57	1
arcs[TokenCheck1St=>EscalateSt]	28	1			T19	2		T16	1		T56	1
arcs[TransProgSt=>EscalateSt]	847	1			T19	22		T43	7		T16	8
arcs[PostTransSt=>EscalateSt]	3816	1			T4	11		T5	4		T19	1
arcs[InvalidSt=>EscalateSt]	9974	1			T21	9		T23	2		T24	15

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5496300	1			T1	89		T2	111		T3	833
auto[0]	auto[IdleSt]	16232662	1			T1	65		T2	1111		T3	1396
auto[0]	auto[ClkMuxSt]	29574	1			T1	1		T3	10		T4	11
auto[0]	auto[CntIncrSt]	29396	1			T1	1		T3	10		T4	11
auto[0]	auto[CntProgSt]	1484633	1			T1	55		T3	20		T4	332
auto[0]	auto[TransCheckSt]	23281	1			T1	1		T3	10		T13	1
auto[0]	auto[TokenHashSt]	15660314	1			T1	44		T3	560		T13	367
auto[0]	auto[FlashRmaSt]	28717	1			T3	58		T15	28		T6	1
auto[0]	auto[TokenCheck0St]	10291	1			T3	10		T15	13		T6	1
auto[0]	auto[TokenCheck1St]	7371	1			T3	10		T15	13		T6	1
auto[0]	auto[TransProgSt]	318953	1			T3	20		T15	731		T6	11
auto[0]	auto[PostTransSt]	9099390	1			T1	1248		T3	888		T4	750
auto[0]	auto[ScrapSt]	69583	1			T15	17		T19	7		T27	93
auto[0]	auto[EscalateSt]	3355105	1			T4	873		T5	566		T21	1527
auto[0]	auto[InvalidSt]	6717807	1			T21	1299		T23	414		T24	2919
auto[1]	auto[ResetSt]	203	1			T19	5		T43	6		T16	4
auto[1]	auto[IdleSt]	96	1			T43	5		T16	1		T57	5
auto[1]	auto[ClkMuxSt]	12	1			T55	1		T187	3		T221	1
auto[1]	auto[CntIncrSt]	53	1			T19	1		T43	2		T56	2
auto[1]	auto[CntProgSt]	741	1			T19	16		T43	4		T16	5
auto[1]	auto[TransCheckSt]	70	1			T19	1		T43	9		T16	2
auto[1]	auto[TokenHashSt]	491	1			T19	4		T43	22		T16	12
auto[1]	auto[FlashRmaSt]	25	1			T19	1		T56	1		T222	1
auto[1]	auto[TokenCheck0St]	28	1			T19	1		T56	1		T222	1
auto[1]	auto[TokenCheck1St]	19	1			T19	1		T56	1		T57	1
auto[1]	auto[TransProgSt]	558	1			T19	12		T43	4		T16	7
auto[1]	auto[PostTransSt]	1978	1			T4	5		T19	1		T24	6
auto[1]	auto[ScrapSt]	51	1			T19	1		T16	1		T56	1
auto[1]	auto[EscalateSt]	1134927	1			T4	490		T21	588		T19	7230
auto[1]	auto[InvalidSt]	5052	1			T21	6		T24	10		T26	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5496301	1			T1	89		T2	111		T3	833
auto[0]	auto[IdleSt]	16232659	1			T1	65		T2	1111		T3	1396
auto[0]	auto[ClkMuxSt]	29568	1			T1	1		T3	10		T4	11
auto[0]	auto[CntIncrSt]	29413	1			T1	1		T3	10		T4	11
auto[0]	auto[CntProgSt]	1484630	1			T1	55		T3	20		T4	332
auto[0]	auto[TransCheckSt]	23286	1			T1	1		T3	10		T13	1
auto[0]	auto[TokenHashSt]	15660333	1			T1	44		T3	560		T13	367
auto[0]	auto[FlashRmaSt]	28715	1			T3	58		T15	28		T6	1
auto[0]	auto[TokenCheck0St]	10289	1			T3	10		T15	13		T6	1
auto[0]	auto[TokenCheck1St]	7372	1			T3	10		T15	13		T6	1
auto[0]	auto[TransProgSt]	318955	1			T3	20		T15	731		T6	11
auto[0]	auto[PostTransSt]	9099442	1			T1	1248		T3	888		T4	749
auto[0]	auto[ScrapSt]	69580	1			T15	17		T19	6		T27	93
auto[0]	auto[EscalateSt]	3379632	1			T4	775		T5	174		T21	1821
auto[0]	auto[InvalidSt]	6717937	1			T21	1302		T23	412		T24	2924
auto[1]	auto[ResetSt]	202	1			T19	3		T43	5		T16	1
auto[1]	auto[IdleSt]	99	1			T43	4		T16	4		T57	4
auto[1]	auto[ClkMuxSt]	18	1			T43	2		T54	1		T187	2
auto[1]	auto[CntIncrSt]	36	1			T43	2		T16	1		T56	2
auto[1]	auto[CntProgSt]	744	1			T19	17		T43	2		T16	7
auto[1]	auto[TransCheckSt]	65	1			T19	1		T43	7		T16	3
auto[1]	auto[TokenHashSt]	472	1			T19	5		T43	26		T16	8
auto[1]	auto[FlashRmaSt]	27	1			T19	1		T43	1		T56	1
auto[1]	auto[TokenCheck0St]	30	1			T19	2		T56	1		T57	1
auto[1]	auto[TokenCheck1St]	18	1			T19	1		T16	1		T18	1
auto[1]	auto[TransProgSt]	556	1			T19	14		T43	5		T16	5
auto[1]	auto[PostTransSt]	1926	1			T4	6		T5	4		T19	1
auto[1]	auto[ScrapSt]	54	1			T19	2		T16	2		T56	1
auto[1]	auto[EscalateSt]	1110400	1			T4	588		T5	392		T21	294
auto[1]	auto[InvalidSt]	4922	1			T21	3		T23	2		T24	5