Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

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Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_q	8	0	8	100.00	100	1	1	0

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_states[ClkMuxSt]	489	1			T20	4		T44	15		T45	12
fsm_states[CntIncrSt]	457	1			T20	11		T44	10		T45	6
fsm_states[CntProgSt]	488	1			T20	5		T44	7		T45	8
fsm_states[TransCheckSt]	476	1			T20	5		T44	9		T45	9
fsm_states[FlashRmaSt]	477	1			T20	17		T44	11		T45	7
fsm_states[TokenHashSt]	482	1			T20	3		T44	11		T45	11
fsm_states[TokenCheck0St]	460	1			T20	14		T44	21		T45	6
fsm_states[TokenCheck1St]	505	1			T20	8		T44	16		T45	8