Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51534 |
1 |
|
|
T6 |
1 |
|
T4 |
444 |
|
T5 |
76 |
auto[1] |
1819 |
1 |
|
|
T4 |
26 |
|
T5 |
11 |
|
T13 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52589 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
auto[1] |
764 |
1 |
|
|
T40 |
17 |
|
T46 |
17 |
|
T47 |
14 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51524 |
1 |
|
|
T6 |
1 |
|
T4 |
450 |
|
T5 |
87 |
auto[1] |
1829 |
1 |
|
|
T4 |
20 |
|
T20 |
11 |
|
T21 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51461 |
1 |
|
|
T6 |
1 |
|
T4 |
443 |
|
T5 |
87 |
auto[1] |
1892 |
1 |
|
|
T4 |
27 |
|
T20 |
9 |
|
T21 |
2 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51514 |
1 |
|
|
T6 |
1 |
|
T4 |
439 |
|
T5 |
87 |
auto[1] |
1839 |
1 |
|
|
T4 |
31 |
|
T20 |
14 |
|
T21 |
2 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48764 |
1 |
|
|
T4 |
416 |
|
T5 |
87 |
|
T13 |
81 |
no_err_inj |
4589 |
1 |
|
|
T6 |
1 |
|
T4 |
54 |
|
T20 |
61 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51516 |
1 |
|
|
T6 |
1 |
|
T4 |
443 |
|
T5 |
77 |
auto[1] |
1837 |
1 |
|
|
T4 |
27 |
|
T5 |
10 |
|
T13 |
5 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52583 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
auto[1] |
770 |
1 |
|
|
T40 |
19 |
|
T46 |
11 |
|
T47 |
17 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36985 |
1 |
|
|
T4 |
283 |
|
T13 |
81 |
|
T14 |
18 |
auto[1] |
16368 |
1 |
|
|
T6 |
1 |
|
T4 |
187 |
|
T5 |
87 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51463 |
1 |
|
|
T6 |
1 |
|
T4 |
451 |
|
T5 |
87 |
auto[1] |
1890 |
1 |
|
|
T4 |
19 |
|
T20 |
10 |
|
T54 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51497 |
1 |
|
|
T6 |
1 |
|
T4 |
449 |
|
T5 |
87 |
auto[1] |
1856 |
1 |
|
|
T4 |
21 |
|
T20 |
7 |
|
T54 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51460 |
1 |
|
|
T6 |
1 |
|
T4 |
447 |
|
T5 |
87 |
auto[1] |
1893 |
1 |
|
|
T4 |
23 |
|
T20 |
11 |
|
T21 |
2 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51521 |
1 |
|
|
T6 |
1 |
|
T4 |
443 |
|
T5 |
70 |
auto[1] |
1832 |
1 |
|
|
T4 |
27 |
|
T5 |
17 |
|
T13 |
18 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51083 |
1 |
|
|
T6 |
1 |
|
T4 |
457 |
|
T5 |
87 |
auto[1] |
2270 |
1 |
|
|
T4 |
13 |
|
T14 |
18 |
|
T20 |
17 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52623 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
auto[1] |
730 |
1 |
|
|
T40 |
22 |
|
T46 |
19 |
|
T47 |
15 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52630 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
auto[1] |
723 |
1 |
|
|
T40 |
11 |
|
T46 |
13 |
|
T47 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52574 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
auto[1] |
779 |
1 |
|
|
T40 |
14 |
|
T46 |
25 |
|
T47 |
6 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50795 |
1 |
|
|
T6 |
1 |
|
T4 |
401 |
|
T5 |
87 |
auto[1] |
2558 |
1 |
|
|
T4 |
69 |
|
T20 |
12 |
|
T54 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49683 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
auto[1] |
3670 |
1 |
|
|
T19 |
83 |
|
T55 |
56 |
|
T56 |
99 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51513 |
1 |
|
|
T6 |
1 |
|
T4 |
446 |
|
T5 |
87 |
auto[1] |
1840 |
1 |
|
|
T4 |
24 |
|
T20 |
11 |
|
T54 |
2 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51545 |
1 |
|
|
T6 |
1 |
|
T4 |
460 |
|
T5 |
87 |
auto[1] |
1808 |
1 |
|
|
T4 |
10 |
|
T20 |
9 |
|
T21 |
3 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51457 |
1 |
|
|
T6 |
1 |
|
T4 |
451 |
|
T5 |
87 |
auto[1] |
1896 |
1 |
|
|
T4 |
19 |
|
T20 |
12 |
|
T54 |
2 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51519 |
1 |
|
|
T6 |
1 |
|
T4 |
446 |
|
T5 |
78 |
auto[1] |
1834 |
1 |
|
|
T4 |
24 |
|
T5 |
9 |
|
T13 |
7 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47732 |
1 |
|
|
T6 |
1 |
|
T4 |
434 |
|
T5 |
73 |
auto[1] |
5621 |
1 |
|
|
T4 |
36 |
|
T5 |
14 |
|
T13 |
12 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49451 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
auto[1] |
3902 |
1 |
|
|
T15 |
91 |
|
T16 |
68 |
|
T18 |
52 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53353 |
1 |
|
|
T6 |
1 |
|
T4 |
470 |
|
T5 |
87 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51495 |
1 |
|
|
T6 |
1 |
|
T4 |
453 |
|
T5 |
79 |
auto[1] |
1858 |
1 |
|
|
T4 |
17 |
|
T5 |
8 |
|
T13 |
11 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51555 |
1 |
|
|
T6 |
1 |
|
T4 |
451 |
|
T5 |
77 |
auto[1] |
1798 |
1 |
|
|
T4 |
19 |
|
T5 |
10 |
|
T13 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51539 |
1 |
|
|
T6 |
1 |
|
T4 |
437 |
|
T5 |
79 |
auto[1] |
1814 |
1 |
|
|
T4 |
33 |
|
T5 |
8 |
|
T13 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47485 |
1 |
|
|
T4 |
378 |
|
T5 |
87 |
|
T13 |
81 |
auto[0] |
no_err_inj |
3310 |
1 |
|
|
T6 |
1 |
|
T4 |
23 |
|
T20 |
55 |
auto[1] |
err_inj |
1279 |
1 |
|
|
T4 |
38 |
|
T20 |
6 |
|
T54 |
7 |
auto[1] |
no_err_inj |
1279 |
1 |
|
|
T4 |
31 |
|
T20 |
6 |
|
T54 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49120 |
1 |
|
|
T6 |
1 |
|
T4 |
391 |
|
T5 |
87 |
auto[0] |
auto[1] |
1675 |
1 |
|
|
T4 |
10 |
|
T20 |
9 |
|
T34 |
4 |
auto[1] |
auto[0] |
2425 |
1 |
|
|
T4 |
69 |
|
T20 |
12 |
|
T54 |
13 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T21 |
3 |
|
T24 |
1 |
|
T99 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49062 |
1 |
|
|
T6 |
1 |
|
T4 |
384 |
|
T5 |
87 |
auto[0] |
auto[1] |
1733 |
1 |
|
|
T4 |
17 |
|
T20 |
7 |
|
T34 |
4 |
auto[1] |
auto[0] |
2435 |
1 |
|
|
T4 |
65 |
|
T20 |
12 |
|
T54 |
11 |
auto[1] |
auto[1] |
123 |
1 |
|
|
T4 |
4 |
|
T54 |
2 |
|
T21 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49053 |
1 |
|
|
T6 |
1 |
|
T4 |
386 |
|
T5 |
87 |
auto[0] |
auto[1] |
1742 |
1 |
|
|
T4 |
15 |
|
T20 |
12 |
|
T34 |
4 |
auto[1] |
auto[0] |
2404 |
1 |
|
|
T4 |
65 |
|
T20 |
12 |
|
T54 |
11 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T4 |
4 |
|
T54 |
2 |
|
T21 |
4 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49061 |
1 |
|
|
T6 |
1 |
|
T4 |
379 |
|
T5 |
87 |
auto[0] |
auto[1] |
1734 |
1 |
|
|
T4 |
22 |
|
T20 |
9 |
|
T34 |
6 |
auto[1] |
auto[0] |
2400 |
1 |
|
|
T4 |
64 |
|
T20 |
12 |
|
T54 |
13 |
auto[1] |
auto[1] |
158 |
1 |
|
|
T4 |
5 |
|
T21 |
2 |
|
T99 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49094 |
1 |
|
|
T6 |
1 |
|
T4 |
375 |
|
T5 |
87 |
auto[0] |
auto[1] |
1701 |
1 |
|
|
T4 |
26 |
|
T20 |
13 |
|
T34 |
12 |
auto[1] |
auto[0] |
2420 |
1 |
|
|
T4 |
64 |
|
T20 |
11 |
|
T54 |
13 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T4 |
5 |
|
T20 |
1 |
|
T21 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49111 |
1 |
|
|
T6 |
1 |
|
T4 |
388 |
|
T5 |
87 |
auto[0] |
auto[1] |
1684 |
1 |
|
|
T4 |
13 |
|
T20 |
9 |
|
T34 |
4 |
auto[1] |
auto[0] |
2413 |
1 |
|
|
T4 |
62 |
|
T20 |
10 |
|
T54 |
13 |
auto[1] |
auto[1] |
145 |
1 |
|
|
T4 |
7 |
|
T20 |
2 |
|
T21 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35940 |
1 |
|
|
T4 |
263 |
|
T13 |
72 |
|
T14 |
18 |
auto[0] |
auto[1] |
1045 |
1 |
|
|
T4 |
20 |
|
T13 |
9 |
|
T17 |
15 |
auto[1] |
auto[0] |
15594 |
1 |
|
|
T6 |
1 |
|
T4 |
181 |
|
T5 |
76 |
auto[1] |
auto[1] |
774 |
1 |
|
|
T4 |
6 |
|
T5 |
11 |
|
T20 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35925 |
1 |
|
|
T4 |
261 |
|
T13 |
76 |
|
T14 |
18 |
auto[0] |
auto[1] |
1060 |
1 |
|
|
T4 |
22 |
|
T13 |
5 |
|
T17 |
8 |
auto[1] |
auto[0] |
15591 |
1 |
|
|
T6 |
1 |
|
T4 |
182 |
|
T5 |
77 |
auto[1] |
auto[1] |
777 |
1 |
|
|
T4 |
5 |
|
T5 |
10 |
|
T20 |
16 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35699 |
1 |
|
|
T4 |
270 |
|
T13 |
81 |
|
T15 |
91 |
auto[0] |
auto[1] |
1286 |
1 |
|
|
T4 |
13 |
|
T14 |
18 |
|
T20 |
17 |
auto[1] |
auto[0] |
15384 |
1 |
|
|
T6 |
1 |
|
T4 |
187 |
|
T5 |
87 |
auto[1] |
auto[1] |
984 |
1 |
|
|
T21 |
18 |
|
T206 |
2 |
|
T44 |
13 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35922 |
1 |
|
|
T4 |
263 |
|
T13 |
63 |
|
T14 |
18 |
auto[0] |
auto[1] |
1063 |
1 |
|
|
T4 |
20 |
|
T13 |
18 |
|
T17 |
7 |
auto[1] |
auto[0] |
15599 |
1 |
|
|
T6 |
1 |
|
T4 |
180 |
|
T5 |
70 |
auto[1] |
auto[1] |
769 |
1 |
|
|
T4 |
7 |
|
T5 |
17 |
|
T20 |
17 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32165 |
1 |
|
|
T4 |
259 |
|
T13 |
69 |
|
T14 |
18 |
auto[0] |
auto[1] |
4820 |
1 |
|
|
T4 |
24 |
|
T13 |
12 |
|
T17 |
10 |
auto[1] |
auto[0] |
15567 |
1 |
|
|
T6 |
1 |
|
T4 |
175 |
|
T5 |
73 |
auto[1] |
auto[1] |
801 |
1 |
|
|
T4 |
12 |
|
T5 |
14 |
|
T20 |
7 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35969 |
1 |
|
|
T4 |
279 |
|
T13 |
81 |
|
T14 |
18 |
auto[0] |
auto[1] |
1016 |
1 |
|
|
T4 |
4 |
|
T20 |
9 |
|
T34 |
4 |
auto[1] |
auto[0] |
15576 |
1 |
|
|
T6 |
1 |
|
T4 |
181 |
|
T5 |
87 |
auto[1] |
auto[1] |
792 |
1 |
|
|
T4 |
6 |
|
T21 |
3 |
|
T24 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35933 |
1 |
|
|
T4 |
270 |
|
T13 |
81 |
|
T14 |
18 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T4 |
13 |
|
T20 |
10 |
|
T54 |
2 |
auto[1] |
auto[0] |
15580 |
1 |
|
|
T6 |
1 |
|
T4 |
176 |
|
T5 |
87 |
auto[1] |
auto[1] |
788 |
1 |
|
|
T4 |
11 |
|
T20 |
1 |
|
T21 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35964 |
1 |
|
|
T4 |
271 |
|
T13 |
81 |
|
T14 |
18 |
auto[0] |
auto[1] |
1021 |
1 |
|
|
T4 |
12 |
|
T20 |
7 |
|
T54 |
2 |
auto[1] |
auto[0] |
15533 |
1 |
|
|
T6 |
1 |
|
T4 |
178 |
|
T5 |
87 |
auto[1] |
auto[1] |
835 |
1 |
|
|
T4 |
9 |
|
T21 |
3 |
|
T24 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35921 |
1 |
|
|
T4 |
272 |
|
T13 |
81 |
|
T14 |
18 |
auto[0] |
auto[1] |
1064 |
1 |
|
|
T4 |
11 |
|
T20 |
10 |
|
T54 |
1 |
auto[1] |
auto[0] |
15542 |
1 |
|
|
T6 |
1 |
|
T4 |
179 |
|
T5 |
87 |
auto[1] |
auto[1] |
826 |
1 |
|
|
T4 |
8 |
|
T21 |
1 |
|
T44 |
37 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35961 |
1 |
|
|
T4 |
272 |
|
T13 |
81 |
|
T14 |
18 |
auto[0] |
auto[1] |
1024 |
1 |
|
|
T4 |
11 |
|
T20 |
9 |
|
T34 |
6 |
auto[1] |
auto[0] |
15500 |
1 |
|
|
T6 |
1 |
|
T4 |
171 |
|
T5 |
87 |
auto[1] |
auto[1] |
868 |
1 |
|
|
T4 |
16 |
|
T21 |
2 |
|
T44 |
41 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35930 |
1 |
|
|
T4 |
273 |
|
T13 |
81 |
|
T14 |
18 |
auto[0] |
auto[1] |
1055 |
1 |
|
|
T4 |
10 |
|
T20 |
9 |
|
T34 |
4 |
auto[1] |
auto[0] |
15594 |
1 |
|
|
T6 |
1 |
|
T4 |
177 |
|
T5 |
87 |
auto[1] |
auto[1] |
774 |
1 |
|
|
T4 |
10 |
|
T20 |
2 |
|
T21 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35963 |
1 |
|
|
T4 |
257 |
|
T13 |
72 |
|
T14 |
18 |
auto[0] |
auto[1] |
1022 |
1 |
|
|
T4 |
26 |
|
T13 |
9 |
|
T17 |
10 |
auto[1] |
auto[0] |
15576 |
1 |
|
|
T6 |
1 |
|
T4 |
180 |
|
T5 |
79 |
auto[1] |
auto[1] |
792 |
1 |
|
|
T4 |
7 |
|
T5 |
8 |
|
T20 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35968 |
1 |
|
|
T4 |
267 |
|
T13 |
71 |
|
T14 |
18 |
auto[0] |
auto[1] |
1017 |
1 |
|
|
T4 |
16 |
|
T13 |
10 |
|
T17 |
7 |
auto[1] |
auto[0] |
15587 |
1 |
|
|
T6 |
1 |
|
T4 |
184 |
|
T5 |
77 |
auto[1] |
auto[1] |
781 |
1 |
|
|
T4 |
3 |
|
T5 |
10 |
|
T20 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35410 |
1 |
|
|
T4 |
248 |
|
T13 |
81 |
|
T14 |
18 |
auto[0] |
auto[1] |
1575 |
1 |
|
|
T4 |
35 |
|
T54 |
13 |
|
T99 |
14 |
auto[1] |
auto[0] |
15385 |
1 |
|
|
T6 |
1 |
|
T4 |
153 |
|
T5 |
87 |
auto[1] |
auto[1] |
983 |
1 |
|
|
T4 |
34 |
|
T20 |
12 |
|
T21 |
42 |