Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105398971

1

T1

19613

T2

1429

T3

1259

auto[1]

1368725

1

T4

8775

T5

495

T13

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105397778

1

T1

19613

T2

1429

T3

1259

auto[1]

1369918

1

T4

10219

T5

594

T13

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7363429	1			T1	10745		T2	99		T3	112
auto[IdleSt]	22126068	1			T1	3967		T2	1330		T3	202
auto[ClkMuxSt]	35507	1			T6	1		T4	277		T5	87
auto[CntIncrSt]	35220	1			T6	1		T4	277		T5	87
auto[CntProgSt]	1297838	1			T6	34		T4	490		T5	2195
auto[TransCheckSt]	27619	1			T6	1		T4	218		T5	66
auto[TokenHashSt]	43384123	1			T6	12		T4	660096		T5	51145
auto[FlashRmaSt]	28234	1			T6	1		T4	262		T5	37
auto[TokenCheck0St]	12655	1			T6	1		T4	107		T5	27
auto[TokenCheck1St]	9266	1			T6	1		T4	86		T5	18
auto[TransProgSt]	247621	1			T6	10		T4	163		T5	559
auto[PostTransSt]	13244958	1			T3	945		T6	999		T4	112480
auto[ScrapSt]	232835	1			T1	242		T4	3129		T20	13
auto[EscalateSt]	6796685	1			T4	70838		T5	4401		T13	1211
auto[InvalidSt]	11923709	1			T1	4639		T4	132687		T20	9651

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1929	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11923709	1			T1	4639		T4	132687		T20	9651
EscalateSt	6796685	1			T4	70838		T5	4401		T13	1211
ScrapSt	232835	1			T1	242		T4	3129		T20	13
PostTransSt	13244958	1			T3	945		T6	999		T4	112480
TransProgSt	247621	1			T6	10		T4	163		T5	559
TokenCheck1St	9266	1			T6	1		T4	86		T5	18
TokenCheck0St	12655	1			T6	1		T4	107		T5	27
FlashRmaSt	28234	1			T6	1		T4	262		T5	37
TokenHashSt	43384123	1			T6	12		T4	660096		T5	51145
TransCheckSt	27619	1			T6	1		T4	218		T5	66
CntProgSt	1297838	1			T6	34		T4	490		T5	2195
CntIncrSt	35220	1			T6	1		T4	277		T5	87
ClkMuxSt	35507	1			T6	1		T4	277		T5	87
IdleSt	22126068	1			T1	3967		T2	1330		T3	202
ResetSt	7363429	1			T1	10745		T2	99		T3	112
arcs[ResetSt=>IdleSt]	53598	1			T1	121		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	298	1			T1	6		T4	1		T20	1
arcs[IdleSt=>ClkMuxSt]	35276	1			T6	1		T4	277		T5	87
arcs[ClkMuxSt=>CntIncrSt]	35220	1			T6	1		T4	277		T5	87
arcs[CntIncrSt=>PostTransSt]	1801	1			T4	19		T5	10		T13	10
arcs[CntIncrSt=>CntProgSt]	33343	1			T6	1		T4	258		T5	77
arcs[CntProgSt=>PostTransSt]	4788	1			T4	40		T5	11		T13	8
arcs[CntProgSt=>TransCheckSt]	27619	1			T6	1		T4	218		T5	66
arcs[TransCheckSt=>PostTransSt]	3737	1			T4	33		T5	8		T13	9
arcs[TransCheckSt=>TokenHashSt]	23739	1			T6	1		T4	185		T5	58
arcs[TokenHashSt=>PostTransSt]	10251	1			T4	78		T5	31		T13	30
arcs[TokenHashSt=>FlashRmaSt]	12757	1			T6	1		T4	107		T5	27
arcs[FlashRmaSt=>TokenCheck0St]	12655	1			T6	1		T4	107		T5	27
arcs[TokenCheck0St=>PostTransSt]	3362	1			T4	21		T5	9		T13	5
arcs[TokenCheck0St=>TokenCheck1St]	9266	1			T6	1		T4	86		T5	18
arcs[TokenCheck1St=>PostTransSt]	669	1			T4	4		T5	1		T15	13
arcs[TransProgSt=>PostTransSt]	7724	1			T6	1		T4	82		T5	17
arcs[IdleSt=>EscalateSt]	205	1			T55	3		T56	8		T58	4
arcs[ClkMuxSt=>EscalateSt]	56	1			T19	1		T55	2		T56	5
arcs[CntIncrSt=>EscalateSt]	76	1			T19	4		T55	2		T57	3
arcs[CntProgSt=>EscalateSt]	936	1			T19	12		T55	19		T56	34
arcs[TransCheckSt=>EscalateSt]	143	1			T19	8		T59	10		T61	1
arcs[TokenHashSt=>EscalateSt]	731	1			T13	1		T19	23		T55	6
arcs[FlashRmaSt=>EscalateSt]	102	1			T19	4		T55	2		T56	1
arcs[TokenCheck0St=>EscalateSt]	27	1			T19	1		T58	1		T60	1
arcs[TokenCheck1St=>EscalateSt]	147	1			T19	6		T55	1		T56	3
arcs[TransProgSt=>EscalateSt]	726	1			T19	6		T55	16		T56	23
arcs[PostTransSt=>EscalateSt]	5081	1			T4	40		T5	11		T13	8
arcs[InvalidSt=>EscalateSt]	13693	1			T4	153		T20	71		T54	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7363271	1			T1	10745		T2	99		T3	112
auto[0]	auto[IdleSt]	22125924	1			T1	3967		T2	1330		T3	202
auto[0]	auto[ClkMuxSt]	35462	1			T6	1		T4	277		T5	87
auto[0]	auto[CntIncrSt]	35167	1			T6	1		T4	277		T5	87
auto[0]	auto[CntProgSt]	1297223	1			T6	34		T4	490		T5	2195
auto[0]	auto[TransCheckSt]	27524	1			T6	1		T4	218		T5	66
auto[0]	auto[TokenHashSt]	43383637	1			T6	12		T4	660096		T5	51145
auto[0]	auto[FlashRmaSt]	28171	1			T6	1		T4	262		T5	37
auto[0]	auto[TokenCheck0St]	12640	1			T6	1		T4	107		T5	27
auto[0]	auto[TokenCheck1St]	9166	1			T6	1		T4	86		T5	18
auto[0]	auto[TransProgSt]	247129	1			T6	10		T4	163		T5	559
auto[0]	auto[PostTransSt]	13242407	1			T3	945		T6	999		T4	112463
auto[0]	auto[ScrapSt]	232799	1			T1	242		T4	3129		T20	13
auto[0]	auto[EscalateSt]	5439643	1			T4	62152		T5	3911		T13	819
auto[0]	auto[InvalidSt]	11916879	1			T1	4639		T4	132615		T20	9613
auto[1]	auto[ResetSt]	158	1			T19	5		T55	3		T56	7
auto[1]	auto[IdleSt]	144	1			T55	2		T56	7		T58	1
auto[1]	auto[ClkMuxSt]	45	1			T55	1		T56	4		T58	2
auto[1]	auto[CntIncrSt]	53	1			T19	3		T55	1		T57	1
auto[1]	auto[CntProgSt]	615	1			T19	7		T55	8		T56	23
auto[1]	auto[TransCheckSt]	95	1			T19	8		T59	7		T202	4
auto[1]	auto[TokenHashSt]	486	1			T19	16		T55	6		T56	6
auto[1]	auto[FlashRmaSt]	63	1			T19	2		T55	1		T56	1
auto[1]	auto[TokenCheck0St]	15	1			T19	1		T59	1		T203	1
auto[1]	auto[TokenCheck1St]	100	1			T19	5		T55	1		T56	2
auto[1]	auto[TransProgSt]	492	1			T19	5		T55	10		T56	17
auto[1]	auto[PostTransSt]	2551	1			T4	17		T5	5		T13	4
auto[1]	auto[ScrapSt]	36	1			T57	1		T204	1		T205	1
auto[1]	auto[EscalateSt]	1357042	1			T4	8686		T5	490		T13	392
auto[1]	auto[InvalidSt]	6830	1			T4	72		T20	38		T54	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7363272	1			T1	10745		T2	99		T3	112
auto[0]	auto[IdleSt]	22125939	1			T1	3967		T2	1330		T3	202
auto[0]	auto[ClkMuxSt]	35473	1			T6	1		T4	277		T5	87
auto[0]	auto[CntIncrSt]	35175	1			T6	1		T4	277		T5	87
auto[0]	auto[CntProgSt]	1297184	1			T6	34		T4	490		T5	2195
auto[0]	auto[TransCheckSt]	27522	1			T6	1		T4	218		T5	66
auto[0]	auto[TokenHashSt]	43383657	1			T6	12		T4	660096		T5	51145
auto[0]	auto[FlashRmaSt]	28164	1			T6	1		T4	262		T5	37
auto[0]	auto[TokenCheck0St]	12637	1			T6	1		T4	107		T5	27
auto[0]	auto[TokenCheck1St]	9174	1			T6	1		T4	86		T5	18
auto[0]	auto[TransProgSt]	247145	1			T6	10		T4	163		T5	559
auto[0]	auto[PostTransSt]	13242351	1			T3	945		T6	999		T4	112457
auto[0]	auto[ScrapSt]	232789	1			T1	242		T4	3129		T20	13
auto[0]	auto[EscalateSt]	5438521	1			T4	60723		T5	3813		T13	721
auto[0]	auto[InvalidSt]	11916846	1			T1	4639		T4	132606		T20	9618
auto[1]	auto[ResetSt]	157	1			T19	6		T55	4		T56	7
auto[1]	auto[IdleSt]	129	1			T55	1		T56	5		T58	3
auto[1]	auto[ClkMuxSt]	34	1			T19	1		T55	1		T56	2
auto[1]	auto[CntIncrSt]	45	1			T19	1		T55	1		T57	3
auto[1]	auto[CntProgSt]	654	1			T19	7		T55	16		T56	24
auto[1]	auto[TransCheckSt]	97	1			T19	3		T59	6		T61	1
auto[1]	auto[TokenHashSt]	466	1			T13	1		T19	14		T55	2
auto[1]	auto[FlashRmaSt]	70	1			T19	3		T55	2		T56	1
auto[1]	auto[TokenCheck0St]	18	1			T19	1		T58	1		T60	1
auto[1]	auto[TokenCheck1St]	92	1			T19	3		T56	1		T58	1
auto[1]	auto[TransProgSt]	476	1			T19	4		T55	13		T56	13
auto[1]	auto[PostTransSt]	2607	1			T4	23		T5	6		T13	4
auto[1]	auto[ScrapSt]	46	1			T56	3		T58	1		T59	1
auto[1]	auto[EscalateSt]	1358164	1			T4	10115		T5	588		T13	490
auto[1]	auto[InvalidSt]	6863	1			T4	81		T20	33		T54	4