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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 97.89 95.95 93.31 100.00 98.55 98.76 96.11


Total test records in report: 998
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T814 /workspace/coverage/default/46.lc_ctrl_alert_test.1151358862 Apr 23 01:13:48 PM PDT 24 Apr 23 01:13:50 PM PDT 24 86083197 ps
T815 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1004809843 Apr 23 01:11:34 PM PDT 24 Apr 23 01:11:44 PM PDT 24 1024408168 ps
T816 /workspace/coverage/default/49.lc_ctrl_prog_failure.424403535 Apr 23 01:14:09 PM PDT 24 Apr 23 01:14:13 PM PDT 24 88578051 ps
T79 /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3938313486 Apr 23 01:10:44 PM PDT 24 Apr 23 01:10:47 PM PDT 24 565174084 ps
T817 /workspace/coverage/default/20.lc_ctrl_alert_test.1425621715 Apr 23 01:12:13 PM PDT 24 Apr 23 01:12:15 PM PDT 24 65839738 ps
T818 /workspace/coverage/default/47.lc_ctrl_stress_all.2399005008 Apr 23 01:13:50 PM PDT 24 Apr 23 01:16:38 PM PDT 24 40214102909 ps
T43 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2887169726 Apr 23 01:12:29 PM PDT 24 Apr 23 01:12:30 PM PDT 24 24144578 ps
T819 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3756236236 Apr 23 01:10:34 PM PDT 24 Apr 23 01:10:50 PM PDT 24 1518904257 ps
T820 /workspace/coverage/default/45.lc_ctrl_errors.3240640208 Apr 23 01:13:42 PM PDT 24 Apr 23 01:13:55 PM PDT 24 332135147 ps
T821 /workspace/coverage/default/34.lc_ctrl_sec_mubi.1611389731 Apr 23 01:13:02 PM PDT 24 Apr 23 01:13:13 PM PDT 24 1183247189 ps
T822 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2400261438 Apr 23 01:10:53 PM PDT 24 Apr 23 01:11:14 PM PDT 24 682548358 ps
T823 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1589352607 Apr 23 01:11:42 PM PDT 24 Apr 23 01:11:43 PM PDT 24 34015920 ps
T824 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3068813320 Apr 23 01:12:26 PM PDT 24 Apr 23 01:18:21 PM PDT 24 36435580720 ps
T825 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.33065863 Apr 23 01:13:00 PM PDT 24 Apr 23 01:13:10 PM PDT 24 1341990769 ps
T826 /workspace/coverage/default/24.lc_ctrl_prog_failure.3474985330 Apr 23 01:12:29 PM PDT 24 Apr 23 01:12:32 PM PDT 24 194207877 ps
T827 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3566887025 Apr 23 01:11:01 PM PDT 24 Apr 23 01:11:06 PM PDT 24 494428471 ps
T828 /workspace/coverage/default/35.lc_ctrl_smoke.3841845261 Apr 23 01:13:02 PM PDT 24 Apr 23 01:13:05 PM PDT 24 112567008 ps
T829 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.815859694 Apr 23 01:13:29 PM PDT 24 Apr 23 01:13:42 PM PDT 24 401853905 ps
T830 /workspace/coverage/default/8.lc_ctrl_state_post_trans.1443281542 Apr 23 01:11:08 PM PDT 24 Apr 23 01:11:16 PM PDT 24 245407906 ps
T831 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.771282561 Apr 23 01:10:34 PM PDT 24 Apr 23 01:10:36 PM PDT 24 11985723 ps
T832 /workspace/coverage/default/31.lc_ctrl_sec_mubi.1031586592 Apr 23 01:12:52 PM PDT 24 Apr 23 01:13:07 PM PDT 24 443012177 ps
T833 /workspace/coverage/default/33.lc_ctrl_stress_all.1673588929 Apr 23 01:13:00 PM PDT 24 Apr 23 01:15:36 PM PDT 24 9573621419 ps
T834 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4249101771 Apr 23 01:10:20 PM PDT 24 Apr 23 01:10:25 PM PDT 24 640465765 ps
T835 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3308268451 Apr 23 01:12:03 PM PDT 24 Apr 23 01:12:34 PM PDT 24 1676518572 ps
T836 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2712451778 Apr 23 01:11:27 PM PDT 24 Apr 23 01:11:39 PM PDT 24 213070452 ps
T837 /workspace/coverage/default/49.lc_ctrl_state_post_trans.3190089188 Apr 23 01:13:56 PM PDT 24 Apr 23 01:14:04 PM PDT 24 46951029 ps
T838 /workspace/coverage/default/28.lc_ctrl_jtag_access.1035526455 Apr 23 01:12:48 PM PDT 24 Apr 23 01:12:56 PM PDT 24 283748531 ps
T839 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.137683689 Apr 23 01:13:33 PM PDT 24 Apr 23 01:13:34 PM PDT 24 11410437 ps
T840 /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1488809664 Apr 23 01:10:56 PM PDT 24 Apr 23 01:11:04 PM PDT 24 740355536 ps
T841 /workspace/coverage/default/17.lc_ctrl_jtag_errors.3861345732 Apr 23 01:11:59 PM PDT 24 Apr 23 01:14:23 PM PDT 24 91294981083 ps
T842 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1849994186 Apr 23 01:10:42 PM PDT 24 Apr 23 01:10:59 PM PDT 24 1596460908 ps
T843 /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.642432091 Apr 23 01:11:39 PM PDT 24 Apr 23 01:11:49 PM PDT 24 264869524 ps
T844 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1625284439 Apr 23 01:13:32 PM PDT 24 Apr 23 01:13:52 PM PDT 24 862100115 ps
T845 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1670144266 Apr 23 01:11:48 PM PDT 24 Apr 23 01:11:49 PM PDT 24 31947108 ps
T846 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2526481062 Apr 23 01:12:19 PM PDT 24 Apr 23 01:12:20 PM PDT 24 50739090 ps
T847 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.4026051643 Apr 23 01:10:20 PM PDT 24 Apr 23 01:10:28 PM PDT 24 675286321 ps
T848 /workspace/coverage/default/42.lc_ctrl_errors.3687968994 Apr 23 01:13:30 PM PDT 24 Apr 23 01:13:40 PM PDT 24 725424649 ps
T70 /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3071718082 Apr 23 01:10:37 PM PDT 24 Apr 23 01:10:38 PM PDT 24 14358412 ps
T849 /workspace/coverage/default/5.lc_ctrl_state_failure.400703177 Apr 23 01:10:56 PM PDT 24 Apr 23 01:11:17 PM PDT 24 248864296 ps
T850 /workspace/coverage/default/14.lc_ctrl_prog_failure.1727609135 Apr 23 01:11:42 PM PDT 24 Apr 23 01:11:46 PM PDT 24 110498880 ps
T851 /workspace/coverage/default/4.lc_ctrl_state_failure.1871155642 Apr 23 01:10:45 PM PDT 24 Apr 23 01:11:05 PM PDT 24 855706179 ps
T852 /workspace/coverage/default/46.lc_ctrl_jtag_access.2588572818 Apr 23 01:13:51 PM PDT 24 Apr 23 01:13:58 PM PDT 24 2953779525 ps
T853 /workspace/coverage/default/0.lc_ctrl_state_post_trans.3697534382 Apr 23 01:10:18 PM PDT 24 Apr 23 01:10:22 PM PDT 24 65295980 ps
T854 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.165037708 Apr 23 01:10:52 PM PDT 24 Apr 23 01:11:05 PM PDT 24 523009742 ps
T855 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2074372266 Apr 23 01:10:23 PM PDT 24 Apr 23 01:11:41 PM PDT 24 7973559085 ps
T856 /workspace/coverage/default/26.lc_ctrl_prog_failure.3948353371 Apr 23 01:12:33 PM PDT 24 Apr 23 01:12:37 PM PDT 24 62101571 ps
T857 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1265052357 Apr 23 01:11:38 PM PDT 24 Apr 23 01:11:41 PM PDT 24 344491115 ps
T858 /workspace/coverage/default/41.lc_ctrl_alert_test.4148927687 Apr 23 01:13:33 PM PDT 24 Apr 23 01:13:34 PM PDT 24 60437223 ps
T859 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1208763274 Apr 23 01:11:36 PM PDT 24 Apr 23 01:11:38 PM PDT 24 29882851 ps
T860 /workspace/coverage/default/38.lc_ctrl_prog_failure.2343918128 Apr 23 01:13:15 PM PDT 24 Apr 23 01:13:19 PM PDT 24 209724411 ps
T861 /workspace/coverage/default/34.lc_ctrl_state_failure.997858143 Apr 23 01:13:01 PM PDT 24 Apr 23 01:13:23 PM PDT 24 214152936 ps
T862 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2377619233 Apr 23 01:13:40 PM PDT 24 Apr 23 01:13:50 PM PDT 24 326397736 ps
T863 /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.941775170 Apr 23 01:11:10 PM PDT 24 Apr 23 01:18:08 PM PDT 24 19503859060 ps
T864 /workspace/coverage/default/15.lc_ctrl_jtag_errors.2139418077 Apr 23 01:11:48 PM PDT 24 Apr 23 01:12:32 PM PDT 24 3433529128 ps
T865 /workspace/coverage/default/10.lc_ctrl_stress_all.173898659 Apr 23 01:11:23 PM PDT 24 Apr 23 01:16:55 PM PDT 24 55010837379 ps
T866 /workspace/coverage/default/22.lc_ctrl_sec_mubi.541033923 Apr 23 01:12:20 PM PDT 24 Apr 23 01:12:40 PM PDT 24 2998688304 ps
T867 /workspace/coverage/default/36.lc_ctrl_errors.2311885088 Apr 23 01:13:08 PM PDT 24 Apr 23 01:13:22 PM PDT 24 388789847 ps
T868 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.4105355853 Apr 23 01:10:56 PM PDT 24 Apr 23 01:11:12 PM PDT 24 363985021 ps
T869 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1302292354 Apr 23 01:10:36 PM PDT 24 Apr 23 01:10:52 PM PDT 24 1598731329 ps
T870 /workspace/coverage/default/3.lc_ctrl_security_escalation.1023395856 Apr 23 01:10:45 PM PDT 24 Apr 23 01:10:57 PM PDT 24 1164084963 ps
T871 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3058339772 Apr 23 01:10:34 PM PDT 24 Apr 23 01:10:36 PM PDT 24 94988311 ps
T872 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.478541867 Apr 23 01:10:55 PM PDT 24 Apr 23 01:10:58 PM PDT 24 33568161 ps
T873 /workspace/coverage/default/1.lc_ctrl_jtag_priority.667096113 Apr 23 01:10:26 PM PDT 24 Apr 23 01:10:45 PM PDT 24 1602508602 ps
T112 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.603243930 Apr 23 02:11:20 PM PDT 24 Apr 23 02:11:22 PM PDT 24 49960531 ps
T116 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2156241452 Apr 23 02:11:34 PM PDT 24 Apr 23 02:11:35 PM PDT 24 30600457 ps
T117 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.302937867 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:21 PM PDT 24 1502208379 ps
T107 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3504770875 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:23 PM PDT 24 17259522 ps
T142 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1524553238 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:24 PM PDT 24 189630508 ps
T113 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.379178197 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:15 PM PDT 24 136957214 ps
T114 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2011960021 Apr 23 02:11:19 PM PDT 24 Apr 23 02:11:21 PM PDT 24 229146700 ps
T191 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1595362901 Apr 23 02:11:26 PM PDT 24 Apr 23 02:11:28 PM PDT 24 30437058 ps
T143 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.96534028 Apr 23 02:11:30 PM PDT 24 Apr 23 02:11:35 PM PDT 24 186918296 ps
T874 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.632460882 Apr 23 02:11:38 PM PDT 24 Apr 23 02:11:40 PM PDT 24 14297461 ps
T192 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4181873849 Apr 23 02:11:38 PM PDT 24 Apr 23 02:11:40 PM PDT 24 27425496 ps
T103 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.89980523 Apr 23 02:11:38 PM PDT 24 Apr 23 02:11:40 PM PDT 24 129795215 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3232485174 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 38217359 ps
T104 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1879072181 Apr 23 02:11:37 PM PDT 24 Apr 23 02:11:39 PM PDT 24 143880587 ps
T110 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1687247920 Apr 23 02:11:36 PM PDT 24 Apr 23 02:11:38 PM PDT 24 55767472 ps
T105 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1500002171 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:15 PM PDT 24 274360035 ps
T150 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4120546092 Apr 23 02:11:32 PM PDT 24 Apr 23 02:11:34 PM PDT 24 453110160 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3861994896 Apr 23 02:11:10 PM PDT 24 Apr 23 02:11:16 PM PDT 24 1579521306 ps
T108 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2405660023 Apr 23 02:11:27 PM PDT 24 Apr 23 02:11:30 PM PDT 24 56959705 ps
T109 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.387823983 Apr 23 02:11:28 PM PDT 24 Apr 23 02:11:30 PM PDT 24 44086311 ps
T151 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1208337808 Apr 23 02:11:24 PM PDT 24 Apr 23 02:11:26 PM PDT 24 46249816 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.166076936 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:24 PM PDT 24 75321088 ps
T193 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.824256587 Apr 23 02:11:40 PM PDT 24 Apr 23 02:11:41 PM PDT 24 105597458 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3439585843 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:16 PM PDT 24 79227612 ps
T111 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1787598683 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:16 PM PDT 24 90026861 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3298167668 Apr 23 02:11:15 PM PDT 24 Apr 23 02:11:20 PM PDT 24 451870654 ps
T118 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1174811812 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:15 PM PDT 24 98961211 ps
T194 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3530284831 Apr 23 02:11:26 PM PDT 24 Apr 23 02:11:28 PM PDT 24 43876781 ps
T877 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3372936941 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:33 PM PDT 24 11365747949 ps
T139 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2077301613 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:25 PM PDT 24 1113299336 ps
T179 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.876791202 Apr 23 02:11:43 PM PDT 24 Apr 23 02:11:44 PM PDT 24 22934629 ps
T878 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2263177197 Apr 23 02:11:35 PM PDT 24 Apr 23 02:11:37 PM PDT 24 87629687 ps
T195 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2377111791 Apr 23 02:11:42 PM PDT 24 Apr 23 02:11:45 PM PDT 24 149943591 ps
T119 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.170350387 Apr 23 02:11:23 PM PDT 24 Apr 23 02:11:27 PM PDT 24 78287899 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.357093795 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:12 PM PDT 24 25355323 ps
T121 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3223858633 Apr 23 02:11:34 PM PDT 24 Apr 23 02:11:37 PM PDT 24 291505693 ps
T134 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1452206663 Apr 23 02:11:38 PM PDT 24 Apr 23 02:11:41 PM PDT 24 345666441 ps
T115 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3103605155 Apr 23 02:11:34 PM PDT 24 Apr 23 02:11:37 PM PDT 24 98931919 ps
T180 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3142229667 Apr 23 02:11:39 PM PDT 24 Apr 23 02:11:40 PM PDT 24 23018562 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2652987988 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:25 PM PDT 24 210329029 ps
T131 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2232459809 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:16 PM PDT 24 509910842 ps
T123 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3745002160 Apr 23 02:11:27 PM PDT 24 Apr 23 02:11:30 PM PDT 24 381072926 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2078514176 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:18 PM PDT 24 736269112 ps
T132 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.779873974 Apr 23 02:11:39 PM PDT 24 Apr 23 02:11:43 PM PDT 24 59889542 ps
T882 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3700840911 Apr 23 02:11:32 PM PDT 24 Apr 23 02:11:33 PM PDT 24 42171928 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1820717492 Apr 23 02:11:15 PM PDT 24 Apr 23 02:11:18 PM PDT 24 167054785 ps
T884 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3156625162 Apr 23 02:11:18 PM PDT 24 Apr 23 02:11:20 PM PDT 24 24813159 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1090902801 Apr 23 02:11:18 PM PDT 24 Apr 23 02:11:20 PM PDT 24 55157645 ps
T886 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1652747183 Apr 23 02:11:42 PM PDT 24 Apr 23 02:11:44 PM PDT 24 36078112 ps
T887 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3724631413 Apr 23 02:11:31 PM PDT 24 Apr 23 02:11:32 PM PDT 24 82280478 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1496846900 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:16 PM PDT 24 338672275 ps
T889 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.476387822 Apr 23 02:11:27 PM PDT 24 Apr 23 02:11:43 PM PDT 24 2669875425 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1764765321 Apr 23 02:11:23 PM PDT 24 Apr 23 02:11:36 PM PDT 24 2417577278 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2405945323 Apr 23 02:11:10 PM PDT 24 Apr 23 02:11:15 PM PDT 24 4391481634 ps
T892 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1123077189 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 39919782 ps
T893 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4129961013 Apr 23 02:11:38 PM PDT 24 Apr 23 02:11:41 PM PDT 24 60998237 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.620589595 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:15 PM PDT 24 164027294 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1393819870 Apr 23 02:11:17 PM PDT 24 Apr 23 02:11:19 PM PDT 24 105491657 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1679845750 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:14 PM PDT 24 35969797 ps
T897 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2436534493 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:24 PM PDT 24 33148752 ps
T898 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2260553336 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:41 PM PDT 24 2561799640 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3549162872 Apr 23 02:11:13 PM PDT 24 Apr 23 02:11:15 PM PDT 24 55135436 ps
T900 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1628906817 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:30 PM PDT 24 3966964934 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3466304198 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 54603730 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.787392020 Apr 23 02:11:13 PM PDT 24 Apr 23 02:11:16 PM PDT 24 64535269 ps
T903 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1278024258 Apr 23 02:11:29 PM PDT 24 Apr 23 02:11:33 PM PDT 24 114948569 ps
T904 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.982200218 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:23 PM PDT 24 37704146 ps
T181 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1184446269 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:16 PM PDT 24 14347590 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1906575500 Apr 23 02:11:43 PM PDT 24 Apr 23 02:11:45 PM PDT 24 187281648 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2925159364 Apr 23 02:11:10 PM PDT 24 Apr 23 02:11:12 PM PDT 24 50061272 ps
T906 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4204349839 Apr 23 02:11:18 PM PDT 24 Apr 23 02:11:19 PM PDT 24 15415276 ps
T907 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1610184357 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:12 PM PDT 24 24860085 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1989913663 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:15 PM PDT 24 289806159 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1053865616 Apr 23 02:11:24 PM PDT 24 Apr 23 02:11:25 PM PDT 24 50405641 ps
T138 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4051506418 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 230324799 ps
T910 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1033909733 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:27 PM PDT 24 509790230 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4141815839 Apr 23 02:11:16 PM PDT 24 Apr 23 02:11:27 PM PDT 24 422403843 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3494079854 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:23 PM PDT 24 56975694 ps
T913 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3581307683 Apr 23 02:11:23 PM PDT 24 Apr 23 02:11:25 PM PDT 24 25826514 ps
T182 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2338051028 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:24 PM PDT 24 42275089 ps
T183 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.803905874 Apr 23 02:11:40 PM PDT 24 Apr 23 02:11:41 PM PDT 24 26264787 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2779736522 Apr 23 02:11:19 PM PDT 24 Apr 23 02:11:23 PM PDT 24 103550730 ps
T184 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3022626639 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 34556923 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2180201067 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:15 PM PDT 24 297243368 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1328851972 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:24 PM PDT 24 431992053 ps
T917 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.959155560 Apr 23 02:11:18 PM PDT 24 Apr 23 02:11:20 PM PDT 24 29859567 ps
T918 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.377828522 Apr 23 02:11:13 PM PDT 24 Apr 23 02:11:15 PM PDT 24 53295312 ps
T185 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.585490636 Apr 23 02:11:34 PM PDT 24 Apr 23 02:11:35 PM PDT 24 31085885 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.758628854 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:15 PM PDT 24 178848056 ps
T920 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2667140469 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:23 PM PDT 24 79058657 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.788935734 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:16 PM PDT 24 217368179 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.711589605 Apr 23 02:11:26 PM PDT 24 Apr 23 02:11:27 PM PDT 24 190773026 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3561623763 Apr 23 02:11:07 PM PDT 24 Apr 23 02:11:09 PM PDT 24 33254534 ps
T924 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3061074587 Apr 23 02:11:18 PM PDT 24 Apr 23 02:11:25 PM PDT 24 568396999 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3822009157 Apr 23 02:11:17 PM PDT 24 Apr 23 02:11:22 PM PDT 24 359770326 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1279467350 Apr 23 02:11:15 PM PDT 24 Apr 23 02:11:18 PM PDT 24 62194583 ps
T927 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.199892088 Apr 23 02:11:33 PM PDT 24 Apr 23 02:11:35 PM PDT 24 68056758 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.531303427 Apr 23 02:11:20 PM PDT 24 Apr 23 02:11:23 PM PDT 24 121217941 ps
T128 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2081550317 Apr 23 02:11:32 PM PDT 24 Apr 23 02:11:35 PM PDT 24 447389850 ps
T929 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1384635007 Apr 23 02:11:40 PM PDT 24 Apr 23 02:11:42 PM PDT 24 55648295 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3481830512 Apr 23 02:11:15 PM PDT 24 Apr 23 02:11:27 PM PDT 24 1850573119 ps
T931 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.163278534 Apr 23 02:11:41 PM PDT 24 Apr 23 02:11:43 PM PDT 24 48394504 ps
T140 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1588630468 Apr 23 02:11:26 PM PDT 24 Apr 23 02:11:32 PM PDT 24 185669576 ps
T932 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4072386945 Apr 23 02:11:40 PM PDT 24 Apr 23 02:11:43 PM PDT 24 92364103 ps
T933 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1671163185 Apr 23 02:11:20 PM PDT 24 Apr 23 02:11:21 PM PDT 24 139994572 ps
T141 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4252326015 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:16 PM PDT 24 62497290 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3084718957 Apr 23 02:11:20 PM PDT 24 Apr 23 02:11:23 PM PDT 24 534517575 ps
T935 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1555364305 Apr 23 02:11:26 PM PDT 24 Apr 23 02:11:32 PM PDT 24 143263726 ps
T936 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1252321341 Apr 23 02:11:34 PM PDT 24 Apr 23 02:11:38 PM PDT 24 1374972029 ps
T937 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1640370052 Apr 23 02:11:16 PM PDT 24 Apr 23 02:11:18 PM PDT 24 52795287 ps
T938 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2644857393 Apr 23 02:11:42 PM PDT 24 Apr 23 02:11:44 PM PDT 24 21701974 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.77081231 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 47575860 ps
T186 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1761604564 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:14 PM PDT 24 86710095 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3652895564 Apr 23 02:11:10 PM PDT 24 Apr 23 02:11:11 PM PDT 24 63866274 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1432939816 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:25 PM PDT 24 3378274227 ps
T942 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2745311968 Apr 23 02:11:42 PM PDT 24 Apr 23 02:11:45 PM PDT 24 31246883 ps
T943 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1600867034 Apr 23 02:11:34 PM PDT 24 Apr 23 02:11:35 PM PDT 24 16973200 ps
T944 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2098328143 Apr 23 02:11:38 PM PDT 24 Apr 23 02:11:41 PM PDT 24 128379328 ps
T945 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3551146520 Apr 23 02:11:25 PM PDT 24 Apr 23 02:11:27 PM PDT 24 41519183 ps
T136 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4122596833 Apr 23 02:11:35 PM PDT 24 Apr 23 02:11:38 PM PDT 24 411760979 ps
T946 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1478698477 Apr 23 02:11:17 PM PDT 24 Apr 23 02:11:20 PM PDT 24 332308287 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.861638273 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:15 PM PDT 24 118375167 ps
T948 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.447007338 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 222778162 ps
T949 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1558411467 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 44846900 ps
T950 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2877834668 Apr 23 02:11:27 PM PDT 24 Apr 23 02:11:30 PM PDT 24 104158310 ps
T135 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4144725744 Apr 23 02:11:40 PM PDT 24 Apr 23 02:11:43 PM PDT 24 204572804 ps
T951 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1957643658 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:22 PM PDT 24 35234967 ps
T952 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1082618519 Apr 23 02:11:06 PM PDT 24 Apr 23 02:11:08 PM PDT 24 37329296 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1534574790 Apr 23 02:11:19 PM PDT 24 Apr 23 02:11:23 PM PDT 24 135657738 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3770059219 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:41 PM PDT 24 4961207702 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2509802917 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:24 PM PDT 24 572952871 ps
T187 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3739360218 Apr 23 02:11:23 PM PDT 24 Apr 23 02:11:24 PM PDT 24 110855311 ps
T956 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.75536868 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:13 PM PDT 24 115020374 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2942294771 Apr 23 02:11:10 PM PDT 24 Apr 23 02:11:14 PM PDT 24 145804671 ps
T957 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3899241920 Apr 23 02:11:39 PM PDT 24 Apr 23 02:11:40 PM PDT 24 42242503 ps
T189 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.271139973 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:17 PM PDT 24 60830017 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4265055693 Apr 23 02:11:25 PM PDT 24 Apr 23 02:11:29 PM PDT 24 138409493 ps
T125 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2709016936 Apr 23 02:11:40 PM PDT 24 Apr 23 02:11:44 PM PDT 24 225798686 ps
T959 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1362851638 Apr 23 02:11:35 PM PDT 24 Apr 23 02:11:37 PM PDT 24 67632154 ps
T960 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.448672807 Apr 23 02:11:17 PM PDT 24 Apr 23 02:11:19 PM PDT 24 106257833 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3895374576 Apr 23 02:11:15 PM PDT 24 Apr 23 02:11:19 PM PDT 24 29927562 ps
T962 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3924634221 Apr 23 02:11:24 PM PDT 24 Apr 23 02:11:26 PM PDT 24 30882361 ps
T963 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3091430269 Apr 23 02:11:33 PM PDT 24 Apr 23 02:11:36 PM PDT 24 79927259 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3989850115 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:16 PM PDT 24 113507066 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.713270213 Apr 23 02:11:19 PM PDT 24 Apr 23 02:11:22 PM PDT 24 909016689 ps
T966 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3670604850 Apr 23 02:11:26 PM PDT 24 Apr 23 02:11:32 PM PDT 24 1395890161 ps
T967 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2762077974 Apr 23 02:11:33 PM PDT 24 Apr 23 02:11:34 PM PDT 24 25189108 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2232279861 Apr 23 02:11:25 PM PDT 24 Apr 23 02:11:27 PM PDT 24 124127258 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1880816531 Apr 23 02:11:17 PM PDT 24 Apr 23 02:11:19 PM PDT 24 51444322 ps
T970 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.755053251 Apr 23 02:11:23 PM PDT 24 Apr 23 02:11:26 PM PDT 24 126194510 ps
T188 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2964614094 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:15 PM PDT 24 39992077 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1178219221 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:25 PM PDT 24 64558795 ps
T972 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2969907980 Apr 23 02:11:40 PM PDT 24 Apr 23 02:11:43 PM PDT 24 184525280 ps
T973 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3543708678 Apr 23 02:11:19 PM PDT 24 Apr 23 02:11:22 PM PDT 24 219766937 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4023037549 Apr 23 02:11:13 PM PDT 24 Apr 23 02:11:37 PM PDT 24 3868331772 ps
T133 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1681676044 Apr 23 02:11:24 PM PDT 24 Apr 23 02:11:27 PM PDT 24 205295774 ps
T975 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2975857121 Apr 23 02:11:24 PM PDT 24 Apr 23 02:11:28 PM PDT 24 53333156 ps
T976 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3187420990 Apr 23 02:11:38 PM PDT 24 Apr 23 02:11:40 PM PDT 24 31605604 ps
T977 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2555520682 Apr 23 02:11:35 PM PDT 24 Apr 23 02:11:36 PM PDT 24 35192297 ps
T978 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1982399179 Apr 23 02:11:22 PM PDT 24 Apr 23 02:11:24 PM PDT 24 28735636 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1219835074 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:24 PM PDT 24 18121479 ps
T980 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1124520384 Apr 23 02:11:15 PM PDT 24 Apr 23 02:11:18 PM PDT 24 89524996 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1555591448 Apr 23 02:11:14 PM PDT 24 Apr 23 02:11:17 PM PDT 24 305881425 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2008336712 Apr 23 02:11:11 PM PDT 24 Apr 23 02:11:14 PM PDT 24 172196042 ps
T983 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2577413206 Apr 23 02:11:16 PM PDT 24 Apr 23 02:11:18 PM PDT 24 30346087 ps
T984 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2781748343 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:15 PM PDT 24 75571119 ps
T985 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2693744990 Apr 23 02:11:23 PM PDT 24 Apr 23 02:11:25 PM PDT 24 98310341 ps
T986 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.103970228 Apr 23 02:11:24 PM PDT 24 Apr 23 02:11:28 PM PDT 24 87626872 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2917871681 Apr 23 02:11:20 PM PDT 24 Apr 23 02:11:21 PM PDT 24 205390824 ps
T137 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1734424636 Apr 23 02:11:21 PM PDT 24 Apr 23 02:11:26 PM PDT 24 126646883 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1808582274 Apr 23 02:11:25 PM PDT 24 Apr 23 02:11:27 PM PDT 24 224453501 ps
T989 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.698064495 Apr 23 02:11:26 PM PDT 24 Apr 23 02:11:30 PM PDT 24 1178671190 ps
T190 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2329816309 Apr 23 02:11:12 PM PDT 24 Apr 23 02:11:14 PM PDT 24 27396051 ps
T129 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1845195418 Apr 23 02:11:35 PM PDT 24 Apr 23 02:11:38 PM PDT 24 458723588 ps
T126 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2736022559 Apr 23 02:11:17 PM PDT 24 Apr 23 02:11:21 PM PDT 24 448852033 ps
T990 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1021296933 Apr 23 02:11:10 PM PDT 24 Apr 23 02:11:12 PM PDT 24 103565479 ps
T991 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3137162599 Apr 23 02:11:28 PM PDT 24 Apr 23 02:11:30 PM PDT 24 596253825 ps
T992 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3432035651 Apr 23 02:11:36 PM PDT 24 Apr 23 02:11:40 PM PDT 24 83569668 ps
T993 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3846349091 Apr 23 02:11:35 PM PDT 24 Apr 23 02:11:36 PM PDT 24 78485246 ps
T994 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2197713788 Apr 23 02:11:17 PM PDT 24 Apr 23 02:11:20 PM PDT 24 1119113859 ps
T120 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1337899570 Apr 23 02:11:19 PM PDT 24 Apr 23 02:11:21 PM PDT 24 317626727 ps
T995 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1865917409 Apr 23 02:11:32 PM PDT 24 Apr 23 02:11:35 PM PDT 24 240952724 ps
T996 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2150709565 Apr 23 02:11:19 PM PDT 24 Apr 23 02:11:40 PM PDT 24 2928668389 ps
T997 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1120494651 Apr 23 02:11:29 PM PDT 24 Apr 23 02:11:30 PM PDT 24 25428493 ps
T998 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.639088176 Apr 23 02:11:27 PM PDT 24 Apr 23 02:11:29 PM PDT 24 24862645 ps

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.596266760
Short name T4
Test name
Test status
Simulation time 48056967543 ps
CPU time 428.11 seconds
Started Apr 23 01:13:13 PM PDT 24
Finished Apr 23 01:20:22 PM PDT 24
Peak memory 274356 kb
Host smart-1eec59e6-9fae-49f1-a6ea-52391479eb65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=596266760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.596266760
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.277031156
Short name T19
Test name
Test status
Simulation time 284502787 ps
CPU time 8.56 seconds
Started Apr 23 01:13:47 PM PDT 24
Finished Apr 23 01:13:57 PM PDT 24
Peak memory 217612 kb
Host smart-a7bdc99d-0a1a-442f-83d4-0ceed3e847b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277031156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.277031156
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2739892848
Short name T47
Test name
Test status
Simulation time 271312581 ps
CPU time 9.64 seconds
Started Apr 23 01:11:49 PM PDT 24
Finished Apr 23 01:11:59 PM PDT 24
Peak memory 218392 kb
Host smart-12ce76fa-e524-4f41-864b-b6e3e3d97470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739892848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2739892848
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1251094985
Short name T44
Test name
Test status
Simulation time 55698812106 ps
CPU time 1045.7 seconds
Started Apr 23 01:13:03 PM PDT 24
Finished Apr 23 01:30:29 PM PDT 24
Peak memory 660404 kb
Host smart-788abce1-336c-47d9-9fb3-4ac775ad167a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1251094985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1251094985
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.590267908
Short name T1
Test name
Test status
Simulation time 213225981 ps
CPU time 39.86 seconds
Started Apr 23 01:10:28 PM PDT 24
Finished Apr 23 01:11:09 PM PDT 24
Peak memory 268308 kb
Host smart-00e13ec3-39fe-47c7-8dc3-2e3edad1ebf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590267908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.590267908
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2005424083
Short name T408
Test name
Test status
Simulation time 2905149143 ps
CPU time 11.6 seconds
Started Apr 23 01:11:02 PM PDT 24
Finished Apr 23 01:11:14 PM PDT 24
Peak memory 224520 kb
Host smart-1acdff29-8f10-426c-86f5-156b1e747ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005424083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2005424083
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3902803237
Short name T3
Test name
Test status
Simulation time 25205329 ps
CPU time 1.01 seconds
Started Apr 23 01:13:39 PM PDT 24
Finished Apr 23 01:13:40 PM PDT 24
Peak memory 208244 kb
Host smart-5130b950-f822-464b-96c0-cbedd1f4ece6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902803237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3902803237
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1500002171
Short name T105
Test name
Test status
Simulation time 274360035 ps
CPU time 3.41 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 217532 kb
Host smart-60a58e85-63d6-4875-809c-1445aa8687b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500002171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1500002171
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3842857289
Short name T15
Test name
Test status
Simulation time 377765491 ps
CPU time 10.16 seconds
Started Apr 23 01:13:03 PM PDT 24
Finished Apr 23 01:13:14 PM PDT 24
Peak memory 217592 kb
Host smart-c162d3ce-33a3-4013-9fec-76723a25acca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842857289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3842857289
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.89980523
Short name T103
Test name
Test status
Simulation time 129795215 ps
CPU time 1.94 seconds
Started Apr 23 02:11:38 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 221388 kb
Host smart-f3085da3-f41f-4839-acc0-f6e799e66fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89980523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_e
rr.89980523
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1435058083
Short name T152
Test name
Test status
Simulation time 17132928969 ps
CPU time 149.58 seconds
Started Apr 23 01:10:47 PM PDT 24
Finished Apr 23 01:13:17 PM PDT 24
Peak memory 283392 kb
Host smart-e195b51a-c1b7-458d-bf6b-5523e6251ff7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435058083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1435058083
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3644362703
Short name T7
Test name
Test status
Simulation time 804656163 ps
CPU time 9.34 seconds
Started Apr 23 01:11:41 PM PDT 24
Finished Apr 23 01:11:51 PM PDT 24
Peak memory 209100 kb
Host smart-d5cf9e0a-dd38-45b9-91ab-3552f36ec251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644362703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3644362703
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2077301613
Short name T139
Test name
Test status
Simulation time 1113299336 ps
CPU time 3.54 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 211064 kb
Host smart-5d21d6e8-3d8a-47f4-a25f-24f8762ede67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077301613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2077301613
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.379178197
Short name T113
Test name
Test status
Simulation time 136957214 ps
CPU time 1.68 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 209256 kb
Host smart-99a643b5-d45f-4145-9813-55da90832c1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379178197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.379178197
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2434398975
Short name T10
Test name
Test status
Simulation time 246007366 ps
CPU time 1.57 seconds
Started Apr 23 01:13:01 PM PDT 24
Finished Apr 23 01:13:03 PM PDT 24
Peak memory 209228 kb
Host smart-eb399208-af68-42fd-b492-991f1d5bab69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434398975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2434398975
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2942294771
Short name T122
Test name
Test status
Simulation time 145804671 ps
CPU time 2.77 seconds
Started Apr 23 02:11:10 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 222460 kb
Host smart-23428af7-20a2-4f72-97fc-1507ecb573a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942294771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2942294771
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2340627683
Short name T40
Test name
Test status
Simulation time 907298965 ps
CPU time 13.79 seconds
Started Apr 23 01:13:46 PM PDT 24
Finished Apr 23 01:14:01 PM PDT 24
Peak memory 225652 kb
Host smart-cdf939e1-b35f-4946-926e-d6d99c71877b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340627683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2340627683
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2050970200
Short name T102
Test name
Test status
Simulation time 50359073835 ps
CPU time 849.85 seconds
Started Apr 23 01:12:14 PM PDT 24
Finished Apr 23 01:26:25 PM PDT 24
Peak memory 313940 kb
Host smart-1878ef02-99c2-472d-87ea-62ad3b3153ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2050970200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2050970200
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2709016936
Short name T125
Test name
Test status
Simulation time 225798686 ps
CPU time 2.82 seconds
Started Apr 23 02:11:40 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 222224 kb
Host smart-47330493-73d2-4b7b-a659-5c675b206edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709016936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2709016936
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4122596833
Short name T136
Test name
Test status
Simulation time 411760979 ps
CPU time 2.46 seconds
Started Apr 23 02:11:35 PM PDT 24
Finished Apr 23 02:11:38 PM PDT 24
Peak memory 221788 kb
Host smart-ba2a9cfe-edec-4d27-8475-a71b7d1b8fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122596833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4122596833
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2232459809
Short name T131
Test name
Test status
Simulation time 509910842 ps
CPU time 4.37 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 217500 kb
Host smart-1c7552d8-3632-422b-a044-4622650a55ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232459809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2232459809
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4120546092
Short name T150
Test name
Test status
Simulation time 453110160 ps
CPU time 1.5 seconds
Started Apr 23 02:11:32 PM PDT 24
Finished Apr 23 02:11:34 PM PDT 24
Peak memory 211276 kb
Host smart-3ec2aa29-2b6c-4f7a-ae9e-0c470869fa37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120546092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.4120546092
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2773760753
Short name T87
Test name
Test status
Simulation time 42006323697 ps
CPU time 690.32 seconds
Started Apr 23 01:12:06 PM PDT 24
Finished Apr 23 01:23:37 PM PDT 24
Peak memory 299900 kb
Host smart-00925ed5-cbd8-4a50-9922-d9ed227c5e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2773760753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2773760753
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.4098807473
Short name T52
Test name
Test status
Simulation time 28679009466 ps
CPU time 413.76 seconds
Started Apr 23 01:11:40 PM PDT 24
Finished Apr 23 01:18:34 PM PDT 24
Peak memory 328244 kb
Host smart-b3c96e15-3e09-4ecb-8332-6e5e172b336a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4098807473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.4098807473
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2081550317
Short name T128
Test name
Test status
Simulation time 447389850 ps
CPU time 2.75 seconds
Started Apr 23 02:11:32 PM PDT 24
Finished Apr 23 02:11:35 PM PDT 24
Peak memory 221752 kb
Host smart-72e0b5d1-61ed-49d8-b464-5888ed0a144a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081550317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2081550317
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1845195418
Short name T129
Test name
Test status
Simulation time 458723588 ps
CPU time 3.06 seconds
Started Apr 23 02:11:35 PM PDT 24
Finished Apr 23 02:11:38 PM PDT 24
Peak memory 222188 kb
Host smart-1a2af59a-16c1-4f81-89bc-036e53b70edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845195418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1845195418
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1337899570
Short name T120
Test name
Test status
Simulation time 317626727 ps
CPU time 2.1 seconds
Started Apr 23 02:11:19 PM PDT 24
Finished Apr 23 02:11:21 PM PDT 24
Peak memory 217484 kb
Host smart-698854c7-a789-4a9d-aac7-ff5e0b57597e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337899570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1337899570
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1880858179
Short name T201
Test name
Test status
Simulation time 14086444 ps
CPU time 0.84 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:10:23 PM PDT 24
Peak memory 209040 kb
Host smart-fa0cff5a-b9f9-4f2d-90a6-859aec714ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880858179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1880858179
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3472879756
Short name T198
Test name
Test status
Simulation time 64667652 ps
CPU time 0.9 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:36 PM PDT 24
Peak memory 209040 kb
Host smart-5e53dd0d-5a4a-4ca6-9415-58a351022c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472879756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3472879756
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3071718082
Short name T70
Test name
Test status
Simulation time 14358412 ps
CPU time 0.85 seconds
Started Apr 23 01:10:37 PM PDT 24
Finished Apr 23 01:10:38 PM PDT 24
Peak memory 209004 kb
Host smart-dfe0ec51-7a2f-4600-acb5-e50ac46a1bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071718082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3071718082
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.758628854
Short name T919
Test name
Test status
Simulation time 178848056 ps
CPU time 3.17 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 217596 kb
Host smart-b0c7875b-80e6-452b-adda-c9385bf29978
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758628854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.758628854
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.387823983
Short name T109
Test name
Test status
Simulation time 44086311 ps
CPU time 1.82 seconds
Started Apr 23 02:11:28 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 221688 kb
Host smart-da22140c-336a-4a19-9a16-59a62c65fcd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387823983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.387823983
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2736022559
Short name T126
Test name
Test status
Simulation time 448852033 ps
CPU time 3.8 seconds
Started Apr 23 02:11:17 PM PDT 24
Finished Apr 23 02:11:21 PM PDT 24
Peak memory 217600 kb
Host smart-cf2c0704-242b-411f-9c72-bd5f863131ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736022559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2736022559
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1681676044
Short name T133
Test name
Test status
Simulation time 205295774 ps
CPU time 2.48 seconds
Started Apr 23 02:11:24 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 217492 kb
Host smart-6c7e9844-ef90-4b8b-9c9d-28f843bc8dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681676044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1681676044
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2477491755
Short name T51
Test name
Test status
Simulation time 541182328 ps
CPU time 13.2 seconds
Started Apr 23 01:11:34 PM PDT 24
Finished Apr 23 01:11:48 PM PDT 24
Peak memory 217456 kb
Host smart-25c46714-4350-4ed5-be9f-8e2fc97fbf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477491755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2477491755
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.702865068
Short name T46
Test name
Test status
Simulation time 741199675 ps
CPU time 16.99 seconds
Started Apr 23 01:10:41 PM PDT 24
Finished Apr 23 01:10:59 PM PDT 24
Peak memory 218656 kb
Host smart-8f36791d-47ca-41d4-9f12-6f098d1914f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702865068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.702865068
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.4122775327
Short name T211
Test name
Test status
Simulation time 2383168915 ps
CPU time 29.75 seconds
Started Apr 23 01:11:20 PM PDT 24
Finished Apr 23 01:11:51 PM PDT 24
Peak memory 250572 kb
Host smart-805bb63d-8bb7-44eb-92b8-36cd0fc80f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122775327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4122775327
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3561623763
Short name T923
Test name
Test status
Simulation time 33254534 ps
CPU time 1.15 seconds
Started Apr 23 02:11:07 PM PDT 24
Finished Apr 23 02:11:09 PM PDT 24
Peak memory 209068 kb
Host smart-8d993271-8271-4325-ad79-594e16f5d20f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561623763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3561623763
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.357093795
Short name T879
Test name
Test status
Simulation time 25355323 ps
CPU time 0.94 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:12 PM PDT 24
Peak memory 209700 kb
Host smart-44162769-f54c-464e-9941-5ca6e2701023
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357093795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.357093795
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1174811812
Short name T118
Test name
Test status
Simulation time 98961211 ps
CPU time 1.44 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 217628 kb
Host smart-45150925-bdf0-40d1-89f2-135497342fbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174811812 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1174811812
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1184446269
Short name T181
Test name
Test status
Simulation time 14347590 ps
CPU time 1.08 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 209296 kb
Host smart-699db3fd-0a02-461c-8626-6d45d3047279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184446269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1184446269
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3232485174
Short name T875
Test name
Test status
Simulation time 38217359 ps
CPU time 1.05 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 207892 kb
Host smart-87edc67c-0773-475a-9854-f6ad13dc40f7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232485174 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3232485174
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2405945323
Short name T891
Test name
Test status
Simulation time 4391481634 ps
CPU time 4.61 seconds
Started Apr 23 02:11:10 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 209356 kb
Host smart-8d077e11-8af0-4e3a-ac87-987165a89a74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405945323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2405945323
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1432939816
Short name T941
Test name
Test status
Simulation time 3378274227 ps
CPU time 9.69 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 209336 kb
Host smart-f323cd3f-afd1-4d55-8f11-e2caa489d446
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432939816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1432939816
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1496846900
Short name T888
Test name
Test status
Simulation time 338672275 ps
CPU time 2.03 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 210872 kb
Host smart-b5a22bcd-703d-4f46-a995-276a7cc81c36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496846900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1496846900
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1989913663
Short name T908
Test name
Test status
Simulation time 289806159 ps
CPU time 1.83 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 217648 kb
Host smart-0fde16ab-64f0-43e3-8955-be1f88fa4eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198991
3663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1989913663
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3652895564
Short name T940
Test name
Test status
Simulation time 63866274 ps
CPU time 1.25 seconds
Started Apr 23 02:11:10 PM PDT 24
Finished Apr 23 02:11:11 PM PDT 24
Peak memory 209296 kb
Host smart-69d6d382-fbb0-4407-8017-1ce519295951
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652895564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3652895564
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1082618519
Short name T952
Test name
Test status
Simulation time 37329296 ps
CPU time 1.31 seconds
Started Apr 23 02:11:06 PM PDT 24
Finished Apr 23 02:11:08 PM PDT 24
Peak memory 209352 kb
Host smart-e09e3cd0-2260-497a-b09f-80a1e7727c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082618519 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1082618519
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3549162872
Short name T899
Test name
Test status
Simulation time 55135436 ps
CPU time 0.96 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 209264 kb
Host smart-85869227-67d0-4fc1-b1cf-1003787799d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549162872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3549162872
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2180201067
Short name T915
Test name
Test status
Simulation time 297243368 ps
CPU time 1.57 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 209228 kb
Host smart-2b9bde3c-1c04-43a4-b44d-f34c383f1780
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180201067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2180201067
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1123077189
Short name T892
Test name
Test status
Simulation time 39919782 ps
CPU time 1.77 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 209352 kb
Host smart-f8869ec1-6baa-480a-922e-992196f0fa24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123077189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1123077189
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1679845750
Short name T896
Test name
Test status
Simulation time 35969797 ps
CPU time 1.08 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 210232 kb
Host smart-cc26c20c-2eb2-439d-8543-3b4e7e259223
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679845750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1679845750
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.787392020
Short name T902
Test name
Test status
Simulation time 64535269 ps
CPU time 1.49 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 219564 kb
Host smart-361f95e6-00e4-4094-9691-9fe77ba7deaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787392020 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.787392020
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2329816309
Short name T190
Test name
Test status
Simulation time 27396051 ps
CPU time 0.84 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 209380 kb
Host smart-2c2a0b20-d66f-4c29-9058-52ffdccecc42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329816309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2329816309
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1555591448
Short name T981
Test name
Test status
Simulation time 305881425 ps
CPU time 1.19 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:17 PM PDT 24
Peak memory 209248 kb
Host smart-1d20e15c-e3fe-4ae5-b609-44c473714c52
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555591448 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1555591448
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3861994896
Short name T144
Test name
Test status
Simulation time 1579521306 ps
CPU time 5.04 seconds
Started Apr 23 02:11:10 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 209056 kb
Host smart-ec8caca6-459e-4020-8fa7-9ece94deb59f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861994896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3861994896
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.302937867
Short name T117
Test name
Test status
Simulation time 1502208379 ps
CPU time 7.93 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:21 PM PDT 24
Peak memory 208976 kb
Host smart-42d17231-717f-401f-9a52-fad90f1d2433
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302937867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.302937867
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1021296933
Short name T990
Test name
Test status
Simulation time 103565479 ps
CPU time 1.51 seconds
Started Apr 23 02:11:10 PM PDT 24
Finished Apr 23 02:11:12 PM PDT 24
Peak memory 210732 kb
Host smart-af504365-e7ef-43c8-b5af-c2e6eb380854
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021296933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1021296933
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.861638273
Short name T947
Test name
Test status
Simulation time 118375167 ps
CPU time 3.19 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 218644 kb
Host smart-f24cb1e1-61d8-43eb-a4fb-c4ddb0f0f831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861638
273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.861638273
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.620589595
Short name T894
Test name
Test status
Simulation time 164027294 ps
CPU time 2.55 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 209276 kb
Host smart-145d20cf-3957-4b8b-bcc4-79aa06ade432
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620589595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.620589595
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3466304198
Short name T901
Test name
Test status
Simulation time 54603730 ps
CPU time 1.31 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 209444 kb
Host smart-52cae33c-9b3c-4137-95bb-bc82891d95bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466304198 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3466304198
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.447007338
Short name T948
Test name
Test status
Simulation time 222778162 ps
CPU time 1.27 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 208752 kb
Host smart-23d779f8-f1aa-48f3-bcc2-09038c2f86c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447007338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.447007338
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1787598683
Short name T111
Test name
Test status
Simulation time 90026861 ps
CPU time 3.74 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 217652 kb
Host smart-8491d758-f6e6-4184-afa1-ecae3c03fa75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787598683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1787598683
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4051506418
Short name T138
Test name
Test status
Simulation time 230324799 ps
CPU time 2.61 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 212652 kb
Host smart-c1e065ce-8084-4dd8-8fee-93d19ed1cf1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051506418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4051506418
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3724631413
Short name T887
Test name
Test status
Simulation time 82280478 ps
CPU time 1.16 seconds
Started Apr 23 02:11:31 PM PDT 24
Finished Apr 23 02:11:32 PM PDT 24
Peak memory 218404 kb
Host smart-93d3b93c-c8ed-4fdf-a714-e9e4541ca721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724631413 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3724631413
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3700840911
Short name T882
Test name
Test status
Simulation time 42171928 ps
CPU time 0.99 seconds
Started Apr 23 02:11:32 PM PDT 24
Finished Apr 23 02:11:33 PM PDT 24
Peak memory 209300 kb
Host smart-e05f57e0-1672-4685-9a4b-f663b235b3d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700840911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3700840911
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.199892088
Short name T927
Test name
Test status
Simulation time 68056758 ps
CPU time 1.31 seconds
Started Apr 23 02:11:33 PM PDT 24
Finished Apr 23 02:11:35 PM PDT 24
Peak memory 217692 kb
Host smart-ac972786-986b-46bc-8d32-4b2bd815e09b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199892088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.199892088
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1278024258
Short name T903
Test name
Test status
Simulation time 114948569 ps
CPU time 3.51 seconds
Started Apr 23 02:11:29 PM PDT 24
Finished Apr 23 02:11:33 PM PDT 24
Peak memory 217704 kb
Host smart-9a2f9770-4fea-45ca-a9c7-1069c77b4a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278024258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1278024258
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2156241452
Short name T116
Test name
Test status
Simulation time 30600457 ps
CPU time 1 seconds
Started Apr 23 02:11:34 PM PDT 24
Finished Apr 23 02:11:35 PM PDT 24
Peak memory 217576 kb
Host smart-c6b1e414-95fc-4cec-9a78-adbc8aee69dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156241452 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2156241452
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1120494651
Short name T997
Test name
Test status
Simulation time 25428493 ps
CPU time 0.87 seconds
Started Apr 23 02:11:29 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 209268 kb
Host smart-c1511f22-31ba-48f5-a844-5028729bb232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120494651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1120494651
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1865917409
Short name T995
Test name
Test status
Simulation time 240952724 ps
CPU time 2.85 seconds
Started Apr 23 02:11:32 PM PDT 24
Finished Apr 23 02:11:35 PM PDT 24
Peak memory 217532 kb
Host smart-72a121fa-485c-418e-bf7c-094bfd267b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865917409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1865917409
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2555520682
Short name T977
Test name
Test status
Simulation time 35192297 ps
CPU time 0.92 seconds
Started Apr 23 02:11:35 PM PDT 24
Finished Apr 23 02:11:36 PM PDT 24
Peak memory 217612 kb
Host smart-ad4a2aee-05d5-470a-92f5-6b57f31f85f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555520682 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2555520682
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2762077974
Short name T967
Test name
Test status
Simulation time 25189108 ps
CPU time 0.82 seconds
Started Apr 23 02:11:33 PM PDT 24
Finished Apr 23 02:11:34 PM PDT 24
Peak memory 209252 kb
Host smart-1e41db8a-3c9e-47bf-bc5f-9c1a3155fc6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762077974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2762077974
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4129961013
Short name T893
Test name
Test status
Simulation time 60998237 ps
CPU time 1.59 seconds
Started Apr 23 02:11:38 PM PDT 24
Finished Apr 23 02:11:41 PM PDT 24
Peak memory 209296 kb
Host smart-a20c626a-3ab8-4bee-8a70-18610127a89d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129961013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4129961013
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1252321341
Short name T936
Test name
Test status
Simulation time 1374972029 ps
CPU time 3.16 seconds
Started Apr 23 02:11:34 PM PDT 24
Finished Apr 23 02:11:38 PM PDT 24
Peak memory 217668 kb
Host smart-09ebcbf4-23dc-4e5d-bf7b-10cb97143552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252321341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1252321341
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3846349091
Short name T993
Test name
Test status
Simulation time 78485246 ps
CPU time 1.1 seconds
Started Apr 23 02:11:35 PM PDT 24
Finished Apr 23 02:11:36 PM PDT 24
Peak memory 218720 kb
Host smart-7e35b545-ffb3-41d8-a6e0-3413a4cf92a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846349091 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3846349091
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.585490636
Short name T185
Test name
Test status
Simulation time 31085885 ps
CPU time 0.81 seconds
Started Apr 23 02:11:34 PM PDT 24
Finished Apr 23 02:11:35 PM PDT 24
Peak memory 209236 kb
Host smart-2835ab93-ac78-4edc-b2fa-4026b95c63c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585490636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.585490636
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1600867034
Short name T943
Test name
Test status
Simulation time 16973200 ps
CPU time 1.18 seconds
Started Apr 23 02:11:34 PM PDT 24
Finished Apr 23 02:11:35 PM PDT 24
Peak memory 209468 kb
Host smart-6d3bc895-a246-4276-b874-887ecdbda8fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600867034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1600867034
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3103605155
Short name T115
Test name
Test status
Simulation time 98931919 ps
CPU time 2.98 seconds
Started Apr 23 02:11:34 PM PDT 24
Finished Apr 23 02:11:37 PM PDT 24
Peak memory 217556 kb
Host smart-f9c2b314-29dd-441d-93bd-6ac041b2872c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103605155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3103605155
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1687247920
Short name T110
Test name
Test status
Simulation time 55767472 ps
CPU time 1.21 seconds
Started Apr 23 02:11:36 PM PDT 24
Finished Apr 23 02:11:38 PM PDT 24
Peak memory 219340 kb
Host smart-98a44ea4-28ea-440a-a327-69c02c5198dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687247920 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1687247920
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2263177197
Short name T878
Test name
Test status
Simulation time 87629687 ps
CPU time 0.89 seconds
Started Apr 23 02:11:35 PM PDT 24
Finished Apr 23 02:11:37 PM PDT 24
Peak memory 209412 kb
Host smart-fd332ad2-ee4e-48fd-85c5-fd22603b2b05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263177197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2263177197
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1362851638
Short name T959
Test name
Test status
Simulation time 67632154 ps
CPU time 1.4 seconds
Started Apr 23 02:11:35 PM PDT 24
Finished Apr 23 02:11:37 PM PDT 24
Peak memory 209408 kb
Host smart-3fadd28d-3705-4cc8-90d3-5a3b581bcecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362851638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1362851638
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3432035651
Short name T992
Test name
Test status
Simulation time 83569668 ps
CPU time 3.24 seconds
Started Apr 23 02:11:36 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 217556 kb
Host smart-e0d384c3-e045-4f08-8f30-ffa9e7ffc45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432035651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3432035651
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3223858633
Short name T121
Test name
Test status
Simulation time 291505693 ps
CPU time 3.2 seconds
Started Apr 23 02:11:34 PM PDT 24
Finished Apr 23 02:11:37 PM PDT 24
Peak memory 217520 kb
Host smart-6e7f5b82-2b67-4e61-9f53-20e31727fc68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223858633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3223858633
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1879072181
Short name T104
Test name
Test status
Simulation time 143880587 ps
CPU time 1.17 seconds
Started Apr 23 02:11:37 PM PDT 24
Finished Apr 23 02:11:39 PM PDT 24
Peak memory 218660 kb
Host smart-a89d2b6e-c121-4545-aa59-5fcb75c632d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879072181 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1879072181
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.632460882
Short name T874
Test name
Test status
Simulation time 14297461 ps
CPU time 0.85 seconds
Started Apr 23 02:11:38 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 209344 kb
Host smart-8906d78a-3a2f-4a31-b46c-69b37bead8cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632460882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.632460882
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3899241920
Short name T957
Test name
Test status
Simulation time 42242503 ps
CPU time 0.96 seconds
Started Apr 23 02:11:39 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 209340 kb
Host smart-84c3b25c-73fa-4104-a783-696e7d85e040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899241920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3899241920
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3091430269
Short name T963
Test name
Test status
Simulation time 79927259 ps
CPU time 1.56 seconds
Started Apr 23 02:11:33 PM PDT 24
Finished Apr 23 02:11:36 PM PDT 24
Peak memory 217560 kb
Host smart-e04eac49-4217-4b76-8d26-afae7f6e994b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091430269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3091430269
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1452206663
Short name T134
Test name
Test status
Simulation time 345666441 ps
CPU time 1.81 seconds
Started Apr 23 02:11:38 PM PDT 24
Finished Apr 23 02:11:41 PM PDT 24
Peak memory 217460 kb
Host smart-2305a9ba-6de8-4a0d-ab85-f49c397185e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452206663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1452206663
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.163278534
Short name T931
Test name
Test status
Simulation time 48394504 ps
CPU time 1.22 seconds
Started Apr 23 02:11:41 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 217704 kb
Host smart-66b98268-bbd6-4292-a7f7-e62fea5193b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163278534 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.163278534
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4181873849
Short name T192
Test name
Test status
Simulation time 27425496 ps
CPU time 0.87 seconds
Started Apr 23 02:11:38 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 209268 kb
Host smart-2e074ef1-c00a-4760-a749-5693cc90a0c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181873849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.4181873849
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1652747183
Short name T886
Test name
Test status
Simulation time 36078112 ps
CPU time 1.71 seconds
Started Apr 23 02:11:42 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 209388 kb
Host smart-605a9d08-5719-49be-b1b7-a10577b1f4e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652747183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1652747183
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2098328143
Short name T944
Test name
Test status
Simulation time 128379328 ps
CPU time 2.79 seconds
Started Apr 23 02:11:38 PM PDT 24
Finished Apr 23 02:11:41 PM PDT 24
Peak memory 217544 kb
Host smart-6ee544d1-9c8b-4949-ab39-a70168957d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098328143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2098328143
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1384635007
Short name T929
Test name
Test status
Simulation time 55648295 ps
CPU time 1.34 seconds
Started Apr 23 02:11:40 PM PDT 24
Finished Apr 23 02:11:42 PM PDT 24
Peak memory 219324 kb
Host smart-448d4514-6fe8-42b6-ad83-de6b58c0a524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384635007 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1384635007
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.803905874
Short name T183
Test name
Test status
Simulation time 26264787 ps
CPU time 1.05 seconds
Started Apr 23 02:11:40 PM PDT 24
Finished Apr 23 02:11:41 PM PDT 24
Peak memory 217276 kb
Host smart-434afa64-27d2-4564-89ad-b0ff180392dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803905874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.803905874
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.824256587
Short name T193
Test name
Test status
Simulation time 105597458 ps
CPU time 1.2 seconds
Started Apr 23 02:11:40 PM PDT 24
Finished Apr 23 02:11:41 PM PDT 24
Peak memory 209368 kb
Host smart-4d63792b-00e0-4eb3-99cc-f01fe090231a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824256587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.824256587
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.779873974
Short name T132
Test name
Test status
Simulation time 59889542 ps
CPU time 2.43 seconds
Started Apr 23 02:11:39 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 217564 kb
Host smart-7ebcdb25-de3c-41a2-ab5e-6c3737004646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779873974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.779873974
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3187420990
Short name T976
Test name
Test status
Simulation time 31605604 ps
CPU time 0.94 seconds
Started Apr 23 02:11:38 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 217600 kb
Host smart-e25e3bd0-12e3-404a-9763-2939a8d41c4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187420990 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3187420990
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3142229667
Short name T180
Test name
Test status
Simulation time 23018562 ps
CPU time 0.95 seconds
Started Apr 23 02:11:39 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 209348 kb
Host smart-5fff4bc8-3586-4597-a173-8a595f17e995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142229667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3142229667
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2644857393
Short name T938
Test name
Test status
Simulation time 21701974 ps
CPU time 1.2 seconds
Started Apr 23 02:11:42 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 211368 kb
Host smart-32236981-31b3-4fa4-b5b1-417ee3e1388a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644857393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2644857393
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2969907980
Short name T972
Test name
Test status
Simulation time 184525280 ps
CPU time 2.39 seconds
Started Apr 23 02:11:40 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 217588 kb
Host smart-56e887f6-e0dd-4c1c-a5b0-565bf68f72f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969907980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2969907980
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4144725744
Short name T135
Test name
Test status
Simulation time 204572804 ps
CPU time 1.91 seconds
Started Apr 23 02:11:40 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 221736 kb
Host smart-ba842acc-8772-43ee-b105-666a97d88ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144725744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.4144725744
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2745311968
Short name T942
Test name
Test status
Simulation time 31246883 ps
CPU time 2.34 seconds
Started Apr 23 02:11:42 PM PDT 24
Finished Apr 23 02:11:45 PM PDT 24
Peak memory 219572 kb
Host smart-e140cfb8-ab20-41eb-8441-ff325ccb53da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745311968 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2745311968
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.876791202
Short name T179
Test name
Test status
Simulation time 22934629 ps
CPU time 0.83 seconds
Started Apr 23 02:11:43 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 209256 kb
Host smart-932ac1e2-8c8a-44f2-8405-2e860539271d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876791202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.876791202
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2377111791
Short name T195
Test name
Test status
Simulation time 149943591 ps
CPU time 1.51 seconds
Started Apr 23 02:11:42 PM PDT 24
Finished Apr 23 02:11:45 PM PDT 24
Peak memory 211252 kb
Host smart-85074df4-a4be-4a47-ba7c-c79e36fa9a2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377111791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2377111791
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4072386945
Short name T932
Test name
Test status
Simulation time 92364103 ps
CPU time 1.68 seconds
Started Apr 23 02:11:40 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 217596 kb
Host smart-34cab8d2-aff3-4703-9277-bf6abe80fb27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072386945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4072386945
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1906575500
Short name T124
Test name
Test status
Simulation time 187281648 ps
CPU time 1.83 seconds
Started Apr 23 02:11:43 PM PDT 24
Finished Apr 23 02:11:45 PM PDT 24
Peak memory 221616 kb
Host smart-1867f64e-81ef-400a-b8e2-b3f06539afd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906575500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1906575500
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.271139973
Short name T189
Test name
Test status
Simulation time 60830017 ps
CPU time 1.19 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:17 PM PDT 24
Peak memory 209380 kb
Host smart-1e2a70f0-df5d-4add-b4ef-4fe2757e926f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271139973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.271139973
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2925159364
Short name T905
Test name
Test status
Simulation time 50061272 ps
CPU time 1.79 seconds
Started Apr 23 02:11:10 PM PDT 24
Finished Apr 23 02:11:12 PM PDT 24
Peak memory 208596 kb
Host smart-0f474b0d-ac4a-4d1d-9b9f-c5b3703603ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925159364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2925159364
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2964614094
Short name T188
Test name
Test status
Simulation time 39992077 ps
CPU time 1.07 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 218256 kb
Host smart-caa40d4a-f5c8-42b9-9d21-06cb16d46c00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964614094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2964614094
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1558411467
Short name T949
Test name
Test status
Simulation time 44846900 ps
CPU time 1.88 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 219844 kb
Host smart-f99fe900-491f-4e7d-8416-897bbcfabdcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558411467 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1558411467
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3022626639
Short name T184
Test name
Test status
Simulation time 34556923 ps
CPU time 0.83 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 208952 kb
Host smart-6d95860e-a60f-4d06-a9c1-72959d8594b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022626639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3022626639
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3439585843
Short name T876
Test name
Test status
Simulation time 79227612 ps
CPU time 1.25 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 209248 kb
Host smart-9ffa5026-c08a-488e-ab63-97175b54bd7b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439585843 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3439585843
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.788935734
Short name T921
Test name
Test status
Simulation time 217368179 ps
CPU time 2.64 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 209088 kb
Host smart-f7d3807a-118e-483e-bec1-facfe3dbc5e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788935734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.788935734
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3372936941
Short name T877
Test name
Test status
Simulation time 11365747949 ps
CPU time 20.4 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:33 PM PDT 24
Peak memory 209364 kb
Host smart-726a80fb-fa97-4b88-b4fc-5f9fffd11214
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372936941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3372936941
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.77081231
Short name T939
Test name
Test status
Simulation time 47575860 ps
CPU time 1.84 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 210684 kb
Host smart-cf2c39c4-5b05-4c2d-8d59-a44a177f2103
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77081231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.77081231
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.75536868
Short name T956
Test name
Test status
Simulation time 115020374 ps
CPU time 2.08 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:13 PM PDT 24
Peak memory 222292 kb
Host smart-3e130157-923f-45fe-aa94-fb8e60dfca16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755368
68 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.75536868
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4252326015
Short name T141
Test name
Test status
Simulation time 62497290 ps
CPU time 2.11 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 209280 kb
Host smart-83d841b0-3b91-4fd3-9f2b-79ec725a2502
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252326015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.4252326015
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3989850115
Short name T964
Test name
Test status
Simulation time 113507066 ps
CPU time 1.37 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:16 PM PDT 24
Peak memory 209300 kb
Host smart-66f4b65e-2610-4373-afa5-18de541be49f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989850115 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3989850115
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.377828522
Short name T918
Test name
Test status
Simulation time 53295312 ps
CPU time 0.99 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 209372 kb
Host smart-021394ab-56f8-43b3-9d93-198f92b97a52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377828522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.377828522
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1761604564
Short name T186
Test name
Test status
Simulation time 86710095 ps
CPU time 1.28 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 209348 kb
Host smart-8be24e1d-8f68-4e09-881f-fe4c312280dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761604564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1761604564
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1640370052
Short name T937
Test name
Test status
Simulation time 52795287 ps
CPU time 1.43 seconds
Started Apr 23 02:11:16 PM PDT 24
Finished Apr 23 02:11:18 PM PDT 24
Peak memory 209180 kb
Host smart-ccd69f09-ce18-431f-bf7d-874962015a73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640370052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1640370052
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2577413206
Short name T983
Test name
Test status
Simulation time 30346087 ps
CPU time 1.03 seconds
Started Apr 23 02:11:16 PM PDT 24
Finished Apr 23 02:11:18 PM PDT 24
Peak memory 211336 kb
Host smart-864e938e-b34f-4fb3-819d-481aa0e7e4ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577413206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2577413206
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3895374576
Short name T961
Test name
Test status
Simulation time 29927562 ps
CPU time 2.38 seconds
Started Apr 23 02:11:15 PM PDT 24
Finished Apr 23 02:11:19 PM PDT 24
Peak memory 217612 kb
Host smart-4ba963b9-3142-48d7-92fb-328de52c1d40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895374576 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3895374576
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1610184357
Short name T907
Test name
Test status
Simulation time 24860085 ps
CPU time 0.85 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:12 PM PDT 24
Peak memory 209212 kb
Host smart-f9c01632-a83d-48bf-967d-8c06845e0fc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610184357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1610184357
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1671163185
Short name T933
Test name
Test status
Simulation time 139994572 ps
CPU time 0.98 seconds
Started Apr 23 02:11:20 PM PDT 24
Finished Apr 23 02:11:21 PM PDT 24
Peak memory 209280 kb
Host smart-bf29257c-8ab2-48db-87f9-36e8ef55e3a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671163185 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1671163185
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3481830512
Short name T930
Test name
Test status
Simulation time 1850573119 ps
CPU time 11.23 seconds
Started Apr 23 02:11:15 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 208972 kb
Host smart-71338d08-4956-49c0-b3c5-3aff835bd5ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481830512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3481830512
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4023037549
Short name T974
Test name
Test status
Simulation time 3868331772 ps
CPU time 22.22 seconds
Started Apr 23 02:11:13 PM PDT 24
Finished Apr 23 02:11:37 PM PDT 24
Peak memory 209372 kb
Host smart-dbcf0f23-de43-45c9-b00d-ec5422c94cf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023037549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4023037549
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2008336712
Short name T982
Test name
Test status
Simulation time 172196042 ps
CPU time 1.27 seconds
Started Apr 23 02:11:11 PM PDT 24
Finished Apr 23 02:11:14 PM PDT 24
Peak memory 210700 kb
Host smart-c28b4750-e76a-46a8-aa58-f97aa96e22c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008336712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2008336712
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3543708678
Short name T973
Test name
Test status
Simulation time 219766937 ps
CPU time 2.81 seconds
Started Apr 23 02:11:19 PM PDT 24
Finished Apr 23 02:11:22 PM PDT 24
Peak memory 222404 kb
Host smart-381ca86b-6abc-43d3-bfdf-2ad026a26a30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354370
8678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3543708678
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2078514176
Short name T881
Test name
Test status
Simulation time 736269112 ps
CPU time 2.49 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:18 PM PDT 24
Peak memory 209252 kb
Host smart-a3bf9f29-943e-4223-9e7b-61cbd239c1cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078514176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2078514176
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1393819870
Short name T895
Test name
Test status
Simulation time 105491657 ps
CPU time 2.01 seconds
Started Apr 23 02:11:17 PM PDT 24
Finished Apr 23 02:11:19 PM PDT 24
Peak memory 211452 kb
Host smart-16c1b587-788f-4f61-89d9-f7f72e461098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393819870 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1393819870
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.603243930
Short name T112
Test name
Test status
Simulation time 49960531 ps
CPU time 2.02 seconds
Started Apr 23 02:11:20 PM PDT 24
Finished Apr 23 02:11:22 PM PDT 24
Peak memory 209500 kb
Host smart-5a8dc483-91f1-43e8-a04f-a4ba2fc6e2ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603243930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.603243930
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3156625162
Short name T884
Test name
Test status
Simulation time 24813159 ps
CPU time 1.46 seconds
Started Apr 23 02:11:18 PM PDT 24
Finished Apr 23 02:11:20 PM PDT 24
Peak memory 217752 kb
Host smart-972b16d0-678d-4d15-84a3-6918817bf190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156625162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3156625162
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3298167668
Short name T127
Test name
Test status
Simulation time 451870654 ps
CPU time 3.95 seconds
Started Apr 23 02:11:15 PM PDT 24
Finished Apr 23 02:11:20 PM PDT 24
Peak memory 217632 kb
Host smart-6a15441d-c273-40a9-b970-69d2498d6081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298167668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3298167668
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4204349839
Short name T906
Test name
Test status
Simulation time 15415276 ps
CPU time 1.17 seconds
Started Apr 23 02:11:18 PM PDT 24
Finished Apr 23 02:11:19 PM PDT 24
Peak memory 209248 kb
Host smart-83f7e82c-1999-4fe0-a59c-bd87fa39bc10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204349839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4204349839
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.448672807
Short name T960
Test name
Test status
Simulation time 106257833 ps
CPU time 1.5 seconds
Started Apr 23 02:11:17 PM PDT 24
Finished Apr 23 02:11:19 PM PDT 24
Peak memory 208516 kb
Host smart-a4bc6826-11ef-4b22-9177-f3bedaaa6e4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448672807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.448672807
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2338051028
Short name T182
Test name
Test status
Simulation time 42275089 ps
CPU time 0.88 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 209432 kb
Host smart-9f0a8cd6-e54d-4e99-aac9-734c63c8fc3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338051028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2338051028
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1124520384
Short name T980
Test name
Test status
Simulation time 89524996 ps
CPU time 1.4 seconds
Started Apr 23 02:11:15 PM PDT 24
Finished Apr 23 02:11:18 PM PDT 24
Peak memory 217572 kb
Host smart-59c2ddeb-c35b-4e55-aa11-f4e88a71f197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124520384 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1124520384
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.959155560
Short name T917
Test name
Test status
Simulation time 29859567 ps
CPU time 0.96 seconds
Started Apr 23 02:11:18 PM PDT 24
Finished Apr 23 02:11:20 PM PDT 24
Peak memory 208800 kb
Host smart-eacd6be3-184f-4fb5-a543-fc746b51baba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959155560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.959155560
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1178219221
Short name T971
Test name
Test status
Simulation time 64558795 ps
CPU time 2.06 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 208940 kb
Host smart-9c6ab9bd-c5ea-497d-9d55-046a058bf2ff
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178219221 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1178219221
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3770059219
Short name T954
Test name
Test status
Simulation time 4961207702 ps
CPU time 25.56 seconds
Started Apr 23 02:11:14 PM PDT 24
Finished Apr 23 02:11:41 PM PDT 24
Peak memory 209312 kb
Host smart-da35b38c-30bb-4725-9e65-5f6c5cbbbbd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770059219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3770059219
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4141815839
Short name T911
Test name
Test status
Simulation time 422403843 ps
CPU time 10.46 seconds
Started Apr 23 02:11:16 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 207996 kb
Host smart-c76932f0-8ac9-4eff-8718-1de18d354efc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141815839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4141815839
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2781748343
Short name T984
Test name
Test status
Simulation time 75571119 ps
CPU time 1.33 seconds
Started Apr 23 02:11:12 PM PDT 24
Finished Apr 23 02:11:15 PM PDT 24
Peak memory 210672 kb
Host smart-7b32c1b3-5d35-4143-aea7-599a8811c612
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781748343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2781748343
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.713270213
Short name T965
Test name
Test status
Simulation time 909016689 ps
CPU time 2.83 seconds
Started Apr 23 02:11:19 PM PDT 24
Finished Apr 23 02:11:22 PM PDT 24
Peak memory 218768 kb
Host smart-1b77e796-3694-4718-9ef9-55aaeca40863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713270
213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.713270213
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1820717492
Short name T883
Test name
Test status
Simulation time 167054785 ps
CPU time 1.75 seconds
Started Apr 23 02:11:15 PM PDT 24
Finished Apr 23 02:11:18 PM PDT 24
Peak memory 209160 kb
Host smart-d231adc0-9294-475d-9125-65b989b339f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820717492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1820717492
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1279467350
Short name T926
Test name
Test status
Simulation time 62194583 ps
CPU time 1.36 seconds
Started Apr 23 02:11:15 PM PDT 24
Finished Apr 23 02:11:18 PM PDT 24
Peak memory 217504 kb
Host smart-6a1f5494-2c44-48f8-aaab-fe116a559eeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279467350 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1279467350
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1880816531
Short name T969
Test name
Test status
Simulation time 51444322 ps
CPU time 1.01 seconds
Started Apr 23 02:11:17 PM PDT 24
Finished Apr 23 02:11:19 PM PDT 24
Peak memory 209408 kb
Host smart-023ac5d0-204f-42a8-9ae3-9e90716011cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880816531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1880816531
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1478698477
Short name T946
Test name
Test status
Simulation time 332308287 ps
CPU time 2.49 seconds
Started Apr 23 02:11:17 PM PDT 24
Finished Apr 23 02:11:20 PM PDT 24
Peak memory 218188 kb
Host smart-b9434864-4a8c-4c91-bcc4-f69c5bb0925e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478698477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1478698477
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3504770875
Short name T107
Test name
Test status
Simulation time 17259522 ps
CPU time 0.96 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 217672 kb
Host smart-090160c3-ab4a-4c86-97dc-d64eb5710f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504770875 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3504770875
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1090902801
Short name T885
Test name
Test status
Simulation time 55157645 ps
CPU time 1.09 seconds
Started Apr 23 02:11:18 PM PDT 24
Finished Apr 23 02:11:20 PM PDT 24
Peak memory 209276 kb
Host smart-052e5a8f-18f6-4304-ab94-fed89a28e13e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090902801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1090902801
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2667140469
Short name T920
Test name
Test status
Simulation time 79058657 ps
CPU time 1.29 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 209276 kb
Host smart-c1b15157-2cdc-4b66-b74a-45236a17f7a8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667140469 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2667140469
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3822009157
Short name T925
Test name
Test status
Simulation time 359770326 ps
CPU time 3.8 seconds
Started Apr 23 02:11:17 PM PDT 24
Finished Apr 23 02:11:22 PM PDT 24
Peak memory 209048 kb
Host smart-e798b96c-0b4c-491d-a210-f545d1aa577d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822009157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3822009157
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2260553336
Short name T898
Test name
Test status
Simulation time 2561799640 ps
CPU time 19.88 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:41 PM PDT 24
Peak memory 208512 kb
Host smart-7ca94266-cfb3-4043-acbd-54cceb6413c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260553336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2260553336
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3084718957
Short name T934
Test name
Test status
Simulation time 534517575 ps
CPU time 2.1 seconds
Started Apr 23 02:11:20 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 210848 kb
Host smart-e641df52-ec37-4f96-bf85-6161d52280de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084718957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3084718957
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1808582274
Short name T988
Test name
Test status
Simulation time 224453501 ps
CPU time 1.74 seconds
Started Apr 23 02:11:25 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 217700 kb
Host smart-32a8f6d8-11bf-4cee-aadc-ddaeb93c2ff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180858
2274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1808582274
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1957643658
Short name T951
Test name
Test status
Simulation time 35234967 ps
CPU time 1.01 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:22 PM PDT 24
Peak memory 209264 kb
Host smart-22d6f1fa-fd90-45b8-a45b-217318ab52de
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957643658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1957643658
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3530284831
Short name T194
Test name
Test status
Simulation time 43876781 ps
CPU time 1.52 seconds
Started Apr 23 02:11:26 PM PDT 24
Finished Apr 23 02:11:28 PM PDT 24
Peak memory 209388 kb
Host smart-5f2b3dcc-84b1-43f5-a7a1-46a6dbf3cce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530284831 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3530284831
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1982399179
Short name T978
Test name
Test status
Simulation time 28735636 ps
CPU time 1.17 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 209380 kb
Host smart-913f0728-6bc4-4cac-8a38-3574f989e38e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982399179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1982399179
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3061074587
Short name T924
Test name
Test status
Simulation time 568396999 ps
CPU time 5.93 seconds
Started Apr 23 02:11:18 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 217808 kb
Host smart-325ea3d8-57ef-4eb8-9044-99db4dd0b8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061074587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3061074587
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.166076936
Short name T130
Test name
Test status
Simulation time 75321088 ps
CPU time 1.39 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 217544 kb
Host smart-f019afff-bbf7-4240-b66d-4e8e9766450f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166076936 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.166076936
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3551146520
Short name T945
Test name
Test status
Simulation time 41519183 ps
CPU time 0.84 seconds
Started Apr 23 02:11:25 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 208868 kb
Host smart-6be4d0fb-5c98-46f9-9083-236296ed119f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551146520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3551146520
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2652987988
Short name T880
Test name
Test status
Simulation time 210329029 ps
CPU time 1.91 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 209236 kb
Host smart-cd4dadf3-b476-4138-abd6-4ee57ef15075
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652987988 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2652987988
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1033909733
Short name T910
Test name
Test status
Simulation time 509790230 ps
CPU time 5.23 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 208456 kb
Host smart-4cdbc687-2a7d-4679-a9d4-25da9b9156ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033909733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1033909733
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1628906817
Short name T900
Test name
Test status
Simulation time 3966964934 ps
CPU time 8.64 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 209348 kb
Host smart-25c05014-0016-4208-b0d2-c2c6cf31e872
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628906817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1628906817
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2779736522
Short name T914
Test name
Test status
Simulation time 103550730 ps
CPU time 3.02 seconds
Started Apr 23 02:11:19 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 210828 kb
Host smart-421654c9-7bc9-4445-a207-5e6248b1251f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779736522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2779736522
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.755053251
Short name T970
Test name
Test status
Simulation time 126194510 ps
CPU time 2.4 seconds
Started Apr 23 02:11:23 PM PDT 24
Finished Apr 23 02:11:26 PM PDT 24
Peak memory 218924 kb
Host smart-e9ea16b5-ee1d-4f85-8f54-f5e8ce9edca7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755053
251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.755053251
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2509802917
Short name T955
Test name
Test status
Simulation time 572952871 ps
CPU time 1.5 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 209260 kb
Host smart-470f0b21-6a3d-4a20-bed6-b95de58de70f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509802917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2509802917
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3494079854
Short name T912
Test name
Test status
Simulation time 56975694 ps
CPU time 1.18 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 209344 kb
Host smart-5b99ecaf-e7cd-4578-87a0-f1e01f3e5135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494079854 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3494079854
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2011960021
Short name T114
Test name
Test status
Simulation time 229146700 ps
CPU time 1.43 seconds
Started Apr 23 02:11:19 PM PDT 24
Finished Apr 23 02:11:21 PM PDT 24
Peak memory 209376 kb
Host smart-408327cf-0adf-4d5b-a1b9-14788ed8f41d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011960021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2011960021
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.531303427
Short name T928
Test name
Test status
Simulation time 121217941 ps
CPU time 2.67 seconds
Started Apr 23 02:11:20 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 217640 kb
Host smart-609d83ff-42ac-491b-a39b-563894fab057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531303427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.531303427
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.170350387
Short name T119
Test name
Test status
Simulation time 78287899 ps
CPU time 3.27 seconds
Started Apr 23 02:11:23 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 217564 kb
Host smart-de30444a-202c-408d-a72a-3ebb3d75ea73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170350387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.170350387
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2693744990
Short name T985
Test name
Test status
Simulation time 98310341 ps
CPU time 1.31 seconds
Started Apr 23 02:11:23 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 217704 kb
Host smart-0f133605-06c9-4e74-b225-9f40c5f5dc24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693744990 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2693744990
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.982200218
Short name T904
Test name
Test status
Simulation time 37704146 ps
CPU time 0.82 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 208856 kb
Host smart-5a812558-4a2d-464a-b9ce-56ca29eb7d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982200218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.982200218
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1328851972
Short name T916
Test name
Test status
Simulation time 431992053 ps
CPU time 1.19 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 209216 kb
Host smart-0e8a5656-eed1-4cab-b014-3715a4c54bd1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328851972 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1328851972
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3670604850
Short name T966
Test name
Test status
Simulation time 1395890161 ps
CPU time 5.26 seconds
Started Apr 23 02:11:26 PM PDT 24
Finished Apr 23 02:11:32 PM PDT 24
Peak memory 209148 kb
Host smart-f23454a1-535f-46ea-aa41-16091ba7f974
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670604850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3670604850
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2150709565
Short name T996
Test name
Test status
Simulation time 2928668389 ps
CPU time 20.39 seconds
Started Apr 23 02:11:19 PM PDT 24
Finished Apr 23 02:11:40 PM PDT 24
Peak memory 209316 kb
Host smart-b2da75cc-c533-4a8e-9861-e33520896969
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150709565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2150709565
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2197713788
Short name T994
Test name
Test status
Simulation time 1119113859 ps
CPU time 2.22 seconds
Started Apr 23 02:11:17 PM PDT 24
Finished Apr 23 02:11:20 PM PDT 24
Peak memory 210860 kb
Host smart-267a4531-bf20-4b0e-b3c2-bd1213ee2433
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197713788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2197713788
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.103970228
Short name T986
Test name
Test status
Simulation time 87626872 ps
CPU time 2.89 seconds
Started Apr 23 02:11:24 PM PDT 24
Finished Apr 23 02:11:28 PM PDT 24
Peak memory 217640 kb
Host smart-d4276523-c421-4fd7-8e31-7e54d99f49c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103970
228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.103970228
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1534574790
Short name T953
Test name
Test status
Simulation time 135657738 ps
CPU time 3.61 seconds
Started Apr 23 02:11:19 PM PDT 24
Finished Apr 23 02:11:23 PM PDT 24
Peak memory 209264 kb
Host smart-83ed281c-d5ba-4eef-ac84-dc7aa98dbdc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534574790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1534574790
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2917871681
Short name T987
Test name
Test status
Simulation time 205390824 ps
CPU time 1.35 seconds
Started Apr 23 02:11:20 PM PDT 24
Finished Apr 23 02:11:21 PM PDT 24
Peak memory 209448 kb
Host smart-22aa270d-17a9-4e54-bfaa-7fcead660592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917871681 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2917871681
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1208337808
Short name T151
Test name
Test status
Simulation time 46249816 ps
CPU time 1.39 seconds
Started Apr 23 02:11:24 PM PDT 24
Finished Apr 23 02:11:26 PM PDT 24
Peak memory 211224 kb
Host smart-9d4f66c6-a3fd-4a80-ab0f-2e462ffe15df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208337808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1208337808
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2975857121
Short name T975
Test name
Test status
Simulation time 53333156 ps
CPU time 3.25 seconds
Started Apr 23 02:11:24 PM PDT 24
Finished Apr 23 02:11:28 PM PDT 24
Peak memory 217700 kb
Host smart-40034cd8-fb74-461c-863b-63da39c954b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975857121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2975857121
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1734424636
Short name T137
Test name
Test status
Simulation time 126646883 ps
CPU time 3.82 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:26 PM PDT 24
Peak memory 217500 kb
Host smart-964780ef-25d1-4047-a197-b22a59ab81b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734424636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1734424636
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1219835074
Short name T979
Test name
Test status
Simulation time 18121479 ps
CPU time 1.24 seconds
Started Apr 23 02:11:21 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 217612 kb
Host smart-0d8f2aa8-693e-48e5-8c44-d12090cabdf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219835074 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1219835074
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3739360218
Short name T187
Test name
Test status
Simulation time 110855311 ps
CPU time 0.88 seconds
Started Apr 23 02:11:23 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 209212 kb
Host smart-f2f797ae-3eea-4d01-bb87-cb8cf2c97ef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739360218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3739360218
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2232279861
Short name T968
Test name
Test status
Simulation time 124127258 ps
CPU time 1.54 seconds
Started Apr 23 02:11:25 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 209300 kb
Host smart-668ec4ec-8565-442e-90d3-d79962cd1e59
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232279861 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2232279861
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.698064495
Short name T989
Test name
Test status
Simulation time 1178671190 ps
CPU time 3.05 seconds
Started Apr 23 02:11:26 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 209080 kb
Host smart-ffca6a83-bccf-4631-9e0a-e450b9d1c4af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698064495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.698064495
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.476387822
Short name T889
Test name
Test status
Simulation time 2669875425 ps
CPU time 14.85 seconds
Started Apr 23 02:11:27 PM PDT 24
Finished Apr 23 02:11:43 PM PDT 24
Peak memory 209332 kb
Host smart-7baea905-a5af-40ff-add2-8ef61e7e5ba9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476387822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.476387822
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.96534028
Short name T143
Test name
Test status
Simulation time 186918296 ps
CPU time 4.52 seconds
Started Apr 23 02:11:30 PM PDT 24
Finished Apr 23 02:11:35 PM PDT 24
Peak memory 210980 kb
Host smart-dbf086a1-b2d8-439b-a26c-897e89b1122a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96534028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.96534028
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3745002160
Short name T123
Test name
Test status
Simulation time 381072926 ps
CPU time 2.94 seconds
Started Apr 23 02:11:27 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 217972 kb
Host smart-beb885b7-3cf1-4d6f-b474-993838270530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374500
2160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3745002160
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1524553238
Short name T142
Test name
Test status
Simulation time 189630508 ps
CPU time 1.16 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 209288 kb
Host smart-b5e0a8c6-46fb-4fd9-8262-7d9de3981d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524553238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1524553238
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1595362901
Short name T191
Test name
Test status
Simulation time 30437058 ps
CPU time 1.44 seconds
Started Apr 23 02:11:26 PM PDT 24
Finished Apr 23 02:11:28 PM PDT 24
Peak memory 209384 kb
Host smart-0b65def8-c6f3-4939-9557-290d842190f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595362901 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1595362901
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3924634221
Short name T962
Test name
Test status
Simulation time 30882361 ps
CPU time 1.16 seconds
Started Apr 23 02:11:24 PM PDT 24
Finished Apr 23 02:11:26 PM PDT 24
Peak memory 209268 kb
Host smart-7d01acd7-1ec5-4d23-9346-cdbafba51159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924634221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3924634221
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1555364305
Short name T935
Test name
Test status
Simulation time 143263726 ps
CPU time 5.23 seconds
Started Apr 23 02:11:26 PM PDT 24
Finished Apr 23 02:11:32 PM PDT 24
Peak memory 217648 kb
Host smart-562cba94-33c2-480d-965f-910f4e23a2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555364305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1555364305
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2405660023
Short name T108
Test name
Test status
Simulation time 56959705 ps
CPU time 2.58 seconds
Started Apr 23 02:11:27 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 217616 kb
Host smart-a7a754e6-7858-41c6-b0a7-445e6fe3fa2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405660023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2405660023
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.639088176
Short name T998
Test name
Test status
Simulation time 24862645 ps
CPU time 1.21 seconds
Started Apr 23 02:11:27 PM PDT 24
Finished Apr 23 02:11:29 PM PDT 24
Peak memory 218856 kb
Host smart-22b153ce-5cd3-4e8f-a111-5ad05aab821e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639088176 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.639088176
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1053865616
Short name T909
Test name
Test status
Simulation time 50405641 ps
CPU time 0.8 seconds
Started Apr 23 02:11:24 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 209240 kb
Host smart-5b1d3a19-55fd-4802-b83a-2e7a7de5b676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053865616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1053865616
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.711589605
Short name T922
Test name
Test status
Simulation time 190773026 ps
CPU time 1.27 seconds
Started Apr 23 02:11:26 PM PDT 24
Finished Apr 23 02:11:27 PM PDT 24
Peak memory 209204 kb
Host smart-b8eae62e-38cd-4dc6-aeaa-c20c30055d60
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711589605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.711589605
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1588630468
Short name T140
Test name
Test status
Simulation time 185669576 ps
CPU time 5.27 seconds
Started Apr 23 02:11:26 PM PDT 24
Finished Apr 23 02:11:32 PM PDT 24
Peak memory 209056 kb
Host smart-12b437bb-044e-4735-8f93-18995027d358
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588630468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1588630468
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1764765321
Short name T890
Test name
Test status
Simulation time 2417577278 ps
CPU time 12.16 seconds
Started Apr 23 02:11:23 PM PDT 24
Finished Apr 23 02:11:36 PM PDT 24
Peak memory 209316 kb
Host smart-1a01dfbd-d357-4f70-b093-52f7ba2b559d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764765321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1764765321
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2877834668
Short name T950
Test name
Test status
Simulation time 104158310 ps
CPU time 2.89 seconds
Started Apr 23 02:11:27 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 217652 kb
Host smart-b96b68ec-8d6f-4707-a888-a59d9d73d029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287783
4668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2877834668
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2436534493
Short name T897
Test name
Test status
Simulation time 33148752 ps
CPU time 1.5 seconds
Started Apr 23 02:11:22 PM PDT 24
Finished Apr 23 02:11:24 PM PDT 24
Peak memory 209260 kb
Host smart-3324f78e-5e89-471c-925c-c577d43c8f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436534493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2436534493
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3581307683
Short name T913
Test name
Test status
Simulation time 25826514 ps
CPU time 1.33 seconds
Started Apr 23 02:11:23 PM PDT 24
Finished Apr 23 02:11:25 PM PDT 24
Peak memory 209300 kb
Host smart-a8a69747-b285-4870-a3a2-a43a80d42c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581307683 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3581307683
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3137162599
Short name T991
Test name
Test status
Simulation time 596253825 ps
CPU time 1.31 seconds
Started Apr 23 02:11:28 PM PDT 24
Finished Apr 23 02:11:30 PM PDT 24
Peak memory 209360 kb
Host smart-f3f2037a-7a4c-46b8-990c-7245f22063eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137162599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3137162599
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4265055693
Short name T958
Test name
Test status
Simulation time 138409493 ps
CPU time 3.71 seconds
Started Apr 23 02:11:25 PM PDT 24
Finished Apr 23 02:11:29 PM PDT 24
Peak memory 218384 kb
Host smart-2a0aceb6-721c-4dc8-8a6a-0326b1b73e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265055693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4265055693
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2469678629
Short name T67
Test name
Test status
Simulation time 119888097 ps
CPU time 1.23 seconds
Started Apr 23 01:10:25 PM PDT 24
Finished Apr 23 01:10:27 PM PDT 24
Peak memory 209152 kb
Host smart-7a1aa2d8-28d4-4677-a5ba-801f3c4490c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469678629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2469678629
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.4274176186
Short name T538
Test name
Test status
Simulation time 2512097861 ps
CPU time 14.33 seconds
Started Apr 23 01:10:23 PM PDT 24
Finished Apr 23 01:10:38 PM PDT 24
Peak memory 217572 kb
Host smart-ef41ce42-f962-42e1-8916-568f546c8430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274176186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.4274176186
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.247257778
Short name T27
Test name
Test status
Simulation time 561074351 ps
CPU time 11.61 seconds
Started Apr 23 01:10:22 PM PDT 24
Finished Apr 23 01:10:35 PM PDT 24
Peak memory 216716 kb
Host smart-e7e64825-697a-4658-882a-820f66f4539f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247257778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.247257778
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.711439741
Short name T328
Test name
Test status
Simulation time 6142972455 ps
CPU time 40.33 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:11:02 PM PDT 24
Peak memory 225576 kb
Host smart-0529d076-269a-4281-a3ea-5c3e2ed3357f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711439741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.711439741
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3388746728
Short name T571
Test name
Test status
Simulation time 10903351170 ps
CPU time 14.56 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:10:36 PM PDT 24
Peak memory 217472 kb
Host smart-338ba2a1-fc99-40a8-9f8e-3741c8b3d957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388746728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
388746728
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3118777647
Short name T781
Test name
Test status
Simulation time 62750408 ps
CPU time 1.96 seconds
Started Apr 23 01:10:22 PM PDT 24
Finished Apr 23 01:10:25 PM PDT 24
Peak memory 217580 kb
Host smart-ca306450-cfc0-4eb2-a478-3984075a8a88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118777647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3118777647
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3274826900
Short name T562
Test name
Test status
Simulation time 1259052806 ps
CPU time 31.26 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:10:53 PM PDT 24
Peak memory 212940 kb
Host smart-bd1bb43f-7bf6-4e5e-a89c-e406e464dd2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274826900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3274826900
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4249101771
Short name T834
Test name
Test status
Simulation time 640465765 ps
CPU time 4.47 seconds
Started Apr 23 01:10:20 PM PDT 24
Finished Apr 23 01:10:25 PM PDT 24
Peak memory 212816 kb
Host smart-259947a2-09f6-4feb-8733-d19622a68d1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249101771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
4249101771
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2074372266
Short name T855
Test name
Test status
Simulation time 7973559085 ps
CPU time 76.6 seconds
Started Apr 23 01:10:23 PM PDT 24
Finished Apr 23 01:11:41 PM PDT 24
Peak memory 283396 kb
Host smart-6b1f2397-fdde-431e-849a-4111a13a0ff1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074372266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2074372266
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.431453859
Short name T393
Test name
Test status
Simulation time 376259090 ps
CPU time 11.65 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:10:34 PM PDT 24
Peak memory 250528 kb
Host smart-0ffd3fe2-7064-46a0-94ce-ced4e56dc8b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431453859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.431453859
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.138963928
Short name T14
Test name
Test status
Simulation time 69155403 ps
CPU time 3.06 seconds
Started Apr 23 01:10:17 PM PDT 24
Finished Apr 23 01:10:21 PM PDT 24
Peak memory 217548 kb
Host smart-c52775b7-a4bd-4edd-9e28-ef317e5b1f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138963928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.138963928
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3655612072
Short name T400
Test name
Test status
Simulation time 240248775 ps
CPU time 13.72 seconds
Started Apr 23 01:10:23 PM PDT 24
Finished Apr 23 01:10:37 PM PDT 24
Peak memory 217472 kb
Host smart-1b3d37e2-8610-4039-aa89-2faaebc7c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655612072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3655612072
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2240607934
Short name T84
Test name
Test status
Simulation time 469849791 ps
CPU time 25.65 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:10:48 PM PDT 24
Peak memory 268532 kb
Host smart-7834a501-aafd-4d8d-865f-197e1ec2edda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240607934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2240607934
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2867893636
Short name T36
Test name
Test status
Simulation time 1901469571 ps
CPU time 12.93 seconds
Started Apr 23 01:10:20 PM PDT 24
Finished Apr 23 01:10:34 PM PDT 24
Peak memory 225644 kb
Host smart-8a9d0100-d099-4b2e-a977-96b29f98756a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867893636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2867893636
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2853869480
Short name T207
Test name
Test status
Simulation time 402343028 ps
CPU time 16.74 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:10:39 PM PDT 24
Peak memory 217576 kb
Host smart-4e1ae404-82b6-4eb1-bb05-7de507eb7100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853869480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2853869480
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.4026051643
Short name T847
Test name
Test status
Simulation time 675286321 ps
CPU time 8.03 seconds
Started Apr 23 01:10:20 PM PDT 24
Finished Apr 23 01:10:28 PM PDT 24
Peak memory 217564 kb
Host smart-d7b5e29d-0426-476f-a154-15d485e545e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026051643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.4
026051643
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2212396915
Short name T667
Test name
Test status
Simulation time 3650183868 ps
CPU time 15.94 seconds
Started Apr 23 01:10:20 PM PDT 24
Finished Apr 23 01:10:36 PM PDT 24
Peak memory 217676 kb
Host smart-97379842-32f0-491f-88b4-e45ac4fe5d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212396915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2212396915
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1792283875
Short name T77
Test name
Test status
Simulation time 49697889 ps
CPU time 2.7 seconds
Started Apr 23 01:10:17 PM PDT 24
Finished Apr 23 01:10:20 PM PDT 24
Peak memory 213568 kb
Host smart-5e92f6e2-81a7-4e40-94e7-b16908e0c118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792283875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1792283875
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2481236014
Short name T743
Test name
Test status
Simulation time 175132883 ps
CPU time 24.01 seconds
Started Apr 23 01:10:18 PM PDT 24
Finished Apr 23 01:10:42 PM PDT 24
Peak memory 250644 kb
Host smart-98fe5e17-449a-491b-a85c-5dd6cddd1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481236014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2481236014
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3697534382
Short name T853
Test name
Test status
Simulation time 65295980 ps
CPU time 3.76 seconds
Started Apr 23 01:10:18 PM PDT 24
Finished Apr 23 01:10:22 PM PDT 24
Peak memory 221936 kb
Host smart-dfecb167-fdbb-42d0-8dec-0d4a5a249a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697534382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3697534382
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.502453551
Short name T741
Test name
Test status
Simulation time 3045398735 ps
CPU time 35.46 seconds
Started Apr 23 01:10:21 PM PDT 24
Finished Apr 23 01:10:57 PM PDT 24
Peak memory 250588 kb
Host smart-c6f11781-959a-4c50-b99c-3bcad702c3eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502453551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.502453551
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3307040245
Short name T784
Test name
Test status
Simulation time 40977758 ps
CPU time 0.92 seconds
Started Apr 23 01:10:17 PM PDT 24
Finished Apr 23 01:10:19 PM PDT 24
Peak memory 208468 kb
Host smart-18796166-aa04-48ef-89d4-07f05b691f63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307040245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3307040245
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4161308128
Short name T552
Test name
Test status
Simulation time 37875180 ps
CPU time 1.59 seconds
Started Apr 23 01:10:29 PM PDT 24
Finished Apr 23 01:10:32 PM PDT 24
Peak memory 209184 kb
Host smart-de4c37c1-6ebb-497a-a5c8-8cffea02810e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161308128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4161308128
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.771282561
Short name T831
Test name
Test status
Simulation time 11985723 ps
CPU time 0.98 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:36 PM PDT 24
Peak memory 209084 kb
Host smart-ec695600-1c3d-48b5-8068-17dc6b1f58b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771282561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.771282561
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1949356894
Short name T242
Test name
Test status
Simulation time 911265223 ps
CPU time 7.95 seconds
Started Apr 23 01:10:28 PM PDT 24
Finished Apr 23 01:10:37 PM PDT 24
Peak memory 225104 kb
Host smart-0a2ecc6e-5159-439b-b117-c444813a3304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949356894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1949356894
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.692599156
Short name T196
Test name
Test status
Simulation time 1046205328 ps
CPU time 1.8 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:36 PM PDT 24
Peak memory 209092 kb
Host smart-a4a97a1e-a420-4f8f-98e4-ae73ac429a4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692599156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.692599156
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3246494736
Short name T45
Test name
Test status
Simulation time 1354306102 ps
CPU time 30.77 seconds
Started Apr 23 01:10:25 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 217524 kb
Host smart-d8ecd201-5394-4038-835b-255ac9dfdd5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246494736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3246494736
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.667096113
Short name T873
Test name
Test status
Simulation time 1602508602 ps
CPU time 19.34 seconds
Started Apr 23 01:10:26 PM PDT 24
Finished Apr 23 01:10:45 PM PDT 24
Peak memory 217368 kb
Host smart-251d23c3-7c5f-4ba8-bdd7-926a040c2492
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667096113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.667096113
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1779570653
Short name T258
Test name
Test status
Simulation time 183001427 ps
CPU time 3.37 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:38 PM PDT 24
Peak memory 217444 kb
Host smart-b131b380-b13b-433b-aba3-243775807740
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779570653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1779570653
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1544248395
Short name T232
Test name
Test status
Simulation time 1335778664 ps
CPU time 36.24 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:11:11 PM PDT 24
Peak memory 212924 kb
Host smart-6f007f9d-6109-4c16-b4a9-fa9be3c77579
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544248395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1544248395
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1159770877
Short name T716
Test name
Test status
Simulation time 592958403 ps
CPU time 5.2 seconds
Started Apr 23 01:10:26 PM PDT 24
Finished Apr 23 01:10:32 PM PDT 24
Peak memory 212768 kb
Host smart-0afb99f8-6b68-4082-bea1-f5305ac5a6ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159770877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1159770877
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.54078111
Short name T299
Test name
Test status
Simulation time 2144837557 ps
CPU time 50.33 seconds
Started Apr 23 01:10:29 PM PDT 24
Finished Apr 23 01:11:20 PM PDT 24
Peak memory 266896 kb
Host smart-02ab924a-6b2c-4f6b-a3b8-51e4a7756f90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54078111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
state_failure.54078111
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3865727764
Short name T398
Test name
Test status
Simulation time 1545638734 ps
CPU time 13.1 seconds
Started Apr 23 01:10:24 PM PDT 24
Finished Apr 23 01:10:38 PM PDT 24
Peak memory 250508 kb
Host smart-804d0348-a8b3-4719-ba48-3448c4b4204b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865727764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3865727764
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.577423100
Short name T726
Test name
Test status
Simulation time 234666137 ps
CPU time 2.93 seconds
Started Apr 23 01:10:24 PM PDT 24
Finished Apr 23 01:10:28 PM PDT 24
Peak memory 217468 kb
Host smart-62c24b82-1e37-4884-8095-b4da2005431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577423100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.577423100
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.214815691
Short name T469
Test name
Test status
Simulation time 1312257302 ps
CPU time 12.85 seconds
Started Apr 23 01:10:30 PM PDT 24
Finished Apr 23 01:10:43 PM PDT 24
Peak memory 217312 kb
Host smart-3a054727-f053-4cbd-b59c-1a49c5eb5a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214815691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.214815691
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1865263751
Short name T666
Test name
Test status
Simulation time 259481413 ps
CPU time 14.1 seconds
Started Apr 23 01:10:29 PM PDT 24
Finished Apr 23 01:10:44 PM PDT 24
Peak memory 225688 kb
Host smart-580bc992-5e26-4073-b23a-c238ba3410d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865263751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1865263751
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.891647737
Short name T89
Test name
Test status
Simulation time 200100666 ps
CPU time 10.46 seconds
Started Apr 23 01:10:28 PM PDT 24
Finished Apr 23 01:10:40 PM PDT 24
Peak memory 217628 kb
Host smart-6328e54e-617f-4410-8627-7c97099c2099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891647737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.891647737
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3503895074
Short name T502
Test name
Test status
Simulation time 543500030 ps
CPU time 8.95 seconds
Started Apr 23 01:10:30 PM PDT 24
Finished Apr 23 01:10:40 PM PDT 24
Peak memory 217476 kb
Host smart-1346b05a-54d9-42ef-b3a0-67992706cb5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503895074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
503895074
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2853350654
Short name T525
Test name
Test status
Simulation time 1460761170 ps
CPU time 9.74 seconds
Started Apr 23 01:10:27 PM PDT 24
Finished Apr 23 01:10:37 PM PDT 24
Peak memory 217612 kb
Host smart-2118035a-16a8-4fb8-a6a5-26dc4e46da4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853350654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2853350654
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1266794388
Short name T267
Test name
Test status
Simulation time 68536293 ps
CPU time 1.68 seconds
Started Apr 23 01:10:25 PM PDT 24
Finished Apr 23 01:10:27 PM PDT 24
Peak memory 212984 kb
Host smart-bfa77db5-a848-47cd-92fc-4acba883e040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266794388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1266794388
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.484858708
Short name T86
Test name
Test status
Simulation time 1410294378 ps
CPU time 22.31 seconds
Started Apr 23 01:10:25 PM PDT 24
Finished Apr 23 01:10:48 PM PDT 24
Peak memory 250604 kb
Host smart-0e2ec8f6-aec6-42d5-a7a0-230b93a2c370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484858708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.484858708
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4076425267
Short name T379
Test name
Test status
Simulation time 91401437 ps
CPU time 8.43 seconds
Started Apr 23 01:10:25 PM PDT 24
Finished Apr 23 01:10:34 PM PDT 24
Peak memory 250628 kb
Host smart-27f79235-c575-4ea6-8b1a-fd18d62b88af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076425267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4076425267
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1375300463
Short name T494
Test name
Test status
Simulation time 16487631265 ps
CPU time 329.47 seconds
Started Apr 23 01:10:30 PM PDT 24
Finished Apr 23 01:16:00 PM PDT 24
Peak memory 219508 kb
Host smart-2020c5a3-41d0-4e2e-959e-3712eacc9263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375300463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1375300463
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3058339772
Short name T871
Test name
Test status
Simulation time 94988311 ps
CPU time 0.8 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:36 PM PDT 24
Peak memory 208140 kb
Host smart-e8bec971-414e-4f4f-9e26-64ef7b2270f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058339772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3058339772
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1127199456
Short name T280
Test name
Test status
Simulation time 73394494 ps
CPU time 0.9 seconds
Started Apr 23 01:11:32 PM PDT 24
Finished Apr 23 01:11:34 PM PDT 24
Peak memory 209228 kb
Host smart-99e4a8ca-56ee-450d-a358-797aa1a56de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127199456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1127199456
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2988481647
Short name T313
Test name
Test status
Simulation time 441880683 ps
CPU time 9.47 seconds
Started Apr 23 01:11:25 PM PDT 24
Finished Apr 23 01:11:35 PM PDT 24
Peak memory 217488 kb
Host smart-04bdf792-d92d-4a03-8226-75b0fc990520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988481647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2988481647
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1941225362
Short name T720
Test name
Test status
Simulation time 958244268 ps
CPU time 5.26 seconds
Started Apr 23 01:11:25 PM PDT 24
Finished Apr 23 01:11:31 PM PDT 24
Peak memory 216576 kb
Host smart-0904d82f-ffa3-467e-a95f-cac7f98d327c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941225362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1941225362
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3461184637
Short name T273
Test name
Test status
Simulation time 6743578889 ps
CPU time 31.67 seconds
Started Apr 23 01:11:29 PM PDT 24
Finished Apr 23 01:12:01 PM PDT 24
Peak memory 217948 kb
Host smart-65f2aca8-71c5-41d5-8ee9-915c7721cfdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461184637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3461184637
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4048852260
Short name T593
Test name
Test status
Simulation time 319062312 ps
CPU time 5.8 seconds
Started Apr 23 01:11:22 PM PDT 24
Finished Apr 23 01:11:28 PM PDT 24
Peak memory 217496 kb
Host smart-f05ab673-4b29-46af-a871-e385cda2a0f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048852260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4048852260
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1499999210
Short name T80
Test name
Test status
Simulation time 632678562 ps
CPU time 5.37 seconds
Started Apr 23 01:11:25 PM PDT 24
Finished Apr 23 01:11:31 PM PDT 24
Peak memory 212936 kb
Host smart-b4aa4b09-acda-4dfe-8dfc-5cfb348f4876
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499999210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1499999210
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2737645655
Short name T361
Test name
Test status
Simulation time 48612310895 ps
CPU time 110.94 seconds
Started Apr 23 01:11:29 PM PDT 24
Finished Apr 23 01:13:21 PM PDT 24
Peak memory 269392 kb
Host smart-b9fe51d6-224b-4568-918e-9042de080ee4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737645655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2737645655
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.519627125
Short name T380
Test name
Test status
Simulation time 941570635 ps
CPU time 19.22 seconds
Started Apr 23 01:11:23 PM PDT 24
Finished Apr 23 01:11:43 PM PDT 24
Peak memory 250536 kb
Host smart-3b59781c-9e03-4b84-ac03-127458e36eed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519627125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.519627125
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3943661702
Short name T813
Test name
Test status
Simulation time 48295743 ps
CPU time 1.71 seconds
Started Apr 23 01:11:27 PM PDT 24
Finished Apr 23 01:11:30 PM PDT 24
Peak memory 217584 kb
Host smart-c754aef0-8263-4b7d-91c7-4930f6fd7b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943661702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3943661702
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1956084677
Short name T804
Test name
Test status
Simulation time 1855417051 ps
CPU time 14.13 seconds
Started Apr 23 01:11:23 PM PDT 24
Finished Apr 23 01:11:38 PM PDT 24
Peak memory 225684 kb
Host smart-b27c95e9-9eae-4955-80d6-f1b99b3342cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956084677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1956084677
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2712451778
Short name T836
Test name
Test status
Simulation time 213070452 ps
CPU time 10.39 seconds
Started Apr 23 01:11:27 PM PDT 24
Finished Apr 23 01:11:39 PM PDT 24
Peak memory 217612 kb
Host smart-559086b2-0964-402a-b56f-0c8645460092
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712451778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2712451778
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2064817425
Short name T497
Test name
Test status
Simulation time 1439011353 ps
CPU time 11.66 seconds
Started Apr 23 01:11:24 PM PDT 24
Finished Apr 23 01:11:36 PM PDT 24
Peak memory 217516 kb
Host smart-d93a50a1-a26d-4420-a6c9-40f618a4d892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064817425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2064817425
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3112321858
Short name T512
Test name
Test status
Simulation time 1042951199 ps
CPU time 7.95 seconds
Started Apr 23 01:11:23 PM PDT 24
Finished Apr 23 01:11:32 PM PDT 24
Peak memory 217592 kb
Host smart-b4b351ee-fb6a-47ad-aca8-746fb3734bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112321858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3112321858
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1428508492
Short name T587
Test name
Test status
Simulation time 147579700 ps
CPU time 8.67 seconds
Started Apr 23 01:11:25 PM PDT 24
Finished Apr 23 01:11:34 PM PDT 24
Peak memory 217308 kb
Host smart-e7e0f37e-b6e4-44cd-9a82-c1434737ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428508492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1428508492
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2931620659
Short name T156
Test name
Test status
Simulation time 55772421 ps
CPU time 9.04 seconds
Started Apr 23 01:11:21 PM PDT 24
Finished Apr 23 01:11:30 PM PDT 24
Peak memory 250576 kb
Host smart-58e8f445-2f87-4e36-b58e-44789a8f710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931620659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2931620659
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.173898659
Short name T865
Test name
Test status
Simulation time 55010837379 ps
CPU time 331.07 seconds
Started Apr 23 01:11:23 PM PDT 24
Finished Apr 23 01:16:55 PM PDT 24
Peak memory 268540 kb
Host smart-b8e7e622-3fb1-4b36-b05c-79c7cace13f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173898659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.173898659
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3702478805
Short name T733
Test name
Test status
Simulation time 12502542 ps
CPU time 1.04 seconds
Started Apr 23 01:11:21 PM PDT 24
Finished Apr 23 01:11:23 PM PDT 24
Peak memory 211128 kb
Host smart-85e06198-af75-4c5e-9ddf-797c57b8a6b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702478805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3702478805
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3720263058
Short name T669
Test name
Test status
Simulation time 59093587 ps
CPU time 0.98 seconds
Started Apr 23 01:11:30 PM PDT 24
Finished Apr 23 01:11:32 PM PDT 24
Peak memory 209248 kb
Host smart-42ab1d06-af25-46dc-a6d0-cbfbcd2563d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720263058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3720263058
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1630545830
Short name T53
Test name
Test status
Simulation time 293278294 ps
CPU time 9.96 seconds
Started Apr 23 01:11:26 PM PDT 24
Finished Apr 23 01:11:37 PM PDT 24
Peak memory 217404 kb
Host smart-91a3b992-0b45-459c-aa0c-4e2cbae92c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630545830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1630545830
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3425170495
Short name T170
Test name
Test status
Simulation time 919774073 ps
CPU time 12.57 seconds
Started Apr 23 01:11:37 PM PDT 24
Finished Apr 23 01:11:50 PM PDT 24
Peak memory 209088 kb
Host smart-c905978e-7c56-4d02-87e8-f86cd6b9611e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425170495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3425170495
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2615021238
Short name T715
Test name
Test status
Simulation time 5865290143 ps
CPU time 84.09 seconds
Started Apr 23 01:11:32 PM PDT 24
Finished Apr 23 01:12:57 PM PDT 24
Peak memory 218188 kb
Host smart-679fdb3a-10cc-4f9b-8e6f-766ffa99acbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615021238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2615021238
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.642741713
Short name T221
Test name
Test status
Simulation time 760055922 ps
CPU time 12.06 seconds
Started Apr 23 01:11:26 PM PDT 24
Finished Apr 23 01:11:39 PM PDT 24
Peak memory 217544 kb
Host smart-963e6974-5874-4a30-a922-7ebff3a506d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642741713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.642741713
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3494510005
Short name T389
Test name
Test status
Simulation time 973515795 ps
CPU time 13.5 seconds
Started Apr 23 01:11:27 PM PDT 24
Finished Apr 23 01:11:41 PM PDT 24
Peak memory 213472 kb
Host smart-a27e0fa9-15db-45fb-bbd7-8c911bca2270
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494510005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3494510005
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.589105182
Short name T739
Test name
Test status
Simulation time 959314671 ps
CPU time 41.4 seconds
Started Apr 23 01:11:27 PM PDT 24
Finished Apr 23 01:12:09 PM PDT 24
Peak memory 250576 kb
Host smart-87c44dea-cda5-4f03-912f-9d5c4d04d956
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589105182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.589105182
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.201303185
Short name T100
Test name
Test status
Simulation time 333719038 ps
CPU time 13.22 seconds
Started Apr 23 01:11:26 PM PDT 24
Finished Apr 23 01:11:40 PM PDT 24
Peak memory 243584 kb
Host smart-9e93c7a4-5f1a-4acc-8139-5c229539f10a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201303185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.201303185
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1656172287
Short name T527
Test name
Test status
Simulation time 162262963 ps
CPU time 1.96 seconds
Started Apr 23 01:11:26 PM PDT 24
Finished Apr 23 01:11:29 PM PDT 24
Peak memory 217492 kb
Host smart-0395641f-d6fc-428f-8a0d-ee64fca703ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656172287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1656172287
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.806106943
Short name T292
Test name
Test status
Simulation time 557569776 ps
CPU time 15.43 seconds
Started Apr 23 01:11:44 PM PDT 24
Finished Apr 23 01:12:00 PM PDT 24
Peak memory 225232 kb
Host smart-a9adf270-9e77-4921-a1e7-574d3982f1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806106943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.806106943
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1357652410
Short name T529
Test name
Test status
Simulation time 233212295 ps
CPU time 10.74 seconds
Started Apr 23 01:11:32 PM PDT 24
Finished Apr 23 01:11:44 PM PDT 24
Peak memory 217584 kb
Host smart-5287d1ef-46e6-4dba-9670-041fdf74354f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357652410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1357652410
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.4017191357
Short name T636
Test name
Test status
Simulation time 1302438093 ps
CPU time 13.13 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:11:57 PM PDT 24
Peak memory 217564 kb
Host smart-118acc62-dd9a-40b9-bb77-6eb97f946baf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017191357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
4017191357
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.562033442
Short name T650
Test name
Test status
Simulation time 294914325 ps
CPU time 9.4 seconds
Started Apr 23 01:11:30 PM PDT 24
Finished Apr 23 01:11:40 PM PDT 24
Peak memory 217640 kb
Host smart-772390ac-a09e-416b-be07-2d63d420ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562033442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.562033442
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.751498280
Short name T786
Test name
Test status
Simulation time 233955441 ps
CPU time 2.67 seconds
Started Apr 23 01:11:26 PM PDT 24
Finished Apr 23 01:11:30 PM PDT 24
Peak memory 213956 kb
Host smart-219b336e-a368-477f-872e-20374b5dca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751498280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.751498280
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3855909834
Short name T549
Test name
Test status
Simulation time 472858009 ps
CPU time 28.58 seconds
Started Apr 23 01:11:33 PM PDT 24
Finished Apr 23 01:12:02 PM PDT 24
Peak memory 250508 kb
Host smart-e49140b6-b8d8-47d8-9b2c-b54a68f190e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855909834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3855909834
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.163654188
Short name T759
Test name
Test status
Simulation time 49783069 ps
CPU time 6.94 seconds
Started Apr 23 01:11:30 PM PDT 24
Finished Apr 23 01:11:38 PM PDT 24
Peak memory 242972 kb
Host smart-49ba1cd8-6b24-4a8b-9252-3689b3ba02e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163654188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.163654188
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1895145579
Short name T282
Test name
Test status
Simulation time 42473919106 ps
CPU time 188.18 seconds
Started Apr 23 01:11:30 PM PDT 24
Finished Apr 23 01:14:39 PM PDT 24
Peak memory 219508 kb
Host smart-69d9509a-c555-45e4-82ee-8d9f64532f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895145579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1895145579
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.31105392
Short name T148
Test name
Test status
Simulation time 42360219811 ps
CPU time 215.56 seconds
Started Apr 23 01:11:31 PM PDT 24
Finished Apr 23 01:15:07 PM PDT 24
Peak memory 306760 kb
Host smart-5b8ebf6a-d9ed-471c-9aff-55cb3448a067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=31105392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.31105392
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.580654618
Short name T802
Test name
Test status
Simulation time 76240137 ps
CPU time 0.94 seconds
Started Apr 23 01:11:26 PM PDT 24
Finished Apr 23 01:11:28 PM PDT 24
Peak memory 212408 kb
Host smart-6a29a99a-dfdf-41e7-b68b-b715cfb7076a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580654618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.580654618
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4007991102
Short name T11
Test name
Test status
Simulation time 12872111 ps
CPU time 0.84 seconds
Started Apr 23 01:11:37 PM PDT 24
Finished Apr 23 01:11:39 PM PDT 24
Peak memory 209052 kb
Host smart-69e11a40-ddde-49d9-a620-e7cd617a0c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007991102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4007991102
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2481602098
Short name T744
Test name
Test status
Simulation time 1024959253 ps
CPU time 28.42 seconds
Started Apr 23 01:11:34 PM PDT 24
Finished Apr 23 01:12:03 PM PDT 24
Peak memory 217440 kb
Host smart-132a8212-ed89-41cf-bc8c-3a1793c211be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481602098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2481602098
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.733945915
Short name T31
Test name
Test status
Simulation time 145954471 ps
CPU time 4.43 seconds
Started Apr 23 01:11:31 PM PDT 24
Finished Apr 23 01:11:36 PM PDT 24
Peak memory 216512 kb
Host smart-366b46db-02ec-4cc9-9eeb-dc6ca4765e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733945915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.733945915
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.752863354
Short name T583
Test name
Test status
Simulation time 2280737913 ps
CPU time 19.74 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:12:04 PM PDT 24
Peak memory 217424 kb
Host smart-901e3f0f-ddf1-44a5-9ca0-ffa51b95c891
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752863354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.752863354
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2420142684
Short name T370
Test name
Test status
Simulation time 172430373 ps
CPU time 5.6 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:49 PM PDT 24
Peak memory 217436 kb
Host smart-2dbd61f8-4394-4cdd-98ad-3453a147b297
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420142684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2420142684
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3539102490
Short name T429
Test name
Test status
Simulation time 769621073 ps
CPU time 4.06 seconds
Started Apr 23 01:11:37 PM PDT 24
Finished Apr 23 01:11:42 PM PDT 24
Peak memory 213072 kb
Host smart-128f752d-92e4-429f-af94-64e9a2f66b3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539102490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3539102490
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.514971682
Short name T694
Test name
Test status
Simulation time 4928801912 ps
CPU time 51.91 seconds
Started Apr 23 01:11:30 PM PDT 24
Finished Apr 23 01:12:23 PM PDT 24
Peak memory 275188 kb
Host smart-c5da3d97-8286-4186-8dd5-44faba6c5cb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514971682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.514971682
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1752341074
Short name T750
Test name
Test status
Simulation time 10483646650 ps
CPU time 13.37 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:56 PM PDT 24
Peak memory 250476 kb
Host smart-86f8e185-564f-48e0-9eb1-06fa6b3f1c65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752341074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1752341074
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2694407699
Short name T399
Test name
Test status
Simulation time 89920248 ps
CPU time 3.27 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:11:47 PM PDT 24
Peak memory 217488 kb
Host smart-c89748a2-c1c4-4d67-a16d-1832268563b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694407699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2694407699
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1786026427
Short name T350
Test name
Test status
Simulation time 558987591 ps
CPU time 10.62 seconds
Started Apr 23 01:11:33 PM PDT 24
Finished Apr 23 01:11:44 PM PDT 24
Peak memory 217696 kb
Host smart-dbefd375-ea78-4505-9080-39b46755ad9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786026427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1786026427
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1668654165
Short name T159
Test name
Test status
Simulation time 2874748599 ps
CPU time 20.17 seconds
Started Apr 23 01:11:37 PM PDT 24
Finished Apr 23 01:11:58 PM PDT 24
Peak memory 217768 kb
Host smart-2137d2e3-e5d2-46af-bb85-ba759cb6afa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668654165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1668654165
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.4035979801
Short name T244
Test name
Test status
Simulation time 1506426674 ps
CPU time 12.73 seconds
Started Apr 23 01:11:32 PM PDT 24
Finished Apr 23 01:11:45 PM PDT 24
Peak memory 217540 kb
Host smart-db037077-24b7-4ee4-8ae0-39d7f139652a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035979801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
4035979801
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1994307831
Short name T93
Test name
Test status
Simulation time 3382204046 ps
CPU time 8.19 seconds
Started Apr 23 01:11:37 PM PDT 24
Finished Apr 23 01:11:46 PM PDT 24
Peak memory 217644 kb
Host smart-2f924cb3-674d-47e3-a4e4-a1774f803b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994307831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1994307831
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.4060422084
Short name T72
Test name
Test status
Simulation time 138111140 ps
CPU time 1.58 seconds
Started Apr 23 01:11:30 PM PDT 24
Finished Apr 23 01:11:32 PM PDT 24
Peak memory 213100 kb
Host smart-bf1edcac-e141-410b-83e2-4128730b6063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060422084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.4060422084
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1176715242
Short name T218
Test name
Test status
Simulation time 162080794 ps
CPU time 20.5 seconds
Started Apr 23 01:11:30 PM PDT 24
Finished Apr 23 01:11:52 PM PDT 24
Peak memory 250592 kb
Host smart-27b6b5e3-082f-4d70-8de2-ec14ed34c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176715242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1176715242
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1147410174
Short name T99
Test name
Test status
Simulation time 683355775 ps
CPU time 3.39 seconds
Started Apr 23 01:11:32 PM PDT 24
Finished Apr 23 01:11:36 PM PDT 24
Peak memory 222080 kb
Host smart-c3c96866-9e41-4c96-b1c4-5c88d449b420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147410174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1147410174
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2783415719
Short name T479
Test name
Test status
Simulation time 5855055166 ps
CPU time 190.96 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:14:55 PM PDT 24
Peak memory 282560 kb
Host smart-d0cdfbba-1611-4660-b883-d4c5c64720e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783415719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2783415719
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.560645151
Short name T411
Test name
Test status
Simulation time 51954766 ps
CPU time 1 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:11:45 PM PDT 24
Peak memory 211196 kb
Host smart-d28274bd-33ad-4e66-96db-3b9614fed113
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560645151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.560645151
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3898893440
Short name T167
Test name
Test status
Simulation time 72066944 ps
CPU time 0.87 seconds
Started Apr 23 01:11:40 PM PDT 24
Finished Apr 23 01:11:41 PM PDT 24
Peak memory 209180 kb
Host smart-21a127a3-8e77-4b3e-86e1-32914ce617c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898893440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3898893440
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3674918810
Short name T394
Test name
Test status
Simulation time 692749318 ps
CPU time 17.23 seconds
Started Apr 23 01:11:36 PM PDT 24
Finished Apr 23 01:11:54 PM PDT 24
Peak memory 209128 kb
Host smart-0a2ea877-958d-459c-9558-ecbccf46c949
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674918810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3674918810
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3221272878
Short name T491
Test name
Test status
Simulation time 6704625377 ps
CPU time 30.55 seconds
Started Apr 23 01:11:44 PM PDT 24
Finished Apr 23 01:12:15 PM PDT 24
Peak memory 218448 kb
Host smart-e4fcf9d3-045e-4cb6-976f-92e85acf9c98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221272878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3221272878
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1265052357
Short name T857
Test name
Test status
Simulation time 344491115 ps
CPU time 2.17 seconds
Started Apr 23 01:11:38 PM PDT 24
Finished Apr 23 01:11:41 PM PDT 24
Peak memory 217448 kb
Host smart-44a6a5d1-84cb-4176-9daa-f38df14fdfeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265052357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1265052357
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3749077686
Short name T69
Test name
Test status
Simulation time 337029439 ps
CPU time 3.28 seconds
Started Apr 23 01:11:38 PM PDT 24
Finished Apr 23 01:11:41 PM PDT 24
Peak memory 212644 kb
Host smart-adf79882-1716-4dc4-a8ae-e38fb3890efc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749077686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3749077686
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1014395907
Short name T541
Test name
Test status
Simulation time 5141008213 ps
CPU time 38.04 seconds
Started Apr 23 01:11:35 PM PDT 24
Finished Apr 23 01:12:14 PM PDT 24
Peak memory 276312 kb
Host smart-38073f74-6972-4b7f-993b-c0790a65c666
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014395907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1014395907
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1004809843
Short name T815
Test name
Test status
Simulation time 1024408168 ps
CPU time 9.09 seconds
Started Apr 23 01:11:34 PM PDT 24
Finished Apr 23 01:11:44 PM PDT 24
Peak memory 222348 kb
Host smart-ad46399c-9bd4-4b17-bedd-e942e398e266
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004809843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1004809843
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1225287814
Short name T528
Test name
Test status
Simulation time 69327148 ps
CPU time 2.42 seconds
Started Apr 23 01:11:35 PM PDT 24
Finished Apr 23 01:11:38 PM PDT 24
Peak memory 217648 kb
Host smart-94fdfaca-94ef-4ecf-9a40-667865cbee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225287814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1225287814
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.4281218392
Short name T276
Test name
Test status
Simulation time 1551350028 ps
CPU time 12.64 seconds
Started Apr 23 01:11:40 PM PDT 24
Finished Apr 23 01:11:53 PM PDT 24
Peak memory 225604 kb
Host smart-ae32f509-712e-4777-af95-8d67b7b2fc54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281218392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.4281218392
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.819748377
Short name T352
Test name
Test status
Simulation time 527918221 ps
CPU time 16.51 seconds
Started Apr 23 01:11:41 PM PDT 24
Finished Apr 23 01:11:58 PM PDT 24
Peak memory 217580 kb
Host smart-6b474648-319d-489f-b197-cdef9dc9cb5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819748377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.819748377
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1606904104
Short name T323
Test name
Test status
Simulation time 2012896907 ps
CPU time 6.18 seconds
Started Apr 23 01:11:39 PM PDT 24
Finished Apr 23 01:11:45 PM PDT 24
Peak memory 217624 kb
Host smart-236c2dbd-fd64-4b0a-a53e-f5691e2f6b64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606904104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1606904104
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2682786840
Short name T319
Test name
Test status
Simulation time 720344288 ps
CPU time 8.24 seconds
Started Apr 23 01:11:37 PM PDT 24
Finished Apr 23 01:11:46 PM PDT 24
Peak memory 224408 kb
Host smart-c00d6000-f38d-4608-916d-84e6836099c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682786840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2682786840
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.585228922
Short name T74
Test name
Test status
Simulation time 42011320 ps
CPU time 1.09 seconds
Started Apr 23 01:11:36 PM PDT 24
Finished Apr 23 01:11:38 PM PDT 24
Peak memory 211560 kb
Host smart-76b4b48b-1b4a-48ed-808e-ba1a5b66d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585228922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.585228922
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2771808702
Short name T539
Test name
Test status
Simulation time 699085096 ps
CPU time 24.54 seconds
Started Apr 23 01:11:36 PM PDT 24
Finished Apr 23 01:12:01 PM PDT 24
Peak memory 250556 kb
Host smart-c74d5833-5886-4744-b2ee-3b520a218820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771808702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2771808702
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.433877665
Short name T576
Test name
Test status
Simulation time 1058294350 ps
CPU time 6.62 seconds
Started Apr 23 01:11:36 PM PDT 24
Finished Apr 23 01:11:44 PM PDT 24
Peak memory 246556 kb
Host smart-51771bef-d678-49fa-a8aa-24ba1e0c5f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433877665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.433877665
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3143437885
Short name T652
Test name
Test status
Simulation time 2584423203 ps
CPU time 81.35 seconds
Started Apr 23 01:11:41 PM PDT 24
Finished Apr 23 01:13:03 PM PDT 24
Peak memory 251828 kb
Host smart-097e880a-e76c-4d48-a4bc-08670d1525e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143437885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3143437885
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1208763274
Short name T859
Test name
Test status
Simulation time 29882851 ps
CPU time 1.23 seconds
Started Apr 23 01:11:36 PM PDT 24
Finished Apr 23 01:11:38 PM PDT 24
Peak memory 212224 kb
Host smart-e78e56e1-9653-45a5-b12a-c78f3077ae5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208763274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1208763274
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3222216348
Short name T343
Test name
Test status
Simulation time 119454625 ps
CPU time 0.87 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:44 PM PDT 24
Peak memory 209144 kb
Host smart-15301642-c4ff-42bb-ada2-f961d7bfc850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222216348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3222216348
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1796139645
Short name T255
Test name
Test status
Simulation time 393266373 ps
CPU time 11.54 seconds
Started Apr 23 01:11:40 PM PDT 24
Finished Apr 23 01:11:53 PM PDT 24
Peak memory 217532 kb
Host smart-a7b5c57f-16dd-4763-966f-232aa5353ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796139645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1796139645
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3042251460
Short name T707
Test name
Test status
Simulation time 6522932469 ps
CPU time 32.3 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:12:16 PM PDT 24
Peak memory 218116 kb
Host smart-ceb586db-259e-411c-afa9-c55b522ffdc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042251460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3042251460
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3716523994
Short name T356
Test name
Test status
Simulation time 1283674098 ps
CPU time 6.9 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:49 PM PDT 24
Peak memory 217460 kb
Host smart-4a8e3de2-4cee-4403-9ee9-b9aa7b040526
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716523994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3716523994
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3768865601
Short name T6
Test name
Test status
Simulation time 260961459 ps
CPU time 2.23 seconds
Started Apr 23 01:11:41 PM PDT 24
Finished Apr 23 01:11:44 PM PDT 24
Peak memory 212200 kb
Host smart-26bdb44c-7a2a-41a5-9bce-3d75be41020a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768865601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3768865601
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2255915270
Short name T568
Test name
Test status
Simulation time 2713488244 ps
CPU time 92 seconds
Started Apr 23 01:11:39 PM PDT 24
Finished Apr 23 01:13:12 PM PDT 24
Peak memory 278588 kb
Host smart-5cff773c-b0c2-443b-9a37-19678763d16f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255915270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2255915270
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.642432091
Short name T843
Test name
Test status
Simulation time 264869524 ps
CPU time 8.75 seconds
Started Apr 23 01:11:39 PM PDT 24
Finished Apr 23 01:11:49 PM PDT 24
Peak memory 245936 kb
Host smart-ffe8f4fa-0f96-46cc-aa4a-2faf6221d30e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642432091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.642432091
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1727609135
Short name T850
Test name
Test status
Simulation time 110498880 ps
CPU time 2.27 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:46 PM PDT 24
Peak memory 217572 kb
Host smart-76362bec-f53a-4aac-8c9b-0a74356b91e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727609135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1727609135
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.92115287
Short name T582
Test name
Test status
Simulation time 280718306 ps
CPU time 13.21 seconds
Started Apr 23 01:11:40 PM PDT 24
Finished Apr 23 01:11:54 PM PDT 24
Peak memory 225632 kb
Host smart-f35fc1b4-0415-4995-8110-29b328522ae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92115287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.92115287
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.405890224
Short name T775
Test name
Test status
Simulation time 2616158390 ps
CPU time 14.65 seconds
Started Apr 23 01:11:40 PM PDT 24
Finished Apr 23 01:11:55 PM PDT 24
Peak memory 217624 kb
Host smart-efba2f50-a638-4e0d-a56d-1a7ae6642f23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405890224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.405890224
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.182021850
Short name T345
Test name
Test status
Simulation time 1116599018 ps
CPU time 11.04 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:11:55 PM PDT 24
Peak memory 217552 kb
Host smart-2103a1c8-98df-487e-8bdb-3c19f4f1e1b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182021850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.182021850
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4235914622
Short name T794
Test name
Test status
Simulation time 211096600 ps
CPU time 6.52 seconds
Started Apr 23 01:11:41 PM PDT 24
Finished Apr 23 01:11:48 PM PDT 24
Peak memory 217672 kb
Host smart-144d3e06-2bc0-42b6-a4e6-80994efd85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235914622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4235914622
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3188039662
Short name T427
Test name
Test status
Simulation time 105256786 ps
CPU time 3.11 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:46 PM PDT 24
Peak memory 213924 kb
Host smart-336e86e7-fee0-4918-ba8a-c59c3ae22381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188039662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3188039662
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.240498583
Short name T478
Test name
Test status
Simulation time 308055957 ps
CPU time 16.52 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:59 PM PDT 24
Peak memory 250628 kb
Host smart-20cdd64d-589e-4fb1-a7c7-ca87762b74d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240498583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.240498583
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.397325150
Short name T309
Test name
Test status
Simulation time 338995444 ps
CPU time 7.96 seconds
Started Apr 23 01:11:39 PM PDT 24
Finished Apr 23 01:11:48 PM PDT 24
Peak memory 250172 kb
Host smart-8ccb78e5-6845-4dea-86e3-ab5fc323b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397325150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.397325150
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.11102737
Short name T551
Test name
Test status
Simulation time 4910782889 ps
CPU time 98.85 seconds
Started Apr 23 01:11:40 PM PDT 24
Finished Apr 23 01:13:20 PM PDT 24
Peak memory 283444 kb
Host smart-8ed0e1b8-4c9a-482b-91b8-72d615ebbd39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.lc_ctrl_stress_all.11102737
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1589352607
Short name T823
Test name
Test status
Simulation time 34015920 ps
CPU time 0.75 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:43 PM PDT 24
Peak memory 208096 kb
Host smart-89f50109-fde2-4a84-a133-a9b1dfe672b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589352607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1589352607
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3966082138
Short name T623
Test name
Test status
Simulation time 14738477 ps
CPU time 0.88 seconds
Started Apr 23 01:11:52 PM PDT 24
Finished Apr 23 01:11:53 PM PDT 24
Peak memory 209036 kb
Host smart-cd0832f1-cbbc-4a13-aaa3-ec9833e8105a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966082138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3966082138
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.313221800
Short name T348
Test name
Test status
Simulation time 298879217 ps
CPU time 11.06 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:11:55 PM PDT 24
Peak memory 217600 kb
Host smart-c76a6288-0159-4519-8a09-8196b87ddbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313221800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.313221800
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2267776685
Short name T95
Test name
Test status
Simulation time 3294702972 ps
CPU time 12.21 seconds
Started Apr 23 01:11:49 PM PDT 24
Finished Apr 23 01:12:01 PM PDT 24
Peak memory 209224 kb
Host smart-d561478e-5317-4448-8749-41ffe094bb2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267776685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2267776685
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2139418077
Short name T864
Test name
Test status
Simulation time 3433529128 ps
CPU time 43.68 seconds
Started Apr 23 01:11:48 PM PDT 24
Finished Apr 23 01:12:32 PM PDT 24
Peak memory 219076 kb
Host smart-e5b94be0-7df9-4025-a46b-afe83e13fff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139418077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2139418077
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4122532049
Short name T364
Test name
Test status
Simulation time 2240513534 ps
CPU time 15.99 seconds
Started Apr 23 01:11:47 PM PDT 24
Finished Apr 23 01:12:03 PM PDT 24
Peak memory 217564 kb
Host smart-2d0c5516-d1ef-44f4-90ae-1f491173cb1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122532049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4122532049
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1711283099
Short name T565
Test name
Test status
Simulation time 586621534 ps
CPU time 7.47 seconds
Started Apr 23 01:11:42 PM PDT 24
Finished Apr 23 01:11:51 PM PDT 24
Peak memory 212976 kb
Host smart-c7b7c4f6-354b-47d7-8a3d-e3c3f9e52150
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711283099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1711283099
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3698134926
Short name T225
Test name
Test status
Simulation time 2310022078 ps
CPU time 79.33 seconds
Started Apr 23 01:11:44 PM PDT 24
Finished Apr 23 01:13:04 PM PDT 24
Peak memory 280900 kb
Host smart-219254cf-f636-461e-b6cc-bf73d68c5d1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698134926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3698134926
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1465575319
Short name T493
Test name
Test status
Simulation time 1284731486 ps
CPU time 10.28 seconds
Started Apr 23 01:11:48 PM PDT 24
Finished Apr 23 01:11:59 PM PDT 24
Peak memory 248864 kb
Host smart-22513c28-72fb-4bf3-9d54-889116d8088d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465575319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1465575319
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.921391932
Short name T516
Test name
Test status
Simulation time 110226703 ps
CPU time 3.28 seconds
Started Apr 23 01:11:44 PM PDT 24
Finished Apr 23 01:11:48 PM PDT 24
Peak memory 217580 kb
Host smart-e2f7c950-c2f8-4e0a-bc7a-8f794ec4c359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921391932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.921391932
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3412512559
Short name T331
Test name
Test status
Simulation time 1880301010 ps
CPU time 18.39 seconds
Started Apr 23 01:11:50 PM PDT 24
Finished Apr 23 01:12:09 PM PDT 24
Peak memory 216832 kb
Host smart-ebb15b24-7d80-4e39-8a1a-8bc345d72e8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412512559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3412512559
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2255708343
Short name T472
Test name
Test status
Simulation time 290187075 ps
CPU time 11.97 seconds
Started Apr 23 01:11:50 PM PDT 24
Finished Apr 23 01:12:03 PM PDT 24
Peak memory 217472 kb
Host smart-6e5013ea-9bdd-4c28-aece-5e7054f44972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255708343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2255708343
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2006577422
Short name T642
Test name
Test status
Simulation time 1785546074 ps
CPU time 16.99 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:12:01 PM PDT 24
Peak memory 225616 kb
Host smart-7b4a533e-b2a4-411a-9c71-2d8d8733ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006577422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2006577422
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.181969166
Short name T543
Test name
Test status
Simulation time 129310730 ps
CPU time 1.64 seconds
Started Apr 23 01:11:44 PM PDT 24
Finished Apr 23 01:11:46 PM PDT 24
Peak memory 213012 kb
Host smart-ccdac530-dba1-49e3-acb8-14219ee987b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181969166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.181969166
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1974585184
Short name T585
Test name
Test status
Simulation time 227020659 ps
CPU time 26.4 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:12:10 PM PDT 24
Peak memory 250588 kb
Host smart-55338da4-372c-4ba2-83c1-5b5e98896ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974585184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1974585184
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1179843317
Short name T224
Test name
Test status
Simulation time 341784524 ps
CPU time 6.32 seconds
Started Apr 23 01:11:43 PM PDT 24
Finished Apr 23 01:11:51 PM PDT 24
Peak memory 243968 kb
Host smart-7ed3a96b-a750-46c1-b2ca-53dc2a84fe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179843317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1179843317
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.434273897
Short name T584
Test name
Test status
Simulation time 14558147533 ps
CPU time 63.89 seconds
Started Apr 23 01:11:50 PM PDT 24
Finished Apr 23 01:12:54 PM PDT 24
Peak memory 272332 kb
Host smart-71e90108-ee4e-4cbd-891c-12ea9f2991d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434273897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.434273897
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2671654952
Short name T12
Test name
Test status
Simulation time 40683248 ps
CPU time 0.87 seconds
Started Apr 23 01:11:45 PM PDT 24
Finished Apr 23 01:11:47 PM PDT 24
Peak memory 207924 kb
Host smart-ca40992d-40d7-4e14-b9de-bba18d4e0e4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671654952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2671654952
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.820620014
Short name T294
Test name
Test status
Simulation time 19751649 ps
CPU time 1.21 seconds
Started Apr 23 01:11:50 PM PDT 24
Finished Apr 23 01:11:52 PM PDT 24
Peak memory 208588 kb
Host smart-22c86956-cd0f-492e-b86c-e1999c3fda6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820620014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.820620014
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4002262947
Short name T748
Test name
Test status
Simulation time 640640816 ps
CPU time 16.73 seconds
Started Apr 23 01:11:51 PM PDT 24
Finished Apr 23 01:12:08 PM PDT 24
Peak memory 225672 kb
Host smart-a0a96ee7-8300-4793-a1a3-b34c1d8c07be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002262947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4002262947
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.4038004437
Short name T8
Test name
Test status
Simulation time 3995726253 ps
CPU time 5.05 seconds
Started Apr 23 01:11:53 PM PDT 24
Finished Apr 23 01:11:58 PM PDT 24
Peak memory 217456 kb
Host smart-2c6a7a60-c506-466e-b7ec-fc4d170eef2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038004437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4038004437
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3410444551
Short name T691
Test name
Test status
Simulation time 6557621867 ps
CPU time 29.36 seconds
Started Apr 23 01:11:52 PM PDT 24
Finished Apr 23 01:12:22 PM PDT 24
Peak memory 218516 kb
Host smart-f6bfe425-8a2d-4a6e-8019-cdd7a25a7caf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410444551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3410444551
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2155192063
Short name T555
Test name
Test status
Simulation time 290830256 ps
CPU time 8.81 seconds
Started Apr 23 01:11:52 PM PDT 24
Finished Apr 23 01:12:02 PM PDT 24
Peak memory 217472 kb
Host smart-75f579d9-ca93-4b8e-a5df-02b501c47cd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155192063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2155192063
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2062304748
Short name T480
Test name
Test status
Simulation time 100600216 ps
CPU time 1.87 seconds
Started Apr 23 01:11:51 PM PDT 24
Finished Apr 23 01:11:53 PM PDT 24
Peak memory 212144 kb
Host smart-53734d18-0a2c-489b-9e50-7aac5b972b23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062304748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2062304748
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2926845910
Short name T395
Test name
Test status
Simulation time 1274396679 ps
CPU time 43.43 seconds
Started Apr 23 01:11:50 PM PDT 24
Finished Apr 23 01:12:35 PM PDT 24
Peak memory 283284 kb
Host smart-f01e18ff-78ca-4d26-be88-cfbecca53a2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926845910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2926845910
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.608059512
Short name T673
Test name
Test status
Simulation time 1497516624 ps
CPU time 11.13 seconds
Started Apr 23 01:11:53 PM PDT 24
Finished Apr 23 01:12:05 PM PDT 24
Peak memory 249972 kb
Host smart-08a6b4ac-2dbb-445b-9898-48ded19006a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608059512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.608059512
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.952858500
Short name T401
Test name
Test status
Simulation time 71899200 ps
CPU time 3.04 seconds
Started Apr 23 01:11:50 PM PDT 24
Finished Apr 23 01:11:53 PM PDT 24
Peak memory 217464 kb
Host smart-f3d72481-33d9-4e61-8ae5-4a41987ad604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952858500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.952858500
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.4289606230
Short name T770
Test name
Test status
Simulation time 320513879 ps
CPU time 14.29 seconds
Started Apr 23 01:11:54 PM PDT 24
Finished Apr 23 01:12:09 PM PDT 24
Peak memory 217724 kb
Host smart-d42aa628-f669-45e4-bf05-55f7e9ddc3ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289606230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.4289606230
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.562236669
Short name T286
Test name
Test status
Simulation time 3651083200 ps
CPU time 10.61 seconds
Started Apr 23 01:11:52 PM PDT 24
Finished Apr 23 01:12:03 PM PDT 24
Peak memory 217660 kb
Host smart-49217a53-c943-4adb-9464-af4a7e4fc168
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562236669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.562236669
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3591263568
Short name T773
Test name
Test status
Simulation time 2086161934 ps
CPU time 13.07 seconds
Started Apr 23 01:11:51 PM PDT 24
Finished Apr 23 01:12:05 PM PDT 24
Peak memory 217560 kb
Host smart-35913406-d1d1-4828-acd3-ef871f491ab4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591263568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3591263568
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2845124570
Short name T465
Test name
Test status
Simulation time 1463053067 ps
CPU time 11.27 seconds
Started Apr 23 01:11:52 PM PDT 24
Finished Apr 23 01:12:04 PM PDT 24
Peak memory 217644 kb
Host smart-87829749-7272-40e4-a390-bc076b3ca451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845124570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2845124570
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.544495046
Short name T738
Test name
Test status
Simulation time 93895806 ps
CPU time 1.94 seconds
Started Apr 23 01:11:49 PM PDT 24
Finished Apr 23 01:11:51 PM PDT 24
Peak memory 213244 kb
Host smart-59413a1e-97f3-4c26-906e-456cc55fa17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544495046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.544495046
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2545753449
Short name T287
Test name
Test status
Simulation time 500181108 ps
CPU time 25.79 seconds
Started Apr 23 01:11:51 PM PDT 24
Finished Apr 23 01:12:17 PM PDT 24
Peak memory 250568 kb
Host smart-f3467911-3deb-4589-ab79-f5273365c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545753449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2545753449
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3703843328
Short name T351
Test name
Test status
Simulation time 337808591 ps
CPU time 6.62 seconds
Started Apr 23 01:11:51 PM PDT 24
Finished Apr 23 01:11:59 PM PDT 24
Peak memory 246716 kb
Host smart-3ad7c48a-7591-4ffc-a53b-0fafc509b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703843328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3703843328
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1233323261
Short name T449
Test name
Test status
Simulation time 47351001685 ps
CPU time 352.44 seconds
Started Apr 23 01:11:52 PM PDT 24
Finished Apr 23 01:17:45 PM PDT 24
Peak memory 250608 kb
Host smart-a30e06f3-03f3-420d-9f5e-8fc5c8993a9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233323261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1233323261
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1670144266
Short name T845
Test name
Test status
Simulation time 31947108 ps
CPU time 0.72 seconds
Started Apr 23 01:11:48 PM PDT 24
Finished Apr 23 01:11:49 PM PDT 24
Peak memory 208196 kb
Host smart-8bf0bf03-2a8b-49db-8746-67e43c3ae437
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670144266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1670144266
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4025160014
Short name T760
Test name
Test status
Simulation time 19749571 ps
CPU time 0.99 seconds
Started Apr 23 01:12:02 PM PDT 24
Finished Apr 23 01:12:03 PM PDT 24
Peak memory 209240 kb
Host smart-9076c68d-d3ae-4348-b4be-f00d437c5338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025160014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4025160014
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1368698341
Short name T236
Test name
Test status
Simulation time 1365685950 ps
CPU time 13.89 seconds
Started Apr 23 01:11:54 PM PDT 24
Finished Apr 23 01:12:09 PM PDT 24
Peak memory 217464 kb
Host smart-53a7cddd-d40c-4ffe-82b1-627dc23dea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368698341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1368698341
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.402039502
Short name T26
Test name
Test status
Simulation time 957156520 ps
CPU time 10.93 seconds
Started Apr 23 01:12:01 PM PDT 24
Finished Apr 23 01:12:13 PM PDT 24
Peak memory 209120 kb
Host smart-7458832a-6cc9-4ddb-9af5-880e3d32a08c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402039502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.402039502
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3861345732
Short name T841
Test name
Test status
Simulation time 91294981083 ps
CPU time 143.29 seconds
Started Apr 23 01:11:59 PM PDT 24
Finished Apr 23 01:14:23 PM PDT 24
Peak memory 219216 kb
Host smart-8dbee0db-c655-4e65-a2c6-7da50483c1a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861345732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3861345732
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3971372252
Short name T470
Test name
Test status
Simulation time 1659490746 ps
CPU time 11.84 seconds
Started Apr 23 01:12:01 PM PDT 24
Finished Apr 23 01:12:14 PM PDT 24
Peak memory 217468 kb
Host smart-1776a94d-dd81-4b7f-a626-eb655b600b4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971372252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3971372252
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1501710359
Short name T353
Test name
Test status
Simulation time 198900596 ps
CPU time 1.85 seconds
Started Apr 23 01:11:56 PM PDT 24
Finished Apr 23 01:11:58 PM PDT 24
Peak memory 212436 kb
Host smart-b6f6493a-8458-44e0-b955-9edcd1989969
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501710359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1501710359
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1482350853
Short name T630
Test name
Test status
Simulation time 2527527475 ps
CPU time 86.66 seconds
Started Apr 23 01:11:55 PM PDT 24
Finished Apr 23 01:13:22 PM PDT 24
Peak memory 275308 kb
Host smart-cb08d448-96a5-4b1d-81eb-e63281ecf4bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482350853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1482350853
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1213605969
Short name T793
Test name
Test status
Simulation time 1295344518 ps
CPU time 10.31 seconds
Started Apr 23 01:11:56 PM PDT 24
Finished Apr 23 01:12:07 PM PDT 24
Peak memory 246760 kb
Host smart-de01d095-dd68-4443-a962-fa2a524ffe9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213605969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1213605969
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.109051988
Short name T640
Test name
Test status
Simulation time 95686697 ps
CPU time 4.69 seconds
Started Apr 23 01:11:55 PM PDT 24
Finished Apr 23 01:12:00 PM PDT 24
Peak memory 217548 kb
Host smart-f7a46e56-328c-4abb-bc63-747fee017a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109051988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.109051988
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1757162774
Short name T157
Test name
Test status
Simulation time 2630158288 ps
CPU time 12.92 seconds
Started Apr 23 01:11:58 PM PDT 24
Finished Apr 23 01:12:11 PM PDT 24
Peak memory 225752 kb
Host smart-eb9152b5-8e7c-4d67-9140-98e2aee33998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757162774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1757162774
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2657113205
Short name T210
Test name
Test status
Simulation time 968131815 ps
CPU time 15.13 seconds
Started Apr 23 01:12:04 PM PDT 24
Finished Apr 23 01:12:19 PM PDT 24
Peak memory 217576 kb
Host smart-4f105e46-8e0b-4176-a091-a7b6c9ac4f2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657113205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2657113205
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2232966842
Short name T519
Test name
Test status
Simulation time 289424269 ps
CPU time 11.17 seconds
Started Apr 23 01:11:58 PM PDT 24
Finished Apr 23 01:12:10 PM PDT 24
Peak memory 217596 kb
Host smart-d7711684-4dec-442f-b2fb-c1695588cb6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232966842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2232966842
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1823610063
Short name T362
Test name
Test status
Simulation time 1078367875 ps
CPU time 9.15 seconds
Started Apr 23 01:11:54 PM PDT 24
Finished Apr 23 01:12:03 PM PDT 24
Peak memory 217664 kb
Host smart-ec71da63-97f9-42be-8df7-2d06ea6dc8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823610063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1823610063
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.418742144
Short name T677
Test name
Test status
Simulation time 59779323 ps
CPU time 3.32 seconds
Started Apr 23 01:11:51 PM PDT 24
Finished Apr 23 01:11:55 PM PDT 24
Peak memory 213976 kb
Host smart-0d5bad7b-9b57-41bb-b007-fda3b1e90d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418742144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.418742144
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1839831402
Short name T260
Test name
Test status
Simulation time 201955629 ps
CPU time 18.61 seconds
Started Apr 23 01:11:57 PM PDT 24
Finished Apr 23 01:12:16 PM PDT 24
Peak memory 250508 kb
Host smart-ada8b445-66bb-48fe-aad7-08c69a3b2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839831402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1839831402
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1882554302
Short name T588
Test name
Test status
Simulation time 1376327381 ps
CPU time 8.68 seconds
Started Apr 23 01:11:54 PM PDT 24
Finished Apr 23 01:12:04 PM PDT 24
Peak memory 250484 kb
Host smart-cd212394-d71e-4b02-8918-be62425d8470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882554302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1882554302
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3741352683
Short name T634
Test name
Test status
Simulation time 581964372 ps
CPU time 10.46 seconds
Started Apr 23 01:12:04 PM PDT 24
Finished Apr 23 01:12:14 PM PDT 24
Peak memory 225624 kb
Host smart-6c393c0b-7449-4b2b-a155-82b48087ba69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741352683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3741352683
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.410581912
Short name T314
Test name
Test status
Simulation time 14315615 ps
CPU time 1.13 seconds
Started Apr 23 01:11:57 PM PDT 24
Finished Apr 23 01:11:59 PM PDT 24
Peak memory 211148 kb
Host smart-e847efe0-2852-4401-8126-f897a5631f94
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410581912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.410581912
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.4253038892
Short name T169
Test name
Test status
Simulation time 83568520 ps
CPU time 1.3 seconds
Started Apr 23 01:12:08 PM PDT 24
Finished Apr 23 01:12:10 PM PDT 24
Peak memory 209228 kb
Host smart-30cadb39-f245-40e3-8467-dd1fda6ffe18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253038892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4253038892
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.792119763
Short name T420
Test name
Test status
Simulation time 426349166 ps
CPU time 14.62 seconds
Started Apr 23 01:12:00 PM PDT 24
Finished Apr 23 01:12:15 PM PDT 24
Peak memory 225632 kb
Host smart-24b292ea-8b3a-4f16-a35a-d1e610256f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792119763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.792119763
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2251042758
Short name T544
Test name
Test status
Simulation time 1448212215 ps
CPU time 2.96 seconds
Started Apr 23 01:12:08 PM PDT 24
Finished Apr 23 01:12:12 PM PDT 24
Peak memory 216432 kb
Host smart-1f6eb9cb-4450-4a78-b49d-77a5e5804131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251042758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2251042758
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1086401942
Short name T311
Test name
Test status
Simulation time 3591598424 ps
CPU time 49.32 seconds
Started Apr 23 01:12:07 PM PDT 24
Finished Apr 23 01:12:56 PM PDT 24
Peak memory 217852 kb
Host smart-ad6feea8-5070-42bd-aef6-0b302c59e75d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086401942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1086401942
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4143165658
Short name T289
Test name
Test status
Simulation time 601419618 ps
CPU time 5.52 seconds
Started Apr 23 01:12:07 PM PDT 24
Finished Apr 23 01:12:13 PM PDT 24
Peak memory 217396 kb
Host smart-cba3411a-a3ab-4c9b-b410-b95831054c06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143165658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4143165658
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3591869311
Short name T780
Test name
Test status
Simulation time 276515490 ps
CPU time 7.96 seconds
Started Apr 23 01:12:04 PM PDT 24
Finished Apr 23 01:12:12 PM PDT 24
Peak memory 213008 kb
Host smart-2296cc6c-7ba2-4180-9ecc-c1be2ae3bc0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591869311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3591869311
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3308268451
Short name T835
Test name
Test status
Simulation time 1676518572 ps
CPU time 31.25 seconds
Started Apr 23 01:12:03 PM PDT 24
Finished Apr 23 01:12:34 PM PDT 24
Peak memory 250528 kb
Host smart-8b7631a9-0607-4fa2-a7aa-8f89b9bd66af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308268451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3308268451
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1330291223
Short name T422
Test name
Test status
Simulation time 1133450388 ps
CPU time 21.72 seconds
Started Apr 23 01:12:04 PM PDT 24
Finished Apr 23 01:12:26 PM PDT 24
Peak memory 246832 kb
Host smart-e2275f75-f163-4a34-88e8-0095658a803a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330291223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1330291223
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1876896660
Short name T659
Test name
Test status
Simulation time 60812289 ps
CPU time 2.25 seconds
Started Apr 23 01:12:05 PM PDT 24
Finished Apr 23 01:12:07 PM PDT 24
Peak memory 217584 kb
Host smart-6cfd6426-d67e-40ab-a513-b5d2539458ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876896660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1876896660
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1092343216
Short name T285
Test name
Test status
Simulation time 324030867 ps
CPU time 9.34 seconds
Started Apr 23 01:12:07 PM PDT 24
Finished Apr 23 01:12:17 PM PDT 24
Peak memory 218504 kb
Host smart-05f58035-59d0-4ac3-9bf4-3caed54f336c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092343216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1092343216
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1214664966
Short name T263
Test name
Test status
Simulation time 1002295055 ps
CPU time 9.35 seconds
Started Apr 23 01:12:06 PM PDT 24
Finished Apr 23 01:12:16 PM PDT 24
Peak memory 217588 kb
Host smart-6dcf733b-29a5-488e-a273-e0e74ac65ff4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214664966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1214664966
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.607101619
Short name T620
Test name
Test status
Simulation time 1782259054 ps
CPU time 16.74 seconds
Started Apr 23 01:12:06 PM PDT 24
Finished Apr 23 01:12:23 PM PDT 24
Peak memory 217472 kb
Host smart-2f0dda1b-053c-4c1e-b258-ccab26887d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607101619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.607101619
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2293733150
Short name T719
Test name
Test status
Simulation time 1157155573 ps
CPU time 9.02 seconds
Started Apr 23 01:12:01 PM PDT 24
Finished Apr 23 01:12:11 PM PDT 24
Peak memory 224232 kb
Host smart-bf7421aa-9364-442e-8115-239d70956697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293733150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2293733150
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.145097559
Short name T384
Test name
Test status
Simulation time 137687629 ps
CPU time 1.49 seconds
Started Apr 23 01:12:05 PM PDT 24
Finished Apr 23 01:12:07 PM PDT 24
Peak memory 213180 kb
Host smart-89693244-5fa3-48fd-a825-070967dcb5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145097559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.145097559
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2263711082
Short name T564
Test name
Test status
Simulation time 301103680 ps
CPU time 29.78 seconds
Started Apr 23 01:12:02 PM PDT 24
Finished Apr 23 01:12:32 PM PDT 24
Peak memory 250408 kb
Host smart-79431d08-23ec-4480-83b5-5216930a6cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263711082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2263711082
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3406416145
Short name T436
Test name
Test status
Simulation time 89504102 ps
CPU time 7.94 seconds
Started Apr 23 01:12:02 PM PDT 24
Finished Apr 23 01:12:11 PM PDT 24
Peak memory 250096 kb
Host smart-31362816-6bca-4021-b2ee-b548f665b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406416145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3406416145
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3940142197
Short name T24
Test name
Test status
Simulation time 1058500374 ps
CPU time 29.21 seconds
Started Apr 23 01:12:06 PM PDT 24
Finished Apr 23 01:12:36 PM PDT 24
Peak memory 227420 kb
Host smart-d101609d-3dea-4a8c-a213-ed5606e8dc7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940142197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3940142197
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.70594421
Short name T797
Test name
Test status
Simulation time 17754358 ps
CPU time 1.22 seconds
Started Apr 23 01:12:03 PM PDT 24
Finished Apr 23 01:12:04 PM PDT 24
Peak memory 212300 kb
Host smart-b6890e31-a192-4b46-8976-ecc7549f2e99
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70594421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_volatile_unlock_smoke.70594421
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3244353316
Short name T578
Test name
Test status
Simulation time 56290275 ps
CPU time 1.04 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:12:12 PM PDT 24
Peak memory 209240 kb
Host smart-d7a8a203-ceeb-46bd-aaa8-b7b63d60d17c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244353316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3244353316
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2980651573
Short name T695
Test name
Test status
Simulation time 647883328 ps
CPU time 16.21 seconds
Started Apr 23 01:12:07 PM PDT 24
Finished Apr 23 01:12:24 PM PDT 24
Peak memory 225636 kb
Host smart-1832e3fd-3157-4306-937b-3b741de6611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980651573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2980651573
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1463553374
Short name T747
Test name
Test status
Simulation time 397830906 ps
CPU time 11.1 seconds
Started Apr 23 01:12:12 PM PDT 24
Finished Apr 23 01:12:23 PM PDT 24
Peak memory 216908 kb
Host smart-80c0af79-87bc-4028-9969-9a46214b488a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463553374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1463553374
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2303666077
Short name T787
Test name
Test status
Simulation time 16293453091 ps
CPU time 119.63 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:14:10 PM PDT 24
Peak memory 218472 kb
Host smart-e4bda218-a47e-49c5-8c33-4e4da407b9e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303666077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2303666077
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2638934754
Short name T805
Test name
Test status
Simulation time 1017181412 ps
CPU time 11.8 seconds
Started Apr 23 01:12:14 PM PDT 24
Finished Apr 23 01:12:27 PM PDT 24
Peak memory 217500 kb
Host smart-37fd2b45-3279-4d3d-ad25-ede77b70f800
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638934754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2638934754
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1463046351
Short name T601
Test name
Test status
Simulation time 655890346 ps
CPU time 3.08 seconds
Started Apr 23 01:12:14 PM PDT 24
Finished Apr 23 01:12:17 PM PDT 24
Peak memory 212660 kb
Host smart-aa34f9be-a225-43c9-a77f-cf1fad50fcdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463046351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1463046351
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3425481210
Short name T632
Test name
Test status
Simulation time 1024456111 ps
CPU time 33.64 seconds
Started Apr 23 01:12:14 PM PDT 24
Finished Apr 23 01:12:48 PM PDT 24
Peak memory 250644 kb
Host smart-ef132e35-8f06-4493-b579-288599c4a9f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425481210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3425481210
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1984085638
Short name T165
Test name
Test status
Simulation time 424799374 ps
CPU time 13.16 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:12:24 PM PDT 24
Peak memory 250576 kb
Host smart-0f1b360a-65f2-45b1-a3d2-3bd706546b18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984085638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1984085638
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3381046329
Short name T463
Test name
Test status
Simulation time 34721769 ps
CPU time 1.86 seconds
Started Apr 23 01:12:07 PM PDT 24
Finished Apr 23 01:12:09 PM PDT 24
Peak memory 217520 kb
Host smart-033ac02c-44f7-4064-9b73-111a87b46980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381046329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3381046329
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1108511677
Short name T300
Test name
Test status
Simulation time 797800326 ps
CPU time 11.65 seconds
Started Apr 23 01:12:12 PM PDT 24
Finished Apr 23 01:12:25 PM PDT 24
Peak memory 217204 kb
Host smart-8f2caf03-7e20-496b-b39c-11cd6b44b8db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108511677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1108511677
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3929967018
Short name T477
Test name
Test status
Simulation time 395067624 ps
CPU time 10.74 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:12:21 PM PDT 24
Peak memory 217468 kb
Host smart-89c43b9a-763b-479d-920c-e89766f82a81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929967018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3929967018
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3965027742
Short name T589
Test name
Test status
Simulation time 567628230 ps
CPU time 10.89 seconds
Started Apr 23 01:12:11 PM PDT 24
Finished Apr 23 01:12:22 PM PDT 24
Peak memory 217580 kb
Host smart-b6100f12-4a7c-4ba7-9330-b1d5f4bcf62f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965027742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3965027742
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1417316972
Short name T56
Test name
Test status
Simulation time 6959610604 ps
CPU time 11.61 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:12:22 PM PDT 24
Peak memory 217684 kb
Host smart-04fbffb6-6d9d-4399-8869-665eb3c503c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417316972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1417316972
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2109567715
Short name T341
Test name
Test status
Simulation time 60961960 ps
CPU time 3.57 seconds
Started Apr 23 01:12:07 PM PDT 24
Finished Apr 23 01:12:11 PM PDT 24
Peak memory 217428 kb
Host smart-e27b73ca-0d3d-4400-9e0a-7a8f88249fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109567715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2109567715
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3307520627
Short name T396
Test name
Test status
Simulation time 669524506 ps
CPU time 24.51 seconds
Started Apr 23 01:12:08 PM PDT 24
Finished Apr 23 01:12:33 PM PDT 24
Peak memory 250592 kb
Host smart-7e9863d6-2ae7-4d5e-ac19-dbf4c7e1d12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307520627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3307520627
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2726284497
Short name T532
Test name
Test status
Simulation time 92547872 ps
CPU time 8.17 seconds
Started Apr 23 01:12:08 PM PDT 24
Finished Apr 23 01:12:17 PM PDT 24
Peak memory 250584 kb
Host smart-59cb3f30-8d0b-4e83-a5eb-d6d19e236dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726284497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2726284497
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1367015102
Short name T803
Test name
Test status
Simulation time 3273482761 ps
CPU time 108.99 seconds
Started Apr 23 01:12:12 PM PDT 24
Finished Apr 23 01:14:02 PM PDT 24
Peak memory 236748 kb
Host smart-c6cbe1f8-8a20-4169-be66-024caf2f6b07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367015102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1367015102
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.851502125
Short name T20
Test name
Test status
Simulation time 49509697120 ps
CPU time 301.08 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:17:12 PM PDT 24
Peak memory 274368 kb
Host smart-555a764f-f7d1-4112-9bb2-939c77a6698e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=851502125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.851502125
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3713762322
Short name T63
Test name
Test status
Simulation time 14075540 ps
CPU time 0.91 seconds
Started Apr 23 01:12:07 PM PDT 24
Finished Apr 23 01:12:09 PM PDT 24
Peak memory 211224 kb
Host smart-8fa18975-6453-4e8b-80ba-ada1d2403c35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713762322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3713762322
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1858118465
Short name T293
Test name
Test status
Simulation time 24858709 ps
CPU time 1.13 seconds
Started Apr 23 01:10:37 PM PDT 24
Finished Apr 23 01:10:40 PM PDT 24
Peak memory 209216 kb
Host smart-84503b3e-c2e3-448e-a13c-8a897c6266a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858118465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1858118465
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.5679670
Short name T49
Test name
Test status
Simulation time 1017494506 ps
CPU time 9.87 seconds
Started Apr 23 01:10:35 PM PDT 24
Finished Apr 23 01:10:45 PM PDT 24
Peak memory 225668 kb
Host smart-a8bd5192-5171-482e-9dc0-bb7f074db317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5679670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.5679670
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1979645123
Short name T809
Test name
Test status
Simulation time 2242513103 ps
CPU time 3.3 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:49 PM PDT 24
Peak memory 209168 kb
Host smart-56daba3c-f50a-4a07-81a8-d0cf03adbeb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979645123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1979645123
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.635797539
Short name T521
Test name
Test status
Simulation time 450003312 ps
CPU time 5.84 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:52 PM PDT 24
Peak memory 216844 kb
Host smart-076cf82c-ebd1-458d-af7c-6e6895e7b7c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635797539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.635797539
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.152342247
Short name T492
Test name
Test status
Simulation time 1653203710 ps
CPU time 10.45 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:45 PM PDT 24
Peak memory 217420 kb
Host smart-42e7a90b-331f-4246-b540-2d00e5e62510
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152342247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.152342247
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4134715489
Short name T611
Test name
Test status
Simulation time 2659597554 ps
CPU time 19.75 seconds
Started Apr 23 01:10:37 PM PDT 24
Finished Apr 23 01:10:58 PM PDT 24
Peak memory 212724 kb
Host smart-a879973d-052b-4f98-b337-c8033606faea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134715489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4134715489
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3073318931
Short name T645
Test name
Test status
Simulation time 2327784269 ps
CPU time 7.31 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:42 PM PDT 24
Peak memory 213132 kb
Host smart-768d530b-9651-4772-b01f-2e5842ce75d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073318931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3073318931
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3867040701
Short name T574
Test name
Test status
Simulation time 33513089975 ps
CPU time 88.31 seconds
Started Apr 23 01:10:32 PM PDT 24
Finished Apr 23 01:12:01 PM PDT 24
Peak memory 273356 kb
Host smart-33094129-2489-4e2c-bf8e-195738864092
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867040701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3867040701
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3756236236
Short name T819
Test name
Test status
Simulation time 1518904257 ps
CPU time 15.79 seconds
Started Apr 23 01:10:34 PM PDT 24
Finished Apr 23 01:10:50 PM PDT 24
Peak memory 245812 kb
Host smart-2f92b8ff-2df3-4f13-b0ab-61acda9cb1d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756236236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3756236236
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2338203153
Short name T222
Test name
Test status
Simulation time 230358008 ps
CPU time 2.58 seconds
Started Apr 23 01:10:29 PM PDT 24
Finished Apr 23 01:10:32 PM PDT 24
Peak memory 217516 kb
Host smart-396777b0-1bb9-498b-898e-3eba74f62663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338203153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2338203153
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.349501266
Short name T697
Test name
Test status
Simulation time 2612626304 ps
CPU time 24.55 seconds
Started Apr 23 01:10:33 PM PDT 24
Finished Apr 23 01:10:58 PM PDT 24
Peak memory 213976 kb
Host smart-a015aaee-2d2e-40a3-b0d0-f9afefc34a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349501266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.349501266
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1840514424
Short name T97
Test name
Test status
Simulation time 426713544 ps
CPU time 21.3 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:11:07 PM PDT 24
Peak memory 280500 kb
Host smart-9aa6dc4e-70ee-4def-815b-d81cde9e8801
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840514424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1840514424
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3115796181
Short name T799
Test name
Test status
Simulation time 839998947 ps
CPU time 14 seconds
Started Apr 23 01:10:41 PM PDT 24
Finished Apr 23 01:10:55 PM PDT 24
Peak memory 218516 kb
Host smart-55366438-f884-4f84-aebf-3ce37dee2fce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115796181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3115796181
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1197823704
Short name T670
Test name
Test status
Simulation time 5349930690 ps
CPU time 12.76 seconds
Started Apr 23 01:10:40 PM PDT 24
Finished Apr 23 01:10:54 PM PDT 24
Peak memory 217756 kb
Host smart-c730d48f-5b10-4b3c-9389-bdaa6ca50acf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197823704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1197823704
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2960837062
Short name T740
Test name
Test status
Simulation time 1744032298 ps
CPU time 7.84 seconds
Started Apr 23 01:10:37 PM PDT 24
Finished Apr 23 01:10:45 PM PDT 24
Peak memory 217504 kb
Host smart-ae38fe6c-58d2-4186-9c40-5b56138934d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960837062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
960837062
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.4032777178
Short name T536
Test name
Test status
Simulation time 1663766887 ps
CPU time 10.05 seconds
Started Apr 23 01:10:33 PM PDT 24
Finished Apr 23 01:10:44 PM PDT 24
Peak memory 225648 kb
Host smart-d6c59ac3-aea1-4acd-b421-4a00c99fa76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032777178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.4032777178
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1954935683
Short name T526
Test name
Test status
Simulation time 61019452 ps
CPU time 2.61 seconds
Started Apr 23 01:10:29 PM PDT 24
Finished Apr 23 01:10:33 PM PDT 24
Peak memory 217488 kb
Host smart-d519f234-9c38-4d90-bc5d-f3b0eb26881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954935683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1954935683
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.690191870
Short name T663
Test name
Test status
Simulation time 1124401257 ps
CPU time 26.51 seconds
Started Apr 23 01:10:29 PM PDT 24
Finished Apr 23 01:10:57 PM PDT 24
Peak memory 250540 kb
Host smart-16a89da8-5362-4016-b2ed-21153125f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690191870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.690191870
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1499201326
Short name T302
Test name
Test status
Simulation time 514255625 ps
CPU time 4.32 seconds
Started Apr 23 01:10:29 PM PDT 24
Finished Apr 23 01:10:34 PM PDT 24
Peak memory 225992 kb
Host smart-f98008cd-09c5-49c1-b953-6eaf1a026982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499201326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1499201326
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2432609211
Short name T566
Test name
Test status
Simulation time 68600085329 ps
CPU time 608.74 seconds
Started Apr 23 01:10:39 PM PDT 24
Finished Apr 23 01:20:48 PM PDT 24
Peak memory 278568 kb
Host smart-2dc0f2bc-e65f-410f-9712-c9e67d482036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432609211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2432609211
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.984684386
Short name T145
Test name
Test status
Simulation time 295054852089 ps
CPU time 1947.35 seconds
Started Apr 23 01:10:42 PM PDT 24
Finished Apr 23 01:43:10 PM PDT 24
Peak memory 512884 kb
Host smart-82d148f7-6247-43cd-84a6-8a6804a5dcf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=984684386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.984684386
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1175434208
Short name T796
Test name
Test status
Simulation time 11927288 ps
CPU time 1.02 seconds
Started Apr 23 01:10:30 PM PDT 24
Finished Apr 23 01:10:32 PM PDT 24
Peak memory 211200 kb
Host smart-ab948931-e42a-401a-a4e6-45a57ea1beb2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175434208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1175434208
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1425621715
Short name T817
Test name
Test status
Simulation time 65839738 ps
CPU time 1 seconds
Started Apr 23 01:12:13 PM PDT 24
Finished Apr 23 01:12:15 PM PDT 24
Peak memory 209196 kb
Host smart-4e707b97-ee30-4721-8ee4-f128961863af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425621715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1425621715
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1056195975
Short name T618
Test name
Test status
Simulation time 5974413884 ps
CPU time 17.3 seconds
Started Apr 23 01:12:12 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 217592 kb
Host smart-46f17a11-3e7a-43ee-8eb8-8beffa101f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056195975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1056195975
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2680152589
Short name T175
Test name
Test status
Simulation time 115323744 ps
CPU time 1.78 seconds
Started Apr 23 01:12:16 PM PDT 24
Finished Apr 23 01:12:18 PM PDT 24
Peak memory 209112 kb
Host smart-4f209954-4b88-46b6-af6b-c08dcc8d034b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680152589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2680152589
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3615195910
Short name T298
Test name
Test status
Simulation time 108386556 ps
CPU time 5.07 seconds
Started Apr 23 01:12:15 PM PDT 24
Finished Apr 23 01:12:21 PM PDT 24
Peak memory 217608 kb
Host smart-f5df676d-f7bd-4d02-822c-904a55fba788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615195910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3615195910
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1122277788
Short name T229
Test name
Test status
Simulation time 910854985 ps
CPU time 8.62 seconds
Started Apr 23 01:12:15 PM PDT 24
Finished Apr 23 01:12:24 PM PDT 24
Peak memory 225560 kb
Host smart-a93ca535-14b7-436c-a365-31aef74e8985
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122277788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1122277788
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3710008479
Short name T432
Test name
Test status
Simulation time 371021058 ps
CPU time 13.76 seconds
Started Apr 23 01:12:13 PM PDT 24
Finished Apr 23 01:12:27 PM PDT 24
Peak memory 217616 kb
Host smart-19498186-5a1b-440a-a626-967531dfd474
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710008479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3710008479
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1981597547
Short name T736
Test name
Test status
Simulation time 636149096 ps
CPU time 11.3 seconds
Started Apr 23 01:12:15 PM PDT 24
Finished Apr 23 01:12:27 PM PDT 24
Peak memory 217524 kb
Host smart-2a4ab2b2-ac6b-4711-bf45-cdfb24700965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981597547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1981597547
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3055613595
Short name T481
Test name
Test status
Simulation time 185951867 ps
CPU time 7.97 seconds
Started Apr 23 01:12:14 PM PDT 24
Finished Apr 23 01:12:23 PM PDT 24
Peak memory 217592 kb
Host smart-f6518e1c-56a0-4f07-b5d6-f6b39bfdb0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055613595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3055613595
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3588231008
Short name T451
Test name
Test status
Simulation time 278300257 ps
CPU time 1.97 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:12:12 PM PDT 24
Peak memory 213504 kb
Host smart-65a669d8-175f-4fd6-af0c-ca909be298f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588231008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3588231008
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3332602598
Short name T621
Test name
Test status
Simulation time 1326496774 ps
CPU time 24.11 seconds
Started Apr 23 01:12:11 PM PDT 24
Finished Apr 23 01:12:36 PM PDT 24
Peak memory 250556 kb
Host smart-a8ba2954-16b6-4164-8de3-761b29e53255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332602598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3332602598
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3197101915
Short name T699
Test name
Test status
Simulation time 750186315 ps
CPU time 9.05 seconds
Started Apr 23 01:12:10 PM PDT 24
Finished Apr 23 01:12:20 PM PDT 24
Peak memory 250612 kb
Host smart-1f2a301f-71f2-42d6-a1ad-a52d65ecdbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197101915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3197101915
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2112198519
Short name T509
Test name
Test status
Simulation time 9533718834 ps
CPU time 72.45 seconds
Started Apr 23 01:12:13 PM PDT 24
Finished Apr 23 01:13:26 PM PDT 24
Peak memory 228344 kb
Host smart-373b0c31-a852-45b1-92bb-32658af20cdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112198519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2112198519
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4054247264
Short name T783
Test name
Test status
Simulation time 14701402 ps
CPU time 1 seconds
Started Apr 23 01:12:13 PM PDT 24
Finished Apr 23 01:12:15 PM PDT 24
Peak memory 208548 kb
Host smart-41910b60-e0c0-428c-be9d-d6041c34092d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054247264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.4054247264
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3088882166
Short name T501
Test name
Test status
Simulation time 110296752 ps
CPU time 0.86 seconds
Started Apr 23 01:12:19 PM PDT 24
Finished Apr 23 01:12:20 PM PDT 24
Peak memory 209056 kb
Host smart-bb1cb092-7e05-4339-b7a9-e28bd6d76b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088882166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3088882166
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.312976491
Short name T295
Test name
Test status
Simulation time 2440213171 ps
CPU time 11.84 seconds
Started Apr 23 01:12:18 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 225632 kb
Host smart-6c0d050a-0545-4e90-8411-22a59ca899ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312976491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.312976491
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1528087097
Short name T28
Test name
Test status
Simulation time 449175842 ps
CPU time 5.51 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:27 PM PDT 24
Peak memory 209240 kb
Host smart-11300189-c89e-4243-bd25-cfecdfe188ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528087097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1528087097
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.467140469
Short name T238
Test name
Test status
Simulation time 57559815 ps
CPU time 2.76 seconds
Started Apr 23 01:12:18 PM PDT 24
Finished Apr 23 01:12:22 PM PDT 24
Peak memory 217592 kb
Host smart-3db28a88-dbce-4383-8379-405a6b568ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467140469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.467140469
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.4220014060
Short name T627
Test name
Test status
Simulation time 1798479586 ps
CPU time 16.31 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:37 PM PDT 24
Peak memory 225608 kb
Host smart-8290e31e-0a48-4f0e-9118-20842449f8c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220014060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.4220014060
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1817017656
Short name T537
Test name
Test status
Simulation time 5656452514 ps
CPU time 15.85 seconds
Started Apr 23 01:12:18 PM PDT 24
Finished Apr 23 01:12:34 PM PDT 24
Peak memory 217784 kb
Host smart-8420487e-9467-4b18-a6c6-f8484da12642
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817017656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1817017656
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1284167579
Short name T253
Test name
Test status
Simulation time 265453460 ps
CPU time 7.42 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:29 PM PDT 24
Peak memory 217596 kb
Host smart-a2606a44-efb7-4b1e-8fbc-6381a5bb9422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284167579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1284167579
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2210469248
Short name T665
Test name
Test status
Simulation time 769134787 ps
CPU time 9.32 seconds
Started Apr 23 01:12:22 PM PDT 24
Finished Apr 23 01:12:32 PM PDT 24
Peak memory 217720 kb
Host smart-03052306-4135-4a5f-be5b-05e039aa8634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210469248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2210469248
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4263096764
Short name T700
Test name
Test status
Simulation time 28359908 ps
CPU time 1.59 seconds
Started Apr 23 01:12:19 PM PDT 24
Finished Apr 23 01:12:21 PM PDT 24
Peak memory 213100 kb
Host smart-9e78fa31-7e31-40f8-a140-ebc6858bcf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263096764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4263096764
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2874380074
Short name T355
Test name
Test status
Simulation time 246824270 ps
CPU time 33.65 seconds
Started Apr 23 01:12:14 PM PDT 24
Finished Apr 23 01:12:48 PM PDT 24
Peak memory 250596 kb
Host smart-6f115ba3-a71f-44e7-9dc5-94ad852bfc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874380074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2874380074
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.513820177
Short name T163
Test name
Test status
Simulation time 50168312 ps
CPU time 5.88 seconds
Started Apr 23 01:12:13 PM PDT 24
Finished Apr 23 01:12:19 PM PDT 24
Peak memory 242504 kb
Host smart-0fa15696-6b69-4473-add5-f9ad22472db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513820177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.513820177
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1348211546
Short name T635
Test name
Test status
Simulation time 10585803337 ps
CPU time 119.38 seconds
Started Apr 23 01:12:18 PM PDT 24
Finished Apr 23 01:14:18 PM PDT 24
Peak memory 283376 kb
Host smart-01b9fdb1-5fc7-4f1c-add0-e24991fadab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348211546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1348211546
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1284411521
Short name T154
Test name
Test status
Simulation time 48284903956 ps
CPU time 440.42 seconds
Started Apr 23 01:12:43 PM PDT 24
Finished Apr 23 01:20:04 PM PDT 24
Peak memory 284196 kb
Host smart-e34b933e-383d-4561-b2cb-f2cdb19963c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1284411521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1284411521
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3294893908
Short name T461
Test name
Test status
Simulation time 42784933 ps
CPU time 1.05 seconds
Started Apr 23 01:12:15 PM PDT 24
Finished Apr 23 01:12:16 PM PDT 24
Peak memory 211236 kb
Host smart-86fb24ee-bfd4-4f24-af59-adc5ce638436
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294893908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3294893908
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3548894859
Short name T237
Test name
Test status
Simulation time 16370826 ps
CPU time 0.95 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:21 PM PDT 24
Peak memory 209128 kb
Host smart-bf01e711-104b-4065-a8d9-0d1703f3191d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548894859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3548894859
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.937779237
Short name T595
Test name
Test status
Simulation time 1209277839 ps
CPU time 13.5 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:34 PM PDT 24
Peak memory 225696 kb
Host smart-8db8f4e0-096d-46cc-8762-9c2e411c0b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937779237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.937779237
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.847513853
Short name T64
Test name
Test status
Simulation time 333258797 ps
CPU time 2.74 seconds
Started Apr 23 01:12:17 PM PDT 24
Finished Apr 23 01:12:20 PM PDT 24
Peak memory 209064 kb
Host smart-7dd9ca8a-2780-4d48-b0cb-c10e17598561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847513853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.847513853
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1501536503
Short name T383
Test name
Test status
Simulation time 104596100 ps
CPU time 4.18 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:26 PM PDT 24
Peak memory 217504 kb
Host smart-94f825cb-430d-41ff-ab8e-280ed62e5135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501536503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1501536503
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.541033923
Short name T866
Test name
Test status
Simulation time 2998688304 ps
CPU time 19.46 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:40 PM PDT 24
Peak memory 218600 kb
Host smart-ea5a5736-1659-47e9-a90c-7bba66c9ad49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541033923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.541033923
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3224534735
Short name T272
Test name
Test status
Simulation time 3257526702 ps
CPU time 9.25 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 217732 kb
Host smart-4e85f083-de67-48bb-8211-a7bc92243de6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224534735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3224534735
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.32328700
Short name T515
Test name
Test status
Simulation time 842294279 ps
CPU time 14.02 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:34 PM PDT 24
Peak memory 217596 kb
Host smart-c4bcb220-77f3-4fc8-828a-1b3392fb8161
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32328700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.32328700
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3390632870
Short name T55
Test name
Test status
Simulation time 959551827 ps
CPU time 8.61 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:29 PM PDT 24
Peak memory 217648 kb
Host smart-6709f4c4-4ff9-4407-97c1-d7b6190610d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390632870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3390632870
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1988186752
Short name T316
Test name
Test status
Simulation time 707445005 ps
CPU time 3.15 seconds
Started Apr 23 01:12:17 PM PDT 24
Finished Apr 23 01:12:21 PM PDT 24
Peak memory 217388 kb
Host smart-356d31be-c956-4555-87b2-33b6b687465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988186752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1988186752
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1224955456
Short name T496
Test name
Test status
Simulation time 1599370200 ps
CPU time 18.27 seconds
Started Apr 23 01:12:19 PM PDT 24
Finished Apr 23 01:12:37 PM PDT 24
Peak memory 250640 kb
Host smart-55db1413-9511-4321-aee7-498dd288dd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224955456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1224955456
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2055108094
Short name T546
Test name
Test status
Simulation time 604822329 ps
CPU time 7.35 seconds
Started Apr 23 01:12:20 PM PDT 24
Finished Apr 23 01:12:28 PM PDT 24
Peak memory 246260 kb
Host smart-507b3911-b33c-47c6-96fc-9d3978f39bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055108094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2055108094
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2496176337
Short name T609
Test name
Test status
Simulation time 11256079906 ps
CPU time 307.27 seconds
Started Apr 23 01:12:23 PM PDT 24
Finished Apr 23 01:17:30 PM PDT 24
Peak memory 272780 kb
Host smart-227c6d0f-4677-4ee6-b00f-b8bb93d7a6e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496176337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2496176337
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2526481062
Short name T846
Test name
Test status
Simulation time 50739090 ps
CPU time 0.81 seconds
Started Apr 23 01:12:19 PM PDT 24
Finished Apr 23 01:12:20 PM PDT 24
Peak memory 208160 kb
Host smart-8236ee8e-b2b6-4d7f-ac9a-f510ea8ff225
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526481062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2526481062
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1268964496
Short name T789
Test name
Test status
Simulation time 47456644 ps
CPU time 1 seconds
Started Apr 23 01:12:25 PM PDT 24
Finished Apr 23 01:12:27 PM PDT 24
Peak memory 209228 kb
Host smart-ba77712c-f1a4-45c0-83c4-02ae7ec0b74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268964496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1268964496
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.267793045
Short name T788
Test name
Test status
Simulation time 1080552737 ps
CPU time 10.09 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:32 PM PDT 24
Peak memory 217548 kb
Host smart-b0769720-9ba3-4cad-bccc-8dd6ef3b1f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267793045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.267793045
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2149717024
Short name T471
Test name
Test status
Simulation time 1240437349 ps
CPU time 1.94 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:24 PM PDT 24
Peak memory 216484 kb
Host smart-b190d2c4-d3b4-4eda-8341-e28365a248cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149717024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2149717024
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.480041406
Short name T488
Test name
Test status
Simulation time 321128364 ps
CPU time 4.24 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:26 PM PDT 24
Peak memory 217580 kb
Host smart-11d52a4e-9de0-4c6e-8b05-400027188e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480041406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.480041406
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3805724032
Short name T434
Test name
Test status
Simulation time 2454756685 ps
CPU time 15.78 seconds
Started Apr 23 01:12:22 PM PDT 24
Finished Apr 23 01:12:38 PM PDT 24
Peak memory 218540 kb
Host smart-8abeaf81-f6c9-4b99-b283-d5716bb90fff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805724032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3805724032
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1954111694
Short name T476
Test name
Test status
Simulation time 300891708 ps
CPU time 13.61 seconds
Started Apr 23 01:12:25 PM PDT 24
Finished Apr 23 01:12:39 PM PDT 24
Peak memory 217560 kb
Host smart-f74d2f7c-9e70-420c-b7f3-3fa1faa409b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954111694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1954111694
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2472264916
Short name T762
Test name
Test status
Simulation time 323719160 ps
CPU time 8.34 seconds
Started Apr 23 01:12:22 PM PDT 24
Finished Apr 23 01:12:31 PM PDT 24
Peak memory 217608 kb
Host smart-3efbc747-c8dd-4675-af93-7d9e59835cab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472264916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2472264916
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3909078806
Short name T671
Test name
Test status
Simulation time 605453734 ps
CPU time 11.87 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:34 PM PDT 24
Peak memory 217608 kb
Host smart-92edceb6-7b68-4d99-9607-9bbdaf601b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909078806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3909078806
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.724275362
Short name T520
Test name
Test status
Simulation time 524773479 ps
CPU time 4.49 seconds
Started Apr 23 01:12:23 PM PDT 24
Finished Apr 23 01:12:28 PM PDT 24
Peak memory 217368 kb
Host smart-9604691a-6517-4285-940f-7c64b82b761a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724275362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.724275362
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.579332339
Short name T708
Test name
Test status
Simulation time 248599299 ps
CPU time 21.97 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:44 PM PDT 24
Peak memory 250576 kb
Host smart-af71548c-a95d-43fb-9519-7087c20c61dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579332339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.579332339
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2584161898
Short name T489
Test name
Test status
Simulation time 69548193 ps
CPU time 4.31 seconds
Started Apr 23 01:12:21 PM PDT 24
Finished Apr 23 01:12:27 PM PDT 24
Peak memory 222300 kb
Host smart-a6a63854-07e1-456a-8dd1-6d0fcc8d6222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584161898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2584161898
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.983699049
Short name T262
Test name
Test status
Simulation time 4930532473 ps
CPU time 168.6 seconds
Started Apr 23 01:12:26 PM PDT 24
Finished Apr 23 01:15:15 PM PDT 24
Peak memory 281548 kb
Host smart-90ae2f10-5ce2-4ae9-b71c-f0d0b3a52202
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983699049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.983699049
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3068813320
Short name T824
Test name
Test status
Simulation time 36435580720 ps
CPU time 353.82 seconds
Started Apr 23 01:12:26 PM PDT 24
Finished Apr 23 01:18:21 PM PDT 24
Peak memory 372612 kb
Host smart-4afcaa8b-90bb-4588-89c1-9fa770d5280f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3068813320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3068813320
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3477833027
Short name T637
Test name
Test status
Simulation time 23566933 ps
CPU time 0.92 seconds
Started Apr 23 01:12:22 PM PDT 24
Finished Apr 23 01:12:24 PM PDT 24
Peak memory 208444 kb
Host smart-9a0fed22-a11b-4387-9fe3-3044d87f9b1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477833027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3477833027
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1698587662
Short name T776
Test name
Test status
Simulation time 53942794 ps
CPU time 0.95 seconds
Started Apr 23 01:12:29 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 209168 kb
Host smart-cf2f7d12-009f-49fe-b36e-6ec1685a9022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698587662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1698587662
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1391409176
Short name T334
Test name
Test status
Simulation time 1160497108 ps
CPU time 9.8 seconds
Started Apr 23 01:12:25 PM PDT 24
Finished Apr 23 01:12:36 PM PDT 24
Peak memory 217480 kb
Host smart-8ea8c268-5cba-4002-9017-412030a5d1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391409176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1391409176
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3123081741
Short name T332
Test name
Test status
Simulation time 207219782 ps
CPU time 3.49 seconds
Started Apr 23 01:12:26 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 216604 kb
Host smart-c20a3772-053a-4b73-a0bc-1ce37d30b298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123081741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3123081741
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3474985330
Short name T826
Test name
Test status
Simulation time 194207877 ps
CPU time 2.4 seconds
Started Apr 23 01:12:29 PM PDT 24
Finished Apr 23 01:12:32 PM PDT 24
Peak memory 217536 kb
Host smart-661283ce-dec9-44c4-a190-715d198f8236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474985330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3474985330
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1483340613
Short name T33
Test name
Test status
Simulation time 922760192 ps
CPU time 10.01 seconds
Started Apr 23 01:12:25 PM PDT 24
Finished Apr 23 01:12:35 PM PDT 24
Peak memory 218472 kb
Host smart-fda07c5c-805b-4269-a492-e92da3518fa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483340613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1483340613
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3473240964
Short name T486
Test name
Test status
Simulation time 4658456314 ps
CPU time 14.95 seconds
Started Apr 23 01:12:25 PM PDT 24
Finished Apr 23 01:12:40 PM PDT 24
Peak memory 217588 kb
Host smart-3915666b-3036-4c60-89ca-509e6d6b30c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473240964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3473240964
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2054831118
Short name T433
Test name
Test status
Simulation time 491196462 ps
CPU time 16.81 seconds
Started Apr 23 01:12:24 PM PDT 24
Finished Apr 23 01:12:41 PM PDT 24
Peak memory 217660 kb
Host smart-6ef1f615-9b6d-4a4e-a6c4-c9ba96822b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054831118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2054831118
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3130203868
Short name T203
Test name
Test status
Simulation time 275471825 ps
CPU time 7.32 seconds
Started Apr 23 01:12:25 PM PDT 24
Finished Apr 23 01:12:33 PM PDT 24
Peak memory 224588 kb
Host smart-f597b89e-aa7c-4ce7-9a3d-695d149e2d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130203868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3130203868
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2753573226
Short name T419
Test name
Test status
Simulation time 120256367 ps
CPU time 1.72 seconds
Started Apr 23 01:12:26 PM PDT 24
Finished Apr 23 01:12:29 PM PDT 24
Peak memory 213192 kb
Host smart-9ef8fc98-5ff6-4569-a8e8-ac0f651f3f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753573226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2753573226
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2772635668
Short name T315
Test name
Test status
Simulation time 735398590 ps
CPU time 21.69 seconds
Started Apr 23 01:12:23 PM PDT 24
Finished Apr 23 01:12:46 PM PDT 24
Peak memory 250540 kb
Host smart-4d725a20-01b9-4bd6-b02a-efab3afc5397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772635668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2772635668
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2304388284
Short name T424
Test name
Test status
Simulation time 236535781 ps
CPU time 2.85 seconds
Started Apr 23 01:12:25 PM PDT 24
Finished Apr 23 01:12:29 PM PDT 24
Peak memory 226012 kb
Host smart-60b99090-314f-4b37-aa4b-cf2f4acfd3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304388284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2304388284
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.565756414
Short name T82
Test name
Test status
Simulation time 4904785799 ps
CPU time 108.83 seconds
Started Apr 23 01:12:30 PM PDT 24
Finished Apr 23 01:14:19 PM PDT 24
Peak memory 283396 kb
Host smart-75ca7393-4f6b-47a6-acca-7f8ca5e61b1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565756414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.565756414
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1763462929
Short name T149
Test name
Test status
Simulation time 87685619606 ps
CPU time 1613.63 seconds
Started Apr 23 01:12:28 PM PDT 24
Finished Apr 23 01:39:23 PM PDT 24
Peak memory 496596 kb
Host smart-34a40f76-13d0-459b-b748-5f602b4729b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1763462929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1763462929
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.298280354
Short name T612
Test name
Test status
Simulation time 11940622 ps
CPU time 0.93 seconds
Started Apr 23 01:12:29 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 208240 kb
Host smart-b54ca502-c794-42c4-bd8e-0fa8e704baf2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298280354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.298280354
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2804228215
Short name T615
Test name
Test status
Simulation time 31282041 ps
CPU time 1.09 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:12:38 PM PDT 24
Peak memory 209180 kb
Host smart-df9528ff-5b9b-4743-8eb9-8befcc2762cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804228215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2804228215
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.84191248
Short name T41
Test name
Test status
Simulation time 1588965306 ps
CPU time 13.52 seconds
Started Apr 23 01:12:29 PM PDT 24
Finished Apr 23 01:12:43 PM PDT 24
Peak memory 225092 kb
Host smart-f0a12de4-9f86-4bb6-a66b-95b665b2ba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84191248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.84191248
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3106460855
Short name T368
Test name
Test status
Simulation time 349434831 ps
CPU time 4.65 seconds
Started Apr 23 01:12:28 PM PDT 24
Finished Apr 23 01:12:33 PM PDT 24
Peak memory 216492 kb
Host smart-bd9bee92-b503-4536-a12f-51326912c0f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106460855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3106460855
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2263893447
Short name T301
Test name
Test status
Simulation time 95309126 ps
CPU time 2.38 seconds
Started Apr 23 01:12:28 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 217584 kb
Host smart-db126440-8ea9-4504-8435-712589ee6a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263893447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2263893447
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.906467792
Short name T772
Test name
Test status
Simulation time 797093680 ps
CPU time 11.39 seconds
Started Apr 23 01:12:29 PM PDT 24
Finished Apr 23 01:12:41 PM PDT 24
Peak memory 217768 kb
Host smart-0f3f7ea7-0a7a-41f2-bfac-08039232c31e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906467792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.906467792
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3247968122
Short name T402
Test name
Test status
Simulation time 575250443 ps
CPU time 10.53 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:12:48 PM PDT 24
Peak memory 217556 kb
Host smart-ea82ccd1-dc4a-4760-b2bd-5ffa967bb1c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247968122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3247968122
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1320804055
Short name T275
Test name
Test status
Simulation time 429869793 ps
CPU time 9.87 seconds
Started Apr 23 01:12:33 PM PDT 24
Finished Apr 23 01:12:44 PM PDT 24
Peak memory 217560 kb
Host smart-bbb7192f-8d37-4256-8608-b6ffe4371270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320804055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1320804055
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4094329460
Short name T553
Test name
Test status
Simulation time 208579038 ps
CPU time 9.54 seconds
Started Apr 23 01:12:30 PM PDT 24
Finished Apr 23 01:12:40 PM PDT 24
Peak memory 217612 kb
Host smart-76ef1041-71a7-4e4f-aac6-795856905bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094329460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4094329460
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1103693971
Short name T735
Test name
Test status
Simulation time 148187649 ps
CPU time 2.68 seconds
Started Apr 23 01:12:30 PM PDT 24
Finished Apr 23 01:12:33 PM PDT 24
Peak memory 213620 kb
Host smart-1606569d-698b-4537-b24a-33a1b37b1034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103693971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1103693971
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1108347602
Short name T508
Test name
Test status
Simulation time 1095042270 ps
CPU time 22.18 seconds
Started Apr 23 01:12:27 PM PDT 24
Finished Apr 23 01:12:50 PM PDT 24
Peak memory 250596 kb
Host smart-c403bc37-7af7-462c-8b7c-d07a9ee9faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108347602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1108347602
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1261192130
Short name T257
Test name
Test status
Simulation time 201433928 ps
CPU time 7.27 seconds
Started Apr 23 01:12:29 PM PDT 24
Finished Apr 23 01:12:37 PM PDT 24
Peak memory 250132 kb
Host smart-56a89666-2eb9-47d2-86ce-0a0478f4f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261192130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1261192130
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2573578408
Short name T731
Test name
Test status
Simulation time 21274459716 ps
CPU time 155.65 seconds
Started Apr 23 01:12:34 PM PDT 24
Finished Apr 23 01:15:10 PM PDT 24
Peak memory 220672 kb
Host smart-ab7de9f0-b5d6-4fff-a1ef-72e324a34975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573578408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2573578408
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2887169726
Short name T43
Test name
Test status
Simulation time 24144578 ps
CPU time 0.85 seconds
Started Apr 23 01:12:29 PM PDT 24
Finished Apr 23 01:12:30 PM PDT 24
Peak memory 208124 kb
Host smart-e318c1f2-16c5-434a-86e4-d442dbe23c38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887169726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2887169726
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1891241650
Short name T283
Test name
Test status
Simulation time 13113022 ps
CPU time 0.91 seconds
Started Apr 23 01:12:37 PM PDT 24
Finished Apr 23 01:12:39 PM PDT 24
Peak memory 209244 kb
Host smart-c14a8e58-055b-4502-86b9-4181bcfb6e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891241650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1891241650
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3635166793
Short name T268
Test name
Test status
Simulation time 264623899 ps
CPU time 13.36 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:12:50 PM PDT 24
Peak memory 217524 kb
Host smart-e46f4400-ac85-4204-a8f5-42b2f23934aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635166793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3635166793
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1758239690
Short name T482
Test name
Test status
Simulation time 2280217653 ps
CPU time 11.82 seconds
Started Apr 23 01:12:32 PM PDT 24
Finished Apr 23 01:12:45 PM PDT 24
Peak memory 209140 kb
Host smart-0b0d310e-d98e-42b8-9391-75f138519db1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758239690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1758239690
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3948353371
Short name T856
Test name
Test status
Simulation time 62101571 ps
CPU time 3.51 seconds
Started Apr 23 01:12:33 PM PDT 24
Finished Apr 23 01:12:37 PM PDT 24
Peak memory 217508 kb
Host smart-5fa65d76-9561-4e8b-885c-f24094e275c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948353371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3948353371
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1314670207
Short name T256
Test name
Test status
Simulation time 1442022262 ps
CPU time 14.2 seconds
Started Apr 23 01:12:34 PM PDT 24
Finished Apr 23 01:12:48 PM PDT 24
Peak memory 225648 kb
Host smart-72dc2fb3-0101-4b33-9e94-7926e6d5e812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314670207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1314670207
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3854086074
Short name T421
Test name
Test status
Simulation time 1683108610 ps
CPU time 10.7 seconds
Started Apr 23 01:12:35 PM PDT 24
Finished Apr 23 01:12:46 PM PDT 24
Peak memory 217560 kb
Host smart-d85b0136-c4de-4455-adfe-b6519e05f849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854086074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3854086074
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2940148287
Short name T683
Test name
Test status
Simulation time 278158816 ps
CPU time 11.47 seconds
Started Apr 23 01:12:34 PM PDT 24
Finished Apr 23 01:12:46 PM PDT 24
Peak memory 217512 kb
Host smart-e0dd0d6b-320b-4738-8e48-2e06eac1275e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940148287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2940148287
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1992043219
Short name T392
Test name
Test status
Simulation time 1270285688 ps
CPU time 7.42 seconds
Started Apr 23 01:12:35 PM PDT 24
Finished Apr 23 01:12:43 PM PDT 24
Peak memory 217604 kb
Host smart-8c398ea3-78f9-425d-b462-b17b007b25ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992043219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1992043219
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1984421509
Short name T347
Test name
Test status
Simulation time 566861936 ps
CPU time 3.14 seconds
Started Apr 23 01:12:35 PM PDT 24
Finished Apr 23 01:12:38 PM PDT 24
Peak memory 214256 kb
Host smart-bec828fc-d1d8-4c46-bb37-db9985ffd917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984421509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1984421509
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.199317381
Short name T597
Test name
Test status
Simulation time 181139026 ps
CPU time 16.86 seconds
Started Apr 23 01:12:34 PM PDT 24
Finished Apr 23 01:12:52 PM PDT 24
Peak memory 250620 kb
Host smart-8ed31fd5-2154-4a87-82da-795abe35c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199317381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.199317381
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.701507572
Short name T335
Test name
Test status
Simulation time 175043094 ps
CPU time 7.81 seconds
Started Apr 23 01:12:34 PM PDT 24
Finished Apr 23 01:12:43 PM PDT 24
Peak memory 250024 kb
Host smart-54bbc9ff-020b-4d51-8f40-32b4312d7d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701507572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.701507572
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1914712113
Short name T643
Test name
Test status
Simulation time 4512753589 ps
CPU time 141.48 seconds
Started Apr 23 01:12:33 PM PDT 24
Finished Apr 23 01:14:55 PM PDT 24
Peak memory 254688 kb
Host smart-82021b3c-c85f-42fc-9fb4-2e1f0527315e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914712113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1914712113
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2862391196
Short name T531
Test name
Test status
Simulation time 13843871 ps
CPU time 1.12 seconds
Started Apr 23 01:12:35 PM PDT 24
Finished Apr 23 01:12:37 PM PDT 24
Peak memory 211220 kb
Host smart-16194186-0a6e-4b0e-9dfa-c0b7392bb527
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862391196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2862391196
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.338665205
Short name T66
Test name
Test status
Simulation time 17546857 ps
CPU time 1.19 seconds
Started Apr 23 01:12:42 PM PDT 24
Finished Apr 23 01:12:43 PM PDT 24
Peak memory 209156 kb
Host smart-301e9f80-4ec6-4516-ba5d-8fd501d0a274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338665205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.338665205
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2270502645
Short name T96
Test name
Test status
Simulation time 498776966 ps
CPU time 11.39 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:12:49 PM PDT 24
Peak memory 225632 kb
Host smart-54139211-1a0a-4d5f-9f68-6b069db6846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270502645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2270502645
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3974912749
Short name T29
Test name
Test status
Simulation time 125829538 ps
CPU time 2.57 seconds
Started Apr 23 01:12:35 PM PDT 24
Finished Apr 23 01:12:39 PM PDT 24
Peak memory 209088 kb
Host smart-e0edc087-2f99-4a91-b9e9-759e5ce8d6f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974912749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3974912749
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4263195907
Short name T208
Test name
Test status
Simulation time 325745328 ps
CPU time 4 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:12:41 PM PDT 24
Peak memory 217588 kb
Host smart-048f3f2e-58ae-4019-9e7c-7feea8bbc898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263195907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4263195907
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.528017473
Short name T751
Test name
Test status
Simulation time 230748080 ps
CPU time 10.47 seconds
Started Apr 23 01:12:37 PM PDT 24
Finished Apr 23 01:12:48 PM PDT 24
Peak memory 217516 kb
Host smart-099e0f85-3790-41fb-b142-1cb20e9019fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528017473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.528017473
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1235427303
Short name T604
Test name
Test status
Simulation time 2504164110 ps
CPU time 11.93 seconds
Started Apr 23 01:12:37 PM PDT 24
Finished Apr 23 01:12:50 PM PDT 24
Peak memory 217616 kb
Host smart-695ead2a-7958-488a-b96a-3d230a587d45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235427303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1235427303
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4052977776
Short name T718
Test name
Test status
Simulation time 3730111074 ps
CPU time 10.79 seconds
Started Apr 23 01:12:37 PM PDT 24
Finished Apr 23 01:12:48 PM PDT 24
Peak memory 217720 kb
Host smart-d7df993e-5be5-4a7c-b3f1-0c3fbadfef3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052977776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4052977776
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1963132704
Short name T60
Test name
Test status
Simulation time 3089070394 ps
CPU time 10.14 seconds
Started Apr 23 01:12:35 PM PDT 24
Finished Apr 23 01:12:46 PM PDT 24
Peak memory 217680 kb
Host smart-b7d548b6-2d43-4ce5-a4bf-3688a2b0e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963132704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1963132704
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.221716752
Short name T749
Test name
Test status
Simulation time 70276256 ps
CPU time 1.58 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:12:39 PM PDT 24
Peak memory 217364 kb
Host smart-3c30a6ca-a190-4323-ba52-998fbd913a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221716752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.221716752
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3477930359
Short name T457
Test name
Test status
Simulation time 572908647 ps
CPU time 24.87 seconds
Started Apr 23 01:12:37 PM PDT 24
Finished Apr 23 01:13:03 PM PDT 24
Peak memory 250588 kb
Host smart-b6029607-37cb-4f73-b61a-e0acaa0ee152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477930359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3477930359
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2004366566
Short name T264
Test name
Test status
Simulation time 324712867 ps
CPU time 6.9 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:12:44 PM PDT 24
Peak memory 246452 kb
Host smart-c373975c-3daa-494f-94b2-88ad2e708713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004366566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2004366566
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.432363246
Short name T505
Test name
Test status
Simulation time 19081278744 ps
CPU time 555.72 seconds
Started Apr 23 01:12:36 PM PDT 24
Finished Apr 23 01:21:53 PM PDT 24
Peak memory 258832 kb
Host smart-1e3dd100-b772-4332-894d-f1fd9aae50cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432363246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.432363246
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.342345070
Short name T71
Test name
Test status
Simulation time 48640338 ps
CPU time 1.51 seconds
Started Apr 23 01:12:35 PM PDT 24
Finished Apr 23 01:12:38 PM PDT 24
Peak memory 212316 kb
Host smart-be654c1a-4c9a-47a7-a02b-fc1b000474f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342345070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.342345070
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3737999017
Short name T807
Test name
Test status
Simulation time 401969920 ps
CPU time 1.24 seconds
Started Apr 23 01:12:44 PM PDT 24
Finished Apr 23 01:12:46 PM PDT 24
Peak memory 209096 kb
Host smart-db0b64a4-f6e5-4de3-89fe-ef13fe0fe183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737999017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3737999017
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3361752242
Short name T503
Test name
Test status
Simulation time 709604937 ps
CPU time 7.49 seconds
Started Apr 23 01:12:49 PM PDT 24
Finished Apr 23 01:12:57 PM PDT 24
Peak memory 217460 kb
Host smart-30e66e01-f6bf-4ddb-9d10-94ff427b2aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361752242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3361752242
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1035526455
Short name T838
Test name
Test status
Simulation time 283748531 ps
CPU time 7.53 seconds
Started Apr 23 01:12:48 PM PDT 24
Finished Apr 23 01:12:56 PM PDT 24
Peak memory 209152 kb
Host smart-bec473be-de43-4d71-9772-4301aee23289
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035526455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1035526455
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3216282505
Short name T306
Test name
Test status
Simulation time 19717979 ps
CPU time 1.45 seconds
Started Apr 23 01:12:40 PM PDT 24
Finished Apr 23 01:12:43 PM PDT 24
Peak memory 217552 kb
Host smart-19e5c843-73fa-4b97-a2da-507714534cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216282505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3216282505
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1074202470
Short name T676
Test name
Test status
Simulation time 363810259 ps
CPU time 15.38 seconds
Started Apr 23 01:12:45 PM PDT 24
Finished Apr 23 01:13:01 PM PDT 24
Peak memory 225544 kb
Host smart-6c4c3303-e305-49b6-a278-b7aaa8e488d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074202470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1074202470
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3107088737
Short name T375
Test name
Test status
Simulation time 337735179 ps
CPU time 11.15 seconds
Started Apr 23 01:12:48 PM PDT 24
Finished Apr 23 01:13:00 PM PDT 24
Peak memory 217580 kb
Host smart-1b6d1bd0-e571-4909-9296-7fe76a1fe67e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107088737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3107088737
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1692837505
Short name T16
Test name
Test status
Simulation time 465400172 ps
CPU time 9.92 seconds
Started Apr 23 01:12:49 PM PDT 24
Finished Apr 23 01:13:00 PM PDT 24
Peak memory 217584 kb
Host smart-0aa55fe0-446a-45b7-bdaf-eb2a8c8a19bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692837505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1692837505
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2395703444
Short name T59
Test name
Test status
Simulation time 533330233 ps
CPU time 8.5 seconds
Started Apr 23 01:12:43 PM PDT 24
Finished Apr 23 01:12:52 PM PDT 24
Peak memory 217588 kb
Host smart-60b96c78-c18d-4a2d-a190-dc3c9eba00ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395703444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2395703444
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.315340723
Short name T765
Test name
Test status
Simulation time 193421631 ps
CPU time 2.32 seconds
Started Apr 23 01:12:38 PM PDT 24
Finished Apr 23 01:12:41 PM PDT 24
Peak memory 213336 kb
Host smart-04e11258-5f24-4b4d-a0da-a462916b45f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315340723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.315340723
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.4290526632
Short name T85
Test name
Test status
Simulation time 920610182 ps
CPU time 23.08 seconds
Started Apr 23 01:12:40 PM PDT 24
Finished Apr 23 01:13:04 PM PDT 24
Peak memory 250564 kb
Host smart-6cea318b-c15d-4d6c-accf-5c7b699df512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290526632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4290526632
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.256709016
Short name T414
Test name
Test status
Simulation time 94854717 ps
CPU time 2.54 seconds
Started Apr 23 01:12:38 PM PDT 24
Finished Apr 23 01:12:41 PM PDT 24
Peak memory 221616 kb
Host smart-265fd04e-94d6-40b2-b464-a0b0d88a1b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256709016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.256709016
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2621564509
Short name T378
Test name
Test status
Simulation time 3752285746 ps
CPU time 67.91 seconds
Started Apr 23 01:12:46 PM PDT 24
Finished Apr 23 01:13:55 PM PDT 24
Peak memory 250656 kb
Host smart-a75cf984-0a15-42e1-9af3-a033ca11354a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621564509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2621564509
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2510824890
Short name T48
Test name
Test status
Simulation time 293895699768 ps
CPU time 1411.93 seconds
Started Apr 23 01:12:49 PM PDT 24
Finished Apr 23 01:36:21 PM PDT 24
Peak memory 283504 kb
Host smart-bf31ea22-379a-43b1-a378-c5875fb4f78f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2510824890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2510824890
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1203164068
Short name T792
Test name
Test status
Simulation time 39402599 ps
CPU time 0.89 seconds
Started Apr 23 01:12:39 PM PDT 24
Finished Apr 23 01:12:40 PM PDT 24
Peak memory 211284 kb
Host smart-524c6259-ffb8-4a43-9b8a-5870911b5850
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203164068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1203164068
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.914426890
Short name T333
Test name
Test status
Simulation time 170261410 ps
CPU time 0.94 seconds
Started Apr 23 01:12:47 PM PDT 24
Finished Apr 23 01:12:49 PM PDT 24
Peak memory 209184 kb
Host smart-44b741a9-3a85-4225-8ed1-1b6e8985e1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914426890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.914426890
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1369425676
Short name T357
Test name
Test status
Simulation time 796181997 ps
CPU time 18.09 seconds
Started Apr 23 01:12:43 PM PDT 24
Finished Apr 23 01:13:01 PM PDT 24
Peak memory 225648 kb
Host smart-ac1d0da1-9a4f-491c-b51c-3aac520861b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369425676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1369425676
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2223028588
Short name T369
Test name
Test status
Simulation time 360650135 ps
CPU time 1.75 seconds
Started Apr 23 01:12:44 PM PDT 24
Finished Apr 23 01:12:46 PM PDT 24
Peak memory 209080 kb
Host smart-e6950258-99e9-482e-aac1-729ca632869b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223028588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2223028588
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4217936308
Short name T381
Test name
Test status
Simulation time 36116783 ps
CPU time 1.63 seconds
Started Apr 23 01:12:49 PM PDT 24
Finished Apr 23 01:12:51 PM PDT 24
Peak memory 217560 kb
Host smart-35dae5ea-e2fa-4364-8ea6-4402c973b270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217936308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4217936308
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3884403078
Short name T688
Test name
Test status
Simulation time 1566225812 ps
CPU time 12.51 seconds
Started Apr 23 01:12:43 PM PDT 24
Finished Apr 23 01:12:56 PM PDT 24
Peak memory 225564 kb
Host smart-41570978-e7a0-4863-a1da-6c56e9b46819
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884403078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3884403078
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.4119436821
Short name T284
Test name
Test status
Simulation time 1967373462 ps
CPU time 10.06 seconds
Started Apr 23 01:12:48 PM PDT 24
Finished Apr 23 01:12:58 PM PDT 24
Peak memory 217556 kb
Host smart-b1b00a29-7fcd-463c-a589-9c225618f152
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119436821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.4119436821
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1344241867
Short name T259
Test name
Test status
Simulation time 6991312345 ps
CPU time 9.21 seconds
Started Apr 23 01:12:47 PM PDT 24
Finished Apr 23 01:12:57 PM PDT 24
Peak memory 217608 kb
Host smart-5bc3ac6d-fba6-4b8b-9d86-dc5798ac9d04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344241867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1344241867
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1697610775
Short name T711
Test name
Test status
Simulation time 2927585861 ps
CPU time 8.79 seconds
Started Apr 23 01:12:43 PM PDT 24
Finished Apr 23 01:12:53 PM PDT 24
Peak memory 224956 kb
Host smart-5fd06a19-7677-47ef-9064-f2bb617e5ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697610775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1697610775
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2440828048
Short name T425
Test name
Test status
Simulation time 99015206 ps
CPU time 1.73 seconds
Started Apr 23 01:12:42 PM PDT 24
Finished Apr 23 01:12:44 PM PDT 24
Peak memory 217436 kb
Host smart-514c80de-de12-4b60-a40f-14a5ff876824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440828048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2440828048
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1585675860
Short name T261
Test name
Test status
Simulation time 207665621 ps
CPU time 16.31 seconds
Started Apr 23 01:12:44 PM PDT 24
Finished Apr 23 01:13:01 PM PDT 24
Peak memory 250440 kb
Host smart-1f8566fa-9d50-4786-aa9a-71ddf5d47843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585675860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1585675860
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2400429202
Short name T633
Test name
Test status
Simulation time 45112892 ps
CPU time 7.01 seconds
Started Apr 23 01:12:46 PM PDT 24
Finished Apr 23 01:12:53 PM PDT 24
Peak memory 250580 kb
Host smart-b83868fa-7e05-499b-935b-bf8e710ec43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400429202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2400429202
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1412048892
Short name T346
Test name
Test status
Simulation time 25643172187 ps
CPU time 200.49 seconds
Started Apr 23 01:12:48 PM PDT 24
Finished Apr 23 01:16:09 PM PDT 24
Peak memory 277672 kb
Host smart-dcf9e722-fae9-4613-9f0e-3d5b700bba26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412048892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1412048892
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.695077716
Short name T500
Test name
Test status
Simulation time 38865338 ps
CPU time 0.88 seconds
Started Apr 23 01:12:44 PM PDT 24
Finished Apr 23 01:12:45 PM PDT 24
Peak memory 211212 kb
Host smart-62f412c2-eb07-4222-a95e-00faa92135e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695077716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.695077716
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1259033404
Short name T68
Test name
Test status
Simulation time 53829779 ps
CPU time 1.06 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:47 PM PDT 24
Peak memory 209208 kb
Host smart-66d3d25c-c204-49b4-a126-8bd7df4110e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259033404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1259033404
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2793295082
Short name T62
Test name
Test status
Simulation time 5060857995 ps
CPU time 13.56 seconds
Started Apr 23 01:10:35 PM PDT 24
Finished Apr 23 01:10:50 PM PDT 24
Peak memory 217948 kb
Host smart-4fa73291-3800-4251-a76d-0e17f55776cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793295082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2793295082
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.942544037
Short name T658
Test name
Test status
Simulation time 460445216 ps
CPU time 8.84 seconds
Started Apr 23 01:10:41 PM PDT 24
Finished Apr 23 01:10:50 PM PDT 24
Peak memory 209164 kb
Host smart-d30388c3-760f-4a4c-ab1e-59575f437d4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942544037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.942544037
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.529152848
Short name T227
Test name
Test status
Simulation time 4877100774 ps
CPU time 22 seconds
Started Apr 23 01:10:41 PM PDT 24
Finished Apr 23 01:11:03 PM PDT 24
Peak memory 218520 kb
Host smart-35e98d4c-807d-455a-bb08-6ca9a33775c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529152848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.529152848
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.682747838
Short name T619
Test name
Test status
Simulation time 295371045 ps
CPU time 4.52 seconds
Started Apr 23 01:10:43 PM PDT 24
Finished Apr 23 01:10:48 PM PDT 24
Peak memory 217380 kb
Host smart-83130973-dd00-4055-9bad-3a2675762dbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682747838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.682747838
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1378341068
Short name T662
Test name
Test status
Simulation time 2299563045 ps
CPU time 8.6 seconds
Started Apr 23 01:10:39 PM PDT 24
Finished Apr 23 01:10:48 PM PDT 24
Peak memory 217500 kb
Host smart-dbeea9a1-7b1a-4c50-bcfa-2b43a509d585
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378341068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1378341068
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1303758407
Short name T764
Test name
Test status
Simulation time 1351944175 ps
CPU time 10.38 seconds
Started Apr 23 01:10:42 PM PDT 24
Finished Apr 23 01:10:53 PM PDT 24
Peak memory 212604 kb
Host smart-50c63353-771e-4dcc-ab54-a0da5dfcc3ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303758407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1303758407
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.271563059
Short name T373
Test name
Test status
Simulation time 205626947 ps
CPU time 3.91 seconds
Started Apr 23 01:10:42 PM PDT 24
Finished Apr 23 01:10:46 PM PDT 24
Peak memory 213020 kb
Host smart-bfcdc880-247b-4dc4-b993-f0de3c5a6925
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271563059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.271563059
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3792693389
Short name T228
Test name
Test status
Simulation time 16028784467 ps
CPU time 54.7 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:11:41 PM PDT 24
Peak memory 266988 kb
Host smart-86f45607-3c30-4602-b418-8bcb7996730d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792693389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3792693389
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1302292354
Short name T869
Test name
Test status
Simulation time 1598731329 ps
CPU time 15.83 seconds
Started Apr 23 01:10:36 PM PDT 24
Finished Apr 23 01:10:52 PM PDT 24
Peak memory 250516 kb
Host smart-792dc976-bf17-4260-8dae-bd9ebaf14fda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302292354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1302292354
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3012342550
Short name T810
Test name
Test status
Simulation time 88185361 ps
CPU time 3.42 seconds
Started Apr 23 01:10:36 PM PDT 24
Finished Apr 23 01:10:40 PM PDT 24
Peak memory 217544 kb
Host smart-f0ab76c5-74f2-4490-89ed-a135a786bd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012342550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3012342550
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3621438961
Short name T769
Test name
Test status
Simulation time 250044580 ps
CPU time 10.14 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 213332 kb
Host smart-39c7bce3-05f4-4cf4-98c9-6e2a4fce69af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621438961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3621438961
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1387884483
Short name T83
Test name
Test status
Simulation time 197203527 ps
CPU time 37.97 seconds
Started Apr 23 01:10:55 PM PDT 24
Finished Apr 23 01:11:34 PM PDT 24
Peak memory 268820 kb
Host smart-d70789df-f29c-4895-8add-ae831b8b316f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387884483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1387884483
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1849994186
Short name T842
Test name
Test status
Simulation time 1596460908 ps
CPU time 16.35 seconds
Started Apr 23 01:10:42 PM PDT 24
Finished Apr 23 01:10:59 PM PDT 24
Peak memory 217556 kb
Host smart-03d4ccc9-8278-4489-b069-9aef63c73671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849994186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1849994186
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1858708273
Short name T782
Test name
Test status
Simulation time 693698089 ps
CPU time 22.37 seconds
Started Apr 23 01:10:42 PM PDT 24
Finished Apr 23 01:11:05 PM PDT 24
Peak memory 217476 kb
Host smart-481d9daa-3366-4ead-8ca6-555b4544c6dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858708273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
858708273
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1023395856
Short name T870
Test name
Test status
Simulation time 1164084963 ps
CPU time 10.85 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:57 PM PDT 24
Peak memory 216976 kb
Host smart-66fadb69-a9e6-4f33-9a1e-97ae004619b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023395856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1023395856
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3033885451
Short name T290
Test name
Test status
Simulation time 188662193 ps
CPU time 7.34 seconds
Started Apr 23 01:10:38 PM PDT 24
Finished Apr 23 01:10:46 PM PDT 24
Peak memory 214132 kb
Host smart-e4904338-d377-4234-8f9d-d8c30df0654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033885451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3033885451
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2914500381
Short name T214
Test name
Test status
Simulation time 149442829 ps
CPU time 22.35 seconds
Started Apr 23 01:10:37 PM PDT 24
Finished Apr 23 01:11:00 PM PDT 24
Peak memory 250648 kb
Host smart-7dbedfe3-a65d-4f5a-bffb-5c40e38204d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914500381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2914500381
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3386514875
Short name T524
Test name
Test status
Simulation time 143896694 ps
CPU time 7.39 seconds
Started Apr 23 01:10:37 PM PDT 24
Finished Apr 23 01:10:45 PM PDT 24
Peak memory 250032 kb
Host smart-7fd7873b-161a-4e56-b69f-a39e60502891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386514875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3386514875
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1856687347
Short name T498
Test name
Test status
Simulation time 1857061479 ps
CPU time 78.27 seconds
Started Apr 23 01:10:42 PM PDT 24
Finished Apr 23 01:12:01 PM PDT 24
Peak memory 275336 kb
Host smart-070ad177-7a25-49d2-8372-c6d27780e99b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856687347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1856687347
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.187571789
Short name T654
Test name
Test status
Simulation time 27373845701 ps
CPU time 305.4 seconds
Started Apr 23 01:10:44 PM PDT 24
Finished Apr 23 01:15:50 PM PDT 24
Peak memory 283560 kb
Host smart-ab5201ce-2784-4b9b-bb2d-f06eb21145a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=187571789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.187571789
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1160050954
Short name T366
Test name
Test status
Simulation time 15324689 ps
CPU time 0.83 seconds
Started Apr 23 01:10:42 PM PDT 24
Finished Apr 23 01:10:43 PM PDT 24
Peak memory 208376 kb
Host smart-15bd0e62-59e9-4f38-afeb-4869279564d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160050954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1160050954
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1389060288
Short name T437
Test name
Test status
Simulation time 44315366 ps
CPU time 0.84 seconds
Started Apr 23 01:12:50 PM PDT 24
Finished Apr 23 01:12:52 PM PDT 24
Peak memory 209084 kb
Host smart-26b30024-541d-460f-b472-f6b83f7ad875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389060288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1389060288
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2077610600
Short name T452
Test name
Test status
Simulation time 451450057 ps
CPU time 17.98 seconds
Started Apr 23 01:12:48 PM PDT 24
Finished Apr 23 01:13:07 PM PDT 24
Peak memory 225672 kb
Host smart-50d84f8a-9ca9-4ce2-96c2-38bc0b8e54ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077610600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2077610600
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.808552700
Short name T88
Test name
Test status
Simulation time 520596312 ps
CPU time 6.27 seconds
Started Apr 23 01:12:49 PM PDT 24
Finished Apr 23 01:12:56 PM PDT 24
Peak memory 209156 kb
Host smart-89669cb6-4567-4dcc-b83b-bf2b05660b1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808552700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.808552700
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3683363986
Short name T448
Test name
Test status
Simulation time 28852467 ps
CPU time 1.9 seconds
Started Apr 23 01:12:46 PM PDT 24
Finished Apr 23 01:12:49 PM PDT 24
Peak memory 217700 kb
Host smart-725e3ce7-3f04-4b3e-931f-3ba1df2e559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683363986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3683363986
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.33484401
Short name T617
Test name
Test status
Simulation time 1158028905 ps
CPU time 11.91 seconds
Started Apr 23 01:12:47 PM PDT 24
Finished Apr 23 01:13:00 PM PDT 24
Peak memory 225520 kb
Host smart-96066d06-c9c2-4c08-a28b-1ea000432077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33484401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.33484401
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1424643275
Short name T358
Test name
Test status
Simulation time 4645243200 ps
CPU time 10.41 seconds
Started Apr 23 01:12:48 PM PDT 24
Finished Apr 23 01:12:59 PM PDT 24
Peak memory 217600 kb
Host smart-facb458d-b16b-491c-a75e-21446c95a9d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424643275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1424643275
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3427279046
Short name T675
Test name
Test status
Simulation time 1805895247 ps
CPU time 9.37 seconds
Started Apr 23 01:12:49 PM PDT 24
Finished Apr 23 01:12:59 PM PDT 24
Peak memory 217600 kb
Host smart-f6ea44c0-0838-4fe8-b697-7cbcff78d342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427279046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3427279046
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3980418522
Short name T758
Test name
Test status
Simulation time 3768747284 ps
CPU time 5.61 seconds
Started Apr 23 01:12:47 PM PDT 24
Finished Apr 23 01:12:53 PM PDT 24
Peak memory 217668 kb
Host smart-9dc3c43e-7c2d-4cbd-9207-9d6d9c31096b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980418522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3980418522
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1140989999
Short name T649
Test name
Test status
Simulation time 125628075 ps
CPU time 3.79 seconds
Started Apr 23 01:12:50 PM PDT 24
Finished Apr 23 01:12:55 PM PDT 24
Peak memory 217320 kb
Host smart-f4422e6b-cfa2-4fbc-bae4-13363591e9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140989999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1140989999
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1936565904
Short name T462
Test name
Test status
Simulation time 179073566 ps
CPU time 26.13 seconds
Started Apr 23 01:12:48 PM PDT 24
Finished Apr 23 01:13:15 PM PDT 24
Peak memory 250640 kb
Host smart-0eabf8bd-1846-4361-8ab0-8487e5947962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936565904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1936565904
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.231542420
Short name T271
Test name
Test status
Simulation time 60561936 ps
CPU time 6.59 seconds
Started Apr 23 01:12:50 PM PDT 24
Finished Apr 23 01:12:57 PM PDT 24
Peak memory 249832 kb
Host smart-2be23d54-0c6d-4183-a595-876bf7ffcc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231542420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.231542420
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1448911660
Short name T50
Test name
Test status
Simulation time 24821331284 ps
CPU time 162.81 seconds
Started Apr 23 01:12:46 PM PDT 24
Finished Apr 23 01:15:29 PM PDT 24
Peak memory 250688 kb
Host smart-40d2b65c-1086-4d2f-bf91-4acb89b193ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448911660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1448911660
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3932125636
Short name T506
Test name
Test status
Simulation time 14354674 ps
CPU time 1.09 seconds
Started Apr 23 01:12:47 PM PDT 24
Finished Apr 23 01:12:49 PM PDT 24
Peak memory 211196 kb
Host smart-31083d13-5535-4b4c-a6c5-4a20f5c73f2e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932125636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3932125636
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.803025553
Short name T518
Test name
Test status
Simulation time 61453847 ps
CPU time 0.87 seconds
Started Apr 23 01:12:55 PM PDT 24
Finished Apr 23 01:12:56 PM PDT 24
Peak memory 209180 kb
Host smart-4379604c-c603-475a-9bd8-82fa286d0a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803025553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.803025553
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.375889719
Short name T13
Test name
Test status
Simulation time 5836145873 ps
CPU time 14.06 seconds
Started Apr 23 01:12:52 PM PDT 24
Finished Apr 23 01:13:06 PM PDT 24
Peak memory 217868 kb
Host smart-3fb87772-3427-48d0-afa2-e73c8c8a4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375889719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.375889719
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.956599550
Short name T178
Test name
Test status
Simulation time 1210181127 ps
CPU time 9 seconds
Started Apr 23 01:12:51 PM PDT 24
Finished Apr 23 01:13:01 PM PDT 24
Peak memory 209120 kb
Host smart-49aa47c5-9197-4f66-9f0c-5c144693632b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956599550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.956599550
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2025481004
Short name T35
Test name
Test status
Simulation time 99689826 ps
CPU time 2.09 seconds
Started Apr 23 01:12:53 PM PDT 24
Finished Apr 23 01:12:55 PM PDT 24
Peak memory 217444 kb
Host smart-cf02a5ff-08da-4c46-8617-3b8a94eeb5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025481004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2025481004
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1031586592
Short name T832
Test name
Test status
Simulation time 443012177 ps
CPU time 14.6 seconds
Started Apr 23 01:12:52 PM PDT 24
Finished Apr 23 01:13:07 PM PDT 24
Peak memory 217772 kb
Host smart-5b181133-8e70-43b5-939d-5c566f947702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031586592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1031586592
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.351114788
Short name T548
Test name
Test status
Simulation time 366389195 ps
CPU time 15.24 seconds
Started Apr 23 01:12:55 PM PDT 24
Finished Apr 23 01:13:11 PM PDT 24
Peak memory 217552 kb
Host smart-b0b0d916-31f8-41dd-9e6e-8e96a9d3ab9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351114788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.351114788
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3405368650
Short name T638
Test name
Test status
Simulation time 2469758785 ps
CPU time 10.15 seconds
Started Apr 23 01:12:51 PM PDT 24
Finished Apr 23 01:13:02 PM PDT 24
Peak memory 217648 kb
Host smart-f63433ca-75b6-41a9-bce9-1a187339cd57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405368650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3405368650
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1415401133
Short name T205
Test name
Test status
Simulation time 863103805 ps
CPU time 16.13 seconds
Started Apr 23 01:12:52 PM PDT 24
Finished Apr 23 01:13:08 PM PDT 24
Peak memory 217584 kb
Host smart-532a9f56-9f5c-41b0-a7fc-af112e14d59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415401133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1415401133
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1661556655
Short name T403
Test name
Test status
Simulation time 84321823 ps
CPU time 4.01 seconds
Started Apr 23 01:12:52 PM PDT 24
Finished Apr 23 01:12:56 PM PDT 24
Peak memory 213980 kb
Host smart-f4431ac6-56f2-4877-9941-2b5ae5578dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661556655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1661556655
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3162863366
Short name T34
Test name
Test status
Simulation time 379353253 ps
CPU time 28.96 seconds
Started Apr 23 01:12:53 PM PDT 24
Finished Apr 23 01:13:23 PM PDT 24
Peak memory 250584 kb
Host smart-0fe0b8e5-1f34-4b02-b0b5-d54a9e785dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162863366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3162863366
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3770812521
Short name T391
Test name
Test status
Simulation time 78125834 ps
CPU time 8.29 seconds
Started Apr 23 01:12:51 PM PDT 24
Finished Apr 23 01:13:00 PM PDT 24
Peak memory 250640 kb
Host smart-7c344e9c-6ba5-4217-9d13-ce0f1277daa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770812521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3770812521
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.620529315
Short name T21
Test name
Test status
Simulation time 8610400980 ps
CPU time 161.81 seconds
Started Apr 23 01:12:54 PM PDT 24
Finished Apr 23 01:15:37 PM PDT 24
Peak memory 250672 kb
Host smart-ca49f325-3f5c-4d55-be22-9e57e64f7fed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620529315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.620529315
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1966112288
Short name T106
Test name
Test status
Simulation time 16194378450 ps
CPU time 318.35 seconds
Started Apr 23 01:12:59 PM PDT 24
Finished Apr 23 01:18:18 PM PDT 24
Peak memory 295388 kb
Host smart-3f76c16f-ede0-4832-8cf1-a4f955601bd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1966112288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1966112288
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2582455254
Short name T450
Test name
Test status
Simulation time 198247443 ps
CPU time 0.88 seconds
Started Apr 23 01:12:52 PM PDT 24
Finished Apr 23 01:12:53 PM PDT 24
Peak memory 211292 kb
Host smart-15bdcd9a-2c3f-471b-bbfb-03d65448b5e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582455254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2582455254
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4074319385
Short name T296
Test name
Test status
Simulation time 19904406 ps
CPU time 1.21 seconds
Started Apr 23 01:12:59 PM PDT 24
Finished Apr 23 01:13:01 PM PDT 24
Peak memory 209180 kb
Host smart-f68e58b6-9707-4f79-9540-1c1a875302fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074319385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4074319385
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3371651771
Short name T212
Test name
Test status
Simulation time 244389682 ps
CPU time 10.14 seconds
Started Apr 23 01:12:54 PM PDT 24
Finished Apr 23 01:13:05 PM PDT 24
Peak memory 217520 kb
Host smart-aec7041d-e16f-44bc-b578-f2c49756c006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371651771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3371651771
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.619689790
Short name T692
Test name
Test status
Simulation time 547038267 ps
CPU time 10.8 seconds
Started Apr 23 01:12:54 PM PDT 24
Finished Apr 23 01:13:06 PM PDT 24
Peak memory 209192 kb
Host smart-f4d895ef-e1e2-448f-81c1-629b984d0cd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619689790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.619689790
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3565965012
Short name T440
Test name
Test status
Simulation time 31089621 ps
CPU time 2.03 seconds
Started Apr 23 01:12:54 PM PDT 24
Finished Apr 23 01:12:57 PM PDT 24
Peak memory 217540 kb
Host smart-cf690a87-a0b6-41c3-8bfd-237ea0ecd8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565965012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3565965012
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1718352200
Short name T473
Test name
Test status
Simulation time 458646108 ps
CPU time 14.39 seconds
Started Apr 23 01:12:54 PM PDT 24
Finished Apr 23 01:13:09 PM PDT 24
Peak memory 225688 kb
Host smart-485079c8-0799-416e-a356-a4e2a6726ad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718352200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1718352200
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1387392221
Short name T279
Test name
Test status
Simulation time 608867508 ps
CPU time 11.68 seconds
Started Apr 23 01:12:56 PM PDT 24
Finished Apr 23 01:13:08 PM PDT 24
Peak memory 217536 kb
Host smart-65aaf86f-8e2b-4526-8914-5c27c4ea1fbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387392221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1387392221
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4287253871
Short name T561
Test name
Test status
Simulation time 3082552698 ps
CPU time 8.95 seconds
Started Apr 23 01:12:55 PM PDT 24
Finished Apr 23 01:13:04 PM PDT 24
Peak memory 217612 kb
Host smart-3556289e-f5d6-4207-830a-1a21f5461d51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287253871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4287253871
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3142134237
Short name T61
Test name
Test status
Simulation time 176502663 ps
CPU time 6.21 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:07 PM PDT 24
Peak memory 224132 kb
Host smart-790ead28-2bcb-407f-9a33-a47221719265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142134237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3142134237
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1394356099
Short name T251
Test name
Test status
Simulation time 16900859 ps
CPU time 1.23 seconds
Started Apr 23 01:12:55 PM PDT 24
Finished Apr 23 01:12:56 PM PDT 24
Peak memory 217340 kb
Host smart-d427794a-3e79-4eb7-97d9-234db8bc5e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394356099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1394356099
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3411755373
Short name T442
Test name
Test status
Simulation time 1496162322 ps
CPU time 30.04 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:30 PM PDT 24
Peak memory 250588 kb
Host smart-f0816da8-75df-4ce2-b222-1ded60c06d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411755373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3411755373
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2984724267
Short name T322
Test name
Test status
Simulation time 279694966 ps
CPU time 3.58 seconds
Started Apr 23 01:12:54 PM PDT 24
Finished Apr 23 01:12:58 PM PDT 24
Peak memory 217432 kb
Host smart-ece3e1b6-86dd-4970-afb5-cc44683a921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984724267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2984724267
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2898509864
Short name T777
Test name
Test status
Simulation time 18822611875 ps
CPU time 139.9 seconds
Started Apr 23 01:12:56 PM PDT 24
Finished Apr 23 01:15:16 PM PDT 24
Peak memory 246068 kb
Host smart-71d147c6-5bdd-42ab-ba1b-cb4d186b4f43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898509864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2898509864
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2567015336
Short name T795
Test name
Test status
Simulation time 21862911 ps
CPU time 0.77 seconds
Started Apr 23 01:12:53 PM PDT 24
Finished Apr 23 01:12:54 PM PDT 24
Peak memory 208424 kb
Host smart-31fbf43f-366a-4d3e-9322-99a9cdd449da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567015336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2567015336
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2950253619
Short name T674
Test name
Test status
Simulation time 1980713312 ps
CPU time 22.68 seconds
Started Apr 23 01:12:58 PM PDT 24
Finished Apr 23 01:13:21 PM PDT 24
Peak memory 217512 kb
Host smart-3c16e5b1-a5c1-4a61-a2f1-f921ef314c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950253619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2950253619
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3500413983
Short name T639
Test name
Test status
Simulation time 1323712617 ps
CPU time 5.42 seconds
Started Apr 23 01:12:59 PM PDT 24
Finished Apr 23 01:13:05 PM PDT 24
Peak memory 216644 kb
Host smart-d53418ed-9a34-4c8f-9d90-d04cfde2c6d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500413983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3500413983
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.156794869
Short name T614
Test name
Test status
Simulation time 58881254 ps
CPU time 3.17 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:04 PM PDT 24
Peak memory 217584 kb
Host smart-2d04c0f0-a565-4559-a6d0-661f21f95815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156794869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.156794869
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.899274499
Short name T336
Test name
Test status
Simulation time 350408477 ps
CPU time 14.24 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:15 PM PDT 24
Peak memory 225472 kb
Host smart-e7ec0ff2-7c2f-491e-ba08-47b3acfdb0ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899274499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.899274499
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2514376685
Short name T542
Test name
Test status
Simulation time 1781169219 ps
CPU time 10.53 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:11 PM PDT 24
Peak memory 217536 kb
Host smart-26015cc6-e886-4699-a4d3-2e0aad5a562a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514376685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2514376685
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1819028501
Short name T766
Test name
Test status
Simulation time 374343309 ps
CPU time 12.22 seconds
Started Apr 23 01:12:59 PM PDT 24
Finished Apr 23 01:13:12 PM PDT 24
Peak memory 217580 kb
Host smart-158aa060-9ce9-435c-bd49-9dd978cf7702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819028501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1819028501
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3689485453
Short name T698
Test name
Test status
Simulation time 491100751 ps
CPU time 9.79 seconds
Started Apr 23 01:12:59 PM PDT 24
Finished Apr 23 01:13:09 PM PDT 24
Peak memory 224212 kb
Host smart-fa500272-2fa4-4701-bf5f-7a0553f7c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689485453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3689485453
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3762000009
Short name T250
Test name
Test status
Simulation time 262292135 ps
CPU time 3.09 seconds
Started Apr 23 01:12:53 PM PDT 24
Finished Apr 23 01:12:57 PM PDT 24
Peak memory 213768 kb
Host smart-fe66d1bd-7a0e-47fd-8796-c4558a23d3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762000009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3762000009
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1836221986
Short name T209
Test name
Test status
Simulation time 703860242 ps
CPU time 26.22 seconds
Started Apr 23 01:12:57 PM PDT 24
Finished Apr 23 01:13:24 PM PDT 24
Peak memory 250528 kb
Host smart-296f856a-0ca7-48bd-b256-0e2d45ce11ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836221986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1836221986
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.688658853
Short name T511
Test name
Test status
Simulation time 263601285 ps
CPU time 7.82 seconds
Started Apr 23 01:12:59 PM PDT 24
Finished Apr 23 01:13:07 PM PDT 24
Peak memory 250576 kb
Host smart-bf95dfac-7f24-43be-87ff-9e134751a3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688658853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.688658853
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1673588929
Short name T833
Test name
Test status
Simulation time 9573621419 ps
CPU time 155.36 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:15:36 PM PDT 24
Peak memory 283420 kb
Host smart-bef720ef-d82c-4f47-8345-1af7a45d0807
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673588929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1673588929
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3538218865
Short name T397
Test name
Test status
Simulation time 21979416 ps
CPU time 0.94 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:02 PM PDT 24
Peak memory 208240 kb
Host smart-c0cc3dbe-553d-4f78-989c-c49985b42e8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538218865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3538218865
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3607056465
Short name T454
Test name
Test status
Simulation time 18754173 ps
CPU time 0.92 seconds
Started Apr 23 01:13:03 PM PDT 24
Finished Apr 23 01:13:05 PM PDT 24
Peak memory 209240 kb
Host smart-1dab9529-b4c7-4561-8124-d0fe59df95d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607056465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3607056465
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2154847803
Short name T248
Test name
Test status
Simulation time 262489241 ps
CPU time 9.59 seconds
Started Apr 23 01:13:03 PM PDT 24
Finished Apr 23 01:13:13 PM PDT 24
Peak memory 217532 kb
Host smart-b06542fc-d620-4ce2-b35f-f318bb5a355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154847803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2154847803
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1958653702
Short name T459
Test name
Test status
Simulation time 1989623733 ps
CPU time 23.44 seconds
Started Apr 23 01:13:03 PM PDT 24
Finished Apr 23 01:13:27 PM PDT 24
Peak memory 216888 kb
Host smart-e0ef18b7-a785-4ed9-aafd-236aae210c8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958653702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1958653702
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.174804181
Short name T672
Test name
Test status
Simulation time 554774894 ps
CPU time 4.41 seconds
Started Apr 23 01:13:03 PM PDT 24
Finished Apr 23 01:13:08 PM PDT 24
Peak memory 217468 kb
Host smart-f944f872-1982-431b-bba4-b2da0ee7b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174804181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.174804181
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1611389731
Short name T821
Test name
Test status
Simulation time 1183247189 ps
CPU time 10.61 seconds
Started Apr 23 01:13:02 PM PDT 24
Finished Apr 23 01:13:13 PM PDT 24
Peak memory 218508 kb
Host smart-3d27caf0-a733-402c-b0c9-847a2ae1c1df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611389731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1611389731
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.33065863
Short name T825
Test name
Test status
Simulation time 1341990769 ps
CPU time 9.27 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:10 PM PDT 24
Peak memory 217492 kb
Host smart-9c215dfe-e8f7-4718-adcb-0f4fb276bf0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33065863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_dig
est.33065863
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2808263171
Short name T554
Test name
Test status
Simulation time 228217688 ps
CPU time 9.32 seconds
Started Apr 23 01:13:05 PM PDT 24
Finished Apr 23 01:13:14 PM PDT 24
Peak memory 224312 kb
Host smart-555511d1-a6ec-4523-93b6-a3bdc8298809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808263171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2808263171
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2262054959
Short name T721
Test name
Test status
Simulation time 257497083 ps
CPU time 1.55 seconds
Started Apr 23 01:13:02 PM PDT 24
Finished Apr 23 01:13:04 PM PDT 24
Peak memory 217504 kb
Host smart-d2133844-b52f-423e-ace1-027f80ffb52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262054959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2262054959
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.997858143
Short name T861
Test name
Test status
Simulation time 214152936 ps
CPU time 21.77 seconds
Started Apr 23 01:13:01 PM PDT 24
Finished Apr 23 01:13:23 PM PDT 24
Peak memory 250600 kb
Host smart-7007c2d7-32e2-4a51-9c68-eda800ee5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997858143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.997858143
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.289478417
Short name T278
Test name
Test status
Simulation time 661283715 ps
CPU time 7.57 seconds
Started Apr 23 01:13:03 PM PDT 24
Finished Apr 23 01:13:12 PM PDT 24
Peak memory 243360 kb
Host smart-fa762dd4-a17d-4444-9d7a-263cb8dc6f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289478417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.289478417
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1976851794
Short name T607
Test name
Test status
Simulation time 45897196505 ps
CPU time 174.16 seconds
Started Apr 23 01:13:02 PM PDT 24
Finished Apr 23 01:15:57 PM PDT 24
Peak memory 271504 kb
Host smart-b97e6f9f-607d-4d65-a411-837776321b68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976851794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1976851794
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3680555762
Short name T37
Test name
Test status
Simulation time 38192237 ps
CPU time 0.92 seconds
Started Apr 23 01:13:00 PM PDT 24
Finished Apr 23 01:13:02 PM PDT 24
Peak memory 211188 kb
Host smart-c94cf61a-1eff-418d-92a7-8545eb7ed48b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680555762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3680555762
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1909051235
Short name T269
Test name
Test status
Simulation time 25169886 ps
CPU time 1.01 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:13:11 PM PDT 24
Peak memory 209168 kb
Host smart-818d980f-2a3a-4558-bf67-4b764a74b00d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909051235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1909051235
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2367651263
Short name T660
Test name
Test status
Simulation time 471240256 ps
CPU time 13 seconds
Started Apr 23 01:13:06 PM PDT 24
Finished Apr 23 01:13:20 PM PDT 24
Peak memory 217384 kb
Host smart-ab11b519-13eb-4667-9e1c-54ea6d8c4ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367651263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2367651263
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4143808194
Short name T406
Test name
Test status
Simulation time 1033197745 ps
CPU time 3.08 seconds
Started Apr 23 01:13:07 PM PDT 24
Finished Apr 23 01:13:10 PM PDT 24
Peak memory 216508 kb
Host smart-d48e8121-b6ef-4d53-9aed-8437894ba570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143808194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4143808194
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3181399865
Short name T517
Test name
Test status
Simulation time 38135048 ps
CPU time 2.04 seconds
Started Apr 23 01:13:05 PM PDT 24
Finished Apr 23 01:13:08 PM PDT 24
Peak memory 217552 kb
Host smart-c72c2511-d5d9-4800-86a8-750818a2bc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181399865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3181399865
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1027144423
Short name T374
Test name
Test status
Simulation time 1546359092 ps
CPU time 14.15 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:13:24 PM PDT 24
Peak memory 217780 kb
Host smart-8b71bba1-c699-4d79-a34a-eb674d0b1fe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027144423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1027144423
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3353147820
Short name T603
Test name
Test status
Simulation time 3224170466 ps
CPU time 12.45 seconds
Started Apr 23 01:13:06 PM PDT 24
Finished Apr 23 01:13:19 PM PDT 24
Peak memory 217728 kb
Host smart-ac5b714e-a01b-4453-ad52-3e0bafd092e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353147820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3353147820
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1184799805
Short name T763
Test name
Test status
Simulation time 290033359 ps
CPU time 7.17 seconds
Started Apr 23 01:13:07 PM PDT 24
Finished Apr 23 01:13:15 PM PDT 24
Peak memory 217632 kb
Host smart-52c618a1-ca4c-44be-b29f-d2731a76c4ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184799805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1184799805
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4170977082
Short name T540
Test name
Test status
Simulation time 741241268 ps
CPU time 7.84 seconds
Started Apr 23 01:13:07 PM PDT 24
Finished Apr 23 01:13:16 PM PDT 24
Peak memory 217608 kb
Host smart-8a375452-5ac9-47bb-9d11-ed9e47373cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170977082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4170977082
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3841845261
Short name T828
Test name
Test status
Simulation time 112567008 ps
CPU time 1.95 seconds
Started Apr 23 01:13:02 PM PDT 24
Finished Apr 23 01:13:05 PM PDT 24
Peak memory 217488 kb
Host smart-4964ed87-020c-41ec-ac69-8cadef83ab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841845261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3841845261
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1024003272
Short name T254
Test name
Test status
Simulation time 905916983 ps
CPU time 26.69 seconds
Started Apr 23 01:13:02 PM PDT 24
Finished Apr 23 01:13:30 PM PDT 24
Peak memory 250644 kb
Host smart-de79238f-e766-4de1-9a56-31f7ede3d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024003272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1024003272
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3403435821
Short name T317
Test name
Test status
Simulation time 56301343 ps
CPU time 6.22 seconds
Started Apr 23 01:13:04 PM PDT 24
Finished Apr 23 01:13:11 PM PDT 24
Peak memory 246028 kb
Host smart-0519b8ad-f256-4861-9980-b67fb38f2651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403435821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3403435821
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.4037320902
Short name T288
Test name
Test status
Simulation time 5592243103 ps
CPU time 87.86 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:14:37 PM PDT 24
Peak memory 250660 kb
Host smart-85a97e6f-f0e0-4199-b9bb-2672c86abd18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037320902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.4037320902
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1218843392
Short name T761
Test name
Test status
Simulation time 108996176037 ps
CPU time 468.66 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:20:58 PM PDT 24
Peak memory 283488 kb
Host smart-90eeb6c5-f18e-4ac8-9036-8dd0fd290d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1218843392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1218843392
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2647658289
Short name T418
Test name
Test status
Simulation time 60062319 ps
CPU time 0.86 seconds
Started Apr 23 01:13:11 PM PDT 24
Finished Apr 23 01:13:12 PM PDT 24
Peak memory 209168 kb
Host smart-cd311891-583d-4b4c-8e1c-795a7148d7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647658289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2647658289
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2311885088
Short name T867
Test name
Test status
Simulation time 388789847 ps
CPU time 12.65 seconds
Started Apr 23 01:13:08 PM PDT 24
Finished Apr 23 01:13:22 PM PDT 24
Peak memory 225460 kb
Host smart-3123f951-71e2-4884-a6a3-7c8786196ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311885088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2311885088
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.239134027
Short name T9
Test name
Test status
Simulation time 522652937 ps
CPU time 5.59 seconds
Started Apr 23 01:13:10 PM PDT 24
Finished Apr 23 01:13:16 PM PDT 24
Peak memory 209096 kb
Host smart-ab3705ea-f133-4c53-af1c-40fc4fea87e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239134027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.239134027
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.933416348
Short name T318
Test name
Test status
Simulation time 69593170 ps
CPU time 2.75 seconds
Started Apr 23 01:13:08 PM PDT 24
Finished Apr 23 01:13:11 PM PDT 24
Peak memory 217600 kb
Host smart-98de40f6-de78-4557-8656-db2918094a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933416348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.933416348
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1473384268
Short name T657
Test name
Test status
Simulation time 316340179 ps
CPU time 9.74 seconds
Started Apr 23 01:13:11 PM PDT 24
Finished Apr 23 01:13:22 PM PDT 24
Peak memory 225696 kb
Host smart-80c3a90e-50c7-4cdd-9383-26e9c6e13186
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473384268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1473384268
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.752584424
Short name T704
Test name
Test status
Simulation time 975978070 ps
CPU time 18.59 seconds
Started Apr 23 01:13:10 PM PDT 24
Finished Apr 23 01:13:29 PM PDT 24
Peak memory 217620 kb
Host smart-1d632e4d-b306-45eb-b84e-74ec62e01f6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752584424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.752584424
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1020656189
Short name T428
Test name
Test status
Simulation time 850071065 ps
CPU time 9.01 seconds
Started Apr 23 01:13:11 PM PDT 24
Finished Apr 23 01:13:21 PM PDT 24
Peak memory 217540 kb
Host smart-7f21b21d-e21d-4ea0-bdd4-194d2fdd1ce8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020656189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1020656189
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3723066669
Short name T653
Test name
Test status
Simulation time 439719707 ps
CPU time 15.19 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:13:25 PM PDT 24
Peak memory 217636 kb
Host smart-9781fb79-3d2c-446d-bc54-4fb6117aebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723066669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3723066669
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.714293403
Short name T701
Test name
Test status
Simulation time 103342841 ps
CPU time 2.97 seconds
Started Apr 23 01:13:08 PM PDT 24
Finished Apr 23 01:13:12 PM PDT 24
Peak memory 217476 kb
Host smart-906c4cde-49fa-449b-89f7-21d9f5338eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714293403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.714293403
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2856076573
Short name T714
Test name
Test status
Simulation time 236763053 ps
CPU time 26.43 seconds
Started Apr 23 01:13:07 PM PDT 24
Finished Apr 23 01:13:34 PM PDT 24
Peak memory 250536 kb
Host smart-f9e37700-15d9-45fb-9385-4c7a8d39cd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856076573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2856076573
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2636430385
Short name T455
Test name
Test status
Simulation time 97247172 ps
CPU time 7.54 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:13:17 PM PDT 24
Peak memory 250608 kb
Host smart-b8876bbc-18aa-4db9-b2c6-39df0b5f7566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636430385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2636430385
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2227264649
Short name T560
Test name
Test status
Simulation time 5264686588 ps
CPU time 127.81 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:15:17 PM PDT 24
Peak memory 283408 kb
Host smart-bb62178f-91e6-4ac4-8fd1-91a29f1faa1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227264649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2227264649
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.891096979
Short name T778
Test name
Test status
Simulation time 101430748155 ps
CPU time 819.36 seconds
Started Apr 23 01:13:12 PM PDT 24
Finished Apr 23 01:26:52 PM PDT 24
Peak memory 496576 kb
Host smart-9f02e2aa-5563-4bc8-9ed0-5d1d81395f5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=891096979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.891096979
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3957292926
Short name T38
Test name
Test status
Simulation time 50394180 ps
CPU time 0.78 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:13:11 PM PDT 24
Peak memory 208040 kb
Host smart-19d93037-076a-41ea-a113-5eec42b6a270
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957292926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3957292926
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2069002507
Short name T628
Test name
Test status
Simulation time 45264478 ps
CPU time 0.83 seconds
Started Apr 23 01:13:14 PM PDT 24
Finished Apr 23 01:13:16 PM PDT 24
Peak memory 209032 kb
Host smart-4c0c31b6-51fe-43c9-935a-b5fdcbcbb495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069002507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2069002507
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.336657313
Short name T416
Test name
Test status
Simulation time 180193657 ps
CPU time 7.97 seconds
Started Apr 23 01:13:12 PM PDT 24
Finished Apr 23 01:13:20 PM PDT 24
Peak memory 217564 kb
Host smart-b853c991-39d9-4688-bfc3-5adedef2cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336657313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.336657313
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4073820497
Short name T359
Test name
Test status
Simulation time 467414324 ps
CPU time 11.48 seconds
Started Apr 23 01:13:10 PM PDT 24
Finished Apr 23 01:13:22 PM PDT 24
Peak memory 216900 kb
Host smart-033a7fca-8599-4018-9e5d-ebdd6e64b8f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073820497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.4073820497
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2503570428
Short name T577
Test name
Test status
Simulation time 54419070 ps
CPU time 1.84 seconds
Started Apr 23 01:13:11 PM PDT 24
Finished Apr 23 01:13:13 PM PDT 24
Peak memory 217536 kb
Host smart-f08247bc-c753-4e16-9f40-a1fa21a55e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503570428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2503570428
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3184487216
Short name T291
Test name
Test status
Simulation time 189064771 ps
CPU time 9.71 seconds
Started Apr 23 01:13:16 PM PDT 24
Finished Apr 23 01:13:26 PM PDT 24
Peak memory 217468 kb
Host smart-06caa98b-45c2-40c9-8235-b10ca8e8817c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184487216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3184487216
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2818097446
Short name T646
Test name
Test status
Simulation time 1873285423 ps
CPU time 11.75 seconds
Started Apr 23 01:13:14 PM PDT 24
Finished Apr 23 01:13:26 PM PDT 24
Peak memory 217496 kb
Host smart-b4c7ef9d-b95d-4384-9ab1-538469685f6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818097446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2818097446
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4204028595
Short name T608
Test name
Test status
Simulation time 226250487 ps
CPU time 9.82 seconds
Started Apr 23 01:13:14 PM PDT 24
Finished Apr 23 01:13:24 PM PDT 24
Peak memory 217652 kb
Host smart-8999fd72-bf6d-4756-bfcc-b01dd6b3c24b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204028595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
4204028595
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2996665708
Short name T622
Test name
Test status
Simulation time 2254949533 ps
CPU time 11.7 seconds
Started Apr 23 01:13:11 PM PDT 24
Finished Apr 23 01:13:23 PM PDT 24
Peak memory 225348 kb
Host smart-d71fef4a-a89e-4071-a2ee-8fb7a5eafe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996665708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2996665708
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3631281679
Short name T73
Test name
Test status
Simulation time 34991672 ps
CPU time 2.26 seconds
Started Apr 23 01:13:10 PM PDT 24
Finished Apr 23 01:13:13 PM PDT 24
Peak memory 222472 kb
Host smart-c492c057-973c-479b-b44e-46f597b7c17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631281679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3631281679
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3540015757
Short name T265
Test name
Test status
Simulation time 1007777595 ps
CPU time 31.77 seconds
Started Apr 23 01:13:10 PM PDT 24
Finished Apr 23 01:13:43 PM PDT 24
Peak memory 250544 kb
Host smart-c57a5dba-97ff-4c85-95e3-a1cabdbe5794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540015757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3540015757
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.631734597
Short name T376
Test name
Test status
Simulation time 44373147 ps
CPU time 8.49 seconds
Started Apr 23 01:13:10 PM PDT 24
Finished Apr 23 01:13:20 PM PDT 24
Peak memory 250592 kb
Host smart-85bb42c7-8eb9-42f1-9db4-b217d3fc498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631734597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.631734597
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2798401749
Short name T325
Test name
Test status
Simulation time 42699044602 ps
CPU time 37.73 seconds
Started Apr 23 01:13:14 PM PDT 24
Finished Apr 23 01:13:52 PM PDT 24
Peak memory 225696 kb
Host smart-69f98cdd-4d78-4691-bb29-af5515f96c2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798401749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2798401749
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.585022620
Short name T606
Test name
Test status
Simulation time 14717517 ps
CPU time 1.14 seconds
Started Apr 23 01:13:09 PM PDT 24
Finished Apr 23 01:13:11 PM PDT 24
Peak memory 211180 kb
Host smart-dabb1eef-1d42-444c-b764-c38bee8130a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585022620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.585022620
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3639474185
Short name T696
Test name
Test status
Simulation time 27529653 ps
CPU time 1.01 seconds
Started Apr 23 01:13:18 PM PDT 24
Finished Apr 23 01:13:20 PM PDT 24
Peak memory 209236 kb
Host smart-70d24657-bd26-41c4-a51d-80b5dfa8e413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639474185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3639474185
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.21033412
Short name T626
Test name
Test status
Simulation time 201544692 ps
CPU time 10.53 seconds
Started Apr 23 01:13:19 PM PDT 24
Finished Apr 23 01:13:30 PM PDT 24
Peak memory 217532 kb
Host smart-0952d6ab-5928-48e0-ac57-0d28db59e059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21033412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.21033412
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2762634037
Short name T629
Test name
Test status
Simulation time 2047832963 ps
CPU time 12.48 seconds
Started Apr 23 01:13:16 PM PDT 24
Finished Apr 23 01:13:29 PM PDT 24
Peak memory 209116 kb
Host smart-1f79d89f-248f-41bf-8348-314ad5164228
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762634037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2762634037
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2343918128
Short name T860
Test name
Test status
Simulation time 209724411 ps
CPU time 3.33 seconds
Started Apr 23 01:13:15 PM PDT 24
Finished Apr 23 01:13:19 PM PDT 24
Peak memory 217528 kb
Host smart-e66b266c-a37c-4bf6-a17e-e02417717b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343918128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2343918128
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.813506969
Short name T233
Test name
Test status
Simulation time 585605342 ps
CPU time 9.35 seconds
Started Apr 23 01:13:19 PM PDT 24
Finished Apr 23 01:13:29 PM PDT 24
Peak memory 225644 kb
Host smart-6224a7cf-99d6-4272-bd50-7751375afd70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813506969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.813506969
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1844385431
Short name T443
Test name
Test status
Simulation time 1451702562 ps
CPU time 11.17 seconds
Started Apr 23 01:13:19 PM PDT 24
Finished Apr 23 01:13:31 PM PDT 24
Peak memory 217556 kb
Host smart-4ef2f2dd-d595-4e7b-8ce7-c641067cb6d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844385431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1844385431
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1501265102
Short name T230
Test name
Test status
Simulation time 678979942 ps
CPU time 6.67 seconds
Started Apr 23 01:13:24 PM PDT 24
Finished Apr 23 01:13:31 PM PDT 24
Peak memory 217596 kb
Host smart-81b4ac0f-9dc9-4f55-a3c6-a32db86895e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501265102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1501265102
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3955197836
Short name T737
Test name
Test status
Simulation time 874559990 ps
CPU time 15.5 seconds
Started Apr 23 01:13:16 PM PDT 24
Finished Apr 23 01:13:32 PM PDT 24
Peak memory 217604 kb
Host smart-692772d8-981c-49a9-8049-c83bfb50ae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955197836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3955197836
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2745675507
Short name T219
Test name
Test status
Simulation time 89236621 ps
CPU time 4.27 seconds
Started Apr 23 01:13:16 PM PDT 24
Finished Apr 23 01:13:21 PM PDT 24
Peak memory 217488 kb
Host smart-0d52cec0-43e9-4282-bf5b-9df33e7f875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745675507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2745675507
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.4111231289
Short name T687
Test name
Test status
Simulation time 182885647 ps
CPU time 23.08 seconds
Started Apr 23 01:13:16 PM PDT 24
Finished Apr 23 01:13:40 PM PDT 24
Peak memory 250424 kb
Host smart-d638229b-1fef-4e4c-a9b7-556843c1c5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111231289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.4111231289
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3958266143
Short name T220
Test name
Test status
Simulation time 340655683 ps
CPU time 6.67 seconds
Started Apr 23 01:13:15 PM PDT 24
Finished Apr 23 01:13:22 PM PDT 24
Peak memory 242392 kb
Host smart-779e750b-8031-4266-abbc-d2d9f9898947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958266143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3958266143
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.871932360
Short name T728
Test name
Test status
Simulation time 10293012491 ps
CPU time 57.35 seconds
Started Apr 23 01:13:19 PM PDT 24
Finished Apr 23 01:14:17 PM PDT 24
Peak memory 267584 kb
Host smart-86307069-75ea-4571-b8da-e905697f798f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871932360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.871932360
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2726295334
Short name T147
Test name
Test status
Simulation time 70910768222 ps
CPU time 369.27 seconds
Started Apr 23 01:13:18 PM PDT 24
Finished Apr 23 01:19:28 PM PDT 24
Peak memory 388948 kb
Host smart-d38d63cd-5b58-4940-a6cf-c1e6c82719d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2726295334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2726295334
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.926481713
Short name T713
Test name
Test status
Simulation time 43458284 ps
CPU time 0.75 seconds
Started Apr 23 01:13:14 PM PDT 24
Finished Apr 23 01:13:16 PM PDT 24
Peak memory 206460 kb
Host smart-25ee56cf-7428-41b2-a4e0-c28c050266f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926481713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.926481713
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1796002575
Short name T690
Test name
Test status
Simulation time 45362245 ps
CPU time 1.04 seconds
Started Apr 23 01:13:22 PM PDT 24
Finished Apr 23 01:13:24 PM PDT 24
Peak memory 209208 kb
Host smart-cc4d44a7-befd-485a-8150-19e77ce557b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796002575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1796002575
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3827358095
Short name T745
Test name
Test status
Simulation time 251152064 ps
CPU time 10.76 seconds
Started Apr 23 01:13:18 PM PDT 24
Finished Apr 23 01:13:29 PM PDT 24
Peak memory 217588 kb
Host smart-6a0f2289-f74b-4305-b6ea-794bbd33c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827358095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3827358095
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1698709172
Short name T767
Test name
Test status
Simulation time 1098234465 ps
CPU time 3.81 seconds
Started Apr 23 01:13:17 PM PDT 24
Finished Apr 23 01:13:22 PM PDT 24
Peak memory 209156 kb
Host smart-0804b015-ab59-40fd-8d00-5270adcc6d3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698709172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1698709172
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3784299697
Short name T586
Test name
Test status
Simulation time 42266421 ps
CPU time 1.93 seconds
Started Apr 23 01:13:19 PM PDT 24
Finished Apr 23 01:13:22 PM PDT 24
Peak memory 217604 kb
Host smart-549afdfc-6e53-427a-ae43-80ab78862340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784299697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3784299697
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3329015552
Short name T92
Test name
Test status
Simulation time 1206414694 ps
CPU time 10.56 seconds
Started Apr 23 01:13:18 PM PDT 24
Finished Apr 23 01:13:29 PM PDT 24
Peak memory 217644 kb
Host smart-03a7e2c4-d999-4dc8-b29c-2d6fef805d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329015552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3329015552
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3317549998
Short name T590
Test name
Test status
Simulation time 383512691 ps
CPU time 14.83 seconds
Started Apr 23 01:13:21 PM PDT 24
Finished Apr 23 01:13:36 PM PDT 24
Peak memory 217540 kb
Host smart-3237a54b-52a3-4ba0-996f-61382feb3b3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317549998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3317549998
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.334423890
Short name T324
Test name
Test status
Simulation time 580733425 ps
CPU time 11.26 seconds
Started Apr 23 01:13:22 PM PDT 24
Finished Apr 23 01:13:34 PM PDT 24
Peak memory 217504 kb
Host smart-51c80312-4600-434f-bab5-4f66fd2bb970
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334423890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.334423890
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1589937737
Short name T58
Test name
Test status
Simulation time 416847079 ps
CPU time 10.47 seconds
Started Apr 23 01:13:19 PM PDT 24
Finished Apr 23 01:13:30 PM PDT 24
Peak memory 217672 kb
Host smart-6dd11c13-b077-4281-a494-72d6b44939b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589937737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1589937737
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1262762626
Short name T684
Test name
Test status
Simulation time 653862985 ps
CPU time 2.73 seconds
Started Apr 23 01:13:18 PM PDT 24
Finished Apr 23 01:13:21 PM PDT 24
Peak memory 214188 kb
Host smart-fb02621f-a080-4643-a12c-709fd01e4076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262762626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1262762626
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1888614529
Short name T513
Test name
Test status
Simulation time 270381626 ps
CPU time 30.47 seconds
Started Apr 23 01:13:18 PM PDT 24
Finished Apr 23 01:13:50 PM PDT 24
Peak memory 250584 kb
Host smart-d9082c32-4fb6-4e09-a3f6-7654481f2630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888614529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1888614529
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3988264518
Short name T215
Test name
Test status
Simulation time 106715875 ps
CPU time 9.03 seconds
Started Apr 23 01:13:21 PM PDT 24
Finished Apr 23 01:13:31 PM PDT 24
Peak memory 250576 kb
Host smart-9a1582ad-67e2-49a0-ba96-f6bc60ed50d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988264518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3988264518
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.547716252
Short name T176
Test name
Test status
Simulation time 3783281776 ps
CPU time 162.84 seconds
Started Apr 23 01:13:26 PM PDT 24
Finished Apr 23 01:16:09 PM PDT 24
Peak memory 283388 kb
Host smart-eb9a260b-4c45-4bc2-890a-92d4838934ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547716252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.547716252
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3110863238
Short name T349
Test name
Test status
Simulation time 18404796 ps
CPU time 1.14 seconds
Started Apr 23 01:13:17 PM PDT 24
Finished Apr 23 01:13:19 PM PDT 24
Peak memory 211216 kb
Host smart-f439ada1-a8f8-4565-8720-c0a6fb1e9910
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110863238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3110863238
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3318870711
Short name T166
Test name
Test status
Simulation time 86275642 ps
CPU time 1.19 seconds
Started Apr 23 01:10:49 PM PDT 24
Finished Apr 23 01:10:51 PM PDT 24
Peak memory 209216 kb
Host smart-cfe06c95-2d8e-4bc3-81c4-1d290ce16c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318870711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3318870711
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1313478131
Short name T65
Test name
Test status
Simulation time 10759385 ps
CPU time 0.9 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:47 PM PDT 24
Peak memory 208980 kb
Host smart-7655205f-7a5d-4b77-aa4c-0459c24c5959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313478131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1313478131
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1801975009
Short name T550
Test name
Test status
Simulation time 251889110 ps
CPU time 7.99 seconds
Started Apr 23 01:10:46 PM PDT 24
Finished Apr 23 01:10:55 PM PDT 24
Peak memory 217528 kb
Host smart-2917815d-adaf-4b30-9dbd-9c410920ea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801975009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1801975009
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2317391515
Short name T30
Test name
Test status
Simulation time 1974310428 ps
CPU time 9.61 seconds
Started Apr 23 01:10:54 PM PDT 24
Finished Apr 23 01:11:05 PM PDT 24
Peak memory 209088 kb
Host smart-539a1ed9-6030-4a2f-8049-feb7d96ac6c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317391515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2317391515
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1337950049
Short name T678
Test name
Test status
Simulation time 5126316696 ps
CPU time 35.51 seconds
Started Apr 23 01:10:55 PM PDT 24
Finished Apr 23 01:11:32 PM PDT 24
Peak memory 217592 kb
Host smart-758a7633-4598-41c3-9e59-d44da69c782d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337950049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1337950049
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2659297602
Short name T664
Test name
Test status
Simulation time 6770082512 ps
CPU time 9.89 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 217456 kb
Host smart-0dfa32eb-2032-4107-ac6e-d0877b7b3c53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659297602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
659297602
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3384139795
Short name T206
Test name
Test status
Simulation time 168560203 ps
CPU time 2.85 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:48 PM PDT 24
Peak memory 217516 kb
Host smart-8f13f079-0165-461f-9985-1743253c0381
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384139795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3384139795
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1345741069
Short name T522
Test name
Test status
Simulation time 1678722086 ps
CPU time 26.48 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:11:12 PM PDT 24
Peak memory 212880 kb
Host smart-09f5c2eb-c178-4cc7-8d1a-cda4c9bf677f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345741069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1345741069
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3938313486
Short name T79
Test name
Test status
Simulation time 565174084 ps
CPU time 2.55 seconds
Started Apr 23 01:10:44 PM PDT 24
Finished Apr 23 01:10:47 PM PDT 24
Peak memory 212720 kb
Host smart-48eb302b-8a75-425a-8fd1-eea8525a823c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938313486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3938313486
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.630109096
Short name T467
Test name
Test status
Simulation time 6160940058 ps
CPU time 40.33 seconds
Started Apr 23 01:10:46 PM PDT 24
Finished Apr 23 01:11:27 PM PDT 24
Peak memory 266940 kb
Host smart-e0ac4126-f44e-4491-9d4d-441a15ca64b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630109096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.630109096
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.661209861
Short name T217
Test name
Test status
Simulation time 1425757004 ps
CPU time 16.32 seconds
Started Apr 23 01:10:46 PM PDT 24
Finished Apr 23 01:11:03 PM PDT 24
Peak memory 250144 kb
Host smart-4073c5d0-71f3-427f-8c59-6bf525bd0c4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661209861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.661209861
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3167132185
Short name T234
Test name
Test status
Simulation time 148162883 ps
CPU time 1.96 seconds
Started Apr 23 01:10:48 PM PDT 24
Finished Apr 23 01:10:52 PM PDT 24
Peak memory 217508 kb
Host smart-2d7b6156-ff10-4472-9809-c99f1a3e0e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167132185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3167132185
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4013260363
Short name T569
Test name
Test status
Simulation time 386689223 ps
CPU time 8.45 seconds
Started Apr 23 01:10:47 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 217340 kb
Host smart-39710940-3aa9-4d90-a51c-f7d2863d0d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013260363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4013260363
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2741767614
Short name T98
Test name
Test status
Simulation time 246388002 ps
CPU time 25.89 seconds
Started Apr 23 01:10:56 PM PDT 24
Finished Apr 23 01:11:23 PM PDT 24
Peak memory 267584 kb
Host smart-869860ae-17f3-474e-b9b1-25906ba10f9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741767614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2741767614
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2946020874
Short name T573
Test name
Test status
Simulation time 925015492 ps
CPU time 8.47 seconds
Started Apr 23 01:10:54 PM PDT 24
Finished Apr 23 01:11:04 PM PDT 24
Peak memory 225548 kb
Host smart-b3035d29-0372-4ee8-9d6e-7555f67ab09b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946020874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2946020874
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1758213288
Short name T460
Test name
Test status
Simulation time 1420736011 ps
CPU time 18.31 seconds
Started Apr 23 01:10:54 PM PDT 24
Finished Apr 23 01:11:14 PM PDT 24
Peak memory 217656 kb
Host smart-1f3d33f8-2a36-4436-8abb-72938083d7a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758213288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1758213288
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.903014390
Short name T812
Test name
Test status
Simulation time 362075983 ps
CPU time 12.07 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:11:04 PM PDT 24
Peak memory 217660 kb
Host smart-c69dac0b-8f93-4e10-b5a7-cdd774228530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903014390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.903014390
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1303532067
Short name T567
Test name
Test status
Simulation time 1798285485 ps
CPU time 10.17 seconds
Started Apr 23 01:10:46 PM PDT 24
Finished Apr 23 01:10:57 PM PDT 24
Peak memory 217216 kb
Host smart-7867ef34-d56c-4e88-8159-ba86d4325bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303532067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1303532067
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2372438496
Short name T155
Test name
Test status
Simulation time 138423314 ps
CPU time 1.72 seconds
Started Apr 23 01:10:54 PM PDT 24
Finished Apr 23 01:10:57 PM PDT 24
Peak memory 217596 kb
Host smart-42f60dc1-0ad0-4631-8c05-cb541c5b4102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372438496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2372438496
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1871155642
Short name T851
Test name
Test status
Simulation time 855706179 ps
CPU time 19.48 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:11:05 PM PDT 24
Peak memory 245560 kb
Host smart-de398fc7-8d11-4caf-be08-c29b17f4deb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871155642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1871155642
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2495248801
Short name T223
Test name
Test status
Simulation time 100167423 ps
CPU time 9.45 seconds
Started Apr 23 01:10:45 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 250556 kb
Host smart-c1fed5dc-3874-44cd-97cb-b13b06fe251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495248801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2495248801
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3428244433
Short name T146
Test name
Test status
Simulation time 17227873538 ps
CPU time 357.99 seconds
Started Apr 23 01:10:49 PM PDT 24
Finished Apr 23 01:16:48 PM PDT 24
Peak memory 282976 kb
Host smart-a3d117af-a428-45cd-bdbf-fed64c24e63e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3428244433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3428244433
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.701109152
Short name T158
Test name
Test status
Simulation time 32662297 ps
CPU time 0.75 seconds
Started Apr 23 01:10:54 PM PDT 24
Finished Apr 23 01:10:57 PM PDT 24
Peak memory 208108 kb
Host smart-8aea531d-3354-4f24-ae2a-6574c5fcf76c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701109152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.701109152
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.4020303020
Short name T661
Test name
Test status
Simulation time 69367975 ps
CPU time 1.14 seconds
Started Apr 23 01:13:27 PM PDT 24
Finished Apr 23 01:13:29 PM PDT 24
Peak memory 209156 kb
Host smart-e1f90570-f14b-4ad4-bf47-600db354a5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020303020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4020303020
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1478334380
Short name T768
Test name
Test status
Simulation time 141015549 ps
CPU time 2.39 seconds
Started Apr 23 01:13:22 PM PDT 24
Finished Apr 23 01:13:25 PM PDT 24
Peak memory 216368 kb
Host smart-a0c9d750-85a0-4bef-8b60-7cf0ad1bb656
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478334380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1478334380
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3078260096
Short name T723
Test name
Test status
Simulation time 1413730194 ps
CPU time 3.44 seconds
Started Apr 23 01:13:22 PM PDT 24
Finished Apr 23 01:13:26 PM PDT 24
Peak memory 217572 kb
Host smart-a9194d2f-fdc2-4c61-adc9-bf89233ad438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078260096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3078260096
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1714769809
Short name T304
Test name
Test status
Simulation time 737111605 ps
CPU time 11.75 seconds
Started Apr 23 01:13:20 PM PDT 24
Finished Apr 23 01:13:33 PM PDT 24
Peak memory 225676 kb
Host smart-3bdec70f-4804-4c32-ab2d-904d62018eb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714769809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1714769809
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1625284439
Short name T844
Test name
Test status
Simulation time 862100115 ps
CPU time 20.14 seconds
Started Apr 23 01:13:32 PM PDT 24
Finished Apr 23 01:13:52 PM PDT 24
Peak memory 217544 kb
Host smart-607b7506-4d88-4f47-a37a-331e2f15cf4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625284439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1625284439
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1149049173
Short name T680
Test name
Test status
Simulation time 303981747 ps
CPU time 10 seconds
Started Apr 23 01:13:27 PM PDT 24
Finished Apr 23 01:13:38 PM PDT 24
Peak memory 217528 kb
Host smart-c123f6db-b43f-4a1d-aa8b-75f9ffa931ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149049173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1149049173
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1298334513
Short name T487
Test name
Test status
Simulation time 376589835 ps
CPU time 14.86 seconds
Started Apr 23 01:13:21 PM PDT 24
Finished Apr 23 01:13:36 PM PDT 24
Peak memory 225252 kb
Host smart-56c085b7-1b8d-4b8e-a500-f331c9b7fbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298334513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1298334513
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1533937148
Short name T75
Test name
Test status
Simulation time 127564804 ps
CPU time 4.63 seconds
Started Apr 23 01:13:23 PM PDT 24
Finished Apr 23 01:13:29 PM PDT 24
Peak memory 213784 kb
Host smart-614cf4cd-9e01-43b3-a4bf-70b288f507ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533937148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1533937148
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.348227910
Short name T729
Test name
Test status
Simulation time 1609009813 ps
CPU time 32.94 seconds
Started Apr 23 01:13:22 PM PDT 24
Finished Apr 23 01:13:55 PM PDT 24
Peak memory 250600 kb
Host smart-9025dfa4-0482-4a1e-b4a4-a5295c3cb3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348227910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.348227910
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.485332311
Short name T474
Test name
Test status
Simulation time 59522877 ps
CPU time 2.91 seconds
Started Apr 23 01:13:21 PM PDT 24
Finished Apr 23 01:13:25 PM PDT 24
Peak memory 225972 kb
Host smart-27c61beb-8f19-4a2e-87f0-c1db4728a71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485332311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.485332311
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2603909216
Short name T382
Test name
Test status
Simulation time 4995228447 ps
CPU time 178.32 seconds
Started Apr 23 01:13:27 PM PDT 24
Finished Apr 23 01:16:25 PM PDT 24
Peak memory 280028 kb
Host smart-e1683dac-129a-4c2d-b6eb-c8ce10057e84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603909216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2603909216
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1486154908
Short name T725
Test name
Test status
Simulation time 13538601 ps
CPU time 0.99 seconds
Started Apr 23 01:13:23 PM PDT 24
Finished Apr 23 01:13:25 PM PDT 24
Peak memory 211296 kb
Host smart-af8d896c-2a13-4fe7-a31a-2ad362c144c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486154908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1486154908
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.4148927687
Short name T858
Test name
Test status
Simulation time 60437223 ps
CPU time 0.85 seconds
Started Apr 23 01:13:33 PM PDT 24
Finished Apr 23 01:13:34 PM PDT 24
Peak memory 208984 kb
Host smart-381ec51a-154a-4e3a-b330-dcdcc5faea80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148927687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.4148927687
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3468796360
Short name T307
Test name
Test status
Simulation time 610067505 ps
CPU time 14.52 seconds
Started Apr 23 01:13:28 PM PDT 24
Finished Apr 23 01:13:43 PM PDT 24
Peak memory 217520 kb
Host smart-78e80be3-d40d-460e-ac78-bd77d506403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468796360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3468796360
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2893090555
Short name T504
Test name
Test status
Simulation time 5430195130 ps
CPU time 8.49 seconds
Started Apr 23 01:13:29 PM PDT 24
Finished Apr 23 01:13:38 PM PDT 24
Peak memory 217356 kb
Host smart-d0c1c352-3ec4-4e87-9fe4-9f1ddc48f1ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893090555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2893090555
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3525402472
Short name T213
Test name
Test status
Simulation time 68784763 ps
CPU time 2.41 seconds
Started Apr 23 01:13:27 PM PDT 24
Finished Apr 23 01:13:30 PM PDT 24
Peak memory 217588 kb
Host smart-efe99944-7d22-4143-bb4b-cf9f59fe1416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525402472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3525402472
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.164158069
Short name T771
Test name
Test status
Simulation time 3427072485 ps
CPU time 11.85 seconds
Started Apr 23 01:13:31 PM PDT 24
Finished Apr 23 01:13:43 PM PDT 24
Peak memory 225860 kb
Host smart-c4e56df6-38f7-4b4e-87ef-c5909ff06ece
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164158069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.164158069
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.815859694
Short name T829
Test name
Test status
Simulation time 401853905 ps
CPU time 12.14 seconds
Started Apr 23 01:13:29 PM PDT 24
Finished Apr 23 01:13:42 PM PDT 24
Peak memory 217468 kb
Host smart-63639088-e4ce-4970-a1fa-8e1203e68eb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815859694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.815859694
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.76673944
Short name T598
Test name
Test status
Simulation time 283060073 ps
CPU time 9.09 seconds
Started Apr 23 01:13:31 PM PDT 24
Finished Apr 23 01:13:40 PM PDT 24
Peak memory 217596 kb
Host smart-a0a3a259-8120-415f-a6ca-28a690aa1d36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76673944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.76673944
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3850806579
Short name T171
Test name
Test status
Simulation time 1247323303 ps
CPU time 9.64 seconds
Started Apr 23 01:13:27 PM PDT 24
Finished Apr 23 01:13:37 PM PDT 24
Peak memory 217608 kb
Host smart-e8b2eda2-1258-4abd-b214-f17cae07f894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850806579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3850806579
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3458046119
Short name T533
Test name
Test status
Simulation time 328754899 ps
CPU time 2.97 seconds
Started Apr 23 01:13:26 PM PDT 24
Finished Apr 23 01:13:30 PM PDT 24
Peak memory 213796 kb
Host smart-ebb82a7b-9ce8-49c5-a796-7035e377aa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458046119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3458046119
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.135934713
Short name T387
Test name
Test status
Simulation time 165416748 ps
CPU time 15.27 seconds
Started Apr 23 01:13:25 PM PDT 24
Finished Apr 23 01:13:41 PM PDT 24
Peak memory 250572 kb
Host smart-2b3df74b-20d1-425f-a402-2447cf23d477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135934713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.135934713
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2400081171
Short name T444
Test name
Test status
Simulation time 127172398 ps
CPU time 8.28 seconds
Started Apr 23 01:13:25 PM PDT 24
Finished Apr 23 01:13:34 PM PDT 24
Peak memory 243284 kb
Host smart-b5df2e29-2fb8-400f-88f1-a6ccd7f819e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400081171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2400081171
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2430641697
Short name T404
Test name
Test status
Simulation time 3539393252 ps
CPU time 112.88 seconds
Started Apr 23 01:13:32 PM PDT 24
Finished Apr 23 01:15:25 PM PDT 24
Peak memory 275224 kb
Host smart-c7d3f4b1-e155-4d89-9713-f88df5457cac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430641697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2430641697
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.341262974
Short name T732
Test name
Test status
Simulation time 46959867 ps
CPU time 1.05 seconds
Started Apr 23 01:13:26 PM PDT 24
Finished Apr 23 01:13:27 PM PDT 24
Peak memory 212256 kb
Host smart-024aa605-a719-458c-a41c-6875332706e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341262974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.341262974
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1802714529
Short name T241
Test name
Test status
Simulation time 19132489 ps
CPU time 1.16 seconds
Started Apr 23 01:13:35 PM PDT 24
Finished Apr 23 01:13:36 PM PDT 24
Peak memory 209160 kb
Host smart-91ff85f3-b351-450f-9c90-d93d7612267a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802714529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1802714529
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3687968994
Short name T848
Test name
Test status
Simulation time 725424649 ps
CPU time 9.31 seconds
Started Apr 23 01:13:30 PM PDT 24
Finished Apr 23 01:13:40 PM PDT 24
Peak memory 217480 kb
Host smart-38785186-e98e-48c5-ba3e-63cd6b3b0cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687968994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3687968994
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.901521853
Short name T624
Test name
Test status
Simulation time 465290781 ps
CPU time 5.45 seconds
Started Apr 23 01:13:31 PM PDT 24
Finished Apr 23 01:13:37 PM PDT 24
Peak memory 216780 kb
Host smart-610de1b2-c241-4431-9237-821d7675a59c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901521853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.901521853
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2512685672
Short name T431
Test name
Test status
Simulation time 65094810 ps
CPU time 2.57 seconds
Started Apr 23 01:13:30 PM PDT 24
Finished Apr 23 01:13:33 PM PDT 24
Peak memory 217544 kb
Host smart-4cd8f625-7d1d-4869-859e-2ab886846b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512685672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2512685672
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.431635516
Short name T441
Test name
Test status
Simulation time 1549085363 ps
CPU time 9.13 seconds
Started Apr 23 01:13:31 PM PDT 24
Finished Apr 23 01:13:41 PM PDT 24
Peak memory 225584 kb
Host smart-5a23fd99-701e-4e59-9e72-b1c1ffdb8078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431635516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.431635516
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3741135599
Short name T303
Test name
Test status
Simulation time 570860728 ps
CPU time 17.62 seconds
Started Apr 23 01:13:34 PM PDT 24
Finished Apr 23 01:13:52 PM PDT 24
Peak memory 217608 kb
Host smart-6eea0efd-4896-4a37-aa1b-cfb685a48e88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741135599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3741135599
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2827799091
Short name T339
Test name
Test status
Simulation time 307680447 ps
CPU time 9.2 seconds
Started Apr 23 01:13:33 PM PDT 24
Finished Apr 23 01:13:43 PM PDT 24
Peak memory 217540 kb
Host smart-18e0589d-0901-41c6-9c8c-5b8e01ec5bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827799091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2827799091
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.83760669
Short name T409
Test name
Test status
Simulation time 225422784 ps
CPU time 9.21 seconds
Started Apr 23 01:13:29 PM PDT 24
Finished Apr 23 01:13:39 PM PDT 24
Peak memory 217644 kb
Host smart-e1c2f87f-0efb-4f9a-b4d4-163482ddcb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83760669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.83760669
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2131645378
Short name T523
Test name
Test status
Simulation time 24651872 ps
CPU time 1.22 seconds
Started Apr 23 01:13:29 PM PDT 24
Finished Apr 23 01:13:31 PM PDT 24
Peak memory 212408 kb
Host smart-d3d6fc2e-a146-4d0e-b35d-882847bc529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131645378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2131645378
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.685778445
Short name T101
Test name
Test status
Simulation time 258076642 ps
CPU time 27.97 seconds
Started Apr 23 01:13:32 PM PDT 24
Finished Apr 23 01:14:01 PM PDT 24
Peak memory 250536 kb
Host smart-43406cc2-620b-4727-a5e6-ca276c56218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685778445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.685778445
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.793841551
Short name T385
Test name
Test status
Simulation time 475702569 ps
CPU time 5.21 seconds
Started Apr 23 01:13:31 PM PDT 24
Finished Apr 23 01:13:37 PM PDT 24
Peak memory 222256 kb
Host smart-3535bd1d-9057-4cb9-82dd-254cc69e1028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793841551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.793841551
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3318687650
Short name T710
Test name
Test status
Simulation time 13241825645 ps
CPU time 95.97 seconds
Started Apr 23 01:13:34 PM PDT 24
Finished Apr 23 01:15:10 PM PDT 24
Peak memory 275896 kb
Host smart-1a0cf9f0-0d9c-46df-8c2c-16d530bac888
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318687650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3318687650
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2479479525
Short name T243
Test name
Test status
Simulation time 44662900 ps
CPU time 0.91 seconds
Started Apr 23 01:13:31 PM PDT 24
Finished Apr 23 01:13:33 PM PDT 24
Peak memory 211148 kb
Host smart-9550ff82-d238-4d82-b0b9-b229e3613c44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479479525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2479479525
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1294115736
Short name T547
Test name
Test status
Simulation time 23908999 ps
CPU time 1.11 seconds
Started Apr 23 01:13:39 PM PDT 24
Finished Apr 23 01:13:41 PM PDT 24
Peak memory 209192 kb
Host smart-8b6633a2-2acd-4d66-a47f-0026bf91e2c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294115736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1294115736
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3253201117
Short name T706
Test name
Test status
Simulation time 864781313 ps
CPU time 10.44 seconds
Started Apr 23 01:13:35 PM PDT 24
Finished Apr 23 01:13:46 PM PDT 24
Peak memory 217460 kb
Host smart-f241d412-94d0-4365-bdcc-33141849dac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253201117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3253201117
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4173974894
Short name T581
Test name
Test status
Simulation time 656938282 ps
CPU time 8.32 seconds
Started Apr 23 01:13:34 PM PDT 24
Finished Apr 23 01:13:43 PM PDT 24
Peak memory 209236 kb
Host smart-00e28bfd-a428-41ec-927d-f76b672d20fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173974894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4173974894
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1227942987
Short name T785
Test name
Test status
Simulation time 288321417 ps
CPU time 3.28 seconds
Started Apr 23 01:13:38 PM PDT 24
Finished Apr 23 01:13:41 PM PDT 24
Peak memory 217492 kb
Host smart-5ae26d0d-558a-45e8-bada-f090da9a9126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227942987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1227942987
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2858449390
Short name T722
Test name
Test status
Simulation time 1823842913 ps
CPU time 17.85 seconds
Started Apr 23 01:13:34 PM PDT 24
Finished Apr 23 01:13:53 PM PDT 24
Peak memory 225628 kb
Host smart-1ebcb71c-cde5-4d7e-bfe8-71ce5b96bca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858449390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2858449390
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.584662119
Short name T556
Test name
Test status
Simulation time 327792935 ps
CPU time 10.21 seconds
Started Apr 23 01:13:35 PM PDT 24
Finished Apr 23 01:13:46 PM PDT 24
Peak memory 217580 kb
Host smart-9b262a6f-db4f-41c2-88ce-d117ef1a8b24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584662119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.584662119
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3011247919
Short name T226
Test name
Test status
Simulation time 535100375 ps
CPU time 8.29 seconds
Started Apr 23 01:13:37 PM PDT 24
Finished Apr 23 01:13:45 PM PDT 24
Peak memory 217492 kb
Host smart-5808c520-ac8f-417a-b41d-bab08c638fa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011247919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3011247919
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1190322990
Short name T755
Test name
Test status
Simulation time 1550242591 ps
CPU time 10.7 seconds
Started Apr 23 01:13:33 PM PDT 24
Finished Apr 23 01:13:45 PM PDT 24
Peak memory 217612 kb
Host smart-d68ad584-2961-490f-a33d-3d3005540225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190322990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1190322990
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3448797863
Short name T592
Test name
Test status
Simulation time 252313283 ps
CPU time 3.04 seconds
Started Apr 23 01:13:34 PM PDT 24
Finished Apr 23 01:13:38 PM PDT 24
Peak memory 214200 kb
Host smart-da7978f4-ac12-4f90-8212-5ddc1a5943e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448797863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3448797863
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1351631912
Short name T168
Test name
Test status
Simulation time 801266633 ps
CPU time 29.33 seconds
Started Apr 23 01:13:34 PM PDT 24
Finished Apr 23 01:14:04 PM PDT 24
Peak memory 250648 kb
Host smart-6b28ef97-2964-4cd4-9baa-8b67699e24bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351631912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1351631912
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3413308106
Short name T371
Test name
Test status
Simulation time 100050070 ps
CPU time 7.15 seconds
Started Apr 23 01:13:34 PM PDT 24
Finished Apr 23 01:13:42 PM PDT 24
Peak memory 247976 kb
Host smart-dec85cb4-e97d-48ba-8df0-2acea454df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413308106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3413308106
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.4180534264
Short name T730
Test name
Test status
Simulation time 1815731594 ps
CPU time 38.79 seconds
Started Apr 23 01:13:33 PM PDT 24
Finished Apr 23 01:14:12 PM PDT 24
Peak memory 250592 kb
Host smart-9abcba3f-15f2-4c2f-ad86-e565196f7a4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180534264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.4180534264
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.137683689
Short name T839
Test name
Test status
Simulation time 11410437 ps
CPU time 0.8 seconds
Started Apr 23 01:13:33 PM PDT 24
Finished Apr 23 01:13:34 PM PDT 24
Peak memory 208364 kb
Host smart-3954315b-83fa-4025-a15f-b7772c143a4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137683689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.137683689
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.227718652
Short name T91
Test name
Test status
Simulation time 38059397 ps
CPU time 0.83 seconds
Started Apr 23 01:13:38 PM PDT 24
Finished Apr 23 01:13:40 PM PDT 24
Peak memory 209064 kb
Host smart-5e119cf0-5724-44de-9b47-98dfa2bbd48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227718652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.227718652
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1901973849
Short name T247
Test name
Test status
Simulation time 677502787 ps
CPU time 10.35 seconds
Started Apr 23 01:13:40 PM PDT 24
Finished Apr 23 01:13:51 PM PDT 24
Peak memory 217480 kb
Host smart-e5f475a7-9e5d-4107-a32f-a476817eae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901973849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1901973849
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.175224661
Short name T625
Test name
Test status
Simulation time 809226977 ps
CPU time 8.6 seconds
Started Apr 23 01:13:41 PM PDT 24
Finished Apr 23 01:13:51 PM PDT 24
Peak memory 209160 kb
Host smart-ed307960-d681-45e9-9c6a-21aa9b48d035
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175224661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.175224661
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3509475281
Short name T798
Test name
Test status
Simulation time 136867575 ps
CPU time 1.62 seconds
Started Apr 23 01:13:40 PM PDT 24
Finished Apr 23 01:13:43 PM PDT 24
Peak memory 217640 kb
Host smart-508c5bde-afa2-420d-b964-1b7f790bd580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509475281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3509475281
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.993824053
Short name T495
Test name
Test status
Simulation time 359277448 ps
CPU time 16.64 seconds
Started Apr 23 01:13:38 PM PDT 24
Finished Apr 23 01:13:55 PM PDT 24
Peak memory 218404 kb
Host smart-9662dc10-4e4d-46db-b9ec-6687c3711a80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993824053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.993824053
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2377619233
Short name T862
Test name
Test status
Simulation time 326397736 ps
CPU time 9.45 seconds
Started Apr 23 01:13:40 PM PDT 24
Finished Apr 23 01:13:50 PM PDT 24
Peak memory 217660 kb
Host smart-ba920ec2-e5aa-4ba5-acd1-82056b89e330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377619233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2377619233
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2285369267
Short name T18
Test name
Test status
Simulation time 1097097964 ps
CPU time 6.33 seconds
Started Apr 23 01:13:39 PM PDT 24
Finished Apr 23 01:13:46 PM PDT 24
Peak memory 217492 kb
Host smart-5932d152-0ba5-459b-80d2-c4de96d51b4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285369267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2285369267
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3281016616
Short name T204
Test name
Test status
Simulation time 307581529 ps
CPU time 10.32 seconds
Started Apr 23 01:13:41 PM PDT 24
Finished Apr 23 01:13:52 PM PDT 24
Peak memory 224280 kb
Host smart-175d2ef2-12bb-410d-9c83-a577f37a4d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281016616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3281016616
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4198483360
Short name T485
Test name
Test status
Simulation time 666429228 ps
CPU time 9.35 seconds
Started Apr 23 01:13:38 PM PDT 24
Finished Apr 23 01:13:47 PM PDT 24
Peak memory 217844 kb
Host smart-5ffbe77e-4cfc-4c87-bdfd-fe0deb11bbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198483360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4198483360
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3742468994
Short name T753
Test name
Test status
Simulation time 759543518 ps
CPU time 33.56 seconds
Started Apr 23 01:13:42 PM PDT 24
Finished Apr 23 01:14:16 PM PDT 24
Peak memory 250600 kb
Host smart-da681ae2-a848-4def-8cf0-5524fb182102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742468994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3742468994
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.4025857742
Short name T647
Test name
Test status
Simulation time 247047357 ps
CPU time 3.34 seconds
Started Apr 23 01:13:39 PM PDT 24
Finished Apr 23 01:13:43 PM PDT 24
Peak memory 221748 kb
Host smart-62f40e26-c351-4727-aaf5-303c5bd04357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025857742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4025857742
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4253011417
Short name T174
Test name
Test status
Simulation time 32127072212 ps
CPU time 118.16 seconds
Started Apr 23 01:13:38 PM PDT 24
Finished Apr 23 01:15:37 PM PDT 24
Peak memory 269496 kb
Host smart-31527357-fa2d-41bf-80ab-c691dbf426e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253011417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4253011417
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1517793936
Short name T386
Test name
Test status
Simulation time 28890375 ps
CPU time 1.42 seconds
Started Apr 23 01:13:41 PM PDT 24
Finished Apr 23 01:13:44 PM PDT 24
Peak memory 209228 kb
Host smart-7a2a75f7-9d64-41c6-b39c-a5dd78120f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517793936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1517793936
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3240640208
Short name T820
Test name
Test status
Simulation time 332135147 ps
CPU time 11.45 seconds
Started Apr 23 01:13:42 PM PDT 24
Finished Apr 23 01:13:55 PM PDT 24
Peak memory 217528 kb
Host smart-906b6fb0-eca4-4cb9-87a6-957bd45ff510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240640208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3240640208
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3501239338
Short name T377
Test name
Test status
Simulation time 167787708 ps
CPU time 1.09 seconds
Started Apr 23 01:13:44 PM PDT 24
Finished Apr 23 01:13:46 PM PDT 24
Peak memory 209156 kb
Host smart-c34e233d-139f-4784-adb6-b263a5c299b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501239338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3501239338
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3919358846
Short name T689
Test name
Test status
Simulation time 99233987 ps
CPU time 1.61 seconds
Started Apr 23 01:13:43 PM PDT 24
Finished Apr 23 01:13:46 PM PDT 24
Peak memory 217572 kb
Host smart-f121bf8d-a6fd-4150-a15d-33cf47e0285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919358846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3919358846
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2574500337
Short name T410
Test name
Test status
Simulation time 1098814027 ps
CPU time 19.39 seconds
Started Apr 23 01:13:41 PM PDT 24
Finished Apr 23 01:14:02 PM PDT 24
Peak memory 225628 kb
Host smart-89f1933e-d684-4f12-b133-cd621dad8900
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574500337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2574500337
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1347090292
Short name T305
Test name
Test status
Simulation time 2857372962 ps
CPU time 9.32 seconds
Started Apr 23 01:13:42 PM PDT 24
Finished Apr 23 01:13:53 PM PDT 24
Peak memory 217588 kb
Host smart-8a877725-530a-4b11-8b2f-6bb1cbc71bd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347090292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1347090292
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.296343508
Short name T616
Test name
Test status
Simulation time 303792118 ps
CPU time 12.19 seconds
Started Apr 23 01:13:43 PM PDT 24
Finished Apr 23 01:13:56 PM PDT 24
Peak memory 217592 kb
Host smart-e0380b2d-b5e9-4ef1-95aa-7dabfa4503f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296343508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.296343508
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2613107274
Short name T757
Test name
Test status
Simulation time 1494614182 ps
CPU time 10.59 seconds
Started Apr 23 01:13:42 PM PDT 24
Finished Apr 23 01:13:53 PM PDT 24
Peak memory 224432 kb
Host smart-150ea436-712c-4a2d-a0f9-359383843b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613107274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2613107274
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3400583924
Short name T320
Test name
Test status
Simulation time 83814987 ps
CPU time 1.53 seconds
Started Apr 23 01:13:47 PM PDT 24
Finished Apr 23 01:13:50 PM PDT 24
Peak memory 217340 kb
Host smart-a7b85cb3-34a2-47a8-bc6a-297ab75a3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400583924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3400583924
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3928948482
Short name T746
Test name
Test status
Simulation time 1049305410 ps
CPU time 33.86 seconds
Started Apr 23 01:13:41 PM PDT 24
Finished Apr 23 01:14:16 PM PDT 24
Peak memory 245884 kb
Host smart-973d6b83-6820-4360-aeb5-216e456deaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928948482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3928948482
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3162892449
Short name T563
Test name
Test status
Simulation time 66513330 ps
CPU time 7.13 seconds
Started Apr 23 01:13:43 PM PDT 24
Finished Apr 23 01:13:51 PM PDT 24
Peak memory 250664 kb
Host smart-f6c7255c-1b5a-46b1-af16-7cd88c01c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162892449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3162892449
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1666867370
Short name T81
Test name
Test status
Simulation time 15826664568 ps
CPU time 93.02 seconds
Started Apr 23 01:13:42 PM PDT 24
Finished Apr 23 01:15:17 PM PDT 24
Peak memory 267052 kb
Host smart-d7050be9-05df-49ee-8f5d-38f11527864b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666867370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1666867370
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3562410086
Short name T162
Test name
Test status
Simulation time 145815088082 ps
CPU time 847.13 seconds
Started Apr 23 01:13:43 PM PDT 24
Finished Apr 23 01:27:51 PM PDT 24
Peak memory 315480 kb
Host smart-38def33a-1cf6-4b13-9e08-5577368bec67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3562410086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3562410086
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.929654235
Short name T310
Test name
Test status
Simulation time 29566573 ps
CPU time 0.96 seconds
Started Apr 23 01:13:45 PM PDT 24
Finished Apr 23 01:13:46 PM PDT 24
Peak memory 212392 kb
Host smart-d0f52010-ec9f-4de3-b5ce-54fe86e404dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929654235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.929654235
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1151358862
Short name T814
Test name
Test status
Simulation time 86083197 ps
CPU time 1.16 seconds
Started Apr 23 01:13:48 PM PDT 24
Finished Apr 23 01:13:50 PM PDT 24
Peak memory 209176 kb
Host smart-00ea0ef1-2fad-42cc-b55a-04837289c6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151358862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1151358862
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2347723006
Short name T17
Test name
Test status
Simulation time 537115074 ps
CPU time 13.08 seconds
Started Apr 23 01:13:45 PM PDT 24
Finished Apr 23 01:14:00 PM PDT 24
Peak memory 225672 kb
Host smart-1f48e498-eaf2-4155-80dc-10db19a6100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347723006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2347723006
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2588572818
Short name T852
Test name
Test status
Simulation time 2953779525 ps
CPU time 5.8 seconds
Started Apr 23 01:13:51 PM PDT 24
Finished Apr 23 01:13:58 PM PDT 24
Peak memory 209188 kb
Host smart-b6cdc3f6-bffa-49b5-a04c-faae8feae1df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588572818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2588572818
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.780865512
Short name T600
Test name
Test status
Simulation time 118475685 ps
CPU time 1.86 seconds
Started Apr 23 01:13:46 PM PDT 24
Finished Apr 23 01:13:49 PM PDT 24
Peak memory 217588 kb
Host smart-59288dc9-7fa0-46af-877f-7aad6e2ac9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780865512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.780865512
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.417473378
Short name T806
Test name
Test status
Simulation time 467699672 ps
CPU time 15.67 seconds
Started Apr 23 01:13:47 PM PDT 24
Finished Apr 23 01:14:04 PM PDT 24
Peak memory 217576 kb
Host smart-9cfe19c7-b1bf-4814-8e4f-3db05b058005
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417473378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.417473378
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3130922778
Short name T507
Test name
Test status
Simulation time 1680486495 ps
CPU time 16.08 seconds
Started Apr 23 01:13:47 PM PDT 24
Finished Apr 23 01:14:04 PM PDT 24
Peak memory 217484 kb
Host smart-3b894177-b944-488c-a827-4d57e6af0c47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130922778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3130922778
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3379488074
Short name T327
Test name
Test status
Simulation time 3097565338 ps
CPU time 23.23 seconds
Started Apr 23 01:13:47 PM PDT 24
Finished Apr 23 01:14:11 PM PDT 24
Peak memory 217648 kb
Host smart-08d1e125-1690-4f37-9399-f5f366919592
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379488074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3379488074
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3306022554
Short name T321
Test name
Test status
Simulation time 17774269 ps
CPU time 1.39 seconds
Started Apr 23 01:13:42 PM PDT 24
Finished Apr 23 01:13:45 PM PDT 24
Peak memory 217480 kb
Host smart-12cd4742-3454-4f01-9e4e-990d4d81e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306022554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3306022554
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1740531228
Short name T779
Test name
Test status
Simulation time 550701629 ps
CPU time 21.54 seconds
Started Apr 23 01:13:44 PM PDT 24
Finished Apr 23 01:14:06 PM PDT 24
Peak memory 250604 kb
Host smart-21645e13-2683-4219-91db-61447db3068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740531228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1740531228
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2657801480
Short name T423
Test name
Test status
Simulation time 118930491 ps
CPU time 7.01 seconds
Started Apr 23 01:13:46 PM PDT 24
Finished Apr 23 01:13:54 PM PDT 24
Peak memory 249832 kb
Host smart-76b8f1ae-9a02-4345-b219-103b674ed872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657801480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2657801480
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1582191526
Short name T693
Test name
Test status
Simulation time 41881865539 ps
CPU time 468.4 seconds
Started Apr 23 01:13:46 PM PDT 24
Finished Apr 23 01:21:36 PM PDT 24
Peak memory 282648 kb
Host smart-98edfff4-b36a-46c5-97c6-364712a9609f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582191526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1582191526
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2484532020
Short name T405
Test name
Test status
Simulation time 35899783 ps
CPU time 0.73 seconds
Started Apr 23 01:13:43 PM PDT 24
Finished Apr 23 01:13:45 PM PDT 24
Peak memory 206788 kb
Host smart-008b3a89-b9b3-43a7-af4a-0dc52357d617
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484532020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2484532020
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1296124802
Short name T530
Test name
Test status
Simulation time 12695463 ps
CPU time 0.99 seconds
Started Apr 23 01:13:51 PM PDT 24
Finished Apr 23 01:13:52 PM PDT 24
Peak memory 209176 kb
Host smart-baef47b8-4702-4f60-aa18-ca854f6c3e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296124802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1296124802
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2450222144
Short name T308
Test name
Test status
Simulation time 304153629 ps
CPU time 12.58 seconds
Started Apr 23 01:13:46 PM PDT 24
Finished Apr 23 01:13:59 PM PDT 24
Peak memory 225604 kb
Host smart-de46ffac-5db7-4507-916e-7b6a8a9bbfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450222144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2450222144
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.884124342
Short name T412
Test name
Test status
Simulation time 224094574 ps
CPU time 1.39 seconds
Started Apr 23 01:13:45 PM PDT 24
Finished Apr 23 01:13:48 PM PDT 24
Peak memory 216448 kb
Host smart-c6a5af05-34ce-41ae-81e2-3475522e2eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884124342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.884124342
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3691930361
Short name T363
Test name
Test status
Simulation time 65325782 ps
CPU time 2.53 seconds
Started Apr 23 01:13:48 PM PDT 24
Finished Apr 23 01:13:51 PM PDT 24
Peak memory 217532 kb
Host smart-dd7fd3be-3d4f-4f42-b2eb-fc50856207f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691930361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3691930361
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1018158612
Short name T709
Test name
Test status
Simulation time 742259638 ps
CPU time 14.79 seconds
Started Apr 23 01:13:49 PM PDT 24
Finished Apr 23 01:14:05 PM PDT 24
Peak memory 217600 kb
Host smart-638b60a7-6c53-4703-ae02-1a007fa2b714
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018158612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1018158612
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2208317770
Short name T558
Test name
Test status
Simulation time 202757908 ps
CPU time 6.14 seconds
Started Apr 23 01:13:46 PM PDT 24
Finished Apr 23 01:13:53 PM PDT 24
Peak memory 217548 kb
Host smart-e6a5b1b2-69b2-4e47-8ac5-333d7ca79bfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208317770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2208317770
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.18664105
Short name T342
Test name
Test status
Simulation time 229897471 ps
CPU time 7.75 seconds
Started Apr 23 01:13:45 PM PDT 24
Finished Apr 23 01:13:54 PM PDT 24
Peak memory 217600 kb
Host smart-afab0277-3e83-4807-a62e-61c9834333e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18664105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.18664105
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3021752677
Short name T78
Test name
Test status
Simulation time 320263656 ps
CPU time 2.99 seconds
Started Apr 23 01:13:47 PM PDT 24
Finished Apr 23 01:13:51 PM PDT 24
Peak memory 217392 kb
Host smart-be98090e-c90b-4ec2-9c70-77cb04911d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021752677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3021752677
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.898003387
Short name T329
Test name
Test status
Simulation time 261222454 ps
CPU time 20.73 seconds
Started Apr 23 01:13:44 PM PDT 24
Finished Apr 23 01:14:05 PM PDT 24
Peak memory 245256 kb
Host smart-aa2f62a4-c7cb-48eb-b3fd-7c874e8e28f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898003387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.898003387
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.273054533
Short name T742
Test name
Test status
Simulation time 379882883 ps
CPU time 8.47 seconds
Started Apr 23 01:13:52 PM PDT 24
Finished Apr 23 01:14:01 PM PDT 24
Peak memory 250388 kb
Host smart-1c57b7a8-f55f-4031-a3f7-4c9eef9890bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273054533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.273054533
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2399005008
Short name T818
Test name
Test status
Simulation time 40214102909 ps
CPU time 166.64 seconds
Started Apr 23 01:13:50 PM PDT 24
Finished Apr 23 01:16:38 PM PDT 24
Peak memory 250688 kb
Host smart-52d4ecda-ced5-429e-a219-81e50145cd89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399005008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2399005008
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.433327243
Short name T426
Test name
Test status
Simulation time 34423212 ps
CPU time 0.75 seconds
Started Apr 23 01:13:46 PM PDT 24
Finished Apr 23 01:13:48 PM PDT 24
Peak memory 208004 kb
Host smart-43bb4c1b-92a2-42f1-8aa2-40b81b54a42f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433327243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.433327243
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4075382474
Short name T277
Test name
Test status
Simulation time 86918850 ps
CPU time 0.91 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:14:11 PM PDT 24
Peak memory 209188 kb
Host smart-1319f134-cc90-4b4c-a235-423636173e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075382474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4075382474
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.4001976972
Short name T388
Test name
Test status
Simulation time 2074035580 ps
CPU time 10.06 seconds
Started Apr 23 01:13:50 PM PDT 24
Finished Apr 23 01:14:01 PM PDT 24
Peak memory 217500 kb
Host smart-324fdc0a-55d0-4be4-8c78-4b7bc2769374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001976972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4001976972
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2803332499
Short name T499
Test name
Test status
Simulation time 145684944 ps
CPU time 3.44 seconds
Started Apr 23 01:13:54 PM PDT 24
Finished Apr 23 01:13:58 PM PDT 24
Peak memory 209072 kb
Host smart-c2239800-edcc-45d2-8be6-7cbb6455123d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803332499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2803332499
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1168747278
Short name T445
Test name
Test status
Simulation time 16053030 ps
CPU time 1.69 seconds
Started Apr 23 01:13:50 PM PDT 24
Finished Apr 23 01:13:53 PM PDT 24
Peak memory 217548 kb
Host smart-fae7314f-12c0-4a19-9391-b7064b44f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168747278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1168747278
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.760735009
Short name T703
Test name
Test status
Simulation time 1299658100 ps
CPU time 19.44 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:14:30 PM PDT 24
Peak memory 225628 kb
Host smart-5d910850-1d12-4cfa-aa46-2518c677f40c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760735009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.760735009
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1120317686
Short name T32
Test name
Test status
Simulation time 1290885834 ps
CPU time 25.77 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:14:36 PM PDT 24
Peak memory 217628 kb
Host smart-10edb190-0dc1-47c5-8e5a-6a58898d3e1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120317686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1120317686
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3767837186
Short name T246
Test name
Test status
Simulation time 325736344 ps
CPU time 9.13 seconds
Started Apr 23 01:13:56 PM PDT 24
Finished Apr 23 01:14:06 PM PDT 24
Peak memory 217584 kb
Host smart-d509e273-0c8c-48a4-a8fb-e3772011f169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767837186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3767837186
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3125602181
Short name T202
Test name
Test status
Simulation time 963796645 ps
CPU time 10.36 seconds
Started Apr 23 01:13:52 PM PDT 24
Finished Apr 23 01:14:03 PM PDT 24
Peak memory 217604 kb
Host smart-4314fc32-62b1-4788-8101-1f0c3192a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125602181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3125602181
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.711098087
Short name T483
Test name
Test status
Simulation time 30230525 ps
CPU time 1.5 seconds
Started Apr 23 01:13:50 PM PDT 24
Finished Apr 23 01:13:52 PM PDT 24
Peak memory 213212 kb
Host smart-4d6a9b4a-c2c5-4cba-86ee-9d8cac74b56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711098087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.711098087
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1798822719
Short name T801
Test name
Test status
Simulation time 272912972 ps
CPU time 26.57 seconds
Started Apr 23 01:13:53 PM PDT 24
Finished Apr 23 01:14:20 PM PDT 24
Peak memory 250604 kb
Host smart-2d068c96-53e8-4852-bd92-17a6a3e7f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798822719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1798822719
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.462807517
Short name T330
Test name
Test status
Simulation time 976324536 ps
CPU time 7.27 seconds
Started Apr 23 01:13:52 PM PDT 24
Finished Apr 23 01:14:00 PM PDT 24
Peak memory 246772 kb
Host smart-65004d01-0892-4552-956e-38f006c6ce9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462807517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.462807517
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.4149580388
Short name T631
Test name
Test status
Simulation time 8973533769 ps
CPU time 67.93 seconds
Started Apr 23 01:13:53 PM PDT 24
Finished Apr 23 01:15:02 PM PDT 24
Peak memory 277664 kb
Host smart-f2be5716-2ee3-40ad-8bed-7a6a337c8919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149580388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.4149580388
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2864795823
Short name T681
Test name
Test status
Simulation time 39036435 ps
CPU time 0.77 seconds
Started Apr 23 01:13:52 PM PDT 24
Finished Apr 23 01:13:53 PM PDT 24
Peak memory 208056 kb
Host smart-ab5b7e28-59e7-4a8b-990b-e18c1a244e8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864795823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2864795823
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3731691690
Short name T651
Test name
Test status
Simulation time 56433709 ps
CPU time 0.89 seconds
Started Apr 23 01:13:56 PM PDT 24
Finished Apr 23 01:13:57 PM PDT 24
Peak memory 209180 kb
Host smart-a90ad746-14fb-450a-975c-52ce5d59b1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731691690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3731691690
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3710185187
Short name T458
Test name
Test status
Simulation time 848475355 ps
CPU time 11.1 seconds
Started Apr 23 01:13:56 PM PDT 24
Finished Apr 23 01:14:08 PM PDT 24
Peak memory 217528 kb
Host smart-e481fcc5-016f-4208-ab0a-7ad7bb865671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710185187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3710185187
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1283616108
Short name T25
Test name
Test status
Simulation time 1345853134 ps
CPU time 9.43 seconds
Started Apr 23 01:13:53 PM PDT 24
Finished Apr 23 01:14:04 PM PDT 24
Peak memory 209232 kb
Host smart-815afc2b-5d59-46a2-8480-fb5ef9019f9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283616108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1283616108
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.424403535
Short name T816
Test name
Test status
Simulation time 88578051 ps
CPU time 2.69 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:14:13 PM PDT 24
Peak memory 217492 kb
Host smart-52854ade-f38d-48cc-a50f-6f90b86150db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424403535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.424403535
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.221983858
Short name T570
Test name
Test status
Simulation time 185179696 ps
CPU time 9.56 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:14:20 PM PDT 24
Peak memory 217708 kb
Host smart-c8419c67-e128-45e4-a163-629ea03d9768
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221983858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.221983858
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1785590246
Short name T490
Test name
Test status
Simulation time 1514322530 ps
CPU time 11.18 seconds
Started Apr 23 01:13:53 PM PDT 24
Finished Apr 23 01:14:05 PM PDT 24
Peak memory 217556 kb
Host smart-3e72762c-8829-45af-9a0a-396c97ea7828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785590246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1785590246
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2157747439
Short name T644
Test name
Test status
Simulation time 640035621 ps
CPU time 12.92 seconds
Started Apr 23 01:13:53 PM PDT 24
Finished Apr 23 01:14:07 PM PDT 24
Peak memory 217544 kb
Host smart-ec03c655-a4d8-4585-bed4-fd9508e905a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157747439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2157747439
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3470927391
Short name T415
Test name
Test status
Simulation time 380476176 ps
CPU time 8.72 seconds
Started Apr 23 01:13:56 PM PDT 24
Finished Apr 23 01:14:05 PM PDT 24
Peak memory 217604 kb
Host smart-165b3639-9d20-4194-b770-8b2183e54aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470927391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3470927391
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1427862471
Short name T754
Test name
Test status
Simulation time 104684209 ps
CPU time 2.54 seconds
Started Apr 23 01:13:54 PM PDT 24
Finished Apr 23 01:13:58 PM PDT 24
Peak memory 214044 kb
Host smart-6b5fdd10-3998-4550-9c6f-cbe5042b3f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427862471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1427862471
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2543993502
Short name T791
Test name
Test status
Simulation time 238465034 ps
CPU time 25.74 seconds
Started Apr 23 01:13:55 PM PDT 24
Finished Apr 23 01:14:21 PM PDT 24
Peak memory 250508 kb
Host smart-580ad5e7-d63c-4edd-938e-74b74d06624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543993502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2543993502
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3190089188
Short name T837
Test name
Test status
Simulation time 46951029 ps
CPU time 6.7 seconds
Started Apr 23 01:13:56 PM PDT 24
Finished Apr 23 01:14:04 PM PDT 24
Peak memory 250568 kb
Host smart-2b6783c2-2aef-4fc1-8778-41f0d28d56cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190089188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3190089188
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.4144911340
Short name T613
Test name
Test status
Simulation time 12928923343 ps
CPU time 409.98 seconds
Started Apr 23 01:13:53 PM PDT 24
Finished Apr 23 01:20:43 PM PDT 24
Peak memory 283452 kb
Host smart-f60283aa-21c2-4281-9c80-9605c27860ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144911340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.4144911340
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1290960149
Short name T39
Test name
Test status
Simulation time 11871390 ps
CPU time 0.85 seconds
Started Apr 23 01:14:09 PM PDT 24
Finished Apr 23 01:14:11 PM PDT 24
Peak memory 208216 kb
Host smart-46dee284-1cda-483f-8c09-84461226ba2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290960149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1290960149
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1469069178
Short name T596
Test name
Test status
Simulation time 21884280 ps
CPU time 0.83 seconds
Started Apr 23 01:10:56 PM PDT 24
Finished Apr 23 01:10:59 PM PDT 24
Peak memory 209152 kb
Host smart-c27a8553-bc0d-405d-929a-4e0da78c16c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469069178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1469069178
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.551712429
Short name T197
Test name
Test status
Simulation time 37589595 ps
CPU time 0.79 seconds
Started Apr 23 01:10:52 PM PDT 24
Finished Apr 23 01:10:55 PM PDT 24
Peak memory 208920 kb
Host smart-00dd5b64-0b31-4a4f-b287-80024b3c4baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551712429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.551712429
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2515086163
Short name T439
Test name
Test status
Simulation time 709285202 ps
CPU time 14.45 seconds
Started Apr 23 01:10:48 PM PDT 24
Finished Apr 23 01:11:05 PM PDT 24
Peak memory 217476 kb
Host smart-90d1e713-3fd7-4720-8c66-a35a1cefd4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515086163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2515086163
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3974229426
Short name T610
Test name
Test status
Simulation time 196452923 ps
CPU time 2.87 seconds
Started Apr 23 01:10:49 PM PDT 24
Finished Apr 23 01:10:54 PM PDT 24
Peak memory 209256 kb
Host smart-f833f60f-4ec4-4c4b-b8d5-137f0467ef5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974229426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3974229426
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3143032264
Short name T160
Test name
Test status
Simulation time 4537505626 ps
CPU time 79.92 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:12:13 PM PDT 24
Peak memory 218504 kb
Host smart-f8bc914c-fb52-4b40-960c-62dc15464b00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143032264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3143032264
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2970821077
Short name T514
Test name
Test status
Simulation time 252494284 ps
CPU time 7.56 seconds
Started Apr 23 01:10:49 PM PDT 24
Finished Apr 23 01:10:58 PM PDT 24
Peak memory 217296 kb
Host smart-8744d331-d686-4028-ac65-d53929a51ca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970821077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
970821077
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1488809664
Short name T840
Test name
Test status
Simulation time 740355536 ps
CPU time 6.06 seconds
Started Apr 23 01:10:56 PM PDT 24
Finished Apr 23 01:11:04 PM PDT 24
Peak memory 217644 kb
Host smart-628b6960-9868-4948-a9d7-4b2020c9b9f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488809664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1488809664
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3051143084
Short name T360
Test name
Test status
Simulation time 1339637916 ps
CPU time 39.36 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:11:32 PM PDT 24
Peak memory 213024 kb
Host smart-87ae6aef-94f8-4aed-b837-8130e776f05d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051143084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3051143084
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1997676069
Short name T344
Test name
Test status
Simulation time 362501072 ps
CPU time 2.85 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 212600 kb
Host smart-be5fd8c3-51e7-41d5-9152-37c216a4dcba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997676069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1997676069
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1938339466
Short name T602
Test name
Test status
Simulation time 8030733712 ps
CPU time 45.57 seconds
Started Apr 23 01:10:49 PM PDT 24
Finished Apr 23 01:11:36 PM PDT 24
Peak memory 268460 kb
Host smart-e43a4bc0-b6ac-45d7-8b0f-65c7bd286d60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938339466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1938339466
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3216856934
Short name T468
Test name
Test status
Simulation time 262255938 ps
CPU time 13.26 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:11:06 PM PDT 24
Peak memory 245888 kb
Host smart-d0012425-d775-44f9-8e59-be1b2145f7cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216856934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3216856934
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.4231388387
Short name T338
Test name
Test status
Simulation time 159788923 ps
CPU time 1.66 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:10:54 PM PDT 24
Peak memory 217516 kb
Host smart-f6eff2c0-12e0-479f-a1a9-1864960e02cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231388387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4231388387
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2388632956
Short name T177
Test name
Test status
Simulation time 863108743 ps
CPU time 8.07 seconds
Started Apr 23 01:10:50 PM PDT 24
Finished Apr 23 01:10:59 PM PDT 24
Peak memory 217496 kb
Host smart-c988983a-9a4a-48d5-93dd-5694e2d9b517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388632956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2388632956
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3565049216
Short name T641
Test name
Test status
Simulation time 753529108 ps
CPU time 22.57 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:11:15 PM PDT 24
Peak memory 218448 kb
Host smart-14abee87-0113-4a58-bd9a-1d71f04dea70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565049216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3565049216
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.4105355853
Short name T868
Test name
Test status
Simulation time 363985021 ps
CPU time 14.74 seconds
Started Apr 23 01:10:56 PM PDT 24
Finished Apr 23 01:11:12 PM PDT 24
Peak memory 217664 kb
Host smart-8db0d601-0c1d-43e8-b9cc-33674cad9bac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105355853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.4105355853
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.165037708
Short name T854
Test name
Test status
Simulation time 523009742 ps
CPU time 10.8 seconds
Started Apr 23 01:10:52 PM PDT 24
Finished Apr 23 01:11:05 PM PDT 24
Peak memory 217640 kb
Host smart-92568dfc-25f3-4436-b970-2239ed8d3c9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165037708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.165037708
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2862246022
Short name T475
Test name
Test status
Simulation time 252940688 ps
CPU time 9.81 seconds
Started Apr 23 01:10:52 PM PDT 24
Finished Apr 23 01:11:04 PM PDT 24
Peak memory 217652 kb
Host smart-4ab621c1-9e8c-432e-841f-74ba24869efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862246022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2862246022
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3684362905
Short name T648
Test name
Test status
Simulation time 183773519 ps
CPU time 2.68 seconds
Started Apr 23 01:10:50 PM PDT 24
Finished Apr 23 01:10:54 PM PDT 24
Peak memory 213576 kb
Host smart-38f29f5a-4b33-4dc1-8528-e06312ad60b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684362905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3684362905
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.400703177
Short name T849
Test name
Test status
Simulation time 248864296 ps
CPU time 19.42 seconds
Started Apr 23 01:10:56 PM PDT 24
Finished Apr 23 01:11:17 PM PDT 24
Peak memory 250640 kb
Host smart-be912eab-71fb-44fd-a229-28759d879441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400703177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.400703177
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2727853876
Short name T808
Test name
Test status
Simulation time 63736962 ps
CPU time 6.56 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:11:00 PM PDT 24
Peak memory 250632 kb
Host smart-3ae04e57-264f-4c83-ad4a-43e242ff8560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727853876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2727853876
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2699370481
Short name T534
Test name
Test status
Simulation time 7858579574 ps
CPU time 174.35 seconds
Started Apr 23 01:10:50 PM PDT 24
Finished Apr 23 01:13:46 PM PDT 24
Peak memory 268676 kb
Host smart-6677757a-fa8c-43b4-8b4c-48f888ec8a01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699370481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2699370481
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.478541867
Short name T872
Test name
Test status
Simulation time 33568161 ps
CPU time 0.94 seconds
Started Apr 23 01:10:55 PM PDT 24
Finished Apr 23 01:10:58 PM PDT 24
Peak memory 212308 kb
Host smart-f71b9ad1-45ea-44df-9ee8-62cf1f1087dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478541867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.478541867
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2456698824
Short name T790
Test name
Test status
Simulation time 27822192 ps
CPU time 0.85 seconds
Started Apr 23 01:10:57 PM PDT 24
Finished Apr 23 01:10:59 PM PDT 24
Peak memory 208972 kb
Host smart-1c7b699a-c1e0-45db-b19e-3cfdcabce205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456698824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2456698824
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3669880239
Short name T572
Test name
Test status
Simulation time 44684164 ps
CPU time 0.94 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:10:54 PM PDT 24
Peak memory 209124 kb
Host smart-b64c987b-c570-496c-94cf-7a97afb56543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669880239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3669880239
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.36599404
Short name T510
Test name
Test status
Simulation time 934357507 ps
CPU time 11.36 seconds
Started Apr 23 01:10:53 PM PDT 24
Finished Apr 23 01:11:06 PM PDT 24
Peak memory 217524 kb
Host smart-ee2516d9-0406-4c17-90c0-672617caf338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36599404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.36599404
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1787498979
Short name T456
Test name
Test status
Simulation time 133121344 ps
CPU time 1.6 seconds
Started Apr 23 01:10:53 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 209116 kb
Host smart-36306204-0abd-4841-8e1b-c197914df6cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787498979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1787498979
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.790278892
Short name T447
Test name
Test status
Simulation time 2465988067 ps
CPU time 31.17 seconds
Started Apr 23 01:10:55 PM PDT 24
Finished Apr 23 01:11:28 PM PDT 24
Peak memory 217484 kb
Host smart-7aa4a514-52a7-44e3-812c-6fdf600a7114
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790278892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.790278892
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3823486760
Short name T22
Test name
Test status
Simulation time 7809853825 ps
CPU time 16.73 seconds
Started Apr 23 01:10:52 PM PDT 24
Finished Apr 23 01:11:11 PM PDT 24
Peak memory 217364 kb
Host smart-96ae428f-6132-4669-87b9-f7473f52d0ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823486760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
823486760
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.707868844
Short name T354
Test name
Test status
Simulation time 510946565 ps
CPU time 8.88 seconds
Started Apr 23 01:10:53 PM PDT 24
Finished Apr 23 01:11:03 PM PDT 24
Peak memory 217512 kb
Host smart-056d9827-a546-486f-9749-e79e9acf852c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707868844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.707868844
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2979020841
Short name T172
Test name
Test status
Simulation time 3653104691 ps
CPU time 12.19 seconds
Started Apr 23 01:10:52 PM PDT 24
Finished Apr 23 01:11:06 PM PDT 24
Peak memory 213428 kb
Host smart-bf97fe64-752c-40fe-9146-eedbd1d60677
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979020841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2979020841
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.852035250
Short name T372
Test name
Test status
Simulation time 203903188 ps
CPU time 5.33 seconds
Started Apr 23 01:10:53 PM PDT 24
Finished Apr 23 01:11:00 PM PDT 24
Peak memory 212724 kb
Host smart-f289f366-165e-4658-bcc3-20931df49f64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852035250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.852035250
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2638620949
Short name T216
Test name
Test status
Simulation time 15334489680 ps
CPU time 85.21 seconds
Started Apr 23 01:10:54 PM PDT 24
Finished Apr 23 01:12:20 PM PDT 24
Peak memory 268652 kb
Host smart-b12716bb-8210-4337-becd-8f0cc67d79c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638620949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2638620949
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2400261438
Short name T822
Test name
Test status
Simulation time 682548358 ps
CPU time 18.69 seconds
Started Apr 23 01:10:53 PM PDT 24
Finished Apr 23 01:11:14 PM PDT 24
Peak memory 249852 kb
Host smart-7b197f76-3bf0-4d44-bb2d-46445e855584
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400261438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2400261438
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2567222954
Short name T605
Test name
Test status
Simulation time 62158106 ps
CPU time 3.58 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 217524 kb
Host smart-c7f644b6-cb11-4c63-ae13-b237f2658a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567222954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2567222954
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3221768993
Short name T594
Test name
Test status
Simulation time 861590935 ps
CPU time 7.96 seconds
Started Apr 23 01:10:54 PM PDT 24
Finished Apr 23 01:11:03 PM PDT 24
Peak memory 217512 kb
Host smart-db778f72-a07e-492e-a82f-f52f718fce58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221768993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3221768993
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3296535174
Short name T712
Test name
Test status
Simulation time 1227059580 ps
CPU time 13.25 seconds
Started Apr 23 01:10:55 PM PDT 24
Finished Apr 23 01:11:10 PM PDT 24
Peak memory 218264 kb
Host smart-348a9027-52a9-4e53-ab85-088142c8b683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296535174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3296535174
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2575061788
Short name T545
Test name
Test status
Simulation time 860235993 ps
CPU time 7.63 seconds
Started Apr 23 01:10:57 PM PDT 24
Finished Apr 23 01:11:06 PM PDT 24
Peak memory 217656 kb
Host smart-b2890bd4-f1af-4582-8352-ddc18f4dc966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575061788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2575061788
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2873806182
Short name T266
Test name
Test status
Simulation time 409299977 ps
CPU time 8.88 seconds
Started Apr 23 01:10:57 PM PDT 24
Finished Apr 23 01:11:07 PM PDT 24
Peak memory 217532 kb
Host smart-0fa1cabc-9a3a-40cc-8fb3-222ee419b3ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873806182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
873806182
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2732717257
Short name T453
Test name
Test status
Simulation time 451000667 ps
CPU time 9.44 seconds
Started Apr 23 01:10:53 PM PDT 24
Finished Apr 23 01:11:04 PM PDT 24
Peak memory 224368 kb
Host smart-31d535e3-6dff-424a-a856-aae8b34a0498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732717257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2732717257
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.533608858
Short name T312
Test name
Test status
Simulation time 482989759 ps
CPU time 2.78 seconds
Started Apr 23 01:10:50 PM PDT 24
Finished Apr 23 01:10:54 PM PDT 24
Peak memory 214020 kb
Host smart-f9c7711f-3532-4358-b664-fdd91ba2fe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533608858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.533608858
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1592972495
Short name T484
Test name
Test status
Simulation time 158547459 ps
CPU time 23.35 seconds
Started Apr 23 01:10:51 PM PDT 24
Finished Apr 23 01:11:17 PM PDT 24
Peak memory 244176 kb
Host smart-9b7694eb-8134-4b9a-adfa-badd7bb08930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592972495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1592972495
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1564918894
Short name T535
Test name
Test status
Simulation time 156191872 ps
CPU time 7.86 seconds
Started Apr 23 01:10:52 PM PDT 24
Finished Apr 23 01:11:02 PM PDT 24
Peak memory 250188 kb
Host smart-0c230fae-2425-4333-b8c4-f4529554f92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564918894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1564918894
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3205815349
Short name T727
Test name
Test status
Simulation time 3088547721 ps
CPU time 88.84 seconds
Started Apr 23 01:10:57 PM PDT 24
Finished Apr 23 01:12:27 PM PDT 24
Peak memory 266996 kb
Host smart-abdde85e-66ba-4db2-b7c3-32c17e63a7db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205815349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3205815349
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.23673643
Short name T270
Test name
Test status
Simulation time 15151105 ps
CPU time 0.81 seconds
Started Apr 23 01:10:53 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 208136 kb
Host smart-6e5aea41-fbd4-407e-9d82-9c41f182066c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23673643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_volatile_unlock_smoke.23673643
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2572626260
Short name T2
Test name
Test status
Simulation time 14918634 ps
CPU time 0.88 seconds
Started Apr 23 01:11:04 PM PDT 24
Finished Apr 23 01:11:05 PM PDT 24
Peak memory 209160 kb
Host smart-3bc6d4cc-cfa0-48bb-91ae-b0c6f4288f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572626260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2572626260
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.70614715
Short name T200
Test name
Test status
Simulation time 31837125 ps
CPU time 0.92 seconds
Started Apr 23 01:11:00 PM PDT 24
Finished Apr 23 01:11:01 PM PDT 24
Peak memory 209088 kb
Host smart-65341172-2b84-4c72-8130-473979511ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70614715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.70614715
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1121232418
Short name T679
Test name
Test status
Simulation time 1198798587 ps
CPU time 14.01 seconds
Started Apr 23 01:10:58 PM PDT 24
Finished Apr 23 01:11:13 PM PDT 24
Peak memory 217528 kb
Host smart-6fbccb31-7b82-48ee-894a-710a91c7788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121232418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1121232418
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.966561379
Short name T90
Test name
Test status
Simulation time 471085326 ps
CPU time 7.28 seconds
Started Apr 23 01:11:04 PM PDT 24
Finished Apr 23 01:11:12 PM PDT 24
Peak memory 209104 kb
Host smart-b55bcae2-0df3-49df-b993-e0eb7e316605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966561379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.966561379
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.708906831
Short name T161
Test name
Test status
Simulation time 1421891832 ps
CPU time 45.38 seconds
Started Apr 23 01:11:08 PM PDT 24
Finished Apr 23 01:11:54 PM PDT 24
Peak memory 217504 kb
Host smart-1e3dc69e-847c-4390-9574-f32ba0e33f2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708906831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.708906831
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1161492289
Short name T281
Test name
Test status
Simulation time 239573402 ps
CPU time 6.03 seconds
Started Apr 23 01:11:04 PM PDT 24
Finished Apr 23 01:11:11 PM PDT 24
Peak memory 217272 kb
Host smart-9eac53c2-3c1f-46be-b8b1-47b9e92c319b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161492289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
161492289
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3566887025
Short name T827
Test name
Test status
Simulation time 494428471 ps
CPU time 4.9 seconds
Started Apr 23 01:11:01 PM PDT 24
Finished Apr 23 01:11:06 PM PDT 24
Peak memory 217384 kb
Host smart-971a0460-f4f4-4180-8ad8-143900edd578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566887025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3566887025
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3609866604
Short name T686
Test name
Test status
Simulation time 1939657294 ps
CPU time 20.71 seconds
Started Apr 23 01:11:03 PM PDT 24
Finished Apr 23 01:11:24 PM PDT 24
Peak memory 212812 kb
Host smart-c7dc8d68-82cb-4743-b44d-366e3108e95e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609866604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3609866604
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1026608214
Short name T559
Test name
Test status
Simulation time 403440189 ps
CPU time 5.03 seconds
Started Apr 23 01:11:00 PM PDT 24
Finished Apr 23 01:11:06 PM PDT 24
Peak memory 213096 kb
Host smart-75cb964c-6691-459a-b9ab-438094d86681
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026608214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1026608214
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1642481681
Short name T682
Test name
Test status
Simulation time 11368769085 ps
CPU time 47.73 seconds
Started Apr 23 01:11:01 PM PDT 24
Finished Apr 23 01:11:50 PM PDT 24
Peak memory 266972 kb
Host smart-f18a374f-399c-447b-af97-9a69faddac9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642481681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1642481681
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.4156705816
Short name T685
Test name
Test status
Simulation time 1363931958 ps
CPU time 11.27 seconds
Started Apr 23 01:11:00 PM PDT 24
Finished Apr 23 01:11:12 PM PDT 24
Peak memory 246096 kb
Host smart-fb04295e-da4d-483a-b349-a6c60fb03252
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156705816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.4156705816
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2211695416
Short name T575
Test name
Test status
Simulation time 71485981 ps
CPU time 3.94 seconds
Started Apr 23 01:10:57 PM PDT 24
Finished Apr 23 01:11:03 PM PDT 24
Peak memory 217584 kb
Host smart-d9573085-39c6-4a0c-9049-7292fa4ba5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211695416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2211695416
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2061844800
Short name T417
Test name
Test status
Simulation time 893164141 ps
CPU time 15.25 seconds
Started Apr 23 01:11:01 PM PDT 24
Finished Apr 23 01:11:16 PM PDT 24
Peak memory 213832 kb
Host smart-54b04e82-dc75-424e-a7a6-b1a4ecb8e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061844800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2061844800
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2343019201
Short name T599
Test name
Test status
Simulation time 303378878 ps
CPU time 14.18 seconds
Started Apr 23 01:11:05 PM PDT 24
Finished Apr 23 01:11:20 PM PDT 24
Peak memory 218568 kb
Host smart-6de276ec-bb36-4980-b2d4-20b100aedda3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343019201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2343019201
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2148468762
Short name T668
Test name
Test status
Simulation time 469628457 ps
CPU time 10.13 seconds
Started Apr 23 01:11:05 PM PDT 24
Finished Apr 23 01:11:16 PM PDT 24
Peak memory 217516 kb
Host smart-1f8be643-8f15-4c7e-8d84-cf249fc6d369
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148468762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2148468762
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3639147945
Short name T231
Test name
Test status
Simulation time 879560083 ps
CPU time 7.93 seconds
Started Apr 23 01:11:03 PM PDT 24
Finished Apr 23 01:11:12 PM PDT 24
Peak memory 217588 kb
Host smart-ca91634b-e0fd-4738-94fc-6d907e8d777c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639147945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
639147945
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2787606219
Short name T734
Test name
Test status
Simulation time 97369069 ps
CPU time 1.98 seconds
Started Apr 23 01:10:56 PM PDT 24
Finished Apr 23 01:10:59 PM PDT 24
Peak memory 213200 kb
Host smart-c982714b-7746-4e3a-930c-3326da0c9c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787606219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2787606219
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2656607515
Short name T274
Test name
Test status
Simulation time 1050029538 ps
CPU time 32.23 seconds
Started Apr 23 01:10:57 PM PDT 24
Finished Apr 23 01:11:31 PM PDT 24
Peak memory 250676 kb
Host smart-b5e71835-52e6-429e-9b80-baef7747e85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656607515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2656607515
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2701253829
Short name T702
Test name
Test status
Simulation time 72492417 ps
CPU time 8.21 seconds
Started Apr 23 01:10:57 PM PDT 24
Finished Apr 23 01:11:07 PM PDT 24
Peak memory 250544 kb
Host smart-f8850d40-140f-459a-baea-be5921a90280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701253829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2701253829
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4145781606
Short name T173
Test name
Test status
Simulation time 44020890514 ps
CPU time 238.44 seconds
Started Apr 23 01:11:05 PM PDT 24
Finished Apr 23 01:15:04 PM PDT 24
Peak memory 267016 kb
Host smart-48d72312-319b-4b73-914e-f7dcff4852c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145781606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4145781606
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3643788973
Short name T235
Test name
Test status
Simulation time 23516420 ps
CPU time 1.09 seconds
Started Apr 23 01:10:58 PM PDT 24
Finished Apr 23 01:11:00 PM PDT 24
Peak memory 211272 kb
Host smart-e069b909-e250-495f-b616-73a304c3307e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643788973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3643788973
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1939229453
Short name T365
Test name
Test status
Simulation time 49783861 ps
CPU time 0.9 seconds
Started Apr 23 01:11:13 PM PDT 24
Finished Apr 23 01:11:14 PM PDT 24
Peak memory 209180 kb
Host smart-a905ada4-9dfc-48b2-adfd-a16258871863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939229453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1939229453
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.826368924
Short name T249
Test name
Test status
Simulation time 26082564 ps
CPU time 0.89 seconds
Started Apr 23 01:11:08 PM PDT 24
Finished Apr 23 01:11:10 PM PDT 24
Peak memory 209008 kb
Host smart-e1c8f617-d004-4290-9b03-d625f57765db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826368924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.826368924
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4145299552
Short name T297
Test name
Test status
Simulation time 1533477993 ps
CPU time 12.67 seconds
Started Apr 23 01:11:07 PM PDT 24
Finished Apr 23 01:11:20 PM PDT 24
Peak memory 217504 kb
Host smart-2ebe50fd-2ee2-407f-ac83-dabb0ce061c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145299552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4145299552
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4041043436
Short name T466
Test name
Test status
Simulation time 578156138 ps
CPU time 3.59 seconds
Started Apr 23 01:11:11 PM PDT 24
Finished Apr 23 01:11:15 PM PDT 24
Peak memory 216484 kb
Host smart-7eda72f4-bdae-47b8-935c-2452a9c0fdc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041043436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4041043436
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2682907363
Short name T435
Test name
Test status
Simulation time 11215855775 ps
CPU time 42.38 seconds
Started Apr 23 01:11:12 PM PDT 24
Finished Apr 23 01:11:54 PM PDT 24
Peak memory 217536 kb
Host smart-dc3eafda-9ef9-4e89-b34e-61f359947edc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682907363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2682907363
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3408997118
Short name T239
Test name
Test status
Simulation time 1191724442 ps
CPU time 3.63 seconds
Started Apr 23 01:11:17 PM PDT 24
Finished Apr 23 01:11:21 PM PDT 24
Peak memory 216588 kb
Host smart-655959cc-ded8-4119-b56b-a83a506acfb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408997118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
408997118
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2048560999
Short name T717
Test name
Test status
Simulation time 1451680109 ps
CPU time 8.83 seconds
Started Apr 23 01:11:12 PM PDT 24
Finished Apr 23 01:11:21 PM PDT 24
Peak memory 217584 kb
Host smart-e5c91a38-8aa3-4cfc-ac7c-19ac2e6d50ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048560999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2048560999
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.537074571
Short name T23
Test name
Test status
Simulation time 6988022201 ps
CPU time 22.72 seconds
Started Apr 23 01:11:17 PM PDT 24
Finished Apr 23 01:11:40 PM PDT 24
Peak memory 213524 kb
Host smart-6670915c-0e92-4913-bdd8-477539e5e7b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537074571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.537074571
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3094829743
Short name T800
Test name
Test status
Simulation time 120760642 ps
CPU time 3.85 seconds
Started Apr 23 01:11:09 PM PDT 24
Finished Apr 23 01:11:13 PM PDT 24
Peak memory 212732 kb
Host smart-64ae6b25-e278-4810-8ba0-63a699c99ff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094829743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3094829743
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.705884120
Short name T464
Test name
Test status
Simulation time 2772980799 ps
CPU time 35.86 seconds
Started Apr 23 01:11:07 PM PDT 24
Finished Apr 23 01:11:43 PM PDT 24
Peak memory 275192 kb
Host smart-85f31d99-e9bb-4980-97b1-7a06f21ce3b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705884120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.705884120
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2775379480
Short name T774
Test name
Test status
Simulation time 8286300256 ps
CPU time 19.3 seconds
Started Apr 23 01:11:20 PM PDT 24
Finished Apr 23 01:11:40 PM PDT 24
Peak memory 242524 kb
Host smart-c187530d-f83b-4032-90bc-946bb69a6581
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775379480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2775379480
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2859129378
Short name T446
Test name
Test status
Simulation time 35416203 ps
CPU time 2.04 seconds
Started Apr 23 01:11:14 PM PDT 24
Finished Apr 23 01:11:16 PM PDT 24
Peak memory 217660 kb
Host smart-dc6f2e93-c89b-46a6-8c68-f68ac8030fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859129378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2859129378
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2851430148
Short name T438
Test name
Test status
Simulation time 722841489 ps
CPU time 11.37 seconds
Started Apr 23 01:11:07 PM PDT 24
Finished Apr 23 01:11:19 PM PDT 24
Peak memory 213808 kb
Host smart-968a3a4c-3194-4717-8df1-58ae166f283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851430148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2851430148
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2981860575
Short name T252
Test name
Test status
Simulation time 708723011 ps
CPU time 14.16 seconds
Started Apr 23 01:11:17 PM PDT 24
Finished Apr 23 01:11:31 PM PDT 24
Peak memory 217676 kb
Host smart-22fa9457-c0e9-4149-875e-1c7009e20311
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981860575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2981860575
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2239109361
Short name T430
Test name
Test status
Simulation time 213275054 ps
CPU time 9.06 seconds
Started Apr 23 01:11:13 PM PDT 24
Finished Apr 23 01:11:22 PM PDT 24
Peak memory 217544 kb
Host smart-be1dae36-b6bd-4f02-a080-bf7c992894ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239109361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2239109361
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3826520702
Short name T580
Test name
Test status
Simulation time 1067711003 ps
CPU time 8.7 seconds
Started Apr 23 01:11:10 PM PDT 24
Finished Apr 23 01:11:19 PM PDT 24
Peak memory 217576 kb
Host smart-e275f1fd-0b4f-4291-8a33-fbb20703eddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826520702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
826520702
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2998904759
Short name T752
Test name
Test status
Simulation time 256462151 ps
CPU time 11.17 seconds
Started Apr 23 01:11:18 PM PDT 24
Finished Apr 23 01:11:30 PM PDT 24
Peak memory 217564 kb
Host smart-b0484a8f-2f48-4519-a38d-20727b85fc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998904759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2998904759
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3889421433
Short name T76
Test name
Test status
Simulation time 62257374 ps
CPU time 1.47 seconds
Started Apr 23 01:11:09 PM PDT 24
Finished Apr 23 01:11:11 PM PDT 24
Peak memory 217332 kb
Host smart-7ad815e9-a395-4030-aaf1-976dc02b31cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889421433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3889421433
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2144870913
Short name T367
Test name
Test status
Simulation time 1938123264 ps
CPU time 20.1 seconds
Started Apr 23 01:11:07 PM PDT 24
Finished Apr 23 01:11:28 PM PDT 24
Peak memory 250524 kb
Host smart-37d7f5c4-5eae-40a1-9ab5-88740603dfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144870913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2144870913
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1443281542
Short name T830
Test name
Test status
Simulation time 245407906 ps
CPU time 7.84 seconds
Started Apr 23 01:11:08 PM PDT 24
Finished Apr 23 01:11:16 PM PDT 24
Peak memory 250580 kb
Host smart-ecd364c3-046a-486c-a5a9-19dd870f39d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443281542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1443281542
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3792554873
Short name T656
Test name
Test status
Simulation time 69976719444 ps
CPU time 285.15 seconds
Started Apr 23 01:11:12 PM PDT 24
Finished Apr 23 01:15:58 PM PDT 24
Peak memory 332556 kb
Host smart-6de1a2c8-9e80-45b1-a014-1dad76156c8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792554873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3792554873
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.941775170
Short name T863
Test name
Test status
Simulation time 19503859060 ps
CPU time 416.91 seconds
Started Apr 23 01:11:10 PM PDT 24
Finished Apr 23 01:18:08 PM PDT 24
Peak memory 438172 kb
Host smart-26305208-b273-40a4-8a03-18523bd88cf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=941775170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.941775170
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1609917039
Short name T42
Test name
Test status
Simulation time 32079087 ps
CPU time 0.87 seconds
Started Apr 23 01:11:09 PM PDT 24
Finished Apr 23 01:11:11 PM PDT 24
Peak memory 208184 kb
Host smart-54f16167-62e5-44d2-acc1-2c8205083734
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609917039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1609917039
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3307654630
Short name T164
Test name
Test status
Simulation time 12329151 ps
CPU time 0.93 seconds
Started Apr 23 01:11:21 PM PDT 24
Finished Apr 23 01:11:23 PM PDT 24
Peak memory 209152 kb
Host smart-4f04d68b-30e6-4166-ac8d-e863c46d2b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307654630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3307654630
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2508614769
Short name T199
Test name
Test status
Simulation time 14657990 ps
CPU time 0.87 seconds
Started Apr 23 01:11:16 PM PDT 24
Finished Apr 23 01:11:18 PM PDT 24
Peak memory 208960 kb
Host smart-58542e0c-26e2-4553-992f-5cf109ec42ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508614769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2508614769
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1665553854
Short name T724
Test name
Test status
Simulation time 1698510157 ps
CPU time 14.8 seconds
Started Apr 23 01:11:16 PM PDT 24
Finished Apr 23 01:11:31 PM PDT 24
Peak memory 217512 kb
Host smart-a147a3c9-90e0-48b6-a8c3-a88b50a91b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665553854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1665553854
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.588649568
Short name T705
Test name
Test status
Simulation time 857932351 ps
CPU time 9.17 seconds
Started Apr 23 01:11:18 PM PDT 24
Finished Apr 23 01:11:28 PM PDT 24
Peak memory 209056 kb
Host smart-9e054794-6960-4fcc-a862-fa34a65648f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588649568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.588649568
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.113559664
Short name T5
Test name
Test status
Simulation time 4374841142 ps
CPU time 35.43 seconds
Started Apr 23 01:11:18 PM PDT 24
Finished Apr 23 01:11:55 PM PDT 24
Peak memory 218516 kb
Host smart-4ee0178e-f71b-42d3-8fdf-e37e61d20014
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113559664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.113559664
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.311884890
Short name T94
Test name
Test status
Simulation time 198289968 ps
CPU time 6.01 seconds
Started Apr 23 01:11:28 PM PDT 24
Finished Apr 23 01:11:35 PM PDT 24
Peak memory 217424 kb
Host smart-15171e5c-d15b-492d-a7b2-1f3f8b5d72bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311884890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.311884890
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.212925158
Short name T240
Test name
Test status
Simulation time 2357273813 ps
CPU time 9.74 seconds
Started Apr 23 01:11:16 PM PDT 24
Finished Apr 23 01:11:26 PM PDT 24
Peak memory 217560 kb
Host smart-1debcf49-7ee5-42b8-bc98-7b11dd4ced35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212925158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.212925158
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.975309896
Short name T655
Test name
Test status
Simulation time 1046803710 ps
CPU time 22.02 seconds
Started Apr 23 01:11:27 PM PDT 24
Finished Apr 23 01:11:50 PM PDT 24
Peak memory 212964 kb
Host smart-20a794f6-3d72-4d92-9164-5c6c253605a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975309896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.975309896
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1950310029
Short name T591
Test name
Test status
Simulation time 344300624 ps
CPU time 4.16 seconds
Started Apr 23 01:11:14 PM PDT 24
Finished Apr 23 01:11:19 PM PDT 24
Peak memory 212760 kb
Host smart-237ea5e6-090f-4cc7-9d18-b493d7fe2554
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950310029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1950310029
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3575308012
Short name T811
Test name
Test status
Simulation time 1653665737 ps
CPU time 59.12 seconds
Started Apr 23 01:11:18 PM PDT 24
Finished Apr 23 01:12:17 PM PDT 24
Peak memory 275568 kb
Host smart-86048ef8-2841-4622-ae06-f3129bc356ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575308012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3575308012
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3691355146
Short name T340
Test name
Test status
Simulation time 420422123 ps
CPU time 13.4 seconds
Started Apr 23 01:11:17 PM PDT 24
Finished Apr 23 01:11:31 PM PDT 24
Peak memory 250512 kb
Host smart-009025ac-80c7-40ab-894d-978bdc09764b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691355146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3691355146
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4199523286
Short name T557
Test name
Test status
Simulation time 19508498 ps
CPU time 1.49 seconds
Started Apr 23 01:11:15 PM PDT 24
Finished Apr 23 01:11:17 PM PDT 24
Peak memory 217544 kb
Host smart-daaf79d5-d99d-43e4-982e-6eb14906d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199523286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4199523286
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2234202204
Short name T407
Test name
Test status
Simulation time 1277007435 ps
CPU time 8.26 seconds
Started Apr 23 01:11:16 PM PDT 24
Finished Apr 23 01:11:25 PM PDT 24
Peak memory 217532 kb
Host smart-bd411de2-3a26-4bb7-94d8-b054e1ec95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234202204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2234202204
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2875288567
Short name T326
Test name
Test status
Simulation time 870554756 ps
CPU time 12.17 seconds
Started Apr 23 01:11:20 PM PDT 24
Finished Apr 23 01:11:33 PM PDT 24
Peak memory 225260 kb
Host smart-7073c61d-0a67-443b-8dc7-d0fa51e9902e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875288567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2875288567
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3083398169
Short name T756
Test name
Test status
Simulation time 1542190981 ps
CPU time 14.56 seconds
Started Apr 23 01:11:21 PM PDT 24
Finished Apr 23 01:11:36 PM PDT 24
Peak memory 217460 kb
Host smart-427b0e16-6d02-41ee-8cd3-5fcb74598341
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083398169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3083398169
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1840669269
Short name T579
Test name
Test status
Simulation time 206886144 ps
CPU time 7.21 seconds
Started Apr 23 01:11:20 PM PDT 24
Finished Apr 23 01:11:28 PM PDT 24
Peak memory 217568 kb
Host smart-399599b1-9fce-4030-9805-7e97422f8ce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840669269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
840669269
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1407614668
Short name T57
Test name
Test status
Simulation time 442696657 ps
CPU time 8.82 seconds
Started Apr 23 01:11:16 PM PDT 24
Finished Apr 23 01:11:25 PM PDT 24
Peak memory 217636 kb
Host smart-e72afb1c-193c-4e5c-aea6-0d086c865bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407614668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1407614668
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3102189525
Short name T245
Test name
Test status
Simulation time 27195326 ps
CPU time 1.58 seconds
Started Apr 23 01:11:10 PM PDT 24
Finished Apr 23 01:11:12 PM PDT 24
Peak memory 213236 kb
Host smart-81e0e2e8-81aa-4607-864a-b106d5d430b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102189525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3102189525
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.85353196
Short name T337
Test name
Test status
Simulation time 153146826 ps
CPU time 24.27 seconds
Started Apr 23 01:11:15 PM PDT 24
Finished Apr 23 01:11:40 PM PDT 24
Peak memory 246116 kb
Host smart-fa33bc26-93f4-43d5-b052-8adb1e41b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85353196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.85353196
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.97351500
Short name T54
Test name
Test status
Simulation time 55268557 ps
CPU time 7.09 seconds
Started Apr 23 01:11:15 PM PDT 24
Finished Apr 23 01:11:23 PM PDT 24
Peak memory 250564 kb
Host smart-6694054e-e5c6-496e-b4fc-15156739c9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97351500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.97351500
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.298165892
Short name T390
Test name
Test status
Simulation time 16310966937 ps
CPU time 121.94 seconds
Started Apr 23 01:11:20 PM PDT 24
Finished Apr 23 01:13:23 PM PDT 24
Peak memory 250688 kb
Host smart-0fcf1e7d-f14e-473a-b3c5-dfe17a116b7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298165892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.298165892
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3332299392
Short name T153
Test name
Test status
Simulation time 199314016447 ps
CPU time 629.05 seconds
Started Apr 23 01:11:19 PM PDT 24
Finished Apr 23 01:21:49 PM PDT 24
Peak memory 300000 kb
Host smart-8c2b7d77-afce-4e95-ba31-12922fb17d36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3332299392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3332299392
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3616658211
Short name T413
Test name
Test status
Simulation time 11802895 ps
CPU time 0.85 seconds
Started Apr 23 01:11:15 PM PDT 24
Finished Apr 23 01:11:17 PM PDT 24
Peak memory 208184 kb
Host smart-327cf4f9-5f0a-4954-b415-d323d434b4ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616658211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3616658211
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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