Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54049 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
1714 |
1 |
|
|
T12 |
7 |
|
T13 |
8 |
|
T14 |
26 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54996 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
767 |
1 |
|
|
T40 |
21 |
|
T41 |
19 |
|
T57 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53604 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2159 |
1 |
|
|
T13 |
33 |
|
T14 |
13 |
|
T15 |
2 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53676 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2087 |
1 |
|
|
T13 |
36 |
|
T14 |
17 |
|
T15 |
2 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53708 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2055 |
1 |
|
|
T13 |
27 |
|
T14 |
13 |
|
T46 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50723 |
1 |
|
|
T3 |
61 |
|
T4 |
14 |
|
T7 |
84 |
no_err_inj |
5040 |
1 |
|
|
T1 |
9 |
|
T9 |
20 |
|
T12 |
14 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53915 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
1848 |
1 |
|
|
T12 |
7 |
|
T13 |
16 |
|
T14 |
19 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54956 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
807 |
1 |
|
|
T40 |
21 |
|
T41 |
17 |
|
T57 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38731 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[1] |
17032 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53702 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2061 |
1 |
|
|
T13 |
23 |
|
T14 |
15 |
|
T46 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53695 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2068 |
1 |
|
|
T13 |
29 |
|
T14 |
18 |
|
T34 |
10 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53699 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2064 |
1 |
|
|
T13 |
30 |
|
T14 |
19 |
|
T34 |
6 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53937 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
1826 |
1 |
|
|
T12 |
12 |
|
T13 |
14 |
|
T14 |
16 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53384 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T7 |
84 |
auto[1] |
2379 |
1 |
|
|
T4 |
14 |
|
T10 |
3 |
|
T13 |
18 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55010 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
753 |
1 |
|
|
T40 |
18 |
|
T41 |
15 |
|
T57 |
16 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54946 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
817 |
1 |
|
|
T40 |
18 |
|
T41 |
17 |
|
T57 |
11 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54955 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
808 |
1 |
|
|
T40 |
20 |
|
T41 |
16 |
|
T57 |
9 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52829 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2934 |
1 |
|
|
T13 |
52 |
|
T46 |
10 |
|
T15 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51930 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
3833 |
1 |
|
|
T35 |
85 |
|
T47 |
99 |
|
T49 |
61 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53664 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2099 |
1 |
|
|
T13 |
28 |
|
T14 |
12 |
|
T46 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53700 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2063 |
1 |
|
|
T13 |
16 |
|
T14 |
15 |
|
T15 |
3 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53698 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
2065 |
1 |
|
|
T13 |
26 |
|
T14 |
15 |
|
T34 |
3 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53951 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
1812 |
1 |
|
|
T12 |
11 |
|
T13 |
13 |
|
T14 |
24 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50278 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
5485 |
1 |
|
|
T11 |
79 |
|
T12 |
12 |
|
T13 |
21 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51983 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
3780 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55763 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53963 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
1800 |
1 |
|
|
T12 |
5 |
|
T13 |
15 |
|
T14 |
22 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53985 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
1778 |
1 |
|
|
T12 |
5 |
|
T13 |
9 |
|
T14 |
19 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53968 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[1] |
1795 |
1 |
|
|
T12 |
6 |
|
T13 |
15 |
|
T14 |
23 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49247 |
1 |
|
|
T3 |
61 |
|
T4 |
14 |
|
T7 |
84 |
auto[0] |
no_err_inj |
3582 |
1 |
|
|
T1 |
9 |
|
T9 |
20 |
|
T12 |
14 |
auto[1] |
err_inj |
1476 |
1 |
|
|
T13 |
25 |
|
T46 |
3 |
|
T15 |
10 |
auto[1] |
no_err_inj |
1458 |
1 |
|
|
T13 |
27 |
|
T46 |
7 |
|
T15 |
4 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50927 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[0] |
auto[1] |
1902 |
1 |
|
|
T13 |
13 |
|
T14 |
15 |
|
T34 |
15 |
auto[1] |
auto[0] |
2773 |
1 |
|
|
T13 |
49 |
|
T46 |
10 |
|
T15 |
11 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T13 |
3 |
|
T15 |
3 |
|
T83 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50912 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[0] |
auto[1] |
1917 |
1 |
|
|
T13 |
27 |
|
T14 |
18 |
|
T34 |
10 |
auto[1] |
auto[0] |
2783 |
1 |
|
|
T13 |
50 |
|
T46 |
10 |
|
T15 |
14 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T13 |
2 |
|
T84 |
2 |
|
T81 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50923 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[0] |
auto[1] |
1906 |
1 |
|
|
T13 |
24 |
|
T14 |
15 |
|
T34 |
3 |
auto[1] |
auto[0] |
2775 |
1 |
|
|
T13 |
50 |
|
T46 |
10 |
|
T15 |
14 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T13 |
2 |
|
T83 |
2 |
|
T84 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50919 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[0] |
auto[1] |
1910 |
1 |
|
|
T13 |
31 |
|
T14 |
17 |
|
T34 |
16 |
auto[1] |
auto[0] |
2757 |
1 |
|
|
T13 |
47 |
|
T46 |
10 |
|
T15 |
12 |
auto[1] |
auto[1] |
177 |
1 |
|
|
T13 |
5 |
|
T15 |
2 |
|
T42 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50927 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[0] |
auto[1] |
1902 |
1 |
|
|
T13 |
26 |
|
T14 |
13 |
|
T34 |
15 |
auto[1] |
auto[0] |
2781 |
1 |
|
|
T13 |
51 |
|
T46 |
9 |
|
T15 |
12 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T13 |
1 |
|
T46 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50866 |
1 |
|
|
T1 |
9 |
|
T3 |
61 |
|
T4 |
14 |
auto[0] |
auto[1] |
1963 |
1 |
|
|
T13 |
30 |
|
T14 |
13 |
|
T34 |
11 |
auto[1] |
auto[0] |
2738 |
1 |
|
|
T13 |
49 |
|
T46 |
10 |
|
T15 |
12 |
auto[1] |
auto[1] |
196 |
1 |
|
|
T13 |
3 |
|
T15 |
2 |
|
T83 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37603 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T13 |
2 |
|
T14 |
26 |
|
T31 |
4 |
auto[1] |
auto[0] |
16446 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
586 |
1 |
|
|
T12 |
7 |
|
T13 |
6 |
|
T30 |
7 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37531 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T13 |
2 |
|
T14 |
19 |
|
T31 |
5 |
auto[1] |
auto[0] |
16384 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
648 |
1 |
|
|
T12 |
7 |
|
T13 |
14 |
|
T30 |
8 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37318 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T10 |
3 |
|
T228 |
2 |
|
T42 |
3 |
auto[1] |
auto[0] |
16066 |
1 |
|
|
T1 |
9 |
|
T9 |
20 |
|
T12 |
76 |
auto[1] |
auto[1] |
966 |
1 |
|
|
T4 |
14 |
|
T13 |
18 |
|
T14 |
14 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37563 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1168 |
1 |
|
|
T13 |
1 |
|
T14 |
16 |
|
T31 |
8 |
auto[1] |
auto[0] |
16374 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
658 |
1 |
|
|
T12 |
12 |
|
T13 |
13 |
|
T30 |
9 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33881 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
4850 |
1 |
|
|
T11 |
79 |
|
T13 |
4 |
|
T14 |
16 |
auto[1] |
auto[0] |
16397 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
635 |
1 |
|
|
T12 |
12 |
|
T13 |
17 |
|
T30 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37631 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1100 |
1 |
|
|
T13 |
5 |
|
T14 |
6 |
|
T34 |
15 |
auto[1] |
auto[0] |
16069 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
963 |
1 |
|
|
T13 |
11 |
|
T14 |
9 |
|
T15 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37628 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1103 |
1 |
|
|
T13 |
10 |
|
T14 |
6 |
|
T46 |
1 |
auto[1] |
auto[0] |
16036 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
996 |
1 |
|
|
T13 |
18 |
|
T14 |
6 |
|
T16 |
10 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37639 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1092 |
1 |
|
|
T13 |
9 |
|
T14 |
7 |
|
T34 |
10 |
auto[1] |
auto[0] |
16056 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
976 |
1 |
|
|
T13 |
20 |
|
T14 |
11 |
|
T16 |
12 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37641 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1090 |
1 |
|
|
T13 |
9 |
|
T14 |
8 |
|
T46 |
1 |
auto[1] |
auto[0] |
16061 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
971 |
1 |
|
|
T13 |
14 |
|
T14 |
7 |
|
T15 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37641 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1090 |
1 |
|
|
T13 |
13 |
|
T14 |
6 |
|
T34 |
16 |
auto[1] |
auto[0] |
16035 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
997 |
1 |
|
|
T13 |
23 |
|
T14 |
11 |
|
T15 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37594 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1137 |
1 |
|
|
T13 |
13 |
|
T14 |
6 |
|
T34 |
11 |
auto[1] |
auto[0] |
16010 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
1022 |
1 |
|
|
T13 |
20 |
|
T14 |
7 |
|
T15 |
2 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37537 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1194 |
1 |
|
|
T13 |
1 |
|
T14 |
23 |
|
T31 |
6 |
auto[1] |
auto[0] |
16431 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
601 |
1 |
|
|
T12 |
6 |
|
T13 |
14 |
|
T30 |
5 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37557 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1174 |
1 |
|
|
T13 |
1 |
|
T14 |
19 |
|
T31 |
5 |
auto[1] |
auto[0] |
16428 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
604 |
1 |
|
|
T12 |
5 |
|
T13 |
8 |
|
T30 |
4 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37114 |
1 |
|
|
T3 |
61 |
|
T7 |
84 |
|
T8 |
80 |
auto[0] |
auto[1] |
1617 |
1 |
|
|
T13 |
26 |
|
T46 |
10 |
|
T84 |
10 |
auto[1] |
auto[0] |
15715 |
1 |
|
|
T1 |
9 |
|
T4 |
14 |
|
T9 |
20 |
auto[1] |
auto[1] |
1317 |
1 |
|
|
T13 |
26 |
|
T15 |
14 |
|
T83 |
15 |