Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110641181

1

T1

120667

T2

72850

T3

22014

auto[1]

1482174

1

T4

785

T10

297

T12

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110638989

1

T1

120667

T2

72850

T3

22014

auto[1]

1484366

1

T4

588

T12

594

T13

10428

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8066465	1			T1	936		T2	114		T3	5500
auto[IdleSt]	22393254	1			T1	14407		T2	72736		T3	2209
auto[ClkMuxSt]	35773	1			T1	9		T3	61		T4	14
auto[CntIncrSt]	35522	1			T1	9		T3	61		T4	14
auto[CntProgSt]	1705209	1			T1	18		T3	2498		T4	622
auto[TransCheckSt]	27664	1			T1	9		T3	61		T7	84
auto[TokenHashSt]	43475301	1			T1	102156		T3	2317		T7	24172
auto[FlashRmaSt]	30186	1			T1	27		T3	40		T7	104
auto[TokenCheck0St]	13136	1			T1	9		T3	23		T7	32
auto[TokenCheck1St]	9752	1			T1	9		T3	5		T7	13
auto[TransProgSt]	438137	1			T1	18		T9	732		T12	1196
auto[PostTransSt]	12808767	1			T1	3060		T3	9239		T4	8910
auto[ScrapSt]	140307	1			T12	630		T13	3473		T35	3
auto[EscalateSt]	7838611	1			T4	7349		T10	412		T12	2745
auto[InvalidSt]	15103131	1			T13	187291		T14	83638		T46	222

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2140	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	15103131	1			T13	187291		T14	83638		T46	222
EscalateSt	7838611	1			T4	7349		T10	412		T12	2745
ScrapSt	140307	1			T12	630		T13	3473		T35	3
PostTransSt	12808767	1			T1	3060		T3	9239		T4	8910
TransProgSt	438137	1			T1	18		T9	732		T12	1196
TokenCheck1St	9752	1			T1	9		T3	5		T7	13
TokenCheck0St	13136	1			T1	9		T3	23		T7	32
FlashRmaSt	30186	1			T1	27		T3	40		T7	104
TokenHashSt	43475301	1			T1	102156		T3	2317		T7	24172
TransCheckSt	27664	1			T1	9		T3	61		T7	84
CntProgSt	1705209	1			T1	18		T3	2498		T4	622
CntIncrSt	35522	1			T1	9		T3	61		T4	14
ClkMuxSt	35773	1			T1	9		T3	61		T4	14
IdleSt	22393254	1			T1	14407		T2	72736		T3	2209
ResetSt	8066465	1			T1	936		T2	114		T3	5500
arcs[ResetSt=>IdleSt]	55878	1			T1	9		T2	1		T3	62
arcs[IdleSt=>ScrapSt]	291	1			T12	2		T13	5		T35	1
arcs[IdleSt=>ClkMuxSt]	35576	1			T1	9		T3	61		T4	14
arcs[ClkMuxSt=>CntIncrSt]	35522	1			T1	9		T3	61		T4	14
arcs[CntIncrSt=>PostTransSt]	1780	1			T12	5		T13	9		T14	19
arcs[CntIncrSt=>CntProgSt]	33681	1			T1	9		T3	61		T4	14
arcs[CntProgSt=>PostTransSt]	4840	1			T4	14		T10	3		T12	7
arcs[CntProgSt=>TransCheckSt]	27664	1			T1	9		T3	61		T7	84
arcs[TransCheckSt=>PostTransSt]	3670	1			T3	30		T7	41		T8	43
arcs[TransCheckSt=>TokenHashSt]	23897	1			T1	9		T3	31		T7	43
arcs[TokenHashSt=>PostTransSt]	10040	1			T3	8		T7	11		T8	8
arcs[TokenHashSt=>FlashRmaSt]	13255	1			T1	9		T3	23		T7	32
arcs[FlashRmaSt=>TokenCheck0St]	13136	1			T1	9		T3	23		T7	32
arcs[TokenCheck0St=>PostTransSt]	3355	1			T3	18		T7	19		T8	20
arcs[TokenCheck0St=>TokenCheck1St]	9752	1			T1	9		T3	5		T7	13
arcs[TokenCheck1St=>PostTransSt]	679	1			T3	5		T7	13		T8	9
arcs[TransProgSt=>PostTransSt]	8112	1			T1	9		T9	20		T12	24
arcs[IdleSt=>EscalateSt]	230	1			T35	5		T47	17		T50	10
arcs[ClkMuxSt=>EscalateSt]	54	1			T35	1		T47	2		T48	3
arcs[CntIncrSt=>EscalateSt]	61	1			T35	2		T47	1		T48	1
arcs[CntProgSt=>EscalateSt]	1177	1			T35	23		T47	28		T49	8
arcs[TransCheckSt=>EscalateSt]	97	1			T35	2		T47	1		T49	8
arcs[TokenHashSt=>EscalateSt]	602	1			T35	16		T47	5		T49	26
arcs[FlashRmaSt=>EscalateSt]	119	1			T35	5		T47	2		T49	3
arcs[TokenCheck0St=>EscalateSt]	29	1			T35	2		T49	1		T50	2
arcs[TokenCheck1St=>EscalateSt]	142	1			T47	3		T49	2		T48	4
arcs[TransProgSt=>EscalateSt]	819	1			T35	17		T47	30		T49	7
arcs[PostTransSt=>EscalateSt]	5050	1			T4	14		T10	3		T12	7
arcs[InvalidSt=>EscalateSt]	15421	1			T13	192		T14	103		T46	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8066291	1			T1	936		T2	114		T3	5500
auto[0]	auto[IdleSt]	22393093	1			T1	14407		T2	72736		T3	2209
auto[0]	auto[ClkMuxSt]	35736	1			T1	9		T3	61		T4	14
auto[0]	auto[CntIncrSt]	35484	1			T1	9		T3	61		T4	14
auto[0]	auto[CntProgSt]	1704451	1			T1	18		T3	2498		T4	622
auto[0]	auto[TransCheckSt]	27605	1			T1	9		T3	61		T7	84
auto[0]	auto[TokenHashSt]	43474893	1			T1	102156		T3	2317		T7	24172
auto[0]	auto[FlashRmaSt]	30106	1			T1	27		T3	40		T7	104
auto[0]	auto[TokenCheck0St]	13120	1			T1	9		T3	23		T7	32
auto[0]	auto[TokenCheck1St]	9648	1			T1	9		T3	5		T7	13
auto[0]	auto[TransProgSt]	437583	1			T1	18		T9	732		T12	1196
auto[0]	auto[PostTransSt]	12806239	1			T1	3060		T3	9239		T4	8902
auto[0]	auto[ScrapSt]	140263	1			T12	630		T13	3473		T35	2
auto[0]	auto[EscalateSt]	6369117	1			T4	6572		T10	118		T12	2647
auto[0]	auto[InvalidSt]	15095412	1			T13	187193		T14	83581		T46	221
auto[1]	auto[ResetSt]	174	1			T35	6		T47	7		T49	2
auto[1]	auto[IdleSt]	161	1			T35	4		T47	11		T50	6
auto[1]	auto[ClkMuxSt]	37	1			T35	1		T47	1		T48	1
auto[1]	auto[CntIncrSt]	38	1			T35	2		T47	1		T50	1
auto[1]	auto[CntProgSt]	758	1			T35	15		T47	22		T49	5
auto[1]	auto[TransCheckSt]	59	1			T35	2		T47	1		T49	5
auto[1]	auto[TokenHashSt]	408	1			T35	11		T47	3		T49	19
auto[1]	auto[FlashRmaSt]	80	1			T35	1		T47	1		T49	1
auto[1]	auto[TokenCheck0St]	16	1			T35	1		T49	1		T50	2
auto[1]	auto[TokenCheck1St]	104	1			T47	3		T49	2		T48	3
auto[1]	auto[TransProgSt]	554	1			T35	12		T47	18		T49	4
auto[1]	auto[PostTransSt]	2528	1			T4	8		T10	3		T12	1
auto[1]	auto[ScrapSt]	44	1			T35	1		T47	2		T49	1
auto[1]	auto[EscalateSt]	1469494	1			T4	777		T10	294		T12	98
auto[1]	auto[InvalidSt]	7719	1			T13	98		T14	57		T46	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8066309	1			T1	936		T2	114		T3	5500
auto[0]	auto[IdleSt]	22393110	1			T1	14407		T2	72736		T3	2209
auto[0]	auto[ClkMuxSt]	35741	1			T1	9		T3	61		T4	14
auto[0]	auto[CntIncrSt]	35477	1			T1	9		T3	61		T4	14
auto[0]	auto[CntProgSt]	1704403	1			T1	18		T3	2498		T4	622
auto[0]	auto[TransCheckSt]	27595	1			T1	9		T3	61		T7	84
auto[0]	auto[TokenHashSt]	43474901	1			T1	102156		T3	2317		T7	24172
auto[0]	auto[FlashRmaSt]	30099	1			T1	27		T3	40		T7	104
auto[0]	auto[TokenCheck0St]	13117	1			T1	9		T3	23		T7	32
auto[0]	auto[TokenCheck1St]	9662	1			T1	9		T3	5		T7	13
auto[0]	auto[TransProgSt]	437601	1			T1	18		T9	732		T12	1196
auto[0]	auto[PostTransSt]	12806176	1			T1	3060		T3	9239		T4	8904
auto[0]	auto[ScrapSt]	140269	1			T12	630		T13	3473		T35	3
auto[0]	auto[EscalateSt]	6366960	1			T4	6767		T10	412		T12	2157
auto[0]	auto[InvalidSt]	15095429	1			T13	187197		T14	83592		T46	220
auto[1]	auto[ResetSt]	156	1			T35	4		T47	2		T49	1
auto[1]	auto[IdleSt]	144	1			T35	3		T47	13		T50	7
auto[1]	auto[ClkMuxSt]	32	1			T47	1		T48	3		T226	1
auto[1]	auto[CntIncrSt]	45	1			T35	1		T47	1		T48	1
auto[1]	auto[CntProgSt]	806	1			T35	15		T47	13		T49	6
auto[1]	auto[TransCheckSt]	69	1			T35	1		T49	8		T48	1
auto[1]	auto[TokenHashSt]	400	1			T35	11		T47	4		T49	19
auto[1]	auto[FlashRmaSt]	87	1			T35	4		T47	2		T49	2
auto[1]	auto[TokenCheck0St]	19	1			T35	1		T50	1		T109	1
auto[1]	auto[TokenCheck1St]	90	1			T47	2		T49	1		T48	2
auto[1]	auto[TransProgSt]	536	1			T35	14		T47	23		T49	4
auto[1]	auto[PostTransSt]	2591	1			T4	6		T12	6		T13	12
auto[1]	auto[ScrapSt]	38	1			T48	1		T227	1		T107	1
auto[1]	auto[EscalateSt]	1471651	1			T4	582		T12	588		T13	10322
auto[1]	auto[InvalidSt]	7702	1			T13	94		T14	46		T46	2