Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105670133

1

T1

11339

T2

40564

T3

33595

auto[1]

1483765

1

T2

10118

T12

198

T4

7872

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105681423

1

T1

11339

T2

40417

T3

33595

auto[1]

1472475

1

T2

10265

T12

198

T4

8450

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7702290	1			T1	6242		T2	8173		T3	5601
auto[IdleSt]	20716658	1			T1	2314		T2	6233		T3	4911
auto[ClkMuxSt]	36955	1			T2	66		T3	54		T11	12
auto[CntIncrSt]	36630	1			T2	64		T3	54		T11	12
auto[CntProgSt]	1532156	1			T2	618		T3	4306		T11	2348
auto[TransCheckSt]	28538	1			T2	36		T3	54		T11	12
auto[TokenHashSt]	44061709	1			T2	20322		T3	9306		T11	781
auto[FlashRmaSt]	29749	1			T2	35		T11	28		T4	339
auto[TokenCheck0St]	13330	1			T2	22		T11	12		T4	108
auto[TokenCheck1St]	9998	1			T2	22		T11	12		T4	77
auto[TransProgSt]	431668	1			T2	55		T11	2011		T4	3606
auto[PostTransSt]	12775942	1			T2	1		T3	9309		T10	1231
auto[ScrapSt]	153956	1			T1	3		T2	3		T4	82
auto[EscalateSt]	7103043	1			T2	15032		T12	492		T4	74677
auto[InvalidSt]	12519236	1			T1	2770		T4	188691		T13	1604

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2040	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12519236	1			T1	2770		T4	188691		T13	1604
EscalateSt	7103043	1			T2	15032		T12	492		T4	74677
ScrapSt	153956	1			T1	3		T2	3		T4	82
PostTransSt	12775942	1			T2	1		T3	9309		T10	1231
TransProgSt	431668	1			T2	55		T11	2011		T4	3606
TokenCheck1St	9998	1			T2	22		T11	12		T4	77
TokenCheck0St	13330	1			T2	22		T11	12		T4	108
FlashRmaSt	29749	1			T2	35		T11	28		T4	339
TokenHashSt	44061709	1			T2	20322		T3	9306		T11	781
TransCheckSt	28538	1			T2	36		T3	54		T11	12
CntProgSt	1532156	1			T2	618		T3	4306		T11	2348
CntIncrSt	36630	1			T2	64		T3	54		T11	12
ClkMuxSt	36955	1			T2	66		T3	54		T11	12
IdleSt	20716658	1			T1	2314		T2	6233		T3	4911
ResetSt	7702290	1			T1	6242		T2	8173		T3	5601
arcs[ResetSt=>IdleSt]	56445	1			T1	61		T2	75		T3	55
arcs[IdleSt=>ScrapSt]	305	1			T1	2		T2	1		T4	3
arcs[IdleSt=>ClkMuxSt]	36698	1			T2	66		T3	54		T11	12
arcs[ClkMuxSt=>CntIncrSt]	36630	1			T2	64		T3	54		T11	12
arcs[CntIncrSt=>PostTransSt]	1998	1			T4	40		T5	24		T16	12
arcs[CntIncrSt=>CntProgSt]	34575	1			T2	63		T3	54		T11	12
arcs[CntProgSt=>PostTransSt]	4996	1			T12	4		T4	38		T13	9
arcs[CntProgSt=>TransCheckSt]	28538	1			T2	36		T3	54		T11	12
arcs[TransCheckSt=>PostTransSt]	3680	1			T4	38		T5	31		T16	10
arcs[TransCheckSt=>TokenHashSt]	24702	1			T2	36		T3	54		T11	12
arcs[TokenHashSt=>PostTransSt]	10566	1			T3	54		T4	122		T13	8
arcs[TokenHashSt=>FlashRmaSt]	13430	1			T2	23		T11	12		T4	108
arcs[FlashRmaSt=>TokenCheck0St]	13330	1			T2	22		T11	12		T4	108
arcs[TokenCheck0St=>PostTransSt]	3296	1			T4	31		T13	14		T5	23
arcs[TokenCheck0St=>TokenCheck1St]	9998	1			T2	22		T11	12		T4	77
arcs[TokenCheck1St=>PostTransSt]	662	1			T4	4		T5	2		T32	1
arcs[TransProgSt=>PostTransSt]	8412	1			T2	1		T11	12		T4	73
arcs[IdleSt=>EscalateSt]	208	1			T2	7		T51	5		T53	13
arcs[ClkMuxSt=>EscalateSt]	68	1			T2	2		T51	1		T52	6
arcs[CntIncrSt=>EscalateSt]	57	1			T2	1		T53	2		T54	1
arcs[CntProgSt=>EscalateSt]	1041	1			T2	27		T51	15		T53	31
arcs[TransCheckSt=>EscalateSt]	156	1			T51	1		T53	1		T52	9
arcs[TokenHashSt=>EscalateSt]	706	1			T2	13		T51	7		T53	6
arcs[FlashRmaSt=>EscalateSt]	100	1			T2	1		T53	1		T54	2
arcs[TokenCheck0St=>EscalateSt]	36	1			T51	1		T53	1		T52	3
arcs[TokenCheck1St=>EscalateSt]	146	1			T2	4		T51	2		T53	3
arcs[TransProgSt=>EscalateSt]	778	1			T2	17		T51	12		T53	25
arcs[PostTransSt=>EscalateSt]	5264	1			T2	1		T12	4		T4	38
arcs[InvalidSt=>EscalateSt]	15015	1			T4	128		T13	8		T14	54

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7702100	1			T1	6242		T2	8170		T3	5601
auto[0]	auto[IdleSt]	20716509	1			T1	2314		T2	6228		T3	4911
auto[0]	auto[ClkMuxSt]	36910	1			T2	65		T3	54		T11	12
auto[0]	auto[CntIncrSt]	36590	1			T2	63		T3	54		T11	12
auto[0]	auto[CntProgSt]	1531462	1			T2	601		T3	4306		T11	2348
auto[0]	auto[TransCheckSt]	28430	1			T2	36		T3	54		T11	12
auto[0]	auto[TokenHashSt]	44061249	1			T2	20315		T3	9306		T11	781
auto[0]	auto[FlashRmaSt]	29678	1			T2	35		T11	28		T4	339
auto[0]	auto[TokenCheck0St]	13302	1			T2	22		T11	12		T4	108
auto[0]	auto[TokenCheck1St]	9895	1			T2	19		T11	12		T4	77
auto[0]	auto[TransProgSt]	431128	1			T2	42		T11	2011		T4	3606
auto[0]	auto[PostTransSt]	12773273	1			T3	9309		T10	1231		T11	1019
auto[0]	auto[ScrapSt]	153909	1			T1	3		T2	3		T4	82
auto[0]	auto[EscalateSt]	5631926	1			T2	4965		T12	296		T4	66885
auto[0]	auto[InvalidSt]	12511732	1			T1	2770		T4	188635		T13	1596
auto[1]	auto[ResetSt]	190	1			T2	3		T51	5		T53	6
auto[1]	auto[IdleSt]	149	1			T2	5		T51	3		T53	10
auto[1]	auto[ClkMuxSt]	45	1			T2	1		T51	1		T52	4
auto[1]	auto[CntIncrSt]	40	1			T2	1		T53	1		T226	2
auto[1]	auto[CntProgSt]	694	1			T2	17		T51	9		T53	17
auto[1]	auto[TransCheckSt]	108	1			T51	1		T53	1		T52	7
auto[1]	auto[TokenHashSt]	460	1			T2	7		T51	2		T53	4
auto[1]	auto[FlashRmaSt]	71	1			T53	1		T54	2		T52	3
auto[1]	auto[TokenCheck0St]	28	1			T51	1		T53	1		T52	3
auto[1]	auto[TokenCheck1St]	103	1			T2	3		T51	1		T53	3
auto[1]	auto[TransProgSt]	540	1			T2	13		T51	7		T53	19
auto[1]	auto[PostTransSt]	2669	1			T2	1		T12	2		T4	24
auto[1]	auto[ScrapSt]	47	1			T51	1		T53	2		T52	2
auto[1]	auto[EscalateSt]	1471117	1			T2	10067		T12	196		T4	7792
auto[1]	auto[InvalidSt]	7504	1			T4	56		T13	8		T14	27

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7702113	1			T1	6242		T2	8172		T3	5601
auto[0]	auto[IdleSt]	20716519	1			T1	2314		T2	6228		T3	4911
auto[0]	auto[ClkMuxSt]	36907	1			T2	65		T3	54		T11	12
auto[0]	auto[CntIncrSt]	36593	1			T2	64		T3	54		T11	12
auto[0]	auto[CntProgSt]	1531467	1			T2	598		T3	4306		T11	2348
auto[0]	auto[TransCheckSt]	28433	1			T2	36		T3	54		T11	12
auto[0]	auto[TokenHashSt]	44061232	1			T2	20311		T3	9306		T11	781
auto[0]	auto[FlashRmaSt]	29688	1			T2	34		T11	28		T4	339
auto[0]	auto[TokenCheck0St]	13307	1			T2	22		T11	12		T4	108
auto[0]	auto[TokenCheck1St]	9906	1			T2	19		T11	12		T4	77
auto[0]	auto[TransProgSt]	431159	1			T2	43		T11	2011		T4	3606
auto[0]	auto[PostTransSt]	12773255	1			T2	1		T3	9309		T10	1231
auto[0]	auto[ScrapSt]	153918	1			T1	3		T2	2		T4	82
auto[0]	auto[EscalateSt]	5643161	1			T2	4822		T12	296		T4	66313
auto[0]	auto[InvalidSt]	12511725	1			T1	2770		T4	188619		T13	1604
auto[1]	auto[ResetSt]	177	1			T2	1		T51	5		T53	4
auto[1]	auto[IdleSt]	139	1			T2	5		T51	3		T53	9
auto[1]	auto[ClkMuxSt]	48	1			T2	1		T52	3		T227	1
auto[1]	auto[CntIncrSt]	37	1			T53	2		T54	1		T228	1
auto[1]	auto[CntProgSt]	689	1			T2	20		T51	9		T53	24
auto[1]	auto[TransCheckSt]	105	1			T51	1		T52	6		T229	4
auto[1]	auto[TokenHashSt]	477	1			T2	11		T51	6		T53	6
auto[1]	auto[FlashRmaSt]	61	1			T2	1		T52	3		T227	1
auto[1]	auto[TokenCheck0St]	23	1			T53	1		T227	1		T226	2
auto[1]	auto[TokenCheck1St]	92	1			T2	3		T51	2		T53	2
auto[1]	auto[TransProgSt]	509	1			T2	12		T51	9		T53	17
auto[1]	auto[PostTransSt]	2687	1			T12	2		T4	14		T13	5
auto[1]	auto[ScrapSt]	38	1			T2	1		T51	2		T53	1
auto[1]	auto[EscalateSt]	1459882	1			T2	10210		T12	196		T4	8364
auto[1]	auto[InvalidSt]	7511	1			T4	72		T14	27		T5	108