Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100715967

1

T1

16028

T2

272278

T3

3384

auto[1]

1378028

1

T1

392

T2

8910

T3

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100694292

1

T1

16224

T2

272773

T3

2988

auto[1]

1399703

1

T1

196

T2

8415

T3

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7357639	1			T1	676		T2	30449		T3	756
auto[IdleSt]	20176414	1			T1	9699		T2	21097		T3	1203
auto[ClkMuxSt]	34818	1			T1	6		T2	99		T3	8
auto[CntIncrSt]	34582	1			T1	6		T2	99		T3	8
auto[CntProgSt]	1521098	1			T1	182		T2	173		T3	16
auto[TransCheckSt]	26672	1			T2	63		T8	1		T10	51
auto[TokenHashSt]	43871989	1			T2	156832		T8	133		T10	1180
auto[FlashRmaSt]	28460	1			T2	112		T8	24		T12	112
auto[TokenCheck0St]	12391	1			T2	39		T8	1		T12	77
auto[TokenCheck1St]	9127	1			T2	27		T8	1		T12	44
auto[TransProgSt]	339987	1			T2	54		T8	6		T12	2039
auto[PostTransSt]	12025191	1			T1	3142		T2	16569		T3	499
auto[ScrapSt]	217160	1			T2	2249		T12	30		T28	3
auto[EscalateSt]	6364690	1			T1	2709		T2	26422		T3	1092
auto[InvalidSt]	10071824	1			T2	26880		T9	4045		T12	32541

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1953	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10071824	1			T2	26880		T9	4045		T12	32541
EscalateSt	6364690	1			T1	2709		T2	26422		T3	1092
ScrapSt	217160	1			T2	2249		T12	30		T28	3
PostTransSt	12025191	1			T1	3142		T2	16569		T3	499
TransProgSt	339987	1			T2	54		T8	6		T12	2039
TokenCheck1St	9127	1			T2	27		T8	1		T12	44
TokenCheck0St	12391	1			T2	39		T8	1		T12	77
FlashRmaSt	28460	1			T2	112		T8	24		T12	112
TokenHashSt	43871989	1			T2	156832		T8	133		T10	1180
TransCheckSt	26672	1			T2	63		T8	1		T10	51
CntProgSt	1521098	1			T1	182		T2	173		T3	16
CntIncrSt	34582	1			T1	6		T2	99		T3	8
ClkMuxSt	34818	1			T1	6		T2	99		T3	8
IdleSt	20176414	1			T1	9699		T2	21097		T3	1203
ResetSt	7357639	1			T1	676		T2	30449		T3	756
arcs[ResetSt=>IdleSt]	53265	1			T1	7		T2	281		T3	9
arcs[IdleSt=>ScrapSt]	290	1			T2	2		T12	1		T28	1
arcs[IdleSt=>ClkMuxSt]	34642	1			T1	6		T2	99		T3	8
arcs[ClkMuxSt=>CntIncrSt]	34582	1			T1	6		T2	99		T3	8
arcs[CntIncrSt=>PostTransSt]	1729	1			T2	8		T12	33		T13	8
arcs[CntIncrSt=>CntProgSt]	32799	1			T1	6		T2	91		T3	8
arcs[CntProgSt=>PostTransSt]	5030	1			T1	6		T2	28		T3	8
arcs[CntProgSt=>TransCheckSt]	26672	1			T2	63		T8	1		T10	51
arcs[TransCheckSt=>PostTransSt]	3624	1			T2	10		T12	30		T13	7
arcs[TransCheckSt=>TokenHashSt]	22931	1			T2	53		T8	1		T10	51
arcs[TokenHashSt=>PostTransSt]	9788	1			T2	14		T10	51		T12	70
arcs[TokenHashSt=>FlashRmaSt]	12488	1			T2	39		T8	1		T12	77
arcs[FlashRmaSt=>TokenCheck0St]	12391	1			T2	39		T8	1		T12	77
arcs[TokenCheck0St=>PostTransSt]	3246	1			T2	12		T12	33		T13	7
arcs[TokenCheck0St=>TokenCheck1St]	9127	1			T2	27		T8	1		T12	44
arcs[TokenCheck1St=>PostTransSt]	612	1			T12	2		T13	2		T14	15
arcs[TransProgSt=>PostTransSt]	7715	1			T2	27		T8	1		T12	42
arcs[IdleSt=>EscalateSt]	195	1			T28	6		T44	5		T45	7
arcs[ClkMuxSt=>EscalateSt]	60	1			T44	2		T45	1		T46	4
arcs[CntIncrSt=>EscalateSt]	54	1			T44	1		T45	1		T46	3
arcs[CntProgSt=>EscalateSt]	1097	1			T28	18		T44	15		T45	12
arcs[TransCheckSt=>EscalateSt]	117	1			T28	1		T45	7		T50	1
arcs[TokenHashSt=>EscalateSt]	654	1			T28	8		T44	6		T51	1
arcs[FlashRmaSt=>EscalateSt]	97	1			T28	1		T45	1		T46	1
arcs[TokenCheck0St=>EscalateSt]	18	1			T28	1		T44	1		T50	1
arcs[TokenCheck1St=>EscalateSt]	126	1			T28	2		T44	1		T45	5
arcs[TransProgSt=>EscalateSt]	674	1			T28	16		T44	17		T45	6
arcs[PostTransSt=>EscalateSt]	5261	1			T1	6		T2	28		T3	8
arcs[InvalidSt=>EscalateSt]	13944	1			T2	147		T9	53		T12	180

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7357471	1			T1	676		T2	30449		T3	756
auto[0]	auto[IdleSt]	20176286	1			T1	9699		T2	21097		T3	1203
auto[0]	auto[ClkMuxSt]	34785	1			T1	6		T2	99		T3	8
auto[0]	auto[CntIncrSt]	34548	1			T1	6		T2	99		T3	8
auto[0]	auto[CntProgSt]	1520359	1			T1	182		T2	173		T3	16
auto[0]	auto[TransCheckSt]	26587	1			T2	63		T8	1		T10	51
auto[0]	auto[TokenHashSt]	43871551	1			T2	156832		T8	133		T10	1180
auto[0]	auto[FlashRmaSt]	28398	1			T2	112		T8	24		T12	112
auto[0]	auto[TokenCheck0St]	12380	1			T2	39		T8	1		T12	77
auto[0]	auto[TokenCheck1St]	9043	1			T2	27		T8	1		T12	44
auto[0]	auto[TransProgSt]	339534	1			T2	54		T8	6		T12	2039
auto[0]	auto[PostTransSt]	12022572	1			T1	3138		T2	16550		T3	497
auto[0]	auto[ScrapSt]	217121	1			T2	2249		T12	30		T28	2
auto[0]	auto[EscalateSt]	4998457	1			T1	2321		T2	17602		T3	896
auto[0]	auto[InvalidSt]	10064922	1			T2	26809		T9	4018		T12	32447
auto[1]	auto[ResetSt]	168	1			T28	3		T44	8		T45	2
auto[1]	auto[IdleSt]	128	1			T28	5		T44	3		T45	3
auto[1]	auto[ClkMuxSt]	33	1			T44	1		T45	1		T46	3
auto[1]	auto[CntIncrSt]	34	1			T45	1		T46	2		T88	1
auto[1]	auto[CntProgSt]	739	1			T28	12		T44	9		T45	6
auto[1]	auto[TransCheckSt]	85	1			T45	4		T182	3		T183	1
auto[1]	auto[TokenHashSt]	438	1			T28	4		T44	5		T51	1
auto[1]	auto[FlashRmaSt]	62	1			T45	1		T88	3		T50	1
auto[1]	auto[TokenCheck0St]	11	1			T44	1		T50	1		T184	1
auto[1]	auto[TokenCheck1St]	84	1			T28	1		T44	1		T45	4
auto[1]	auto[TransProgSt]	453	1			T28	10		T44	12		T45	5
auto[1]	auto[PostTransSt]	2619	1			T1	4		T2	19		T3	2
auto[1]	auto[ScrapSt]	39	1			T28	1		T44	1		T88	2
auto[1]	auto[EscalateSt]	1366233	1			T1	388		T2	8820		T3	196
auto[1]	auto[InvalidSt]	6902	1			T2	71		T9	27		T12	94

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7357467	1			T1	676		T2	30449		T3	756
auto[0]	auto[IdleSt]	20176282	1			T1	9699		T2	21097		T3	1203
auto[0]	auto[ClkMuxSt]	34776	1			T1	6		T2	99		T3	8
auto[0]	auto[CntIncrSt]	34555	1			T1	6		T2	99		T3	8
auto[0]	auto[CntProgSt]	1520366	1			T1	182		T2	173		T3	16
auto[0]	auto[TransCheckSt]	26593	1			T2	63		T8	1		T10	51
auto[0]	auto[TokenHashSt]	43871567	1			T2	156832		T8	133		T10	1180
auto[0]	auto[FlashRmaSt]	28393	1			T2	112		T8	24		T12	112
auto[0]	auto[TokenCheck0St]	12381	1			T2	39		T8	1		T12	77
auto[0]	auto[TokenCheck1St]	9038	1			T2	27		T8	1		T12	44
auto[0]	auto[TransProgSt]	339560	1			T2	54		T8	6		T12	2039
auto[0]	auto[PostTransSt]	12022468	1			T1	3140		T2	16560		T3	493
auto[0]	auto[ScrapSt]	217115	1			T2	2249		T12	30		T28	2
auto[0]	auto[EscalateSt]	4976996	1			T1	2515		T2	18092		T3	504
auto[0]	auto[InvalidSt]	10064782	1			T2	26804		T9	4019		T12	32455
auto[1]	auto[ResetSt]	172	1			T28	4		T44	5		T45	1
auto[1]	auto[IdleSt]	132	1			T28	3		T44	3		T45	4
auto[1]	auto[ClkMuxSt]	42	1			T44	1		T45	1		T46	3
auto[1]	auto[CntIncrSt]	27	1			T44	1		T46	1		T88	2
auto[1]	auto[CntProgSt]	732	1			T28	13		T44	9		T45	9
auto[1]	auto[TransCheckSt]	79	1			T28	1		T45	6		T50	1
auto[1]	auto[TokenHashSt]	422	1			T28	7		T44	5		T45	17
auto[1]	auto[FlashRmaSt]	67	1			T28	1		T46	1		T88	3
auto[1]	auto[TokenCheck0St]	10	1			T28	1		T50	1		T185	1
auto[1]	auto[TokenCheck1St]	89	1			T28	2		T44	1		T45	2
auto[1]	auto[TransProgSt]	427	1			T28	8		T44	7		T45	3
auto[1]	auto[PostTransSt]	2723	1			T1	2		T2	9		T3	6
auto[1]	auto[ScrapSt]	45	1			T28	1		T44	1		T46	1
auto[1]	auto[EscalateSt]	1387694	1			T1	194		T2	8330		T3	588
auto[1]	auto[InvalidSt]	7042	1			T2	76		T9	26		T12	86