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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.15 97.89 95.50 93.31 100.00 98.55 98.51 96.29


Total test records in report: 995
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T804 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2575317126 Apr 30 01:37:02 PM PDT 24 Apr 30 01:37:10 PM PDT 24 291786999 ps
T805 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.606223645 Apr 30 01:38:00 PM PDT 24 Apr 30 01:38:01 PM PDT 24 12023367 ps
T806 /workspace/coverage/default/44.lc_ctrl_stress_all.2037962868 Apr 30 01:40:04 PM PDT 24 Apr 30 01:41:28 PM PDT 24 5029789119 ps
T807 /workspace/coverage/default/17.lc_ctrl_alert_test.3242862004 Apr 30 01:38:55 PM PDT 24 Apr 30 01:38:56 PM PDT 24 15499338 ps
T808 /workspace/coverage/default/16.lc_ctrl_jtag_errors.3316449555 Apr 30 01:38:42 PM PDT 24 Apr 30 01:39:12 PM PDT 24 1727702199 ps
T809 /workspace/coverage/default/22.lc_ctrl_stress_all.3680092493 Apr 30 01:38:57 PM PDT 24 Apr 30 01:41:01 PM PDT 24 7090616126 ps
T810 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1412029052 Apr 30 01:40:03 PM PDT 24 Apr 30 01:40:15 PM PDT 24 1204429907 ps
T811 /workspace/coverage/default/6.lc_ctrl_errors.3099575224 Apr 30 01:37:39 PM PDT 24 Apr 30 01:37:52 PM PDT 24 1912057097 ps
T177 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4098855958 Apr 30 01:37:33 PM PDT 24 Apr 30 01:37:34 PM PDT 24 38658979 ps
T812 /workspace/coverage/default/30.lc_ctrl_security_escalation.1400719631 Apr 30 01:39:22 PM PDT 24 Apr 30 01:39:32 PM PDT 24 534910531 ps
T813 /workspace/coverage/default/13.lc_ctrl_smoke.2354376058 Apr 30 01:38:20 PM PDT 24 Apr 30 01:38:22 PM PDT 24 18645468 ps
T814 /workspace/coverage/default/46.lc_ctrl_smoke.2656142082 Apr 30 01:40:02 PM PDT 24 Apr 30 01:40:04 PM PDT 24 91980136 ps
T815 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2373206751 Apr 30 01:37:22 PM PDT 24 Apr 30 01:37:23 PM PDT 24 24831290 ps
T816 /workspace/coverage/default/30.lc_ctrl_state_post_trans.360326642 Apr 30 01:39:16 PM PDT 24 Apr 30 01:39:23 PM PDT 24 87088210 ps
T817 /workspace/coverage/default/4.lc_ctrl_jtag_errors.3512185400 Apr 30 01:37:34 PM PDT 24 Apr 30 01:38:13 PM PDT 24 9559589570 ps
T818 /workspace/coverage/default/24.lc_ctrl_prog_failure.1073709552 Apr 30 01:39:07 PM PDT 24 Apr 30 01:39:09 PM PDT 24 120859582 ps
T819 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2157508611 Apr 30 01:37:51 PM PDT 24 Apr 30 01:38:04 PM PDT 24 589066403 ps
T820 /workspace/coverage/default/16.lc_ctrl_smoke.115451282 Apr 30 01:38:42 PM PDT 24 Apr 30 01:38:44 PM PDT 24 52469930 ps
T821 /workspace/coverage/default/31.lc_ctrl_security_escalation.520402124 Apr 30 01:39:25 PM PDT 24 Apr 30 01:39:32 PM PDT 24 1068221066 ps
T43 /workspace/coverage/default/8.lc_ctrl_jtag_errors.3095966028 Apr 30 01:37:59 PM PDT 24 Apr 30 01:38:44 PM PDT 24 6516933117 ps
T822 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1081536805 Apr 30 01:39:26 PM PDT 24 Apr 30 01:39:38 PM PDT 24 371994916 ps
T823 /workspace/coverage/default/48.lc_ctrl_alert_test.629886351 Apr 30 01:40:11 PM PDT 24 Apr 30 01:40:12 PM PDT 24 45626564 ps
T824 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2357733037 Apr 30 01:37:21 PM PDT 24 Apr 30 01:37:38 PM PDT 24 4153063737 ps
T825 /workspace/coverage/default/22.lc_ctrl_errors.4217916677 Apr 30 01:38:59 PM PDT 24 Apr 30 01:39:12 PM PDT 24 2576366240 ps
T826 /workspace/coverage/default/34.lc_ctrl_prog_failure.6572540 Apr 30 01:39:43 PM PDT 24 Apr 30 01:39:48 PM PDT 24 1713283952 ps
T827 /workspace/coverage/default/44.lc_ctrl_security_escalation.128825825 Apr 30 01:40:06 PM PDT 24 Apr 30 01:40:16 PM PDT 24 279151245 ps
T828 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2352217315 Apr 30 01:37:41 PM PDT 24 Apr 30 01:38:00 PM PDT 24 7169246664 ps
T829 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3135611747 Apr 30 01:39:44 PM PDT 24 Apr 30 01:39:54 PM PDT 24 468937961 ps
T830 /workspace/coverage/default/38.lc_ctrl_sec_mubi.1119408433 Apr 30 01:39:46 PM PDT 24 Apr 30 01:39:59 PM PDT 24 822278864 ps
T831 /workspace/coverage/default/13.lc_ctrl_security_escalation.1736201984 Apr 30 01:38:21 PM PDT 24 Apr 30 01:38:29 PM PDT 24 991087357 ps
T832 /workspace/coverage/default/22.lc_ctrl_state_post_trans.1487916267 Apr 30 01:39:04 PM PDT 24 Apr 30 01:39:10 PM PDT 24 67489218 ps
T833 /workspace/coverage/default/42.lc_ctrl_errors.3389821416 Apr 30 01:39:56 PM PDT 24 Apr 30 01:40:08 PM PDT 24 809368084 ps
T834 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1038994704 Apr 30 01:38:39 PM PDT 24 Apr 30 01:38:43 PM PDT 24 496649595 ps
T835 /workspace/coverage/default/9.lc_ctrl_jtag_priority.3073851084 Apr 30 01:38:06 PM PDT 24 Apr 30 01:38:08 PM PDT 24 306100606 ps
T836 /workspace/coverage/default/4.lc_ctrl_alert_test.1052973901 Apr 30 01:37:39 PM PDT 24 Apr 30 01:37:41 PM PDT 24 15917687 ps
T837 /workspace/coverage/default/42.lc_ctrl_security_escalation.1020149159 Apr 30 01:39:53 PM PDT 24 Apr 30 01:40:01 PM PDT 24 775717930 ps
T838 /workspace/coverage/default/33.lc_ctrl_state_post_trans.3838168243 Apr 30 01:39:29 PM PDT 24 Apr 30 01:39:32 PM PDT 24 351247330 ps
T839 /workspace/coverage/default/47.lc_ctrl_errors.1951276133 Apr 30 01:40:12 PM PDT 24 Apr 30 01:40:21 PM PDT 24 898368541 ps
T840 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.475398409 Apr 30 01:38:31 PM PDT 24 Apr 30 01:39:28 PM PDT 24 6765187692 ps
T841 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1721906918 Apr 30 01:38:56 PM PDT 24 Apr 30 01:38:57 PM PDT 24 14013922 ps
T842 /workspace/coverage/default/24.lc_ctrl_smoke.2152175709 Apr 30 01:39:07 PM PDT 24 Apr 30 01:39:09 PM PDT 24 23572610 ps
T843 /workspace/coverage/default/3.lc_ctrl_security_escalation.3746101097 Apr 30 01:37:23 PM PDT 24 Apr 30 01:37:32 PM PDT 24 732906073 ps
T844 /workspace/coverage/default/0.lc_ctrl_jtag_priority.3745920708 Apr 30 01:37:03 PM PDT 24 Apr 30 01:37:06 PM PDT 24 187577743 ps
T845 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.446853310 Apr 30 01:38:32 PM PDT 24 Apr 30 01:38:49 PM PDT 24 2432461087 ps
T846 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1871471708 Apr 30 01:39:41 PM PDT 24 Apr 30 01:39:42 PM PDT 24 13509950 ps
T847 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3994896479 Apr 30 01:37:32 PM PDT 24 Apr 30 01:37:50 PM PDT 24 834534936 ps
T848 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1485778277 Apr 30 01:38:48 PM PDT 24 Apr 30 01:39:00 PM PDT 24 1440906200 ps
T849 /workspace/coverage/default/39.lc_ctrl_prog_failure.3558153825 Apr 30 01:39:46 PM PDT 24 Apr 30 01:39:51 PM PDT 24 88911165 ps
T850 /workspace/coverage/default/3.lc_ctrl_jtag_errors.2161960449 Apr 30 01:37:26 PM PDT 24 Apr 30 01:38:29 PM PDT 24 4963251076 ps
T851 /workspace/coverage/default/21.lc_ctrl_state_failure.421708360 Apr 30 01:38:58 PM PDT 24 Apr 30 01:39:23 PM PDT 24 250121005 ps
T852 /workspace/coverage/default/42.lc_ctrl_stress_all.3579235038 Apr 30 01:39:56 PM PDT 24 Apr 30 01:41:41 PM PDT 24 5663427063 ps
T853 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3830495048 Apr 30 01:37:09 PM PDT 24 Apr 30 01:37:20 PM PDT 24 1434894253 ps
T854 /workspace/coverage/default/36.lc_ctrl_prog_failure.3689272280 Apr 30 01:39:39 PM PDT 24 Apr 30 01:39:42 PM PDT 24 162726350 ps
T855 /workspace/coverage/default/14.lc_ctrl_prog_failure.2926331498 Apr 30 01:38:31 PM PDT 24 Apr 30 01:38:34 PM PDT 24 452071605 ps
T856 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.734878827 Apr 30 01:39:53 PM PDT 24 Apr 30 01:40:02 PM PDT 24 1834053100 ps
T857 /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1291116874 Apr 30 01:37:58 PM PDT 24 Apr 30 01:50:16 PM PDT 24 27867117481 ps
T858 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2777562730 Apr 30 01:38:15 PM PDT 24 Apr 30 01:39:00 PM PDT 24 1701233424 ps
T859 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.99575927 Apr 30 01:37:24 PM PDT 24 Apr 30 01:37:38 PM PDT 24 1322448008 ps
T860 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1346310913 Apr 30 01:37:02 PM PDT 24 Apr 30 01:37:15 PM PDT 24 1011233474 ps
T861 /workspace/coverage/default/28.lc_ctrl_state_post_trans.1617173058 Apr 30 01:39:09 PM PDT 24 Apr 30 01:39:15 PM PDT 24 251030117 ps
T105 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.686988265 Apr 30 02:13:32 PM PDT 24 Apr 30 02:13:33 PM PDT 24 19824974 ps
T100 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2595142968 Apr 30 02:13:32 PM PDT 24 Apr 30 02:13:34 PM PDT 24 49274908 ps
T106 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3310487462 Apr 30 02:13:21 PM PDT 24 Apr 30 02:13:23 PM PDT 24 121969152 ps
T93 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3048697714 Apr 30 02:14:36 PM PDT 24 Apr 30 02:14:45 PM PDT 24 221366695 ps
T94 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3165677316 Apr 30 02:14:09 PM PDT 24 Apr 30 02:14:13 PM PDT 24 189983418 ps
T170 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2081784710 Apr 30 02:14:01 PM PDT 24 Apr 30 02:14:02 PM PDT 24 53650466 ps
T95 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1937031666 Apr 30 02:14:12 PM PDT 24 Apr 30 02:14:16 PM PDT 24 63562306 ps
T97 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2476056489 Apr 30 02:13:49 PM PDT 24 Apr 30 02:13:51 PM PDT 24 38146213 ps
T96 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2223821230 Apr 30 02:13:58 PM PDT 24 Apr 30 02:14:03 PM PDT 24 333193210 ps
T138 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2176094827 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:51 PM PDT 24 38523130 ps
T98 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.386232800 Apr 30 02:13:49 PM PDT 24 Apr 30 02:13:53 PM PDT 24 318693364 ps
T118 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2238339988 Apr 30 02:13:27 PM PDT 24 Apr 30 02:13:31 PM PDT 24 317340890 ps
T165 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2874806680 Apr 30 02:13:34 PM PDT 24 Apr 30 02:13:36 PM PDT 24 34601453 ps
T163 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2728917778 Apr 30 02:13:47 PM PDT 24 Apr 30 02:13:49 PM PDT 24 164838809 ps
T124 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2268611437 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:51 PM PDT 24 174270996 ps
T862 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3347762783 Apr 30 02:13:45 PM PDT 24 Apr 30 02:13:48 PM PDT 24 351249258 ps
T863 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2141823393 Apr 30 02:13:53 PM PDT 24 Apr 30 02:13:56 PM PDT 24 89664862 ps
T99 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3749567988 Apr 30 02:13:23 PM PDT 24 Apr 30 02:13:25 PM PDT 24 108818284 ps
T175 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3814628544 Apr 30 02:13:15 PM PDT 24 Apr 30 02:13:22 PM PDT 24 3000912177 ps
T139 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1809402193 Apr 30 02:14:20 PM PDT 24 Apr 30 02:14:22 PM PDT 24 119952088 ps
T140 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2505949162 Apr 30 02:14:07 PM PDT 24 Apr 30 02:14:09 PM PDT 24 207383473 ps
T166 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3446457355 Apr 30 02:13:56 PM PDT 24 Apr 30 02:13:58 PM PDT 24 13712382 ps
T125 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.314598806 Apr 30 02:13:25 PM PDT 24 Apr 30 02:13:27 PM PDT 24 255756833 ps
T102 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.235904663 Apr 30 02:13:53 PM PDT 24 Apr 30 02:13:56 PM PDT 24 82710322 ps
T171 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2690394841 Apr 30 02:14:03 PM PDT 24 Apr 30 02:14:05 PM PDT 24 113527351 ps
T864 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2693301629 Apr 30 02:13:45 PM PDT 24 Apr 30 02:13:47 PM PDT 24 85656396 ps
T141 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3154643293 Apr 30 02:13:45 PM PDT 24 Apr 30 02:13:47 PM PDT 24 101256019 ps
T865 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3942541851 Apr 30 02:14:12 PM PDT 24 Apr 30 02:14:14 PM PDT 24 13708838 ps
T153 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1499688898 Apr 30 02:14:09 PM PDT 24 Apr 30 02:14:11 PM PDT 24 54191875 ps
T142 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.79259501 Apr 30 02:13:24 PM PDT 24 Apr 30 02:13:25 PM PDT 24 62517385 ps
T866 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2262649156 Apr 30 02:13:32 PM PDT 24 Apr 30 02:13:39 PM PDT 24 46270554 ps
T154 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1697686127 Apr 30 02:13:50 PM PDT 24 Apr 30 02:13:53 PM PDT 24 342373717 ps
T172 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1534135470 Apr 30 02:14:06 PM PDT 24 Apr 30 02:14:07 PM PDT 24 14595994 ps
T867 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.892795740 Apr 30 02:14:02 PM PDT 24 Apr 30 02:14:06 PM PDT 24 169456417 ps
T173 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2474267341 Apr 30 02:13:54 PM PDT 24 Apr 30 02:13:57 PM PDT 24 46945993 ps
T868 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1838972375 Apr 30 02:14:17 PM PDT 24 Apr 30 02:14:19 PM PDT 24 69241163 ps
T869 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.419637617 Apr 30 02:14:00 PM PDT 24 Apr 30 02:14:09 PM PDT 24 713353871 ps
T117 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3729196273 Apr 30 02:14:04 PM PDT 24 Apr 30 02:14:09 PM PDT 24 90939149 ps
T870 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2168528697 Apr 30 02:13:47 PM PDT 24 Apr 30 02:13:49 PM PDT 24 14131363 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2139156860 Apr 30 02:13:44 PM PDT 24 Apr 30 02:13:46 PM PDT 24 1116341895 ps
T103 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.586625248 Apr 30 02:13:31 PM PDT 24 Apr 30 02:13:37 PM PDT 24 200385631 ps
T872 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.47266020 Apr 30 02:14:02 PM PDT 24 Apr 30 02:14:04 PM PDT 24 167142977 ps
T873 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2236918822 Apr 30 02:13:41 PM PDT 24 Apr 30 02:13:43 PM PDT 24 60750407 ps
T874 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1141541916 Apr 30 02:13:30 PM PDT 24 Apr 30 02:13:33 PM PDT 24 372688242 ps
T875 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2695672081 Apr 30 02:13:28 PM PDT 24 Apr 30 02:13:30 PM PDT 24 58315065 ps
T876 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1589919199 Apr 30 02:14:05 PM PDT 24 Apr 30 02:14:07 PM PDT 24 27806625 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.41585967 Apr 30 02:14:01 PM PDT 24 Apr 30 02:14:03 PM PDT 24 35608671 ps
T878 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3978393079 Apr 30 02:13:51 PM PDT 24 Apr 30 02:14:05 PM PDT 24 548121756 ps
T879 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1618097154 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:59 PM PDT 24 1638488001 ps
T111 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1792591856 Apr 30 02:13:44 PM PDT 24 Apr 30 02:13:47 PM PDT 24 41698631 ps
T116 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1477686878 Apr 30 02:14:09 PM PDT 24 Apr 30 02:14:12 PM PDT 24 49599434 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3919386090 Apr 30 02:13:44 PM PDT 24 Apr 30 02:14:06 PM PDT 24 2017985570 ps
T881 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2289954299 Apr 30 02:13:33 PM PDT 24 Apr 30 02:13:35 PM PDT 24 89730132 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1888423260 Apr 30 02:13:56 PM PDT 24 Apr 30 02:14:07 PM PDT 24 4029464051 ps
T121 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4218929669 Apr 30 02:13:47 PM PDT 24 Apr 30 02:13:51 PM PDT 24 47398861 ps
T167 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2894188088 Apr 30 02:13:16 PM PDT 24 Apr 30 02:13:18 PM PDT 24 22304309 ps
T107 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2255522708 Apr 30 02:13:33 PM PDT 24 Apr 30 02:13:36 PM PDT 24 80105003 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3389018517 Apr 30 02:13:51 PM PDT 24 Apr 30 02:13:58 PM PDT 24 28759365 ps
T884 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.233605892 Apr 30 02:14:19 PM PDT 24 Apr 30 02:14:20 PM PDT 24 15404095 ps
T119 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2652327282 Apr 30 02:14:15 PM PDT 24 Apr 30 02:14:18 PM PDT 24 128597715 ps
T885 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.268762818 Apr 30 02:13:46 PM PDT 24 Apr 30 02:13:53 PM PDT 24 2319819648 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.231634734 Apr 30 02:13:36 PM PDT 24 Apr 30 02:13:37 PM PDT 24 805454713 ps
T108 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.793400827 Apr 30 02:13:37 PM PDT 24 Apr 30 02:13:39 PM PDT 24 159379661 ps
T887 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3081739081 Apr 30 02:14:00 PM PDT 24 Apr 30 02:14:02 PM PDT 24 26001025 ps
T126 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1855070874 Apr 30 02:13:55 PM PDT 24 Apr 30 02:13:58 PM PDT 24 761312163 ps
T168 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.674983979 Apr 30 02:13:39 PM PDT 24 Apr 30 02:13:41 PM PDT 24 80038864 ps
T888 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1377982050 Apr 30 02:14:19 PM PDT 24 Apr 30 02:14:22 PM PDT 24 185220755 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1418239643 Apr 30 02:13:43 PM PDT 24 Apr 30 02:13:48 PM PDT 24 595679522 ps
T890 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.338919646 Apr 30 02:14:02 PM PDT 24 Apr 30 02:14:06 PM PDT 24 505046933 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1985586073 Apr 30 02:13:21 PM PDT 24 Apr 30 02:13:27 PM PDT 24 21327291 ps
T104 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.216139705 Apr 30 02:14:07 PM PDT 24 Apr 30 02:14:11 PM PDT 24 40084368 ps
T122 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1117997763 Apr 30 02:13:28 PM PDT 24 Apr 30 02:13:31 PM PDT 24 861546328 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1199777869 Apr 30 02:13:07 PM PDT 24 Apr 30 02:13:10 PM PDT 24 94398892 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1437803009 Apr 30 02:13:53 PM PDT 24 Apr 30 02:13:55 PM PDT 24 50782792 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.164723885 Apr 30 02:13:49 PM PDT 24 Apr 30 02:13:52 PM PDT 24 766447352 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2978036222 Apr 30 02:13:44 PM PDT 24 Apr 30 02:13:53 PM PDT 24 934934138 ps
T896 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2232024031 Apr 30 02:13:35 PM PDT 24 Apr 30 02:13:43 PM PDT 24 1500051637 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3411975153 Apr 30 02:13:50 PM PDT 24 Apr 30 02:13:54 PM PDT 24 51250440 ps
T898 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1454298995 Apr 30 02:14:09 PM PDT 24 Apr 30 02:14:13 PM PDT 24 81727254 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4049158581 Apr 30 02:13:55 PM PDT 24 Apr 30 02:13:57 PM PDT 24 241397043 ps
T900 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4052667639 Apr 30 02:13:25 PM PDT 24 Apr 30 02:13:32 PM PDT 24 806714777 ps
T901 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3567368034 Apr 30 02:14:19 PM PDT 24 Apr 30 02:14:21 PM PDT 24 141971038 ps
T902 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.945848737 Apr 30 02:14:07 PM PDT 24 Apr 30 02:14:10 PM PDT 24 97531833 ps
T903 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1944445994 Apr 30 02:13:37 PM PDT 24 Apr 30 02:13:39 PM PDT 24 99113209 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1640527295 Apr 30 02:13:46 PM PDT 24 Apr 30 02:13:49 PM PDT 24 299865502 ps
T905 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.728724795 Apr 30 02:14:02 PM PDT 24 Apr 30 02:14:13 PM PDT 24 4987728892 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1194750193 Apr 30 02:13:36 PM PDT 24 Apr 30 02:13:38 PM PDT 24 24057916 ps
T123 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2559654202 Apr 30 02:14:21 PM PDT 24 Apr 30 02:14:24 PM PDT 24 515927568 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2903843268 Apr 30 02:14:03 PM PDT 24 Apr 30 02:14:05 PM PDT 24 21333249 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3119985652 Apr 30 02:13:32 PM PDT 24 Apr 30 02:13:34 PM PDT 24 28486910 ps
T909 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4138151644 Apr 30 02:13:32 PM PDT 24 Apr 30 02:13:53 PM PDT 24 1612838641 ps
T910 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1713871410 Apr 30 02:14:02 PM PDT 24 Apr 30 02:14:03 PM PDT 24 100186962 ps
T911 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1198908092 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:50 PM PDT 24 42713996 ps
T912 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2620690233 Apr 30 02:14:05 PM PDT 24 Apr 30 02:14:07 PM PDT 24 50591285 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3338783512 Apr 30 02:13:41 PM PDT 24 Apr 30 02:13:43 PM PDT 24 18414793 ps
T114 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3170873567 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:52 PM PDT 24 213384977 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.219679553 Apr 30 02:13:55 PM PDT 24 Apr 30 02:13:57 PM PDT 24 38484316 ps
T915 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.899364164 Apr 30 02:13:26 PM PDT 24 Apr 30 02:13:38 PM PDT 24 240302859 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3219360860 Apr 30 02:13:29 PM PDT 24 Apr 30 02:13:38 PM PDT 24 292811146 ps
T917 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1796790327 Apr 30 02:13:15 PM PDT 24 Apr 30 02:13:18 PM PDT 24 91450840 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.137485535 Apr 30 02:13:44 PM PDT 24 Apr 30 02:13:47 PM PDT 24 46627243 ps
T919 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3218704744 Apr 30 02:13:58 PM PDT 24 Apr 30 02:14:01 PM PDT 24 59507624 ps
T920 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3843471704 Apr 30 02:13:50 PM PDT 24 Apr 30 02:13:53 PM PDT 24 91477164 ps
T921 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2104756602 Apr 30 02:14:16 PM PDT 24 Apr 30 02:14:19 PM PDT 24 57073867 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3270972584 Apr 30 02:14:05 PM PDT 24 Apr 30 02:14:09 PM PDT 24 818036390 ps
T112 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.848157088 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:53 PM PDT 24 1735686096 ps
T113 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1591944809 Apr 30 02:13:51 PM PDT 24 Apr 30 02:13:55 PM PDT 24 397870377 ps
T923 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.370602091 Apr 30 02:14:10 PM PDT 24 Apr 30 02:14:13 PM PDT 24 255270007 ps
T924 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3306071153 Apr 30 02:13:53 PM PDT 24 Apr 30 02:13:55 PM PDT 24 16985462 ps
T925 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.513528741 Apr 30 02:14:03 PM PDT 24 Apr 30 02:14:05 PM PDT 24 174126683 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2748750183 Apr 30 02:13:35 PM PDT 24 Apr 30 02:13:38 PM PDT 24 142399522 ps
T927 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1079724019 Apr 30 02:14:16 PM PDT 24 Apr 30 02:14:18 PM PDT 24 17217264 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2929325739 Apr 30 02:14:03 PM PDT 24 Apr 30 02:14:08 PM PDT 24 153662775 ps
T929 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3475675947 Apr 30 02:13:15 PM PDT 24 Apr 30 02:13:18 PM PDT 24 90426759 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.370389259 Apr 30 02:13:39 PM PDT 24 Apr 30 02:13:41 PM PDT 24 28965716 ps
T931 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3699865107 Apr 30 02:13:45 PM PDT 24 Apr 30 02:13:48 PM PDT 24 152416703 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1244676088 Apr 30 02:13:47 PM PDT 24 Apr 30 02:13:51 PM PDT 24 58474398 ps
T933 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3443353501 Apr 30 02:13:36 PM PDT 24 Apr 30 02:13:38 PM PDT 24 23992917 ps
T934 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.524138314 Apr 30 02:14:18 PM PDT 24 Apr 30 02:14:19 PM PDT 24 14897837 ps
T935 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1325962101 Apr 30 02:13:24 PM PDT 24 Apr 30 02:13:26 PM PDT 24 322014730 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3333654226 Apr 30 02:13:37 PM PDT 24 Apr 30 02:13:40 PM PDT 24 83999973 ps
T120 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.235222686 Apr 30 02:14:12 PM PDT 24 Apr 30 02:14:15 PM PDT 24 402470122 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3939701316 Apr 30 02:13:34 PM PDT 24 Apr 30 02:13:35 PM PDT 24 25165404 ps
T938 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3152106735 Apr 30 02:13:56 PM PDT 24 Apr 30 02:13:58 PM PDT 24 37471270 ps
T939 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3200407318 Apr 30 02:13:58 PM PDT 24 Apr 30 02:14:00 PM PDT 24 19787670 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2225542256 Apr 30 02:13:12 PM PDT 24 Apr 30 02:13:14 PM PDT 24 19271702 ps
T169 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4195636629 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:51 PM PDT 24 46894808 ps
T941 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1978966738 Apr 30 02:13:46 PM PDT 24 Apr 30 02:13:51 PM PDT 24 500703438 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3459374168 Apr 30 02:13:50 PM PDT 24 Apr 30 02:13:52 PM PDT 24 37979645 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2848209483 Apr 30 02:13:43 PM PDT 24 Apr 30 02:13:46 PM PDT 24 60987187 ps
T944 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.776194351 Apr 30 02:13:56 PM PDT 24 Apr 30 02:13:58 PM PDT 24 47313944 ps
T109 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1795434971 Apr 30 02:13:54 PM PDT 24 Apr 30 02:13:57 PM PDT 24 56450517 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3140319811 Apr 30 02:13:29 PM PDT 24 Apr 30 02:13:31 PM PDT 24 318537868 ps
T946 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1035582580 Apr 30 02:14:15 PM PDT 24 Apr 30 02:14:16 PM PDT 24 34687212 ps
T947 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3848604447 Apr 30 02:13:41 PM PDT 24 Apr 30 02:13:43 PM PDT 24 454312217 ps
T948 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4060739837 Apr 30 02:13:40 PM PDT 24 Apr 30 02:13:41 PM PDT 24 17034197 ps
T949 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3707901722 Apr 30 02:13:41 PM PDT 24 Apr 30 02:13:42 PM PDT 24 37486398 ps
T950 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1379971423 Apr 30 02:13:38 PM PDT 24 Apr 30 02:13:42 PM PDT 24 115081988 ps
T951 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2951376813 Apr 30 02:14:29 PM PDT 24 Apr 30 02:14:32 PM PDT 24 45241019 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2624318927 Apr 30 02:13:47 PM PDT 24 Apr 30 02:13:49 PM PDT 24 45671753 ps
T953 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.847741589 Apr 30 02:13:28 PM PDT 24 Apr 30 02:13:30 PM PDT 24 118315175 ps
T954 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1080917 Apr 30 02:13:44 PM PDT 24 Apr 30 02:13:46 PM PDT 24 28321396 ps
T110 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3603376174 Apr 30 02:13:43 PM PDT 24 Apr 30 02:13:47 PM PDT 24 270094034 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1803272717 Apr 30 02:13:29 PM PDT 24 Apr 30 02:13:30 PM PDT 24 230098330 ps
T956 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.785885850 Apr 30 02:13:46 PM PDT 24 Apr 30 02:13:58 PM PDT 24 832389309 ps
T957 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2989857482 Apr 30 02:14:10 PM PDT 24 Apr 30 02:14:12 PM PDT 24 133538575 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.605890061 Apr 30 02:14:08 PM PDT 24 Apr 30 02:14:11 PM PDT 24 114710709 ps
T959 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3365451819 Apr 30 02:13:51 PM PDT 24 Apr 30 02:13:53 PM PDT 24 418250963 ps
T960 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.329516331 Apr 30 02:13:56 PM PDT 24 Apr 30 02:13:58 PM PDT 24 28461177 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3053647150 Apr 30 02:13:26 PM PDT 24 Apr 30 02:13:30 PM PDT 24 1495466659 ps
T962 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2507165952 Apr 30 02:13:50 PM PDT 24 Apr 30 02:13:52 PM PDT 24 35843657 ps
T963 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.668876376 Apr 30 02:13:50 PM PDT 24 Apr 30 02:13:54 PM PDT 24 35551994 ps
T964 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2675130721 Apr 30 02:13:58 PM PDT 24 Apr 30 02:14:03 PM PDT 24 126593565 ps
T115 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.801950912 Apr 30 02:14:22 PM PDT 24 Apr 30 02:14:25 PM PDT 24 91730784 ps
T965 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2610797314 Apr 30 02:13:16 PM PDT 24 Apr 30 02:13:22 PM PDT 24 45645967 ps
T966 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4057897853 Apr 30 02:14:09 PM PDT 24 Apr 30 02:14:11 PM PDT 24 415534151 ps
T967 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2687191812 Apr 30 02:14:21 PM PDT 24 Apr 30 02:14:23 PM PDT 24 397421037 ps
T968 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2303003650 Apr 30 02:14:20 PM PDT 24 Apr 30 02:14:22 PM PDT 24 33360265 ps
T969 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.325643402 Apr 30 02:13:29 PM PDT 24 Apr 30 02:13:31 PM PDT 24 145692303 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.237419947 Apr 30 02:13:16 PM PDT 24 Apr 30 02:13:18 PM PDT 24 15979685 ps
T971 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.660325263 Apr 30 02:13:57 PM PDT 24 Apr 30 02:14:00 PM PDT 24 51428116 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3766383038 Apr 30 02:13:49 PM PDT 24 Apr 30 02:13:57 PM PDT 24 579920695 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1262322225 Apr 30 02:13:49 PM PDT 24 Apr 30 02:13:52 PM PDT 24 89745188 ps
T974 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1775337040 Apr 30 02:13:34 PM PDT 24 Apr 30 02:13:38 PM PDT 24 107337925 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1978649379 Apr 30 02:13:44 PM PDT 24 Apr 30 02:13:45 PM PDT 24 47706973 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.223649218 Apr 30 02:13:36 PM PDT 24 Apr 30 02:13:38 PM PDT 24 171860073 ps
T977 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1112284845 Apr 30 02:13:46 PM PDT 24 Apr 30 02:13:48 PM PDT 24 25446152 ps
T978 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.110958618 Apr 30 02:14:07 PM PDT 24 Apr 30 02:14:10 PM PDT 24 49775921 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.380270384 Apr 30 02:13:56 PM PDT 24 Apr 30 02:13:59 PM PDT 24 369586660 ps
T980 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.448595522 Apr 30 02:14:10 PM PDT 24 Apr 30 02:14:13 PM PDT 24 58073774 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1366951553 Apr 30 02:13:43 PM PDT 24 Apr 30 02:13:51 PM PDT 24 9273269067 ps
T982 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.685864510 Apr 30 02:14:01 PM PDT 24 Apr 30 02:14:03 PM PDT 24 111383592 ps
T983 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.327243753 Apr 30 02:14:01 PM PDT 24 Apr 30 02:14:03 PM PDT 24 165024252 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4168928887 Apr 30 02:13:45 PM PDT 24 Apr 30 02:13:48 PM PDT 24 208812382 ps
T985 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2119016924 Apr 30 02:13:48 PM PDT 24 Apr 30 02:13:52 PM PDT 24 884510285 ps
T986 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2578578823 Apr 30 02:13:47 PM PDT 24 Apr 30 02:14:12 PM PDT 24 16775294466 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4003585453 Apr 30 02:13:23 PM PDT 24 Apr 30 02:13:33 PM PDT 24 781889015 ps
T988 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3505280063 Apr 30 02:13:40 PM PDT 24 Apr 30 02:13:42 PM PDT 24 39684251 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3017738542 Apr 30 02:13:46 PM PDT 24 Apr 30 02:13:48 PM PDT 24 84901741 ps
T990 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2259560759 Apr 30 02:13:46 PM PDT 24 Apr 30 02:13:48 PM PDT 24 15093294 ps
T991 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3134903569 Apr 30 02:13:39 PM PDT 24 Apr 30 02:13:40 PM PDT 24 78734998 ps
T992 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.383817575 Apr 30 02:14:00 PM PDT 24 Apr 30 02:14:02 PM PDT 24 108912876 ps
T993 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.576017385 Apr 30 02:14:03 PM PDT 24 Apr 30 02:14:40 PM PDT 24 6284335415 ps
T994 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2415522585 Apr 30 02:14:02 PM PDT 24 Apr 30 02:14:03 PM PDT 24 15081294 ps
T995 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1846100440 Apr 30 02:14:02 PM PDT 24 Apr 30 02:14:05 PM PDT 24 57864866 ps

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3534005378
Short name T2
Test name
Test status
Simulation time 2869265222 ps
CPU time 126.74 seconds
Started Apr 30 01:37:05 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 271292 kb
Host smart-36366b73-2a2d-42e7-bf62-89471e89d2d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534005378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3534005378
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2445600338
Short name T28
Test name
Test status
Simulation time 250815510 ps
CPU time 9.34 seconds
Started Apr 30 01:40:04 PM PDT 24
Finished Apr 30 01:40:15 PM PDT 24
Peak memory 217908 kb
Host smart-437fcb81-775d-47e5-baf5-1e754e06c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445600338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2445600338
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1778888693
Short name T60
Test name
Test status
Simulation time 1752972682 ps
CPU time 15.65 seconds
Started Apr 30 01:39:36 PM PDT 24
Finished Apr 30 01:39:53 PM PDT 24
Peak memory 225864 kb
Host smart-698004d2-a581-4045-84c1-f71ccd066223
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778888693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1778888693
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.135530548
Short name T29
Test name
Test status
Simulation time 9935601374 ps
CPU time 342.7 seconds
Started Apr 30 01:39:23 PM PDT 24
Finished Apr 30 01:45:06 PM PDT 24
Peak memory 283780 kb
Host smart-65df99a9-94cb-434c-86c4-d8a2ce50ccbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=135530548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.135530548
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.386232800
Short name T98
Test name
Test status
Simulation time 318693364 ps
CPU time 2.31 seconds
Started Apr 30 02:13:49 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 217920 kb
Host smart-72162d95-126e-49f5-a590-468de3b945f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386232
800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.386232800
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1146505984
Short name T25
Test name
Test status
Simulation time 14497744 ps
CPU time 0.8 seconds
Started Apr 30 01:39:06 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 208572 kb
Host smart-32200e3d-b192-4195-9242-c396ce9be58a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146505984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1146505984
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3215714246
Short name T44
Test name
Test status
Simulation time 1923564019 ps
CPU time 9.18 seconds
Started Apr 30 01:39:11 PM PDT 24
Finished Apr 30 01:39:20 PM PDT 24
Peak memory 217860 kb
Host smart-d0dba996-e4e4-4a3d-9645-1e41b9454ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215714246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3215714246
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2903003734
Short name T47
Test name
Test status
Simulation time 947103549 ps
CPU time 35.12 seconds
Started Apr 30 01:37:15 PM PDT 24
Finished Apr 30 01:37:51 PM PDT 24
Peak memory 269548 kb
Host smart-5f6ec19a-4be2-496f-955d-87cc3811842d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903003734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2903003734
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2142908049
Short name T51
Test name
Test status
Simulation time 253200942890 ps
CPU time 1040.66 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:55:53 PM PDT 24
Peak memory 389000 kb
Host smart-d2c12b84-0966-4559-a01d-fb5a6f3d2117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2142908049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2142908049
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3093583175
Short name T14
Test name
Test status
Simulation time 740316193 ps
CPU time 12.4 seconds
Started Apr 30 01:39:06 PM PDT 24
Finished Apr 30 01:39:19 PM PDT 24
Peak memory 217856 kb
Host smart-7a85aa35-8bf2-4b7d-b1ee-1e37ec2d07d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093583175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3093583175
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2238339988
Short name T118
Test name
Test status
Simulation time 317340890 ps
CPU time 3.28 seconds
Started Apr 30 02:13:27 PM PDT 24
Finished Apr 30 02:13:31 PM PDT 24
Peak memory 217772 kb
Host smart-c47e4efa-adf6-4696-82a7-b5abdccaf495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238339988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2238339988
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1996070245
Short name T20
Test name
Test status
Simulation time 1225541284 ps
CPU time 4.99 seconds
Started Apr 30 01:39:01 PM PDT 24
Finished Apr 30 01:39:06 PM PDT 24
Peak memory 217044 kb
Host smart-20232990-eec8-4862-bef9-af50084749b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996070245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1996070245
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3188106877
Short name T151
Test name
Test status
Simulation time 1302420643 ps
CPU time 8.01 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 223956 kb
Host smart-7f11821b-62a1-4467-9568-f982d11ae192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188106877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3188106877
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3446457355
Short name T166
Test name
Test status
Simulation time 13712382 ps
CPU time 0.85 seconds
Started Apr 30 02:13:56 PM PDT 24
Finished Apr 30 02:13:58 PM PDT 24
Peak memory 209584 kb
Host smart-06634f91-bbe0-4585-a84a-0635f62570f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446457355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3446457355
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1105435876
Short name T11
Test name
Test status
Simulation time 20346066 ps
CPU time 0.99 seconds
Started Apr 30 01:37:44 PM PDT 24
Finished Apr 30 01:37:46 PM PDT 24
Peak memory 209416 kb
Host smart-2d60e8d8-360f-407e-a653-7ee71f973387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105435876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1105435876
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.848403864
Short name T13
Test name
Test status
Simulation time 11610354773 ps
CPU time 66.55 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:40:12 PM PDT 24
Peak memory 247304 kb
Host smart-91e8f821-9a51-48a1-8161-74fcadf2b7db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848403864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.848403864
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3228123871
Short name T42
Test name
Test status
Simulation time 35904851512 ps
CPU time 9790.76 seconds
Started Apr 30 01:38:43 PM PDT 24
Finished Apr 30 04:21:55 PM PDT 24
Peak memory 2696100 kb
Host smart-908d8b3d-439a-4fe6-9a68-a2ed5a5d1ec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3228123871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3228123871
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1591944809
Short name T113
Test name
Test status
Simulation time 397870377 ps
CPU time 3.23 seconds
Started Apr 30 02:13:51 PM PDT 24
Finished Apr 30 02:13:55 PM PDT 24
Peak memory 222272 kb
Host smart-3f06d829-b3af-49db-bf87-f5a25998bc55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591944809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1591944809
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2208128818
Short name T36
Test name
Test status
Simulation time 15224816621 ps
CPU time 142.46 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:41:10 PM PDT 24
Peak memory 274528 kb
Host smart-447249b0-c6d7-4244-8976-8854c5eac636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208128818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2208128818
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3218099657
Short name T182
Test name
Test status
Simulation time 216634361 ps
CPU time 8.85 seconds
Started Apr 30 01:39:01 PM PDT 24
Finished Apr 30 01:39:10 PM PDT 24
Peak memory 217948 kb
Host smart-b0cd4f1b-3287-4960-b608-6672e77498b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218099657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3218099657
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1454298995
Short name T898
Test name
Test status
Simulation time 81727254 ps
CPU time 2.61 seconds
Started Apr 30 02:14:09 PM PDT 24
Finished Apr 30 02:14:13 PM PDT 24
Peak memory 218068 kb
Host smart-be129870-7c60-4d33-9bfc-0e88d04bfbbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454298995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1454298995
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.449230176
Short name T15
Test name
Test status
Simulation time 321619482 ps
CPU time 12.95 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:07 PM PDT 24
Peak memory 225932 kb
Host smart-bd45edb1-5fa8-47df-9360-2ede06830e86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449230176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.449230176
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1117997763
Short name T122
Test name
Test status
Simulation time 861546328 ps
CPU time 3.1 seconds
Started Apr 30 02:13:28 PM PDT 24
Finished Apr 30 02:13:31 PM PDT 24
Peak memory 222672 kb
Host smart-00c3aed5-1006-4f79-9f1f-e159512d6c38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117997763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1117997763
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.314598806
Short name T125
Test name
Test status
Simulation time 255756833 ps
CPU time 1.69 seconds
Started Apr 30 02:13:25 PM PDT 24
Finished Apr 30 02:13:27 PM PDT 24
Peak memory 219376 kb
Host smart-7651f2fb-1dc4-480e-9f26-ccf6d0ec657d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314598
806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.314598806
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.793400827
Short name T108
Test name
Test status
Simulation time 159379661 ps
CPU time 2.1 seconds
Started Apr 30 02:13:37 PM PDT 24
Finished Apr 30 02:13:39 PM PDT 24
Peak memory 221644 kb
Host smart-79f8d64c-111f-4220-9ebb-3a4f35df09ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793400827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.793400827
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.726851571
Short name T12
Test name
Test status
Simulation time 6905991797 ps
CPU time 255.52 seconds
Started Apr 30 01:39:08 PM PDT 24
Finished Apr 30 01:43:24 PM PDT 24
Peak memory 264624 kb
Host smart-8e2de582-d70c-4d35-90bc-0a6989b42179
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726851571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.726851571
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.801950912
Short name T115
Test name
Test status
Simulation time 91730784 ps
CPU time 2.38 seconds
Started Apr 30 02:14:22 PM PDT 24
Finished Apr 30 02:14:25 PM PDT 24
Peak memory 222336 kb
Host smart-5fdcb1f7-7555-4bc0-aec0-4b7f3982d213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801950912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.801950912
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3603376174
Short name T110
Test name
Test status
Simulation time 270094034 ps
CPU time 3.59 seconds
Started Apr 30 02:13:43 PM PDT 24
Finished Apr 30 02:13:47 PM PDT 24
Peak memory 222148 kb
Host smart-e92b2b4e-9586-4e60-b0e8-ae07acbd6a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603376174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3603376174
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2868064688
Short name T176
Test name
Test status
Simulation time 13501700 ps
CPU time 0.87 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:04 PM PDT 24
Peak memory 209356 kb
Host smart-70683ab4-032f-4be7-971d-fe7bc367b7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868064688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2868064688
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3100134527
Short name T181
Test name
Test status
Simulation time 38578796 ps
CPU time 0.87 seconds
Started Apr 30 01:37:28 PM PDT 24
Finished Apr 30 01:37:29 PM PDT 24
Peak memory 209380 kb
Host smart-c7c8f613-b42f-4eb9-a6ac-47ae8b91caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100134527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3100134527
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4098855958
Short name T177
Test name
Test status
Simulation time 38658979 ps
CPU time 0.91 seconds
Started Apr 30 01:37:33 PM PDT 24
Finished Apr 30 01:37:34 PM PDT 24
Peak memory 209336 kb
Host smart-2ad46493-1a95-4d53-97a3-52db886f4294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098855958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4098855958
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3933540073
Short name T180
Test name
Test status
Simulation time 28082316 ps
CPU time 0.91 seconds
Started Apr 30 01:37:50 PM PDT 24
Finished Apr 30 01:37:52 PM PDT 24
Peak memory 209400 kb
Host smart-f1f8cb5c-d7a9-4039-b1f8-f9ca7a118ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933540073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3933540073
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2223821230
Short name T96
Test name
Test status
Simulation time 333193210 ps
CPU time 3.35 seconds
Started Apr 30 02:13:58 PM PDT 24
Finished Apr 30 02:14:03 PM PDT 24
Peak memory 222648 kb
Host smart-ff01a35c-4405-41e9-ad02-d4f9d6ce8dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223821230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2223821230
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.848157088
Short name T112
Test name
Test status
Simulation time 1735686096 ps
CPU time 2.88 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 221740 kb
Host smart-b70c6c0a-0ef2-4fca-b7be-777f03e0a4d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848157088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.848157088
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2559654202
Short name T123
Test name
Test status
Simulation time 515927568 ps
CPU time 2.41 seconds
Started Apr 30 02:14:21 PM PDT 24
Finished Apr 30 02:14:24 PM PDT 24
Peak memory 217820 kb
Host smart-7ce95265-2638-4bf0-ba44-fe556db08dba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559654202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2559654202
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.235222686
Short name T120
Test name
Test status
Simulation time 402470122 ps
CPU time 1.86 seconds
Started Apr 30 02:14:12 PM PDT 24
Finished Apr 30 02:14:15 PM PDT 24
Peak memory 217800 kb
Host smart-82571dca-d01d-4cd9-98b4-802ad85c8b66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235222686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.235222686
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2255522708
Short name T107
Test name
Test status
Simulation time 80105003 ps
CPU time 2.14 seconds
Started Apr 30 02:13:33 PM PDT 24
Finished Apr 30 02:13:36 PM PDT 24
Peak memory 222112 kb
Host smart-982eb7cb-9e6d-45ef-bc9b-29f256024747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255522708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2255522708
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3095966028
Short name T43
Test name
Test status
Simulation time 6516933117 ps
CPU time 44.88 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:44 PM PDT 24
Peak memory 218776 kb
Host smart-fbca1d92-aebb-4d6c-b266-645d6125ebc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095966028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3095966028
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2774148067
Short name T64
Test name
Test status
Simulation time 532747269 ps
CPU time 25.46 seconds
Started Apr 30 01:37:10 PM PDT 24
Finished Apr 30 01:37:36 PM PDT 24
Peak memory 250836 kb
Host smart-1a94574a-117d-4424-bd03-aeae92e4294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774148067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2774148067
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2225542256
Short name T940
Test name
Test status
Simulation time 19271702 ps
CPU time 1.41 seconds
Started Apr 30 02:13:12 PM PDT 24
Finished Apr 30 02:13:14 PM PDT 24
Peak memory 209216 kb
Host smart-d46ee443-f53b-4445-8a42-0539cff925ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225542256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2225542256
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3338783512
Short name T913
Test name
Test status
Simulation time 18414793 ps
CPU time 1.21 seconds
Started Apr 30 02:13:41 PM PDT 24
Finished Apr 30 02:13:43 PM PDT 24
Peak memory 209472 kb
Host smart-beb64b3f-052c-4d0b-a571-a47f0f3b1ef5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338783512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3338783512
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1194750193
Short name T906
Test name
Test status
Simulation time 24057916 ps
CPU time 1.03 seconds
Started Apr 30 02:13:36 PM PDT 24
Finished Apr 30 02:13:38 PM PDT 24
Peak memory 209856 kb
Host smart-31f64709-b914-4191-b706-1b7f171a88be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194750193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1194750193
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4060739837
Short name T948
Test name
Test status
Simulation time 17034197 ps
CPU time 1.16 seconds
Started Apr 30 02:13:40 PM PDT 24
Finished Apr 30 02:13:41 PM PDT 24
Peak memory 217808 kb
Host smart-a766da75-8aee-4ef2-af25-6a313f3f52a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060739837 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4060739837
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1985586073
Short name T891
Test name
Test status
Simulation time 21327291 ps
CPU time 0.85 seconds
Started Apr 30 02:13:21 PM PDT 24
Finished Apr 30 02:13:27 PM PDT 24
Peak memory 209548 kb
Host smart-953d4265-0526-40de-8d39-ac620bd46e07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985586073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1985586073
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1199777869
Short name T892
Test name
Test status
Simulation time 94398892 ps
CPU time 2.84 seconds
Started Apr 30 02:13:07 PM PDT 24
Finished Apr 30 02:13:10 PM PDT 24
Peak memory 209400 kb
Host smart-c058f349-c7d3-497b-838b-ac00be474044
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199777869 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1199777869
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2978036222
Short name T895
Test name
Test status
Simulation time 934934138 ps
CPU time 3.06 seconds
Started Apr 30 02:13:44 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 209300 kb
Host smart-b026acb1-7c58-4433-a8fd-e5b09a8cde24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978036222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2978036222
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3814628544
Short name T175
Test name
Test status
Simulation time 3000912177 ps
CPU time 5.67 seconds
Started Apr 30 02:13:15 PM PDT 24
Finished Apr 30 02:13:22 PM PDT 24
Peak memory 209528 kb
Host smart-67dddbf0-0717-4c97-b523-527811c1fad5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814628544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3814628544
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.899364164
Short name T915
Test name
Test status
Simulation time 240302859 ps
CPU time 6.09 seconds
Started Apr 30 02:13:26 PM PDT 24
Finished Apr 30 02:13:38 PM PDT 24
Peak memory 211296 kb
Host smart-3a95aff4-7184-4af2-85a3-293592ae6b34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899364164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.899364164
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.586625248
Short name T103
Test name
Test status
Simulation time 200385631 ps
CPU time 5.59 seconds
Started Apr 30 02:13:31 PM PDT 24
Finished Apr 30 02:13:37 PM PDT 24
Peak memory 223528 kb
Host smart-07a872a2-693f-4c05-8aee-f858de8f35be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586625
248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.586625248
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3310487462
Short name T106
Test name
Test status
Simulation time 121969152 ps
CPU time 1.16 seconds
Started Apr 30 02:13:21 PM PDT 24
Finished Apr 30 02:13:23 PM PDT 24
Peak memory 209536 kb
Host smart-ab2aeb86-2fb1-45d6-97ba-2bb4e411aa52
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310487462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3310487462
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.686988265
Short name T105
Test name
Test status
Simulation time 19824974 ps
CPU time 1.29 seconds
Started Apr 30 02:13:32 PM PDT 24
Finished Apr 30 02:13:33 PM PDT 24
Peak memory 211600 kb
Host smart-2c56acbd-76ac-4f8f-847e-c628b9b822c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686988265 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.686988265
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2474267341
Short name T173
Test name
Test status
Simulation time 46945993 ps
CPU time 1.88 seconds
Started Apr 30 02:13:54 PM PDT 24
Finished Apr 30 02:13:57 PM PDT 24
Peak memory 209580 kb
Host smart-2649e028-c5c0-4ce5-b88d-7bc7ea9890e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474267341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2474267341
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3475675947
Short name T929
Test name
Test status
Simulation time 90426759 ps
CPU time 1.43 seconds
Started Apr 30 02:13:15 PM PDT 24
Finished Apr 30 02:13:18 PM PDT 24
Peak memory 218988 kb
Host smart-19f0791f-f587-406a-a1c3-3c7b66f97dea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475675947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3475675947
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3170873567
Short name T114
Test name
Test status
Simulation time 213384977 ps
CPU time 3.05 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:52 PM PDT 24
Peak memory 222448 kb
Host smart-33e732b3-ff59-4f1e-aa46-bf6afb86d396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170873567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3170873567
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2894188088
Short name T167
Test name
Test status
Simulation time 22304309 ps
CPU time 1.01 seconds
Started Apr 30 02:13:16 PM PDT 24
Finished Apr 30 02:13:18 PM PDT 24
Peak memory 208816 kb
Host smart-16b5ee3d-2252-44c5-9eb6-9c4a83ba913a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894188088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2894188088
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.231634734
Short name T886
Test name
Test status
Simulation time 805454713 ps
CPU time 1.47 seconds
Started Apr 30 02:13:36 PM PDT 24
Finished Apr 30 02:13:37 PM PDT 24
Peak memory 209124 kb
Host smart-2fde466f-bf18-42cc-8978-227ed794e95b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231634734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.231634734
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.237419947
Short name T970
Test name
Test status
Simulation time 15979685 ps
CPU time 1.07 seconds
Started Apr 30 02:13:16 PM PDT 24
Finished Apr 30 02:13:18 PM PDT 24
Peak memory 210216 kb
Host smart-f439d06f-6076-43f3-99d1-7f8312516a8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237419947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.237419947
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1112284845
Short name T977
Test name
Test status
Simulation time 25446152 ps
CPU time 1.11 seconds
Started Apr 30 02:13:46 PM PDT 24
Finished Apr 30 02:13:48 PM PDT 24
Peak memory 218836 kb
Host smart-6b6adddc-4f95-47cb-ae67-77255224018f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112284845 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1112284845
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2610797314
Short name T965
Test name
Test status
Simulation time 45645967 ps
CPU time 0.84 seconds
Started Apr 30 02:13:16 PM PDT 24
Finished Apr 30 02:13:22 PM PDT 24
Peak memory 209512 kb
Host smart-79e23fc6-9218-46c9-be74-758ec222952d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610797314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2610797314
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.164723885
Short name T894
Test name
Test status
Simulation time 766447352 ps
CPU time 2.25 seconds
Started Apr 30 02:13:49 PM PDT 24
Finished Apr 30 02:13:52 PM PDT 24
Peak memory 209416 kb
Host smart-9ce8fe5f-4d12-45be-b863-164e3cdcd58a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164723885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.164723885
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3219360860
Short name T916
Test name
Test status
Simulation time 292811146 ps
CPU time 7.69 seconds
Started Apr 30 02:13:29 PM PDT 24
Finished Apr 30 02:13:38 PM PDT 24
Peak memory 209280 kb
Host smart-356a3c13-8840-493c-8303-d6be7b2e1fe3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219360860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3219360860
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4052667639
Short name T900
Test name
Test status
Simulation time 806714777 ps
CPU time 7.45 seconds
Started Apr 30 02:13:25 PM PDT 24
Finished Apr 30 02:13:32 PM PDT 24
Peak memory 209300 kb
Host smart-4e15b8a7-b011-465a-ac6d-fafa0067d1a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052667639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4052667639
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1141541916
Short name T874
Test name
Test status
Simulation time 372688242 ps
CPU time 2.78 seconds
Started Apr 30 02:13:30 PM PDT 24
Finished Apr 30 02:13:33 PM PDT 24
Peak memory 210996 kb
Host smart-83da4b46-fdf1-46f4-b239-0f6287b8f342
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141541916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1141541916
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3140319811
Short name T945
Test name
Test status
Simulation time 318537868 ps
CPU time 1.47 seconds
Started Apr 30 02:13:29 PM PDT 24
Finished Apr 30 02:13:31 PM PDT 24
Peak memory 209464 kb
Host smart-3dc0e88a-42d0-414e-b3a4-6d4208e06b28
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140319811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3140319811
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3134903569
Short name T991
Test name
Test status
Simulation time 78734998 ps
CPU time 1.24 seconds
Started Apr 30 02:13:39 PM PDT 24
Finished Apr 30 02:13:40 PM PDT 24
Peak memory 209540 kb
Host smart-423a1a1c-4d77-45d3-9354-684784745fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134903569 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3134903569
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1325962101
Short name T935
Test name
Test status
Simulation time 322014730 ps
CPU time 1.21 seconds
Started Apr 30 02:13:24 PM PDT 24
Finished Apr 30 02:13:26 PM PDT 24
Peak memory 209748 kb
Host smart-6f36e9c6-938a-4a27-a89b-1e8051297642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325962101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1325962101
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3749567988
Short name T99
Test name
Test status
Simulation time 108818284 ps
CPU time 1.9 seconds
Started Apr 30 02:13:23 PM PDT 24
Finished Apr 30 02:13:25 PM PDT 24
Peak memory 218984 kb
Host smart-3921c829-ed5f-4bce-9a11-d58afba0656d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749567988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3749567988
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1499688898
Short name T153
Test name
Test status
Simulation time 54191875 ps
CPU time 1.37 seconds
Started Apr 30 02:14:09 PM PDT 24
Finished Apr 30 02:14:11 PM PDT 24
Peak memory 217956 kb
Host smart-46e3a090-09dd-44cb-8377-4a84b5840249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499688898 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1499688898
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2168528697
Short name T870
Test name
Test status
Simulation time 14131363 ps
CPU time 0.96 seconds
Started Apr 30 02:13:47 PM PDT 24
Finished Apr 30 02:13:49 PM PDT 24
Peak memory 209116 kb
Host smart-60a73ab1-8142-4a11-9d6b-09e8b4398e84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168528697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2168528697
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3154643293
Short name T141
Test name
Test status
Simulation time 101256019 ps
CPU time 1.31 seconds
Started Apr 30 02:13:45 PM PDT 24
Finished Apr 30 02:13:47 PM PDT 24
Peak memory 209588 kb
Host smart-f5be8add-d011-4e09-a436-e219ba163e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154643293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3154643293
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.329516331
Short name T960
Test name
Test status
Simulation time 28461177 ps
CPU time 1.65 seconds
Started Apr 30 02:13:56 PM PDT 24
Finished Apr 30 02:13:58 PM PDT 24
Peak memory 221760 kb
Host smart-4280eab9-10de-4fff-af36-9a2aa07fbd22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329516331 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.329516331
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1377982050
Short name T888
Test name
Test status
Simulation time 185220755 ps
CPU time 2.04 seconds
Started Apr 30 02:14:19 PM PDT 24
Finished Apr 30 02:14:22 PM PDT 24
Peak memory 209596 kb
Host smart-72430ded-c91b-44a7-9587-f52725c75251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377982050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1377982050
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2675130721
Short name T964
Test name
Test status
Simulation time 126593565 ps
CPU time 3.36 seconds
Started Apr 30 02:13:58 PM PDT 24
Finished Apr 30 02:14:03 PM PDT 24
Peak memory 217984 kb
Host smart-601fcc9d-5472-4e95-b117-1a8973bc60e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675130721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2675130721
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1795434971
Short name T109
Test name
Test status
Simulation time 56450517 ps
CPU time 1.95 seconds
Started Apr 30 02:13:54 PM PDT 24
Finished Apr 30 02:13:57 PM PDT 24
Peak memory 222020 kb
Host smart-539d7ee7-a811-45df-8a12-a6be99132526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795434971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1795434971
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4057897853
Short name T966
Test name
Test status
Simulation time 415534151 ps
CPU time 1.39 seconds
Started Apr 30 02:14:09 PM PDT 24
Finished Apr 30 02:14:11 PM PDT 24
Peak memory 219032 kb
Host smart-53e93171-0c44-4a9e-b1dd-5672cb68cdb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057897853 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4057897853
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1534135470
Short name T172
Test name
Test status
Simulation time 14595994 ps
CPU time 1.07 seconds
Started Apr 30 02:14:06 PM PDT 24
Finished Apr 30 02:14:07 PM PDT 24
Peak memory 209572 kb
Host smart-c324ca65-19be-4e54-bcb9-04e966e6068d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534135470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1534135470
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3567368034
Short name T901
Test name
Test status
Simulation time 141971038 ps
CPU time 1.57 seconds
Started Apr 30 02:14:19 PM PDT 24
Finished Apr 30 02:14:21 PM PDT 24
Peak memory 209548 kb
Host smart-3d9abecf-919e-4491-901d-6cd9d48bea9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567368034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3567368034
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2119016924
Short name T985
Test name
Test status
Simulation time 884510285 ps
CPU time 3.53 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:52 PM PDT 24
Peak memory 217852 kb
Host smart-b64a6003-38c7-4cfd-95c3-74b1d757bb84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119016924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2119016924
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.383817575
Short name T992
Test name
Test status
Simulation time 108912876 ps
CPU time 1.59 seconds
Started Apr 30 02:14:00 PM PDT 24
Finished Apr 30 02:14:02 PM PDT 24
Peak memory 217860 kb
Host smart-df634b14-9ca8-4152-9dd9-f3d6fee6e6b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383817575 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.383817575
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2303003650
Short name T968
Test name
Test status
Simulation time 33360265 ps
CPU time 0.97 seconds
Started Apr 30 02:14:20 PM PDT 24
Finished Apr 30 02:14:22 PM PDT 24
Peak memory 209528 kb
Host smart-303cb8f8-ed41-4bba-b0e7-2fc2bb5c7d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303003650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2303003650
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3200407318
Short name T939
Test name
Test status
Simulation time 19787670 ps
CPU time 1.42 seconds
Started Apr 30 02:13:58 PM PDT 24
Finished Apr 30 02:14:00 PM PDT 24
Peak memory 209608 kb
Host smart-d9f3d26a-cbd6-4955-aa3c-ec5e996c2a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200407318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3200407318
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.235904663
Short name T102
Test name
Test status
Simulation time 82710322 ps
CPU time 1.44 seconds
Started Apr 30 02:13:53 PM PDT 24
Finished Apr 30 02:13:56 PM PDT 24
Peak memory 217912 kb
Host smart-945f6b4f-ebe1-4cde-b345-d64c0eedca0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235904663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.235904663
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3048697714
Short name T93
Test name
Test status
Simulation time 221366695 ps
CPU time 3.1 seconds
Started Apr 30 02:14:36 PM PDT 24
Finished Apr 30 02:14:45 PM PDT 24
Peak memory 222584 kb
Host smart-0a42eb78-dca0-474e-b6c2-0edd5b1ddafe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048697714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3048697714
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.448595522
Short name T980
Test name
Test status
Simulation time 58073774 ps
CPU time 1.35 seconds
Started Apr 30 02:14:10 PM PDT 24
Finished Apr 30 02:14:13 PM PDT 24
Peak memory 217864 kb
Host smart-94787c8d-8201-410d-af36-4cd3d4dadefe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448595522 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.448595522
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2415522585
Short name T994
Test name
Test status
Simulation time 15081294 ps
CPU time 1.07 seconds
Started Apr 30 02:14:02 PM PDT 24
Finished Apr 30 02:14:03 PM PDT 24
Peak memory 209276 kb
Host smart-1260ec80-af5a-4bf3-81dc-ad5358b14e74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415522585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2415522585
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.327243753
Short name T983
Test name
Test status
Simulation time 165024252 ps
CPU time 1.46 seconds
Started Apr 30 02:14:01 PM PDT 24
Finished Apr 30 02:14:03 PM PDT 24
Peak memory 211476 kb
Host smart-0d906770-882d-4e79-af5f-01e99a70cbc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327243753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.327243753
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.110958618
Short name T978
Test name
Test status
Simulation time 49775921 ps
CPU time 1.94 seconds
Started Apr 30 02:14:07 PM PDT 24
Finished Apr 30 02:14:10 PM PDT 24
Peak memory 217936 kb
Host smart-252042fc-7ebe-47ef-9c42-6633411bb268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110958618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.110958618
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1809402193
Short name T139
Test name
Test status
Simulation time 119952088 ps
CPU time 1.98 seconds
Started Apr 30 02:14:20 PM PDT 24
Finished Apr 30 02:14:22 PM PDT 24
Peak memory 221656 kb
Host smart-12c4621c-1dbd-4017-840f-5cd341c31ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809402193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1809402193
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2620690233
Short name T912
Test name
Test status
Simulation time 50591285 ps
CPU time 1.54 seconds
Started Apr 30 02:14:05 PM PDT 24
Finished Apr 30 02:14:07 PM PDT 24
Peak memory 217932 kb
Host smart-c5cd48eb-7cb7-4082-bd80-6caa7e157ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620690233 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2620690233
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3942541851
Short name T865
Test name
Test status
Simulation time 13708838 ps
CPU time 0.97 seconds
Started Apr 30 02:14:12 PM PDT 24
Finished Apr 30 02:14:14 PM PDT 24
Peak memory 209036 kb
Host smart-0fc132c4-461e-4997-b011-5df107ea7e6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942541851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3942541851
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.945848737
Short name T902
Test name
Test status
Simulation time 97531833 ps
CPU time 1.49 seconds
Started Apr 30 02:14:07 PM PDT 24
Finished Apr 30 02:14:10 PM PDT 24
Peak memory 211696 kb
Host smart-70c4c613-7445-4388-b7d8-c649c3ca3e0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945848737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.945848737
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.216139705
Short name T104
Test name
Test status
Simulation time 40084368 ps
CPU time 2.39 seconds
Started Apr 30 02:14:07 PM PDT 24
Finished Apr 30 02:14:11 PM PDT 24
Peak memory 217944 kb
Host smart-ae3754f2-504e-485b-8acf-4d62781f0314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216139705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.216139705
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2652327282
Short name T119
Test name
Test status
Simulation time 128597715 ps
CPU time 2.61 seconds
Started Apr 30 02:14:15 PM PDT 24
Finished Apr 30 02:14:18 PM PDT 24
Peak memory 217780 kb
Host smart-f18e9a5a-4b1c-49c6-b7f5-6b6923f6f7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652327282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2652327282
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3165677316
Short name T94
Test name
Test status
Simulation time 189983418 ps
CPU time 2.32 seconds
Started Apr 30 02:14:09 PM PDT 24
Finished Apr 30 02:14:13 PM PDT 24
Peak memory 219856 kb
Host smart-08caf1e5-06d0-48d4-9298-eb4e00ec137f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165677316 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3165677316
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.524138314
Short name T934
Test name
Test status
Simulation time 14897837 ps
CPU time 0.85 seconds
Started Apr 30 02:14:18 PM PDT 24
Finished Apr 30 02:14:19 PM PDT 24
Peak memory 209192 kb
Host smart-e82c367f-58a3-4dc4-be5f-cecf85700e2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524138314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.524138314
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.513528741
Short name T925
Test name
Test status
Simulation time 174126683 ps
CPU time 1.41 seconds
Started Apr 30 02:14:03 PM PDT 24
Finished Apr 30 02:14:05 PM PDT 24
Peak memory 209544 kb
Host smart-23246b2c-9960-46cc-adaa-407cd688c00d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513528741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.513528741
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1846100440
Short name T995
Test name
Test status
Simulation time 57864866 ps
CPU time 2.04 seconds
Started Apr 30 02:14:02 PM PDT 24
Finished Apr 30 02:14:05 PM PDT 24
Peak memory 217860 kb
Host smart-0e404c35-5732-47f0-8cd2-b6b7ad570076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846100440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1846100440
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1035582580
Short name T946
Test name
Test status
Simulation time 34687212 ps
CPU time 1.15 seconds
Started Apr 30 02:14:15 PM PDT 24
Finished Apr 30 02:14:16 PM PDT 24
Peak memory 219688 kb
Host smart-45223add-d571-40c2-b285-2d8d754172dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035582580 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1035582580
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2081784710
Short name T170
Test name
Test status
Simulation time 53650466 ps
CPU time 0.87 seconds
Started Apr 30 02:14:01 PM PDT 24
Finished Apr 30 02:14:02 PM PDT 24
Peak memory 209516 kb
Host smart-a160425b-36d4-4e47-90e8-1d8c0a3a192b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081784710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2081784710
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1589919199
Short name T876
Test name
Test status
Simulation time 27806625 ps
CPU time 1.08 seconds
Started Apr 30 02:14:05 PM PDT 24
Finished Apr 30 02:14:07 PM PDT 24
Peak memory 209652 kb
Host smart-d492b80c-8423-41d9-b109-5e255ee612f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589919199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1589919199
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2951376813
Short name T951
Test name
Test status
Simulation time 45241019 ps
CPU time 2.92 seconds
Started Apr 30 02:14:29 PM PDT 24
Finished Apr 30 02:14:32 PM PDT 24
Peak memory 219088 kb
Host smart-531b11f1-ba12-4abc-8e8e-4e39fc948568
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951376813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2951376813
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1838972375
Short name T868
Test name
Test status
Simulation time 69241163 ps
CPU time 1.24 seconds
Started Apr 30 02:14:17 PM PDT 24
Finished Apr 30 02:14:19 PM PDT 24
Peak memory 219988 kb
Host smart-db263053-9159-4b2f-bc85-bcc41cc10ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838972375 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1838972375
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1079724019
Short name T927
Test name
Test status
Simulation time 17217264 ps
CPU time 1.13 seconds
Started Apr 30 02:14:16 PM PDT 24
Finished Apr 30 02:14:18 PM PDT 24
Peak memory 209592 kb
Host smart-49291191-d88c-473e-b7b1-5bec756382ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079724019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1079724019
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2989857482
Short name T957
Test name
Test status
Simulation time 133538575 ps
CPU time 1.66 seconds
Started Apr 30 02:14:10 PM PDT 24
Finished Apr 30 02:14:12 PM PDT 24
Peak memory 209620 kb
Host smart-aeff0ced-1eca-47f1-93dc-6a6503d4eb39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989857482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2989857482
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1477686878
Short name T116
Test name
Test status
Simulation time 49599434 ps
CPU time 2.49 seconds
Started Apr 30 02:14:09 PM PDT 24
Finished Apr 30 02:14:12 PM PDT 24
Peak memory 217940 kb
Host smart-b3540084-fe9a-4d5e-a6d4-3a213dcb6a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477686878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1477686878
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1937031666
Short name T95
Test name
Test status
Simulation time 63562306 ps
CPU time 2.72 seconds
Started Apr 30 02:14:12 PM PDT 24
Finished Apr 30 02:14:16 PM PDT 24
Peak memory 217776 kb
Host smart-fedd8b78-5dad-48e5-9603-f0117f445c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937031666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1937031666
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2687191812
Short name T967
Test name
Test status
Simulation time 397421037 ps
CPU time 1.27 seconds
Started Apr 30 02:14:21 PM PDT 24
Finished Apr 30 02:14:23 PM PDT 24
Peak memory 219512 kb
Host smart-56b94f08-c8ff-4f5a-a9c6-cba08dc5c3ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687191812 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2687191812
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.233605892
Short name T884
Test name
Test status
Simulation time 15404095 ps
CPU time 0.84 seconds
Started Apr 30 02:14:19 PM PDT 24
Finished Apr 30 02:14:20 PM PDT 24
Peak memory 209616 kb
Host smart-eebb1c42-1b1e-4155-9e6e-7e7acaa84efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233605892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.233605892
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.370602091
Short name T923
Test name
Test status
Simulation time 255270007 ps
CPU time 1.76 seconds
Started Apr 30 02:14:10 PM PDT 24
Finished Apr 30 02:14:13 PM PDT 24
Peak memory 211608 kb
Host smart-9e7a1737-d0af-4c31-b9cc-c42d72ac893c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370602091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.370602091
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2104756602
Short name T921
Test name
Test status
Simulation time 57073867 ps
CPU time 2.37 seconds
Started Apr 30 02:14:16 PM PDT 24
Finished Apr 30 02:14:19 PM PDT 24
Peak memory 219032 kb
Host smart-d7d4508d-1389-4b70-8c04-dff6286474b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104756602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2104756602
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2262649156
Short name T866
Test name
Test status
Simulation time 46270554 ps
CPU time 1.13 seconds
Started Apr 30 02:13:32 PM PDT 24
Finished Apr 30 02:13:39 PM PDT 24
Peak memory 209564 kb
Host smart-f1b2b496-6f70-403a-93e0-c30e18d1a5e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262649156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2262649156
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.370389259
Short name T930
Test name
Test status
Simulation time 28965716 ps
CPU time 1.55 seconds
Started Apr 30 02:13:39 PM PDT 24
Finished Apr 30 02:13:41 PM PDT 24
Peak memory 209628 kb
Host smart-8fa2ab75-264f-432f-8516-e27e1e5f3483
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370389259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.370389259
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2695672081
Short name T875
Test name
Test status
Simulation time 58315065 ps
CPU time 0.98 seconds
Started Apr 30 02:13:28 PM PDT 24
Finished Apr 30 02:13:30 PM PDT 24
Peak memory 209896 kb
Host smart-3c73a500-900c-4db6-89c5-ed0fb904040d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695672081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2695672081
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1803272717
Short name T955
Test name
Test status
Simulation time 230098330 ps
CPU time 1.1 seconds
Started Apr 30 02:13:29 PM PDT 24
Finished Apr 30 02:13:30 PM PDT 24
Peak memory 217844 kb
Host smart-bb4db054-d3db-400a-a2a5-fdc908cabaa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803272717 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1803272717
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.79259501
Short name T142
Test name
Test status
Simulation time 62517385 ps
CPU time 0.86 seconds
Started Apr 30 02:13:24 PM PDT 24
Finished Apr 30 02:13:25 PM PDT 24
Peak memory 209440 kb
Host smart-a9c848e4-08b6-44ae-a439-ac81d392c8e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79259501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.79259501
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2289954299
Short name T881
Test name
Test status
Simulation time 89730132 ps
CPU time 1.27 seconds
Started Apr 30 02:13:33 PM PDT 24
Finished Apr 30 02:13:35 PM PDT 24
Peak memory 209384 kb
Host smart-b6069986-ba4c-4a83-9358-2c862e89128a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289954299 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2289954299
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4003585453
Short name T987
Test name
Test status
Simulation time 781889015 ps
CPU time 9.93 seconds
Started Apr 30 02:13:23 PM PDT 24
Finished Apr 30 02:13:33 PM PDT 24
Peak memory 209360 kb
Host smart-8fd7a438-35b6-40b8-b2ee-31b06bd0d048
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003585453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4003585453
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4138151644
Short name T909
Test name
Test status
Simulation time 1612838641 ps
CPU time 20.42 seconds
Started Apr 30 02:13:32 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 209372 kb
Host smart-3be9ad3c-4aff-4e22-9ed5-427be32c77ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138151644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4138151644
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1796790327
Short name T917
Test name
Test status
Simulation time 91450840 ps
CPU time 1.81 seconds
Started Apr 30 02:13:15 PM PDT 24
Finished Apr 30 02:13:18 PM PDT 24
Peak memory 211044 kb
Host smart-9f908efb-6999-4847-95b9-3390dafb4183
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796790327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1796790327
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3411975153
Short name T897
Test name
Test status
Simulation time 51250440 ps
CPU time 2.28 seconds
Started Apr 30 02:13:50 PM PDT 24
Finished Apr 30 02:13:54 PM PDT 24
Peak memory 217824 kb
Host smart-bf9325e6-16c1-402e-a1a9-898bb56516f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341197
5153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3411975153
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.847741589
Short name T953
Test name
Test status
Simulation time 118315175 ps
CPU time 2.11 seconds
Started Apr 30 02:13:28 PM PDT 24
Finished Apr 30 02:13:30 PM PDT 24
Peak memory 209492 kb
Host smart-17de114d-af27-41ca-833c-b5d70eb75053
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847741589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.847741589
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3119985652
Short name T908
Test name
Test status
Simulation time 28486910 ps
CPU time 1.44 seconds
Started Apr 30 02:13:32 PM PDT 24
Finished Apr 30 02:13:34 PM PDT 24
Peak memory 209604 kb
Host smart-9fc1fe32-137b-4b9d-a29a-aacf8435d15a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119985652 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3119985652
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2595142968
Short name T100
Test name
Test status
Simulation time 49274908 ps
CPU time 1.02 seconds
Started Apr 30 02:13:32 PM PDT 24
Finished Apr 30 02:13:34 PM PDT 24
Peak memory 209540 kb
Host smart-9aa16c74-b2a6-4b25-b3a9-7eca0271d0a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595142968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2595142968
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1775337040
Short name T974
Test name
Test status
Simulation time 107337925 ps
CPU time 3.24 seconds
Started Apr 30 02:13:34 PM PDT 24
Finished Apr 30 02:13:38 PM PDT 24
Peak memory 217948 kb
Host smart-6ccfebd9-c995-4bd5-8f85-d96af46117d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775337040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1775337040
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2874806680
Short name T165
Test name
Test status
Simulation time 34601453 ps
CPU time 1.65 seconds
Started Apr 30 02:13:34 PM PDT 24
Finished Apr 30 02:13:36 PM PDT 24
Peak memory 209576 kb
Host smart-2706dc29-5c52-43c9-86b9-4aac6b6ab17f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874806680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2874806680
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1379971423
Short name T950
Test name
Test status
Simulation time 115081988 ps
CPU time 3.23 seconds
Started Apr 30 02:13:38 PM PDT 24
Finished Apr 30 02:13:42 PM PDT 24
Peak memory 209548 kb
Host smart-027113ea-684b-4323-a12e-ac4c6b36ab1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379971423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1379971423
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3443353501
Short name T933
Test name
Test status
Simulation time 23992917 ps
CPU time 1.05 seconds
Started Apr 30 02:13:36 PM PDT 24
Finished Apr 30 02:13:38 PM PDT 24
Peak memory 211760 kb
Host smart-eb697caa-d382-4913-baba-2333f6db9706
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443353501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3443353501
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1080917
Short name T954
Test name
Test status
Simulation time 28321396 ps
CPU time 1.6 seconds
Started Apr 30 02:13:44 PM PDT 24
Finished Apr 30 02:13:46 PM PDT 24
Peak memory 217992 kb
Host smart-e321906f-fcfa-4650-88dd-474f5c8d493d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080917 -assert nopostproc +UVM_TESTNAME=lc
_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1080917
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2259560759
Short name T990
Test name
Test status
Simulation time 15093294 ps
CPU time 0.86 seconds
Started Apr 30 02:13:46 PM PDT 24
Finished Apr 30 02:13:48 PM PDT 24
Peak memory 209532 kb
Host smart-c7f8f527-09b2-496f-b7d0-db188f174bdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259560759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2259560759
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2139156860
Short name T871
Test name
Test status
Simulation time 1116341895 ps
CPU time 2.16 seconds
Started Apr 30 02:13:44 PM PDT 24
Finished Apr 30 02:13:46 PM PDT 24
Peak memory 209496 kb
Host smart-977ec5ee-062e-4ce2-ace6-c18ba39c07a5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139156860 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2139156860
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3053647150
Short name T961
Test name
Test status
Simulation time 1495466659 ps
CPU time 3.78 seconds
Started Apr 30 02:13:26 PM PDT 24
Finished Apr 30 02:13:30 PM PDT 24
Peak memory 209312 kb
Host smart-52779003-bca1-42ad-9e9e-bd390bf9fb26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053647150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3053647150
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2232024031
Short name T896
Test name
Test status
Simulation time 1500051637 ps
CPU time 7.39 seconds
Started Apr 30 02:13:35 PM PDT 24
Finished Apr 30 02:13:43 PM PDT 24
Peak memory 209540 kb
Host smart-251665b7-95d3-425a-a480-cd10369c16b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232024031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2232024031
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3699865107
Short name T931
Test name
Test status
Simulation time 152416703 ps
CPU time 2.1 seconds
Started Apr 30 02:13:45 PM PDT 24
Finished Apr 30 02:13:48 PM PDT 24
Peak memory 210936 kb
Host smart-aab9fe3d-d843-4a43-b2dd-1c5a9f04df0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699865107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3699865107
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3333654226
Short name T936
Test name
Test status
Simulation time 83999973 ps
CPU time 2.07 seconds
Started Apr 30 02:13:37 PM PDT 24
Finished Apr 30 02:13:40 PM PDT 24
Peak memory 223224 kb
Host smart-5ee3d6a5-b7ca-4e26-a366-ac5439a58173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333365
4226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3333654226
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1244676088
Short name T932
Test name
Test status
Simulation time 58474398 ps
CPU time 2.12 seconds
Started Apr 30 02:13:47 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 209484 kb
Host smart-95bd8751-4b08-40bd-9e67-464edf2accd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244676088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1244676088
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2176094827
Short name T138
Test name
Test status
Simulation time 38523130 ps
CPU time 1.38 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 209380 kb
Host smart-7ed04fdb-9e64-44aa-97d9-7be0c6143eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176094827 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2176094827
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1944445994
Short name T903
Test name
Test status
Simulation time 99113209 ps
CPU time 1.35 seconds
Started Apr 30 02:13:37 PM PDT 24
Finished Apr 30 02:13:39 PM PDT 24
Peak memory 209524 kb
Host smart-7c8b4b98-586d-4fc2-b62f-d99535aaf420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944445994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1944445994
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.325643402
Short name T969
Test name
Test status
Simulation time 145692303 ps
CPU time 2.03 seconds
Started Apr 30 02:13:29 PM PDT 24
Finished Apr 30 02:13:31 PM PDT 24
Peak memory 217920 kb
Host smart-9a7bbaae-0bff-4149-9f49-3a1d3ca86235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325643402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.325643402
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.674983979
Short name T168
Test name
Test status
Simulation time 80038864 ps
CPU time 1.05 seconds
Started Apr 30 02:13:39 PM PDT 24
Finished Apr 30 02:13:41 PM PDT 24
Peak memory 209692 kb
Host smart-36ba821c-82c9-4181-a304-22d02f5766f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674983979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.674983979
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3848604447
Short name T947
Test name
Test status
Simulation time 454312217 ps
CPU time 1.95 seconds
Started Apr 30 02:13:41 PM PDT 24
Finished Apr 30 02:13:43 PM PDT 24
Peak memory 209576 kb
Host smart-060af774-ad47-4a71-9b32-556d0ccbfa1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848604447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3848604447
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3939701316
Short name T937
Test name
Test status
Simulation time 25165404 ps
CPU time 1.13 seconds
Started Apr 30 02:13:34 PM PDT 24
Finished Apr 30 02:13:35 PM PDT 24
Peak memory 218304 kb
Host smart-a6f8d3fb-5847-41c1-891c-4f6afc4b12f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939701316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3939701316
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1437803009
Short name T893
Test name
Test status
Simulation time 50782792 ps
CPU time 1.24 seconds
Started Apr 30 02:13:53 PM PDT 24
Finished Apr 30 02:13:55 PM PDT 24
Peak memory 218888 kb
Host smart-3f0976e4-1777-4ee1-944e-e45800a1e5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437803009 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1437803009
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3306071153
Short name T924
Test name
Test status
Simulation time 16985462 ps
CPU time 0.94 seconds
Started Apr 30 02:13:53 PM PDT 24
Finished Apr 30 02:13:55 PM PDT 24
Peak memory 209780 kb
Host smart-d96a1962-aa5c-4a3e-8d3b-532106673346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306071153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3306071153
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3505280063
Short name T988
Test name
Test status
Simulation time 39684251 ps
CPU time 1.03 seconds
Started Apr 30 02:13:40 PM PDT 24
Finished Apr 30 02:13:42 PM PDT 24
Peak memory 209468 kb
Host smart-5a779df8-0ce0-4538-8f0a-cfe0b472d36e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505280063 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3505280063
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.785885850
Short name T956
Test name
Test status
Simulation time 832389309 ps
CPU time 10.25 seconds
Started Apr 30 02:13:46 PM PDT 24
Finished Apr 30 02:13:58 PM PDT 24
Peak memory 209300 kb
Host smart-b0b361df-e15b-45a5-b5ec-68109547c7ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785885850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.785885850
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.268762818
Short name T885
Test name
Test status
Simulation time 2319819648 ps
CPU time 6.48 seconds
Started Apr 30 02:13:46 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 209344 kb
Host smart-16810306-4f05-4474-897b-88bcbcacad24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268762818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.268762818
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2236918822
Short name T873
Test name
Test status
Simulation time 60750407 ps
CPU time 1.91 seconds
Started Apr 30 02:13:41 PM PDT 24
Finished Apr 30 02:13:43 PM PDT 24
Peak memory 210940 kb
Host smart-9ab8cbec-6f7d-4962-867d-761d44b6f7b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236918822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2236918822
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.892795740
Short name T867
Test name
Test status
Simulation time 169456417 ps
CPU time 3.11 seconds
Started Apr 30 02:14:02 PM PDT 24
Finished Apr 30 02:14:06 PM PDT 24
Peak memory 222468 kb
Host smart-af3e306a-6cba-4fab-8974-7469cc2737df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892795
740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.892795740
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2929325739
Short name T928
Test name
Test status
Simulation time 153662775 ps
CPU time 3.96 seconds
Started Apr 30 02:14:03 PM PDT 24
Finished Apr 30 02:14:08 PM PDT 24
Peak memory 209540 kb
Host smart-d00999cf-fbaa-4e06-a2d3-a716bcc127e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929325739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2929325739
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3459374168
Short name T942
Test name
Test status
Simulation time 37979645 ps
CPU time 1.43 seconds
Started Apr 30 02:13:50 PM PDT 24
Finished Apr 30 02:13:52 PM PDT 24
Peak memory 211464 kb
Host smart-eab5460b-6940-4612-9fbb-3c821091d8be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459374168 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3459374168
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2748750183
Short name T926
Test name
Test status
Simulation time 142399522 ps
CPU time 1.78 seconds
Started Apr 30 02:13:35 PM PDT 24
Finished Apr 30 02:13:38 PM PDT 24
Peak memory 209584 kb
Host smart-7489b4e8-4460-4237-b78d-10a02d6f5d6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748750183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2748750183
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1418239643
Short name T889
Test name
Test status
Simulation time 595679522 ps
CPU time 3.96 seconds
Started Apr 30 02:13:43 PM PDT 24
Finished Apr 30 02:13:48 PM PDT 24
Peak memory 217968 kb
Host smart-efc3ebd1-0a47-4ef5-8ee3-a3a60fd60939
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418239643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1418239643
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.137485535
Short name T918
Test name
Test status
Simulation time 46627243 ps
CPU time 1.94 seconds
Started Apr 30 02:13:44 PM PDT 24
Finished Apr 30 02:13:47 PM PDT 24
Peak memory 219060 kb
Host smart-0a2dcf87-6689-4aa9-b70b-1c1ad88de125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137485535 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.137485535
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4195636629
Short name T169
Test name
Test status
Simulation time 46894808 ps
CPU time 1.04 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 209300 kb
Host smart-65a57486-944b-4a05-ac77-0252fed314ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195636629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.4195636629
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.776194351
Short name T944
Test name
Test status
Simulation time 47313944 ps
CPU time 1.83 seconds
Started Apr 30 02:13:56 PM PDT 24
Finished Apr 30 02:13:58 PM PDT 24
Peak memory 208188 kb
Host smart-6ceb71df-a68a-4361-9471-65245ac6f4e0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776194351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.776194351
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3919386090
Short name T880
Test name
Test status
Simulation time 2017985570 ps
CPU time 21.94 seconds
Started Apr 30 02:13:44 PM PDT 24
Finished Apr 30 02:14:06 PM PDT 24
Peak memory 209256 kb
Host smart-cf87578c-87e6-4d4f-a0a4-030d3b994b24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919386090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3919386090
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1888423260
Short name T882
Test name
Test status
Simulation time 4029464051 ps
CPU time 9.89 seconds
Started Apr 30 02:13:56 PM PDT 24
Finished Apr 30 02:14:07 PM PDT 24
Peak memory 209416 kb
Host smart-fbebb308-5870-4449-84c7-ca85063f168f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888423260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1888423260
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1640527295
Short name T904
Test name
Test status
Simulation time 299865502 ps
CPU time 1.76 seconds
Started Apr 30 02:13:46 PM PDT 24
Finished Apr 30 02:13:49 PM PDT 24
Peak memory 211060 kb
Host smart-c3201645-bf15-4a7c-8d07-a312e683a766
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640527295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1640527295
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4168928887
Short name T984
Test name
Test status
Simulation time 208812382 ps
CPU time 1.51 seconds
Started Apr 30 02:13:45 PM PDT 24
Finished Apr 30 02:13:48 PM PDT 24
Peak memory 218912 kb
Host smart-7ae2c3fe-b4aa-4b1e-912e-0619e965ed28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416892
8887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4168928887
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3347762783
Short name T862
Test name
Test status
Simulation time 351249258 ps
CPU time 1.43 seconds
Started Apr 30 02:13:45 PM PDT 24
Finished Apr 30 02:13:48 PM PDT 24
Peak memory 209512 kb
Host smart-6195c2d5-a887-406a-9477-4dcb1066e589
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347762783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3347762783
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2624318927
Short name T952
Test name
Test status
Simulation time 45671753 ps
CPU time 1.05 seconds
Started Apr 30 02:13:47 PM PDT 24
Finished Apr 30 02:13:49 PM PDT 24
Peak memory 209608 kb
Host smart-ba7ca7e6-ac41-4bd0-83be-14c1337ca681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624318927 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2624318927
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.660325263
Short name T971
Test name
Test status
Simulation time 51428116 ps
CPU time 1.43 seconds
Started Apr 30 02:13:57 PM PDT 24
Finished Apr 30 02:14:00 PM PDT 24
Peak memory 209272 kb
Host smart-b2131865-08c7-4493-abfd-e78699176833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660325263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.660325263
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3843471704
Short name T920
Test name
Test status
Simulation time 91477164 ps
CPU time 1.7 seconds
Started Apr 30 02:13:50 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 218080 kb
Host smart-90ee442b-2176-4262-819b-a46ec9dc9c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843471704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3843471704
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.219679553
Short name T914
Test name
Test status
Simulation time 38484316 ps
CPU time 1.05 seconds
Started Apr 30 02:13:55 PM PDT 24
Finished Apr 30 02:13:57 PM PDT 24
Peak memory 218996 kb
Host smart-0355279b-912c-4908-b2d0-501e03b219cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219679553 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.219679553
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3707901722
Short name T949
Test name
Test status
Simulation time 37486398 ps
CPU time 0.81 seconds
Started Apr 30 02:13:41 PM PDT 24
Finished Apr 30 02:13:42 PM PDT 24
Peak memory 208820 kb
Host smart-01d6e320-6556-41e4-9892-79521a1f6364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707901722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3707901722
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1198908092
Short name T911
Test name
Test status
Simulation time 42713996 ps
CPU time 1.26 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:50 PM PDT 24
Peak memory 208144 kb
Host smart-29855c03-fe44-4846-8d89-e6cfb1543e3c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198908092 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1198908092
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1618097154
Short name T879
Test name
Test status
Simulation time 1638488001 ps
CPU time 9.99 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:59 PM PDT 24
Peak memory 209380 kb
Host smart-c5632b61-214a-4a60-adc5-f22463d3cd8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618097154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1618097154
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.576017385
Short name T993
Test name
Test status
Simulation time 6284335415 ps
CPU time 36.29 seconds
Started Apr 30 02:14:03 PM PDT 24
Finished Apr 30 02:14:40 PM PDT 24
Peak memory 209556 kb
Host smart-55748535-861e-462d-a128-d516667a9124
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576017385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.576017385
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.380270384
Short name T979
Test name
Test status
Simulation time 369586660 ps
CPU time 2.89 seconds
Started Apr 30 02:13:56 PM PDT 24
Finished Apr 30 02:13:59 PM PDT 24
Peak memory 211208 kb
Host smart-9630b675-b2cc-48fb-901f-19ef45018528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380270384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.380270384
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1697686127
Short name T154
Test name
Test status
Simulation time 342373717 ps
CPU time 1.75 seconds
Started Apr 30 02:13:50 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 219160 kb
Host smart-30f40c97-4dd2-49f3-a176-ced676396152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169768
6127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1697686127
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1262322225
Short name T973
Test name
Test status
Simulation time 89745188 ps
CPU time 1.58 seconds
Started Apr 30 02:13:49 PM PDT 24
Finished Apr 30 02:13:52 PM PDT 24
Peak memory 209492 kb
Host smart-7ce945a7-1160-41f3-9ddb-26c3ee3276c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262322225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1262322225
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.223649218
Short name T976
Test name
Test status
Simulation time 171860073 ps
CPU time 1.27 seconds
Started Apr 30 02:13:36 PM PDT 24
Finished Apr 30 02:13:38 PM PDT 24
Peak memory 209564 kb
Host smart-69269236-66cc-4ede-8c8c-c001dbecceab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223649218 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.223649218
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1978649379
Short name T975
Test name
Test status
Simulation time 47706973 ps
CPU time 0.97 seconds
Started Apr 30 02:13:44 PM PDT 24
Finished Apr 30 02:13:45 PM PDT 24
Peak memory 209608 kb
Host smart-c3ded988-02c4-44cc-9720-b0774efb0d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978649379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1978649379
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1792591856
Short name T111
Test name
Test status
Simulation time 41698631 ps
CPU time 1.43 seconds
Started Apr 30 02:13:44 PM PDT 24
Finished Apr 30 02:13:47 PM PDT 24
Peak memory 217972 kb
Host smart-22a306ef-fb78-419a-9dba-a0778d20755f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792591856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1792591856
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2848209483
Short name T943
Test name
Test status
Simulation time 60987187 ps
CPU time 1.96 seconds
Started Apr 30 02:13:43 PM PDT 24
Finished Apr 30 02:13:46 PM PDT 24
Peak memory 221784 kb
Host smart-7240250d-a587-45bb-a058-477261926588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848209483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2848209483
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3017738542
Short name T989
Test name
Test status
Simulation time 84901741 ps
CPU time 1.04 seconds
Started Apr 30 02:13:46 PM PDT 24
Finished Apr 30 02:13:48 PM PDT 24
Peak memory 219088 kb
Host smart-f72e7280-821d-4d72-9802-3e2b6a825388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017738542 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3017738542
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3081739081
Short name T887
Test name
Test status
Simulation time 26001025 ps
CPU time 0.85 seconds
Started Apr 30 02:14:00 PM PDT 24
Finished Apr 30 02:14:02 PM PDT 24
Peak memory 209516 kb
Host smart-bf995ce8-618d-4d7e-8098-098be0dcd9b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081739081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3081739081
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2693301629
Short name T864
Test name
Test status
Simulation time 85656396 ps
CPU time 0.94 seconds
Started Apr 30 02:13:45 PM PDT 24
Finished Apr 30 02:13:47 PM PDT 24
Peak memory 208044 kb
Host smart-70c3d82d-d334-4b6d-805c-2d90f2fedd1f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693301629 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2693301629
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1366951553
Short name T981
Test name
Test status
Simulation time 9273269067 ps
CPU time 8 seconds
Started Apr 30 02:13:43 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 209584 kb
Host smart-119492ba-a834-4f97-a364-dbd6fa33936d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366951553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1366951553
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3978393079
Short name T878
Test name
Test status
Simulation time 548121756 ps
CPU time 12.77 seconds
Started Apr 30 02:13:51 PM PDT 24
Finished Apr 30 02:14:05 PM PDT 24
Peak memory 209328 kb
Host smart-d0441d06-fd40-42e6-8651-3b43d73b3849
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978393079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3978393079
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2268611437
Short name T124
Test name
Test status
Simulation time 174270996 ps
CPU time 2.11 seconds
Started Apr 30 02:13:48 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 211068 kb
Host smart-7e65ff50-f023-44ec-adc7-317057b2c6ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268611437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2268611437
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.41585967
Short name T877
Test name
Test status
Simulation time 35608671 ps
CPU time 1.56 seconds
Started Apr 30 02:14:01 PM PDT 24
Finished Apr 30 02:14:03 PM PDT 24
Peak memory 209536 kb
Host smart-d44613d9-322d-4065-a9c4-1697e8154137
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 7.lc_ctrl_jtag_csr_rw.41585967
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2903843268
Short name T907
Test name
Test status
Simulation time 21333249 ps
CPU time 1.39 seconds
Started Apr 30 02:14:03 PM PDT 24
Finished Apr 30 02:14:05 PM PDT 24
Peak memory 209632 kb
Host smart-d6dabad3-6b3e-48bc-9ae9-f17e0d959cf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903843268 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2903843268
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3152106735
Short name T938
Test name
Test status
Simulation time 37471270 ps
CPU time 1.36 seconds
Started Apr 30 02:13:56 PM PDT 24
Finished Apr 30 02:13:58 PM PDT 24
Peak memory 209556 kb
Host smart-927255c6-eb9c-49f3-8179-ad68f351c9c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152106735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3152106735
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.668876376
Short name T963
Test name
Test status
Simulation time 35551994 ps
CPU time 2.48 seconds
Started Apr 30 02:13:50 PM PDT 24
Finished Apr 30 02:13:54 PM PDT 24
Peak memory 217868 kb
Host smart-d9627957-b530-4064-b5a1-29d7fd370ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668876376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.668876376
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.685864510
Short name T982
Test name
Test status
Simulation time 111383592 ps
CPU time 1.3 seconds
Started Apr 30 02:14:01 PM PDT 24
Finished Apr 30 02:14:03 PM PDT 24
Peak memory 217836 kb
Host smart-6041f071-c6a3-47d2-bb55-f0258a95a5e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685864510 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.685864510
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2507165952
Short name T962
Test name
Test status
Simulation time 35843657 ps
CPU time 0.93 seconds
Started Apr 30 02:13:50 PM PDT 24
Finished Apr 30 02:13:52 PM PDT 24
Peak memory 209528 kb
Host smart-e56933cf-8100-4681-9e68-d73a2405d04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507165952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2507165952
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.605890061
Short name T958
Test name
Test status
Simulation time 114710709 ps
CPU time 1.62 seconds
Started Apr 30 02:14:08 PM PDT 24
Finished Apr 30 02:14:11 PM PDT 24
Peak memory 209416 kb
Host smart-51d1651c-10e7-4546-b456-38c745501bc4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605890061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.605890061
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.419637617
Short name T869
Test name
Test status
Simulation time 713353871 ps
CPU time 7.98 seconds
Started Apr 30 02:14:00 PM PDT 24
Finished Apr 30 02:14:09 PM PDT 24
Peak memory 209268 kb
Host smart-e775935e-1f28-4337-9ea3-9e767176130f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419637617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.419637617
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.728724795
Short name T905
Test name
Test status
Simulation time 4987728892 ps
CPU time 10.67 seconds
Started Apr 30 02:14:02 PM PDT 24
Finished Apr 30 02:14:13 PM PDT 24
Peak memory 209596 kb
Host smart-e5f6aa30-bd2c-4b59-829c-9b585684cd1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728724795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.728724795
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3218704744
Short name T919
Test name
Test status
Simulation time 59507624 ps
CPU time 1.55 seconds
Started Apr 30 02:13:58 PM PDT 24
Finished Apr 30 02:14:01 PM PDT 24
Peak memory 210980 kb
Host smart-f7c1813a-fe70-4d5f-8a19-6c951091394d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218704744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3218704744
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.338919646
Short name T890
Test name
Test status
Simulation time 505046933 ps
CPU time 2.46 seconds
Started Apr 30 02:14:02 PM PDT 24
Finished Apr 30 02:14:06 PM PDT 24
Peak memory 218996 kb
Host smart-84e75784-92fd-4255-9237-4e409423adbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338919
646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.338919646
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3365451819
Short name T959
Test name
Test status
Simulation time 418250963 ps
CPU time 1.11 seconds
Started Apr 30 02:13:51 PM PDT 24
Finished Apr 30 02:13:53 PM PDT 24
Peak memory 209540 kb
Host smart-d62bbf5e-6790-42fb-931d-4c0d943e2c42
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365451819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3365451819
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3389018517
Short name T883
Test name
Test status
Simulation time 28759365 ps
CPU time 1.15 seconds
Started Apr 30 02:13:51 PM PDT 24
Finished Apr 30 02:13:58 PM PDT 24
Peak memory 209600 kb
Host smart-d2f24f64-75b7-49ca-8214-ebe69209e069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389018517 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3389018517
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2690394841
Short name T171
Test name
Test status
Simulation time 113527351 ps
CPU time 1.4 seconds
Started Apr 30 02:14:03 PM PDT 24
Finished Apr 30 02:14:05 PM PDT 24
Peak memory 209608 kb
Host smart-09ca6519-fb58-42b1-9d91-e5c51d28e7f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690394841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2690394841
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1978966738
Short name T941
Test name
Test status
Simulation time 500703438 ps
CPU time 3.64 seconds
Started Apr 30 02:13:46 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 217848 kb
Host smart-fbf0326e-8c61-4bbc-afd9-f67dae0dd3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978966738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1978966738
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2728917778
Short name T163
Test name
Test status
Simulation time 164838809 ps
CPU time 1.89 seconds
Started Apr 30 02:13:47 PM PDT 24
Finished Apr 30 02:13:49 PM PDT 24
Peak memory 222172 kb
Host smart-4f81db54-49e8-4fcf-9b2f-62b8bee4d330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728917778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2728917778
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2476056489
Short name T97
Test name
Test status
Simulation time 38146213 ps
CPU time 1.26 seconds
Started Apr 30 02:13:49 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 217872 kb
Host smart-20d32d06-307e-4ee8-a5c0-ef881cefbf20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476056489 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2476056489
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1713871410
Short name T910
Test name
Test status
Simulation time 100186962 ps
CPU time 0.97 seconds
Started Apr 30 02:14:02 PM PDT 24
Finished Apr 30 02:14:03 PM PDT 24
Peak memory 209468 kb
Host smart-185a9876-0c29-4fbf-9a22-3ac98b95a897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713871410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1713871410
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2141823393
Short name T863
Test name
Test status
Simulation time 89664862 ps
CPU time 1.69 seconds
Started Apr 30 02:13:53 PM PDT 24
Finished Apr 30 02:13:56 PM PDT 24
Peak memory 209420 kb
Host smart-4caa5706-48f4-4aee-bd75-365121aea912
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141823393 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2141823393
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3766383038
Short name T972
Test name
Test status
Simulation time 579920695 ps
CPU time 6.85 seconds
Started Apr 30 02:13:49 PM PDT 24
Finished Apr 30 02:13:57 PM PDT 24
Peak memory 209300 kb
Host smart-bd84d7b0-13c7-4a16-97ee-c2ad54a78223
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766383038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3766383038
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2578578823
Short name T986
Test name
Test status
Simulation time 16775294466 ps
CPU time 24.37 seconds
Started Apr 30 02:13:47 PM PDT 24
Finished Apr 30 02:14:12 PM PDT 24
Peak memory 209524 kb
Host smart-3b0dbdce-7b84-4083-b088-2b010283c6db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578578823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2578578823
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1855070874
Short name T126
Test name
Test status
Simulation time 761312163 ps
CPU time 1.87 seconds
Started Apr 30 02:13:55 PM PDT 24
Finished Apr 30 02:13:58 PM PDT 24
Peak memory 210992 kb
Host smart-6e4cdfab-0ad6-4710-ae9e-45ec7a6b1821
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855070874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1855070874
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3270972584
Short name T922
Test name
Test status
Simulation time 818036390 ps
CPU time 2.48 seconds
Started Apr 30 02:14:05 PM PDT 24
Finished Apr 30 02:14:09 PM PDT 24
Peak memory 219208 kb
Host smart-24b1b8c5-7801-4070-acf6-f3ed24960f85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327097
2584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3270972584
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.47266020
Short name T872
Test name
Test status
Simulation time 167142977 ps
CPU time 1.34 seconds
Started Apr 30 02:14:02 PM PDT 24
Finished Apr 30 02:14:04 PM PDT 24
Peak memory 209396 kb
Host smart-6872873a-5d4d-42a2-86ac-96bc19e3c0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47266020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 9.lc_ctrl_jtag_csr_rw.47266020
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2505949162
Short name T140
Test name
Test status
Simulation time 207383473 ps
CPU time 1.45 seconds
Started Apr 30 02:14:07 PM PDT 24
Finished Apr 30 02:14:09 PM PDT 24
Peak memory 211732 kb
Host smart-4ee036ec-e9af-4962-ba1c-e42ecdbb14fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505949162 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2505949162
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4049158581
Short name T899
Test name
Test status
Simulation time 241397043 ps
CPU time 1.47 seconds
Started Apr 30 02:13:55 PM PDT 24
Finished Apr 30 02:13:57 PM PDT 24
Peak memory 211408 kb
Host smart-b3be87ec-6a77-4584-80ce-c2846013eca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049158581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4049158581
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3729196273
Short name T117
Test name
Test status
Simulation time 90939149 ps
CPU time 3.83 seconds
Started Apr 30 02:14:04 PM PDT 24
Finished Apr 30 02:14:09 PM PDT 24
Peak memory 217880 kb
Host smart-9cadaef8-4fc3-4eb3-8ab9-230b2a348727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729196273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3729196273
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4218929669
Short name T121
Test name
Test status
Simulation time 47398861 ps
CPU time 2.3 seconds
Started Apr 30 02:13:47 PM PDT 24
Finished Apr 30 02:13:51 PM PDT 24
Peak memory 222136 kb
Host smart-aeed6796-4c05-454e-8168-708d7954d949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218929669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4218929669
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3256057754
Short name T293
Test name
Test status
Simulation time 67069191 ps
CPU time 1.18 seconds
Started Apr 30 01:37:03 PM PDT 24
Finished Apr 30 01:37:05 PM PDT 24
Peak memory 209460 kb
Host smart-0f2dfab4-f2c5-41f3-878e-d9ddb2b93e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256057754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3256057754
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2921678600
Short name T511
Test name
Test status
Simulation time 671232595 ps
CPU time 18.21 seconds
Started Apr 30 01:37:04 PM PDT 24
Finished Apr 30 01:37:23 PM PDT 24
Peak memory 217756 kb
Host smart-bcfab0de-7084-4e43-b2eb-1efb0b963eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921678600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2921678600
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.228170380
Short name T443
Test name
Test status
Simulation time 2190013324 ps
CPU time 2.62 seconds
Started Apr 30 01:37:06 PM PDT 24
Finished Apr 30 01:37:09 PM PDT 24
Peak memory 209420 kb
Host smart-90f0be78-063f-474f-aa1c-4dae66481243
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228170380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.228170380
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2537956517
Short name T551
Test name
Test status
Simulation time 20483280647 ps
CPU time 33.37 seconds
Started Apr 30 01:37:07 PM PDT 24
Finished Apr 30 01:37:40 PM PDT 24
Peak memory 218860 kb
Host smart-4a32c51a-7a95-4fc0-8a28-46c4693e4102
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537956517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2537956517
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3745920708
Short name T844
Test name
Test status
Simulation time 187577743 ps
CPU time 2.86 seconds
Started Apr 30 01:37:03 PM PDT 24
Finished Apr 30 01:37:06 PM PDT 24
Peak memory 217784 kb
Host smart-12c59512-6f9f-48d9-8c85-eab56550e06c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745920708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
745920708
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1880614940
Short name T712
Test name
Test status
Simulation time 372536779 ps
CPU time 6.8 seconds
Started Apr 30 01:37:03 PM PDT 24
Finished Apr 30 01:37:10 PM PDT 24
Peak memory 217680 kb
Host smart-760900e7-58ba-4a90-8a07-3d442b027008
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880614940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1880614940
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1346310913
Short name T860
Test name
Test status
Simulation time 1011233474 ps
CPU time 12.95 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:15 PM PDT 24
Peak memory 213184 kb
Host smart-8d95ac2b-4eec-44e3-acfa-429c1a3a8f1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346310913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1346310913
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2248616270
Short name T764
Test name
Test status
Simulation time 278144629 ps
CPU time 2.88 seconds
Started Apr 30 01:37:07 PM PDT 24
Finished Apr 30 01:37:10 PM PDT 24
Peak memory 213056 kb
Host smart-25983e70-4653-4a85-b9f1-fac33a8a21fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248616270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2248616270
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.351716457
Short name T400
Test name
Test status
Simulation time 5240024092 ps
CPU time 91.97 seconds
Started Apr 30 01:37:03 PM PDT 24
Finished Apr 30 01:38:35 PM PDT 24
Peak memory 275868 kb
Host smart-ac36c49a-326f-48c2-965c-5e179c0ae9ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351716457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.351716457
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.785774834
Short name T391
Test name
Test status
Simulation time 2313837847 ps
CPU time 12.43 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:14 PM PDT 24
Peak memory 250784 kb
Host smart-a17bdb84-62c1-4b76-832b-dfa422908649
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785774834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.785774834
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2175080203
Short name T528
Test name
Test status
Simulation time 339314834 ps
CPU time 3.16 seconds
Started Apr 30 01:37:01 PM PDT 24
Finished Apr 30 01:37:04 PM PDT 24
Peak memory 217728 kb
Host smart-3306dbbd-4dd9-4c20-aa77-4c16c4e930eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175080203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2175080203
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.408872531
Short name T740
Test name
Test status
Simulation time 346217858 ps
CPU time 8.76 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:11 PM PDT 24
Peak memory 214192 kb
Host smart-1257979a-9a31-4b95-93c2-c3bfc7419569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408872531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.408872531
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1063370251
Short name T70
Test name
Test status
Simulation time 123995713 ps
CPU time 23.89 seconds
Started Apr 30 01:37:07 PM PDT 24
Finished Apr 30 01:37:31 PM PDT 24
Peak memory 269184 kb
Host smart-527dc4b2-abd7-4134-8a2e-0b822dc2a688
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063370251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1063370251
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.989274878
Short name T189
Test name
Test status
Simulation time 751056835 ps
CPU time 16.2 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:19 PM PDT 24
Peak memory 218964 kb
Host smart-85726bcc-eeee-401b-a38d-d4373106f458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989274878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.989274878
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2575317126
Short name T804
Test name
Test status
Simulation time 291786999 ps
CPU time 7.94 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:10 PM PDT 24
Peak memory 217828 kb
Host smart-a332f315-4448-4742-a665-af4ef64b3dc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575317126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2575317126
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1464410182
Short name T595
Test name
Test status
Simulation time 1256779457 ps
CPU time 11.87 seconds
Started Apr 30 01:37:07 PM PDT 24
Finished Apr 30 01:37:19 PM PDT 24
Peak memory 217896 kb
Host smart-655b3df5-2972-4ade-8607-1cdcdc43dee6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464410182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
464410182
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.980189250
Short name T185
Test name
Test status
Simulation time 1238355136 ps
CPU time 12.07 seconds
Started Apr 30 01:37:01 PM PDT 24
Finished Apr 30 01:37:13 PM PDT 24
Peak memory 217852 kb
Host smart-5bfc3918-5b07-424d-8fb0-3ee0cfd1f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980189250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.980189250
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1361486253
Short name T333
Test name
Test status
Simulation time 64429658 ps
CPU time 4.19 seconds
Started Apr 30 01:36:56 PM PDT 24
Finished Apr 30 01:37:01 PM PDT 24
Peak memory 214656 kb
Host smart-c80ee7bc-e860-401b-b875-0f499859ca40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361486253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1361486253
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3471661776
Short name T404
Test name
Test status
Simulation time 249952544 ps
CPU time 26.09 seconds
Started Apr 30 01:37:04 PM PDT 24
Finished Apr 30 01:37:30 PM PDT 24
Peak memory 248640 kb
Host smart-d018861b-4bda-4974-a330-d7c6efbeff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471661776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3471661776
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3406882140
Short name T794
Test name
Test status
Simulation time 345426845 ps
CPU time 8.55 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:11 PM PDT 24
Peak memory 250728 kb
Host smart-523792e3-3d06-4ee0-a126-8784e7b20bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406882140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3406882140
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1073202522
Short name T556
Test name
Test status
Simulation time 45057947 ps
CPU time 0.98 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:03 PM PDT 24
Peak memory 212588 kb
Host smart-c14c843e-d058-41c1-bcb3-a00024809545
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073202522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1073202522
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2806965075
Short name T390
Test name
Test status
Simulation time 22774026 ps
CPU time 1.26 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:19 PM PDT 24
Peak memory 209596 kb
Host smart-12910d30-bcb1-447d-912b-fd3d3955fffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806965075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2806965075
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2453363171
Short name T416
Test name
Test status
Simulation time 12446815 ps
CPU time 0.83 seconds
Started Apr 30 01:37:08 PM PDT 24
Finished Apr 30 01:37:10 PM PDT 24
Peak memory 209328 kb
Host smart-340494ba-9d3e-4775-abf4-5067d3aab0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453363171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2453363171
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.16324771
Short name T378
Test name
Test status
Simulation time 1483861167 ps
CPU time 10.55 seconds
Started Apr 30 01:37:10 PM PDT 24
Finished Apr 30 01:37:21 PM PDT 24
Peak memory 217844 kb
Host smart-bb754555-0e29-4c41-9085-e73ed1a6a0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16324771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.16324771
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.143034734
Short name T674
Test name
Test status
Simulation time 2468417567 ps
CPU time 11.13 seconds
Started Apr 30 01:37:12 PM PDT 24
Finished Apr 30 01:37:23 PM PDT 24
Peak memory 217436 kb
Host smart-42cf8cb3-fa36-4867-8c76-eae0a87e45a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143034734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.143034734
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2171989344
Short name T622
Test name
Test status
Simulation time 6563701759 ps
CPU time 24.32 seconds
Started Apr 30 01:37:14 PM PDT 24
Finished Apr 30 01:37:39 PM PDT 24
Peak memory 218364 kb
Host smart-9ec3ab85-f2db-4b3d-9e94-41a02ce388ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171989344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2171989344
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1615707668
Short name T62
Test name
Test status
Simulation time 1939595247 ps
CPU time 6.35 seconds
Started Apr 30 01:37:09 PM PDT 24
Finished Apr 30 01:37:16 PM PDT 24
Peak memory 217236 kb
Host smart-97a40b61-1acb-444e-b761-7a90ea783bfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615707668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
615707668
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3830495048
Short name T853
Test name
Test status
Simulation time 1434894253 ps
CPU time 10.73 seconds
Started Apr 30 01:37:09 PM PDT 24
Finished Apr 30 01:37:20 PM PDT 24
Peak memory 217752 kb
Host smart-2eb02fd5-9e33-40e4-a052-edaff3f06cf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830495048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3830495048
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3904095429
Short name T85
Test name
Test status
Simulation time 4321173849 ps
CPU time 30.96 seconds
Started Apr 30 01:37:08 PM PDT 24
Finished Apr 30 01:37:40 PM PDT 24
Peak memory 213964 kb
Host smart-88445d25-6da3-4ba3-b472-44a178efedb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904095429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3904095429
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2651885551
Short name T190
Test name
Test status
Simulation time 85615985 ps
CPU time 2.67 seconds
Started Apr 30 01:37:10 PM PDT 24
Finished Apr 30 01:37:13 PM PDT 24
Peak memory 212452 kb
Host smart-b845cb8f-3eee-463a-88d1-64c2020b8e4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651885551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2651885551
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2631497862
Short name T709
Test name
Test status
Simulation time 5487447973 ps
CPU time 33.03 seconds
Started Apr 30 01:37:11 PM PDT 24
Finished Apr 30 01:37:45 PM PDT 24
Peak memory 267236 kb
Host smart-bc57cdc6-15a2-4cf8-81ab-c8991aca1d62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631497862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2631497862
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2972307194
Short name T547
Test name
Test status
Simulation time 1715726559 ps
CPU time 37.95 seconds
Started Apr 30 01:37:13 PM PDT 24
Finished Apr 30 01:37:52 PM PDT 24
Peak memory 250780 kb
Host smart-e6a7c0c5-47d1-4ff9-b35e-a22e062f0c05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972307194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2972307194
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3953002032
Short name T711
Test name
Test status
Simulation time 242829277 ps
CPU time 3.16 seconds
Started Apr 30 01:37:08 PM PDT 24
Finished Apr 30 01:37:12 PM PDT 24
Peak memory 217836 kb
Host smart-f689e019-e230-4daa-ac44-d769433c1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953002032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3953002032
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2207140739
Short name T569
Test name
Test status
Simulation time 325049774 ps
CPU time 7.26 seconds
Started Apr 30 01:37:13 PM PDT 24
Finished Apr 30 01:37:21 PM PDT 24
Peak memory 217840 kb
Host smart-908325a9-f782-47da-8824-564259cce932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207140739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2207140739
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3737484175
Short name T309
Test name
Test status
Simulation time 1292358701 ps
CPU time 11.27 seconds
Started Apr 30 01:37:09 PM PDT 24
Finished Apr 30 01:37:21 PM PDT 24
Peak memory 226024 kb
Host smart-e3bd77ab-452b-404a-9312-142a7cd29de3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737484175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3737484175
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2057104615
Short name T646
Test name
Test status
Simulation time 306908038 ps
CPU time 11.87 seconds
Started Apr 30 01:37:18 PM PDT 24
Finished Apr 30 01:37:30 PM PDT 24
Peak memory 217844 kb
Host smart-00b3f42c-44d2-49fb-98cd-2ed4a0578e58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057104615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2057104615
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1042464687
Short name T156
Test name
Test status
Simulation time 950285980 ps
CPU time 7.11 seconds
Started Apr 30 01:37:11 PM PDT 24
Finished Apr 30 01:37:18 PM PDT 24
Peak memory 217768 kb
Host smart-a6d52d8d-9a65-4ce7-82f9-2f0b2e762ce7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042464687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
042464687
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3068603854
Short name T619
Test name
Test status
Simulation time 655317756 ps
CPU time 9.19 seconds
Started Apr 30 01:37:13 PM PDT 24
Finished Apr 30 01:37:23 PM PDT 24
Peak memory 217908 kb
Host smart-54ce67c0-a7d5-48c6-bb40-abaeb517e9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068603854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3068603854
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.979717528
Short name T246
Test name
Test status
Simulation time 75796734 ps
CPU time 4.71 seconds
Started Apr 30 01:37:04 PM PDT 24
Finished Apr 30 01:37:09 PM PDT 24
Peak memory 217640 kb
Host smart-ef07a97a-3711-4376-a002-c83010f2dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979717528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.979717528
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3937428214
Short name T534
Test name
Test status
Simulation time 89689171 ps
CPU time 2.4 seconds
Started Apr 30 01:37:14 PM PDT 24
Finished Apr 30 01:37:16 PM PDT 24
Peak memory 217780 kb
Host smart-22d1f58d-a6d4-40e2-bfb6-63bb26787b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937428214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3937428214
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2928563614
Short name T431
Test name
Test status
Simulation time 43104943810 ps
CPU time 192.95 seconds
Started Apr 30 01:37:16 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 276320 kb
Host smart-25f193fc-21c6-4f8a-a764-fa18a536c671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928563614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2928563614
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.631891585
Short name T130
Test name
Test status
Simulation time 72220202233 ps
CPU time 627.83 seconds
Started Apr 30 01:37:16 PM PDT 24
Finished Apr 30 01:47:45 PM PDT 24
Peak memory 300136 kb
Host smart-d6c01e11-1ecb-41a0-ae82-9e01ddd4010d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=631891585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.631891585
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1590876202
Short name T574
Test name
Test status
Simulation time 89573014 ps
CPU time 1.31 seconds
Started Apr 30 01:37:02 PM PDT 24
Finished Apr 30 01:37:03 PM PDT 24
Peak memory 212628 kb
Host smart-eb609dcf-8262-4277-bac9-48c35d568cdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590876202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1590876202
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1231737276
Short name T296
Test name
Test status
Simulation time 27519999 ps
CPU time 1.02 seconds
Started Apr 30 01:38:18 PM PDT 24
Finished Apr 30 01:38:19 PM PDT 24
Peak memory 209432 kb
Host smart-4fac5b6a-eec6-4351-8358-b2da2d0c20a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231737276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1231737276
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.335918570
Short name T84
Test name
Test status
Simulation time 457299060 ps
CPU time 11.16 seconds
Started Apr 30 01:38:11 PM PDT 24
Finished Apr 30 01:38:23 PM PDT 24
Peak memory 225936 kb
Host smart-c5661c24-d904-4264-a56c-c797c0564c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335918570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.335918570
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2570863292
Short name T282
Test name
Test status
Simulation time 605872899 ps
CPU time 6.2 seconds
Started Apr 30 01:38:07 PM PDT 24
Finished Apr 30 01:38:14 PM PDT 24
Peak memory 209340 kb
Host smart-545b019c-6a71-453a-9adc-2248a67f15d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570863292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2570863292
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1523509360
Short name T313
Test name
Test status
Simulation time 12264948719 ps
CPU time 37.05 seconds
Started Apr 30 01:38:07 PM PDT 24
Finished Apr 30 01:38:45 PM PDT 24
Peak memory 218444 kb
Host smart-cb18bb6f-5309-42a6-89b0-9b9180f948ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523509360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1523509360
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1918362554
Short name T222
Test name
Test status
Simulation time 312046644 ps
CPU time 6.31 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:15 PM PDT 24
Peak memory 217748 kb
Host smart-6799afd5-f04b-4024-8c44-d89d811920e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918362554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1918362554
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3467041516
Short name T76
Test name
Test status
Simulation time 851925740 ps
CPU time 11.61 seconds
Started Apr 30 01:38:07 PM PDT 24
Finished Apr 30 01:38:20 PM PDT 24
Peak memory 213544 kb
Host smart-851e6fae-4c45-4fbc-883c-6b8540437b50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467041516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3467041516
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2972965187
Short name T266
Test name
Test status
Simulation time 11992358888 ps
CPU time 97.92 seconds
Started Apr 30 01:38:09 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 283192 kb
Host smart-9daedf92-d42a-49e1-b409-87bef7e85a75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972965187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2972965187
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2292492880
Short name T368
Test name
Test status
Simulation time 5509682970 ps
CPU time 23.09 seconds
Started Apr 30 01:38:11 PM PDT 24
Finished Apr 30 01:38:35 PM PDT 24
Peak memory 250864 kb
Host smart-22f9d736-3963-40c9-a411-53bc30312ecc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292492880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2292492880
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.201819385
Short name T307
Test name
Test status
Simulation time 75081627 ps
CPU time 1.66 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:11 PM PDT 24
Peak memory 217848 kb
Host smart-071e673c-58bf-4d70-884a-c954ef22e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201819385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.201819385
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.466965656
Short name T38
Test name
Test status
Simulation time 328084147 ps
CPU time 16.21 seconds
Started Apr 30 01:38:06 PM PDT 24
Finished Apr 30 01:38:23 PM PDT 24
Peak memory 218764 kb
Host smart-92ad8d24-622b-428d-a06b-55c896d1186c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466965656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.466965656
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1675468528
Short name T354
Test name
Test status
Simulation time 839908854 ps
CPU time 9.24 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:19 PM PDT 24
Peak memory 217844 kb
Host smart-bfa0d6a9-6ab8-4a05-aba5-d6e214b21a95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675468528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1675468528
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1760563214
Short name T456
Test name
Test status
Simulation time 380406307 ps
CPU time 13.58 seconds
Started Apr 30 01:38:10 PM PDT 24
Finished Apr 30 01:38:24 PM PDT 24
Peak memory 217828 kb
Host smart-e89a9914-7152-4179-b8b0-b1b52848e793
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760563214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1760563214
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1847830071
Short name T50
Test name
Test status
Simulation time 356657955 ps
CPU time 9.1 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:18 PM PDT 24
Peak memory 217876 kb
Host smart-58084c5d-c3da-4436-8b27-86098998a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847830071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1847830071
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.290757013
Short name T620
Test name
Test status
Simulation time 97390361 ps
CPU time 1.55 seconds
Started Apr 30 01:38:09 PM PDT 24
Finished Apr 30 01:38:11 PM PDT 24
Peak memory 213508 kb
Host smart-faf2767a-5992-4a8b-989a-b6e6106d7a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290757013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.290757013
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1705104735
Short name T767
Test name
Test status
Simulation time 547669860 ps
CPU time 30.46 seconds
Started Apr 30 01:38:07 PM PDT 24
Finished Apr 30 01:38:39 PM PDT 24
Peak memory 250740 kb
Host smart-e4c6811f-4478-4e74-9e36-e02aef7ace58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705104735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1705104735
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2514886819
Short name T741
Test name
Test status
Simulation time 275459547 ps
CPU time 6.19 seconds
Started Apr 30 01:38:09 PM PDT 24
Finished Apr 30 01:38:17 PM PDT 24
Peak memory 246188 kb
Host smart-63fd396e-82fe-49c3-9aa3-5c0306c1bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514886819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2514886819
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.815601625
Short name T502
Test name
Test status
Simulation time 15199033901 ps
CPU time 97.56 seconds
Started Apr 30 01:38:10 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 282808 kb
Host smart-88aaec9e-6537-41a9-a8ab-09d8f923353d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815601625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.815601625
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2240007401
Short name T273
Test name
Test status
Simulation time 86706103 ps
CPU time 0.88 seconds
Started Apr 30 01:38:11 PM PDT 24
Finished Apr 30 01:38:12 PM PDT 24
Peak memory 211476 kb
Host smart-e7f36747-a336-4075-995d-742dfa6678d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240007401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2240007401
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.228314933
Short name T7
Test name
Test status
Simulation time 17373230 ps
CPU time 1.16 seconds
Started Apr 30 01:38:14 PM PDT 24
Finished Apr 30 01:38:16 PM PDT 24
Peak memory 209432 kb
Host smart-e614fb3a-bdd8-4299-8398-ada0bc376b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228314933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.228314933
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1913879510
Short name T188
Test name
Test status
Simulation time 353499452 ps
CPU time 12.92 seconds
Started Apr 30 01:38:19 PM PDT 24
Finished Apr 30 01:38:32 PM PDT 24
Peak memory 226112 kb
Host smart-43486254-0ebc-4bd1-b473-6cc73317f199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913879510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1913879510
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2177885301
Short name T750
Test name
Test status
Simulation time 278630780 ps
CPU time 7.63 seconds
Started Apr 30 01:38:18 PM PDT 24
Finished Apr 30 01:38:26 PM PDT 24
Peak memory 217080 kb
Host smart-7b0871e5-bb40-40eb-914d-c09e9e4baaf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177885301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2177885301
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2008705384
Short name T668
Test name
Test status
Simulation time 4185774562 ps
CPU time 18.23 seconds
Started Apr 30 01:38:17 PM PDT 24
Finished Apr 30 01:38:35 PM PDT 24
Peak memory 217916 kb
Host smart-2354d206-0501-4b8e-b33c-d1cf71631407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008705384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2008705384
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2768336645
Short name T87
Test name
Test status
Simulation time 5488214958 ps
CPU time 8.16 seconds
Started Apr 30 01:38:13 PM PDT 24
Finished Apr 30 01:38:21 PM PDT 24
Peak memory 217820 kb
Host smart-9737c5b0-1487-439e-b18d-8d42ba4b6421
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768336645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2768336645
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2443447217
Short name T527
Test name
Test status
Simulation time 636738585 ps
CPU time 7.64 seconds
Started Apr 30 01:38:16 PM PDT 24
Finished Apr 30 01:38:24 PM PDT 24
Peak memory 213548 kb
Host smart-12d73f49-b37a-40f5-8a87-0e01080888c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443447217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2443447217
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2777562730
Short name T858
Test name
Test status
Simulation time 1701233424 ps
CPU time 44.95 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:39:00 PM PDT 24
Peak memory 271756 kb
Host smart-54fcfd69-05b8-426c-a801-0252b7372745
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777562730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2777562730
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4188498967
Short name T193
Test name
Test status
Simulation time 377560625 ps
CPU time 8.4 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:38:24 PM PDT 24
Peak memory 222688 kb
Host smart-f3218eaf-0432-41b3-bc2d-e06dc53505d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188498967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4188498967
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.984191162
Short name T621
Test name
Test status
Simulation time 57508859 ps
CPU time 3.31 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:38:19 PM PDT 24
Peak memory 217836 kb
Host smart-4f6e64d1-a0ed-4cff-9e97-cd8bf3382d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984191162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.984191162
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2351497248
Short name T337
Test name
Test status
Simulation time 179167386 ps
CPU time 8.16 seconds
Started Apr 30 01:38:14 PM PDT 24
Finished Apr 30 01:38:23 PM PDT 24
Peak memory 218812 kb
Host smart-09f70136-df55-4a21-a0f6-76a3e8fc119c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351497248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2351497248
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3381473798
Short name T496
Test name
Test status
Simulation time 345459512 ps
CPU time 10.9 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:38:26 PM PDT 24
Peak memory 217812 kb
Host smart-bee5b39d-a52f-4a95-9285-aa2211ecc582
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381473798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3381473798
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1509404575
Short name T402
Test name
Test status
Simulation time 267231091 ps
CPU time 8.97 seconds
Started Apr 30 01:38:18 PM PDT 24
Finished Apr 30 01:38:27 PM PDT 24
Peak memory 217796 kb
Host smart-0ee6403f-29ce-445d-b47f-3f29931737f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509404575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1509404575
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2153851242
Short name T277
Test name
Test status
Simulation time 205222041 ps
CPU time 7.85 seconds
Started Apr 30 01:38:17 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 217836 kb
Host smart-86561404-74b3-4204-a1de-a467886a72c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153851242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2153851242
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.751878889
Short name T782
Test name
Test status
Simulation time 39408222 ps
CPU time 2.64 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:38:18 PM PDT 24
Peak memory 213900 kb
Host smart-ebf16388-16cb-4fa9-b2a4-49f29146f147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751878889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.751878889
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3186536061
Short name T360
Test name
Test status
Simulation time 220438906 ps
CPU time 18.31 seconds
Started Apr 30 01:38:18 PM PDT 24
Finished Apr 30 01:38:37 PM PDT 24
Peak memory 250812 kb
Host smart-94a5a050-e8e8-4f26-9d36-c7aa7e906b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186536061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3186536061
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4234384494
Short name T148
Test name
Test status
Simulation time 69645664 ps
CPU time 10.22 seconds
Started Apr 30 01:38:14 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 250840 kb
Host smart-1590822a-fb8d-41dd-b909-98d8ecb566e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234384494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4234384494
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1477056993
Short name T455
Test name
Test status
Simulation time 82999310948 ps
CPU time 201.38 seconds
Started Apr 30 01:38:16 PM PDT 24
Finished Apr 30 01:41:38 PM PDT 24
Peak memory 283636 kb
Host smart-d1482324-0a32-4e79-be33-dad1ec2f0677
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477056993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1477056993
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3399358520
Short name T128
Test name
Test status
Simulation time 10155073255 ps
CPU time 316.93 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:43:33 PM PDT 24
Peak memory 389236 kb
Host smart-46cec514-263a-4036-85cc-935932f9b5ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3399358520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3399358520
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4292968091
Short name T773
Test name
Test status
Simulation time 19041400 ps
CPU time 0.8 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:38:16 PM PDT 24
Peak memory 208424 kb
Host smart-987374df-71de-42cd-ae04-87d6bae6ba36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292968091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4292968091
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.682462409
Short name T81
Test name
Test status
Simulation time 67702328 ps
CPU time 1.53 seconds
Started Apr 30 01:38:22 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 209432 kb
Host smart-b3dc18a9-b644-4986-9cc0-5029fa4422d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682462409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.682462409
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3287104580
Short name T720
Test name
Test status
Simulation time 3036352465 ps
CPU time 14.81 seconds
Started Apr 30 01:38:17 PM PDT 24
Finished Apr 30 01:38:32 PM PDT 24
Peak memory 225976 kb
Host smart-99a6b38e-ff3f-408b-97ba-752afbbe58bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287104580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3287104580
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3731717568
Short name T320
Test name
Test status
Simulation time 131890360 ps
CPU time 2.11 seconds
Started Apr 30 01:38:16 PM PDT 24
Finished Apr 30 01:38:18 PM PDT 24
Peak memory 209372 kb
Host smart-6fbf2d51-2a22-4909-9384-626dc1da9b09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731717568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3731717568
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2335515327
Short name T408
Test name
Test status
Simulation time 1436139131 ps
CPU time 42.31 seconds
Started Apr 30 01:38:18 PM PDT 24
Finished Apr 30 01:39:01 PM PDT 24
Peak memory 217732 kb
Host smart-88dcc4da-13cc-4f16-aaa9-40c9d850565e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335515327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2335515327
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3819744847
Short name T342
Test name
Test status
Simulation time 582958184 ps
CPU time 9.17 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 217796 kb
Host smart-41a3a401-9961-4252-9ed9-cba2307b9332
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819744847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3819744847
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2600743087
Short name T8
Test name
Test status
Simulation time 56399296 ps
CPU time 1.4 seconds
Started Apr 30 01:38:16 PM PDT 24
Finished Apr 30 01:38:18 PM PDT 24
Peak memory 212468 kb
Host smart-1464af9f-7b9a-4aee-8890-8e5766790f45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600743087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2600743087
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.4182553167
Short name T17
Test name
Test status
Simulation time 1279286201 ps
CPU time 64.39 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:39:20 PM PDT 24
Peak memory 270244 kb
Host smart-9940f584-c324-4a4c-9b2b-46f20e06c545
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182553167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.4182553167
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4183656757
Short name T364
Test name
Test status
Simulation time 850632857 ps
CPU time 17.11 seconds
Started Apr 30 01:38:16 PM PDT 24
Finished Apr 30 01:38:34 PM PDT 24
Peak memory 250272 kb
Host smart-eb21b105-0cb2-4c9b-a74f-5c24291d258c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183656757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4183656757
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.53339227
Short name T779
Test name
Test status
Simulation time 357423969 ps
CPU time 3.03 seconds
Started Apr 30 01:38:17 PM PDT 24
Finished Apr 30 01:38:21 PM PDT 24
Peak memory 218068 kb
Host smart-056830e4-30b4-4427-a4d5-dc0b4475d140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53339227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.53339227
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.825645981
Short name T206
Test name
Test status
Simulation time 311587645 ps
CPU time 15.03 seconds
Started Apr 30 01:38:23 PM PDT 24
Finished Apr 30 01:38:38 PM PDT 24
Peak memory 225548 kb
Host smart-d9882d72-88e2-460a-b0ff-1476cf691778
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825645981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.825645981
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.824754216
Short name T701
Test name
Test status
Simulation time 1518060963 ps
CPU time 13.28 seconds
Started Apr 30 01:38:22 PM PDT 24
Finished Apr 30 01:38:36 PM PDT 24
Peak memory 217824 kb
Host smart-a7bb1f47-fb97-44df-9133-f3d23443a8f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824754216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.824754216
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1043199137
Short name T784
Test name
Test status
Simulation time 352669368 ps
CPU time 7.46 seconds
Started Apr 30 01:38:22 PM PDT 24
Finished Apr 30 01:38:30 PM PDT 24
Peak memory 217828 kb
Host smart-1b8ee3b4-3b4c-4e55-bc80-92a455c07ab5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043199137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1043199137
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3360986951
Short name T264
Test name
Test status
Simulation time 560409114 ps
CPU time 9.92 seconds
Started Apr 30 01:38:16 PM PDT 24
Finished Apr 30 01:38:26 PM PDT 24
Peak memory 224876 kb
Host smart-84908a4c-ac43-432f-afe0-67ead6af53c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360986951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3360986951
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3554080891
Short name T200
Test name
Test status
Simulation time 446810940 ps
CPU time 2.69 seconds
Started Apr 30 01:38:14 PM PDT 24
Finished Apr 30 01:38:17 PM PDT 24
Peak memory 217616 kb
Host smart-ab770a9a-f87f-4c99-924c-5d61111021c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554080891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3554080891
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2344031490
Short name T91
Test name
Test status
Simulation time 313877210 ps
CPU time 33.58 seconds
Started Apr 30 01:38:14 PM PDT 24
Finished Apr 30 01:38:48 PM PDT 24
Peak memory 250800 kb
Host smart-6bc5a5e6-e734-4cbd-b8ca-d71b3fa1c9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344031490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2344031490
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.994388383
Short name T763
Test name
Test status
Simulation time 155398628 ps
CPU time 7.98 seconds
Started Apr 30 01:38:13 PM PDT 24
Finished Apr 30 01:38:22 PM PDT 24
Peak memory 250712 kb
Host smart-9a249b90-f2c9-4b71-b9db-894227dcaef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994388383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.994388383
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2057472437
Short name T626
Test name
Test status
Simulation time 34641560362 ps
CPU time 521.02 seconds
Started Apr 30 01:38:23 PM PDT 24
Finished Apr 30 01:47:05 PM PDT 24
Peak memory 275008 kb
Host smart-3f00771d-0a48-498e-a65f-a99976974afd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057472437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2057472437
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3663813170
Short name T324
Test name
Test status
Simulation time 41901203 ps
CPU time 0.91 seconds
Started Apr 30 01:38:15 PM PDT 24
Finished Apr 30 01:38:16 PM PDT 24
Peak memory 208608 kb
Host smart-a73ea9cf-ca44-4daf-8185-9279190c71a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663813170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3663813170
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1023931790
Short name T377
Test name
Test status
Simulation time 67273249 ps
CPU time 1.25 seconds
Started Apr 30 01:38:23 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 209396 kb
Host smart-40fd1476-3263-42fe-a474-2bc14757380e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023931790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1023931790
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1130633785
Short name T392
Test name
Test status
Simulation time 2843401034 ps
CPU time 14.29 seconds
Started Apr 30 01:38:21 PM PDT 24
Finished Apr 30 01:38:36 PM PDT 24
Peak memory 217964 kb
Host smart-f8879039-3f8a-4b67-a90e-b833c5732035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130633785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1130633785
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3432066191
Short name T758
Test name
Test status
Simulation time 571185834 ps
CPU time 4.14 seconds
Started Apr 30 01:38:21 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 216832 kb
Host smart-ba7cf8ce-2b1d-4eb9-adbb-b60763b3b330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432066191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3432066191
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1333701847
Short name T83
Test name
Test status
Simulation time 17732622048 ps
CPU time 99.57 seconds
Started Apr 30 01:38:26 PM PDT 24
Finished Apr 30 01:40:06 PM PDT 24
Peak memory 218508 kb
Host smart-44513495-1ed0-4eea-8e2e-f450d0c2a0e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333701847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1333701847
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1387598184
Short name T707
Test name
Test status
Simulation time 904333414 ps
CPU time 22.73 seconds
Started Apr 30 01:38:23 PM PDT 24
Finished Apr 30 01:38:46 PM PDT 24
Peak memory 217732 kb
Host smart-464c7ef8-e665-4e29-a77e-93896ff128cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387598184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1387598184
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1072371932
Short name T532
Test name
Test status
Simulation time 987277542 ps
CPU time 7.86 seconds
Started Apr 30 01:38:21 PM PDT 24
Finished Apr 30 01:38:30 PM PDT 24
Peak memory 213580 kb
Host smart-7cc82239-7ec1-4a0a-aaad-7f187621e74a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072371932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1072371932
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.496644044
Short name T413
Test name
Test status
Simulation time 2175089065 ps
CPU time 55.54 seconds
Started Apr 30 01:38:22 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 272012 kb
Host smart-3cd8297a-8cc9-415f-a72e-2d2a14e47eaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496644044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.496644044
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1559433191
Short name T564
Test name
Test status
Simulation time 938389871 ps
CPU time 27.65 seconds
Started Apr 30 01:38:23 PM PDT 24
Finished Apr 30 01:38:51 PM PDT 24
Peak memory 221968 kb
Host smart-2a50046d-94c5-4f67-b64a-466fa41b8dc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559433191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1559433191
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.938276793
Short name T618
Test name
Test status
Simulation time 48147113 ps
CPU time 2.35 seconds
Started Apr 30 01:38:21 PM PDT 24
Finished Apr 30 01:38:24 PM PDT 24
Peak memory 217788 kb
Host smart-8ec17adc-b0e6-4d22-8368-e774648cf952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938276793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.938276793
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.936174816
Short name T599
Test name
Test status
Simulation time 236436885 ps
CPU time 9.44 seconds
Started Apr 30 01:38:27 PM PDT 24
Finished Apr 30 01:38:37 PM PDT 24
Peak memory 218832 kb
Host smart-f68ba8ec-a396-4b4c-8bfe-2c515a5163cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936174816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.936174816
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2390322509
Short name T732
Test name
Test status
Simulation time 1173405261 ps
CPU time 9.45 seconds
Started Apr 30 01:38:23 PM PDT 24
Finished Apr 30 01:38:33 PM PDT 24
Peak memory 217792 kb
Host smart-729acf13-6f2d-48ce-9bc6-fd195cbfed73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390322509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2390322509
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3045247980
Short name T682
Test name
Test status
Simulation time 818603041 ps
CPU time 10.95 seconds
Started Apr 30 01:38:23 PM PDT 24
Finished Apr 30 01:38:34 PM PDT 24
Peak memory 217852 kb
Host smart-c74773e4-048d-4845-b609-fa1f7b214619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045247980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3045247980
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1736201984
Short name T831
Test name
Test status
Simulation time 991087357 ps
CPU time 7.38 seconds
Started Apr 30 01:38:21 PM PDT 24
Finished Apr 30 01:38:29 PM PDT 24
Peak memory 217860 kb
Host smart-3b41a5f4-16b9-4a9a-8b55-750c74002487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736201984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1736201984
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2354376058
Short name T813
Test name
Test status
Simulation time 18645468 ps
CPU time 1.42 seconds
Started Apr 30 01:38:20 PM PDT 24
Finished Apr 30 01:38:22 PM PDT 24
Peak memory 213100 kb
Host smart-e6a97025-7a04-4019-815f-345f4275242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354376058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2354376058
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3826853942
Short name T705
Test name
Test status
Simulation time 404769801 ps
CPU time 36.15 seconds
Started Apr 30 01:38:22 PM PDT 24
Finished Apr 30 01:38:59 PM PDT 24
Peak memory 250800 kb
Host smart-db8d355f-baa1-4b03-97eb-b2740938fffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826853942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3826853942
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1485339294
Short name T481
Test name
Test status
Simulation time 66487081 ps
CPU time 3.31 seconds
Started Apr 30 01:38:21 PM PDT 24
Finished Apr 30 01:38:24 PM PDT 24
Peak memory 226228 kb
Host smart-4cd601ad-8208-4434-b21b-c74eb1791d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485339294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1485339294
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1112825645
Short name T609
Test name
Test status
Simulation time 6886007871 ps
CPU time 303.28 seconds
Started Apr 30 01:38:27 PM PDT 24
Finished Apr 30 01:43:31 PM PDT 24
Peak memory 250996 kb
Host smart-05dc6967-9879-46ed-a8c5-a16dabd2f9ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112825645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1112825645
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2919063072
Short name T27
Test name
Test status
Simulation time 22036550 ps
CPU time 0.92 seconds
Started Apr 30 01:38:22 PM PDT 24
Finished Apr 30 01:38:23 PM PDT 24
Peak memory 208496 kb
Host smart-ab252633-a92f-477e-9aba-1dd1ec99cd2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919063072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2919063072
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2415557378
Short name T238
Test name
Test status
Simulation time 14654242 ps
CPU time 0.88 seconds
Started Apr 30 01:38:33 PM PDT 24
Finished Apr 30 01:38:34 PM PDT 24
Peak memory 209344 kb
Host smart-0fe912a3-ab1d-41b7-b753-f446dee3baf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415557378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2415557378
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.571213527
Short name T329
Test name
Test status
Simulation time 914420247 ps
CPU time 10.87 seconds
Started Apr 30 01:38:29 PM PDT 24
Finished Apr 30 01:38:40 PM PDT 24
Peak memory 217848 kb
Host smart-b3874224-2c0b-4783-9c98-528fc81b500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571213527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.571213527
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.720426677
Short name T593
Test name
Test status
Simulation time 516923474 ps
CPU time 3.98 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:38:34 PM PDT 24
Peak memory 209412 kb
Host smart-c40b4f4b-3623-4890-87bf-f0de6b9f717e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720426677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.720426677
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1523727928
Short name T627
Test name
Test status
Simulation time 1320405553 ps
CPU time 41.01 seconds
Started Apr 30 01:38:29 PM PDT 24
Finished Apr 30 01:39:11 PM PDT 24
Peak memory 217800 kb
Host smart-ef9cc780-5253-4ecb-87d8-3ae6f17e1385
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523727928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1523727928
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.446853310
Short name T845
Test name
Test status
Simulation time 2432461087 ps
CPU time 17.13 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:49 PM PDT 24
Peak memory 217860 kb
Host smart-f77a5342-8138-4153-b852-7522e951e828
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446853310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.446853310
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.295624680
Short name T252
Test name
Test status
Simulation time 746257838 ps
CPU time 6.13 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:38:37 PM PDT 24
Peak memory 213388 kb
Host smart-7190141b-6ff2-4475-9bff-2a39c1186683
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295624680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
295624680
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2734482022
Short name T501
Test name
Test status
Simulation time 2622775135 ps
CPU time 59.12 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:39:30 PM PDT 24
Peak memory 268164 kb
Host smart-797c1c0d-d032-46df-b49c-9ea4abd6e404
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734482022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2734482022
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1778988219
Short name T695
Test name
Test status
Simulation time 1596962107 ps
CPU time 20.31 seconds
Started Apr 30 01:38:31 PM PDT 24
Finished Apr 30 01:38:51 PM PDT 24
Peak memory 250808 kb
Host smart-f6f7c824-08d2-4831-b101-e47aa5273755
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778988219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1778988219
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2926331498
Short name T855
Test name
Test status
Simulation time 452071605 ps
CPU time 2.74 seconds
Started Apr 30 01:38:31 PM PDT 24
Finished Apr 30 01:38:34 PM PDT 24
Peak memory 217892 kb
Host smart-8ce62b6b-5b9f-4181-88ff-38db4f4f42b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926331498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2926331498
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.384511469
Short name T195
Test name
Test status
Simulation time 338138983 ps
CPU time 11.52 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:44 PM PDT 24
Peak memory 225864 kb
Host smart-99059dc5-c821-4aae-b262-88b228284886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384511469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.384511469
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.586192383
Short name T196
Test name
Test status
Simulation time 272456541 ps
CPU time 9.5 seconds
Started Apr 30 01:38:29 PM PDT 24
Finished Apr 30 01:38:39 PM PDT 24
Peak memory 217800 kb
Host smart-7f93b730-3876-4652-b083-e766fdaee224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586192383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.586192383
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2738928162
Short name T410
Test name
Test status
Simulation time 880909490 ps
CPU time 6.85 seconds
Started Apr 30 01:38:29 PM PDT 24
Finished Apr 30 01:38:36 PM PDT 24
Peak memory 217920 kb
Host smart-1b1f84a4-3572-4328-afdf-a2c1e09cef07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738928162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2738928162
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.934173803
Short name T473
Test name
Test status
Simulation time 1341054350 ps
CPU time 6.5 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:39 PM PDT 24
Peak memory 217908 kb
Host smart-21e0620c-2991-4ea5-9883-835dbd176454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934173803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.934173803
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3830943304
Short name T616
Test name
Test status
Simulation time 85875317 ps
CPU time 2.18 seconds
Started Apr 30 01:38:26 PM PDT 24
Finished Apr 30 01:38:29 PM PDT 24
Peak memory 213580 kb
Host smart-941ef028-ce45-4b7d-907a-b5ee712e1e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830943304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3830943304
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.756215206
Short name T477
Test name
Test status
Simulation time 1356157904 ps
CPU time 32.16 seconds
Started Apr 30 01:38:22 PM PDT 24
Finished Apr 30 01:38:55 PM PDT 24
Peak memory 250812 kb
Host smart-4e7d23e8-d582-47c0-84d8-a7bf748a872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756215206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.756215206
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3282151988
Short name T774
Test name
Test status
Simulation time 73142925 ps
CPU time 8.4 seconds
Started Apr 30 01:38:33 PM PDT 24
Finished Apr 30 01:38:41 PM PDT 24
Peak memory 246120 kb
Host smart-351f6c1f-b721-47b1-a67e-6573512aac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282151988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3282151988
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1616829501
Short name T629
Test name
Test status
Simulation time 41633532949 ps
CPU time 577.6 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:48:08 PM PDT 24
Peak memory 272668 kb
Host smart-04493aa2-d0bd-407f-9867-5782323fd327
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616829501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1616829501
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3814025031
Short name T683
Test name
Test status
Simulation time 11521770 ps
CPU time 0.84 seconds
Started Apr 30 01:38:25 PM PDT 24
Finished Apr 30 01:38:27 PM PDT 24
Peak memory 207876 kb
Host smart-f2da1bdb-cec6-429f-8a47-03d72eedbe25
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814025031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3814025031
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3048946865
Short name T652
Test name
Test status
Simulation time 15265524 ps
CPU time 0.86 seconds
Started Apr 30 01:38:39 PM PDT 24
Finished Apr 30 01:38:40 PM PDT 24
Peak memory 209316 kb
Host smart-f6092817-1d47-48d4-9154-37ee24d143f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048946865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3048946865
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.540683006
Short name T16
Test name
Test status
Simulation time 254017328 ps
CPU time 11.83 seconds
Started Apr 30 01:38:31 PM PDT 24
Finished Apr 30 01:38:43 PM PDT 24
Peak memory 225952 kb
Host smart-a1528b49-4dd2-402d-a0a7-b7959e7d076d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540683006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.540683006
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1122331035
Short name T5
Test name
Test status
Simulation time 192647138 ps
CPU time 2.68 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:35 PM PDT 24
Peak memory 209424 kb
Host smart-e5a5eb1a-b8e3-4916-ae03-07944bb6ad7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122331035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1122331035
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1590708422
Short name T742
Test name
Test status
Simulation time 33759895834 ps
CPU time 47.86 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:39:19 PM PDT 24
Peak memory 218848 kb
Host smart-628b43d4-7dc3-4f15-bceb-df16b14ebe41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590708422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1590708422
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4069357028
Short name T161
Test name
Test status
Simulation time 1320837852 ps
CPU time 6.03 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:39 PM PDT 24
Peak memory 217808 kb
Host smart-d2e1b636-50d3-4419-8beb-237679e954ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069357028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4069357028
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3418518246
Short name T478
Test name
Test status
Simulation time 380095318 ps
CPU time 11.03 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:44 PM PDT 24
Peak memory 213476 kb
Host smart-eec9b00c-cf85-476c-a5cb-bc323bf23d4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418518246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3418518246
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.475398409
Short name T840
Test name
Test status
Simulation time 6765187692 ps
CPU time 56.81 seconds
Started Apr 30 01:38:31 PM PDT 24
Finished Apr 30 01:39:28 PM PDT 24
Peak memory 268324 kb
Host smart-ea8e32aa-4a45-4535-990a-e12ad9c85307
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475398409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.475398409
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3970739451
Short name T224
Test name
Test status
Simulation time 603723477 ps
CPU time 12.7 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:45 PM PDT 24
Peak memory 247176 kb
Host smart-e44dd831-a79a-4f51-9ab4-31361e18b00f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970739451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3970739451
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.568239556
Short name T259
Test name
Test status
Simulation time 28741005 ps
CPU time 2.12 seconds
Started Apr 30 01:38:28 PM PDT 24
Finished Apr 30 01:38:31 PM PDT 24
Peak memory 217796 kb
Host smart-7c4f2b02-d613-46e5-906b-416f9d87d1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568239556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.568239556
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1298210144
Short name T341
Test name
Test status
Simulation time 224396231 ps
CPU time 10.36 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:38:41 PM PDT 24
Peak memory 225980 kb
Host smart-0c09c4da-37b8-433d-a3b5-10d3fe0088d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298210144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1298210144
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.448827753
Short name T591
Test name
Test status
Simulation time 1220830581 ps
CPU time 9.91 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:43 PM PDT 24
Peak memory 217848 kb
Host smart-ef5dd63d-c97e-4745-8fe5-2af9ca51ba0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448827753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.448827753
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.941646086
Short name T719
Test name
Test status
Simulation time 813468283 ps
CPU time 10.13 seconds
Started Apr 30 01:38:29 PM PDT 24
Finished Apr 30 01:38:39 PM PDT 24
Peak memory 217892 kb
Host smart-80d27821-fa4a-4dba-ab64-9085deb2c3b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941646086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.941646086
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3875667974
Short name T495
Test name
Test status
Simulation time 478710376 ps
CPU time 10.46 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:38:41 PM PDT 24
Peak memory 225848 kb
Host smart-1b21ab24-2880-4061-af4e-59d01755c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875667974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3875667974
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2971397778
Short name T56
Test name
Test status
Simulation time 113361007 ps
CPU time 2.17 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:38:32 PM PDT 24
Peak memory 213736 kb
Host smart-11667dab-1461-4485-8913-c9ea532bbe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971397778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2971397778
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1782667397
Short name T436
Test name
Test status
Simulation time 1249505687 ps
CPU time 19.82 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:52 PM PDT 24
Peak memory 248908 kb
Host smart-4b802d29-e5a6-40a4-b9f6-3252f6b956a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782667397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1782667397
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1335059133
Short name T649
Test name
Test status
Simulation time 95473786 ps
CPU time 3.07 seconds
Started Apr 30 01:38:30 PM PDT 24
Finished Apr 30 01:38:34 PM PDT 24
Peak memory 226244 kb
Host smart-baea6162-99e3-4ca0-a035-053cf9c362a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335059133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1335059133
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.268424481
Short name T35
Test name
Test status
Simulation time 19487518832 ps
CPU time 100.89 seconds
Started Apr 30 01:38:33 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 280612 kb
Host smart-8f63c03c-6522-46e7-ac5f-b2f6590bf82d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268424481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.268424481
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3279508263
Short name T452
Test name
Test status
Simulation time 41799139 ps
CPU time 0.79 seconds
Started Apr 30 01:38:32 PM PDT 24
Finished Apr 30 01:38:34 PM PDT 24
Peak memory 208500 kb
Host smart-3b2e821a-3d3b-4bef-a5c7-84d09f6fccf0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279508263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3279508263
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.557801039
Short name T388
Test name
Test status
Simulation time 50645425 ps
CPU time 1.1 seconds
Started Apr 30 01:38:37 PM PDT 24
Finished Apr 30 01:38:39 PM PDT 24
Peak memory 209388 kb
Host smart-4dd981a0-daeb-45e5-bf40-46111ffeaf5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557801039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.557801039
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2004747404
Short name T262
Test name
Test status
Simulation time 1030150385 ps
CPU time 9.88 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:38:52 PM PDT 24
Peak memory 217852 kb
Host smart-cd662771-50bf-4280-b483-0c04c90d70ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004747404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2004747404
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.118141621
Short name T625
Test name
Test status
Simulation time 1870078784 ps
CPU time 13.55 seconds
Started Apr 30 01:38:39 PM PDT 24
Finished Apr 30 01:38:53 PM PDT 24
Peak memory 209368 kb
Host smart-42ae8647-f0fa-4a85-a83b-e9f24f7c41b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118141621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.118141621
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3316449555
Short name T808
Test name
Test status
Simulation time 1727702199 ps
CPU time 29.58 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 217772 kb
Host smart-2759b309-9d24-4c75-8dbc-0b67b00b08f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316449555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3316449555
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1038994704
Short name T834
Test name
Test status
Simulation time 496649595 ps
CPU time 3.18 seconds
Started Apr 30 01:38:39 PM PDT 24
Finished Apr 30 01:38:43 PM PDT 24
Peak memory 217732 kb
Host smart-032bd29e-8b15-4e12-aca7-9c39e00d511d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038994704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1038994704
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2312190106
Short name T685
Test name
Test status
Simulation time 816585804 ps
CPU time 5.71 seconds
Started Apr 30 01:38:38 PM PDT 24
Finished Apr 30 01:38:44 PM PDT 24
Peak memory 213180 kb
Host smart-f5687313-3843-4bba-8eef-e7f65e505312
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312190106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2312190106
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2404992312
Short name T651
Test name
Test status
Simulation time 3159580455 ps
CPU time 36.66 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:39:19 PM PDT 24
Peak memory 276696 kb
Host smart-a46fb3d7-d0b8-41f1-9a8b-e44ae82a9513
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404992312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2404992312
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1519769051
Short name T399
Test name
Test status
Simulation time 1281821447 ps
CPU time 11.74 seconds
Started Apr 30 01:38:39 PM PDT 24
Finished Apr 30 01:38:51 PM PDT 24
Peak memory 250696 kb
Host smart-308410cd-b85c-41d7-a697-2b308321aa79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519769051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1519769051
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3660827974
Short name T221
Test name
Test status
Simulation time 207174857 ps
CPU time 2.07 seconds
Started Apr 30 01:38:43 PM PDT 24
Finished Apr 30 01:38:45 PM PDT 24
Peak memory 217804 kb
Host smart-293140d2-693b-4df3-8b84-4c82ce8b806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660827974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3660827974
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1141164205
Short name T215
Test name
Test status
Simulation time 319290736 ps
CPU time 12.06 seconds
Started Apr 30 01:38:40 PM PDT 24
Finished Apr 30 01:38:53 PM PDT 24
Peak memory 218744 kb
Host smart-a574f356-4566-4bcc-aef5-11e6886acdb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141164205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1141164205
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3590095654
Short name T210
Test name
Test status
Simulation time 1367723045 ps
CPU time 33.71 seconds
Started Apr 30 01:38:40 PM PDT 24
Finished Apr 30 01:39:14 PM PDT 24
Peak memory 217792 kb
Host smart-28605807-282d-4239-9f83-a94d9e05a6d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590095654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3590095654
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4025050756
Short name T526
Test name
Test status
Simulation time 463925711 ps
CPU time 9.86 seconds
Started Apr 30 01:38:41 PM PDT 24
Finished Apr 30 01:38:51 PM PDT 24
Peak memory 217892 kb
Host smart-f1a14a83-44a8-4b2a-88dd-f76222c9946e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025050756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4025050756
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.324901999
Short name T469
Test name
Test status
Simulation time 392320467 ps
CPU time 11.23 seconds
Started Apr 30 01:38:41 PM PDT 24
Finished Apr 30 01:38:53 PM PDT 24
Peak memory 217916 kb
Host smart-e0a55ea5-e873-41e7-9ffd-9fb5c9c7d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324901999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.324901999
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.115451282
Short name T820
Test name
Test status
Simulation time 52469930 ps
CPU time 1.08 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:38:44 PM PDT 24
Peak memory 213124 kb
Host smart-78a6ba30-55f7-4a38-ae93-3fa524f87f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115451282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.115451282
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4007196434
Short name T419
Test name
Test status
Simulation time 1374740219 ps
CPU time 25.77 seconds
Started Apr 30 01:38:41 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 250404 kb
Host smart-fcac59a1-e8f2-40ce-aa5b-8d3df1653c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007196434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4007196434
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.238977745
Short name T690
Test name
Test status
Simulation time 286347082 ps
CPU time 6.48 seconds
Started Apr 30 01:38:40 PM PDT 24
Finished Apr 30 01:38:47 PM PDT 24
Peak memory 250448 kb
Host smart-df0f03e4-f114-4d4d-b9c3-d4bf19f5956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238977745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.238977745
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3532045780
Short name T672
Test name
Test status
Simulation time 3420181886 ps
CPU time 18.64 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:39:01 PM PDT 24
Peak memory 250936 kb
Host smart-5d6203ba-d8ac-4d88-b810-56e3a434e22a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532045780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3532045780
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3477178314
Short name T129
Test name
Test status
Simulation time 12922458056 ps
CPU time 168.84 seconds
Started Apr 30 01:38:41 PM PDT 24
Finished Apr 30 01:41:31 PM PDT 24
Peak memory 268656 kb
Host smart-7c5fe94d-9cb7-4ee7-b75a-0fb6a1f7a854
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3477178314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3477178314
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3347688846
Short name T310
Test name
Test status
Simulation time 53438724 ps
CPU time 0.95 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:38:43 PM PDT 24
Peak memory 211428 kb
Host smart-1b284f71-4b2d-4230-b220-b7b09a098a75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347688846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3347688846
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3242862004
Short name T807
Test name
Test status
Simulation time 15499338 ps
CPU time 0.86 seconds
Started Apr 30 01:38:55 PM PDT 24
Finished Apr 30 01:38:56 PM PDT 24
Peak memory 209360 kb
Host smart-e4961efa-84e4-4a7a-abb6-cb3198cd15f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242862004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3242862004
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3287044588
Short name T226
Test name
Test status
Simulation time 2251082606 ps
CPU time 12.64 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:38:55 PM PDT 24
Peak memory 217908 kb
Host smart-ecda22d8-bf2e-4f4a-848e-0917db17bba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287044588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3287044588
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.301769912
Short name T362
Test name
Test status
Simulation time 87054533 ps
CPU time 1.82 seconds
Started Apr 30 01:38:40 PM PDT 24
Finished Apr 30 01:38:43 PM PDT 24
Peak memory 209432 kb
Host smart-aca14ddb-912e-4813-b013-47da06eaea6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301769912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.301769912
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2994381417
Short name T150
Test name
Test status
Simulation time 12477413814 ps
CPU time 33.11 seconds
Started Apr 30 01:38:41 PM PDT 24
Finished Apr 30 01:39:14 PM PDT 24
Peak memory 218260 kb
Host smart-37ce8233-4f4f-40c1-bba1-c13151b6ec5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994381417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2994381417
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2180784652
Short name T300
Test name
Test status
Simulation time 537569451 ps
CPU time 6.96 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:38:50 PM PDT 24
Peak memory 217820 kb
Host smart-d582a662-d592-4428-87f4-93d9faa052c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180784652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2180784652
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1048339715
Short name T474
Test name
Test status
Simulation time 467363541 ps
CPU time 11.34 seconds
Started Apr 30 01:38:40 PM PDT 24
Finished Apr 30 01:38:52 PM PDT 24
Peak memory 213440 kb
Host smart-fb93418d-89b2-444e-aba6-77e2290df94b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048339715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1048339715
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.250143094
Short name T791
Test name
Test status
Simulation time 3972004866 ps
CPU time 77.16 seconds
Started Apr 30 01:38:43 PM PDT 24
Finished Apr 30 01:40:01 PM PDT 24
Peak memory 279868 kb
Host smart-10ceeb14-44e7-49b1-882c-adbd724585c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250143094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.250143094
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1708969657
Short name T242
Test name
Test status
Simulation time 2821909065 ps
CPU time 23.47 seconds
Started Apr 30 01:38:42 PM PDT 24
Finished Apr 30 01:39:06 PM PDT 24
Peak memory 248952 kb
Host smart-945e1c11-c25f-43b0-85a5-dd8e9d8d5f5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708969657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1708969657
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2648294384
Short name T565
Test name
Test status
Simulation time 37258537 ps
CPU time 2.56 seconds
Started Apr 30 01:38:38 PM PDT 24
Finished Apr 30 01:38:41 PM PDT 24
Peak memory 217828 kb
Host smart-c15d7123-0fd2-4264-96dd-61576dd0b20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648294384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2648294384
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3196701339
Short name T503
Test name
Test status
Simulation time 4195276282 ps
CPU time 10.5 seconds
Started Apr 30 01:38:41 PM PDT 24
Finished Apr 30 01:38:52 PM PDT 24
Peak memory 226072 kb
Host smart-77d3428e-9354-4aa9-875c-579a36946ccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196701339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3196701339
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.352811014
Short name T101
Test name
Test status
Simulation time 10858418728 ps
CPU time 25.26 seconds
Started Apr 30 01:38:37 PM PDT 24
Finished Apr 30 01:39:03 PM PDT 24
Peak memory 218008 kb
Host smart-241cfc1d-030b-48fc-9952-721e8d75c8a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352811014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.352811014
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2258103646
Short name T464
Test name
Test status
Simulation time 234955783 ps
CPU time 9.9 seconds
Started Apr 30 01:38:43 PM PDT 24
Finished Apr 30 01:38:53 PM PDT 24
Peak memory 217888 kb
Host smart-d2736dc2-d551-45e6-95cc-88f19ff176bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258103646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2258103646
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.350672704
Short name T294
Test name
Test status
Simulation time 1107147208 ps
CPU time 12.15 seconds
Started Apr 30 01:38:43 PM PDT 24
Finished Apr 30 01:38:55 PM PDT 24
Peak memory 225912 kb
Host smart-cca1a068-1ab5-4cbd-b135-94d7dce764eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350672704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.350672704
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2300555842
Short name T546
Test name
Test status
Simulation time 60101212 ps
CPU time 3.21 seconds
Started Apr 30 01:38:43 PM PDT 24
Finished Apr 30 01:38:46 PM PDT 24
Peak memory 213796 kb
Host smart-8577db28-f6ce-4411-a700-2903cfec57bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300555842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2300555842
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3661133304
Short name T147
Test name
Test status
Simulation time 789380284 ps
CPU time 24.62 seconds
Started Apr 30 01:38:44 PM PDT 24
Finished Apr 30 01:39:09 PM PDT 24
Peak memory 250744 kb
Host smart-ab4ddcc8-3845-4690-a35c-f92fd99e8cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661133304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3661133304
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3791196194
Short name T786
Test name
Test status
Simulation time 1080572078 ps
CPU time 8 seconds
Started Apr 30 01:38:39 PM PDT 24
Finished Apr 30 01:38:47 PM PDT 24
Peak memory 250580 kb
Host smart-50780dea-ed24-4b80-8523-14d02d73c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791196194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3791196194
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2943169466
Short name T132
Test name
Test status
Simulation time 266458431898 ps
CPU time 602.23 seconds
Started Apr 30 01:38:50 PM PDT 24
Finished Apr 30 01:48:52 PM PDT 24
Peak memory 422044 kb
Host smart-cc3bddc2-8827-4609-a56a-dc714dfa13a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2943169466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2943169466
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1413995249
Short name T422
Test name
Test status
Simulation time 27663754 ps
CPU time 0.78 seconds
Started Apr 30 01:38:43 PM PDT 24
Finished Apr 30 01:38:44 PM PDT 24
Peak memory 208600 kb
Host smart-60d5f1c2-3034-4892-a44c-22c20fde4626
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413995249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1413995249
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2893591608
Short name T510
Test name
Test status
Simulation time 60771638 ps
CPU time 0.84 seconds
Started Apr 30 01:38:48 PM PDT 24
Finished Apr 30 01:38:49 PM PDT 24
Peak memory 209360 kb
Host smart-7ad86c0c-5b6c-485c-8afb-79de99b22696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893591608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2893591608
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3229264511
Short name T518
Test name
Test status
Simulation time 294245106 ps
CPU time 11.38 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:38:59 PM PDT 24
Peak memory 217764 kb
Host smart-d0242465-5a28-44de-a11d-b5e96b2b7a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229264511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3229264511
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.611878064
Short name T4
Test name
Test status
Simulation time 396856864 ps
CPU time 5.26 seconds
Started Apr 30 01:38:48 PM PDT 24
Finished Apr 30 01:38:54 PM PDT 24
Peak memory 209408 kb
Host smart-f3c85f91-6b5c-49f4-9d86-de64a5058683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611878064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.611878064
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.355829748
Short name T509
Test name
Test status
Simulation time 4531333273 ps
CPU time 63 seconds
Started Apr 30 01:38:54 PM PDT 24
Finished Apr 30 01:39:58 PM PDT 24
Peak memory 218356 kb
Host smart-7599b9ce-2acc-450a-b9a9-6e9703246ae0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355829748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.355829748
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1689696941
Short name T644
Test name
Test status
Simulation time 829370970 ps
CPU time 4.09 seconds
Started Apr 30 01:38:49 PM PDT 24
Finished Apr 30 01:38:53 PM PDT 24
Peak memory 217664 kb
Host smart-b15938e7-adda-4bbd-a9ca-ef7a390b0c32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689696941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1689696941
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.5339209
Short name T355
Test name
Test status
Simulation time 1285831374 ps
CPU time 9.39 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:38:57 PM PDT 24
Peak memory 213692 kb
Host smart-30bfcf73-85dd-45fe-a2d1-aa63e617a597
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5339209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.5339209
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.112772050
Short name T648
Test name
Test status
Simulation time 3738025289 ps
CPU time 52.92 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:39:40 PM PDT 24
Peak memory 272828 kb
Host smart-23bc1396-ff40-4a25-a810-bfd23c674786
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112772050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.112772050
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.903415761
Short name T733
Test name
Test status
Simulation time 2097323979 ps
CPU time 8.43 seconds
Started Apr 30 01:38:51 PM PDT 24
Finished Apr 30 01:39:00 PM PDT 24
Peak memory 217720 kb
Host smart-438c7405-c038-4f78-8d36-f52ee2edec1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903415761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.903415761
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3452719781
Short name T318
Test name
Test status
Simulation time 62107332 ps
CPU time 2.4 seconds
Started Apr 30 01:38:55 PM PDT 24
Finished Apr 30 01:38:58 PM PDT 24
Peak memory 217920 kb
Host smart-583952cf-ae17-4ad6-8451-3195d1af5016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452719781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3452719781
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1850800955
Short name T545
Test name
Test status
Simulation time 553715319 ps
CPU time 21.24 seconds
Started Apr 30 01:38:50 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 225944 kb
Host smart-edc637bb-0652-4f32-8324-0f06ed3fdb72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850800955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1850800955
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.609448001
Short name T284
Test name
Test status
Simulation time 2440902256 ps
CPU time 13.39 seconds
Started Apr 30 01:38:55 PM PDT 24
Finished Apr 30 01:39:09 PM PDT 24
Peak memory 217980 kb
Host smart-12e4c6a2-2f10-4e6a-8379-5c50733d9e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609448001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.609448001
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2779844765
Short name T653
Test name
Test status
Simulation time 842484123 ps
CPU time 7.05 seconds
Started Apr 30 01:38:50 PM PDT 24
Finished Apr 30 01:38:58 PM PDT 24
Peak memory 217776 kb
Host smart-6bbde8c7-69a5-461b-be24-f3b0fdc7f576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779844765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2779844765
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2185146208
Short name T331
Test name
Test status
Simulation time 487363272 ps
CPU time 7.88 seconds
Started Apr 30 01:38:53 PM PDT 24
Finished Apr 30 01:39:01 PM PDT 24
Peak memory 217868 kb
Host smart-4aea6b88-c3e3-4d6a-abfe-1d4be84db2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185146208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2185146208
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1396754595
Short name T291
Test name
Test status
Simulation time 46888673 ps
CPU time 2.12 seconds
Started Apr 30 01:38:51 PM PDT 24
Finished Apr 30 01:38:54 PM PDT 24
Peak memory 213860 kb
Host smart-a64d034c-1705-4973-a053-ccb791263418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396754595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1396754595
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3529158905
Short name T640
Test name
Test status
Simulation time 367921285 ps
CPU time 33.88 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:39:22 PM PDT 24
Peak memory 245412 kb
Host smart-0542765a-f90b-4e36-9cd1-baa4fea9e18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529158905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3529158905
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.975785546
Short name T231
Test name
Test status
Simulation time 1095198625 ps
CPU time 6.91 seconds
Started Apr 30 01:38:55 PM PDT 24
Finished Apr 30 01:39:03 PM PDT 24
Peak memory 248724 kb
Host smart-c4aff4ad-fdd1-41cd-a1cf-62152c6f4165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975785546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.975785546
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1909230164
Short name T765
Test name
Test status
Simulation time 4330504736 ps
CPU time 86.74 seconds
Started Apr 30 01:38:53 PM PDT 24
Finished Apr 30 01:40:20 PM PDT 24
Peak memory 250860 kb
Host smart-4111bd01-6ac1-4950-99f9-eba32b64174e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909230164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1909230164
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1623141822
Short name T575
Test name
Test status
Simulation time 14143169 ps
CPU time 0.78 seconds
Started Apr 30 01:38:52 PM PDT 24
Finished Apr 30 01:38:53 PM PDT 24
Peak memory 208352 kb
Host smart-97ac761d-a46a-4b16-aeb9-42462cedac24
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623141822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1623141822
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.325062537
Short name T435
Test name
Test status
Simulation time 55810378 ps
CPU time 1.04 seconds
Started Apr 30 01:38:55 PM PDT 24
Finished Apr 30 01:38:56 PM PDT 24
Peak memory 209432 kb
Host smart-32e8ce62-6366-415c-aa7e-63e7984afd73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325062537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.325062537
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3860617237
Short name T361
Test name
Test status
Simulation time 816858987 ps
CPU time 7.58 seconds
Started Apr 30 01:38:48 PM PDT 24
Finished Apr 30 01:38:56 PM PDT 24
Peak memory 217728 kb
Host smart-12bb10e5-eee9-45e9-b41b-8871518900c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860617237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3860617237
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.4209250669
Short name T414
Test name
Test status
Simulation time 265572547 ps
CPU time 2.48 seconds
Started Apr 30 01:38:55 PM PDT 24
Finished Apr 30 01:38:58 PM PDT 24
Peak memory 216772 kb
Host smart-f1e9d78f-c173-402d-98ce-46acc3b8e35e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209250669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.4209250669
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1812111095
Short name T677
Test name
Test status
Simulation time 1921496557 ps
CPU time 21.23 seconds
Started Apr 30 01:38:52 PM PDT 24
Finished Apr 30 01:39:14 PM PDT 24
Peak memory 217696 kb
Host smart-f363e24c-18b6-4c13-9851-c0533e9594a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812111095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1812111095
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.10501481
Short name T135
Test name
Test status
Simulation time 334565793 ps
CPU time 9.01 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:38:57 PM PDT 24
Peak memory 217824 kb
Host smart-89473959-496a-46b7-8117-dbe8151d0dfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10501481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_
prog_failure.10501481
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3765713452
Short name T65
Test name
Test status
Simulation time 170727346 ps
CPU time 5.42 seconds
Started Apr 30 01:38:50 PM PDT 24
Finished Apr 30 01:38:56 PM PDT 24
Peak memory 213300 kb
Host smart-1af01e1c-a374-4074-95ac-5532c1d1708a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765713452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3765713452
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1117200264
Short name T548
Test name
Test status
Simulation time 11040164435 ps
CPU time 81.07 seconds
Started Apr 30 01:38:50 PM PDT 24
Finished Apr 30 01:40:11 PM PDT 24
Peak memory 271736 kb
Host smart-f19e2eb6-4282-4c9f-af8f-4a67fb9ed730
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117200264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1117200264
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1485778277
Short name T848
Test name
Test status
Simulation time 1440906200 ps
CPU time 11.79 seconds
Started Apr 30 01:38:48 PM PDT 24
Finished Apr 30 01:39:00 PM PDT 24
Peak memory 221720 kb
Host smart-3ab802fe-cdf5-4228-b7ed-baaf4308fc63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485778277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1485778277
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3889400844
Short name T216
Test name
Test status
Simulation time 52827284 ps
CPU time 2.63 seconds
Started Apr 30 01:38:51 PM PDT 24
Finished Apr 30 01:38:54 PM PDT 24
Peak memory 217780 kb
Host smart-6f8224b6-99db-4d2e-9f1f-f75abf7f2272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889400844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3889400844
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1838910076
Short name T770
Test name
Test status
Simulation time 265142049 ps
CPU time 9.54 seconds
Started Apr 30 01:38:49 PM PDT 24
Finished Apr 30 01:38:59 PM PDT 24
Peak memory 225912 kb
Host smart-939bf710-cb1d-4594-8151-a05a6f442a6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838910076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1838910076
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.139023080
Short name T406
Test name
Test status
Simulation time 1647374424 ps
CPU time 11.42 seconds
Started Apr 30 01:38:55 PM PDT 24
Finished Apr 30 01:39:06 PM PDT 24
Peak memory 217820 kb
Host smart-6e04e5c2-181c-4ab0-80b7-95586836d829
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139023080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.139023080
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2709774464
Short name T628
Test name
Test status
Simulation time 2206157573 ps
CPU time 11.75 seconds
Started Apr 30 01:38:54 PM PDT 24
Finished Apr 30 01:39:06 PM PDT 24
Peak memory 217892 kb
Host smart-bf10160a-4c6e-41d5-bb3f-cf3df7e52bd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709774464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2709774464
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2508767853
Short name T432
Test name
Test status
Simulation time 852222734 ps
CPU time 9.79 seconds
Started Apr 30 01:38:49 PM PDT 24
Finished Apr 30 01:39:00 PM PDT 24
Peak memory 217880 kb
Host smart-f6f04d52-258a-4043-884c-17f0e729db43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508767853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2508767853
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3572812344
Short name T549
Test name
Test status
Simulation time 590432235 ps
CPU time 10.14 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:16 PM PDT 24
Peak memory 217572 kb
Host smart-25c5a331-9c20-4beb-848d-d8096e3188f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572812344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3572812344
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1840529384
Short name T328
Test name
Test status
Simulation time 297114499 ps
CPU time 27.4 seconds
Started Apr 30 01:38:46 PM PDT 24
Finished Apr 30 01:39:14 PM PDT 24
Peak memory 250756 kb
Host smart-ea745ed4-1568-4189-8b85-a75a3b15d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840529384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1840529384
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3254435797
Short name T243
Test name
Test status
Simulation time 290844736 ps
CPU time 4.01 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:38:52 PM PDT 24
Peak memory 222204 kb
Host smart-0607fcc6-4eb3-4764-930a-6973051f5d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254435797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3254435797
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.508725833
Short name T706
Test name
Test status
Simulation time 3542445551 ps
CPU time 101.27 seconds
Started Apr 30 01:38:49 PM PDT 24
Finished Apr 30 01:40:31 PM PDT 24
Peak memory 274660 kb
Host smart-f0775d6d-437a-4842-a4ce-af1c979e8525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508725833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.508725833
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1701234869
Short name T780
Test name
Test status
Simulation time 20734857 ps
CPU time 0.93 seconds
Started Apr 30 01:38:57 PM PDT 24
Finished Apr 30 01:38:58 PM PDT 24
Peak memory 211480 kb
Host smart-f138209d-5789-46f3-997b-775e8a79bd51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701234869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1701234869
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1735585106
Short name T485
Test name
Test status
Simulation time 46642683 ps
CPU time 0.97 seconds
Started Apr 30 01:37:28 PM PDT 24
Finished Apr 30 01:37:29 PM PDT 24
Peak memory 209436 kb
Host smart-b1224d2f-82ab-4363-a7ae-d5ed3526957f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735585106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1735585106
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1986479756
Short name T207
Test name
Test status
Simulation time 35670157 ps
CPU time 0.87 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:18 PM PDT 24
Peak memory 209252 kb
Host smart-e7441d06-16c5-4697-914e-bcf2929ef911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986479756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1986479756
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.4262618159
Short name T379
Test name
Test status
Simulation time 561754312 ps
CPU time 23.89 seconds
Started Apr 30 01:37:19 PM PDT 24
Finished Apr 30 01:37:43 PM PDT 24
Peak memory 217700 kb
Host smart-ea152c7b-46b0-44ad-b42b-e6e7d6b2d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262618159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.4262618159
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3820096149
Short name T472
Test name
Test status
Simulation time 160823609 ps
CPU time 2.88 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:20 PM PDT 24
Peak memory 216840 kb
Host smart-44885689-ddc1-4f63-bdce-fcdcde3b29b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820096149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3820096149
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1879844625
Short name T751
Test name
Test status
Simulation time 1390984891 ps
CPU time 40.02 seconds
Started Apr 30 01:37:15 PM PDT 24
Finished Apr 30 01:37:56 PM PDT 24
Peak memory 217684 kb
Host smart-8f48df81-ab75-4a3d-be58-2b94dc1cfc37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879844625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1879844625
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2259640080
Short name T292
Test name
Test status
Simulation time 112739611 ps
CPU time 3.35 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:21 PM PDT 24
Peak memory 217660 kb
Host smart-ddd51cd4-03f8-43be-9fe5-a933e8611440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259640080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
259640080
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3678839854
Short name T552
Test name
Test status
Simulation time 512757311 ps
CPU time 3.91 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:21 PM PDT 24
Peak memory 217740 kb
Host smart-93a1e891-8987-468b-ac5f-8cc2a9e90b00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678839854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3678839854
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1405268048
Short name T530
Test name
Test status
Simulation time 3728531501 ps
CPU time 13.47 seconds
Started Apr 30 01:37:15 PM PDT 24
Finished Apr 30 01:37:29 PM PDT 24
Peak memory 213636 kb
Host smart-91d223fc-bcf9-4701-84bf-f6131d6939aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405268048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1405268048
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3182493798
Short name T63
Test name
Test status
Simulation time 592787456 ps
CPU time 4.6 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:22 PM PDT 24
Peak memory 213196 kb
Host smart-4269b2ee-6bc9-4499-a183-39e1d2ad4558
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182493798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3182493798
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2246231963
Short name T218
Test name
Test status
Simulation time 945791719 ps
CPU time 45.77 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:38:03 PM PDT 24
Peak memory 250684 kb
Host smart-956228b8-d1c7-45e8-b564-bddaf20c2e8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246231963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2246231963
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2357733037
Short name T824
Test name
Test status
Simulation time 4153063737 ps
CPU time 16.69 seconds
Started Apr 30 01:37:21 PM PDT 24
Finished Apr 30 01:37:38 PM PDT 24
Peak memory 250864 kb
Host smart-8d8b9804-7c51-46b1-8203-f75c0ad4ae00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357733037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2357733037
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3805492236
Short name T269
Test name
Test status
Simulation time 278736677 ps
CPU time 2.78 seconds
Started Apr 30 01:37:18 PM PDT 24
Finished Apr 30 01:37:21 PM PDT 24
Peak memory 217856 kb
Host smart-2fdc32a0-34b4-4c0e-bb1f-6471fb11d489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805492236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3805492236
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1809717872
Short name T77
Test name
Test status
Simulation time 261643229 ps
CPU time 6.35 seconds
Started Apr 30 01:37:16 PM PDT 24
Finished Apr 30 01:37:23 PM PDT 24
Peak memory 217616 kb
Host smart-b7318d95-82b7-4abe-8476-e16758d2b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809717872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1809717872
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1872689295
Short name T68
Test name
Test status
Simulation time 852658103 ps
CPU time 36 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:38:00 PM PDT 24
Peak memory 284452 kb
Host smart-034b480d-2961-4bee-8fd1-7a87848961cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872689295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1872689295
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2981622975
Short name T759
Test name
Test status
Simulation time 4059539440 ps
CPU time 28.16 seconds
Started Apr 30 01:37:19 PM PDT 24
Finished Apr 30 01:37:47 PM PDT 24
Peak memory 225984 kb
Host smart-402bcfea-fc0a-46d0-b943-fdf18b4677ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981622975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2981622975
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1316944643
Short name T412
Test name
Test status
Simulation time 897687700 ps
CPU time 10.33 seconds
Started Apr 30 01:37:22 PM PDT 24
Finished Apr 30 01:37:32 PM PDT 24
Peak memory 217800 kb
Host smart-15595a54-28e7-46e8-a1db-805de276d119
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316944643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1316944643
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1984597702
Short name T697
Test name
Test status
Simulation time 1937393041 ps
CPU time 15.62 seconds
Started Apr 30 01:37:18 PM PDT 24
Finished Apr 30 01:37:34 PM PDT 24
Peak memory 217840 kb
Host smart-f1dc4a04-7d66-49cb-979d-05aa48e8e4b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984597702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
984597702
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.871931239
Short name T637
Test name
Test status
Simulation time 358615450 ps
CPU time 13.66 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:31 PM PDT 24
Peak memory 217824 kb
Host smart-98ceb216-7a81-4ef1-87af-105d6dee67de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871931239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.871931239
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3495928446
Short name T799
Test name
Test status
Simulation time 81289189 ps
CPU time 2.68 seconds
Started Apr 30 01:37:18 PM PDT 24
Finished Apr 30 01:37:21 PM PDT 24
Peak memory 213904 kb
Host smart-0d27d2d4-4561-4bb2-89d6-dce1b0262de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495928446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3495928446
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.829644887
Short name T229
Test name
Test status
Simulation time 741088801 ps
CPU time 22.44 seconds
Started Apr 30 01:37:22 PM PDT 24
Finished Apr 30 01:37:45 PM PDT 24
Peak memory 250776 kb
Host smart-5a75bbaf-9d94-4a35-90aa-e457fa17732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829644887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.829644887
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3888696576
Short name T657
Test name
Test status
Simulation time 443522441 ps
CPU time 6.44 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:37:31 PM PDT 24
Peak memory 246728 kb
Host smart-adaca8de-1254-40da-acac-2e97b60ab12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888696576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3888696576
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1043674988
Short name T311
Test name
Test status
Simulation time 2899250183 ps
CPU time 21.41 seconds
Started Apr 30 01:37:17 PM PDT 24
Finished Apr 30 01:37:39 PM PDT 24
Peak memory 217816 kb
Host smart-eb1255f5-e6fa-4d98-909d-f766e92624fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043674988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1043674988
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2373206751
Short name T815
Test name
Test status
Simulation time 24831290 ps
CPU time 0.91 seconds
Started Apr 30 01:37:22 PM PDT 24
Finished Apr 30 01:37:23 PM PDT 24
Peak memory 211432 kb
Host smart-435216ea-b3cc-4ae6-a631-fab3130e9f4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373206751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2373206751
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4221243963
Short name T606
Test name
Test status
Simulation time 49530120 ps
CPU time 0.93 seconds
Started Apr 30 01:39:00 PM PDT 24
Finished Apr 30 01:39:02 PM PDT 24
Peak memory 209476 kb
Host smart-611b9995-f2da-468c-b360-940cd3b5a5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221243963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4221243963
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3066224725
Short name T492
Test name
Test status
Simulation time 312520310 ps
CPU time 13.36 seconds
Started Apr 30 01:38:54 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 225920 kb
Host smart-9720ee1f-fc47-4858-ba4d-848b1d895a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066224725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3066224725
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.355768972
Short name T692
Test name
Test status
Simulation time 999978940 ps
CPU time 14.24 seconds
Started Apr 30 01:38:56 PM PDT 24
Finished Apr 30 01:39:10 PM PDT 24
Peak memory 209460 kb
Host smart-a3cb26ee-0bed-4103-b858-d65842bd7089
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355768972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.355768972
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1478030217
Short name T803
Test name
Test status
Simulation time 188554685 ps
CPU time 4.33 seconds
Started Apr 30 01:39:02 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 217880 kb
Host smart-081fa2d1-1592-4fab-b2cd-67c2e1434a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478030217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1478030217
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2645791922
Short name T716
Test name
Test status
Simulation time 797120445 ps
CPU time 22.67 seconds
Started Apr 30 01:38:56 PM PDT 24
Finished Apr 30 01:39:19 PM PDT 24
Peak memory 225928 kb
Host smart-ca95a0af-11af-4a09-b71a-33f55dff4f7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645791922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2645791922
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1788867767
Short name T31
Test name
Test status
Simulation time 268867327 ps
CPU time 10.75 seconds
Started Apr 30 01:38:59 PM PDT 24
Finished Apr 30 01:39:10 PM PDT 24
Peak memory 217752 kb
Host smart-3538a992-56a3-4ebf-abcd-197d0a592c10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788867767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1788867767
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2833721113
Short name T579
Test name
Test status
Simulation time 473975486 ps
CPU time 6.25 seconds
Started Apr 30 01:38:58 PM PDT 24
Finished Apr 30 01:39:04 PM PDT 24
Peak memory 217868 kb
Host smart-167ec139-98c6-482a-a050-84e1ebdf0f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833721113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2833721113
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.127501837
Short name T604
Test name
Test status
Simulation time 606438897 ps
CPU time 6.97 seconds
Started Apr 30 01:38:58 PM PDT 24
Finished Apr 30 01:39:06 PM PDT 24
Peak memory 217868 kb
Host smart-741419ba-e56e-4928-9005-f54c4249db80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127501837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.127501837
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.4280217935
Short name T327
Test name
Test status
Simulation time 101910003 ps
CPU time 1.85 seconds
Started Apr 30 01:38:51 PM PDT 24
Finished Apr 30 01:38:53 PM PDT 24
Peak memory 213504 kb
Host smart-3df84507-842c-4583-881d-e6da8c88863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280217935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.4280217935
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.694550484
Short name T802
Test name
Test status
Simulation time 201755860 ps
CPU time 21.68 seconds
Started Apr 30 01:38:51 PM PDT 24
Finished Apr 30 01:39:13 PM PDT 24
Peak memory 250760 kb
Host smart-57f99f0d-bad3-4437-892a-0a0e34e4a5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694550484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.694550484
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4014917377
Short name T776
Test name
Test status
Simulation time 494717313 ps
CPU time 7.37 seconds
Started Apr 30 01:38:47 PM PDT 24
Finished Apr 30 01:38:54 PM PDT 24
Peak memory 250464 kb
Host smart-ae9b9e3f-1ca2-454b-8b4a-98d2e51c1d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014917377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4014917377
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2172959808
Short name T265
Test name
Test status
Simulation time 972458040 ps
CPU time 31.09 seconds
Started Apr 30 01:38:56 PM PDT 24
Finished Apr 30 01:39:27 PM PDT 24
Peak memory 214140 kb
Host smart-bf7c8422-c5d5-4811-8880-e6b409debf6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172959808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2172959808
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2112737660
Short name T137
Test name
Test status
Simulation time 177053515551 ps
CPU time 931.59 seconds
Started Apr 30 01:39:02 PM PDT 24
Finished Apr 30 01:54:35 PM PDT 24
Peak memory 422028 kb
Host smart-5dac7095-6542-4da8-9d7f-ca7b0ddafc1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2112737660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2112737660
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1183242665
Short name T234
Test name
Test status
Simulation time 25830335 ps
CPU time 1 seconds
Started Apr 30 01:38:53 PM PDT 24
Finished Apr 30 01:38:54 PM PDT 24
Peak memory 208708 kb
Host smart-1f6f2b46-c2a1-4e6b-be55-f0517b9492d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183242665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1183242665
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.852371962
Short name T715
Test name
Test status
Simulation time 65211903 ps
CPU time 1.19 seconds
Started Apr 30 01:38:57 PM PDT 24
Finished Apr 30 01:38:58 PM PDT 24
Peak memory 209428 kb
Host smart-c923ea8f-fb3f-42af-b3a3-c6a6e941d397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852371962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.852371962
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.69633741
Short name T514
Test name
Test status
Simulation time 774573208 ps
CPU time 10.83 seconds
Started Apr 30 01:38:54 PM PDT 24
Finished Apr 30 01:39:05 PM PDT 24
Peak memory 217844 kb
Host smart-17f7a9f8-5d0a-455e-8cfa-d8d9a4b27bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69633741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.69633741
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.132030795
Short name T6
Test name
Test status
Simulation time 995654367 ps
CPU time 5.54 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:11 PM PDT 24
Peak memory 209488 kb
Host smart-43df7504-6ca0-4b06-b656-36c54636f3a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132030795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.132030795
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3929516959
Short name T462
Test name
Test status
Simulation time 66875864 ps
CPU time 2.73 seconds
Started Apr 30 01:39:00 PM PDT 24
Finished Apr 30 01:39:03 PM PDT 24
Peak memory 217736 kb
Host smart-b4eba3c6-1b7b-44af-bc7c-06d38062b7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929516959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3929516959
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1357286236
Short name T699
Test name
Test status
Simulation time 789928122 ps
CPU time 12.25 seconds
Started Apr 30 01:39:00 PM PDT 24
Finished Apr 30 01:39:13 PM PDT 24
Peak memory 225892 kb
Host smart-ae1e4d87-c2c3-4f80-94e4-0556b6ad5cae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357286236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1357286236
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1993090739
Short name T352
Test name
Test status
Simulation time 1732260009 ps
CPU time 12.79 seconds
Started Apr 30 01:38:54 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 217788 kb
Host smart-15a82683-71f4-4363-9788-0795867545ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993090739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1993090739
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2831121826
Short name T409
Test name
Test status
Simulation time 1009815036 ps
CPU time 9.11 seconds
Started Apr 30 01:39:00 PM PDT 24
Finished Apr 30 01:39:10 PM PDT 24
Peak memory 218004 kb
Host smart-eeef0ad4-21c5-42ca-b588-4554547361ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831121826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2831121826
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1493000220
Short name T608
Test name
Test status
Simulation time 5443373073 ps
CPU time 6.81 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 224508 kb
Host smart-a369e106-de8a-4038-aa2c-26d34c150e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493000220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1493000220
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2846968518
Short name T381
Test name
Test status
Simulation time 46941096 ps
CPU time 2.91 seconds
Started Apr 30 01:38:56 PM PDT 24
Finished Apr 30 01:38:59 PM PDT 24
Peak memory 214120 kb
Host smart-7fe7da4c-5461-427e-b3db-e079becc04e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846968518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2846968518
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.421708360
Short name T851
Test name
Test status
Simulation time 250121005 ps
CPU time 24.6 seconds
Started Apr 30 01:38:58 PM PDT 24
Finished Apr 30 01:39:23 PM PDT 24
Peak memory 249432 kb
Host smart-25860c98-a744-4d0a-931c-82d261194673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421708360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.421708360
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3330633660
Short name T326
Test name
Test status
Simulation time 67908684 ps
CPU time 6.91 seconds
Started Apr 30 01:39:04 PM PDT 24
Finished Apr 30 01:39:11 PM PDT 24
Peak memory 246752 kb
Host smart-6f960f13-b10d-4dfa-89cb-4af93a6f1cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330633660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3330633660
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.561797697
Short name T639
Test name
Test status
Simulation time 23161957 ps
CPU time 0.88 seconds
Started Apr 30 01:38:57 PM PDT 24
Finished Apr 30 01:38:59 PM PDT 24
Peak memory 208712 kb
Host smart-33880bc3-dc1f-4c3d-bbd8-272b2a76f333
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561797697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.561797697
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3944338007
Short name T748
Test name
Test status
Simulation time 52339040 ps
CPU time 0.99 seconds
Started Apr 30 01:39:01 PM PDT 24
Finished Apr 30 01:39:03 PM PDT 24
Peak memory 209372 kb
Host smart-a5953660-94e0-4973-a06d-faa715ccc384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944338007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3944338007
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.4217916677
Short name T825
Test name
Test status
Simulation time 2576366240 ps
CPU time 12.91 seconds
Started Apr 30 01:38:59 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 226060 kb
Host smart-7f3a5495-8a7d-4d9c-9ff8-2cb1ef29e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217916677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.4217916677
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1796112826
Short name T723
Test name
Test status
Simulation time 37107964 ps
CPU time 2.56 seconds
Started Apr 30 01:39:01 PM PDT 24
Finished Apr 30 01:39:04 PM PDT 24
Peak memory 217900 kb
Host smart-6cefc466-5623-4d06-91f6-90f88ba4286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796112826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1796112826
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3289746240
Short name T714
Test name
Test status
Simulation time 1764038016 ps
CPU time 18.16 seconds
Started Apr 30 01:39:00 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 225892 kb
Host smart-09168d10-72d0-42b8-8ed7-3aee19227814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289746240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3289746240
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1022772306
Short name T662
Test name
Test status
Simulation time 265013451 ps
CPU time 12.67 seconds
Started Apr 30 01:38:59 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 217748 kb
Host smart-a69bb2dc-0cff-4a06-b1a9-58616aea8032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022772306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1022772306
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3896062554
Short name T631
Test name
Test status
Simulation time 765209110 ps
CPU time 10.89 seconds
Started Apr 30 01:38:56 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 218004 kb
Host smart-2a67ffe3-0429-481d-bcdf-30889d8109d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896062554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3896062554
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2676482253
Short name T370
Test name
Test status
Simulation time 386940584 ps
CPU time 2.96 seconds
Started Apr 30 01:38:57 PM PDT 24
Finished Apr 30 01:39:00 PM PDT 24
Peak memory 214004 kb
Host smart-dddfa8f6-cc88-49ee-9a52-33be3a71112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676482253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2676482253
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.823934673
Short name T374
Test name
Test status
Simulation time 1371635963 ps
CPU time 26.31 seconds
Started Apr 30 01:39:02 PM PDT 24
Finished Apr 30 01:39:29 PM PDT 24
Peak memory 250780 kb
Host smart-91757028-d34a-4607-bc97-fadcd7f92430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823934673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.823934673
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1487916267
Short name T832
Test name
Test status
Simulation time 67489218 ps
CPU time 5.88 seconds
Started Apr 30 01:39:04 PM PDT 24
Finished Apr 30 01:39:10 PM PDT 24
Peak memory 246464 kb
Host smart-5a5020df-90ad-48f8-8c5a-f9e97c26a6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487916267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1487916267
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3680092493
Short name T809
Test name
Test status
Simulation time 7090616126 ps
CPU time 123.67 seconds
Started Apr 30 01:38:57 PM PDT 24
Finished Apr 30 01:41:01 PM PDT 24
Peak memory 250908 kb
Host smart-bdb14d14-aacf-4992-b686-faa047cdd40b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680092493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3680092493
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2056946267
Short name T560
Test name
Test status
Simulation time 37250317 ps
CPU time 0.85 seconds
Started Apr 30 01:38:54 PM PDT 24
Finished Apr 30 01:38:55 PM PDT 24
Peak memory 211420 kb
Host smart-4988611d-eb93-4d9a-93cc-9c4efaeb7a72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056946267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2056946267
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3384133505
Short name T694
Test name
Test status
Simulation time 18186347 ps
CPU time 1.11 seconds
Started Apr 30 01:39:06 PM PDT 24
Finished Apr 30 01:39:08 PM PDT 24
Peak memory 209520 kb
Host smart-b143c006-859b-4706-937b-dd762c5c28d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384133505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3384133505
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.25946075
Short name T661
Test name
Test status
Simulation time 526885702 ps
CPU time 11.44 seconds
Started Apr 30 01:39:01 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 225472 kb
Host smart-71fb7133-f124-4de9-9aec-99932edba377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25946075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.25946075
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3592460824
Short name T445
Test name
Test status
Simulation time 1351062422 ps
CPU time 8 seconds
Started Apr 30 01:38:59 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 209416 kb
Host smart-f7f15924-0537-470d-af6a-116603140c9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592460824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3592460824
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2032711884
Short name T136
Test name
Test status
Simulation time 196221020 ps
CPU time 2.19 seconds
Started Apr 30 01:39:01 PM PDT 24
Finished Apr 30 01:39:04 PM PDT 24
Peak memory 217824 kb
Host smart-9d4d4250-77a1-47a3-8da3-a3789491a98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032711884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2032711884
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2186359834
Short name T708
Test name
Test status
Simulation time 2626926731 ps
CPU time 16.73 seconds
Started Apr 30 01:39:03 PM PDT 24
Finished Apr 30 01:39:21 PM PDT 24
Peak memory 226048 kb
Host smart-4e9f5661-ede9-493b-af13-71ae1e8948da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186359834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2186359834
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3465536833
Short name T584
Test name
Test status
Simulation time 490593422 ps
CPU time 11.51 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:17 PM PDT 24
Peak memory 217832 kb
Host smart-47f4a2a5-cffb-4b56-a258-9b5da112cae8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465536833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3465536833
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.351654428
Short name T766
Test name
Test status
Simulation time 608734947 ps
CPU time 10.02 seconds
Started Apr 30 01:39:06 PM PDT 24
Finished Apr 30 01:39:16 PM PDT 24
Peak memory 217796 kb
Host smart-24b59afb-2b02-4b55-9fa6-7f1845ca4fc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351654428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.351654428
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2175365042
Short name T299
Test name
Test status
Simulation time 365365988 ps
CPU time 8.78 seconds
Started Apr 30 01:38:57 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 225224 kb
Host smart-c416ebbe-f7ca-457d-b8a1-76d0a254985d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175365042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2175365042
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.509034735
Short name T61
Test name
Test status
Simulation time 36215585 ps
CPU time 1.69 seconds
Started Apr 30 01:39:00 PM PDT 24
Finished Apr 30 01:39:02 PM PDT 24
Peak memory 217732 kb
Host smart-dcc2becf-5ee1-41ca-9161-53074fe1a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509034735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.509034735
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4261910472
Short name T479
Test name
Test status
Simulation time 224938118 ps
CPU time 22.67 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:28 PM PDT 24
Peak memory 248456 kb
Host smart-11f74a03-5f89-4790-8710-77a13e5d9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261910472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4261910472
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3915784483
Short name T214
Test name
Test status
Simulation time 70163100 ps
CPU time 6.83 seconds
Started Apr 30 01:39:03 PM PDT 24
Finished Apr 30 01:39:11 PM PDT 24
Peak memory 250136 kb
Host smart-1fd69c48-2921-4dc5-a01a-ee898b1616e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915784483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3915784483
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3538286279
Short name T679
Test name
Test status
Simulation time 24567815067 ps
CPU time 95.58 seconds
Started Apr 30 01:39:03 PM PDT 24
Finished Apr 30 01:40:39 PM PDT 24
Peak memory 267312 kb
Host smart-8db04b1c-d202-4f5b-85e8-576237283d88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538286279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3538286279
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1721906918
Short name T841
Test name
Test status
Simulation time 14013922 ps
CPU time 0.89 seconds
Started Apr 30 01:38:56 PM PDT 24
Finished Apr 30 01:38:57 PM PDT 24
Peak memory 208704 kb
Host smart-378e19aa-6520-43cf-8a0c-90d451e486ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721906918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1721906918
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.464994347
Short name T393
Test name
Test status
Simulation time 17959549 ps
CPU time 0.87 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 209392 kb
Host smart-10ff0ee6-b383-4967-9a8a-4ab637af38f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464994347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.464994347
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1367659901
Short name T439
Test name
Test status
Simulation time 497450803 ps
CPU time 19.79 seconds
Started Apr 30 01:39:04 PM PDT 24
Finished Apr 30 01:39:24 PM PDT 24
Peak memory 217752 kb
Host smart-35386aa4-aa8c-451f-8e8b-b22884f8a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367659901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1367659901
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3076750646
Short name T676
Test name
Test status
Simulation time 1327179100 ps
CPU time 8.83 seconds
Started Apr 30 01:39:08 PM PDT 24
Finished Apr 30 01:39:17 PM PDT 24
Peak memory 209492 kb
Host smart-0b87cffd-6b14-42d1-beeb-6b36d986e43e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076750646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3076750646
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1073709552
Short name T818
Test name
Test status
Simulation time 120859582 ps
CPU time 1.87 seconds
Started Apr 30 01:39:07 PM PDT 24
Finished Apr 30 01:39:09 PM PDT 24
Peak memory 217852 kb
Host smart-1e711b27-2c27-490f-969b-a300c112b151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073709552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1073709552
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2873906173
Short name T446
Test name
Test status
Simulation time 1794439290 ps
CPU time 15.08 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:21 PM PDT 24
Peak memory 218456 kb
Host smart-a8300445-7197-47d6-8140-bf6f34c03f60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873906173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2873906173
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3864048822
Short name T670
Test name
Test status
Simulation time 723689703 ps
CPU time 15.46 seconds
Started Apr 30 01:39:03 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 217928 kb
Host smart-b3c0dc1f-e169-4df4-b8d2-3b0012d29371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864048822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3864048822
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.4011196933
Short name T440
Test name
Test status
Simulation time 2089274822 ps
CPU time 12.14 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 217856 kb
Host smart-42adfd31-56a1-46d1-8f38-c54363ef3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011196933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.4011196933
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2152175709
Short name T842
Test name
Test status
Simulation time 23572610 ps
CPU time 1.61 seconds
Started Apr 30 01:39:07 PM PDT 24
Finished Apr 30 01:39:09 PM PDT 24
Peak memory 217912 kb
Host smart-e043f78e-1d26-43b1-8c93-fba39397685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152175709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2152175709
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2137136071
Short name T516
Test name
Test status
Simulation time 984461754 ps
CPU time 25.42 seconds
Started Apr 30 01:39:04 PM PDT 24
Finished Apr 30 01:39:30 PM PDT 24
Peak memory 250740 kb
Host smart-272e45b2-3c63-4835-9dfc-9cb10b35907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137136071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2137136071
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.215658073
Short name T539
Test name
Test status
Simulation time 88543230 ps
CPU time 6.17 seconds
Started Apr 30 01:39:02 PM PDT 24
Finished Apr 30 01:39:09 PM PDT 24
Peak memory 246596 kb
Host smart-a1d423ec-e37a-4beb-8687-54aa72d10e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215658073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.215658073
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1965505699
Short name T236
Test name
Test status
Simulation time 5847942565 ps
CPU time 165.28 seconds
Started Apr 30 01:39:03 PM PDT 24
Finished Apr 30 01:41:49 PM PDT 24
Peak memory 283672 kb
Host smart-8dfa7748-58b5-4a4b-a2fd-ddcbc4baf886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965505699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1965505699
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4197420054
Short name T272
Test name
Test status
Simulation time 70710256 ps
CPU time 0.87 seconds
Started Apr 30 01:39:10 PM PDT 24
Finished Apr 30 01:39:11 PM PDT 24
Peak memory 208452 kb
Host smart-e35bee29-2d15-4aea-863f-0f58031b8d29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197420054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.4197420054
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3219526318
Short name T678
Test name
Test status
Simulation time 78645060 ps
CPU time 1.06 seconds
Started Apr 30 01:39:06 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 209320 kb
Host smart-5170f562-4e97-41ea-85e8-c594304b1fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219526318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3219526318
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.372785588
Short name T664
Test name
Test status
Simulation time 356311848 ps
CPU time 15.6 seconds
Started Apr 30 01:39:04 PM PDT 24
Finished Apr 30 01:39:20 PM PDT 24
Peak memory 217824 kb
Host smart-1397eee5-2757-4ddd-a7b6-c5ea2f2fede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372785588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.372785588
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1851297996
Short name T787
Test name
Test status
Simulation time 519362969 ps
CPU time 8.71 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 209388 kb
Host smart-1586212c-1ca6-445a-95ee-e9122b7773f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851297996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1851297996
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3227469042
Short name T159
Test name
Test status
Simulation time 366399206 ps
CPU time 3.2 seconds
Started Apr 30 01:39:10 PM PDT 24
Finished Apr 30 01:39:13 PM PDT 24
Peak memory 217868 kb
Host smart-c29dd92e-a4f3-48e7-90d5-aacee4dc0e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227469042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3227469042
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3644958961
Short name T490
Test name
Test status
Simulation time 3504309734 ps
CPU time 18.88 seconds
Started Apr 30 01:39:13 PM PDT 24
Finished Apr 30 01:39:32 PM PDT 24
Peak memory 226236 kb
Host smart-707be227-21aa-400b-8f8c-7d42ce19d0b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644958961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3644958961
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1609463217
Short name T338
Test name
Test status
Simulation time 2501286267 ps
CPU time 13.92 seconds
Started Apr 30 01:39:08 PM PDT 24
Finished Apr 30 01:39:22 PM PDT 24
Peak memory 217972 kb
Host smart-b97b1965-765e-4662-b1df-7335c794a510
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609463217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1609463217
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.479483474
Short name T254
Test name
Test status
Simulation time 312677139 ps
CPU time 11.02 seconds
Started Apr 30 01:39:13 PM PDT 24
Finished Apr 30 01:39:24 PM PDT 24
Peak memory 218076 kb
Host smart-52e3e077-a990-4f8c-ae25-21fa9890a64e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479483474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.479483474
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3880022310
Short name T581
Test name
Test status
Simulation time 1653431246 ps
CPU time 10.53 seconds
Started Apr 30 01:39:07 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 217844 kb
Host smart-e1855799-5f23-44eb-a73b-ca942e9be3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880022310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3880022310
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.399450394
Short name T211
Test name
Test status
Simulation time 53490155 ps
CPU time 3.73 seconds
Started Apr 30 01:39:03 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 217756 kb
Host smart-93c79923-90fb-46ad-a082-27bec0732693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399450394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.399450394
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.655840521
Short name T336
Test name
Test status
Simulation time 545278307 ps
CPU time 27.35 seconds
Started Apr 30 01:39:05 PM PDT 24
Finished Apr 30 01:39:33 PM PDT 24
Peak memory 250836 kb
Host smart-4e770fb7-bf49-4b01-acfa-18c4663cb46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655840521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.655840521
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1716781256
Short name T285
Test name
Test status
Simulation time 75136190 ps
CPU time 8.54 seconds
Started Apr 30 01:39:07 PM PDT 24
Finished Apr 30 01:39:16 PM PDT 24
Peak memory 248464 kb
Host smart-2f25227a-6100-4a2e-80b2-8d8d1c5586a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716781256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1716781256
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2835035329
Short name T152
Test name
Test status
Simulation time 12897777327 ps
CPU time 106.5 seconds
Started Apr 30 01:39:13 PM PDT 24
Finished Apr 30 01:41:00 PM PDT 24
Peak memory 246424 kb
Host smart-f64fe1df-18a0-463f-a0d9-4fabf7e1e088
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835035329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2835035329
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3840987867
Short name T775
Test name
Test status
Simulation time 14065870 ps
CPU time 0.82 seconds
Started Apr 30 01:39:07 PM PDT 24
Finished Apr 30 01:39:08 PM PDT 24
Peak memory 208400 kb
Host smart-4100d0e9-cc7f-4d5b-b7a2-a4e3ebb963b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840987867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3840987867
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1225063532
Short name T451
Test name
Test status
Simulation time 18433934 ps
CPU time 1.1 seconds
Started Apr 30 01:39:10 PM PDT 24
Finished Apr 30 01:39:11 PM PDT 24
Peak memory 209380 kb
Host smart-51606180-63cc-4678-b1de-21d2d72d50c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225063532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1225063532
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2896602800
Short name T288
Test name
Test status
Simulation time 1254278385 ps
CPU time 10.57 seconds
Started Apr 30 01:39:13 PM PDT 24
Finished Apr 30 01:39:24 PM PDT 24
Peak memory 226112 kb
Host smart-fed68cce-3cf8-46a5-9f53-e6371b33c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896602800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2896602800
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.787581215
Short name T19
Test name
Test status
Simulation time 689186503 ps
CPU time 9.39 seconds
Started Apr 30 01:39:07 PM PDT 24
Finished Apr 30 01:39:17 PM PDT 24
Peak memory 209444 kb
Host smart-c1f025bb-04e8-432e-92c8-bd4cc8008a04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787581215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.787581215
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2054156519
Short name T208
Test name
Test status
Simulation time 319755754 ps
CPU time 2.7 seconds
Started Apr 30 01:39:06 PM PDT 24
Finished Apr 30 01:39:09 PM PDT 24
Peak memory 217796 kb
Host smart-0245bfc1-26a2-4b68-987d-4aea413ba0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054156519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2054156519
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.748974417
Short name T577
Test name
Test status
Simulation time 896875336 ps
CPU time 10.07 seconds
Started Apr 30 01:39:03 PM PDT 24
Finished Apr 30 01:39:13 PM PDT 24
Peak memory 225956 kb
Host smart-30f8057c-d115-412a-b421-6121dbcf82ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748974417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.748974417
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2856711615
Short name T680
Test name
Test status
Simulation time 3616896015 ps
CPU time 13.36 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:22 PM PDT 24
Peak memory 217912 kb
Host smart-5a3db0b1-eff0-4388-86fb-49f05c1cb86e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856711615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2856711615
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1643125289
Short name T372
Test name
Test status
Simulation time 568242092 ps
CPU time 12.2 seconds
Started Apr 30 01:39:12 PM PDT 24
Finished Apr 30 01:39:24 PM PDT 24
Peak memory 218008 kb
Host smart-b5c3d8d6-8e2c-45ee-8216-78232ce0efea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643125289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1643125289
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.57346172
Short name T798
Test name
Test status
Simulation time 472344078 ps
CPU time 8.82 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 217804 kb
Host smart-e4e5ac30-2488-4910-97fc-bcfec19bbb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57346172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.57346172
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1971580081
Short name T643
Test name
Test status
Simulation time 110465310 ps
CPU time 2.58 seconds
Started Apr 30 01:39:04 PM PDT 24
Finished Apr 30 01:39:07 PM PDT 24
Peak memory 214312 kb
Host smart-975423b0-edcc-4db3-ae48-88726fd74cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971580081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1971580081
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.452300573
Short name T240
Test name
Test status
Simulation time 470135751 ps
CPU time 15.16 seconds
Started Apr 30 01:39:06 PM PDT 24
Finished Apr 30 01:39:22 PM PDT 24
Peak memory 250840 kb
Host smart-c07cdb2f-8e23-44c8-8486-b0535adb2cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452300573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.452300573
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.322262152
Short name T191
Test name
Test status
Simulation time 596219602 ps
CPU time 7.63 seconds
Started Apr 30 01:39:08 PM PDT 24
Finished Apr 30 01:39:16 PM PDT 24
Peak memory 250636 kb
Host smart-b21bdcb9-1f38-424e-9325-f44eee9a4d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322262152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.322262152
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2738377526
Short name T30
Test name
Test status
Simulation time 6068102058 ps
CPU time 196.07 seconds
Started Apr 30 01:39:10 PM PDT 24
Finished Apr 30 01:42:27 PM PDT 24
Peak memory 269204 kb
Host smart-2209fb89-928b-4fd3-b7ae-0e900b988786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738377526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2738377526
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.549124176
Short name T131
Test name
Test status
Simulation time 152780071541 ps
CPU time 958.61 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:55:08 PM PDT 24
Peak memory 389308 kb
Host smart-53238b60-a588-48d7-9669-ca6d85ef5e35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=549124176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.549124176
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.960496916
Short name T334
Test name
Test status
Simulation time 19796211 ps
CPU time 0.98 seconds
Started Apr 30 01:39:10 PM PDT 24
Finished Apr 30 01:39:11 PM PDT 24
Peak memory 209376 kb
Host smart-70c82e8f-8ea5-445f-86de-4983a8d6ca19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960496916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.960496916
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3926163793
Short name T459
Test name
Test status
Simulation time 1730312414 ps
CPU time 19.75 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:29 PM PDT 24
Peak memory 217788 kb
Host smart-fc221220-b7da-4743-aa09-d5183539dc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926163793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3926163793
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.676422422
Short name T578
Test name
Test status
Simulation time 729694083 ps
CPU time 5.12 seconds
Started Apr 30 01:39:10 PM PDT 24
Finished Apr 30 01:39:16 PM PDT 24
Peak memory 216668 kb
Host smart-2f16c55a-edc7-41ef-b7ce-7a34cd57de3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676422422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.676422422
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3831581128
Short name T561
Test name
Test status
Simulation time 32689841 ps
CPU time 2.2 seconds
Started Apr 30 01:39:11 PM PDT 24
Finished Apr 30 01:39:14 PM PDT 24
Peak memory 217892 kb
Host smart-fb9c892c-0b54-41d2-ae07-f37d5511cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831581128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3831581128
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.806073493
Short name T519
Test name
Test status
Simulation time 725807283 ps
CPU time 17.39 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:27 PM PDT 24
Peak memory 225872 kb
Host smart-eee3f81d-f5f4-4bf7-ba53-3411e490279f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806073493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.806073493
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.264520551
Short name T302
Test name
Test status
Simulation time 233942853 ps
CPU time 8.47 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 217848 kb
Host smart-34969b0e-cb3b-44d4-9d6c-f42b9ca2171e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264520551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.264520551
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3075544860
Short name T583
Test name
Test status
Simulation time 1446542408 ps
CPU time 9.2 seconds
Started Apr 30 01:39:14 PM PDT 24
Finished Apr 30 01:39:23 PM PDT 24
Peak memory 218016 kb
Host smart-daa1940d-65f8-4ee6-88da-11646c739c0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075544860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3075544860
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3832176603
Short name T395
Test name
Test status
Simulation time 81068707 ps
CPU time 1.34 seconds
Started Apr 30 01:39:10 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 217704 kb
Host smart-7b755d13-5773-4b0c-9300-cb14a7540539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832176603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3832176603
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1208224742
Short name T134
Test name
Test status
Simulation time 644594699 ps
CPU time 27.65 seconds
Started Apr 30 01:39:14 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 250960 kb
Host smart-2e5865c0-23cb-49a5-a555-5903bed5e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208224742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1208224742
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3323205146
Short name T219
Test name
Test status
Simulation time 55790229 ps
CPU time 9.31 seconds
Started Apr 30 01:39:12 PM PDT 24
Finished Apr 30 01:39:22 PM PDT 24
Peak memory 248532 kb
Host smart-2206159e-d5a1-438a-b94c-699f2231d9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323205146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3323205146
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1751681351
Short name T403
Test name
Test status
Simulation time 15191705 ps
CPU time 0.81 seconds
Started Apr 30 01:39:11 PM PDT 24
Finished Apr 30 01:39:12 PM PDT 24
Peak memory 208356 kb
Host smart-5131870e-7a5a-44cc-b3ef-1e9bcda904d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751681351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1751681351
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3978919139
Short name T667
Test name
Test status
Simulation time 33407959 ps
CPU time 0.91 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:39:26 PM PDT 24
Peak memory 209280 kb
Host smart-e2f2f66a-a4c8-4387-bfea-71f300ee94b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978919139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3978919139
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1964547147
Short name T427
Test name
Test status
Simulation time 371836513 ps
CPU time 12.45 seconds
Started Apr 30 01:39:15 PM PDT 24
Finished Apr 30 01:39:28 PM PDT 24
Peak memory 225296 kb
Host smart-2b892d69-78d4-4a92-8351-7d5c9455f5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964547147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1964547147
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2484959947
Short name T22
Test name
Test status
Simulation time 812596722 ps
CPU time 2.85 seconds
Started Apr 30 01:39:19 PM PDT 24
Finished Apr 30 01:39:22 PM PDT 24
Peak memory 216784 kb
Host smart-87e1bb11-cc0a-4608-83eb-e55e0cefc999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484959947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2484959947
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2774925988
Short name T460
Test name
Test status
Simulation time 35065228 ps
CPU time 2.27 seconds
Started Apr 30 01:39:18 PM PDT 24
Finished Apr 30 01:39:20 PM PDT 24
Peak memory 217808 kb
Host smart-bcba04f2-4ac9-47ef-973d-1a5475b54e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774925988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2774925988
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2418777258
Short name T592
Test name
Test status
Simulation time 1457764564 ps
CPU time 12.25 seconds
Started Apr 30 01:39:17 PM PDT 24
Finished Apr 30 01:39:29 PM PDT 24
Peak memory 225952 kb
Host smart-81af42c7-bc76-4113-9abb-aaadbe1b03f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418777258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2418777258
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4014595532
Short name T186
Test name
Test status
Simulation time 1141610446 ps
CPU time 12.19 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:39:33 PM PDT 24
Peak memory 218020 kb
Host smart-ff5a2225-6133-49f1-bb11-04711a9f3fdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014595532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4014595532
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.840016306
Short name T245
Test name
Test status
Simulation time 4932080681 ps
CPU time 16.19 seconds
Started Apr 30 01:39:18 PM PDT 24
Finished Apr 30 01:39:34 PM PDT 24
Peak memory 217932 kb
Host smart-2e11eea7-4dc2-4ea1-ae9e-f959a5cc677f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840016306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.840016306
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1867772206
Short name T184
Test name
Test status
Simulation time 921832048 ps
CPU time 9.94 seconds
Started Apr 30 01:39:22 PM PDT 24
Finished Apr 30 01:39:32 PM PDT 24
Peak memory 225248 kb
Host smart-77f62b13-84c3-44b3-9fb0-1823cbaccb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867772206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1867772206
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2509248243
Short name T71
Test name
Test status
Simulation time 46110846 ps
CPU time 2.34 seconds
Started Apr 30 01:39:12 PM PDT 24
Finished Apr 30 01:39:15 PM PDT 24
Peak memory 214116 kb
Host smart-a9b66fee-3f26-4a21-83e0-34202ce728a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509248243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2509248243
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.559653933
Short name T9
Test name
Test status
Simulation time 285825375 ps
CPU time 17.56 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:27 PM PDT 24
Peak memory 250848 kb
Host smart-16b0d0f1-b028-41bc-9434-fd732d4c3752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559653933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.559653933
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1617173058
Short name T861
Test name
Test status
Simulation time 251030117 ps
CPU time 6.1 seconds
Started Apr 30 01:39:09 PM PDT 24
Finished Apr 30 01:39:15 PM PDT 24
Peak memory 250716 kb
Host smart-f430af4d-e452-4593-b6b0-e5386c6f1a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617173058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1617173058
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2309984218
Short name T566
Test name
Test status
Simulation time 4522700622 ps
CPU time 93.19 seconds
Started Apr 30 01:39:17 PM PDT 24
Finished Apr 30 01:40:50 PM PDT 24
Peak memory 267328 kb
Host smart-d6b23171-a8e3-4f37-9f5b-c4aa9a0235f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309984218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2309984218
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3087322612
Short name T146
Test name
Test status
Simulation time 26617851 ps
CPU time 0.82 seconds
Started Apr 30 01:39:11 PM PDT 24
Finished Apr 30 01:39:13 PM PDT 24
Peak memory 208360 kb
Host smart-88ecb344-0d6e-4dc0-a75c-82ef5bfc94da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087322612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3087322612
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.689115731
Short name T517
Test name
Test status
Simulation time 92482170 ps
CPU time 0.98 seconds
Started Apr 30 01:39:20 PM PDT 24
Finished Apr 30 01:39:21 PM PDT 24
Peak memory 209120 kb
Host smart-b4459d6d-36b1-474c-926f-3e3e739629e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689115731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.689115731
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.286218407
Short name T411
Test name
Test status
Simulation time 1407289991 ps
CPU time 11.48 seconds
Started Apr 30 01:39:18 PM PDT 24
Finished Apr 30 01:39:30 PM PDT 24
Peak memory 217808 kb
Host smart-daa7f427-fdb1-4552-8477-67fc47705f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286218407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.286218407
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.4151479902
Short name T586
Test name
Test status
Simulation time 5650915120 ps
CPU time 4.61 seconds
Started Apr 30 01:39:16 PM PDT 24
Finished Apr 30 01:39:21 PM PDT 24
Peak memory 217764 kb
Host smart-2231ebd9-2a09-417d-b888-29b60e448fdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151479902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4151479902
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3648682049
Short name T461
Test name
Test status
Simulation time 31796886 ps
CPU time 2.26 seconds
Started Apr 30 01:39:17 PM PDT 24
Finished Apr 30 01:39:20 PM PDT 24
Peak memory 217808 kb
Host smart-28936d0c-f8f9-478c-a8f2-5942656a07e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648682049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3648682049
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3267038729
Short name T52
Test name
Test status
Simulation time 1922090112 ps
CPU time 13.5 seconds
Started Apr 30 01:39:15 PM PDT 24
Finished Apr 30 01:39:29 PM PDT 24
Peak memory 218796 kb
Host smart-c7caf01a-28e2-448e-a97a-865cbb6e6955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267038729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3267038729
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3178858705
Short name T704
Test name
Test status
Simulation time 3110973375 ps
CPU time 13.73 seconds
Started Apr 30 01:39:15 PM PDT 24
Finished Apr 30 01:39:29 PM PDT 24
Peak memory 217984 kb
Host smart-57ecaf43-9e5a-485b-a966-5f69b7853b39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178858705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3178858705
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.119340574
Short name T544
Test name
Test status
Simulation time 570727600 ps
CPU time 7.07 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:39:29 PM PDT 24
Peak memory 217796 kb
Host smart-1d23f38d-4168-403d-a4bf-76f23cfb660b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119340574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.119340574
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.399136128
Short name T570
Test name
Test status
Simulation time 320962706 ps
CPU time 9.62 seconds
Started Apr 30 01:39:15 PM PDT 24
Finished Apr 30 01:39:25 PM PDT 24
Peak memory 217948 kb
Host smart-3f42377d-0b79-4b3f-8198-104009e123d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399136128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.399136128
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.417514794
Short name T72
Test name
Test status
Simulation time 132809827 ps
CPU time 2.67 seconds
Started Apr 30 01:39:14 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 213992 kb
Host smart-59a9f65e-4d61-445e-94d4-208cc227856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417514794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.417514794
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3172254329
Short name T611
Test name
Test status
Simulation time 238138711 ps
CPU time 19.33 seconds
Started Apr 30 01:39:20 PM PDT 24
Finished Apr 30 01:39:40 PM PDT 24
Peak memory 250420 kb
Host smart-57bc9b23-00b6-469b-af32-7c68de67d9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172254329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3172254329
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.978720071
Short name T585
Test name
Test status
Simulation time 305589056 ps
CPU time 6.7 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:39:28 PM PDT 24
Peak memory 246188 kb
Host smart-5a769280-bdd6-4caa-bb25-489cdf60d8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978720071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.978720071
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.334469147
Short name T347
Test name
Test status
Simulation time 2058820958 ps
CPU time 59.96 seconds
Started Apr 30 01:39:20 PM PDT 24
Finished Apr 30 01:40:20 PM PDT 24
Peak memory 250452 kb
Host smart-827343b8-1b6c-4239-ae33-03483e9bf3de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334469147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.334469147
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2241536049
Short name T33
Test name
Test status
Simulation time 18462492 ps
CPU time 1.04 seconds
Started Apr 30 01:39:18 PM PDT 24
Finished Apr 30 01:39:20 PM PDT 24
Peak memory 212576 kb
Host smart-61919654-c8ef-403d-a381-2eb79c549e00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241536049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2241536049
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3276918397
Short name T785
Test name
Test status
Simulation time 23030408 ps
CPU time 1.24 seconds
Started Apr 30 01:37:32 PM PDT 24
Finished Apr 30 01:37:34 PM PDT 24
Peak memory 209344 kb
Host smart-5b4f4a64-abd2-45bc-b66f-17384b680a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276918397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3276918397
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2513168459
Short name T760
Test name
Test status
Simulation time 1357385029 ps
CPU time 12.77 seconds
Started Apr 30 01:37:35 PM PDT 24
Finished Apr 30 01:37:48 PM PDT 24
Peak memory 217800 kb
Host smart-fb159254-1b5e-459a-aa47-359f1ed123c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513168459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2513168459
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3115470250
Short name T721
Test name
Test status
Simulation time 1860904501 ps
CPU time 7.53 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:37:32 PM PDT 24
Peak memory 217104 kb
Host smart-b898e791-2a41-4013-8f0e-410d3a0031ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115470250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3115470250
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2161960449
Short name T850
Test name
Test status
Simulation time 4963251076 ps
CPU time 62.32 seconds
Started Apr 30 01:37:26 PM PDT 24
Finished Apr 30 01:38:29 PM PDT 24
Peak memory 219876 kb
Host smart-c0db5135-c2f1-4554-b502-508c2903a3cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161960449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2161960449
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4039153678
Short name T523
Test name
Test status
Simulation time 1125449994 ps
CPU time 12.09 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:37:37 PM PDT 24
Peak memory 217460 kb
Host smart-cd93a476-f8ac-4e68-9f92-fb0c73e5e002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039153678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
039153678
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3192384449
Short name T1
Test name
Test status
Simulation time 631631177 ps
CPU time 3.54 seconds
Started Apr 30 01:37:25 PM PDT 24
Finished Apr 30 01:37:28 PM PDT 24
Peak memory 217716 kb
Host smart-4aed5d85-3e8b-4612-82c2-e89a8d85d0f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192384449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3192384449
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3102671421
Short name T498
Test name
Test status
Simulation time 6251107628 ps
CPU time 18.15 seconds
Started Apr 30 01:37:25 PM PDT 24
Finished Apr 30 01:37:43 PM PDT 24
Peak memory 213920 kb
Host smart-3a331617-015e-41e1-88e0-c0f35e53be6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102671421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3102671421
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2979477387
Short name T295
Test name
Test status
Simulation time 419604686 ps
CPU time 5.75 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:37:31 PM PDT 24
Peak memory 213124 kb
Host smart-3943172c-49dc-409a-b252-143a6ad0df2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979477387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2979477387
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1047850108
Short name T279
Test name
Test status
Simulation time 2822662650 ps
CPU time 58 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:38:23 PM PDT 24
Peak memory 267216 kb
Host smart-18b3c3a6-720c-45ec-af15-0f3c02ffc867
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047850108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1047850108
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.716892206
Short name T531
Test name
Test status
Simulation time 1967641338 ps
CPU time 23.02 seconds
Started Apr 30 01:37:25 PM PDT 24
Finished Apr 30 01:37:48 PM PDT 24
Peak memory 250828 kb
Host smart-bf5e93d2-5c16-4a40-a227-89198ac166cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716892206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.716892206
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2127170206
Short name T777
Test name
Test status
Simulation time 245514549 ps
CPU time 2.62 seconds
Started Apr 30 01:37:25 PM PDT 24
Finished Apr 30 01:37:28 PM PDT 24
Peak memory 217832 kb
Host smart-804e7c21-6ca2-4764-9c31-406c4478b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127170206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2127170206
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3896177126
Short name T74
Test name
Test status
Simulation time 779665586 ps
CPU time 5.82 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:37:30 PM PDT 24
Peak memory 217804 kb
Host smart-95fe21ce-498d-410d-9d31-94b4f15621f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896177126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3896177126
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.364244342
Short name T49
Test name
Test status
Simulation time 3176180853 ps
CPU time 37.56 seconds
Started Apr 30 01:37:32 PM PDT 24
Finished Apr 30 01:38:10 PM PDT 24
Peak memory 282432 kb
Host smart-dd0d6f83-857c-4118-a9b6-d80d895fcbf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364244342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.364244342
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1247696120
Short name T681
Test name
Test status
Simulation time 2143307389 ps
CPU time 17.42 seconds
Started Apr 30 01:37:26 PM PDT 24
Finished Apr 30 01:37:44 PM PDT 24
Peak memory 218996 kb
Host smart-723c2974-19b3-46a8-8e96-c26186c5b90e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247696120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1247696120
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.99575927
Short name T859
Test name
Test status
Simulation time 1322448008 ps
CPU time 13.75 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:37:38 PM PDT 24
Peak memory 217856 kb
Host smart-7f72d431-5f39-42f2-be0b-c703cd5f2866
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99575927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dige
st.99575927
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2862794360
Short name T663
Test name
Test status
Simulation time 985166866 ps
CPU time 9.19 seconds
Started Apr 30 01:37:24 PM PDT 24
Finished Apr 30 01:37:34 PM PDT 24
Peak memory 217776 kb
Host smart-af86bf34-3d17-4dd2-ad4d-5e465af65759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862794360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
862794360
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3746101097
Short name T843
Test name
Test status
Simulation time 732906073 ps
CPU time 9.14 seconds
Started Apr 30 01:37:23 PM PDT 24
Finished Apr 30 01:37:32 PM PDT 24
Peak memory 225892 kb
Host smart-ad7ad2f5-aa4f-44a6-ada0-c878894049c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746101097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3746101097
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3137462519
Short name T235
Test name
Test status
Simulation time 105854507 ps
CPU time 1.13 seconds
Started Apr 30 01:37:25 PM PDT 24
Finished Apr 30 01:37:26 PM PDT 24
Peak memory 212844 kb
Host smart-17feeb02-e690-4c49-8aca-bbe8916aca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137462519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3137462519
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3147098774
Short name T261
Test name
Test status
Simulation time 370097225 ps
CPU time 23.52 seconds
Started Apr 30 01:37:28 PM PDT 24
Finished Apr 30 01:37:52 PM PDT 24
Peak memory 250860 kb
Host smart-e2f90762-3755-448d-ab5b-e790690aae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147098774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3147098774
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.84527387
Short name T500
Test name
Test status
Simulation time 1792817863 ps
CPU time 11.7 seconds
Started Apr 30 01:37:26 PM PDT 24
Finished Apr 30 01:37:38 PM PDT 24
Peak memory 245752 kb
Host smart-36daad13-1b15-490b-b92e-8303e44396d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84527387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.84527387
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.104691912
Short name T375
Test name
Test status
Simulation time 12374510901 ps
CPU time 428.42 seconds
Started Apr 30 01:37:23 PM PDT 24
Finished Apr 30 01:44:32 PM PDT 24
Peak memory 421856 kb
Host smart-2f595c5f-def0-45a5-81ec-fe72defba749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104691912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.104691912
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.112141537
Short name T437
Test name
Test status
Simulation time 43460122 ps
CPU time 0.79 seconds
Started Apr 30 01:37:23 PM PDT 24
Finished Apr 30 01:37:24 PM PDT 24
Peak memory 208272 kb
Host smart-288fb90e-359f-459b-a37a-5b2aee939b36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112141537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.112141537
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3125818427
Short name T69
Test name
Test status
Simulation time 14585939 ps
CPU time 1.16 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:39:27 PM PDT 24
Peak memory 209408 kb
Host smart-fe72c59e-aa1a-4e9e-8028-bdc413d81ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125818427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3125818427
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.157442508
Short name T754
Test name
Test status
Simulation time 732717116 ps
CPU time 15.33 seconds
Started Apr 30 01:39:27 PM PDT 24
Finished Apr 30 01:39:43 PM PDT 24
Peak memory 225904 kb
Host smart-5515da65-3425-4f5a-81ef-0e534729c9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157442508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.157442508
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2436983661
Short name T21
Test name
Test status
Simulation time 668395781 ps
CPU time 8.96 seconds
Started Apr 30 01:39:24 PM PDT 24
Finished Apr 30 01:39:34 PM PDT 24
Peak memory 209416 kb
Host smart-43c2ab75-9052-43c9-8967-868ab655d1d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436983661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2436983661
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.686594299
Short name T450
Test name
Test status
Simulation time 185205811 ps
CPU time 2.77 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:39:24 PM PDT 24
Peak memory 217796 kb
Host smart-09401610-13e0-4a21-946f-b36d8c7e1918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686594299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.686594299
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3265860027
Short name T521
Test name
Test status
Simulation time 2044695047 ps
CPU time 16.58 seconds
Started Apr 30 01:39:24 PM PDT 24
Finished Apr 30 01:39:41 PM PDT 24
Peak memory 225860 kb
Host smart-2bdf7b5a-dbb7-44c2-83d9-308b41e1b033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265860027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3265860027
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2364791949
Short name T605
Test name
Test status
Simulation time 1200742641 ps
CPU time 12.87 seconds
Started Apr 30 01:39:22 PM PDT 24
Finished Apr 30 01:39:35 PM PDT 24
Peak memory 217880 kb
Host smart-c4948035-3dd8-49b2-8f38-639da5e5030a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364791949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2364791949
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2818387040
Short name T792
Test name
Test status
Simulation time 386367177 ps
CPU time 10.03 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:39:36 PM PDT 24
Peak memory 217828 kb
Host smart-b800f259-c683-4cfb-a75a-3798d0d4d205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818387040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2818387040
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1400719631
Short name T812
Test name
Test status
Simulation time 534910531 ps
CPU time 9.16 seconds
Started Apr 30 01:39:22 PM PDT 24
Finished Apr 30 01:39:32 PM PDT 24
Peak memory 217864 kb
Host smart-cad9b8f9-896b-48e7-a326-db2afb3f3b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400719631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1400719631
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3370905720
Short name T729
Test name
Test status
Simulation time 53320692 ps
CPU time 2.43 seconds
Started Apr 30 01:39:16 PM PDT 24
Finished Apr 30 01:39:18 PM PDT 24
Peak memory 214124 kb
Host smart-c3a7c0c5-354e-4554-905c-02f7935cdd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370905720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3370905720
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.955079101
Short name T522
Test name
Test status
Simulation time 296226323 ps
CPU time 26.48 seconds
Started Apr 30 01:39:22 PM PDT 24
Finished Apr 30 01:39:49 PM PDT 24
Peak memory 246060 kb
Host smart-bb5635cc-f254-4cd7-9efb-843021133299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955079101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.955079101
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.360326642
Short name T816
Test name
Test status
Simulation time 87088210 ps
CPU time 6.43 seconds
Started Apr 30 01:39:16 PM PDT 24
Finished Apr 30 01:39:23 PM PDT 24
Peak memory 250728 kb
Host smart-95647217-d7a1-4a69-92f4-079d44a9425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360326642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.360326642
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.310329766
Short name T405
Test name
Test status
Simulation time 10206334544 ps
CPU time 368.56 seconds
Started Apr 30 01:39:20 PM PDT 24
Finished Apr 30 01:45:29 PM PDT 24
Peak memory 272632 kb
Host smart-af642fab-5b76-4f86-9a77-a3b02f759de7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310329766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.310329766
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.734261685
Short name T665
Test name
Test status
Simulation time 44522234 ps
CPU time 0.95 seconds
Started Apr 30 01:39:17 PM PDT 24
Finished Apr 30 01:39:19 PM PDT 24
Peak memory 212588 kb
Host smart-77a51748-5d31-4ff3-8d79-2c7a33ca55d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734261685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.734261685
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1807311878
Short name T308
Test name
Test status
Simulation time 50449189 ps
CPU time 1.02 seconds
Started Apr 30 01:39:24 PM PDT 24
Finished Apr 30 01:39:25 PM PDT 24
Peak memory 209376 kb
Host smart-bd7d38ca-8ac2-404e-8fe5-f6a909950724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807311878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1807311878
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.642338327
Short name T717
Test name
Test status
Simulation time 1793807304 ps
CPU time 14.02 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:39:35 PM PDT 24
Peak memory 225960 kb
Host smart-4fb7bcc0-b569-4917-ad7f-c036207d8c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642338327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.642338327
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1859495690
Short name T559
Test name
Test status
Simulation time 1846412069 ps
CPU time 11.25 seconds
Started Apr 30 01:39:26 PM PDT 24
Finished Apr 30 01:39:38 PM PDT 24
Peak memory 209352 kb
Host smart-07ac661e-76e8-4808-b5cf-4695445c7702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859495690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1859495690
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.4153865688
Short name T3
Test name
Test status
Simulation time 36949413 ps
CPU time 2.28 seconds
Started Apr 30 01:39:23 PM PDT 24
Finished Apr 30 01:39:26 PM PDT 24
Peak memory 217828 kb
Host smart-04954557-fb87-42c6-b564-eb0fdc67589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153865688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.4153865688
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1736734619
Short name T613
Test name
Test status
Simulation time 1478711596 ps
CPU time 11.31 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:39:33 PM PDT 24
Peak memory 225940 kb
Host smart-acd19817-5b66-4f0c-aefa-2bd853574a3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736734619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1736734619
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1081536805
Short name T822
Test name
Test status
Simulation time 371994916 ps
CPU time 11.14 seconds
Started Apr 30 01:39:26 PM PDT 24
Finished Apr 30 01:39:38 PM PDT 24
Peak memory 217716 kb
Host smart-e2009800-2ab7-49a8-9d04-8c23927dcb03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081536805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1081536805
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2803905033
Short name T251
Test name
Test status
Simulation time 487253804 ps
CPU time 12.11 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:39:33 PM PDT 24
Peak memory 217824 kb
Host smart-050f2821-850d-417a-a66a-3d15a0d3127f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803905033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2803905033
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.520402124
Short name T821
Test name
Test status
Simulation time 1068221066 ps
CPU time 6.92 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:39:32 PM PDT 24
Peak memory 223964 kb
Host smart-740a36d7-908e-48e7-97da-05c7a89f418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520402124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.520402124
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3494916177
Short name T220
Test name
Test status
Simulation time 22486802 ps
CPU time 1.23 seconds
Started Apr 30 01:39:22 PM PDT 24
Finished Apr 30 01:39:25 PM PDT 24
Peak memory 213172 kb
Host smart-3c66be57-9562-46eb-8300-2d5ba05e031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494916177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3494916177
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3659645377
Short name T666
Test name
Test status
Simulation time 1214402897 ps
CPU time 29.71 seconds
Started Apr 30 01:39:24 PM PDT 24
Finished Apr 30 01:39:54 PM PDT 24
Peak memory 245516 kb
Host smart-0aa93060-f681-4c1c-8c04-9e23d67516f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659645377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3659645377
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1385172199
Short name T684
Test name
Test status
Simulation time 219903113 ps
CPU time 6.61 seconds
Started Apr 30 01:39:23 PM PDT 24
Finished Apr 30 01:39:31 PM PDT 24
Peak memory 245284 kb
Host smart-572ed114-10c3-4c96-b6d1-b1b986b2be6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385172199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1385172199
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2494207715
Short name T562
Test name
Test status
Simulation time 82789257588 ps
CPU time 439.54 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:46:45 PM PDT 24
Peak memory 421900 kb
Host smart-ba93192e-8552-4422-928f-07c32e19b846
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494207715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2494207715
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1254576177
Short name T127
Test name
Test status
Simulation time 421593252784 ps
CPU time 1194.12 seconds
Started Apr 30 01:39:21 PM PDT 24
Finished Apr 30 01:59:16 PM PDT 24
Peak memory 300248 kb
Host smart-9a6ced47-65b2-42d2-b0d2-914b70f12f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1254576177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1254576177
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3779947079
Short name T34
Test name
Test status
Simulation time 38806566 ps
CPU time 0.91 seconds
Started Apr 30 01:39:26 PM PDT 24
Finished Apr 30 01:39:27 PM PDT 24
Peak memory 211612 kb
Host smart-3ea457b1-4c28-434f-a4e9-2797f91ff876
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779947079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3779947079
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3728832306
Short name T162
Test name
Test status
Simulation time 68739537 ps
CPU time 0.94 seconds
Started Apr 30 01:39:31 PM PDT 24
Finished Apr 30 01:39:33 PM PDT 24
Peak memory 209404 kb
Host smart-b3a2a95b-6333-4c78-9612-7e603de1d2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728832306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3728832306
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2430746691
Short name T199
Test name
Test status
Simulation time 1215506425 ps
CPU time 16.29 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 225936 kb
Host smart-e211cbdf-e921-43ea-a452-5a776d11737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430746691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2430746691
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1487230284
Short name T789
Test name
Test status
Simulation time 194418628 ps
CPU time 5.49 seconds
Started Apr 30 01:39:29 PM PDT 24
Finished Apr 30 01:39:35 PM PDT 24
Peak memory 216880 kb
Host smart-5ef6ec76-81ea-49d0-8b8c-bd90792bb81a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487230284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1487230284
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.243590984
Short name T290
Test name
Test status
Simulation time 24766931 ps
CPU time 2.03 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:39:28 PM PDT 24
Peak memory 217704 kb
Host smart-244ffa77-8fc7-4e07-baf7-b5de483cee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243590984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.243590984
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.915366044
Short name T237
Test name
Test status
Simulation time 342286671 ps
CPU time 11.82 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:43 PM PDT 24
Peak memory 225892 kb
Host smart-5004b50c-80ed-4f6b-9bf5-c6fe7e06f468
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915366044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.915366044
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2405493635
Short name T10
Test name
Test status
Simulation time 459528054 ps
CPU time 8.32 seconds
Started Apr 30 01:39:26 PM PDT 24
Finished Apr 30 01:39:35 PM PDT 24
Peak memory 217932 kb
Host smart-4f35d128-77d2-4c46-b6c3-7395239b7f6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405493635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2405493635
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3032072119
Short name T691
Test name
Test status
Simulation time 9811955019 ps
CPU time 12.77 seconds
Started Apr 30 01:39:33 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 217980 kb
Host smart-24e3af3d-a0c9-46f9-bd24-064e41e768a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032072119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3032072119
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.506933305
Short name T671
Test name
Test status
Simulation time 230151427 ps
CPU time 9 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:40 PM PDT 24
Peak memory 217912 kb
Host smart-2bf8e956-cc7d-461d-b15b-e1aeaca3d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506933305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.506933305
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3911710158
Short name T149
Test name
Test status
Simulation time 130793631 ps
CPU time 2.55 seconds
Started Apr 30 01:39:22 PM PDT 24
Finished Apr 30 01:39:25 PM PDT 24
Peak memory 213844 kb
Host smart-6be3f89b-484c-4676-86bb-4214a7096793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911710158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3911710158
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.817442009
Short name T197
Test name
Test status
Simulation time 231539419 ps
CPU time 24.88 seconds
Started Apr 30 01:39:24 PM PDT 24
Finished Apr 30 01:39:50 PM PDT 24
Peak memory 245680 kb
Host smart-84ad5556-f3bc-4248-9106-853f55c7f0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817442009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.817442009
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3857819304
Short name T747
Test name
Test status
Simulation time 165927760 ps
CPU time 3.58 seconds
Started Apr 30 01:39:22 PM PDT 24
Finished Apr 30 01:39:26 PM PDT 24
Peak memory 222624 kb
Host smart-44b39ee0-50bb-40e1-9f1d-eca500135f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857819304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3857819304
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3725104500
Short name T731
Test name
Test status
Simulation time 78252898339 ps
CPU time 760.85 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:52:12 PM PDT 24
Peak memory 245884 kb
Host smart-db3ee227-8269-4936-8cd6-9a7af4392aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725104500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3725104500
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1887262379
Short name T203
Test name
Test status
Simulation time 16530127 ps
CPU time 0.87 seconds
Started Apr 30 01:39:25 PM PDT 24
Finished Apr 30 01:39:27 PM PDT 24
Peak memory 208636 kb
Host smart-99eafa46-d3b0-4578-9618-73e53f75370e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887262379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1887262379
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3868544152
Short name T602
Test name
Test status
Simulation time 137698708 ps
CPU time 1.49 seconds
Started Apr 30 01:39:32 PM PDT 24
Finished Apr 30 01:39:34 PM PDT 24
Peak memory 209404 kb
Host smart-90d8984e-91c0-46da-a1f0-86e04713cb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868544152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3868544152
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1302871510
Short name T482
Test name
Test status
Simulation time 167604308 ps
CPU time 8.3 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:39 PM PDT 24
Peak memory 217788 kb
Host smart-b2733768-bcd9-4b78-8229-9331bbe7a371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302871510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1302871510
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1786817349
Short name T233
Test name
Test status
Simulation time 329315583 ps
CPU time 5.05 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:36 PM PDT 24
Peak memory 209436 kb
Host smart-c8e99c3d-0c3b-46a2-bb1f-aae6aff90735
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786817349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1786817349
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1090522933
Short name T346
Test name
Test status
Simulation time 431727940 ps
CPU time 3.51 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:34 PM PDT 24
Peak memory 217824 kb
Host smart-82c8dc0a-c6ff-48ba-9b14-60a3cd6e42f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090522933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1090522933
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.344370105
Short name T571
Test name
Test status
Simulation time 2273941538 ps
CPU time 11.64 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 225944 kb
Host smart-b76939c7-f63e-44e4-825e-5f05f8776077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344370105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.344370105
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.335578703
Short name T241
Test name
Test status
Simulation time 3815666882 ps
CPU time 9.52 seconds
Started Apr 30 01:39:32 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 218028 kb
Host smart-c9dbd6b0-501b-41e4-b895-1668657fa37a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335578703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.335578703
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3617372463
Short name T319
Test name
Test status
Simulation time 867144934 ps
CPU time 11.33 seconds
Started Apr 30 01:39:31 PM PDT 24
Finished Apr 30 01:39:43 PM PDT 24
Peak memory 217844 kb
Host smart-6210cbe5-3826-4dfe-8401-c173c6d9bdfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617372463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3617372463
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2252306668
Short name T447
Test name
Test status
Simulation time 1699646088 ps
CPU time 9.15 seconds
Started Apr 30 01:39:29 PM PDT 24
Finished Apr 30 01:39:38 PM PDT 24
Peak memory 224180 kb
Host smart-f2cbcb2d-355a-407b-8a95-28f67b600822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252306668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2252306668
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1036752930
Short name T421
Test name
Test status
Simulation time 34604791 ps
CPU time 1.29 seconds
Started Apr 30 01:39:27 PM PDT 24
Finished Apr 30 01:39:29 PM PDT 24
Peak memory 213160 kb
Host smart-ece5d4ad-422d-4999-9bd3-1aabe1ce38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036752930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1036752930
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.34728294
Short name T607
Test name
Test status
Simulation time 157494242 ps
CPU time 15.85 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 250768 kb
Host smart-1aef9e21-0d0e-4e11-b09d-106738c47b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34728294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.34728294
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3838168243
Short name T838
Test name
Test status
Simulation time 351247330 ps
CPU time 3.26 seconds
Started Apr 30 01:39:29 PM PDT 24
Finished Apr 30 01:39:32 PM PDT 24
Peak memory 222188 kb
Host smart-94f2a02d-0f3b-40dd-84f9-26aa5a89f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838168243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3838168243
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2124583219
Short name T348
Test name
Test status
Simulation time 3975503638 ps
CPU time 102.04 seconds
Started Apr 30 01:39:29 PM PDT 24
Finished Apr 30 01:41:11 PM PDT 24
Peak memory 283572 kb
Host smart-06baf8a9-b3ab-4c9d-a45a-515da0e81001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124583219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2124583219
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.437119822
Short name T444
Test name
Test status
Simulation time 15676539394 ps
CPU time 532.55 seconds
Started Apr 30 01:39:33 PM PDT 24
Finished Apr 30 01:48:26 PM PDT 24
Peak memory 283836 kb
Host smart-39142dfa-482e-4262-a6d9-116569c07b38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=437119822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.437119822
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2086023370
Short name T600
Test name
Test status
Simulation time 47269635 ps
CPU time 0.8 seconds
Started Apr 30 01:39:30 PM PDT 24
Finished Apr 30 01:39:31 PM PDT 24
Peak memory 208380 kb
Host smart-d3a94a5a-b4a2-418f-9378-5ed172839f31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086023370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2086023370
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2894169543
Short name T772
Test name
Test status
Simulation time 128896633 ps
CPU time 1.12 seconds
Started Apr 30 01:39:41 PM PDT 24
Finished Apr 30 01:39:43 PM PDT 24
Peak memory 209360 kb
Host smart-219df2fc-7c18-416e-b2e2-2dea1cdeade8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894169543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2894169543
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.500148569
Short name T480
Test name
Test status
Simulation time 897910948 ps
CPU time 10.1 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:39:49 PM PDT 24
Peak memory 217848 kb
Host smart-4b458627-9d64-4dbf-93e7-ecbc09214257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500148569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.500148569
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2232879422
Short name T801
Test name
Test status
Simulation time 92391827 ps
CPU time 2.65 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:39:40 PM PDT 24
Peak memory 209512 kb
Host smart-e36c55f5-48bb-4d2e-b910-c5626e699a6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232879422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2232879422
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.6572540
Short name T826
Test name
Test status
Simulation time 1713283952 ps
CPU time 5.26 seconds
Started Apr 30 01:39:43 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 217884 kb
Host smart-fa8e4936-7946-4312-bfcf-db708d827414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6572540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.6572540
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1876565897
Short name T340
Test name
Test status
Simulation time 402102981 ps
CPU time 19.06 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:39:57 PM PDT 24
Peak memory 225952 kb
Host smart-da642594-6f87-4424-8b92-0780448c0919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876565897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1876565897
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1150031924
Short name T194
Test name
Test status
Simulation time 470037188 ps
CPU time 7.45 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 217928 kb
Host smart-ab6c2bc0-2227-4c4c-9579-7edff3cfb929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150031924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1150031924
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2266129281
Short name T739
Test name
Test status
Simulation time 459566796 ps
CPU time 8.25 seconds
Started Apr 30 01:39:41 PM PDT 24
Finished Apr 30 01:39:50 PM PDT 24
Peak memory 217792 kb
Host smart-d17a312e-830b-4ce9-a20f-31f9da044077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266129281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2266129281
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1914915857
Short name T88
Test name
Test status
Simulation time 1136827033 ps
CPU time 12.44 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:39:50 PM PDT 24
Peak memory 217844 kb
Host smart-c4e3ddfc-efab-432d-8b12-22eb4b5c204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914915857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1914915857
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3139622505
Short name T438
Test name
Test status
Simulation time 273281649 ps
CPU time 2.14 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:39:40 PM PDT 24
Peak memory 213924 kb
Host smart-5b2f37be-bc9d-4411-8c0f-6a49866752ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139622505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3139622505
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2656056835
Short name T610
Test name
Test status
Simulation time 304787029 ps
CPU time 22.34 seconds
Started Apr 30 01:39:39 PM PDT 24
Finished Apr 30 01:40:02 PM PDT 24
Peak memory 247176 kb
Host smart-1456ce9d-679e-41dc-9fb4-36279b59ceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656056835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2656056835
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.954545344
Short name T675
Test name
Test status
Simulation time 88329031 ps
CPU time 8.95 seconds
Started Apr 30 01:39:36 PM PDT 24
Finished Apr 30 01:39:45 PM PDT 24
Peak memory 250836 kb
Host smart-fb5355d5-b827-4354-a8d3-2a182c723440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954545344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.954545344
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3972831303
Short name T587
Test name
Test status
Simulation time 24139586730 ps
CPU time 81.57 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:41:00 PM PDT 24
Peak memory 230424 kb
Host smart-3f770974-09f3-4b45-9e36-83ab17f3ef88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972831303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3972831303
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.113607961
Short name T67
Test name
Test status
Simulation time 20786987 ps
CPU time 1.05 seconds
Started Apr 30 01:39:39 PM PDT 24
Finished Apr 30 01:39:40 PM PDT 24
Peak memory 211504 kb
Host smart-e998b661-ea05-4222-8128-40cd73073bd1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113607961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.113607961
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1428333740
Short name T278
Test name
Test status
Simulation time 20727845 ps
CPU time 1.24 seconds
Started Apr 30 01:39:36 PM PDT 24
Finished Apr 30 01:39:38 PM PDT 24
Peak memory 209456 kb
Host smart-d81f059d-4bc8-41ee-8634-935707e51319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428333740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1428333740
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3647936670
Short name T144
Test name
Test status
Simulation time 1078924738 ps
CPU time 12.31 seconds
Started Apr 30 01:39:35 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 217856 kb
Host smart-b58124a6-503c-44e2-a67c-fa0fd2a791bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647936670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3647936670
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2092166299
Short name T494
Test name
Test status
Simulation time 586598584 ps
CPU time 7.16 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 209400 kb
Host smart-6963a4e1-2df3-49df-8d50-718568e1079f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092166299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2092166299
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.345129335
Short name T249
Test name
Test status
Simulation time 34295969 ps
CPU time 1.68 seconds
Started Apr 30 01:39:39 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 217856 kb
Host smart-37c19e7e-eef5-403a-a8ec-07647e0bbf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345129335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.345129335
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2752570951
Short name T730
Test name
Test status
Simulation time 388382530 ps
CPU time 12.61 seconds
Started Apr 30 01:39:43 PM PDT 24
Finished Apr 30 01:39:56 PM PDT 24
Peak memory 225932 kb
Host smart-02434394-1382-41b1-881f-5704a2938413
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752570951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2752570951
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.268281688
Short name T769
Test name
Test status
Simulation time 570475226 ps
CPU time 12 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:39:50 PM PDT 24
Peak memory 217744 kb
Host smart-03120829-ba13-433b-8fa8-d560241aeb9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268281688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.268281688
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1354220000
Short name T415
Test name
Test status
Simulation time 1165648461 ps
CPU time 10.25 seconds
Started Apr 30 01:39:40 PM PDT 24
Finished Apr 30 01:39:51 PM PDT 24
Peak memory 217804 kb
Host smart-33b7a31f-d6e6-4606-9a1b-62efd6a0824f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354220000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1354220000
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1406940622
Short name T244
Test name
Test status
Simulation time 276762092 ps
CPU time 8.75 seconds
Started Apr 30 01:39:39 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 217912 kb
Host smart-c57d5c69-d9ae-46a3-81f5-5e1acbbe9bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406940622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1406940622
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2920563294
Short name T258
Test name
Test status
Simulation time 66264164 ps
CPU time 3.68 seconds
Started Apr 30 01:39:41 PM PDT 24
Finished Apr 30 01:39:45 PM PDT 24
Peak memory 217548 kb
Host smart-40eb7116-3702-428d-8cee-73a233c18670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920563294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2920563294
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3565214273
Short name T225
Test name
Test status
Simulation time 494530569 ps
CPU time 23.11 seconds
Started Apr 30 01:39:40 PM PDT 24
Finished Apr 30 01:40:03 PM PDT 24
Peak memory 248620 kb
Host smart-a3249bf8-d2bf-4dae-a93c-0504c4b7d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565214273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3565214273
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1747764349
Short name T645
Test name
Test status
Simulation time 67231925 ps
CPU time 7.05 seconds
Started Apr 30 01:39:36 PM PDT 24
Finished Apr 30 01:39:43 PM PDT 24
Peak memory 250712 kb
Host smart-4d423bc8-8194-412b-b622-6c66184dec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747764349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1747764349
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3322509166
Short name T37
Test name
Test status
Simulation time 4413840587 ps
CPU time 77.43 seconds
Started Apr 30 01:39:36 PM PDT 24
Finished Apr 30 01:40:54 PM PDT 24
Peak memory 226044 kb
Host smart-57b5df4c-7731-48d1-8ce0-5edd4f5a1418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322509166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3322509166
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3224096768
Short name T82
Test name
Test status
Simulation time 43105722 ps
CPU time 1.14 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:39:40 PM PDT 24
Peak memory 212820 kb
Host smart-6825bd77-cd8d-42f6-a734-2e6df1c8e993
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224096768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3224096768
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.4085719372
Short name T728
Test name
Test status
Simulation time 24042476 ps
CPU time 1.01 seconds
Started Apr 30 01:39:47 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 209380 kb
Host smart-9d51773c-3e32-49c2-904b-753da816d91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085719372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4085719372
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1774641715
Short name T713
Test name
Test status
Simulation time 247084117 ps
CPU time 9.62 seconds
Started Apr 30 01:39:39 PM PDT 24
Finished Apr 30 01:39:49 PM PDT 24
Peak memory 225908 kb
Host smart-0e734223-9762-47c3-944c-86e69b5a7e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774641715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1774641715
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1353176745
Short name T66
Test name
Test status
Simulation time 2016563992 ps
CPU time 4.55 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 209476 kb
Host smart-a3b59023-1a52-4ad8-a6a8-6b3ff9000fee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353176745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1353176745
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3689272280
Short name T854
Test name
Test status
Simulation time 162726350 ps
CPU time 2.38 seconds
Started Apr 30 01:39:39 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 217896 kb
Host smart-1632b551-8f08-4d8b-bbf8-fbb8003be419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689272280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3689272280
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.435221317
Short name T590
Test name
Test status
Simulation time 195064762 ps
CPU time 6.84 seconds
Started Apr 30 01:39:39 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 217920 kb
Host smart-8b43dac8-9fe4-4948-b673-63fae0a7f0a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435221317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.435221317
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3789935321
Short name T58
Test name
Test status
Simulation time 312068719 ps
CPU time 9.14 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 217836 kb
Host smart-0b440656-47a3-4e32-ba28-94f776eaea13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789935321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3789935321
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3671902874
Short name T301
Test name
Test status
Simulation time 2399951729 ps
CPU time 7.01 seconds
Started Apr 30 01:39:38 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 218000 kb
Host smart-b703cfb8-baf5-4ee0-8815-87c027578544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671902874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3671902874
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3821020529
Short name T80
Test name
Test status
Simulation time 126022599 ps
CPU time 1.83 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:39:39 PM PDT 24
Peak memory 213716 kb
Host smart-2104cb91-bf09-4cec-9c12-10a5d007e1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821020529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3821020529
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.785348481
Short name T520
Test name
Test status
Simulation time 868589692 ps
CPU time 23.86 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:40:01 PM PDT 24
Peak memory 250748 kb
Host smart-a69e8860-3ae8-4b97-9d99-fdb79fe55375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785348481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.785348481
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3369196012
Short name T380
Test name
Test status
Simulation time 252579889 ps
CPU time 8.27 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 250840 kb
Host smart-00f94ceb-2697-40cf-b7e0-50a930af7433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369196012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3369196012
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3633745997
Short name T568
Test name
Test status
Simulation time 5537829023 ps
CPU time 140.38 seconds
Started Apr 30 01:39:37 PM PDT 24
Finished Apr 30 01:41:58 PM PDT 24
Peak memory 263592 kb
Host smart-97a8f5ae-d9c9-45f8-8276-53ebf83f7691
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633745997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3633745997
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1871471708
Short name T846
Test name
Test status
Simulation time 13509950 ps
CPU time 0.98 seconds
Started Apr 30 01:39:41 PM PDT 24
Finished Apr 30 01:39:42 PM PDT 24
Peak memory 211344 kb
Host smart-74311330-7b06-4d3e-978b-4479dedab40d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871471708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1871471708
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.325367574
Short name T738
Test name
Test status
Simulation time 33088233 ps
CPU time 0.95 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 209320 kb
Host smart-f895113b-70cf-4693-904f-4b1862df014c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325367574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.325367574
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3370993434
Short name T247
Test name
Test status
Simulation time 5159850627 ps
CPU time 13.88 seconds
Started Apr 30 01:39:45 PM PDT 24
Finished Apr 30 01:39:59 PM PDT 24
Peak memory 218224 kb
Host smart-0da63a98-4fea-46d1-95a6-89c6665b19cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370993434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3370993434
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4155527696
Short name T18
Test name
Test status
Simulation time 558200349 ps
CPU time 7.82 seconds
Started Apr 30 01:39:49 PM PDT 24
Finished Apr 30 01:39:57 PM PDT 24
Peak memory 209384 kb
Host smart-ce642b2d-1539-44e2-9025-cf1cbc309687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155527696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.4155527696
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3829907729
Short name T298
Test name
Test status
Simulation time 203500055 ps
CPU time 2.51 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:39:49 PM PDT 24
Peak memory 217792 kb
Host smart-a8523d72-35aa-4647-a6ef-e1afa21d4f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829907729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3829907729
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.824212741
Short name T483
Test name
Test status
Simulation time 2088602972 ps
CPU time 11.44 seconds
Started Apr 30 01:39:48 PM PDT 24
Finished Apr 30 01:40:00 PM PDT 24
Peak memory 218200 kb
Host smart-57f1e89f-12ea-498d-917e-2f050aa5deed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824212741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.824212741
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1550439743
Short name T617
Test name
Test status
Simulation time 313312914 ps
CPU time 13.22 seconds
Started Apr 30 01:39:49 PM PDT 24
Finished Apr 30 01:40:03 PM PDT 24
Peak memory 217824 kb
Host smart-e9cc4757-1f81-4e27-8e10-5244a698c7f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550439743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1550439743
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1500504392
Short name T507
Test name
Test status
Simulation time 1586729255 ps
CPU time 6.73 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:39:51 PM PDT 24
Peak memory 217756 kb
Host smart-3f7c4602-b510-4197-90ce-553982544a9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500504392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1500504392
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4194441394
Short name T582
Test name
Test status
Simulation time 472816433 ps
CPU time 6.52 seconds
Started Apr 30 01:39:45 PM PDT 24
Finished Apr 30 01:39:52 PM PDT 24
Peak memory 217912 kb
Host smart-b6dc9904-da9d-46a4-a351-b1bb54fde846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194441394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4194441394
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.687589031
Short name T603
Test name
Test status
Simulation time 26372178 ps
CPU time 1.26 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:39:48 PM PDT 24
Peak memory 213164 kb
Host smart-ae82238a-a46f-42c5-93fe-5c36b8011d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687589031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.687589031
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1708995864
Short name T357
Test name
Test status
Simulation time 273517067 ps
CPU time 20.08 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:40:05 PM PDT 24
Peak memory 250780 kb
Host smart-5ca7276a-4303-4f50-a828-4eb513a0a967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708995864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1708995864
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1564383593
Short name T660
Test name
Test status
Simulation time 395669567 ps
CPU time 7.85 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:39:55 PM PDT 24
Peak memory 250568 kb
Host smart-d1cb0e9d-370d-4e65-8f2b-f13600b2104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564383593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1564383593
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2751597012
Short name T363
Test name
Test status
Simulation time 71435297418 ps
CPU time 557.38 seconds
Started Apr 30 01:39:45 PM PDT 24
Finished Apr 30 01:49:03 PM PDT 24
Peak memory 250848 kb
Host smart-b975d1b3-d5a7-4c2e-88eb-74f05d16ed81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751597012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2751597012
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3591165847
Short name T737
Test name
Test status
Simulation time 15292920 ps
CPU time 1.14 seconds
Started Apr 30 01:39:48 PM PDT 24
Finished Apr 30 01:39:49 PM PDT 24
Peak memory 211500 kb
Host smart-21e91fa5-355d-4099-92d7-6d78702f42ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591165847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3591165847
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1407324323
Short name T636
Test name
Test status
Simulation time 20321374 ps
CPU time 0.83 seconds
Started Apr 30 01:39:45 PM PDT 24
Finished Apr 30 01:39:46 PM PDT 24
Peak memory 209328 kb
Host smart-9b778bc5-078b-4b38-892e-f1704317b1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407324323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1407324323
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3532764711
Short name T538
Test name
Test status
Simulation time 172674801 ps
CPU time 9.03 seconds
Started Apr 30 01:39:48 PM PDT 24
Finished Apr 30 01:39:58 PM PDT 24
Peak memory 217812 kb
Host smart-eb4b2c2c-d858-4234-9894-2dc50d7260f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532764711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3532764711
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2281346598
Short name T322
Test name
Test status
Simulation time 241127627 ps
CPU time 6.6 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:39:52 PM PDT 24
Peak memory 217072 kb
Host smart-23b0d2da-ef0c-4a5f-923b-8be39b83c8d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281346598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2281346598
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1656223434
Short name T698
Test name
Test status
Simulation time 52727401 ps
CPU time 2.97 seconds
Started Apr 30 01:39:43 PM PDT 24
Finished Apr 30 01:39:47 PM PDT 24
Peak memory 217880 kb
Host smart-b45565cb-b497-4df7-be57-768b8861b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656223434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1656223434
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1119408433
Short name T830
Test name
Test status
Simulation time 822278864 ps
CPU time 12.83 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:39:59 PM PDT 24
Peak memory 217840 kb
Host smart-9c89a7ff-53eb-4e5d-9c22-95509731e31e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119408433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1119408433
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3774701175
Short name T257
Test name
Test status
Simulation time 799101558 ps
CPU time 9.83 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:39:54 PM PDT 24
Peak memory 217744 kb
Host smart-199d0e74-e859-40bc-ad53-e07051e86649
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774701175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3774701175
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3135611747
Short name T829
Test name
Test status
Simulation time 468937961 ps
CPU time 9.57 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:39:54 PM PDT 24
Peak memory 217884 kb
Host smart-e2dcba6e-5acf-4834-b471-ffaecbac1b56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135611747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3135611747
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.969340616
Short name T359
Test name
Test status
Simulation time 364872519 ps
CPU time 14.91 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:40:00 PM PDT 24
Peak memory 217956 kb
Host smart-49c14776-b6f0-481f-aaa8-8090c984ad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969340616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.969340616
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1144354592
Short name T614
Test name
Test status
Simulation time 296239214 ps
CPU time 1.55 seconds
Started Apr 30 01:39:43 PM PDT 24
Finished Apr 30 01:39:45 PM PDT 24
Peak memory 213472 kb
Host smart-ea288263-868c-453b-90d9-c82142c52345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144354592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1144354592
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.841098226
Short name T601
Test name
Test status
Simulation time 645415376 ps
CPU time 29.77 seconds
Started Apr 30 01:39:47 PM PDT 24
Finished Apr 30 01:40:17 PM PDT 24
Peak memory 250744 kb
Host smart-a3a716f5-7689-4fda-af57-8ddc213709aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841098226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.841098226
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2070747772
Short name T398
Test name
Test status
Simulation time 114930463 ps
CPU time 2.98 seconds
Started Apr 30 01:39:49 PM PDT 24
Finished Apr 30 01:39:52 PM PDT 24
Peak memory 217880 kb
Host smart-2fe4b647-a52b-49b8-9b61-bdcbea2a1a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070747772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2070747772
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4260935364
Short name T312
Test name
Test status
Simulation time 2057508663 ps
CPU time 89.47 seconds
Started Apr 30 01:39:48 PM PDT 24
Finished Apr 30 01:41:18 PM PDT 24
Peak memory 251584 kb
Host smart-549b82e8-24f2-4c6b-bb65-199dbe6c0bca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260935364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4260935364
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.47034292
Short name T57
Test name
Test status
Simulation time 16234657081 ps
CPU time 362.1 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:45:47 PM PDT 24
Peak memory 269012 kb
Host smart-35562c17-565d-430f-b14d-9219902aa286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=47034292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.47034292
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1637995710
Short name T283
Test name
Test status
Simulation time 15228731 ps
CPU time 0.84 seconds
Started Apr 30 01:39:43 PM PDT 24
Finished Apr 30 01:39:44 PM PDT 24
Peak memory 208360 kb
Host smart-f8d1cce2-b495-476d-bc18-5ee8371ee4a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637995710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1637995710
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.492336784
Short name T554
Test name
Test status
Simulation time 329378754 ps
CPU time 0.92 seconds
Started Apr 30 01:39:57 PM PDT 24
Finished Apr 30 01:39:58 PM PDT 24
Peak memory 209408 kb
Host smart-b484f5bd-0572-4295-8d87-ffd4c1ff85f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492336784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.492336784
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2970673394
Short name T718
Test name
Test status
Simulation time 508247625 ps
CPU time 8.81 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:39:55 PM PDT 24
Peak memory 225904 kb
Host smart-e76c69f0-961c-4482-94cf-f4e7782ee6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970673394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2970673394
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2271511540
Short name T160
Test name
Test status
Simulation time 358470343 ps
CPU time 4.86 seconds
Started Apr 30 01:39:48 PM PDT 24
Finished Apr 30 01:39:53 PM PDT 24
Peak memory 216964 kb
Host smart-81e900ed-4b7f-4306-8f96-8f92f5e5218d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271511540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2271511540
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3558153825
Short name T849
Test name
Test status
Simulation time 88911165 ps
CPU time 3.97 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:39:51 PM PDT 24
Peak memory 217848 kb
Host smart-65511d45-3a2a-4b9d-baa5-a7e1fdd540c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558153825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3558153825
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2559513863
Short name T471
Test name
Test status
Simulation time 1935445717 ps
CPU time 20.61 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:40:06 PM PDT 24
Peak memory 217840 kb
Host smart-1ea46277-8f7d-49f5-a012-0e34f50d3f13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559513863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2559513863
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1203411107
Short name T386
Test name
Test status
Simulation time 420350533 ps
CPU time 10.11 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:39:56 PM PDT 24
Peak memory 217836 kb
Host smart-71aadea2-6633-4ce9-b66a-4213133f387d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203411107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1203411107
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1037247381
Short name T389
Test name
Test status
Simulation time 3384640881 ps
CPU time 8.57 seconds
Started Apr 30 01:39:44 PM PDT 24
Finished Apr 30 01:39:53 PM PDT 24
Peak memory 217936 kb
Host smart-af76da97-f48f-4ddd-a8e5-f8d6669e4c16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037247381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1037247381
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.490762619
Short name T756
Test name
Test status
Simulation time 2312978873 ps
CPU time 14.94 seconds
Started Apr 30 01:39:47 PM PDT 24
Finished Apr 30 01:40:03 PM PDT 24
Peak memory 217940 kb
Host smart-46deb9e8-97a9-44fc-8abd-9df54528b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490762619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.490762619
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.4046937055
Short name T75
Test name
Test status
Simulation time 42229123 ps
CPU time 2.1 seconds
Started Apr 30 01:39:49 PM PDT 24
Finished Apr 30 01:39:52 PM PDT 24
Peak memory 213796 kb
Host smart-f674903d-ed5d-4675-acc2-f0cd4514acdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046937055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.4046937055
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.841847451
Short name T726
Test name
Test status
Simulation time 249187877 ps
CPU time 21.77 seconds
Started Apr 30 01:39:46 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 250804 kb
Host smart-2e151e99-5aba-4bfd-92bb-42a1988b91c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841847451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.841847451
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2183427715
Short name T596
Test name
Test status
Simulation time 630583159 ps
CPU time 8.15 seconds
Started Apr 30 01:39:50 PM PDT 24
Finished Apr 30 01:39:59 PM PDT 24
Peak memory 250804 kb
Host smart-df8b321a-dda7-4d5c-8dc1-dd6f21b9f02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183427715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2183427715
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3808032266
Short name T55
Test name
Test status
Simulation time 5587360710 ps
CPU time 95.25 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:41:29 PM PDT 24
Peak memory 250780 kb
Host smart-1dd1a24f-3ae3-48d4-b5c2-671352a24f8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808032266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3808032266
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.4174743451
Short name T746
Test name
Test status
Simulation time 201189803466 ps
CPU time 5926.44 seconds
Started Apr 30 01:39:51 PM PDT 24
Finished Apr 30 03:18:39 PM PDT 24
Peak memory 1151856 kb
Host smart-13095e36-4bfe-4fec-aff4-d18a436d4c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4174743451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.4174743451
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.843154727
Short name T795
Test name
Test status
Simulation time 117394907 ps
CPU time 0.89 seconds
Started Apr 30 01:39:43 PM PDT 24
Finished Apr 30 01:39:45 PM PDT 24
Peak memory 211468 kb
Host smart-55813872-a78c-42fb-94d9-31178b39a2d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843154727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.843154727
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1052973901
Short name T836
Test name
Test status
Simulation time 15917687 ps
CPU time 1 seconds
Started Apr 30 01:37:39 PM PDT 24
Finished Apr 30 01:37:41 PM PDT 24
Peak memory 209436 kb
Host smart-f3499c6c-afcb-4d2e-b8c3-66983fd7464c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052973901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1052973901
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.22267064
Short name T382
Test name
Test status
Simulation time 2628423313 ps
CPU time 17.01 seconds
Started Apr 30 01:37:31 PM PDT 24
Finished Apr 30 01:37:48 PM PDT 24
Peak memory 218056 kb
Host smart-95280ded-d3f7-4d0f-b46d-76a5f5140b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22267064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.22267064
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1382748756
Short name T594
Test name
Test status
Simulation time 247396077 ps
CPU time 2.89 seconds
Started Apr 30 01:37:33 PM PDT 24
Finished Apr 30 01:37:36 PM PDT 24
Peak memory 209432 kb
Host smart-85675c9b-d6d5-4f43-a2ca-2e0e20dc36a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382748756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1382748756
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3512185400
Short name T817
Test name
Test status
Simulation time 9559589570 ps
CPU time 38.37 seconds
Started Apr 30 01:37:34 PM PDT 24
Finished Apr 30 01:38:13 PM PDT 24
Peak memory 218860 kb
Host smart-5208e845-7790-4321-8cf6-c1919667cb8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512185400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3512185400
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.820336980
Short name T743
Test name
Test status
Simulation time 1495423971 ps
CPU time 14.43 seconds
Started Apr 30 01:37:33 PM PDT 24
Finished Apr 30 01:37:49 PM PDT 24
Peak memory 217616 kb
Host smart-cd3e17b4-5fa6-455f-951c-dc54e8094774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820336980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.820336980
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3530957724
Short name T281
Test name
Test status
Simulation time 347008697 ps
CPU time 10.41 seconds
Started Apr 30 01:37:31 PM PDT 24
Finished Apr 30 01:37:42 PM PDT 24
Peak memory 217760 kb
Host smart-4fb498dc-9aba-494a-9e9b-f25a09e6375a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530957724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3530957724
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1622159113
Short name T673
Test name
Test status
Simulation time 23091331638 ps
CPU time 15.01 seconds
Started Apr 30 01:37:37 PM PDT 24
Finished Apr 30 01:37:52 PM PDT 24
Peak memory 213704 kb
Host smart-5d555bae-5de8-4d8f-9731-ccef79ba39a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622159113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1622159113
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1972610989
Short name T260
Test name
Test status
Simulation time 607558398 ps
CPU time 5.5 seconds
Started Apr 30 01:37:33 PM PDT 24
Finished Apr 30 01:37:39 PM PDT 24
Peak memory 213388 kb
Host smart-8a93dfe3-d386-42d0-a141-b5201f3b1ad8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972610989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1972610989
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3780554408
Short name T394
Test name
Test status
Simulation time 1827184948 ps
CPU time 46.72 seconds
Started Apr 30 01:37:32 PM PDT 24
Finished Apr 30 01:38:20 PM PDT 24
Peak memory 274272 kb
Host smart-bf2d049f-18a4-4bc8-ad6f-ad983babe8c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780554408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3780554408
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3606575579
Short name T418
Test name
Test status
Simulation time 1593340203 ps
CPU time 13.42 seconds
Started Apr 30 01:37:32 PM PDT 24
Finished Apr 30 01:37:45 PM PDT 24
Peak memory 223932 kb
Host smart-db35c576-5029-48ce-8c12-466fc707d33f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606575579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3606575579
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.860500692
Short name T458
Test name
Test status
Simulation time 659578261 ps
CPU time 6.48 seconds
Started Apr 30 01:37:32 PM PDT 24
Finished Apr 30 01:37:40 PM PDT 24
Peak memory 217812 kb
Host smart-978da7c8-da13-461b-bc27-c6c7353f370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860500692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.860500692
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.898856568
Short name T781
Test name
Test status
Simulation time 3111466306 ps
CPU time 10.52 seconds
Started Apr 30 01:37:32 PM PDT 24
Finished Apr 30 01:37:44 PM PDT 24
Peak memory 214436 kb
Host smart-974c05cf-ec5e-4f13-9879-f545ec444724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898856568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.898856568
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.272038312
Short name T48
Test name
Test status
Simulation time 403300200 ps
CPU time 25.93 seconds
Started Apr 30 01:37:33 PM PDT 24
Finished Apr 30 01:38:00 PM PDT 24
Peak memory 280756 kb
Host smart-f310af13-8398-4ecc-9058-20125e5e3567
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272038312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.272038312
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1223087118
Short name T540
Test name
Test status
Simulation time 841039218 ps
CPU time 15.39 seconds
Started Apr 30 01:37:34 PM PDT 24
Finished Apr 30 01:37:50 PM PDT 24
Peak memory 218764 kb
Host smart-768c90ab-395c-4264-9695-04fa5fa18837
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223087118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1223087118
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3994896479
Short name T847
Test name
Test status
Simulation time 834534936 ps
CPU time 16.91 seconds
Started Apr 30 01:37:32 PM PDT 24
Finished Apr 30 01:37:50 PM PDT 24
Peak memory 217812 kb
Host smart-5c9e491a-ded0-4cc3-95a9-8822eded60d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994896479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3994896479
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2286382233
Short name T745
Test name
Test status
Simulation time 316622068 ps
CPU time 11.65 seconds
Started Apr 30 01:37:33 PM PDT 24
Finished Apr 30 01:37:45 PM PDT 24
Peak memory 217852 kb
Host smart-8c4267f6-bfed-4702-aafc-40f44cd95002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286382233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
286382233
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3375212338
Short name T744
Test name
Test status
Simulation time 509058664 ps
CPU time 16.33 seconds
Started Apr 30 01:37:34 PM PDT 24
Finished Apr 30 01:37:51 PM PDT 24
Peak memory 217852 kb
Host smart-1f1d58cd-a4b1-4e6a-975c-a3e756ffef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375212338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3375212338
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.766013219
Short name T476
Test name
Test status
Simulation time 21816190 ps
CPU time 1.45 seconds
Started Apr 30 01:37:30 PM PDT 24
Finished Apr 30 01:37:32 PM PDT 24
Peak memory 217560 kb
Host smart-a4434ff3-29d9-43d6-a26c-b3c363863cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766013219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.766013219
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2628917437
Short name T466
Test name
Test status
Simulation time 230306079 ps
CPU time 26.63 seconds
Started Apr 30 01:37:36 PM PDT 24
Finished Apr 30 01:38:03 PM PDT 24
Peak memory 248656 kb
Host smart-0787c0ff-f8ef-4ff2-825f-23cae1910867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628917437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2628917437
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3650872602
Short name T143
Test name
Test status
Simulation time 121502757 ps
CPU time 4.57 seconds
Started Apr 30 01:37:33 PM PDT 24
Finished Apr 30 01:37:38 PM PDT 24
Peak memory 222560 kb
Host smart-c63f259c-68a2-4f80-b3e8-ed00ba97eeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650872602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3650872602
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2889438282
Short name T557
Test name
Test status
Simulation time 8102665698 ps
CPU time 145.93 seconds
Started Apr 30 01:37:34 PM PDT 24
Finished Apr 30 01:40:00 PM PDT 24
Peak memory 270936 kb
Host smart-9593d40d-6e36-4a04-8cbc-8cc59ce86aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889438282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2889438282
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2733710048
Short name T647
Test name
Test status
Simulation time 13912130 ps
CPU time 1.06 seconds
Started Apr 30 01:37:31 PM PDT 24
Finished Apr 30 01:37:33 PM PDT 24
Peak memory 211464 kb
Host smart-753825de-ae09-4f8d-b638-3a8e6a114ca5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733710048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2733710048
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2676305089
Short name T762
Test name
Test status
Simulation time 62748028 ps
CPU time 1.05 seconds
Started Apr 30 01:39:51 PM PDT 24
Finished Apr 30 01:39:52 PM PDT 24
Peak memory 209412 kb
Host smart-1be933bf-d581-4285-82cc-e6b7367c301d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676305089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2676305089
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1092642190
Short name T227
Test name
Test status
Simulation time 248392230 ps
CPU time 10.35 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:07 PM PDT 24
Peak memory 217820 kb
Host smart-25305b8e-3aab-4d88-b09b-a6e34f29807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092642190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1092642190
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.4223469566
Short name T768
Test name
Test status
Simulation time 144794624 ps
CPU time 1.72 seconds
Started Apr 30 01:39:51 PM PDT 24
Finished Apr 30 01:39:53 PM PDT 24
Peak memory 209516 kb
Host smart-cf47b55b-30bb-4633-bf12-23c1b59c01c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223469566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.4223469566
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1659467240
Short name T612
Test name
Test status
Simulation time 75111509 ps
CPU time 2.79 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:39:57 PM PDT 24
Peak memory 217920 kb
Host smart-316dce5e-7471-415d-a14a-ab7c76ae41a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659467240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1659467240
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3661369888
Short name T39
Test name
Test status
Simulation time 290395039 ps
CPU time 13.69 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 218756 kb
Host smart-2863a7d3-064e-42cc-89dc-33f182c9daf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661369888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3661369888
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.769188894
Short name T491
Test name
Test status
Simulation time 476816788 ps
CPU time 12.73 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:07 PM PDT 24
Peak memory 217872 kb
Host smart-b79532e2-650d-4950-b2ec-79af55218f6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769188894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.769188894
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3383846180
Short name T349
Test name
Test status
Simulation time 359603387 ps
CPU time 14.06 seconds
Started Apr 30 01:39:57 PM PDT 24
Finished Apr 30 01:40:12 PM PDT 24
Peak memory 217788 kb
Host smart-51cbee92-20e0-48b6-ac0c-c9fc4b50c2b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383846180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3383846180
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.304544689
Short name T796
Test name
Test status
Simulation time 668104855 ps
CPU time 13.38 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 217800 kb
Host smart-0b1d89e9-255e-41da-9f6a-15005fa52f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304544689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.304544689
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.106780296
Short name T232
Test name
Test status
Simulation time 1393583804 ps
CPU time 2.83 seconds
Started Apr 30 01:39:52 PM PDT 24
Finished Apr 30 01:39:56 PM PDT 24
Peak memory 214228 kb
Host smart-067b85df-0ee6-4ebd-832b-27fdd605356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106780296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.106780296
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2512528346
Short name T430
Test name
Test status
Simulation time 1102700142 ps
CPU time 31.4 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 250816 kb
Host smart-8db72c3b-fd5e-457f-bbfa-b69e01ccb135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512528346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2512528346
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.375943008
Short name T255
Test name
Test status
Simulation time 526006241 ps
CPU time 7.72 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:01 PM PDT 24
Peak memory 247172 kb
Host smart-b89b99e8-42be-440d-9522-15a7003dd2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375943008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.375943008
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3548997235
Short name T558
Test name
Test status
Simulation time 11797671605 ps
CPU time 140.85 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:42:14 PM PDT 24
Peak memory 229380 kb
Host smart-f3b2c0a1-c487-4a96-bdc3-f6efb98338ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548997235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3548997235
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2222859249
Short name T383
Test name
Test status
Simulation time 20216444 ps
CPU time 1.08 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:39:55 PM PDT 24
Peak memory 211412 kb
Host smart-c0897939-f532-4413-9084-0e1085f9c23a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222859249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2222859249
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.489492811
Short name T306
Test name
Test status
Simulation time 31470123 ps
CPU time 1.06 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:39:58 PM PDT 24
Peak memory 209428 kb
Host smart-9cba09fd-3808-46e1-94f1-a09dbe7b0743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489492811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.489492811
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1452182934
Short name T133
Test name
Test status
Simulation time 4202453063 ps
CPU time 18.52 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 218832 kb
Host smart-97e42e42-2757-4354-8e7e-c6970b71a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452182934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1452182934
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2466739655
Short name T23
Test name
Test status
Simulation time 2993727804 ps
CPU time 11.36 seconds
Started Apr 30 01:39:55 PM PDT 24
Finished Apr 30 01:40:07 PM PDT 24
Peak memory 217308 kb
Host smart-40ed5984-a749-4ae4-b663-20e7a7f72efe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466739655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2466739655
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.109616848
Short name T553
Test name
Test status
Simulation time 95592654 ps
CPU time 4.26 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:01 PM PDT 24
Peak memory 217796 kb
Host smart-47378fbe-e1c9-4bf1-8945-07924b715676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109616848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.109616848
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.106331463
Short name T506
Test name
Test status
Simulation time 443432220 ps
CPU time 7.76 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:01 PM PDT 24
Peak memory 217812 kb
Host smart-c093a9f3-ad31-4a53-b582-224828a7d34c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106331463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.106331463
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.734878827
Short name T856
Test name
Test status
Simulation time 1834053100 ps
CPU time 8.69 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:02 PM PDT 24
Peak memory 217800 kb
Host smart-6f230b3f-1980-4acf-ad5b-802f48d8bb8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734878827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.734878827
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.826739351
Short name T250
Test name
Test status
Simulation time 360601004 ps
CPU time 12.82 seconds
Started Apr 30 01:39:52 PM PDT 24
Finished Apr 30 01:40:06 PM PDT 24
Peak memory 225564 kb
Host smart-ab64d6e4-32d9-43d4-8a19-8d30f3282fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826739351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.826739351
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2209436868
Short name T788
Test name
Test status
Simulation time 37616403 ps
CPU time 1.93 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:39:56 PM PDT 24
Peak memory 213724 kb
Host smart-dd9f7472-c327-4e1c-8cbb-47e752037ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209436868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2209436868
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1968017004
Short name T351
Test name
Test status
Simulation time 2391212112 ps
CPU time 22.57 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 250864 kb
Host smart-231d6487-c453-498c-b6a0-0d1f14b7886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968017004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1968017004
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4178774375
Short name T686
Test name
Test status
Simulation time 80627557 ps
CPU time 8.46 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:05 PM PDT 24
Peak memory 250372 kb
Host smart-9492a7f9-9446-44c0-9f9e-c952e5bee04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178774375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4178774375
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.4067259398
Short name T201
Test name
Test status
Simulation time 14807463936 ps
CPU time 64.44 seconds
Started Apr 30 01:39:51 PM PDT 24
Finished Apr 30 01:40:56 PM PDT 24
Peak memory 280148 kb
Host smart-6ac5d470-0d7c-44b8-9e30-82eb7fcfad2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067259398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.4067259398
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4025044158
Short name T356
Test name
Test status
Simulation time 49945588 ps
CPU time 0.91 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:39:58 PM PDT 24
Peak memory 208680 kb
Host smart-6c229933-cee2-4452-beba-26bbd0ef684a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025044158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4025044158
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3962561943
Short name T597
Test name
Test status
Simulation time 56863327 ps
CPU time 0.88 seconds
Started Apr 30 01:39:58 PM PDT 24
Finished Apr 30 01:39:59 PM PDT 24
Peak memory 209340 kb
Host smart-b390a457-2ae8-484a-887b-14f9d6e3a02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962561943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3962561943
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3389821416
Short name T833
Test name
Test status
Simulation time 809368084 ps
CPU time 11.08 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 225960 kb
Host smart-b89e3c5f-90ab-4715-8def-5cb6020e7c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389821416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3389821416
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1434062911
Short name T297
Test name
Test status
Simulation time 158621902 ps
CPU time 2.38 seconds
Started Apr 30 01:39:55 PM PDT 24
Finished Apr 30 01:39:58 PM PDT 24
Peak memory 209464 kb
Host smart-007ea388-0d4a-46cf-9168-e144860c628f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434062911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1434062911
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3871819723
Short name T642
Test name
Test status
Simulation time 682103944 ps
CPU time 4.1 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:39:59 PM PDT 24
Peak memory 217848 kb
Host smart-dc32f9e3-8b4d-41c4-a0dc-37fb2f1828e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871819723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3871819723
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1253832647
Short name T53
Test name
Test status
Simulation time 1609801436 ps
CPU time 12.61 seconds
Started Apr 30 01:39:57 PM PDT 24
Finished Apr 30 01:40:10 PM PDT 24
Peak memory 225852 kb
Host smart-b8fa8713-3129-4f37-bef0-ccff1f7a0cde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253832647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1253832647
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3927141788
Short name T289
Test name
Test status
Simulation time 3782835476 ps
CPU time 10.57 seconds
Started Apr 30 01:39:57 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 217940 kb
Host smart-4e9decd1-5651-47c0-8e5d-f2ed98274693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927141788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3927141788
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2828740265
Short name T223
Test name
Test status
Simulation time 300585640 ps
CPU time 7.98 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:02 PM PDT 24
Peak memory 217828 kb
Host smart-8a04eaf1-f83e-48da-9e0d-2017a0b932cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828740265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2828740265
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1020149159
Short name T837
Test name
Test status
Simulation time 775717930 ps
CPU time 6.46 seconds
Started Apr 30 01:39:53 PM PDT 24
Finished Apr 30 01:40:01 PM PDT 24
Peak memory 224040 kb
Host smart-5c27ed82-33a8-4bf1-9c79-5604908f1e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020149159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1020149159
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2215637206
Short name T305
Test name
Test status
Simulation time 57025058 ps
CPU time 4.51 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:39:59 PM PDT 24
Peak memory 214544 kb
Host smart-69e4409d-0254-4250-94cd-7c06b723b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215637206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2215637206
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1057057786
Short name T771
Test name
Test status
Simulation time 1203971543 ps
CPU time 29.96 seconds
Started Apr 30 01:39:52 PM PDT 24
Finished Apr 30 01:40:23 PM PDT 24
Peak memory 250728 kb
Host smart-35a12dbc-2231-44ba-a258-05c9a246e718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057057786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1057057786
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3321169651
Short name T366
Test name
Test status
Simulation time 228425964 ps
CPU time 2.86 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:00 PM PDT 24
Peak memory 217796 kb
Host smart-f38bd7aa-3b9c-42b0-add5-9cd07c551798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321169651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3321169651
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3579235038
Short name T852
Test name
Test status
Simulation time 5663427063 ps
CPU time 103.84 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:41:41 PM PDT 24
Peak memory 283664 kb
Host smart-d2267096-babf-4a49-a4d5-bcb17e86cdf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579235038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3579235038
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3209147464
Short name T757
Test name
Test status
Simulation time 61004476 ps
CPU time 0.91 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:39:55 PM PDT 24
Peak memory 208492 kb
Host smart-93d4dd62-e681-4d1e-8316-cd27b267da9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209147464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3209147464
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.4153575282
Short name T205
Test name
Test status
Simulation time 56437834 ps
CPU time 0.89 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:03 PM PDT 24
Peak memory 209312 kb
Host smart-cd2b5d3e-ceb1-4a65-9249-58cfcf68ef06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153575282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4153575282
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2295684075
Short name T650
Test name
Test status
Simulation time 1020657168 ps
CPU time 15 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:12 PM PDT 24
Peak memory 217792 kb
Host smart-c3a17624-63f5-4252-8c47-1b794015524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295684075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2295684075
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4088230304
Short name T332
Test name
Test status
Simulation time 3392628630 ps
CPU time 9.74 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:12 PM PDT 24
Peak memory 209476 kb
Host smart-26344730-5bf5-4345-a8d7-83f1b10725a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088230304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4088230304
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3961308226
Short name T710
Test name
Test status
Simulation time 127051129 ps
CPU time 2.46 seconds
Started Apr 30 01:39:57 PM PDT 24
Finished Apr 30 01:40:00 PM PDT 24
Peak memory 217828 kb
Host smart-6f063b32-91d4-48b0-883c-3329e1ce66e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961308226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3961308226
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.195450681
Short name T790
Test name
Test status
Simulation time 261702565 ps
CPU time 10.87 seconds
Started Apr 30 01:40:00 PM PDT 24
Finished Apr 30 01:40:11 PM PDT 24
Peak memory 217972 kb
Host smart-e44a3242-a46f-494d-b52e-f707498af973
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195450681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.195450681
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2544961075
Short name T441
Test name
Test status
Simulation time 1117384558 ps
CPU time 13 seconds
Started Apr 30 01:40:03 PM PDT 24
Finished Apr 30 01:40:17 PM PDT 24
Peak memory 217856 kb
Host smart-67fb11cf-c514-48ec-9126-9fed032c77b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544961075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2544961075
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1415014056
Short name T384
Test name
Test status
Simulation time 1314155678 ps
CPU time 16.05 seconds
Started Apr 30 01:40:00 PM PDT 24
Finished Apr 30 01:40:17 PM PDT 24
Peak memory 217880 kb
Host smart-145e5128-de6a-4934-ae60-fb301b673077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415014056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1415014056
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.76371184
Short name T46
Test name
Test status
Simulation time 2184806032 ps
CPU time 11.43 seconds
Started Apr 30 01:39:56 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 217984 kb
Host smart-625f0a26-e8bc-49ad-ad95-644463779d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76371184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.76371184
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1921308952
Short name T268
Test name
Test status
Simulation time 927776924 ps
CPU time 13.33 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 217656 kb
Host smart-ef27043b-a78e-4c22-89e1-48c49d998d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921308952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1921308952
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2098606365
Short name T468
Test name
Test status
Simulation time 1244435172 ps
CPU time 24.96 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:40:19 PM PDT 24
Peak memory 245764 kb
Host smart-99d3f6e3-fd12-4d01-ac1a-c89a411fc0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098606365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2098606365
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2710605955
Short name T505
Test name
Test status
Simulation time 210290323 ps
CPU time 6.75 seconds
Started Apr 30 01:39:57 PM PDT 24
Finished Apr 30 01:40:04 PM PDT 24
Peak memory 246092 kb
Host smart-6707af23-cdfd-4080-a377-07fbb0c6042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710605955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2710605955
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3013258618
Short name T73
Test name
Test status
Simulation time 30012389300 ps
CPU time 297.97 seconds
Started Apr 30 01:40:05 PM PDT 24
Finished Apr 30 01:45:04 PM PDT 24
Peak memory 421016 kb
Host smart-14d081b0-e9ad-4d48-8ad1-9fb9440a3e40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013258618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3013258618
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.510491071
Short name T217
Test name
Test status
Simulation time 91557839 ps
CPU time 0.81 seconds
Started Apr 30 01:39:54 PM PDT 24
Finished Apr 30 01:39:55 PM PDT 24
Peak memory 208448 kb
Host smart-6eeeb666-53b0-4e79-bc60-ef8b7cda71a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510491071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.510491071
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3725928950
Short name T385
Test name
Test status
Simulation time 15116039 ps
CPU time 1.07 seconds
Started Apr 30 01:40:03 PM PDT 24
Finished Apr 30 01:40:05 PM PDT 24
Peak memory 209408 kb
Host smart-ae05504b-fb7a-486e-bd56-e19c9e31ea70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725928950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3725928950
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.769940831
Short name T314
Test name
Test status
Simulation time 278638806 ps
CPU time 8.68 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:11 PM PDT 24
Peak memory 217788 kb
Host smart-9a71d924-f7f8-41a9-8810-e4b2eab8111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769940831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.769940831
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3279003074
Short name T24
Test name
Test status
Simulation time 429174648 ps
CPU time 5.74 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:08 PM PDT 24
Peak memory 209400 kb
Host smart-219c50c2-a3e0-4203-b81a-b4a265f9de1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279003074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3279003074
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1098539757
Short name T696
Test name
Test status
Simulation time 1660972637 ps
CPU time 3.27 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:06 PM PDT 24
Peak memory 217892 kb
Host smart-3cb209cf-5085-49d3-b59c-818400639aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098539757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1098539757
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1999581596
Short name T423
Test name
Test status
Simulation time 1091476504 ps
CPU time 9.48 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:11 PM PDT 24
Peak memory 225880 kb
Host smart-26ee6bc7-51a3-45a5-98dd-baf08d9747c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999581596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1999581596
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2842241910
Short name T513
Test name
Test status
Simulation time 1797954067 ps
CPU time 18.11 seconds
Started Apr 30 01:40:06 PM PDT 24
Finished Apr 30 01:40:25 PM PDT 24
Peak memory 217796 kb
Host smart-db885d34-cc7b-4ffc-8a99-238b77081142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842241910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2842241910
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1412029052
Short name T810
Test name
Test status
Simulation time 1204429907 ps
CPU time 10.92 seconds
Started Apr 30 01:40:03 PM PDT 24
Finished Apr 30 01:40:15 PM PDT 24
Peak memory 217808 kb
Host smart-c2b9912b-fee8-4c1e-bf63-06b8e477be1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412029052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1412029052
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.128825825
Short name T827
Test name
Test status
Simulation time 279151245 ps
CPU time 9.16 seconds
Started Apr 30 01:40:06 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 224856 kb
Host smart-8a164ece-6a2d-4138-89ec-d5070c5ca559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128825825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.128825825
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.241093513
Short name T689
Test name
Test status
Simulation time 49464678 ps
CPU time 1.96 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:06 PM PDT 24
Peak memory 217572 kb
Host smart-37c4ebaf-d23d-4dfd-a0fc-337cfbb6dea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241093513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.241093513
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1336223372
Short name T638
Test name
Test status
Simulation time 1460472285 ps
CPU time 30.38 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:34 PM PDT 24
Peak memory 250820 kb
Host smart-e8a05ac5-5212-4115-9c2a-71ba001d17fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336223372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1336223372
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3918634339
Short name T339
Test name
Test status
Simulation time 223372474 ps
CPU time 7.21 seconds
Started Apr 30 01:40:05 PM PDT 24
Finished Apr 30 01:40:13 PM PDT 24
Peak memory 250756 kb
Host smart-f73cfeef-13b8-43b3-87f9-7f2de557bd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918634339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3918634339
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2037962868
Short name T806
Test name
Test status
Simulation time 5029789119 ps
CPU time 82.81 seconds
Started Apr 30 01:40:04 PM PDT 24
Finished Apr 30 01:41:28 PM PDT 24
Peak memory 245668 kb
Host smart-9186a1b9-6332-4d05-a214-f12021b2fa65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037962868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2037962868
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3408658442
Short name T41
Test name
Test status
Simulation time 26354588440 ps
CPU time 859.58 seconds
Started Apr 30 01:40:03 PM PDT 24
Finished Apr 30 01:54:24 PM PDT 24
Peak memory 284024 kb
Host smart-b777566a-da34-4377-8c4d-c006cf4f2c7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3408658442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3408658442
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.670123238
Short name T26
Test name
Test status
Simulation time 12488129 ps
CPU time 0.99 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:02 PM PDT 24
Peak memory 208476 kb
Host smart-ed542e25-50bd-40ae-a85f-67ba5a4be53b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670123238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.670123238
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2354602446
Short name T230
Test name
Test status
Simulation time 57116707 ps
CPU time 0.9 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:03 PM PDT 24
Peak memory 209412 kb
Host smart-2acd05ea-1752-418b-865a-eb334ae44683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354602446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2354602446
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2073525951
Short name T371
Test name
Test status
Simulation time 315957580 ps
CPU time 13.31 seconds
Started Apr 30 01:40:04 PM PDT 24
Finished Apr 30 01:40:19 PM PDT 24
Peak memory 217848 kb
Host smart-42eed178-5412-4e01-8a28-7b26bb11a785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073525951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2073525951
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2901696302
Short name T793
Test name
Test status
Simulation time 1502924639 ps
CPU time 18.45 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:22 PM PDT 24
Peak memory 217108 kb
Host smart-15e717c4-7c43-445b-804d-7a973e5b7244
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901696302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2901696302
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.387906684
Short name T367
Test name
Test status
Simulation time 75235170 ps
CPU time 1.82 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:05 PM PDT 24
Peak memory 217760 kb
Host smart-f2e22a13-9647-42f5-9206-ad13d3747e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387906684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.387906684
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.771338886
Short name T632
Test name
Test status
Simulation time 845801277 ps
CPU time 23.37 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:25 PM PDT 24
Peak memory 219008 kb
Host smart-c6b7c663-4883-4344-ad73-e082ce1a7bb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771338886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.771338886
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1285838503
Short name T493
Test name
Test status
Simulation time 1531756286 ps
CPU time 9.92 seconds
Started Apr 30 01:40:05 PM PDT 24
Finished Apr 30 01:40:15 PM PDT 24
Peak memory 217800 kb
Host smart-51665b42-adba-4320-92b2-90c1373870c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285838503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1285838503
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3622849265
Short name T59
Test name
Test status
Simulation time 1827877565 ps
CPU time 13.44 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 217828 kb
Host smart-3d056d37-e0a1-4f4b-9371-8463b56d6c63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622849265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3622849265
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1122171236
Short name T45
Test name
Test status
Simulation time 353966592 ps
CPU time 13.01 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:15 PM PDT 24
Peak memory 217920 kb
Host smart-8fd3fd58-e205-4f72-93f3-0c0da35255b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122171236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1122171236
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1143264745
Short name T783
Test name
Test status
Simulation time 72399811 ps
CPU time 2.43 seconds
Started Apr 30 01:40:03 PM PDT 24
Finished Apr 30 01:40:06 PM PDT 24
Peak memory 213520 kb
Host smart-54b5927f-ff10-4078-bd22-5ccda00bf681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143264745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1143264745
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.883441562
Short name T659
Test name
Test status
Simulation time 252242365 ps
CPU time 24.01 seconds
Started Apr 30 01:40:03 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 245984 kb
Host smart-c9de16b7-4558-4be9-8cc6-ee602dfc7ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883441562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.883441562
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3774940822
Short name T330
Test name
Test status
Simulation time 146045133 ps
CPU time 6.72 seconds
Started Apr 30 01:40:04 PM PDT 24
Finished Apr 30 01:40:11 PM PDT 24
Peak memory 242968 kb
Host smart-428c1207-3dca-4631-b5db-bc28f827b18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774940822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3774940822
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.350357502
Short name T274
Test name
Test status
Simulation time 11822379 ps
CPU time 1.08 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:05 PM PDT 24
Peak memory 211464 kb
Host smart-23cf5cd7-34e7-43f9-8e88-b11a73f501e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350357502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.350357502
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3172563385
Short name T401
Test name
Test status
Simulation time 25967355 ps
CPU time 0.85 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:13 PM PDT 24
Peak memory 209276 kb
Host smart-1df10850-2fdd-4cff-807d-5f8cf8139df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172563385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3172563385
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2609425049
Short name T797
Test name
Test status
Simulation time 759990368 ps
CPU time 7.47 seconds
Started Apr 30 01:40:06 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 217756 kb
Host smart-8053e997-f23e-4ba9-b405-5de0c03e0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609425049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2609425049
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.402093279
Short name T630
Test name
Test status
Simulation time 105821829 ps
CPU time 1.38 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:05 PM PDT 24
Peak memory 209440 kb
Host smart-11d3ddf3-aa14-44f9-a5ef-31b7bf29f770
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402093279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.402093279
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1490691689
Short name T90
Test name
Test status
Simulation time 48525210 ps
CPU time 2.21 seconds
Started Apr 30 01:40:01 PM PDT 24
Finished Apr 30 01:40:04 PM PDT 24
Peak memory 217748 kb
Host smart-c0a62a38-21b7-48db-90d4-97f095562a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490691689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1490691689
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3848108808
Short name T576
Test name
Test status
Simulation time 1261605432 ps
CPU time 10.07 seconds
Started Apr 30 01:40:05 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 225660 kb
Host smart-55f79847-32ac-44d1-a00b-1e847698d51d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848108808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3848108808
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2766211726
Short name T633
Test name
Test status
Simulation time 295419985 ps
CPU time 8.14 seconds
Started Apr 30 01:40:06 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 217856 kb
Host smart-f79aa2ef-4d88-43e3-8f91-fa51a8117142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766211726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2766211726
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1706432814
Short name T387
Test name
Test status
Simulation time 2160918579 ps
CPU time 17.56 seconds
Started Apr 30 01:40:05 PM PDT 24
Finished Apr 30 01:40:24 PM PDT 24
Peak memory 217840 kb
Host smart-c501f890-4b10-4052-8e98-ebe77609e50e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706432814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1706432814
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2656142082
Short name T814
Test name
Test status
Simulation time 91980136 ps
CPU time 1.54 seconds
Started Apr 30 01:40:02 PM PDT 24
Finished Apr 30 01:40:04 PM PDT 24
Peak memory 213452 kb
Host smart-84f96cf0-47a3-498d-a31b-4487dcdcffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656142082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2656142082
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3646636357
Short name T489
Test name
Test status
Simulation time 1005937836 ps
CPU time 30.5 seconds
Started Apr 30 01:40:04 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 246828 kb
Host smart-b666ce27-80d2-4923-83b5-4a1f9ed06cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646636357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3646636357
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2673800815
Short name T286
Test name
Test status
Simulation time 71914383 ps
CPU time 6.48 seconds
Started Apr 30 01:40:03 PM PDT 24
Finished Apr 30 01:40:11 PM PDT 24
Peak memory 242636 kb
Host smart-769331ea-99f8-4dcf-9430-5063ef51dedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673800815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2673800815
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3056727524
Short name T417
Test name
Test status
Simulation time 2753037670 ps
CPU time 131.37 seconds
Started Apr 30 01:40:13 PM PDT 24
Finished Apr 30 01:42:25 PM PDT 24
Peak memory 271408 kb
Host smart-e600b38a-417f-4bfe-8c28-dac9b1a0d8d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056727524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3056727524
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.142559775
Short name T688
Test name
Test status
Simulation time 61429732 ps
CPU time 0.93 seconds
Started Apr 30 01:40:06 PM PDT 24
Finished Apr 30 01:40:07 PM PDT 24
Peak memory 208676 kb
Host smart-9dea0c40-1d4b-4069-88c9-40904aac0ab9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142559775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.142559775
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2889883787
Short name T693
Test name
Test status
Simulation time 13100440 ps
CPU time 0.96 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:13 PM PDT 24
Peak memory 209440 kb
Host smart-0641a7d1-4b9a-4404-97bf-f985285953ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889883787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2889883787
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1951276133
Short name T839
Test name
Test status
Simulation time 898368541 ps
CPU time 8.29 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 225912 kb
Host smart-c3cc8e66-09d4-4b01-a773-cbde89e77970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951276133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1951276133
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3308159372
Short name T724
Test name
Test status
Simulation time 1164974919 ps
CPU time 6.55 seconds
Started Apr 30 01:40:13 PM PDT 24
Finished Apr 30 01:40:20 PM PDT 24
Peak memory 209412 kb
Host smart-34750162-db20-4993-9d68-94c435ac0406
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308159372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3308159372
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3127691074
Short name T736
Test name
Test status
Simulation time 177049578 ps
CPU time 2.15 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 217852 kb
Host smart-a2fe6f93-6843-46f5-8528-06b5b02aad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127691074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3127691074
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3586124883
Short name T658
Test name
Test status
Simulation time 1320411404 ps
CPU time 14.54 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 218824 kb
Host smart-0174d6c9-bd74-48de-94fe-d5230c1f5e85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586124883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3586124883
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1597009193
Short name T529
Test name
Test status
Simulation time 600168909 ps
CPU time 13.16 seconds
Started Apr 30 01:40:13 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 217832 kb
Host smart-0a4e6964-200f-4d45-a87d-97d017ec812d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597009193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1597009193
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1500226390
Short name T213
Test name
Test status
Simulation time 590572022 ps
CPU time 14.51 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 217752 kb
Host smart-9332881a-df36-4bf7-b918-65d812a849d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500226390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1500226390
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3023011312
Short name T256
Test name
Test status
Simulation time 232992067 ps
CPU time 9 seconds
Started Apr 30 01:40:10 PM PDT 24
Finished Apr 30 01:40:19 PM PDT 24
Peak memory 217868 kb
Host smart-0bb21790-78db-42ee-82f7-e091366b4b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023011312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3023011312
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3221324360
Short name T192
Test name
Test status
Simulation time 18757437 ps
CPU time 1.38 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 213396 kb
Host smart-f80e7d41-a88c-4a24-a8bd-c31c99c853d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221324360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3221324360
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2965464600
Short name T92
Test name
Test status
Simulation time 519233283 ps
CPU time 25.48 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:38 PM PDT 24
Peak memory 250900 kb
Host smart-ae76944b-de13-4cd3-9cbb-a4fb53b2c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965464600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2965464600
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3064753169
Short name T454
Test name
Test status
Simulation time 72303289 ps
CPU time 3.14 seconds
Started Apr 30 01:40:10 PM PDT 24
Finished Apr 30 01:40:13 PM PDT 24
Peak memory 226268 kb
Host smart-977377c4-d00c-45c6-900a-3c94e750cbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064753169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3064753169
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4207679808
Short name T800
Test name
Test status
Simulation time 4715872833 ps
CPU time 136.75 seconds
Started Apr 30 01:40:13 PM PDT 24
Finished Apr 30 01:42:30 PM PDT 24
Peak memory 273812 kb
Host smart-394cd580-90df-4553-a94c-5a2fe5403419
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207679808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4207679808
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2745943678
Short name T727
Test name
Test status
Simulation time 34506140 ps
CPU time 0.96 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 208480 kb
Host smart-606c30f6-8925-4c4b-b64a-9ac138f6d20a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745943678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2745943678
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.629886351
Short name T823
Test name
Test status
Simulation time 45626564 ps
CPU time 0.84 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:12 PM PDT 24
Peak memory 209424 kb
Host smart-46a2d1ea-dd89-4760-b7a1-2622476a7bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629886351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.629886351
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3873267603
Short name T325
Test name
Test status
Simulation time 390696919 ps
CPU time 11.87 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:24 PM PDT 24
Peak memory 217796 kb
Host smart-6c40551d-7838-452b-ae1e-522aa6c28008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873267603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3873267603
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2850700597
Short name T263
Test name
Test status
Simulation time 1914205562 ps
CPU time 11.38 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:24 PM PDT 24
Peak memory 209464 kb
Host smart-c18013e0-0f84-40b2-8eee-1e1c39e91968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850700597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2850700597
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2253806063
Short name T573
Test name
Test status
Simulation time 109055742 ps
CPU time 1.88 seconds
Started Apr 30 01:40:15 PM PDT 24
Finished Apr 30 01:40:18 PM PDT 24
Peak memory 217804 kb
Host smart-44298546-7117-41e4-9ce5-75b8dcee44ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253806063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2253806063
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4192737534
Short name T428
Test name
Test status
Simulation time 320009629 ps
CPU time 13.64 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 225908 kb
Host smart-ab1ac8c0-9114-4884-89c6-97ffcc11cfcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192737534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4192737534
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1826504347
Short name T89
Test name
Test status
Simulation time 1163962041 ps
CPU time 13.03 seconds
Started Apr 30 01:40:10 PM PDT 24
Finished Apr 30 01:40:24 PM PDT 24
Peak memory 217848 kb
Host smart-fb332b73-f30f-4258-ad60-b5185a2cf61f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826504347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1826504347
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2848678315
Short name T248
Test name
Test status
Simulation time 986990008 ps
CPU time 7.96 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:19 PM PDT 24
Peak memory 217768 kb
Host smart-4c4316b5-c143-44f8-ae43-787bae521227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848678315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2848678315
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3766396847
Short name T588
Test name
Test status
Simulation time 129058762 ps
CPU time 3.08 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 214364 kb
Host smart-fb468c65-12a0-405f-913e-9272bc530dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766396847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3766396847
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1071688631
Short name T335
Test name
Test status
Simulation time 678048374 ps
CPU time 27.8 seconds
Started Apr 30 01:40:10 PM PDT 24
Finished Apr 30 01:40:38 PM PDT 24
Peak memory 249364 kb
Host smart-8ec7c2c6-eb95-4c75-8010-427fe9b804e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071688631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1071688631
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.8578474
Short name T703
Test name
Test status
Simulation time 71486421 ps
CPU time 3.03 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 217796 kb
Host smart-160c3331-e721-45c5-aa14-226bbb0e189f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8578474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.8578474
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.4077003311
Short name T164
Test name
Test status
Simulation time 15137569102 ps
CPU time 90.31 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:41:43 PM PDT 24
Peak memory 277592 kb
Host smart-97df8fb9-38f6-47ca-87d3-0602b7507b16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077003311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.4077003311
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1602103157
Short name T486
Test name
Test status
Simulation time 44944604 ps
CPU time 0.91 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:13 PM PDT 24
Peak memory 209408 kb
Host smart-b2a4a9fb-4f39-4fce-8bbe-d5ed7a3b73dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602103157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1602103157
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.426755646
Short name T253
Test name
Test status
Simulation time 2239483303 ps
CPU time 8.97 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:22 PM PDT 24
Peak memory 226020 kb
Host smart-5eeaff05-380c-4900-8cbd-6ae7c7118f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426755646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.426755646
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2365368781
Short name T467
Test name
Test status
Simulation time 405213786 ps
CPU time 1.21 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:12 PM PDT 24
Peak memory 209436 kb
Host smart-81f91c31-6391-4f6c-aca3-30b7ee8fd50a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365368781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2365368781
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3003018319
Short name T635
Test name
Test status
Simulation time 71860599 ps
CPU time 3.19 seconds
Started Apr 30 01:40:15 PM PDT 24
Finished Apr 30 01:40:19 PM PDT 24
Peak memory 217876 kb
Host smart-6d73eb6d-9c17-47dd-894c-c463ef32c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003018319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3003018319
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.608582007
Short name T725
Test name
Test status
Simulation time 1483550481 ps
CPU time 12.25 seconds
Started Apr 30 01:40:17 PM PDT 24
Finished Apr 30 01:40:30 PM PDT 24
Peak memory 225416 kb
Host smart-a038c8d4-3b23-4c5f-a55a-bdfc4220cead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608582007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.608582007
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1050976192
Short name T722
Test name
Test status
Simulation time 3575088540 ps
CPU time 8.27 seconds
Started Apr 30 01:40:14 PM PDT 24
Finished Apr 30 01:40:23 PM PDT 24
Peak memory 217932 kb
Host smart-811fb113-46b8-46bf-81c6-575c021d1a50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050976192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1050976192
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1515735785
Short name T350
Test name
Test status
Simulation time 1419398045 ps
CPU time 11.77 seconds
Started Apr 30 01:40:15 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 217808 kb
Host smart-32dc8983-7201-4266-8ef8-edc350c34f15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515735785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1515735785
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1984181654
Short name T183
Test name
Test status
Simulation time 550223528 ps
CPU time 8.6 seconds
Started Apr 30 01:40:15 PM PDT 24
Finished Apr 30 01:40:24 PM PDT 24
Peak memory 217892 kb
Host smart-bb887b5b-e91b-49a0-b251-98f79d41e31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984181654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1984181654
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3375811903
Short name T303
Test name
Test status
Simulation time 37045475 ps
CPU time 1.76 seconds
Started Apr 30 01:40:12 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 213576 kb
Host smart-3c295ef9-3643-4f65-b474-1891118234c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375811903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3375811903
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3867872306
Short name T280
Test name
Test status
Simulation time 1706811474 ps
CPU time 27.24 seconds
Started Apr 30 01:40:13 PM PDT 24
Finished Apr 30 01:40:41 PM PDT 24
Peak memory 245388 kb
Host smart-e964200e-cac1-4990-a926-5c51c60fd561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867872306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3867872306
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2970227790
Short name T32
Test name
Test status
Simulation time 94543208 ps
CPU time 6.83 seconds
Started Apr 30 01:40:13 PM PDT 24
Finished Apr 30 01:40:20 PM PDT 24
Peak memory 250736 kb
Host smart-53379b48-72db-4a64-8fbd-5492f9da21a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970227790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2970227790
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2823088994
Short name T475
Test name
Test status
Simulation time 9334037584 ps
CPU time 147.4 seconds
Started Apr 30 01:40:17 PM PDT 24
Finished Apr 30 01:42:45 PM PDT 24
Peak memory 267268 kb
Host smart-d06b7706-888d-4802-9c00-a33a0c2649b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823088994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2823088994
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1549351224
Short name T79
Test name
Test status
Simulation time 110620947 ps
CPU time 1.02 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:12 PM PDT 24
Peak memory 211444 kb
Host smart-5bfe94f1-8c6f-4214-94b0-73eda1ef117a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549351224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1549351224
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2839775130
Short name T198
Test name
Test status
Simulation time 26477242 ps
CPU time 0.82 seconds
Started Apr 30 01:37:42 PM PDT 24
Finished Apr 30 01:37:44 PM PDT 24
Peak memory 209328 kb
Host smart-3c3a2ec9-0002-4c5e-a306-16c3d4980ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839775130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2839775130
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1353221315
Short name T656
Test name
Test status
Simulation time 1185969227 ps
CPU time 13.65 seconds
Started Apr 30 01:37:39 PM PDT 24
Finished Apr 30 01:37:54 PM PDT 24
Peak memory 218016 kb
Host smart-f961da40-890a-49a5-941d-08f501839b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353221315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1353221315
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1512050531
Short name T702
Test name
Test status
Simulation time 737906118 ps
CPU time 9.02 seconds
Started Apr 30 01:37:41 PM PDT 24
Finished Apr 30 01:37:50 PM PDT 24
Peak memory 217636 kb
Host smart-14de9d8e-93c9-4688-8840-97d8eff65c0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512050531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1512050531
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.524077872
Short name T434
Test name
Test status
Simulation time 5562287200 ps
CPU time 44.88 seconds
Started Apr 30 01:37:39 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 218824 kb
Host smart-11a4339a-484e-4647-950c-5ed91ee4ebca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524077872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.524077872
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3797810024
Short name T449
Test name
Test status
Simulation time 2527335030 ps
CPU time 10.06 seconds
Started Apr 30 01:37:43 PM PDT 24
Finished Apr 30 01:37:54 PM PDT 24
Peak memory 217540 kb
Host smart-8604d61e-6739-48a3-89ae-923a7521d9a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797810024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
797810024
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3050471108
Short name T536
Test name
Test status
Simulation time 139834018 ps
CPU time 4.76 seconds
Started Apr 30 01:37:41 PM PDT 24
Finished Apr 30 01:37:46 PM PDT 24
Peak memory 217868 kb
Host smart-d0b78ca0-89e8-4b52-88ec-79e14b8bf817
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050471108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3050471108
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2352217315
Short name T828
Test name
Test status
Simulation time 7169246664 ps
CPU time 17.4 seconds
Started Apr 30 01:37:41 PM PDT 24
Finished Apr 30 01:38:00 PM PDT 24
Peak memory 213820 kb
Host smart-4c0f41bd-634b-4409-8ec6-2334a15ef76f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352217315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2352217315
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.209988131
Short name T448
Test name
Test status
Simulation time 155561252 ps
CPU time 5.42 seconds
Started Apr 30 01:37:41 PM PDT 24
Finished Apr 30 01:37:47 PM PDT 24
Peak memory 213200 kb
Host smart-6af7c052-1766-4178-b044-4d4b79abc044
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209988131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.209988131
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3597599441
Short name T623
Test name
Test status
Simulation time 2723719847 ps
CPU time 77.28 seconds
Started Apr 30 01:37:43 PM PDT 24
Finished Apr 30 01:39:01 PM PDT 24
Peak memory 272960 kb
Host smart-c30238a1-6931-4aa7-8ae4-64f58e41b91d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597599441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3597599441
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3148249955
Short name T407
Test name
Test status
Simulation time 4622711262 ps
CPU time 36.9 seconds
Started Apr 30 01:37:41 PM PDT 24
Finished Apr 30 01:38:18 PM PDT 24
Peak memory 250836 kb
Host smart-5d96afa3-505f-4a7c-a2d7-b6f89c140daa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148249955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3148249955
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1467580715
Short name T634
Test name
Test status
Simulation time 52045707 ps
CPU time 1.59 seconds
Started Apr 30 01:37:43 PM PDT 24
Finished Apr 30 01:37:46 PM PDT 24
Peak memory 217920 kb
Host smart-56a08310-3013-47b9-87bd-20040b28306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467580715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1467580715
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3453065818
Short name T778
Test name
Test status
Simulation time 631265740 ps
CPU time 11.63 seconds
Started Apr 30 01:37:40 PM PDT 24
Finished Apr 30 01:37:53 PM PDT 24
Peak memory 217712 kb
Host smart-eaa37ed4-0124-4763-a40f-2378caa3e725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453065818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3453065818
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2292036035
Short name T187
Test name
Test status
Simulation time 884663303 ps
CPU time 9.07 seconds
Started Apr 30 01:37:41 PM PDT 24
Finished Apr 30 01:37:51 PM PDT 24
Peak memory 225944 kb
Host smart-ded9ce49-1f3f-4017-9d9a-248f5b1a1a43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292036035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2292036035
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.683140947
Short name T470
Test name
Test status
Simulation time 865843114 ps
CPU time 15.43 seconds
Started Apr 30 01:37:40 PM PDT 24
Finished Apr 30 01:37:56 PM PDT 24
Peak memory 217748 kb
Host smart-a8ee5a5d-e555-429e-a011-a064f7766e09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683140947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.683140947
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3988023287
Short name T424
Test name
Test status
Simulation time 800653103 ps
CPU time 9.17 seconds
Started Apr 30 01:37:44 PM PDT 24
Finished Apr 30 01:37:54 PM PDT 24
Peak memory 217848 kb
Host smart-b54af91a-6f3b-49bf-afbe-7938c244890c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988023287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
988023287
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3132783277
Short name T433
Test name
Test status
Simulation time 360924187 ps
CPU time 13.74 seconds
Started Apr 30 01:37:42 PM PDT 24
Finished Apr 30 01:37:57 PM PDT 24
Peak memory 224800 kb
Host smart-4ba5820a-770a-4e63-af13-8f39d4f4d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132783277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3132783277
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1150872992
Short name T78
Test name
Test status
Simulation time 536785666 ps
CPU time 3.15 seconds
Started Apr 30 01:37:43 PM PDT 24
Finished Apr 30 01:37:47 PM PDT 24
Peak memory 213944 kb
Host smart-bb996731-8d14-4da7-9753-014ad4d0b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150872992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1150872992
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2085910735
Short name T358
Test name
Test status
Simulation time 137312839 ps
CPU time 19.73 seconds
Started Apr 30 01:37:44 PM PDT 24
Finished Apr 30 01:38:05 PM PDT 24
Peak memory 250836 kb
Host smart-c27d15c0-701c-4b33-b1c5-a891bf510d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085910735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2085910735
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2425462757
Short name T397
Test name
Test status
Simulation time 44835798 ps
CPU time 5.64 seconds
Started Apr 30 01:37:44 PM PDT 24
Finished Apr 30 01:37:50 PM PDT 24
Peak memory 242556 kb
Host smart-16599d9b-d6fc-467d-ba10-0c0b5c42c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425462757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2425462757
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1012794320
Short name T369
Test name
Test status
Simulation time 3938058341 ps
CPU time 154.07 seconds
Started Apr 30 01:37:41 PM PDT 24
Finished Apr 30 01:40:16 PM PDT 24
Peak memory 276872 kb
Host smart-7c1546eb-46f2-4114-b259-76b623879e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012794320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1012794320
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2182267569
Short name T508
Test name
Test status
Simulation time 23233449 ps
CPU time 0.87 seconds
Started Apr 30 01:37:42 PM PDT 24
Finished Apr 30 01:37:44 PM PDT 24
Peak memory 208604 kb
Host smart-feaae1e3-549e-49db-8b41-181e0dd761e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182267569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2182267569
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2903445710
Short name T426
Test name
Test status
Simulation time 66539480 ps
CPU time 1.13 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:37:52 PM PDT 24
Peak memory 209516 kb
Host smart-15784462-cfb7-482f-a1ad-064578ea04e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903445710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2903445710
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3099575224
Short name T811
Test name
Test status
Simulation time 1912057097 ps
CPU time 11.67 seconds
Started Apr 30 01:37:39 PM PDT 24
Finished Apr 30 01:37:52 PM PDT 24
Peak memory 217808 kb
Host smart-d7fd1296-bd1c-403c-b7fa-59152737117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099575224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3099575224
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.590613148
Short name T345
Test name
Test status
Simulation time 253228704 ps
CPU time 7.56 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:00 PM PDT 24
Peak memory 209424 kb
Host smart-663ccd7e-94ae-4481-b26b-df645d94d08b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590613148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.590613148
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.558152890
Short name T453
Test name
Test status
Simulation time 1296045351 ps
CPU time 20.52 seconds
Started Apr 30 01:37:49 PM PDT 24
Finished Apr 30 01:38:11 PM PDT 24
Peak memory 217736 kb
Host smart-0b860b64-3690-4710-9157-3c24d2828a6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558152890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.558152890
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2532212477
Short name T344
Test name
Test status
Simulation time 400676972 ps
CPU time 4.07 seconds
Started Apr 30 01:37:49 PM PDT 24
Finished Apr 30 01:37:54 PM PDT 24
Peak memory 217684 kb
Host smart-00ac4f88-357d-4d12-8516-66ac7a8546f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532212477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
532212477
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2202923422
Short name T572
Test name
Test status
Simulation time 391610130 ps
CPU time 11.96 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:03 PM PDT 24
Peak memory 217732 kb
Host smart-5c344249-a4cc-4791-b1d3-b6968ae1c82f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202923422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2202923422
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.949270332
Short name T735
Test name
Test status
Simulation time 2830513206 ps
CPU time 20.01 seconds
Started Apr 30 01:37:49 PM PDT 24
Finished Apr 30 01:38:10 PM PDT 24
Peak memory 213316 kb
Host smart-332fa672-d9fe-4318-a346-9bc22079b7b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949270332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.949270332
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3238838994
Short name T267
Test name
Test status
Simulation time 790304291 ps
CPU time 11.06 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:03 PM PDT 24
Peak memory 213352 kb
Host smart-ae437904-4a0e-48f2-b153-f6564098df83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238838994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3238838994
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2722759231
Short name T425
Test name
Test status
Simulation time 1287110060 ps
CPU time 56.25 seconds
Started Apr 30 01:37:53 PM PDT 24
Finished Apr 30 01:38:49 PM PDT 24
Peak memory 267440 kb
Host smart-d57f1fea-c5a9-46d1-b37e-867e24d199b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722759231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2722759231
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2157508611
Short name T819
Test name
Test status
Simulation time 589066403 ps
CPU time 12.67 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:04 PM PDT 24
Peak memory 248456 kb
Host smart-67422efb-c215-42d2-a581-1a2299408161
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157508611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2157508611
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1158067352
Short name T442
Test name
Test status
Simulation time 96127560 ps
CPU time 4.51 seconds
Started Apr 30 01:37:44 PM PDT 24
Finished Apr 30 01:37:50 PM PDT 24
Peak memory 217900 kb
Host smart-bad80c84-9016-49ea-b4f6-059d141bf021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158067352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1158067352
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.665368809
Short name T239
Test name
Test status
Simulation time 851818526 ps
CPU time 8.53 seconds
Started Apr 30 01:37:53 PM PDT 24
Finished Apr 30 01:38:01 PM PDT 24
Peak memory 213316 kb
Host smart-65b8cd25-87b0-4406-9bb7-4cf42f21d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665368809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.665368809
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1362273400
Short name T228
Test name
Test status
Simulation time 455487646 ps
CPU time 12.9 seconds
Started Apr 30 01:37:49 PM PDT 24
Finished Apr 30 01:38:03 PM PDT 24
Peak memory 217916 kb
Host smart-43919f8f-17ae-431a-be1f-1e9852319c6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362273400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1362273400
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.851251248
Short name T749
Test name
Test status
Simulation time 486304077 ps
CPU time 11.38 seconds
Started Apr 30 01:37:49 PM PDT 24
Finished Apr 30 01:38:01 PM PDT 24
Peak memory 217868 kb
Host smart-3fc1bd35-bbab-43a6-9b3c-9b8ce2e0f579
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851251248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.851251248
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2161742487
Short name T396
Test name
Test status
Simulation time 615365937 ps
CPU time 13.51 seconds
Started Apr 30 01:37:53 PM PDT 24
Finished Apr 30 01:38:07 PM PDT 24
Peak memory 217884 kb
Host smart-681a9098-3cb6-449f-b9c0-f7d0f07bdf5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161742487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
161742487
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2879900060
Short name T589
Test name
Test status
Simulation time 582710396 ps
CPU time 7.42 seconds
Started Apr 30 01:37:40 PM PDT 24
Finished Apr 30 01:37:48 PM PDT 24
Peak memory 224612 kb
Host smart-d84aa8ca-bf23-4784-97bf-67f8ec9caf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879900060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2879900060
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3411721855
Short name T174
Test name
Test status
Simulation time 74344341 ps
CPU time 1.43 seconds
Started Apr 30 01:37:44 PM PDT 24
Finished Apr 30 01:37:46 PM PDT 24
Peak memory 213092 kb
Host smart-80664789-ebc5-4eda-b6a8-813fdd00c5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411721855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3411721855
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3867844180
Short name T317
Test name
Test status
Simulation time 599387568 ps
CPU time 19.82 seconds
Started Apr 30 01:37:42 PM PDT 24
Finished Apr 30 01:38:03 PM PDT 24
Peak memory 250716 kb
Host smart-65e4c3d8-5595-4246-b72c-23d3117458e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867844180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3867844180
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1783676084
Short name T429
Test name
Test status
Simulation time 208337157 ps
CPU time 9.16 seconds
Started Apr 30 01:37:43 PM PDT 24
Finished Apr 30 01:37:54 PM PDT 24
Peak memory 250824 kb
Host smart-80a61661-04c7-4c20-8d45-37768bf4566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783676084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1783676084
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.588628088
Short name T145
Test name
Test status
Simulation time 6357388310 ps
CPU time 69.83 seconds
Started Apr 30 01:37:52 PM PDT 24
Finished Apr 30 01:39:02 PM PDT 24
Peak memory 250992 kb
Host smart-61a89b0f-5ac5-42db-a992-6ddd721fdfaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588628088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.588628088
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3505457619
Short name T158
Test name
Test status
Simulation time 24228757 ps
CPU time 0.79 seconds
Started Apr 30 01:37:42 PM PDT 24
Finished Apr 30 01:37:44 PM PDT 24
Peak memory 208368 kb
Host smart-019c7494-b428-4a1b-8441-5c7a58b56d39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505457619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3505457619
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1213151181
Short name T580
Test name
Test status
Simulation time 76690500 ps
CPU time 1.19 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:00 PM PDT 24
Peak memory 209376 kb
Host smart-437552f4-e886-46b8-ab5c-99eb6c9e9fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213151181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1213151181
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.696848375
Short name T86
Test name
Test status
Simulation time 13179824 ps
CPU time 0.81 seconds
Started Apr 30 01:37:50 PM PDT 24
Finished Apr 30 01:37:52 PM PDT 24
Peak memory 209292 kb
Host smart-cefb9dc7-af3f-42eb-aaa4-8dd1def68d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696848375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.696848375
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2151521388
Short name T323
Test name
Test status
Simulation time 1411930986 ps
CPU time 15.24 seconds
Started Apr 30 01:37:49 PM PDT 24
Finished Apr 30 01:38:05 PM PDT 24
Peak memory 217852 kb
Host smart-1414c352-d676-4be6-b1c3-046922835437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151521388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2151521388
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3331577125
Short name T465
Test name
Test status
Simulation time 271564002 ps
CPU time 1.62 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:37:53 PM PDT 24
Peak memory 216940 kb
Host smart-96c02171-4b84-409c-ad26-64f860fe1dc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331577125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3331577125
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2188003856
Short name T598
Test name
Test status
Simulation time 3273801939 ps
CPU time 32.28 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:24 PM PDT 24
Peak memory 219028 kb
Host smart-54f6f614-5fa6-4334-a1a6-da5fe45efdbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188003856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2188003856
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2965986426
Short name T376
Test name
Test status
Simulation time 1071974234 ps
CPU time 8.01 seconds
Started Apr 30 01:37:54 PM PDT 24
Finished Apr 30 01:38:02 PM PDT 24
Peak memory 217632 kb
Host smart-ccebb80f-59ff-40db-a047-216bb0d34aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965986426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
965986426
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1207404821
Short name T321
Test name
Test status
Simulation time 3630263177 ps
CPU time 11.78 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:04 PM PDT 24
Peak memory 217956 kb
Host smart-88195358-cfaf-4b59-8275-29baf2e8ecd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207404821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1207404821
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.275297056
Short name T316
Test name
Test status
Simulation time 1174914350 ps
CPU time 33.66 seconds
Started Apr 30 01:37:56 PM PDT 24
Finished Apr 30 01:38:30 PM PDT 24
Peak memory 213256 kb
Host smart-2cfe4640-713c-4f59-8d43-8f096d55764f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275297056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.275297056
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1036138176
Short name T655
Test name
Test status
Simulation time 515915463 ps
CPU time 8.06 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:00 PM PDT 24
Peak memory 213744 kb
Host smart-a69ba390-f6c6-48ea-b207-2c355b423b1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036138176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1036138176
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2096254431
Short name T761
Test name
Test status
Simulation time 1506325502 ps
CPU time 34.91 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:27 PM PDT 24
Peak memory 249036 kb
Host smart-aeeb0ba0-fa2b-4648-8b9c-5045b10219e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096254431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2096254431
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2464700850
Short name T209
Test name
Test status
Simulation time 1415514446 ps
CPU time 10.12 seconds
Started Apr 30 01:37:56 PM PDT 24
Finished Apr 30 01:38:06 PM PDT 24
Peak memory 250276 kb
Host smart-2e429f75-feb6-4b6e-a1df-f223014d4c95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464700850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2464700850
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.978298085
Short name T654
Test name
Test status
Simulation time 80725458 ps
CPU time 3.25 seconds
Started Apr 30 01:37:55 PM PDT 24
Finished Apr 30 01:37:59 PM PDT 24
Peak memory 217896 kb
Host smart-541fea73-b503-4d89-b181-a778d13115ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978298085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.978298085
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3576314900
Short name T270
Test name
Test status
Simulation time 1337786875 ps
CPU time 13.89 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:06 PM PDT 24
Peak memory 214512 kb
Host smart-77d5dfd1-e5a1-4917-bb21-a6a11e23f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576314900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3576314900
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.54335816
Short name T365
Test name
Test status
Simulation time 1181124406 ps
CPU time 10.28 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:09 PM PDT 24
Peak memory 225948 kb
Host smart-56dc260a-5690-46df-93be-3dd45a5834b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54335816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.54335816
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1616119364
Short name T373
Test name
Test status
Simulation time 910965002 ps
CPU time 9.43 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:38:10 PM PDT 24
Peak memory 217728 kb
Host smart-36999403-0248-4958-8ac3-391fa700fd9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616119364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1616119364
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1173067466
Short name T512
Test name
Test status
Simulation time 303821448 ps
CPU time 12 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:10 PM PDT 24
Peak memory 217760 kb
Host smart-b587685d-33c1-4854-8c40-2dfb6313767d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173067466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
173067466
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1538768777
Short name T543
Test name
Test status
Simulation time 197263079 ps
CPU time 8.82 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:38:01 PM PDT 24
Peak memory 217904 kb
Host smart-5f3dd2ce-ad49-4fe9-8632-f0e225ca2499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538768777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1538768777
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1346782389
Short name T488
Test name
Test status
Simulation time 1140943068 ps
CPU time 15.69 seconds
Started Apr 30 01:37:52 PM PDT 24
Finished Apr 30 01:38:08 PM PDT 24
Peak memory 217616 kb
Host smart-e35e70b6-c5cc-4218-b469-5356d3502aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346782389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1346782389
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3062475817
Short name T287
Test name
Test status
Simulation time 899037015 ps
CPU time 22.38 seconds
Started Apr 30 01:37:52 PM PDT 24
Finished Apr 30 01:38:15 PM PDT 24
Peak memory 250644 kb
Host smart-27a36b3b-bb84-42d1-98da-79b7f7de0454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062475817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3062475817
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1793516201
Short name T550
Test name
Test status
Simulation time 81214857 ps
CPU time 4.24 seconds
Started Apr 30 01:37:51 PM PDT 24
Finished Apr 30 01:37:56 PM PDT 24
Peak memory 222408 kb
Host smart-a36fce35-b918-46f7-b066-a00c4617edda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793516201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1793516201
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3176917117
Short name T615
Test name
Test status
Simulation time 34826975691 ps
CPU time 173.11 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:40:53 PM PDT 24
Peak memory 246652 kb
Host smart-b475f123-f167-4c01-9150-c3cd785e4e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176917117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3176917117
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1291116874
Short name T857
Test name
Test status
Simulation time 27867117481 ps
CPU time 737.29 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:50:16 PM PDT 24
Peak memory 283788 kb
Host smart-70506606-38e6-40c4-ad0a-f9cbfad0b5ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1291116874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1291116874
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1120777739
Short name T563
Test name
Test status
Simulation time 15246138 ps
CPU time 0.94 seconds
Started Apr 30 01:37:55 PM PDT 24
Finished Apr 30 01:37:57 PM PDT 24
Peak memory 208756 kb
Host smart-74ef2ffd-1fcb-4b35-8e72-88879274e3cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120777739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1120777739
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1228992615
Short name T275
Test name
Test status
Simulation time 30210470 ps
CPU time 1.35 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:01 PM PDT 24
Peak memory 209456 kb
Host smart-69839d19-1db6-4b3b-a431-5349541a0920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228992615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1228992615
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.334521503
Short name T179
Test name
Test status
Simulation time 19523874 ps
CPU time 0.79 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:01 PM PDT 24
Peak memory 209284 kb
Host smart-9b6b0976-925f-4450-ae4a-d673ce2796c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334521503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.334521503
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1304734983
Short name T499
Test name
Test status
Simulation time 248411625 ps
CPU time 10.9 seconds
Started Apr 30 01:38:01 PM PDT 24
Finished Apr 30 01:38:12 PM PDT 24
Peak memory 217820 kb
Host smart-33b0ceaa-888c-49c2-b7de-d0ae116bbeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304734983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1304734983
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4266390759
Short name T343
Test name
Test status
Simulation time 832772455 ps
CPU time 2.97 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:02 PM PDT 24
Peak memory 209388 kb
Host smart-3241ec51-842c-43d8-a2c2-da03cc080a11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266390759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4266390759
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1958106135
Short name T734
Test name
Test status
Simulation time 361696716 ps
CPU time 4.96 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:04 PM PDT 24
Peak memory 217304 kb
Host smart-70413fbb-11c6-4c17-81ca-272b80866ada
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958106135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
958106135
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1418486294
Short name T304
Test name
Test status
Simulation time 1237105484 ps
CPU time 5.67 seconds
Started Apr 30 01:38:01 PM PDT 24
Finished Apr 30 01:38:07 PM PDT 24
Peak memory 217784 kb
Host smart-8d8e2f9c-793a-4fee-a551-a3581de14404
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418486294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1418486294
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1156417944
Short name T54
Test name
Test status
Simulation time 3112308688 ps
CPU time 15.25 seconds
Started Apr 30 01:37:57 PM PDT 24
Finished Apr 30 01:38:13 PM PDT 24
Peak memory 213384 kb
Host smart-24747f19-c320-4b73-8dba-8b6c970b5d58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156417944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1156417944
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3490806997
Short name T535
Test name
Test status
Simulation time 277956507 ps
CPU time 4.73 seconds
Started Apr 30 01:38:01 PM PDT 24
Finished Apr 30 01:38:06 PM PDT 24
Peak memory 213424 kb
Host smart-51fc7c69-0ec5-4bb6-b79b-f9c92caf22f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490806997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3490806997
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.509968015
Short name T641
Test name
Test status
Simulation time 3171663813 ps
CPU time 68.35 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:39:09 PM PDT 24
Peak memory 271724 kb
Host smart-611822bc-2790-46f3-a5b6-546c219f578f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509968015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.509968015
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1783436039
Short name T537
Test name
Test status
Simulation time 2067674630 ps
CPU time 14.25 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:38:15 PM PDT 24
Peak memory 247220 kb
Host smart-d18f14cb-64df-4b1e-80af-44891d9a4a25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783436039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1783436039
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2285712057
Short name T515
Test name
Test status
Simulation time 233962940 ps
CPU time 3.12 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:01 PM PDT 24
Peak memory 217788 kb
Host smart-fc2cc548-bd29-4f1e-b83c-487b2ee8b22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285712057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2285712057
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1082115216
Short name T752
Test name
Test status
Simulation time 651489254 ps
CPU time 21.65 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:38:22 PM PDT 24
Peak memory 214332 kb
Host smart-3e499911-5838-42db-b7db-07408f5108e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082115216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1082115216
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3055022129
Short name T567
Test name
Test status
Simulation time 227862868 ps
CPU time 10.83 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:09 PM PDT 24
Peak memory 217984 kb
Host smart-69f14bc8-184e-47e0-b605-44f5ab1b0213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055022129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3055022129
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3985556920
Short name T157
Test name
Test status
Simulation time 1019819808 ps
CPU time 11.9 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:38:12 PM PDT 24
Peak memory 217812 kb
Host smart-5c8db109-615b-4224-9980-67993d7adca0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985556920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3985556920
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1555871183
Short name T271
Test name
Test status
Simulation time 3173248591 ps
CPU time 10.16 seconds
Started Apr 30 01:38:02 PM PDT 24
Finished Apr 30 01:38:12 PM PDT 24
Peak memory 217824 kb
Host smart-149d2749-6cc5-4a29-942b-6a711a6dea24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555871183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
555871183
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3424041705
Short name T497
Test name
Test status
Simulation time 1154297040 ps
CPU time 6.6 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:05 PM PDT 24
Peak memory 217796 kb
Host smart-d17e733e-a96d-479a-b534-2cd4f29e7dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424041705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3424041705
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.509024284
Short name T700
Test name
Test status
Simulation time 73463612 ps
CPU time 3.14 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:02 PM PDT 24
Peak memory 214652 kb
Host smart-aabeab2a-b44c-476f-83a2-fc7f37d04999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509024284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.509024284
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2348703838
Short name T753
Test name
Test status
Simulation time 437519897 ps
CPU time 27.1 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:27 PM PDT 24
Peak memory 246140 kb
Host smart-fa74ec07-1568-4004-99d8-2f4ae831d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348703838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2348703838
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2933114699
Short name T463
Test name
Test status
Simulation time 356388213 ps
CPU time 8.5 seconds
Started Apr 30 01:37:58 PM PDT 24
Finished Apr 30 01:38:07 PM PDT 24
Peak memory 247112 kb
Host smart-30fd155e-d191-4b87-9637-9e8c498cae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933114699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2933114699
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2512172624
Short name T555
Test name
Test status
Simulation time 8893569554 ps
CPU time 292.38 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:42:53 PM PDT 24
Peak memory 273672 kb
Host smart-5752c40a-ca11-4124-b587-116315ebb29e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512172624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2512172624
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1522819926
Short name T155
Test name
Test status
Simulation time 86727968381 ps
CPU time 523.51 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:46:44 PM PDT 24
Peak memory 496764 kb
Host smart-5f8f06c6-1f74-4e7d-a4d7-40d3504a0510
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1522819926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1522819926
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3640038916
Short name T212
Test name
Test status
Simulation time 21394061 ps
CPU time 0.74 seconds
Started Apr 30 01:37:57 PM PDT 24
Finished Apr 30 01:37:58 PM PDT 24
Peak memory 207764 kb
Host smart-729b42e1-c8bb-461c-af63-7f11a1969dd1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640038916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3640038916
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.202003472
Short name T541
Test name
Test status
Simulation time 50033933 ps
CPU time 1.2 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:10 PM PDT 24
Peak memory 209420 kb
Host smart-23df5945-c1e6-4638-9573-51f67396baaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202003472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.202003472
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3810101245
Short name T178
Test name
Test status
Simulation time 12156454 ps
CPU time 0.8 seconds
Started Apr 30 01:38:07 PM PDT 24
Finished Apr 30 01:38:08 PM PDT 24
Peak memory 209284 kb
Host smart-caf325c2-7554-49da-8bee-53b9760d3e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810101245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3810101245
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3403438568
Short name T457
Test name
Test status
Simulation time 2295014098 ps
CPU time 15.53 seconds
Started Apr 30 01:38:09 PM PDT 24
Finished Apr 30 01:38:25 PM PDT 24
Peak memory 217776 kb
Host smart-6cd25f8e-b748-44fe-9a0e-9d5c385f2e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403438568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3403438568
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1393570679
Short name T755
Test name
Test status
Simulation time 176809407 ps
CPU time 5.46 seconds
Started Apr 30 01:38:06 PM PDT 24
Finished Apr 30 01:38:12 PM PDT 24
Peak memory 209392 kb
Host smart-b5f21012-fe4c-4ee0-9ddb-cf86394d8757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393570679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1393570679
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2783474296
Short name T484
Test name
Test status
Simulation time 1429521272 ps
CPU time 39.51 seconds
Started Apr 30 01:38:06 PM PDT 24
Finished Apr 30 01:38:47 PM PDT 24
Peak memory 217696 kb
Host smart-0aa4b268-63a0-4faa-a812-fbfad61b68b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783474296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2783474296
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3073851084
Short name T835
Test name
Test status
Simulation time 306100606 ps
CPU time 1.4 seconds
Started Apr 30 01:38:06 PM PDT 24
Finished Apr 30 01:38:08 PM PDT 24
Peak memory 217136 kb
Host smart-5c905201-7f3d-4192-a401-255796917652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073851084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
073851084
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2018352062
Short name T624
Test name
Test status
Simulation time 1755983216 ps
CPU time 9.46 seconds
Started Apr 30 01:38:10 PM PDT 24
Finished Apr 30 01:38:20 PM PDT 24
Peak memory 217792 kb
Host smart-57c9c621-06b0-41ee-b737-e2e33120f1ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018352062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2018352062
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.889690928
Short name T420
Test name
Test status
Simulation time 1020598582 ps
CPU time 16.59 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:26 PM PDT 24
Peak memory 213232 kb
Host smart-9e9a2b96-8bd4-4922-b9db-ed000963fed2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889690928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.889690928
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.4060061138
Short name T687
Test name
Test status
Simulation time 493649837 ps
CPU time 10.46 seconds
Started Apr 30 01:38:06 PM PDT 24
Finished Apr 30 01:38:17 PM PDT 24
Peak memory 213608 kb
Host smart-f0c270d7-11dd-4118-835e-ec8fac4c7725
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060061138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
4060061138
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1016189314
Short name T525
Test name
Test status
Simulation time 4839335913 ps
CPU time 45.96 seconds
Started Apr 30 01:38:09 PM PDT 24
Finished Apr 30 01:38:56 PM PDT 24
Peak memory 250804 kb
Host smart-77fa8ef4-4ead-4f45-a463-57a83a031872
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016189314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1016189314
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3990479059
Short name T204
Test name
Test status
Simulation time 2768967639 ps
CPU time 22.56 seconds
Started Apr 30 01:38:12 PM PDT 24
Finished Apr 30 01:38:35 PM PDT 24
Peak memory 244316 kb
Host smart-e8592bb7-0ab3-46a0-a7c0-27846f8f8fa9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990479059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3990479059
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1990195426
Short name T202
Test name
Test status
Simulation time 54420669 ps
CPU time 3.1 seconds
Started Apr 30 01:38:07 PM PDT 24
Finished Apr 30 01:38:11 PM PDT 24
Peak memory 217860 kb
Host smart-d6bb6129-abc8-4169-be10-601ec27e583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990195426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1990195426
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1290744752
Short name T487
Test name
Test status
Simulation time 332400311 ps
CPU time 7.68 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:17 PM PDT 24
Peak memory 214100 kb
Host smart-b4736d48-3d15-4e0e-8801-4e146409958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290744752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1290744752
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2046068977
Short name T533
Test name
Test status
Simulation time 520832986 ps
CPU time 14.8 seconds
Started Apr 30 01:38:07 PM PDT 24
Finished Apr 30 01:38:23 PM PDT 24
Peak memory 225764 kb
Host smart-f99ce3b4-e5f7-48c1-93f6-2b1962d356f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046068977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2046068977
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2902162664
Short name T524
Test name
Test status
Simulation time 1382951781 ps
CPU time 25.13 seconds
Started Apr 30 01:38:11 PM PDT 24
Finished Apr 30 01:38:36 PM PDT 24
Peak memory 217824 kb
Host smart-582f5864-44fa-4659-ad07-f5e266c6547a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902162664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2902162664
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3348803370
Short name T669
Test name
Test status
Simulation time 1437987655 ps
CPU time 7.96 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:38:17 PM PDT 24
Peak memory 217824 kb
Host smart-73a0ef46-2e03-4c63-ab14-2e9b53dd85be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348803370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
348803370
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1711810531
Short name T353
Test name
Test status
Simulation time 1767922010 ps
CPU time 10.21 seconds
Started Apr 30 01:38:10 PM PDT 24
Finished Apr 30 01:38:21 PM PDT 24
Peak memory 217868 kb
Host smart-a608d5e6-e19a-484a-9bbf-9cebbd894bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711810531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1711810531
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3805556822
Short name T504
Test name
Test status
Simulation time 1332185448 ps
CPU time 2.62 seconds
Started Apr 30 01:38:01 PM PDT 24
Finished Apr 30 01:38:04 PM PDT 24
Peak memory 217560 kb
Host smart-1b096c46-ef5e-4f6d-9634-c181446430ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805556822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3805556822
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.160211469
Short name T315
Test name
Test status
Simulation time 179554622 ps
CPU time 27.97 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:27 PM PDT 24
Peak memory 250896 kb
Host smart-3f1f0615-3c16-4ddc-8fb4-18f4e7fae3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160211469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.160211469
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3653805013
Short name T542
Test name
Test status
Simulation time 321123600 ps
CPU time 6.41 seconds
Started Apr 30 01:37:59 PM PDT 24
Finished Apr 30 01:38:05 PM PDT 24
Peak memory 250804 kb
Host smart-614bd322-e4bd-4fe3-b61c-eff8725a1466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653805013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3653805013
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1416576563
Short name T276
Test name
Test status
Simulation time 16274162220 ps
CPU time 86.78 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:39:36 PM PDT 24
Peak memory 238572 kb
Host smart-7d1824c5-8545-411a-ba99-54bd4e1ced75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416576563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1416576563
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.4027964966
Short name T40
Test name
Test status
Simulation time 65841873550 ps
CPU time 1188.14 seconds
Started Apr 30 01:38:08 PM PDT 24
Finished Apr 30 01:57:57 PM PDT 24
Peak memory 496384 kb
Host smart-80196de9-90a6-45fc-9ba4-d6be082e5376
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4027964966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.4027964966
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.606223645
Short name T805
Test name
Test status
Simulation time 12023367 ps
CPU time 1.01 seconds
Started Apr 30 01:38:00 PM PDT 24
Finished Apr 30 01:38:01 PM PDT 24
Peak memory 211472 kb
Host smart-b9d32007-4b51-4dfb-b3e2-0ea24fcc74c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606223645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.606223645
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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