Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53607 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
806 |
auto[1] |
1955 |
1 |
|
|
T3 |
21 |
|
T10 |
8 |
|
T14 |
6 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54834 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
auto[1] |
728 |
1 |
|
|
T46 |
9 |
|
T38 |
7 |
|
T47 |
8 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53526 |
1 |
|
|
T1 |
78 |
|
T2 |
71 |
|
T3 |
768 |
auto[1] |
2036 |
1 |
|
|
T1 |
7 |
|
T2 |
9 |
|
T3 |
59 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53570 |
1 |
|
|
T1 |
75 |
|
T2 |
68 |
|
T3 |
768 |
auto[1] |
1992 |
1 |
|
|
T1 |
10 |
|
T2 |
12 |
|
T3 |
59 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53512 |
1 |
|
|
T1 |
80 |
|
T2 |
73 |
|
T3 |
779 |
auto[1] |
2050 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T3 |
48 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50442 |
1 |
|
|
T1 |
82 |
|
T2 |
80 |
|
T3 |
740 |
no_err_inj |
5120 |
1 |
|
|
T1 |
3 |
|
T3 |
87 |
|
T8 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53634 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
802 |
auto[1] |
1928 |
1 |
|
|
T3 |
25 |
|
T10 |
11 |
|
T14 |
7 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54847 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
auto[1] |
715 |
1 |
|
|
T46 |
6 |
|
T38 |
9 |
|
T47 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38367 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
375 |
auto[1] |
17195 |
1 |
|
|
T1 |
31 |
|
T3 |
452 |
|
T4 |
94 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53512 |
1 |
|
|
T1 |
73 |
|
T2 |
73 |
|
T3 |
762 |
auto[1] |
2050 |
1 |
|
|
T1 |
12 |
|
T2 |
7 |
|
T3 |
65 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53649 |
1 |
|
|
T1 |
75 |
|
T2 |
70 |
|
T3 |
764 |
auto[1] |
1913 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
63 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53598 |
1 |
|
|
T1 |
81 |
|
T2 |
69 |
|
T3 |
757 |
auto[1] |
1964 |
1 |
|
|
T1 |
4 |
|
T2 |
11 |
|
T3 |
70 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53599 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
809 |
auto[1] |
1963 |
1 |
|
|
T3 |
18 |
|
T10 |
6 |
|
T14 |
16 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53167 |
1 |
|
|
T1 |
66 |
|
T2 |
80 |
|
T3 |
794 |
auto[1] |
2395 |
1 |
|
|
T1 |
19 |
|
T3 |
33 |
|
T4 |
33 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54798 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
auto[1] |
764 |
1 |
|
|
T46 |
13 |
|
T38 |
18 |
|
T47 |
8 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54841 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
auto[1] |
721 |
1 |
|
|
T46 |
7 |
|
T38 |
13 |
|
T47 |
13 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54807 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
auto[1] |
755 |
1 |
|
|
T46 |
16 |
|
T38 |
14 |
|
T47 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52831 |
1 |
|
|
T1 |
74 |
|
T2 |
80 |
|
T3 |
785 |
auto[1] |
2731 |
1 |
|
|
T1 |
11 |
|
T3 |
42 |
|
T4 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52039 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
auto[1] |
3523 |
1 |
|
|
T9 |
59 |
|
T15 |
100 |
|
T53 |
86 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53633 |
1 |
|
|
T1 |
82 |
|
T2 |
74 |
|
T3 |
769 |
auto[1] |
1929 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T3 |
58 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53637 |
1 |
|
|
T1 |
78 |
|
T2 |
72 |
|
T3 |
776 |
auto[1] |
1925 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T3 |
51 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53543 |
1 |
|
|
T1 |
80 |
|
T2 |
70 |
|
T3 |
782 |
auto[1] |
2019 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T3 |
45 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53650 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
805 |
auto[1] |
1912 |
1 |
|
|
T3 |
22 |
|
T10 |
10 |
|
T14 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49983 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
792 |
auto[1] |
5579 |
1 |
|
|
T3 |
35 |
|
T10 |
9 |
|
T14 |
9 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51754 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
auto[1] |
3808 |
1 |
|
|
T40 |
92 |
|
T52 |
78 |
|
T63 |
86 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55562 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
827 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53629 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
798 |
auto[1] |
1933 |
1 |
|
|
T3 |
29 |
|
T10 |
11 |
|
T14 |
17 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53635 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
807 |
auto[1] |
1927 |
1 |
|
|
T3 |
20 |
|
T10 |
6 |
|
T14 |
11 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53604 |
1 |
|
|
T1 |
85 |
|
T2 |
80 |
|
T3 |
808 |
auto[1] |
1958 |
1 |
|
|
T3 |
19 |
|
T10 |
11 |
|
T14 |
10 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49082 |
1 |
|
|
T1 |
73 |
|
T2 |
80 |
|
T3 |
718 |
auto[0] |
no_err_inj |
3749 |
1 |
|
|
T1 |
1 |
|
T3 |
67 |
|
T8 |
5 |
auto[1] |
err_inj |
1360 |
1 |
|
|
T1 |
9 |
|
T3 |
22 |
|
T4 |
7 |
auto[1] |
no_err_inj |
1371 |
1 |
|
|
T1 |
2 |
|
T3 |
20 |
|
T4 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51039 |
1 |
|
|
T1 |
67 |
|
T2 |
72 |
|
T3 |
737 |
auto[0] |
auto[1] |
1792 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T3 |
48 |
auto[1] |
auto[0] |
2598 |
1 |
|
|
T1 |
11 |
|
T3 |
39 |
|
T4 |
12 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T3 |
3 |
|
T18 |
1 |
|
T224 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51053 |
1 |
|
|
T1 |
68 |
|
T2 |
70 |
|
T3 |
725 |
auto[0] |
auto[1] |
1778 |
1 |
|
|
T1 |
6 |
|
T2 |
10 |
|
T3 |
60 |
auto[1] |
auto[0] |
2596 |
1 |
|
|
T1 |
7 |
|
T3 |
39 |
|
T4 |
10 |
auto[1] |
auto[1] |
135 |
1 |
|
|
T1 |
4 |
|
T3 |
3 |
|
T4 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50949 |
1 |
|
|
T1 |
70 |
|
T2 |
70 |
|
T3 |
742 |
auto[0] |
auto[1] |
1882 |
1 |
|
|
T1 |
4 |
|
T2 |
10 |
|
T3 |
43 |
auto[1] |
auto[0] |
2594 |
1 |
|
|
T1 |
10 |
|
T3 |
40 |
|
T4 |
12 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T18 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51024 |
1 |
|
|
T1 |
64 |
|
T2 |
68 |
|
T3 |
729 |
auto[0] |
auto[1] |
1807 |
1 |
|
|
T1 |
10 |
|
T2 |
12 |
|
T3 |
56 |
auto[1] |
auto[0] |
2546 |
1 |
|
|
T1 |
11 |
|
T3 |
39 |
|
T4 |
10 |
auto[1] |
auto[1] |
185 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T224 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50940 |
1 |
|
|
T1 |
71 |
|
T2 |
73 |
|
T3 |
739 |
auto[0] |
auto[1] |
1891 |
1 |
|
|
T1 |
3 |
|
T2 |
7 |
|
T3 |
46 |
auto[1] |
auto[0] |
2572 |
1 |
|
|
T1 |
9 |
|
T3 |
40 |
|
T4 |
10 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50942 |
1 |
|
|
T1 |
67 |
|
T2 |
71 |
|
T3 |
727 |
auto[0] |
auto[1] |
1889 |
1 |
|
|
T1 |
7 |
|
T2 |
9 |
|
T3 |
58 |
auto[1] |
auto[0] |
2584 |
1 |
|
|
T1 |
11 |
|
T3 |
41 |
|
T4 |
12 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T3 |
1 |
|
T18 |
1 |
|
T224 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37123 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
367 |
auto[0] |
auto[1] |
1244 |
1 |
|
|
T3 |
8 |
|
T10 |
8 |
|
T14 |
6 |
auto[1] |
auto[0] |
16484 |
1 |
|
|
T1 |
31 |
|
T3 |
439 |
|
T4 |
94 |
auto[1] |
auto[1] |
711 |
1 |
|
|
T3 |
13 |
|
T17 |
11 |
|
T65 |
12 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37189 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
365 |
auto[0] |
auto[1] |
1178 |
1 |
|
|
T3 |
10 |
|
T10 |
11 |
|
T14 |
7 |
auto[1] |
auto[0] |
16445 |
1 |
|
|
T1 |
31 |
|
T3 |
437 |
|
T4 |
94 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T3 |
15 |
|
T17 |
9 |
|
T65 |
4 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37035 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
355 |
auto[0] |
auto[1] |
1332 |
1 |
|
|
T3 |
20 |
|
T4 |
33 |
|
T14 |
16 |
auto[1] |
auto[0] |
16132 |
1 |
|
|
T1 |
12 |
|
T3 |
439 |
|
T4 |
94 |
auto[1] |
auto[1] |
1063 |
1 |
|
|
T1 |
19 |
|
T3 |
13 |
|
T14 |
31 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37171 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
368 |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T3 |
7 |
|
T10 |
6 |
|
T14 |
16 |
auto[1] |
auto[0] |
16428 |
1 |
|
|
T1 |
31 |
|
T3 |
441 |
|
T4 |
94 |
auto[1] |
auto[1] |
767 |
1 |
|
|
T3 |
11 |
|
T17 |
15 |
|
T65 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33553 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
362 |
auto[0] |
auto[1] |
4814 |
1 |
|
|
T3 |
13 |
|
T10 |
9 |
|
T14 |
9 |
auto[1] |
auto[0] |
16430 |
1 |
|
|
T1 |
31 |
|
T3 |
430 |
|
T4 |
94 |
auto[1] |
auto[1] |
765 |
1 |
|
|
T3 |
22 |
|
T17 |
9 |
|
T65 |
13 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37275 |
1 |
|
|
T1 |
47 |
|
T2 |
72 |
|
T3 |
352 |
auto[0] |
auto[1] |
1092 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T3 |
23 |
auto[1] |
auto[0] |
16362 |
1 |
|
|
T1 |
31 |
|
T3 |
424 |
|
T4 |
85 |
auto[1] |
auto[1] |
833 |
1 |
|
|
T3 |
28 |
|
T4 |
9 |
|
T18 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37302 |
1 |
|
|
T1 |
51 |
|
T2 |
74 |
|
T3 |
351 |
auto[0] |
auto[1] |
1065 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T3 |
24 |
auto[1] |
auto[0] |
16331 |
1 |
|
|
T1 |
31 |
|
T3 |
418 |
|
T4 |
84 |
auto[1] |
auto[1] |
864 |
1 |
|
|
T3 |
34 |
|
T4 |
10 |
|
T18 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37355 |
1 |
|
|
T1 |
48 |
|
T2 |
70 |
|
T3 |
350 |
auto[0] |
auto[1] |
1012 |
1 |
|
|
T1 |
6 |
|
T2 |
10 |
|
T3 |
25 |
auto[1] |
auto[0] |
16294 |
1 |
|
|
T1 |
27 |
|
T3 |
414 |
|
T4 |
84 |
auto[1] |
auto[1] |
901 |
1 |
|
|
T1 |
4 |
|
T3 |
38 |
|
T4 |
10 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37259 |
1 |
|
|
T1 |
44 |
|
T2 |
73 |
|
T3 |
349 |
auto[0] |
auto[1] |
1108 |
1 |
|
|
T1 |
10 |
|
T2 |
7 |
|
T3 |
26 |
auto[1] |
auto[0] |
16253 |
1 |
|
|
T1 |
29 |
|
T3 |
413 |
|
T4 |
86 |
auto[1] |
auto[1] |
942 |
1 |
|
|
T1 |
2 |
|
T3 |
39 |
|
T4 |
8 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37255 |
1 |
|
|
T1 |
44 |
|
T2 |
68 |
|
T3 |
351 |
auto[0] |
auto[1] |
1112 |
1 |
|
|
T1 |
10 |
|
T2 |
12 |
|
T3 |
24 |
auto[1] |
auto[0] |
16315 |
1 |
|
|
T1 |
31 |
|
T3 |
417 |
|
T4 |
84 |
auto[1] |
auto[1] |
880 |
1 |
|
|
T3 |
35 |
|
T4 |
10 |
|
T19 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37239 |
1 |
|
|
T1 |
47 |
|
T2 |
71 |
|
T3 |
344 |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T1 |
7 |
|
T2 |
9 |
|
T3 |
31 |
auto[1] |
auto[0] |
16287 |
1 |
|
|
T1 |
31 |
|
T3 |
424 |
|
T4 |
87 |
auto[1] |
auto[1] |
908 |
1 |
|
|
T3 |
28 |
|
T4 |
7 |
|
T18 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37151 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
369 |
auto[0] |
auto[1] |
1216 |
1 |
|
|
T3 |
6 |
|
T10 |
11 |
|
T14 |
10 |
auto[1] |
auto[0] |
16453 |
1 |
|
|
T1 |
31 |
|
T3 |
439 |
|
T4 |
94 |
auto[1] |
auto[1] |
742 |
1 |
|
|
T3 |
13 |
|
T17 |
6 |
|
T65 |
17 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37201 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
366 |
auto[0] |
auto[1] |
1166 |
1 |
|
|
T3 |
9 |
|
T10 |
6 |
|
T14 |
11 |
auto[1] |
auto[0] |
16434 |
1 |
|
|
T1 |
31 |
|
T3 |
441 |
|
T4 |
94 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T3 |
11 |
|
T17 |
8 |
|
T65 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36828 |
1 |
|
|
T1 |
54 |
|
T2 |
80 |
|
T3 |
374 |
auto[0] |
auto[1] |
1539 |
1 |
|
|
T3 |
1 |
|
T224 |
10 |
|
T225 |
15 |
auto[1] |
auto[0] |
16003 |
1 |
|
|
T1 |
20 |
|
T3 |
411 |
|
T4 |
82 |
auto[1] |
auto[1] |
1192 |
1 |
|
|
T1 |
11 |
|
T3 |
41 |
|
T4 |
12 |