Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109880932

1

T1

80167

T2

24247

T3

302114

auto[1]

1420457

1

T1

3943

T2

2079

T3

23540

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109879265

1

T1

80853

T2

22564

T3

302311

auto[1]

1422124

1

T1

3257

T2

3762

T3

21563

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7833407	1			T1	8033		T2	8715		T3	253956
auto[IdleSt]	22205991	1			T1	23896		T2	944		T3	548582
auto[ClkMuxSt]	36575	1			T1	22		T3	310		T8	5
auto[CntIncrSt]	36278	1			T1	22		T3	310		T8	5
auto[CntProgSt]	1664922	1			T1	67		T3	561		T8	1041
auto[TransCheckSt]	28117	1			T1	3		T3	238		T8	5
auto[TokenHashSt]	45624958	1			T1	153		T3	707023		T8	4782
auto[FlashRmaSt]	29356	1			T1	3		T3	238		T8	5
auto[TokenCheck0St]	13156	1			T1	3		T3	106		T8	5
auto[TokenCheck1St]	9763	1			T1	3		T3	84		T8	5
auto[TransProgSt]	427747	1			T1	8		T3	160		T8	1092
auto[PostTransSt]	13023615	1			T1	11463		T3	383980		T8	1169
auto[ScrapSt]	163015	1			T3	520		T9	6		T4	9
auto[EscalateSt]	7219609	1			T1	22697		T2	8339		T3	303695
auto[InvalidSt]	12982886	1			T1	17727		T2	8318		T3	844854

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1994	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12982886	1			T1	17727		T2	8318		T3	844854
EscalateSt	7219609	1			T1	22697		T2	8339		T3	303695
ScrapSt	163015	1			T3	520		T9	6		T4	9
PostTransSt	13023615	1			T1	11463		T3	383980		T8	1169
TransProgSt	427747	1			T1	8		T3	160		T8	1092
TokenCheck1St	9763	1			T1	3		T3	84		T8	5
TokenCheck0St	13156	1			T1	3		T3	106		T8	5
FlashRmaSt	29356	1			T1	3		T3	238		T8	5
TokenHashSt	45624958	1			T1	153		T3	707023		T8	4782
TransCheckSt	28117	1			T1	3		T3	238		T8	5
CntProgSt	1664922	1			T1	67		T3	561		T8	1041
CntIncrSt	36278	1			T1	22		T3	310		T8	5
ClkMuxSt	36575	1			T1	22		T3	310		T8	5
IdleSt	22205991	1			T1	23896		T2	944		T3	548582
ResetSt	7833407	1			T1	8033		T2	8715		T3	253956
arcs[ResetSt=>IdleSt]	55869	1			T1	85		T2	70		T3	784
arcs[IdleSt=>ScrapSt]	316	1			T3	2		T9	2		T4	1
arcs[IdleSt=>ClkMuxSt]	36347	1			T1	22		T3	310		T8	5
arcs[ClkMuxSt=>CntIncrSt]	36278	1			T1	22		T3	310		T8	5
arcs[CntIncrSt=>PostTransSt]	1927	1			T3	20		T10	6		T14	11
arcs[CntIncrSt=>CntProgSt]	34292	1			T1	22		T3	290		T8	5
arcs[CntProgSt=>PostTransSt]	5035	1			T1	19		T3	52		T10	8
arcs[CntProgSt=>TransCheckSt]	28117	1			T1	3		T3	238		T8	5
arcs[TransCheckSt=>PostTransSt]	3859	1			T3	19		T10	11		T14	10
arcs[TransCheckSt=>TokenHashSt]	24191	1			T1	3		T3	219		T8	5
arcs[TokenHashSt=>PostTransSt]	10415	1			T3	111		T10	30		T14	34
arcs[TokenHashSt=>FlashRmaSt]	13257	1			T1	3		T3	106		T8	5
arcs[FlashRmaSt=>TokenCheck0St]	13156	1			T1	3		T3	106		T8	5
arcs[TokenCheck0St=>PostTransSt]	3368	1			T3	22		T10	11		T14	6
arcs[TokenCheck0St=>TokenCheck1St]	9763	1			T1	3		T3	84		T8	5
arcs[TokenCheck1St=>PostTransSt]	658	1			T3	4		T14	1		T40	11
arcs[TransProgSt=>PostTransSt]	8234	1			T1	3		T3	80		T8	5
arcs[IdleSt=>EscalateSt]	205	1			T54	6		T55	7		T56	8
arcs[ClkMuxSt=>EscalateSt]	69	1			T15	5		T53	3		T54	1
arcs[CntIncrSt=>EscalateSt]	59	1			T15	3		T53	2		T54	2
arcs[CntProgSt=>EscalateSt]	1140	1			T9	26		T15	34		T53	7
arcs[TransCheckSt=>EscalateSt]	67	1			T53	11		T55	4		T56	3
arcs[TokenHashSt=>EscalateSt]	519	1			T3	2		T9	9		T15	13
arcs[FlashRmaSt=>EscalateSt]	101	1			T15	3		T53	3		T54	1
arcs[TokenCheck0St=>EscalateSt]	25	1			T9	1		T56	2		T60	1
arcs[TokenCheck1St=>EscalateSt]	138	1			T9	4		T15	2		T53	2
arcs[TransProgSt=>EscalateSt]	733	1			T9	12		T15	24		T53	6
arcs[PostTransSt=>EscalateSt]	5237	1			T1	19		T3	52		T9	1
arcs[InvalidSt=>EscalateSt]	14632	1			T1	54		T2	59		T3	404

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7833238	1			T1	8033		T2	8715		T3	253956
auto[0]	auto[IdleSt]	22205835	1			T1	23896		T2	944		T3	548582
auto[0]	auto[ClkMuxSt]	36527	1			T1	22		T3	310		T8	5
auto[0]	auto[CntIncrSt]	36235	1			T1	22		T3	310		T8	5
auto[0]	auto[CntProgSt]	1664181	1			T1	67		T3	561		T8	1041
auto[0]	auto[TransCheckSt]	28070	1			T1	3		T3	238		T8	5
auto[0]	auto[TokenHashSt]	45624606	1			T1	153		T3	707022		T8	4782
auto[0]	auto[FlashRmaSt]	29284	1			T1	3		T3	238		T8	5
auto[0]	auto[TokenCheck0St]	13140	1			T1	3		T3	106		T8	5
auto[0]	auto[TokenCheck1St]	9672	1			T1	3		T3	84		T8	5
auto[0]	auto[TransProgSt]	427251	1			T1	8		T3	160		T8	1092
auto[0]	auto[PostTransSt]	13021015	1			T1	11451		T3	383954		T8	1169
auto[0]	auto[ScrapSt]	162967	1			T3	520		T9	4		T4	9
auto[0]	auto[EscalateSt]	5811377	1			T1	18794		T2	6281		T3	280394
auto[0]	auto[InvalidSt]	12975540	1			T1	17699		T2	8297		T3	844642
auto[1]	auto[ResetSt]	169	1			T9	2		T15	8		T53	7
auto[1]	auto[IdleSt]	156	1			T54	5		T55	5		T56	6
auto[1]	auto[ClkMuxSt]	48	1			T15	3		T53	1		T54	1
auto[1]	auto[CntIncrSt]	43	1			T15	1		T53	1		T54	2
auto[1]	auto[CntProgSt]	741	1			T9	19		T15	18		T53	5
auto[1]	auto[TransCheckSt]	47	1			T53	8		T55	3		T56	2
auto[1]	auto[TokenHashSt]	352	1			T3	1		T9	2		T15	7
auto[1]	auto[FlashRmaSt]	72	1			T15	1		T53	2		T54	1
auto[1]	auto[TokenCheck0St]	16	1			T9	1		T56	1		T223	1
auto[1]	auto[TokenCheck1St]	91	1			T9	3		T15	1		T53	1
auto[1]	auto[TransProgSt]	496	1			T9	7		T15	18		T53	5
auto[1]	auto[PostTransSt]	2600	1			T1	12		T3	26		T10	5
auto[1]	auto[ScrapSt]	48	1			T9	2		T53	1		T55	4
auto[1]	auto[EscalateSt]	1408232	1			T1	3903		T2	2058		T3	23301
auto[1]	auto[InvalidSt]	7346	1			T1	28		T2	21		T3	212

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7833248	1			T1	8033		T2	8715		T3	253956
auto[0]	auto[IdleSt]	22205857	1			T1	23896		T2	944		T3	548582
auto[0]	auto[ClkMuxSt]	36531	1			T1	22		T3	310		T8	5
auto[0]	auto[CntIncrSt]	36239	1			T1	22		T3	310		T8	5
auto[0]	auto[CntProgSt]	1664155	1			T1	67		T3	561		T8	1041
auto[0]	auto[TransCheckSt]	28063	1			T1	3		T3	238		T8	5
auto[0]	auto[TokenHashSt]	45624606	1			T1	153		T3	707022		T8	4782
auto[0]	auto[FlashRmaSt]	29287	1			T1	3		T3	238		T8	5
auto[0]	auto[TokenCheck0St]	13140	1			T1	3		T3	106		T8	5
auto[0]	auto[TokenCheck1St]	9667	1			T1	3		T3	84		T8	5
auto[0]	auto[TransProgSt]	427252	1			T1	8		T3	160		T8	1092
auto[0]	auto[PostTransSt]	13020925	1			T1	11456		T3	383954		T8	1169
auto[0]	auto[ScrapSt]	162969	1			T3	520		T9	5		T4	9
auto[0]	auto[EscalateSt]	5809732	1			T1	19473		T2	4615		T3	282351
auto[0]	auto[InvalidSt]	12975600	1			T1	17701		T2	8280		T3	844662
auto[1]	auto[ResetSt]	159	1			T9	2		T15	8		T53	3
auto[1]	auto[IdleSt]	134	1			T54	4		T55	5		T56	7
auto[1]	auto[ClkMuxSt]	44	1			T15	5		T53	2		T55	2
auto[1]	auto[CntIncrSt]	39	1			T15	2		T53	2		T54	2
auto[1]	auto[CntProgSt]	767	1			T9	18		T15	22		T53	3
auto[1]	auto[TransCheckSt]	54	1			T53	8		T55	4		T56	1
auto[1]	auto[TokenHashSt]	352	1			T3	1		T9	7		T15	7
auto[1]	auto[FlashRmaSt]	69	1			T15	3		T53	3		T54	1
auto[1]	auto[TokenCheck0St]	16	1			T9	1		T56	2		T60	1
auto[1]	auto[TokenCheck1St]	96	1			T9	3		T15	1		T53	2
auto[1]	auto[TransProgSt]	495	1			T9	8		T15	14		T53	4
auto[1]	auto[PostTransSt]	2690	1			T1	7		T3	26		T9	1
auto[1]	auto[ScrapSt]	46	1			T9	1		T53	1		T55	3
auto[1]	auto[EscalateSt]	1409877	1			T1	3224		T2	3724		T3	21344
auto[1]	auto[InvalidSt]	7286	1			T1	26		T2	38		T3	192