Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94118417

1

T1

20715

T2

31164

T3

20707

auto[1]

1339768

1

T1

891

T3

11068

T4

294

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94151380

1

T1

20121

T2

31164

T3

21439

auto[1]

1306805

1

T1

1485

T3

10336

T4

490

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7108116	1			T1	4717		T2	7934		T3	8918
auto[IdleSt]	19917235	1			T1	3309		T2	9579		T3	2936
auto[ClkMuxSt]	34584	1			T1	36		T2	81		T3	93
auto[CntIncrSt]	34239	1			T1	36		T2	81		T3	91
auto[CntProgSt]	1924457	1			T1	1539		T2	162		T3	208
auto[TransCheckSt]	26914	1			T1	27		T2	81		T3	72
auto[TokenHashSt]	36735773	1			T1	296		T2	448		T3	3338
auto[FlashRmaSt]	28077	1			T1	53		T2	64		T3	61
auto[TokenCheck0St]	12622	1			T1	25		T2	29		T3	28
auto[TokenCheck1St]	9499	1			T1	14		T2	12		T3	27
auto[TransProgSt]	516641	1			T1	625		T3	41		T10	210
auto[PostTransSt]	11840821	1			T1	5372		T2	12693		T3	8
auto[ScrapSt]	109030	1			T3	3		T10	27		T44	9
auto[EscalateSt]	6310410	1			T1	3333		T3	15951		T4	5097
auto[InvalidSt]	10848001	1			T1	2224		T12	1161		T5	140080

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1766	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10848001	1			T1	2224		T12	1161		T5	140080
EscalateSt	6310410	1			T1	3333		T3	15951		T4	5097
ScrapSt	109030	1			T3	3		T10	27		T44	9
PostTransSt	11840821	1			T1	5372		T2	12693		T3	8
TransProgSt	516641	1			T1	625		T3	41		T10	210
TokenCheck1St	9499	1			T1	14		T2	12		T3	27
TokenCheck0St	12622	1			T1	25		T2	29		T3	28
FlashRmaSt	28077	1			T1	53		T2	64		T3	61
TokenHashSt	36735773	1			T1	296		T2	448		T3	3338
TransCheckSt	26914	1			T1	27		T2	81		T3	72
CntProgSt	1924457	1			T1	1539		T2	162		T3	208
CntIncrSt	34239	1			T1	36		T2	81		T3	91
ClkMuxSt	34584	1			T1	36		T2	81		T3	93
IdleSt	19917235	1			T1	3309		T2	9579		T3	2936
ResetSt	7108116	1			T1	4717		T2	7934		T3	8918
arcs[ResetSt=>IdleSt]	51468	1			T1	52		T2	82		T3	95
arcs[IdleSt=>ScrapSt]	281	1			T3	1		T10	1		T44	1
arcs[IdleSt=>ClkMuxSt]	34294	1			T1	36		T2	81		T3	93
arcs[ClkMuxSt=>CntIncrSt]	34239	1			T1	36		T2	81		T3	91
arcs[CntIncrSt=>PostTransSt]	1545	1			T5	17		T40	8		T41	12
arcs[CntIncrSt=>CntProgSt]	32625	1			T1	36		T2	81		T3	87
arcs[CntProgSt=>PostTransSt]	4525	1			T1	9		T4	8		T12	10
arcs[CntProgSt=>TransCheckSt]	26914	1			T1	27		T2	81		T3	72
arcs[TransCheckSt=>PostTransSt]	3601	1			T2	40		T11	46		T5	19
arcs[TransCheckSt=>TokenHashSt]	23216	1			T1	27		T2	41		T3	66
arcs[TokenHashSt=>PostTransSt]	9822	1			T1	2		T2	12		T11	5
arcs[TokenHashSt=>FlashRmaSt]	12722	1			T1	25		T2	29		T3	36
arcs[FlashRmaSt=>TokenCheck0St]	12622	1			T1	25		T2	29		T3	28
arcs[TokenCheck0St=>PostTransSt]	3101	1			T1	11		T2	17		T11	21
arcs[TokenCheck0St=>TokenCheck1St]	9499	1			T1	14		T2	12		T3	27
arcs[TokenCheck1St=>PostTransSt]	668	1			T2	12		T11	10		T40	1
arcs[TransProgSt=>PostTransSt]	7904	1			T1	14		T3	4		T10	13
arcs[IdleSt=>EscalateSt]	184	1			T55	13		T57	8		T58	6
arcs[ClkMuxSt=>EscalateSt]	55	1			T3	2		T55	2		T56	4
arcs[CntIncrSt=>EscalateSt]	69	1			T3	4		T56	1		T57	5
arcs[CntProgSt=>EscalateSt]	1186	1			T3	15		T55	34		T56	40
arcs[TransCheckSt=>EscalateSt]	97	1			T3	6		T55	1		T57	9
arcs[TokenHashSt=>EscalateSt]	672	1			T3	30		T55	8		T63	1
arcs[FlashRmaSt=>EscalateSt]	100	1			T3	8		T55	2		T56	1
arcs[TokenCheck0St=>EscalateSt]	22	1			T3	1		T55	1		T62	1
arcs[TokenCheck1St=>EscalateSt]	154	1			T3	4		T55	7		T56	1
arcs[TransProgSt=>EscalateSt]	773	1			T3	19		T55	21		T56	21
arcs[PostTransSt=>EscalateSt]	4754	1			T1	9		T3	4		T4	8
arcs[InvalidSt=>EscalateSt]	12710	1			T1	15		T12	15		T5	70

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7107928	1			T1	4717		T2	7934		T3	8914
auto[0]	auto[IdleSt]	19917115	1			T1	3309		T2	9579		T3	2936
auto[0]	auto[ClkMuxSt]	34550	1			T1	36		T2	81		T3	91
auto[0]	auto[CntIncrSt]	34192	1			T1	36		T2	81		T3	87
auto[0]	auto[CntProgSt]	1923657	1			T1	1539		T2	162		T3	203
auto[0]	auto[TransCheckSt]	26844	1			T1	27		T2	81		T3	66
auto[0]	auto[TokenHashSt]	36735323	1			T1	296		T2	448		T3	3318
auto[0]	auto[FlashRmaSt]	28012	1			T1	53		T2	64		T3	54
auto[0]	auto[TokenCheck0St]	12603	1			T1	25		T2	29		T3	27
auto[0]	auto[TokenCheck1St]	9390	1			T1	14		T2	12		T3	24
auto[0]	auto[TransProgSt]	516143	1			T1	625		T3	29		T10	210
auto[0]	auto[PostTransSt]	11838331	1			T1	5370		T2	12693		T3	4
auto[0]	auto[ScrapSt]	108998	1			T3	2		T10	27		T44	9
auto[0]	auto[EscalateSt]	4981980	1			T1	2451		T3	4952		T4	4806
auto[0]	auto[InvalidSt]	10841585	1			T1	2217		T12	1156		T5	140050
auto[1]	auto[ResetSt]	188	1			T3	4		T55	1		T56	5
auto[1]	auto[IdleSt]	120	1			T55	7		T57	5		T58	5
auto[1]	auto[ClkMuxSt]	34	1			T3	2		T55	2		T56	2
auto[1]	auto[CntIncrSt]	47	1			T3	4		T56	1		T57	2
auto[1]	auto[CntProgSt]	800	1			T3	5		T55	24		T56	32
auto[1]	auto[TransCheckSt]	70	1			T3	6		T57	5		T58	5
auto[1]	auto[TokenHashSt]	450	1			T3	20		T55	6		T63	1
auto[1]	auto[FlashRmaSt]	65	1			T3	7		T55	1		T56	1
auto[1]	auto[TokenCheck0St]	19	1			T3	1		T55	1		T62	1
auto[1]	auto[TokenCheck1St]	109	1			T3	3		T55	4		T56	1
auto[1]	auto[TransProgSt]	498	1			T3	12		T55	13		T56	12
auto[1]	auto[PostTransSt]	2490	1			T1	2		T3	4		T4	3
auto[1]	auto[ScrapSt]	32	1			T3	1		T55	1		T62	1
auto[1]	auto[EscalateSt]	1328430	1			T1	882		T3	10999		T4	291
auto[1]	auto[InvalidSt]	6416	1			T1	7		T12	5		T5	30

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7107923	1			T1	4717		T2	7934		T3	8914
auto[0]	auto[IdleSt]	19917112	1			T1	3309		T2	9579		T3	2936
auto[0]	auto[ClkMuxSt]	34548	1			T1	36		T2	81		T3	93
auto[0]	auto[CntIncrSt]	34193	1			T1	36		T2	81		T3	89
auto[0]	auto[CntProgSt]	1923689	1			T1	1539		T2	162		T3	195
auto[0]	auto[TransCheckSt]	26854	1			T1	27		T2	81		T3	68
auto[0]	auto[TokenHashSt]	36735338	1			T1	296		T2	448		T3	3318
auto[0]	auto[FlashRmaSt]	28008	1			T1	53		T2	64		T3	57
auto[0]	auto[TokenCheck0St]	12608	1			T1	25		T2	29		T3	27
auto[0]	auto[TokenCheck1St]	9401	1			T1	14		T2	12		T3	26
auto[0]	auto[TransProgSt]	516115	1			T1	625		T3	30		T10	210
auto[0]	auto[PostTransSt]	11838473	1			T1	5365		T2	12693		T3	4
auto[0]	auto[ScrapSt]	108989	1			T3	2		T10	27		T44	9
auto[0]	auto[EscalateSt]	5014656	1			T1	1863		T3	5680		T4	4612
auto[0]	auto[InvalidSt]	10841707	1			T1	2216		T12	1151		T5	140040
auto[1]	auto[ResetSt]	193	1			T3	4		T55	4		T56	6
auto[1]	auto[IdleSt]	123	1			T55	13		T57	4		T58	6
auto[1]	auto[ClkMuxSt]	36	1			T55	1		T56	3		T57	2
auto[1]	auto[CntIncrSt]	46	1			T3	2		T56	1		T57	5
auto[1]	auto[CntProgSt]	768	1			T3	13		T55	23		T56	24
auto[1]	auto[TransCheckSt]	60	1			T3	4		T55	1		T57	6
auto[1]	auto[TokenHashSt]	435	1			T3	20		T55	4		T93	4
auto[1]	auto[FlashRmaSt]	69	1			T3	4		T55	2		T56	1
auto[1]	auto[TokenCheck0St]	14	1			T3	1		T55	1		T227	1
auto[1]	auto[TokenCheck1St]	98	1			T3	1		T55	7		T56	1
auto[1]	auto[TransProgSt]	526	1			T3	11		T55	14		T56	18
auto[1]	auto[PostTransSt]	2348	1			T1	7		T3	4		T4	5
auto[1]	auto[ScrapSt]	41	1			T3	1		T57	1		T62	1
auto[1]	auto[EscalateSt]	1295754	1			T1	1470		T3	10271		T4	485
auto[1]	auto[InvalidSt]	6294	1			T1	8		T12	10		T5	40