Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52921 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
1858 |
1 |
|
|
T11 |
37 |
|
T19 |
20 |
|
T20 |
15 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53987 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
792 |
1 |
|
|
T46 |
13 |
|
T51 |
16 |
|
T64 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52778 |
1 |
|
|
T2 |
6 |
|
T3 |
65 |
|
T4 |
9 |
auto[1] |
2001 |
1 |
|
|
T3 |
7 |
|
T5 |
10 |
|
T11 |
48 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52865 |
1 |
|
|
T2 |
6 |
|
T3 |
69 |
|
T4 |
9 |
auto[1] |
1914 |
1 |
|
|
T3 |
3 |
|
T5 |
14 |
|
T11 |
51 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52833 |
1 |
|
|
T2 |
6 |
|
T3 |
63 |
|
T4 |
9 |
auto[1] |
1946 |
1 |
|
|
T3 |
9 |
|
T5 |
6 |
|
T11 |
64 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49718 |
1 |
|
|
T3 |
72 |
|
T4 |
9 |
|
T5 |
77 |
no_err_inj |
5061 |
1 |
|
|
T2 |
6 |
|
T11 |
54 |
|
T12 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52927 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
1852 |
1 |
|
|
T11 |
23 |
|
T19 |
23 |
|
T20 |
8 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53934 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
845 |
1 |
|
|
T46 |
13 |
|
T51 |
10 |
|
T64 |
10 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38066 |
1 |
|
|
T3 |
72 |
|
T11 |
471 |
|
T12 |
7 |
auto[1] |
16713 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52847 |
1 |
|
|
T2 |
6 |
|
T3 |
59 |
|
T4 |
9 |
auto[1] |
1932 |
1 |
|
|
T3 |
13 |
|
T5 |
6 |
|
T11 |
56 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52739 |
1 |
|
|
T2 |
6 |
|
T3 |
66 |
|
T4 |
9 |
auto[1] |
2040 |
1 |
|
|
T3 |
6 |
|
T5 |
10 |
|
T11 |
57 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52819 |
1 |
|
|
T2 |
6 |
|
T3 |
63 |
|
T4 |
9 |
auto[1] |
1960 |
1 |
|
|
T3 |
9 |
|
T5 |
5 |
|
T11 |
49 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52879 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
1900 |
1 |
|
|
T11 |
37 |
|
T19 |
13 |
|
T20 |
7 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52497 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T5 |
77 |
auto[1] |
2282 |
1 |
|
|
T4 |
9 |
|
T11 |
56 |
|
T15 |
18 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53973 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
806 |
1 |
|
|
T46 |
10 |
|
T51 |
16 |
|
T64 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53989 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
790 |
1 |
|
|
T46 |
15 |
|
T51 |
10 |
|
T64 |
9 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53975 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
804 |
1 |
|
|
T46 |
14 |
|
T51 |
12 |
|
T64 |
15 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51844 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
2935 |
1 |
|
|
T11 |
23 |
|
T19 |
12 |
|
T65 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51043 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
3736 |
1 |
|
|
T16 |
71 |
|
T17 |
91 |
|
T29 |
72 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52755 |
1 |
|
|
T2 |
6 |
|
T3 |
65 |
|
T4 |
9 |
auto[1] |
2024 |
1 |
|
|
T3 |
7 |
|
T5 |
10 |
|
T11 |
57 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52840 |
1 |
|
|
T2 |
6 |
|
T3 |
66 |
|
T4 |
9 |
auto[1] |
1939 |
1 |
|
|
T3 |
6 |
|
T5 |
5 |
|
T11 |
46 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52795 |
1 |
|
|
T2 |
6 |
|
T3 |
60 |
|
T4 |
9 |
auto[1] |
1984 |
1 |
|
|
T3 |
12 |
|
T5 |
11 |
|
T11 |
52 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52917 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
1862 |
1 |
|
|
T11 |
28 |
|
T19 |
15 |
|
T20 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49187 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
5592 |
1 |
|
|
T11 |
23 |
|
T18 |
96 |
|
T19 |
21 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51173 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
3606 |
1 |
|
|
T47 |
65 |
|
T36 |
68 |
|
T37 |
60 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54779 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53049 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
1730 |
1 |
|
|
T11 |
30 |
|
T19 |
13 |
|
T20 |
17 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53013 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
1766 |
1 |
|
|
T11 |
32 |
|
T19 |
16 |
|
T20 |
12 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53022 |
1 |
|
|
T2 |
6 |
|
T3 |
72 |
|
T4 |
9 |
auto[1] |
1757 |
1 |
|
|
T11 |
40 |
|
T19 |
11 |
|
T20 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48238 |
1 |
|
|
T3 |
72 |
|
T4 |
9 |
|
T5 |
77 |
auto[0] |
no_err_inj |
3606 |
1 |
|
|
T2 |
6 |
|
T11 |
42 |
|
T12 |
7 |
auto[1] |
err_inj |
1480 |
1 |
|
|
T11 |
11 |
|
T19 |
6 |
|
T65 |
7 |
auto[1] |
no_err_inj |
1455 |
1 |
|
|
T11 |
12 |
|
T19 |
6 |
|
T65 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50055 |
1 |
|
|
T2 |
6 |
|
T3 |
66 |
|
T4 |
9 |
auto[0] |
auto[1] |
1789 |
1 |
|
|
T3 |
6 |
|
T5 |
5 |
|
T11 |
45 |
auto[1] |
auto[0] |
2785 |
1 |
|
|
T11 |
22 |
|
T19 |
12 |
|
T65 |
12 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T11 |
1 |
|
T52 |
3 |
|
T48 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49971 |
1 |
|
|
T2 |
6 |
|
T3 |
66 |
|
T4 |
9 |
auto[0] |
auto[1] |
1873 |
1 |
|
|
T3 |
6 |
|
T5 |
10 |
|
T11 |
55 |
auto[1] |
auto[0] |
2768 |
1 |
|
|
T11 |
21 |
|
T19 |
12 |
|
T65 |
10 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T11 |
2 |
|
T65 |
2 |
|
T48 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50062 |
1 |
|
|
T2 |
6 |
|
T3 |
60 |
|
T4 |
9 |
auto[0] |
auto[1] |
1782 |
1 |
|
|
T3 |
12 |
|
T5 |
11 |
|
T11 |
51 |
auto[1] |
auto[0] |
2733 |
1 |
|
|
T11 |
22 |
|
T19 |
11 |
|
T65 |
12 |
auto[1] |
auto[1] |
202 |
1 |
|
|
T11 |
1 |
|
T19 |
1 |
|
T52 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50100 |
1 |
|
|
T2 |
6 |
|
T3 |
69 |
|
T4 |
9 |
auto[0] |
auto[1] |
1744 |
1 |
|
|
T3 |
3 |
|
T5 |
14 |
|
T11 |
49 |
auto[1] |
auto[0] |
2765 |
1 |
|
|
T11 |
21 |
|
T19 |
10 |
|
T65 |
11 |
auto[1] |
auto[1] |
170 |
1 |
|
|
T11 |
2 |
|
T19 |
2 |
|
T65 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50075 |
1 |
|
|
T2 |
6 |
|
T3 |
63 |
|
T4 |
9 |
auto[0] |
auto[1] |
1769 |
1 |
|
|
T3 |
9 |
|
T5 |
6 |
|
T11 |
61 |
auto[1] |
auto[0] |
2758 |
1 |
|
|
T11 |
20 |
|
T19 |
12 |
|
T65 |
11 |
auto[1] |
auto[1] |
177 |
1 |
|
|
T11 |
3 |
|
T65 |
1 |
|
T52 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49993 |
1 |
|
|
T2 |
6 |
|
T3 |
65 |
|
T4 |
9 |
auto[0] |
auto[1] |
1851 |
1 |
|
|
T3 |
7 |
|
T5 |
10 |
|
T11 |
48 |
auto[1] |
auto[0] |
2785 |
1 |
|
|
T11 |
23 |
|
T19 |
12 |
|
T65 |
11 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T65 |
1 |
|
T52 |
1 |
|
T48 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36935 |
1 |
|
|
T3 |
72 |
|
T11 |
453 |
|
T12 |
7 |
auto[0] |
auto[1] |
1131 |
1 |
|
|
T11 |
18 |
|
T52 |
13 |
|
T48 |
20 |
auto[1] |
auto[0] |
15986 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
auto[1] |
auto[1] |
727 |
1 |
|
|
T11 |
19 |
|
T19 |
20 |
|
T20 |
15 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36934 |
1 |
|
|
T3 |
72 |
|
T11 |
454 |
|
T12 |
7 |
auto[0] |
auto[1] |
1132 |
1 |
|
|
T11 |
17 |
|
T52 |
11 |
|
T48 |
15 |
auto[1] |
auto[0] |
15993 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
auto[1] |
auto[1] |
720 |
1 |
|
|
T11 |
6 |
|
T19 |
23 |
|
T20 |
8 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36766 |
1 |
|
|
T3 |
72 |
|
T11 |
432 |
|
T12 |
7 |
auto[0] |
auto[1] |
1300 |
1 |
|
|
T11 |
39 |
|
T31 |
9 |
|
T35 |
13 |
auto[1] |
auto[0] |
15731 |
1 |
|
|
T2 |
6 |
|
T5 |
77 |
|
T11 |
352 |
auto[1] |
auto[1] |
982 |
1 |
|
|
T4 |
9 |
|
T11 |
17 |
|
T15 |
18 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36933 |
1 |
|
|
T3 |
72 |
|
T11 |
453 |
|
T12 |
7 |
auto[0] |
auto[1] |
1133 |
1 |
|
|
T11 |
18 |
|
T52 |
22 |
|
T48 |
21 |
auto[1] |
auto[0] |
15946 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
auto[1] |
auto[1] |
767 |
1 |
|
|
T11 |
19 |
|
T19 |
13 |
|
T20 |
7 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33177 |
1 |
|
|
T3 |
72 |
|
T11 |
457 |
|
T12 |
7 |
auto[0] |
auto[1] |
4889 |
1 |
|
|
T11 |
14 |
|
T18 |
96 |
|
T229 |
59 |
auto[1] |
auto[0] |
16010 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
auto[1] |
auto[1] |
703 |
1 |
|
|
T11 |
9 |
|
T19 |
21 |
|
T20 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37013 |
1 |
|
|
T3 |
66 |
|
T11 |
446 |
|
T12 |
7 |
auto[0] |
auto[1] |
1053 |
1 |
|
|
T3 |
6 |
|
T11 |
25 |
|
T30 |
7 |
auto[1] |
auto[0] |
15827 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
72 |
auto[1] |
auto[1] |
886 |
1 |
|
|
T5 |
5 |
|
T11 |
21 |
|
T21 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36926 |
1 |
|
|
T3 |
65 |
|
T11 |
439 |
|
T12 |
7 |
auto[0] |
auto[1] |
1140 |
1 |
|
|
T3 |
7 |
|
T11 |
32 |
|
T30 |
7 |
auto[1] |
auto[0] |
15829 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
67 |
auto[1] |
auto[1] |
884 |
1 |
|
|
T5 |
10 |
|
T11 |
25 |
|
T21 |
12 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36935 |
1 |
|
|
T3 |
66 |
|
T11 |
431 |
|
T12 |
7 |
auto[0] |
auto[1] |
1131 |
1 |
|
|
T3 |
6 |
|
T11 |
40 |
|
T30 |
10 |
auto[1] |
auto[0] |
15804 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
67 |
auto[1] |
auto[1] |
909 |
1 |
|
|
T5 |
10 |
|
T11 |
17 |
|
T21 |
8 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36991 |
1 |
|
|
T3 |
59 |
|
T11 |
439 |
|
T12 |
7 |
auto[0] |
auto[1] |
1075 |
1 |
|
|
T3 |
13 |
|
T11 |
32 |
|
T30 |
10 |
auto[1] |
auto[0] |
15856 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
71 |
auto[1] |
auto[1] |
857 |
1 |
|
|
T5 |
6 |
|
T11 |
24 |
|
T21 |
6 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36983 |
1 |
|
|
T3 |
69 |
|
T11 |
439 |
|
T12 |
7 |
auto[0] |
auto[1] |
1083 |
1 |
|
|
T3 |
3 |
|
T11 |
32 |
|
T30 |
13 |
auto[1] |
auto[0] |
15882 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
63 |
auto[1] |
auto[1] |
831 |
1 |
|
|
T5 |
14 |
|
T11 |
19 |
|
T21 |
6 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36939 |
1 |
|
|
T3 |
65 |
|
T11 |
443 |
|
T12 |
7 |
auto[0] |
auto[1] |
1127 |
1 |
|
|
T3 |
7 |
|
T11 |
28 |
|
T30 |
8 |
auto[1] |
auto[0] |
15839 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
67 |
auto[1] |
auto[1] |
874 |
1 |
|
|
T5 |
10 |
|
T11 |
20 |
|
T21 |
10 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36972 |
1 |
|
|
T3 |
72 |
|
T11 |
449 |
|
T12 |
7 |
auto[0] |
auto[1] |
1094 |
1 |
|
|
T11 |
22 |
|
T52 |
17 |
|
T48 |
13 |
auto[1] |
auto[0] |
16050 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
auto[1] |
auto[1] |
663 |
1 |
|
|
T11 |
18 |
|
T19 |
11 |
|
T20 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36978 |
1 |
|
|
T3 |
72 |
|
T11 |
453 |
|
T12 |
7 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T11 |
18 |
|
T52 |
17 |
|
T48 |
16 |
auto[1] |
auto[0] |
16035 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
auto[1] |
auto[1] |
678 |
1 |
|
|
T11 |
14 |
|
T19 |
16 |
|
T20 |
12 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36472 |
1 |
|
|
T3 |
72 |
|
T11 |
461 |
|
T12 |
7 |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T11 |
10 |
|
T19 |
12 |
|
T230 |
15 |
auto[1] |
auto[0] |
15372 |
1 |
|
|
T2 |
6 |
|
T4 |
9 |
|
T5 |
77 |
auto[1] |
auto[1] |
1341 |
1 |
|
|
T11 |
13 |
|
T65 |
12 |
|
T52 |
25 |