Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107219427

1

T1

1728

T2

76757

T3

20536

auto[1]

1412800

1

T3

2574

T4

294

T5

3038

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107187764

1

T1

1728

T2

76757

T3

20635

auto[1]

1444463

1

T3

2475

T4

589

T5

2940

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7611122	1			T1	127		T2	538		T3	7904
auto[IdleSt]	20851878	1			T1	1601		T2	8411		T3	1145
auto[ClkMuxSt]	35877	1			T2	6		T4	9		T11	359
auto[CntIncrSt]	35607	1			T2	6		T4	9		T11	359
auto[CntProgSt]	1669009	1			T2	1584		T4	18		T11	11381
auto[TransCheckSt]	27824	1			T2	6		T11	233		T12	7
auto[TokenHashSt]	45159363	1			T2	61750		T11	115005		T12	25116
auto[FlashRmaSt]	28746	1			T2	6		T11	320		T12	11
auto[TokenCheck0St]	13241	1			T2	6		T11	110		T12	7
auto[TokenCheck1St]	9872	1			T2	6		T11	90		T12	7
auto[TransProgSt]	468612	1			T2	2530		T11	3540		T12	184
auto[PostTransSt]	12611200	1			T2	1908		T4	4541		T11	238635
auto[ScrapSt]	134990	1			T11	1851		T16	9		T17	6
auto[EscalateSt]	7134331	1			T3	6919		T4	3593		T5	28720
auto[InvalidSt]	12838453	1			T3	7136		T5	98018		T11	397528

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2102	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12838453	1			T3	7136		T5	98018		T11	397528
EscalateSt	7134331	1			T3	6919		T4	3593		T5	28720
ScrapSt	134990	1			T11	1851		T16	9		T17	6
PostTransSt	12611200	1			T2	1908		T4	4541		T11	238635
TransProgSt	468612	1			T2	2530		T11	3540		T12	184
TokenCheck1St	9872	1			T2	6		T11	90		T12	7
TokenCheck0St	13241	1			T2	6		T11	110		T12	7
FlashRmaSt	28746	1			T2	6		T11	320		T12	11
TokenHashSt	45159363	1			T2	61750		T11	115005		T12	25116
TransCheckSt	27824	1			T2	6		T11	233		T12	7
CntProgSt	1669009	1			T2	1584		T4	18		T11	11381
CntIncrSt	35607	1			T2	6		T4	9		T11	359
ClkMuxSt	35877	1			T2	6		T4	9		T11	359
IdleSt	20851878	1			T1	1601		T2	8411		T3	1145
ResetSt	7611122	1			T1	127		T2	538		T3	7904
arcs[ResetSt=>IdleSt]	54894	1			T1	1		T2	6		T3	64
arcs[IdleSt=>ScrapSt]	262	1			T11	4		T16	3		T17	2
arcs[IdleSt=>ClkMuxSt]	35681	1			T2	6		T4	9		T11	359
arcs[ClkMuxSt=>CntIncrSt]	35607	1			T2	6		T4	9		T11	359
arcs[CntIncrSt=>PostTransSt]	1768	1			T11	33		T19	16		T20	12
arcs[CntIncrSt=>CntProgSt]	33759	1			T2	6		T4	9		T11	326
arcs[CntProgSt=>PostTransSt]	4884	1			T4	9		T11	93		T15	18
arcs[CntProgSt=>TransCheckSt]	27824	1			T2	6		T11	233		T12	7
arcs[TransCheckSt=>PostTransSt]	3557	1			T11	40		T47	34		T36	38
arcs[TransCheckSt=>TokenHashSt]	24139	1			T2	6		T11	193		T12	7
arcs[TokenHashSt=>PostTransSt]	10134	1			T11	83		T18	96		T47	12
arcs[TokenHashSt=>FlashRmaSt]	13321	1			T2	6		T11	110		T12	7
arcs[FlashRmaSt=>TokenCheck0St]	13241	1			T2	6		T11	110		T12	7
arcs[TokenCheck0St=>PostTransSt]	3334	1			T11	20		T47	4		T46	12
arcs[TokenCheck0St=>TokenCheck1St]	9872	1			T2	6		T11	90		T12	7
arcs[TokenCheck1St=>PostTransSt]	623	1			T11	2		T47	15		T46	1
arcs[TransProgSt=>PostTransSt]	8362	1			T2	6		T11	88		T12	7
arcs[IdleSt=>EscalateSt]	185	1			T16	4		T17	7		T29	6
arcs[ClkMuxSt=>EscalateSt]	74	1			T16	2		T17	1		T29	1
arcs[CntIncrSt=>EscalateSt]	80	1			T16	2		T17	5		T29	4
arcs[CntProgSt=>EscalateSt]	1051	1			T16	9		T17	12		T29	6
arcs[TransCheckSt=>EscalateSt]	128	1			T16	7		T17	5		T29	7
arcs[TokenHashSt=>EscalateSt]	682	1			T16	16		T17	19		T29	14
arcs[FlashRmaSt=>EscalateSt]	80	1			T16	1		T17	3		T29	1
arcs[TokenCheck0St=>EscalateSt]	35	1			T16	2		T17	2		T44	2
arcs[TokenCheck1St=>EscalateSt]	140	1			T16	1		T17	6		T29	6
arcs[TransProgSt=>EscalateSt]	747	1			T16	8		T17	14		T29	9
arcs[PostTransSt=>EscalateSt]	5157	1			T4	9		T11	93		T15	18
arcs[InvalidSt=>EscalateSt]	14592	1			T3	51		T5	61		T11	379

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7610964	1			T1	127		T2	538		T3	7904
auto[0]	auto[IdleSt]	20851750	1			T1	1601		T2	8411		T3	1145
auto[0]	auto[ClkMuxSt]	35824	1			T2	6		T4	9		T11	359
auto[0]	auto[CntIncrSt]	35560	1			T2	6		T4	9		T11	359
auto[0]	auto[CntProgSt]	1668309	1			T2	1584		T4	18		T11	11381
auto[0]	auto[TransCheckSt]	27737	1			T2	6		T11	233		T12	7
auto[0]	auto[TokenHashSt]	45158914	1			T2	61750		T11	115005		T12	25116
auto[0]	auto[FlashRmaSt]	28697	1			T2	6		T11	320		T12	11
auto[0]	auto[TokenCheck0St]	13216	1			T2	6		T11	110		T12	7
auto[0]	auto[TokenCheck1St]	9776	1			T2	6		T11	90		T12	7
auto[0]	auto[TransProgSt]	468127	1			T2	2530		T11	3540		T12	184
auto[0]	auto[PostTransSt]	12608580	1			T2	1908		T4	4538		T11	238592
auto[0]	auto[ScrapSt]	134950	1			T11	1851		T16	7		T17	4
auto[0]	auto[EscalateSt]	5733643	1			T3	4371		T4	3302		T5	25713
auto[0]	auto[InvalidSt]	12831278	1			T3	7110		T5	97987		T11	397344
auto[1]	auto[ResetSt]	158	1			T16	3		T29	3		T44	2
auto[1]	auto[IdleSt]	128	1			T16	3		T17	4		T29	5
auto[1]	auto[ClkMuxSt]	53	1			T16	2		T17	1		T29	1
auto[1]	auto[CntIncrSt]	47	1			T16	1		T17	2		T29	2
auto[1]	auto[CntProgSt]	700	1			T16	7		T17	2		T29	3
auto[1]	auto[TransCheckSt]	87	1			T16	4		T17	4		T29	5
auto[1]	auto[TokenHashSt]	449	1			T16	8		T17	10		T29	8
auto[1]	auto[FlashRmaSt]	49	1			T17	3		T29	1		T227	1
auto[1]	auto[TokenCheck0St]	25	1			T16	1		T17	2		T44	2
auto[1]	auto[TokenCheck1St]	96	1			T17	4		T29	5		T44	3
auto[1]	auto[TransProgSt]	485	1			T16	3		T17	9		T29	4
auto[1]	auto[PostTransSt]	2620	1			T4	3		T11	43		T15	7
auto[1]	auto[ScrapSt]	40	1			T16	2		T17	2		T29	2
auto[1]	auto[EscalateSt]	1400688	1			T3	2548		T4	291		T5	3007
auto[1]	auto[InvalidSt]	7175	1			T3	26		T5	31		T11	184

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7610952	1			T1	127		T2	538		T3	7904
auto[0]	auto[IdleSt]	20851757	1			T1	1601		T2	8411		T3	1145
auto[0]	auto[ClkMuxSt]	35839	1			T2	6		T4	9		T11	359
auto[0]	auto[CntIncrSt]	35549	1			T2	6		T4	9		T11	359
auto[0]	auto[CntProgSt]	1668314	1			T2	1584		T4	18		T11	11381
auto[0]	auto[TransCheckSt]	27741	1			T2	6		T11	233		T12	7
auto[0]	auto[TokenHashSt]	45158902	1			T2	61750		T11	115005		T12	25116
auto[0]	auto[FlashRmaSt]	28689	1			T2	6		T11	320		T12	11
auto[0]	auto[TokenCheck0St]	13224	1			T2	6		T11	110		T12	7
auto[0]	auto[TokenCheck1St]	9783	1			T2	6		T11	90		T12	7
auto[0]	auto[TransProgSt]	468094	1			T2	2530		T11	3540		T12	184
auto[0]	auto[PostTransSt]	12608568	1			T2	1908		T4	4535		T11	238585
auto[0]	auto[ScrapSt]	134946	1			T11	1851		T16	7		T17	6
auto[0]	auto[EscalateSt]	5702268	1			T3	4469		T4	3010		T5	25810
auto[0]	auto[InvalidSt]	12831036	1			T3	7111		T5	97988		T11	397333
auto[1]	auto[ResetSt]	170	1			T16	4		T17	1		T29	2
auto[1]	auto[IdleSt]	121	1			T16	1		T17	6		T29	3
auto[1]	auto[ClkMuxSt]	38	1			T16	1		T227	1		T228	2
auto[1]	auto[CntIncrSt]	58	1			T16	1		T17	4		T29	3
auto[1]	auto[CntProgSt]	695	1			T16	6		T17	10		T29	5
auto[1]	auto[TransCheckSt]	83	1			T16	5		T17	2		T29	4
auto[1]	auto[TokenHashSt]	461	1			T16	13		T17	17		T29	10
auto[1]	auto[FlashRmaSt]	57	1			T16	1		T29	1		T44	5
auto[1]	auto[TokenCheck0St]	17	1			T16	1		T17	1		T44	2
auto[1]	auto[TokenCheck1St]	89	1			T16	1		T17	5		T29	2
auto[1]	auto[TransProgSt]	518	1			T16	7		T17	10		T29	6
auto[1]	auto[PostTransSt]	2632	1			T4	6		T11	50		T15	11
auto[1]	auto[ScrapSt]	44	1			T16	2		T29	4		T44	1
auto[1]	auto[EscalateSt]	1432063	1			T3	2450		T4	583		T5	2910
auto[1]	auto[InvalidSt]	7417	1			T3	25		T5	30		T11	195