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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.86 97.89 95.50 93.31 97.67 98.55 99.00 96.11


Total test records in report: 1002
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T163 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1794090062 May 07 01:27:01 PM PDT 24 May 07 01:35:56 PM PDT 24 15868609503 ps
T812 /workspace/coverage/default/40.lc_ctrl_state_post_trans.2413772097 May 07 01:28:17 PM PDT 24 May 07 01:28:27 PM PDT 24 49624354 ps
T813 /workspace/coverage/default/39.lc_ctrl_errors.2845380659 May 07 01:28:21 PM PDT 24 May 07 01:28:32 PM PDT 24 357750856 ps
T814 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.87156244 May 07 01:26:20 PM PDT 24 May 07 01:27:03 PM PDT 24 4172793965 ps
T815 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3943760030 May 07 01:27:48 PM PDT 24 May 07 01:27:50 PM PDT 24 13826955 ps
T816 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2071751154 May 07 01:27:46 PM PDT 24 May 07 01:27:48 PM PDT 24 81908225 ps
T817 /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3243091415 May 07 01:28:02 PM PDT 24 May 07 01:28:11 PM PDT 24 462579185 ps
T818 /workspace/coverage/default/19.lc_ctrl_jtag_errors.1089716522 May 07 01:27:25 PM PDT 24 May 07 01:28:41 PM PDT 24 10866746622 ps
T819 /workspace/coverage/default/37.lc_ctrl_state_post_trans.1812595196 May 07 01:28:09 PM PDT 24 May 07 01:28:17 PM PDT 24 292692895 ps
T820 /workspace/coverage/default/18.lc_ctrl_errors.1094129750 May 07 01:27:26 PM PDT 24 May 07 01:27:45 PM PDT 24 1187010853 ps
T821 /workspace/coverage/default/44.lc_ctrl_jtag_access.2855210389 May 07 01:28:29 PM PDT 24 May 07 01:28:33 PM PDT 24 805159346 ps
T822 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.230749121 May 07 01:27:46 PM PDT 24 May 07 01:27:55 PM PDT 24 278044429 ps
T823 /workspace/coverage/default/33.lc_ctrl_smoke.859109649 May 07 01:27:54 PM PDT 24 May 07 01:27:59 PM PDT 24 32162699 ps
T824 /workspace/coverage/default/49.lc_ctrl_stress_all.1668350250 May 07 01:28:41 PM PDT 24 May 07 01:28:56 PM PDT 24 3129893570 ps
T825 /workspace/coverage/default/8.lc_ctrl_stress_all.259263395 May 07 01:26:40 PM PDT 24 May 07 01:28:46 PM PDT 24 11639896313 ps
T826 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.711593313 May 07 01:27:32 PM PDT 24 May 07 01:27:36 PM PDT 24 33461929 ps
T827 /workspace/coverage/default/43.lc_ctrl_smoke.3297840276 May 07 01:28:25 PM PDT 24 May 07 01:28:33 PM PDT 24 254912403 ps
T828 /workspace/coverage/default/9.lc_ctrl_state_post_trans.2465783274 May 07 01:26:50 PM PDT 24 May 07 01:26:59 PM PDT 24 100072899 ps
T829 /workspace/coverage/default/41.lc_ctrl_state_failure.2231088046 May 07 01:28:19 PM PDT 24 May 07 01:28:45 PM PDT 24 230060711 ps
T830 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1299873020 May 07 01:26:39 PM PDT 24 May 07 01:26:48 PM PDT 24 1344700075 ps
T831 /workspace/coverage/default/41.lc_ctrl_security_escalation.2396588289 May 07 01:28:20 PM PDT 24 May 07 01:28:29 PM PDT 24 2955161145 ps
T832 /workspace/coverage/default/15.lc_ctrl_security_escalation.1692500820 May 07 01:27:10 PM PDT 24 May 07 01:27:23 PM PDT 24 825025979 ps
T833 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1665132483 May 07 01:28:25 PM PDT 24 May 07 01:28:28 PM PDT 24 46861337 ps
T834 /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3940316207 May 07 01:26:36 PM PDT 24 May 07 01:42:00 PM PDT 24 24094781788 ps
T835 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2038663225 May 07 01:27:38 PM PDT 24 May 07 01:27:41 PM PDT 24 37985939 ps
T836 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.371382523 May 07 01:27:27 PM PDT 24 May 07 01:28:00 PM PDT 24 901881307 ps
T837 /workspace/coverage/default/14.lc_ctrl_state_failure.4125477088 May 07 01:26:59 PM PDT 24 May 07 01:27:22 PM PDT 24 2680979096 ps
T838 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1974998649 May 07 01:27:16 PM PDT 24 May 07 01:27:31 PM PDT 24 445573310 ps
T839 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4181897503 May 07 01:28:17 PM PDT 24 May 07 01:28:28 PM PDT 24 947899392 ps
T840 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.551913736 May 07 01:26:38 PM PDT 24 May 07 01:26:49 PM PDT 24 877615516 ps
T841 /workspace/coverage/default/48.lc_ctrl_smoke.2781482231 May 07 01:28:35 PM PDT 24 May 07 01:28:43 PM PDT 24 459303149 ps
T842 /workspace/coverage/default/42.lc_ctrl_smoke.2338518647 May 07 01:28:17 PM PDT 24 May 07 01:28:21 PM PDT 24 54286253 ps
T843 /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.803101381 May 07 01:26:31 PM PDT 24 May 07 01:26:33 PM PDT 24 41257936 ps
T844 /workspace/coverage/default/39.lc_ctrl_stress_all.3626383755 May 07 01:28:17 PM PDT 24 May 07 01:32:01 PM PDT 24 12025633739 ps
T845 /workspace/coverage/default/30.lc_ctrl_stress_all.1932546604 May 07 01:27:50 PM PDT 24 May 07 01:30:17 PM PDT 24 11084025178 ps
T846 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2617538709 May 07 01:26:47 PM PDT 24 May 07 01:27:02 PM PDT 24 1987820116 ps
T847 /workspace/coverage/default/6.lc_ctrl_alert_test.1097700500 May 07 01:26:40 PM PDT 24 May 07 01:26:44 PM PDT 24 23327616 ps
T848 /workspace/coverage/default/8.lc_ctrl_state_failure.2874697408 May 07 01:26:41 PM PDT 24 May 07 01:27:11 PM PDT 24 910375971 ps
T849 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.323835648 May 07 01:27:54 PM PDT 24 May 07 01:28:04 PM PDT 24 980797903 ps
T850 /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2468344096 May 07 01:26:48 PM PDT 24 May 07 01:38:35 PM PDT 24 34682611406 ps
T851 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1444261755 May 07 01:27:26 PM PDT 24 May 07 01:27:42 PM PDT 24 1174412268 ps
T852 /workspace/coverage/default/39.lc_ctrl_alert_test.1916200089 May 07 01:28:19 PM PDT 24 May 07 01:28:20 PM PDT 24 27285418 ps
T853 /workspace/coverage/default/31.lc_ctrl_jtag_access.1728333171 May 07 01:27:52 PM PDT 24 May 07 01:27:57 PM PDT 24 1006783881 ps
T854 /workspace/coverage/default/45.lc_ctrl_errors.836171150 May 07 01:28:31 PM PDT 24 May 07 01:28:41 PM PDT 24 750530091 ps
T855 /workspace/coverage/default/15.lc_ctrl_sec_mubi.1602785074 May 07 01:27:13 PM PDT 24 May 07 01:27:34 PM PDT 24 1719467677 ps
T856 /workspace/coverage/default/13.lc_ctrl_errors.1748116929 May 07 01:27:02 PM PDT 24 May 07 01:27:18 PM PDT 24 309064448 ps
T857 /workspace/coverage/default/21.lc_ctrl_state_post_trans.3793138103 May 07 01:27:25 PM PDT 24 May 07 01:27:33 PM PDT 24 1064655344 ps
T858 /workspace/coverage/default/3.lc_ctrl_alert_test.513320934 May 07 01:26:33 PM PDT 24 May 07 01:26:35 PM PDT 24 90253282 ps
T859 /workspace/coverage/default/29.lc_ctrl_state_post_trans.1000243821 May 07 01:27:45 PM PDT 24 May 07 01:27:53 PM PDT 24 136247956 ps
T860 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3497836429 May 07 01:26:40 PM PDT 24 May 07 01:26:43 PM PDT 24 20653228 ps
T861 /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1227927979 May 07 01:26:40 PM PDT 24 May 07 01:26:53 PM PDT 24 3150073712 ps
T862 /workspace/coverage/default/38.lc_ctrl_security_escalation.734982698 May 07 01:28:10 PM PDT 24 May 07 01:28:20 PM PDT 24 2180081113 ps
T863 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3161561676 May 07 01:26:22 PM PDT 24 May 07 01:26:24 PM PDT 24 12673882 ps
T864 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3546770114 May 07 01:27:26 PM PDT 24 May 07 01:28:12 PM PDT 24 1076509827 ps
T865 /workspace/coverage/default/18.lc_ctrl_alert_test.596861595 May 07 01:27:28 PM PDT 24 May 07 01:27:31 PM PDT 24 14576077 ps
T866 /workspace/coverage/default/23.lc_ctrl_sec_token_digest.720162014 May 07 01:27:33 PM PDT 24 May 07 01:27:55 PM PDT 24 516550905 ps
T867 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1989240336 May 07 01:27:27 PM PDT 24 May 07 01:27:45 PM PDT 24 467869202 ps
T868 /workspace/coverage/default/3.lc_ctrl_prog_failure.4249273472 May 07 01:26:32 PM PDT 24 May 07 01:26:36 PM PDT 24 134086731 ps
T869 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3345520610 May 07 01:27:18 PM PDT 24 May 07 01:27:31 PM PDT 24 1620462456 ps
T870 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1048991238 May 07 01:27:18 PM PDT 24 May 07 01:27:28 PM PDT 24 396423337 ps
T871 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2505261829 May 07 01:28:19 PM PDT 24 May 07 01:28:21 PM PDT 24 44050763 ps
T872 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2955817092 May 07 01:27:12 PM PDT 24 May 07 01:27:26 PM PDT 24 4534923588 ps
T873 /workspace/coverage/default/42.lc_ctrl_state_failure.4150425642 May 07 01:28:21 PM PDT 24 May 07 01:28:45 PM PDT 24 285128899 ps
T874 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.835536862 May 07 01:27:30 PM PDT 24 May 07 01:27:32 PM PDT 24 20477510 ps
T875 /workspace/coverage/default/16.lc_ctrl_stress_all.3589654075 May 07 01:27:19 PM PDT 24 May 07 01:32:48 PM PDT 24 85417162031 ps
T876 /workspace/coverage/default/2.lc_ctrl_jtag_priority.2080348131 May 07 01:26:29 PM PDT 24 May 07 01:26:36 PM PDT 24 412676748 ps
T877 /workspace/coverage/default/44.lc_ctrl_state_post_trans.42232689 May 07 01:28:28 PM PDT 24 May 07 01:28:33 PM PDT 24 500158127 ps
T132 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4066480124 May 07 12:39:48 PM PDT 24 May 07 12:40:01 PM PDT 24 3094331702 ps
T133 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3591364987 May 07 12:39:54 PM PDT 24 May 07 12:40:12 PM PDT 24 6436494097 ps
T121 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.408825969 May 07 12:40:13 PM PDT 24 May 07 12:40:19 PM PDT 24 323076050 ps
T158 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3947105960 May 07 12:40:13 PM PDT 24 May 07 12:40:30 PM PDT 24 4158616648 ps
T150 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1467698939 May 07 12:40:10 PM PDT 24 May 07 12:40:18 PM PDT 24 19198927 ps
T122 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.213287404 May 07 12:40:01 PM PDT 24 May 07 12:40:06 PM PDT 24 77468940 ps
T151 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1587428601 May 07 12:40:19 PM PDT 24 May 07 12:40:23 PM PDT 24 70599330 ps
T123 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3852484979 May 07 12:40:11 PM PDT 24 May 07 12:40:16 PM PDT 24 134442695 ps
T222 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3473269371 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 29683226 ps
T126 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1213128681 May 07 12:40:15 PM PDT 24 May 07 12:40:20 PM PDT 24 42712753 ps
T878 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2131603678 May 07 12:40:08 PM PDT 24 May 07 12:40:30 PM PDT 24 3517549648 ps
T213 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4250495720 May 07 12:40:07 PM PDT 24 May 07 12:40:09 PM PDT 24 34232709 ps
T164 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1752477289 May 07 12:39:52 PM PDT 24 May 07 12:39:55 PM PDT 24 48258782 ps
T172 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2638063415 May 07 12:39:58 PM PDT 24 May 07 12:40:01 PM PDT 24 26621948 ps
T134 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1846092831 May 07 12:39:54 PM PDT 24 May 07 12:40:00 PM PDT 24 186382034 ps
T155 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4166779047 May 07 12:39:51 PM PDT 24 May 07 12:39:54 PM PDT 24 58838940 ps
T214 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1163104326 May 07 12:39:54 PM PDT 24 May 07 12:39:57 PM PDT 24 13302531 ps
T201 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2025622742 May 07 12:40:00 PM PDT 24 May 07 12:40:03 PM PDT 24 112852381 ps
T202 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2166666802 May 07 12:39:48 PM PDT 24 May 07 12:39:51 PM PDT 24 22425436 ps
T156 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3559596278 May 07 12:39:56 PM PDT 24 May 07 12:40:05 PM PDT 24 506912987 ps
T157 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3843715521 May 07 12:40:23 PM PDT 24 May 07 12:40:30 PM PDT 24 150937486 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.117712105 May 07 12:39:58 PM PDT 24 May 07 12:40:03 PM PDT 24 116582936 ps
T152 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2516389305 May 07 12:39:55 PM PDT 24 May 07 12:40:07 PM PDT 24 1563986028 ps
T153 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.224096465 May 07 12:40:05 PM PDT 24 May 07 12:40:08 PM PDT 24 340273703 ps
T127 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.148577452 May 07 12:40:04 PM PDT 24 May 07 12:40:09 PM PDT 24 199388648 ps
T165 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.366990211 May 07 12:40:00 PM PDT 24 May 07 12:40:04 PM PDT 24 185213133 ps
T154 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3635535691 May 07 12:39:53 PM PDT 24 May 07 12:39:57 PM PDT 24 32970396 ps
T215 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4280631955 May 07 12:39:56 PM PDT 24 May 07 12:39:59 PM PDT 24 20598774 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2614767742 May 07 12:40:01 PM PDT 24 May 07 12:40:04 PM PDT 24 106542402 ps
T203 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2068541675 May 07 12:40:17 PM PDT 24 May 07 12:40:22 PM PDT 24 45756349 ps
T216 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3863930193 May 07 12:40:01 PM PDT 24 May 07 12:40:04 PM PDT 24 137885192 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2286918188 May 07 12:39:54 PM PDT 24 May 07 12:39:57 PM PDT 24 53619710 ps
T130 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3708037712 May 07 12:39:51 PM PDT 24 May 07 12:39:57 PM PDT 24 127054883 ps
T141 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3974901835 May 07 12:40:00 PM PDT 24 May 07 12:40:05 PM PDT 24 441799264 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3603981254 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 38296987 ps
T128 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.269492842 May 07 12:40:07 PM PDT 24 May 07 12:40:10 PM PDT 24 46496825 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2599429473 May 07 12:40:05 PM PDT 24 May 07 12:40:08 PM PDT 24 36779985 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3959263949 May 07 12:39:57 PM PDT 24 May 07 12:40:20 PM PDT 24 3647854964 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.498236882 May 07 12:39:55 PM PDT 24 May 07 12:39:59 PM PDT 24 60107447 ps
T135 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3713693873 May 07 12:40:21 PM PDT 24 May 07 12:40:26 PM PDT 24 296214160 ps
T885 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1494599410 May 07 12:40:25 PM PDT 24 May 07 12:40:28 PM PDT 24 15025132 ps
T886 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4275602866 May 07 12:39:54 PM PDT 24 May 07 12:39:59 PM PDT 24 169021824 ps
T131 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3431485331 May 07 12:40:04 PM PDT 24 May 07 12:40:10 PM PDT 24 219883083 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4003387879 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 39006894 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1978614238 May 07 12:40:14 PM PDT 24 May 07 12:40:24 PM PDT 24 292863662 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3820324400 May 07 12:39:59 PM PDT 24 May 07 12:40:03 PM PDT 24 40055216 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4187160740 May 07 12:40:05 PM PDT 24 May 07 12:40:10 PM PDT 24 121749575 ps
T891 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1812473209 May 07 12:40:09 PM PDT 24 May 07 12:40:12 PM PDT 24 44487589 ps
T892 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2558499605 May 07 12:40:21 PM PDT 24 May 07 12:40:25 PM PDT 24 58173296 ps
T893 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2850589494 May 07 12:39:50 PM PDT 24 May 07 12:39:57 PM PDT 24 294162960 ps
T142 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.893440481 May 07 12:39:54 PM PDT 24 May 07 12:39:59 PM PDT 24 183824636 ps
T217 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2482239149 May 07 12:40:02 PM PDT 24 May 07 12:40:05 PM PDT 24 16911514 ps
T218 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2620070609 May 07 12:39:57 PM PDT 24 May 07 12:40:00 PM PDT 24 89911313 ps
T146 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4174823344 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 403240842 ps
T894 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2872968850 May 07 12:40:18 PM PDT 24 May 07 12:40:24 PM PDT 24 40559216 ps
T219 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.481556224 May 07 12:39:57 PM PDT 24 May 07 12:40:00 PM PDT 24 96256140 ps
T895 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2009618573 May 07 12:40:08 PM PDT 24 May 07 12:40:11 PM PDT 24 155629389 ps
T204 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2039870098 May 07 12:40:18 PM PDT 24 May 07 12:40:23 PM PDT 24 61606273 ps
T143 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3981718981 May 07 12:40:08 PM PDT 24 May 07 12:40:13 PM PDT 24 238920493 ps
T220 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1343147943 May 07 12:40:15 PM PDT 24 May 07 12:40:19 PM PDT 24 50414115 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1854222744 May 07 12:40:13 PM PDT 24 May 07 12:40:17 PM PDT 24 216318902 ps
T897 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2258615618 May 07 12:39:54 PM PDT 24 May 07 12:39:57 PM PDT 24 40171880 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3110266145 May 07 12:39:53 PM PDT 24 May 07 12:39:58 PM PDT 24 101332803 ps
T899 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3230047389 May 07 12:40:08 PM PDT 24 May 07 12:40:11 PM PDT 24 17359514 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2921742913 May 07 12:39:52 PM PDT 24 May 07 12:39:56 PM PDT 24 49117550 ps
T901 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2079939135 May 07 12:40:16 PM PDT 24 May 07 12:40:31 PM PDT 24 496681117 ps
T902 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1094449981 May 07 12:40:10 PM PDT 24 May 07 12:40:14 PM PDT 24 50163339 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1425358643 May 07 12:40:01 PM PDT 24 May 07 12:40:11 PM PDT 24 741841685 ps
T904 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3596883299 May 07 12:40:27 PM PDT 24 May 07 12:40:30 PM PDT 24 19578540 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4283107500 May 07 12:39:57 PM PDT 24 May 07 12:40:00 PM PDT 24 47324316 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3630123585 May 07 12:39:55 PM PDT 24 May 07 12:39:59 PM PDT 24 98277733 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1414695766 May 07 12:39:59 PM PDT 24 May 07 12:40:04 PM PDT 24 781709772 ps
T908 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3594658997 May 07 12:40:05 PM PDT 24 May 07 12:40:08 PM PDT 24 36040145 ps
T909 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1160243597 May 07 12:40:11 PM PDT 24 May 07 12:40:14 PM PDT 24 16109458 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.597783574 May 07 12:39:59 PM PDT 24 May 07 12:40:02 PM PDT 24 27056582 ps
T911 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3741215978 May 07 12:39:53 PM PDT 24 May 07 12:39:56 PM PDT 24 33221541 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1896652044 May 07 12:40:20 PM PDT 24 May 07 12:40:24 PM PDT 24 44513956 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3636563652 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 18107957 ps
T914 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4279284359 May 07 12:40:29 PM PDT 24 May 07 12:40:31 PM PDT 24 53127045 ps
T915 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3294318358 May 07 12:40:14 PM PDT 24 May 07 12:40:18 PM PDT 24 23248648 ps
T205 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1200606456 May 07 12:39:58 PM PDT 24 May 07 12:40:01 PM PDT 24 17499694 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1269907729 May 07 12:39:53 PM PDT 24 May 07 12:39:58 PM PDT 24 59797360 ps
T917 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.498471561 May 07 12:40:12 PM PDT 24 May 07 12:40:16 PM PDT 24 18965363 ps
T206 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3480509006 May 07 12:40:10 PM PDT 24 May 07 12:40:12 PM PDT 24 25918152 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1372489204 May 07 12:39:53 PM PDT 24 May 07 12:39:57 PM PDT 24 101237311 ps
T919 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4124093236 May 07 12:40:20 PM PDT 24 May 07 12:40:24 PM PDT 24 34611048 ps
T920 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.637550113 May 07 12:40:09 PM PDT 24 May 07 12:40:11 PM PDT 24 45716981 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4212221123 May 07 12:40:06 PM PDT 24 May 07 12:40:10 PM PDT 24 161445170 ps
T922 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4174964879 May 07 12:40:03 PM PDT 24 May 07 12:40:06 PM PDT 24 76123935 ps
T923 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.101656978 May 07 12:40:03 PM PDT 24 May 07 12:40:06 PM PDT 24 50490136 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2456773640 May 07 12:39:57 PM PDT 24 May 07 12:40:01 PM PDT 24 51104104 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.29871940 May 07 12:40:06 PM PDT 24 May 07 12:40:09 PM PDT 24 242202127 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1300639387 May 07 12:39:54 PM PDT 24 May 07 12:39:58 PM PDT 24 109241483 ps
T927 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4213577379 May 07 12:40:04 PM PDT 24 May 07 12:40:06 PM PDT 24 18350465 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2480215523 May 07 12:40:02 PM PDT 24 May 07 12:40:06 PM PDT 24 136335380 ps
T929 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.143272590 May 07 12:40:02 PM PDT 24 May 07 12:40:05 PM PDT 24 163836861 ps
T136 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.444072578 May 07 12:40:17 PM PDT 24 May 07 12:40:23 PM PDT 24 289898894 ps
T930 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.329510357 May 07 12:40:04 PM PDT 24 May 07 12:40:12 PM PDT 24 516696955 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2466835553 May 07 12:40:11 PM PDT 24 May 07 12:40:20 PM PDT 24 465714979 ps
T932 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.596043402 May 07 12:39:47 PM PDT 24 May 07 12:39:50 PM PDT 24 55730816 ps
T933 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.380013238 May 07 12:40:19 PM PDT 24 May 07 12:40:23 PM PDT 24 121896602 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.144326997 May 07 12:40:00 PM PDT 24 May 07 12:40:05 PM PDT 24 92232356 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2763441050 May 07 12:39:56 PM PDT 24 May 07 12:40:01 PM PDT 24 74253175 ps
T936 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.30905936 May 07 12:40:02 PM PDT 24 May 07 12:40:05 PM PDT 24 32121622 ps
T937 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3256577431 May 07 12:40:10 PM PDT 24 May 07 12:40:13 PM PDT 24 282995184 ps
T147 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1706623963 May 07 12:40:21 PM PDT 24 May 07 12:40:26 PM PDT 24 205583127 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2259517622 May 07 12:39:55 PM PDT 24 May 07 12:39:59 PM PDT 24 56740584 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1535503758 May 07 12:39:54 PM PDT 24 May 07 12:39:58 PM PDT 24 278071832 ps
T940 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3623924670 May 07 12:40:06 PM PDT 24 May 07 12:40:09 PM PDT 24 49778924 ps
T941 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2729616181 May 07 12:40:04 PM PDT 24 May 07 12:40:08 PM PDT 24 174706269 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2764836747 May 07 12:40:18 PM PDT 24 May 07 12:40:34 PM PDT 24 1467909971 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3649280233 May 07 12:39:58 PM PDT 24 May 07 12:40:06 PM PDT 24 909047082 ps
T139 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3808326063 May 07 12:40:05 PM PDT 24 May 07 12:40:09 PM PDT 24 114644842 ps
T944 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2146078251 May 07 12:40:10 PM PDT 24 May 07 12:40:13 PM PDT 24 139293390 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.490422484 May 07 12:39:47 PM PDT 24 May 07 12:39:54 PM PDT 24 477600389 ps
T946 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.863229626 May 07 12:39:59 PM PDT 24 May 07 12:40:02 PM PDT 24 17048458 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2243946937 May 07 12:40:05 PM PDT 24 May 07 12:40:08 PM PDT 24 150123701 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2803869061 May 07 12:40:15 PM PDT 24 May 07 12:40:21 PM PDT 24 351764983 ps
T144 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2506220647 May 07 12:40:15 PM PDT 24 May 07 12:40:21 PM PDT 24 112537139 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3992400686 May 07 12:40:03 PM PDT 24 May 07 12:40:06 PM PDT 24 66791164 ps
T950 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3268820589 May 07 12:40:12 PM PDT 24 May 07 12:40:15 PM PDT 24 66858646 ps
T951 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1347218049 May 07 12:40:07 PM PDT 24 May 07 12:40:10 PM PDT 24 13409139 ps
T952 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2393963288 May 07 12:40:00 PM PDT 24 May 07 12:40:22 PM PDT 24 3497117412 ps
T953 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1615402792 May 07 12:39:54 PM PDT 24 May 07 12:40:02 PM PDT 24 1699571958 ps
T140 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1421785090 May 07 12:40:04 PM PDT 24 May 07 12:40:08 PM PDT 24 206047744 ps
T954 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1139702812 May 07 12:40:01 PM PDT 24 May 07 12:40:05 PM PDT 24 43812078 ps
T955 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.864628219 May 07 12:40:31 PM PDT 24 May 07 12:40:38 PM PDT 24 219242050 ps
T956 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1677368267 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 117919422 ps
T207 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3526362276 May 07 12:39:58 PM PDT 24 May 07 12:40:02 PM PDT 24 38145689 ps
T148 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1720753369 May 07 12:40:09 PM PDT 24 May 07 12:40:14 PM PDT 24 192850309 ps
T957 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1534280100 May 07 12:40:28 PM PDT 24 May 07 12:40:30 PM PDT 24 63612772 ps
T208 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.683348294 May 07 12:39:59 PM PDT 24 May 07 12:40:02 PM PDT 24 42216706 ps
T958 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2434988963 May 07 12:40:12 PM PDT 24 May 07 12:40:16 PM PDT 24 25441866 ps
T959 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2319576667 May 07 12:39:57 PM PDT 24 May 07 12:40:05 PM PDT 24 677621038 ps
T145 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.340215509 May 07 12:40:11 PM PDT 24 May 07 12:40:15 PM PDT 24 47041879 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2878378793 May 07 12:40:00 PM PDT 24 May 07 12:40:03 PM PDT 24 115480619 ps
T961 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2010935856 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 16658949 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.583433911 May 07 12:40:10 PM PDT 24 May 07 12:40:13 PM PDT 24 36722482 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3620815589 May 07 12:40:04 PM PDT 24 May 07 12:40:09 PM PDT 24 108931741 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4259351165 May 07 12:39:57 PM PDT 24 May 07 12:40:02 PM PDT 24 386727773 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3849903162 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 69460443 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2781524183 May 07 12:40:07 PM PDT 24 May 07 12:40:10 PM PDT 24 354908622 ps
T967 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.781544706 May 07 12:40:19 PM PDT 24 May 07 12:40:24 PM PDT 24 273389848 ps
T968 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1950995252 May 07 12:40:15 PM PDT 24 May 07 12:40:26 PM PDT 24 857816833 ps
T209 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2407209362 May 07 12:40:25 PM PDT 24 May 07 12:40:28 PM PDT 24 37497951 ps
T969 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4252847561 May 07 12:39:51 PM PDT 24 May 07 12:39:54 PM PDT 24 250702206 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2322339308 May 07 12:40:04 PM PDT 24 May 07 12:40:08 PM PDT 24 406538418 ps
T971 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2269706253 May 07 12:40:14 PM PDT 24 May 07 12:40:18 PM PDT 24 30408475 ps
T149 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1794635020 May 07 12:40:02 PM PDT 24 May 07 12:40:07 PM PDT 24 1131139640 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2067633342 May 07 12:39:54 PM PDT 24 May 07 12:40:00 PM PDT 24 184755415 ps
T973 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.570282591 May 07 12:40:05 PM PDT 24 May 07 12:40:08 PM PDT 24 22021207 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.575674995 May 07 12:39:54 PM PDT 24 May 07 12:40:03 PM PDT 24 1163330897 ps
T975 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2955168346 May 07 12:40:07 PM PDT 24 May 07 12:40:09 PM PDT 24 31785978 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.99464564 May 07 12:40:13 PM PDT 24 May 07 12:40:19 PM PDT 24 149918437 ps
T977 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2953790127 May 07 12:40:02 PM PDT 24 May 07 12:40:05 PM PDT 24 73709348 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3907575408 May 07 12:40:14 PM PDT 24 May 07 12:40:19 PM PDT 24 143078460 ps
T137 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.183515741 May 07 12:40:09 PM PDT 24 May 07 12:40:12 PM PDT 24 82893703 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4052248988 May 07 12:39:53 PM PDT 24 May 07 12:39:58 PM PDT 24 1663202100 ps
T980 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2736790487 May 07 12:40:28 PM PDT 24 May 07 12:40:30 PM PDT 24 15167329 ps
T981 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1125492332 May 07 12:40:13 PM PDT 24 May 07 12:40:18 PM PDT 24 285560230 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2346612329 May 07 12:39:52 PM PDT 24 May 07 12:39:55 PM PDT 24 271674122 ps
T983 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2798074309 May 07 12:39:55 PM PDT 24 May 07 12:39:59 PM PDT 24 28931289 ps
T984 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2371434148 May 07 12:40:09 PM PDT 24 May 07 12:40:12 PM PDT 24 31264613 ps
T985 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2005309043 May 07 12:40:03 PM PDT 24 May 07 12:40:09 PM PDT 24 464666065 ps
T986 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3377199494 May 07 12:39:56 PM PDT 24 May 07 12:40:01 PM PDT 24 1142296965 ps
T987 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.96146373 May 07 12:40:24 PM PDT 24 May 07 12:40:29 PM PDT 24 230286832 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.899840455 May 07 12:40:04 PM PDT 24 May 07 12:40:11 PM PDT 24 349005964 ps
T210 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.582699147 May 07 12:40:07 PM PDT 24 May 07 12:40:09 PM PDT 24 21587792 ps
T989 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4113627349 May 07 12:39:55 PM PDT 24 May 07 12:39:59 PM PDT 24 84784954 ps
T211 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1688489110 May 07 12:40:24 PM PDT 24 May 07 12:40:27 PM PDT 24 26900378 ps
T990 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.433172506 May 07 12:40:08 PM PDT 24 May 07 12:40:13 PM PDT 24 54061943 ps
T991 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4146672170 May 07 12:40:00 PM PDT 24 May 07 12:40:12 PM PDT 24 2371283715 ps
T992 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3599169075 May 07 12:40:15 PM PDT 24 May 07 12:40:20 PM PDT 24 160745872 ps
T212 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.942442851 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 32020894 ps
T993 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1567707466 May 07 12:39:58 PM PDT 24 May 07 12:40:02 PM PDT 24 49889605 ps
T994 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3877254598 May 07 12:40:19 PM PDT 24 May 07 12:40:25 PM PDT 24 80859111 ps
T995 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.255459134 May 07 12:40:31 PM PDT 24 May 07 12:40:34 PM PDT 24 107414069 ps
T996 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4155183415 May 07 12:40:09 PM PDT 24 May 07 12:40:12 PM PDT 24 93599186 ps
T997 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3926811758 May 07 12:40:03 PM PDT 24 May 07 12:40:09 PM PDT 24 115819671 ps
T998 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1000513117 May 07 12:40:33 PM PDT 24 May 07 12:40:35 PM PDT 24 30446710 ps
T999 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1676855258 May 07 12:39:56 PM PDT 24 May 07 12:40:00 PM PDT 24 46546865 ps
T138 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.251848170 May 07 12:40:05 PM PDT 24 May 07 12:40:08 PM PDT 24 57270363 ps
T1000 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1824714749 May 07 12:40:10 PM PDT 24 May 07 12:40:13 PM PDT 24 61274736 ps
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