Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99925992

1

T1

71955

T2

23478

T3

21811

auto[1]

1394767

1

T3

1485

T4

22920

T11

1188

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99937042

1

T1

71955

T2

23478

T3

22306

auto[1]

1383717

1

T3

990

T4

20915

T11

1485

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7301334	1			T1	11664		T2	11630		T3	5718
auto[IdleSt]	21863279	1			T1	9956		T2	6167		T3	1898
auto[ClkMuxSt]	37093	1			T1	100		T3	48		T4	231
auto[CntIncrSt]	36756	1			T1	100		T3	48		T4	231
auto[CntProgSt]	1636323	1			T1	1053		T3	1234		T4	30922
auto[TransCheckSt]	28736	1			T1	100		T3	37		T4	144
auto[TokenHashSt]	38814954	1			T1	30584		T3	2684		T4	314188
auto[FlashRmaSt]	29678	1			T3	71		T4	227		T5	36
auto[TokenCheck0St]	13293	1			T3	30		T4	88		T5	18
auto[TokenCheck1St]	9871	1			T3	18		T4	79		T5	18
auto[TransProgSt]	456466	1			T3	908		T4	10445		T5	36
auto[PostTransSt]	13513382	1			T1	18398		T3	6197		T4	130870
auto[ScrapSt]	114282	1			T2	6		T4	926		T5	467
auto[EscalateSt]	6593687	1			T3	3283		T4	112933		T11	3597
auto[InvalidSt]	10869714	1			T2	5655		T3	1122		T4	169391

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1911	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10869714	1			T2	5655		T3	1122		T4	169391
EscalateSt	6593687	1			T3	3283		T4	112933		T11	3597
ScrapSt	114282	1			T2	6		T4	926		T5	467
PostTransSt	13513382	1			T1	18398		T3	6197		T4	130870
TransProgSt	456466	1			T3	908		T4	10445		T5	36
TokenCheck1St	9871	1			T3	18		T4	79		T5	18
TokenCheck0St	13293	1			T3	30		T4	88		T5	18
FlashRmaSt	29678	1			T3	71		T4	227		T5	36
TokenHashSt	38814954	1			T1	30584		T3	2684		T4	314188
TransCheckSt	28736	1			T1	100		T3	37		T4	144
CntProgSt	1636323	1			T1	1053		T3	1234		T4	30922
CntIncrSt	36756	1			T1	100		T3	48		T4	231
ClkMuxSt	37093	1			T1	100		T3	48		T4	231
IdleSt	21863279	1			T1	9956		T2	6167		T3	1898
ResetSt	7301334	1			T1	11664		T2	11630		T3	5718
arcs[ResetSt=>IdleSt]	55634	1			T1	101		T2	121		T3	63
arcs[IdleSt=>ScrapSt]	288	1			T2	2		T4	3		T5	1
arcs[IdleSt=>ClkMuxSt]	36814	1			T1	100		T3	48		T4	231
arcs[ClkMuxSt=>CntIncrSt]	36756	1			T1	100		T3	48		T4	231
arcs[CntIncrSt=>PostTransSt]	2070	1			T4	18		T15	11		T16	44
arcs[CntIncrSt=>CntProgSt]	34622	1			T1	100		T3	48		T4	213
arcs[CntProgSt=>PostTransSt]	4907	1			T3	11		T4	69		T11	12
arcs[CntProgSt=>TransCheckSt]	28736	1			T1	100		T3	37		T4	144
arcs[TransCheckSt=>PostTransSt]	3896	1			T4	13		T15	6		T16	40
arcs[TransCheckSt=>TokenHashSt]	24727	1			T1	100		T3	37		T4	131
arcs[TokenHashSt=>PostTransSt]	10656	1			T1	100		T3	7		T4	43
arcs[TokenHashSt=>FlashRmaSt]	13380	1			T3	30		T4	88		T5	18
arcs[FlashRmaSt=>TokenCheck0St]	13293	1			T3	30		T4	88		T5	18
arcs[TokenCheck0St=>PostTransSt]	3394	1			T3	12		T4	9		T11	19
arcs[TokenCheck0St=>TokenCheck1St]	9871	1			T3	18		T4	79		T5	18
arcs[TokenCheck1St=>PostTransSt]	687	1			T3	1		T4	2		T11	2
arcs[TransProgSt=>PostTransSt]	8388	1			T3	17		T4	77		T5	18
arcs[IdleSt=>EscalateSt]	209	1			T33	3		T58	3		T56	7
arcs[ClkMuxSt=>EscalateSt]	58	1			T55	2		T56	1		T57	1
arcs[CntIncrSt=>EscalateSt]	64	1			T33	2		T58	1		T55	1
arcs[CntProgSt=>EscalateSt]	979	1			T33	20		T58	31		T55	9
arcs[TransCheckSt=>EscalateSt]	113	1			T55	7		T56	6		T62	1
arcs[TokenHashSt=>EscalateSt]	691	1			T33	4		T58	7		T55	29
arcs[FlashRmaSt=>EscalateSt]	87	1			T33	2		T58	2		T55	1
arcs[TokenCheck0St=>EscalateSt]	28	1			T58	1		T55	2		T56	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T33	2		T58	3		T55	2
arcs[TransProgSt=>EscalateSt]	657	1			T33	18		T58	12		T55	6
arcs[PostTransSt=>EscalateSt]	5194	1			T3	11		T4	69		T11	12
arcs[InvalidSt=>EscalateSt]	14107	1			T3	14		T4	375		T11	15

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7301162	1			T1	11664		T2	11630		T3	5718
auto[0]	auto[IdleSt]	21863138	1			T1	9956		T2	6167		T3	1898
auto[0]	auto[ClkMuxSt]	37054	1			T1	100		T3	48		T4	231
auto[0]	auto[CntIncrSt]	36708	1			T1	100		T3	48		T4	231
auto[0]	auto[CntProgSt]	1635684	1			T1	1053		T3	1234		T4	30922
auto[0]	auto[TransCheckSt]	28665	1			T1	100		T3	37		T4	144
auto[0]	auto[TokenHashSt]	38814484	1			T1	30584		T3	2684		T4	314188
auto[0]	auto[FlashRmaSt]	29624	1			T3	71		T4	227		T5	36
auto[0]	auto[TokenCheck0St]	13274	1			T3	30		T4	88		T5	18
auto[0]	auto[TokenCheck1St]	9782	1			T3	18		T4	79		T5	18
auto[0]	auto[TransProgSt]	456028	1			T3	908		T4	10445		T5	36
auto[0]	auto[PostTransSt]	13510723	1			T1	18398		T3	6187		T4	130838
auto[0]	auto[ScrapSt]	114243	1			T2	6		T4	926		T5	467
auto[0]	auto[EscalateSt]	5210877	1			T3	1813		T4	90245		T11	2421
auto[0]	auto[InvalidSt]	10862635	1			T2	5655		T3	1117		T4	169191
auto[1]	auto[ResetSt]	172	1			T33	2		T58	3		T55	3
auto[1]	auto[IdleSt]	141	1			T33	3		T58	1		T56	4
auto[1]	auto[ClkMuxSt]	39	1			T55	1		T56	1		T57	1
auto[1]	auto[CntIncrSt]	48	1			T33	2		T58	1		T55	1
auto[1]	auto[CntProgSt]	639	1			T33	15		T58	22		T55	4
auto[1]	auto[TransCheckSt]	71	1			T55	3		T56	4		T62	1
auto[1]	auto[TokenHashSt]	470	1			T33	4		T58	7		T55	22
auto[1]	auto[FlashRmaSt]	54	1			T58	2		T62	5		T64	2
auto[1]	auto[TokenCheck0St]	19	1			T55	1		T56	1		T227	1
auto[1]	auto[TokenCheck1St]	89	1			T33	1		T58	3		T55	1
auto[1]	auto[TransProgSt]	438	1			T33	11		T58	9		T55	5
auto[1]	auto[PostTransSt]	2659	1			T3	10		T4	32		T11	4
auto[1]	auto[ScrapSt]	39	1			T56	1		T228	2		T62	1
auto[1]	auto[EscalateSt]	1382810	1			T3	1470		T4	22688		T11	1176
auto[1]	auto[InvalidSt]	7079	1			T3	5		T4	200		T11	8

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7301164	1			T1	11664		T2	11630		T3	5718
auto[0]	auto[IdleSt]	21863140	1			T1	9956		T2	6167		T3	1898
auto[0]	auto[ClkMuxSt]	37054	1			T1	100		T3	48		T4	231
auto[0]	auto[CntIncrSt]	36713	1			T1	100		T3	48		T4	231
auto[0]	auto[CntProgSt]	1635679	1			T1	1053		T3	1234		T4	30922
auto[0]	auto[TransCheckSt]	28654	1			T1	100		T3	37		T4	144
auto[0]	auto[TokenHashSt]	38814510	1			T1	30584		T3	2684		T4	314188
auto[0]	auto[FlashRmaSt]	29624	1			T3	71		T4	227		T5	36
auto[0]	auto[TokenCheck0St]	13274	1			T3	30		T4	88		T5	18
auto[0]	auto[TokenCheck1St]	9771	1			T3	18		T4	79		T5	18
auto[0]	auto[TransProgSt]	456030	1			T3	908		T4	10445		T5	36
auto[0]	auto[PostTransSt]	13510754	1			T1	18398		T3	6196		T4	130833
auto[0]	auto[ScrapSt]	114238	1			T2	6		T4	926		T5	467
auto[0]	auto[EscalateSt]	5221840	1			T3	2303		T4	92230		T11	2127
auto[0]	auto[InvalidSt]	10862686	1			T2	5655		T3	1113		T4	169216
auto[1]	auto[ResetSt]	170	1			T33	2		T58	2		T55	3
auto[1]	auto[IdleSt]	139	1			T33	2		T58	3		T56	5
auto[1]	auto[ClkMuxSt]	39	1			T55	1		T56	1		T57	1
auto[1]	auto[CntIncrSt]	43	1			T33	2		T55	1		T56	1
auto[1]	auto[CntProgSt]	644	1			T33	10		T58	20		T55	7
auto[1]	auto[TransCheckSt]	82	1			T55	6		T56	4		T62	1
auto[1]	auto[TokenHashSt]	444	1			T33	3		T58	3		T55	18
auto[1]	auto[FlashRmaSt]	54	1			T33	2		T55	1		T56	1
auto[1]	auto[TokenCheck0St]	19	1			T58	1		T55	1		T59	1
auto[1]	auto[TokenCheck1St]	100	1			T33	1		T55	1		T59	2
auto[1]	auto[TransProgSt]	436	1			T33	10		T58	9		T55	4
auto[1]	auto[PostTransSt]	2628	1			T3	1		T4	37		T11	8
auto[1]	auto[ScrapSt]	44	1			T33	1		T56	1		T59	1
auto[1]	auto[EscalateSt]	1371847	1			T3	980		T4	20703		T11	1470
auto[1]	auto[InvalidSt]	7028	1			T3	9		T4	175		T11	7