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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.90 97.89 95.59 93.31 97.67 98.55 99.00 96.29


Total test records in report: 1000
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T818 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3813740533 May 09 01:14:12 PM PDT 24 May 09 01:14:21 PM PDT 24 843697915 ps
T819 /workspace/coverage/default/44.lc_ctrl_state_failure.1904663967 May 09 01:15:31 PM PDT 24 May 09 01:15:53 PM PDT 24 169505292 ps
T45 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.794712826 May 09 01:13:59 PM PDT 24 May 09 01:14:02 PM PDT 24 44221641 ps
T820 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2831960201 May 09 01:13:03 PM PDT 24 May 09 01:13:14 PM PDT 24 277491210 ps
T821 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2205056593 May 09 01:13:33 PM PDT 24 May 09 01:13:35 PM PDT 24 44513059 ps
T822 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.373274927 May 09 01:15:35 PM PDT 24 May 09 01:15:38 PM PDT 24 13114913 ps
T823 /workspace/coverage/default/24.lc_ctrl_prog_failure.2799224329 May 09 01:14:34 PM PDT 24 May 09 01:14:39 PM PDT 24 344276960 ps
T824 /workspace/coverage/default/15.lc_ctrl_state_post_trans.3179952573 May 09 01:14:07 PM PDT 24 May 09 01:14:18 PM PDT 24 175235752 ps
T825 /workspace/coverage/default/3.lc_ctrl_errors.2723702992 May 09 01:13:11 PM PDT 24 May 09 01:13:26 PM PDT 24 3100441529 ps
T826 /workspace/coverage/default/24.lc_ctrl_state_failure.1232799085 May 09 01:14:31 PM PDT 24 May 09 01:14:57 PM PDT 24 1059400038 ps
T827 /workspace/coverage/default/1.lc_ctrl_jtag_errors.1599225668 May 09 01:13:11 PM PDT 24 May 09 01:14:05 PM PDT 24 3485854427 ps
T828 /workspace/coverage/default/6.lc_ctrl_prog_failure.1193851394 May 09 01:13:33 PM PDT 24 May 09 01:13:36 PM PDT 24 106884884 ps
T829 /workspace/coverage/default/45.lc_ctrl_sec_mubi.2295768126 May 09 01:15:36 PM PDT 24 May 09 01:15:50 PM PDT 24 528932799 ps
T830 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1089192527 May 09 01:14:10 PM PDT 24 May 09 01:15:19 PM PDT 24 14692022646 ps
T831 /workspace/coverage/default/45.lc_ctrl_security_escalation.69670483 May 09 01:15:36 PM PDT 24 May 09 01:15:50 PM PDT 24 326672061 ps
T832 /workspace/coverage/default/38.lc_ctrl_state_post_trans.3091253598 May 09 01:15:19 PM PDT 24 May 09 01:15:29 PM PDT 24 153770466 ps
T833 /workspace/coverage/default/10.lc_ctrl_state_post_trans.2168187538 May 09 01:13:57 PM PDT 24 May 09 01:14:03 PM PDT 24 86573385 ps
T834 /workspace/coverage/default/49.lc_ctrl_alert_test.870199384 May 09 01:15:43 PM PDT 24 May 09 01:15:46 PM PDT 24 33073216 ps
T835 /workspace/coverage/default/26.lc_ctrl_security_escalation.2592039062 May 09 01:14:36 PM PDT 24 May 09 01:14:51 PM PDT 24 384529056 ps
T836 /workspace/coverage/default/16.lc_ctrl_prog_failure.1509679213 May 09 01:14:15 PM PDT 24 May 09 01:14:21 PM PDT 24 256970599 ps
T837 /workspace/coverage/default/47.lc_ctrl_state_post_trans.3416618484 May 09 01:15:39 PM PDT 24 May 09 01:15:43 PM PDT 24 253010396 ps
T838 /workspace/coverage/default/14.lc_ctrl_alert_test.3188967375 May 09 01:14:15 PM PDT 24 May 09 01:14:19 PM PDT 24 22319736 ps
T839 /workspace/coverage/default/49.lc_ctrl_state_failure.2335452236 May 09 01:15:40 PM PDT 24 May 09 01:16:18 PM PDT 24 488001389 ps
T840 /workspace/coverage/default/15.lc_ctrl_alert_test.3672794026 May 09 01:14:15 PM PDT 24 May 09 01:14:18 PM PDT 24 20259921 ps
T841 /workspace/coverage/default/29.lc_ctrl_jtag_access.1325693910 May 09 01:14:42 PM PDT 24 May 09 01:14:48 PM PDT 24 105331390 ps
T842 /workspace/coverage/default/16.lc_ctrl_security_escalation.1254703124 May 09 01:14:09 PM PDT 24 May 09 01:14:20 PM PDT 24 250308160 ps
T843 /workspace/coverage/default/47.lc_ctrl_errors.796095469 May 09 01:15:41 PM PDT 24 May 09 01:15:56 PM PDT 24 288533118 ps
T844 /workspace/coverage/default/9.lc_ctrl_prog_failure.3800163820 May 09 01:13:47 PM PDT 24 May 09 01:13:51 PM PDT 24 30554115 ps
T845 /workspace/coverage/default/5.lc_ctrl_sec_mubi.1088173855 May 09 01:13:34 PM PDT 24 May 09 01:13:43 PM PDT 24 161118256 ps
T846 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3448347549 May 09 01:14:08 PM PDT 24 May 09 01:14:18 PM PDT 24 264640877 ps
T847 /workspace/coverage/default/13.lc_ctrl_prog_failure.2288088022 May 09 01:14:00 PM PDT 24 May 09 01:14:06 PM PDT 24 368918840 ps
T848 /workspace/coverage/default/39.lc_ctrl_smoke.647524291 May 09 01:15:22 PM PDT 24 May 09 01:15:27 PM PDT 24 60275532 ps
T849 /workspace/coverage/default/15.lc_ctrl_state_failure.276502104 May 09 01:14:08 PM PDT 24 May 09 01:14:29 PM PDT 24 379782292 ps
T850 /workspace/coverage/default/12.lc_ctrl_alert_test.2806025679 May 09 01:14:01 PM PDT 24 May 09 01:14:05 PM PDT 24 66625397 ps
T851 /workspace/coverage/default/5.lc_ctrl_stress_all.2769285689 May 09 01:13:31 PM PDT 24 May 09 01:15:14 PM PDT 24 18312411846 ps
T852 /workspace/coverage/default/17.lc_ctrl_sec_mubi.3998095525 May 09 01:14:20 PM PDT 24 May 09 01:14:33 PM PDT 24 285496256 ps
T853 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3934408220 May 09 01:13:45 PM PDT 24 May 09 01:14:04 PM PDT 24 547735069 ps
T854 /workspace/coverage/default/7.lc_ctrl_errors.1759039654 May 09 01:13:46 PM PDT 24 May 09 01:13:56 PM PDT 24 1146439199 ps
T855 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2311142878 May 09 01:14:01 PM PDT 24 May 09 01:14:19 PM PDT 24 2088861966 ps
T856 /workspace/coverage/default/11.lc_ctrl_state_failure.2345466765 May 09 01:13:57 PM PDT 24 May 09 01:14:17 PM PDT 24 943764444 ps
T857 /workspace/coverage/default/2.lc_ctrl_jtag_priority.4069130259 May 09 01:13:11 PM PDT 24 May 09 01:13:17 PM PDT 24 419463931 ps
T858 /workspace/coverage/default/4.lc_ctrl_state_failure.4140073951 May 09 01:13:20 PM PDT 24 May 09 01:13:45 PM PDT 24 886669279 ps
T859 /workspace/coverage/default/26.lc_ctrl_smoke.3934830825 May 09 01:14:36 PM PDT 24 May 09 01:14:40 PM PDT 24 93627556 ps
T860 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.557023728 May 09 01:15:36 PM PDT 24 May 09 01:15:58 PM PDT 24 1930997276 ps
T861 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.899510577 May 09 01:15:28 PM PDT 24 May 09 01:15:42 PM PDT 24 1222360633 ps
T862 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1808752018 May 09 01:12:58 PM PDT 24 May 09 01:13:12 PM PDT 24 432651643 ps
T863 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2300329552 May 09 01:13:13 PM PDT 24 May 09 01:13:37 PM PDT 24 9381031287 ps
T864 /workspace/coverage/default/5.lc_ctrl_errors.3810813227 May 09 01:13:31 PM PDT 24 May 09 01:13:47 PM PDT 24 2718405427 ps
T76 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4257641122 May 09 01:13:59 PM PDT 24 May 09 01:14:05 PM PDT 24 204653865 ps
T865 /workspace/coverage/default/15.lc_ctrl_smoke.523586246 May 09 01:14:13 PM PDT 24 May 09 01:14:17 PM PDT 24 90610644 ps
T866 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.616022473 May 09 01:13:16 PM PDT 24 May 09 01:13:31 PM PDT 24 473153780 ps
T867 /workspace/coverage/default/1.lc_ctrl_errors.3986642301 May 09 01:13:06 PM PDT 24 May 09 01:13:26 PM PDT 24 1750339715 ps
T868 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1652121614 May 09 01:13:20 PM PDT 24 May 09 01:13:59 PM PDT 24 4064176117 ps
T869 /workspace/coverage/default/40.lc_ctrl_alert_test.1144686094 May 09 01:15:23 PM PDT 24 May 09 01:15:26 PM PDT 24 22699386 ps
T101 /workspace/coverage/default/2.lc_ctrl_sec_cm.2952133197 May 09 01:13:13 PM PDT 24 May 09 01:13:39 PM PDT 24 539628706 ps
T870 /workspace/coverage/default/5.lc_ctrl_smoke.2584830035 May 09 01:13:24 PM PDT 24 May 09 01:13:27 PM PDT 24 36345712 ps
T871 /workspace/coverage/default/6.lc_ctrl_jtag_access.4147480997 May 09 01:13:31 PM PDT 24 May 09 01:13:51 PM PDT 24 737283693 ps
T872 /workspace/coverage/default/39.lc_ctrl_security_escalation.4167943252 May 09 01:15:20 PM PDT 24 May 09 01:15:34 PM PDT 24 906442004 ps
T873 /workspace/coverage/default/14.lc_ctrl_state_failure.2126103843 May 09 01:14:03 PM PDT 24 May 09 01:14:25 PM PDT 24 970619667 ps
T46 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1631423877 May 09 01:13:03 PM PDT 24 May 09 01:13:07 PM PDT 24 16491102 ps
T874 /workspace/coverage/default/13.lc_ctrl_alert_test.4005829196 May 09 01:14:03 PM PDT 24 May 09 01:14:07 PM PDT 24 18535611 ps
T875 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.436652597 May 09 01:15:21 PM PDT 24 May 09 01:15:33 PM PDT 24 481740010 ps
T876 /workspace/coverage/default/19.lc_ctrl_prog_failure.4177326626 May 09 01:14:20 PM PDT 24 May 09 01:14:27 PM PDT 24 69184807 ps
T877 /workspace/coverage/default/22.lc_ctrl_alert_test.3463392371 May 09 01:14:35 PM PDT 24 May 09 01:14:38 PM PDT 24 295551640 ps
T878 /workspace/coverage/default/31.lc_ctrl_smoke.2335502727 May 09 01:14:52 PM PDT 24 May 09 01:14:57 PM PDT 24 129755777 ps
T106 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3637727784 May 09 01:12:10 PM PDT 24 May 09 01:12:13 PM PDT 24 142409936 ps
T120 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3472345122 May 09 01:12:15 PM PDT 24 May 09 01:12:17 PM PDT 24 115128872 ps
T107 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3898747460 May 09 01:12:20 PM PDT 24 May 09 01:12:24 PM PDT 24 106440378 ps
T114 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.560674446 May 09 01:12:12 PM PDT 24 May 09 01:12:15 PM PDT 24 13931560 ps
T141 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2471215052 May 09 01:11:53 PM PDT 24 May 09 01:11:55 PM PDT 24 30792583 ps
T115 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2460491984 May 09 01:12:20 PM PDT 24 May 09 01:12:22 PM PDT 24 233828400 ps
T108 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1047244188 May 09 01:12:22 PM PDT 24 May 09 01:12:25 PM PDT 24 48002675 ps
T110 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3133506933 May 09 01:12:13 PM PDT 24 May 09 01:12:17 PM PDT 24 36873348 ps
T139 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2022422791 May 09 01:12:01 PM PDT 24 May 09 01:12:04 PM PDT 24 45583356 ps
T148 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.610143137 May 09 01:11:48 PM PDT 24 May 09 01:11:50 PM PDT 24 36361012 ps
T111 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.414869090 May 09 01:12:21 PM PDT 24 May 09 01:12:25 PM PDT 24 39001865 ps
T116 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.524230041 May 09 01:12:07 PM PDT 24 May 09 01:12:10 PM PDT 24 41592207 ps
T142 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.259203730 May 09 01:11:58 PM PDT 24 May 09 01:12:02 PM PDT 24 305868382 ps
T143 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.583086471 May 09 01:12:01 PM PDT 24 May 09 01:12:24 PM PDT 24 1890722767 ps
T140 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1064363522 May 09 01:11:48 PM PDT 24 May 09 01:11:56 PM PDT 24 951101831 ps
T149 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.58098412 May 09 01:12:21 PM PDT 24 May 09 01:12:23 PM PDT 24 124348077 ps
T213 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2566985410 May 09 01:12:00 PM PDT 24 May 09 01:12:04 PM PDT 24 19353503 ps
T214 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2236042240 May 09 01:12:07 PM PDT 24 May 09 01:12:09 PM PDT 24 71054418 ps
T215 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3258714316 May 09 01:12:14 PM PDT 24 May 09 01:12:17 PM PDT 24 22422126 ps
T136 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2838782792 May 09 01:12:01 PM PDT 24 May 09 01:12:04 PM PDT 24 65125883 ps
T216 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.640274065 May 09 01:11:59 PM PDT 24 May 09 01:12:02 PM PDT 24 67652077 ps
T217 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.707364519 May 09 01:12:15 PM PDT 24 May 09 01:12:18 PM PDT 24 379696543 ps
T161 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4108997386 May 09 01:12:00 PM PDT 24 May 09 01:12:05 PM PDT 24 157539728 ps
T879 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2831032450 May 09 01:12:10 PM PDT 24 May 09 01:12:13 PM PDT 24 76251424 ps
T137 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4013519716 May 09 01:11:48 PM PDT 24 May 09 01:11:51 PM PDT 24 152917471 ps
T880 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3457410934 May 09 01:11:50 PM PDT 24 May 09 01:11:53 PM PDT 24 562739916 ps
T218 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3145435172 May 09 01:12:11 PM PDT 24 May 09 01:12:15 PM PDT 24 25573660 ps
T112 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.728784909 May 09 01:12:00 PM PDT 24 May 09 01:12:04 PM PDT 24 293973202 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1839982607 May 09 01:11:48 PM PDT 24 May 09 01:11:51 PM PDT 24 56723871 ps
T219 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2337901341 May 09 01:12:10 PM PDT 24 May 09 01:12:13 PM PDT 24 77338556 ps
T118 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1666072392 May 09 01:12:00 PM PDT 24 May 09 01:12:06 PM PDT 24 210947215 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3003085238 May 09 01:12:04 PM PDT 24 May 09 01:12:09 PM PDT 24 195038628 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.984522777 May 09 01:12:05 PM PDT 24 May 09 01:12:16 PM PDT 24 1778623416 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1011692181 May 09 01:11:36 PM PDT 24 May 09 01:11:47 PM PDT 24 1492990428 ps
T885 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3046619827 May 09 01:12:03 PM PDT 24 May 09 01:12:16 PM PDT 24 4978285665 ps
T201 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2838096654 May 09 01:12:06 PM PDT 24 May 09 01:12:08 PM PDT 24 71918909 ps
T138 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.42467181 May 09 01:11:53 PM PDT 24 May 09 01:11:58 PM PDT 24 92692846 ps
T124 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.12824745 May 09 01:12:12 PM PDT 24 May 09 01:12:18 PM PDT 24 1819888777 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.253590807 May 09 01:12:03 PM PDT 24 May 09 01:12:05 PM PDT 24 15585606 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2903283836 May 09 01:11:49 PM PDT 24 May 09 01:11:52 PM PDT 24 78261343 ps
T888 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2892926800 May 09 01:11:53 PM PDT 24 May 09 01:11:57 PM PDT 24 563923568 ps
T119 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3127432410 May 09 01:12:00 PM PDT 24 May 09 01:12:04 PM PDT 24 121593392 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.728783402 May 09 01:11:54 PM PDT 24 May 09 01:11:56 PM PDT 24 15236308 ps
T890 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1266383145 May 09 01:12:00 PM PDT 24 May 09 01:12:03 PM PDT 24 44965366 ps
T891 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1040852858 May 09 01:11:47 PM PDT 24 May 09 01:11:49 PM PDT 24 15446686 ps
T150 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3000818762 May 09 01:12:05 PM PDT 24 May 09 01:12:08 PM PDT 24 27489041 ps
T202 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3202819577 May 09 01:12:22 PM PDT 24 May 09 01:12:25 PM PDT 24 15644204 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3616753513 May 09 01:12:12 PM PDT 24 May 09 01:12:15 PM PDT 24 14673568 ps
T113 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1216198194 May 09 01:12:11 PM PDT 24 May 09 01:12:17 PM PDT 24 80223992 ps
T893 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2031107760 May 09 01:12:02 PM PDT 24 May 09 01:12:12 PM PDT 24 947579098 ps
T151 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4117726105 May 09 01:12:14 PM PDT 24 May 09 01:12:18 PM PDT 24 101021489 ps
T894 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1031804068 May 09 01:12:22 PM PDT 24 May 09 01:12:28 PM PDT 24 151145042 ps
T152 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1322957528 May 09 01:12:14 PM PDT 24 May 09 01:12:17 PM PDT 24 13313804 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2028330064 May 09 01:11:48 PM PDT 24 May 09 01:11:53 PM PDT 24 409068633 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.592593131 May 09 01:11:49 PM PDT 24 May 09 01:11:52 PM PDT 24 19934364 ps
T897 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.599889674 May 09 01:12:06 PM PDT 24 May 09 01:12:08 PM PDT 24 33575106 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.134652388 May 09 01:11:51 PM PDT 24 May 09 01:11:54 PM PDT 24 127822654 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3056856364 May 09 01:12:05 PM PDT 24 May 09 01:12:10 PM PDT 24 436939517 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.658328277 May 09 01:11:46 PM PDT 24 May 09 01:11:54 PM PDT 24 1665850870 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3588692552 May 09 01:11:46 PM PDT 24 May 09 01:11:49 PM PDT 24 26774762 ps
T902 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2040237640 May 09 01:12:19 PM PDT 24 May 09 01:12:22 PM PDT 24 25796042 ps
T903 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2892025516 May 09 01:12:13 PM PDT 24 May 09 01:12:20 PM PDT 24 584061741 ps
T904 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1247667996 May 09 01:12:11 PM PDT 24 May 09 01:12:19 PM PDT 24 897030855 ps
T203 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2678302135 May 09 01:11:48 PM PDT 24 May 09 01:11:51 PM PDT 24 89941900 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1964449722 May 09 01:11:48 PM PDT 24 May 09 01:11:51 PM PDT 24 383323334 ps
T130 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1806725074 May 09 01:12:08 PM PDT 24 May 09 01:12:11 PM PDT 24 375127842 ps
T133 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.750500694 May 09 01:12:11 PM PDT 24 May 09 01:12:15 PM PDT 24 80152500 ps
T226 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3300603898 May 09 01:12:06 PM PDT 24 May 09 01:12:09 PM PDT 24 153950179 ps
T906 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1800521174 May 09 01:12:22 PM PDT 24 May 09 01:12:26 PM PDT 24 15938972 ps
T907 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3992014570 May 09 01:12:05 PM PDT 24 May 09 01:12:08 PM PDT 24 728522017 ps
T204 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3491846382 May 09 01:12:03 PM PDT 24 May 09 01:12:05 PM PDT 24 43737834 ps
T205 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3047846878 May 09 01:12:20 PM PDT 24 May 09 01:12:22 PM PDT 24 12080773 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2302718074 May 09 01:11:35 PM PDT 24 May 09 01:11:42 PM PDT 24 770141436 ps
T135 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4045697906 May 09 01:12:01 PM PDT 24 May 09 01:12:05 PM PDT 24 251362425 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1128294152 May 09 01:12:01 PM PDT 24 May 09 01:12:03 PM PDT 24 36452259 ps
T910 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.838235930 May 09 01:12:12 PM PDT 24 May 09 01:12:15 PM PDT 24 17528560 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2341934154 May 09 01:11:48 PM PDT 24 May 09 01:11:55 PM PDT 24 2111464728 ps
T912 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2711770831 May 09 01:12:07 PM PDT 24 May 09 01:12:14 PM PDT 24 204215957 ps
T913 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1671858689 May 09 01:12:15 PM PDT 24 May 09 01:12:17 PM PDT 24 56811872 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2696585110 May 09 01:12:02 PM PDT 24 May 09 01:12:05 PM PDT 24 63491038 ps
T915 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1037216153 May 09 01:12:09 PM PDT 24 May 09 01:12:12 PM PDT 24 39749424 ps
T916 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3498346927 May 09 01:12:11 PM PDT 24 May 09 01:12:14 PM PDT 24 13245411 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3828558364 May 09 01:11:49 PM PDT 24 May 09 01:11:52 PM PDT 24 141423092 ps
T918 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2368330316 May 09 01:12:15 PM PDT 24 May 09 01:12:18 PM PDT 24 17242308 ps
T919 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3993653540 May 09 01:12:01 PM PDT 24 May 09 01:12:11 PM PDT 24 330664792 ps
T920 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1170896781 May 09 01:12:13 PM PDT 24 May 09 01:12:17 PM PDT 24 208028618 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.158407056 May 09 01:11:59 PM PDT 24 May 09 01:12:14 PM PDT 24 568892319 ps
T922 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3679714575 May 09 01:12:12 PM PDT 24 May 09 01:12:15 PM PDT 24 52971062 ps
T923 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3173590253 May 09 01:12:02 PM PDT 24 May 09 01:12:05 PM PDT 24 84226540 ps
T924 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2161954282 May 09 01:12:00 PM PDT 24 May 09 01:12:05 PM PDT 24 110453533 ps
T925 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1926940442 May 09 01:11:59 PM PDT 24 May 09 01:12:06 PM PDT 24 192324305 ps
T926 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.65827510 May 09 01:12:13 PM PDT 24 May 09 01:12:16 PM PDT 24 177918002 ps
T927 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1638671539 May 09 01:12:21 PM PDT 24 May 09 01:12:24 PM PDT 24 114534885 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4105029447 May 09 01:11:49 PM PDT 24 May 09 01:11:52 PM PDT 24 21777489 ps
T929 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2997775639 May 09 01:12:01 PM PDT 24 May 09 01:12:04 PM PDT 24 76206860 ps
T132 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1803010044 May 09 01:12:09 PM PDT 24 May 09 01:12:13 PM PDT 24 550333598 ps
T930 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2791129199 May 09 01:12:05 PM PDT 24 May 09 01:12:07 PM PDT 24 79064803 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1932166801 May 09 01:11:48 PM PDT 24 May 09 01:11:52 PM PDT 24 365271363 ps
T932 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4131908815 May 09 01:12:15 PM PDT 24 May 09 01:12:18 PM PDT 24 85259882 ps
T933 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.363949399 May 09 01:12:21 PM PDT 24 May 09 01:12:24 PM PDT 24 43942117 ps
T934 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.752484336 May 09 01:12:10 PM PDT 24 May 09 01:12:13 PM PDT 24 101758841 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1223998678 May 09 01:12:05 PM PDT 24 May 09 01:12:07 PM PDT 24 25813637 ps
T936 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3799989210 May 09 01:11:49 PM PDT 24 May 09 01:11:52 PM PDT 24 31107732 ps
T937 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1380657947 May 09 01:12:09 PM PDT 24 May 09 01:12:12 PM PDT 24 221607023 ps
T938 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.986098333 May 09 01:12:13 PM PDT 24 May 09 01:12:16 PM PDT 24 65972569 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1670526814 May 09 01:11:47 PM PDT 24 May 09 01:11:59 PM PDT 24 5646362651 ps
T940 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4273832701 May 09 01:11:47 PM PDT 24 May 09 01:11:50 PM PDT 24 32487090 ps
T206 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3915137579 May 09 01:12:06 PM PDT 24 May 09 01:12:08 PM PDT 24 13424341 ps
T121 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3444902320 May 09 01:11:39 PM PDT 24 May 09 01:11:43 PM PDT 24 115365951 ps
T122 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3249141905 May 09 01:12:12 PM PDT 24 May 09 01:12:18 PM PDT 24 264120598 ps
T207 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3196270479 May 09 01:11:47 PM PDT 24 May 09 01:11:49 PM PDT 24 19707335 ps
T123 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2047348587 May 09 01:11:51 PM PDT 24 May 09 01:11:55 PM PDT 24 103675504 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2545191079 May 09 01:12:11 PM PDT 24 May 09 01:12:15 PM PDT 24 18840032 ps
T942 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2740375917 May 09 01:12:16 PM PDT 24 May 09 01:12:23 PM PDT 24 273433145 ps
T943 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1365029794 May 09 01:12:05 PM PDT 24 May 09 01:12:12 PM PDT 24 362891944 ps
T944 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.201038770 May 09 01:12:18 PM PDT 24 May 09 01:12:21 PM PDT 24 46408738 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2722916917 May 09 01:12:00 PM PDT 24 May 09 01:12:02 PM PDT 24 45290267 ps
T208 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2921599681 May 09 01:11:53 PM PDT 24 May 09 01:11:56 PM PDT 24 81158141 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3827998387 May 09 01:12:13 PM PDT 24 May 09 01:12:25 PM PDT 24 678868704 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.742101948 May 09 01:11:40 PM PDT 24 May 09 01:11:43 PM PDT 24 80455581 ps
T948 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1626130993 May 09 01:11:47 PM PDT 24 May 09 01:11:51 PM PDT 24 221835834 ps
T209 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.741203282 May 09 01:11:49 PM PDT 24 May 09 01:11:52 PM PDT 24 144142838 ps
T210 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.899735957 May 09 01:11:58 PM PDT 24 May 09 01:12:01 PM PDT 24 57053316 ps
T131 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.515632015 May 09 01:12:11 PM PDT 24 May 09 01:12:15 PM PDT 24 76592070 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.256628845 May 09 01:11:38 PM PDT 24 May 09 01:11:41 PM PDT 24 36519422 ps
T950 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4037628013 May 09 01:12:05 PM PDT 24 May 09 01:12:18 PM PDT 24 14769205114 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.774041028 May 09 01:11:59 PM PDT 24 May 09 01:12:02 PM PDT 24 129798101 ps
T952 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1253361134 May 09 01:12:10 PM PDT 24 May 09 01:12:15 PM PDT 24 237504451 ps
T953 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2757164500 May 09 01:12:12 PM PDT 24 May 09 01:12:16 PM PDT 24 152917593 ps
T211 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2264673914 May 09 01:11:59 PM PDT 24 May 09 01:12:03 PM PDT 24 42745205 ps
T954 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3571752804 May 09 01:12:12 PM PDT 24 May 09 01:12:21 PM PDT 24 1400813245 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2956123435 May 09 01:11:58 PM PDT 24 May 09 01:12:00 PM PDT 24 257956214 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2093459972 May 09 01:12:14 PM PDT 24 May 09 01:12:17 PM PDT 24 537244107 ps
T128 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.52660488 May 09 01:12:21 PM PDT 24 May 09 01:12:25 PM PDT 24 91322674 ps
T957 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.513629165 May 09 01:12:01 PM PDT 24 May 09 01:12:04 PM PDT 24 70721340 ps
T958 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1053068996 May 09 01:11:37 PM PDT 24 May 09 01:11:52 PM PDT 24 4813846913 ps
T959 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2092380779 May 09 01:12:03 PM PDT 24 May 09 01:12:07 PM PDT 24 247410465 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2439213426 May 09 01:12:07 PM PDT 24 May 09 01:12:09 PM PDT 24 49021333 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3902269500 May 09 01:11:34 PM PDT 24 May 09 01:11:38 PM PDT 24 140530278 ps
T962 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3382257358 May 09 01:11:54 PM PDT 24 May 09 01:11:59 PM PDT 24 360574628 ps
T963 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3835498005 May 09 01:11:53 PM PDT 24 May 09 01:11:57 PM PDT 24 752165710 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.616269852 May 09 01:11:49 PM PDT 24 May 09 01:11:56 PM PDT 24 185870244 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1508813188 May 09 01:12:04 PM PDT 24 May 09 01:12:07 PM PDT 24 91465795 ps
T966 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3420884769 May 09 01:12:10 PM PDT 24 May 09 01:12:13 PM PDT 24 105027254 ps
T134 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.497975502 May 09 01:12:13 PM PDT 24 May 09 01:12:17 PM PDT 24 45480473 ps
T967 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1760958176 May 09 01:11:36 PM PDT 24 May 09 01:11:39 PM PDT 24 53557747 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2830323382 May 09 01:12:09 PM PDT 24 May 09 01:12:13 PM PDT 24 163924464 ps
T129 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2582317144 May 09 01:12:20 PM PDT 24 May 09 01:12:23 PM PDT 24 135874802 ps
T969 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.63864667 May 09 01:12:00 PM PDT 24 May 09 01:12:04 PM PDT 24 45979825 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2783667395 May 09 01:12:05 PM PDT 24 May 09 01:12:07 PM PDT 24 17611004 ps
T212 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4163218902 May 09 01:12:09 PM PDT 24 May 09 01:12:11 PM PDT 24 32595306 ps
T125 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.636591885 May 09 01:12:16 PM PDT 24 May 09 01:12:21 PM PDT 24 801578413 ps
T971 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3579807993 May 09 01:12:10 PM PDT 24 May 09 01:12:13 PM PDT 24 155050787 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.919811884 May 09 01:12:16 PM PDT 24 May 09 01:12:19 PM PDT 24 220956105 ps
T973 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2269793796 May 09 01:12:00 PM PDT 24 May 09 01:12:03 PM PDT 24 36683231 ps
T974 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.321887264 May 09 01:12:10 PM PDT 24 May 09 01:12:13 PM PDT 24 19728854 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3284407624 May 09 01:11:47 PM PDT 24 May 09 01:11:50 PM PDT 24 15075045 ps
T976 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3564619350 May 09 01:12:11 PM PDT 24 May 09 01:12:14 PM PDT 24 46680919 ps
T977 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3246248758 May 09 01:12:13 PM PDT 24 May 09 01:12:17 PM PDT 24 33462393 ps
T978 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.676835961 May 09 01:11:59 PM PDT 24 May 09 01:12:02 PM PDT 24 156768446 ps
T979 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1977838739 May 09 01:12:13 PM PDT 24 May 09 01:12:18 PM PDT 24 1617201935 ps
T980 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.211163817 May 09 01:12:00 PM PDT 24 May 09 01:12:05 PM PDT 24 245799937 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1303804760 May 09 01:12:04 PM PDT 24 May 09 01:12:07 PM PDT 24 210436814 ps
T982 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.310587769 May 09 01:11:50 PM PDT 24 May 09 01:11:52 PM PDT 24 81384686 ps
T983 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3923090136 May 09 01:12:20 PM PDT 24 May 09 01:12:23 PM PDT 24 38560935 ps
T984 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.232863969 May 09 01:11:49 PM PDT 24 May 09 01:11:52 PM PDT 24 501477863 ps
T117 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.193993467 May 09 01:12:05 PM PDT 24 May 09 01:12:08 PM PDT 24 90011736 ps
T985 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1449848470 May 09 01:12:21 PM PDT 24 May 09 01:12:23 PM PDT 24 26453059 ps
T986 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2016464385 May 09 01:12:11 PM PDT 24 May 09 01:12:16 PM PDT 24 78745492 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3363545341 May 09 01:11:47 PM PDT 24 May 09 01:11:50 PM PDT 24 93191808 ps
T988 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2756746108 May 09 01:11:47 PM PDT 24 May 09 01:11:49 PM PDT 24 101180121 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1547809502 May 09 01:11:58 PM PDT 24 May 09 01:12:00 PM PDT 24 52129276 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3504682360 May 09 01:11:51 PM PDT 24 May 09 01:11:53 PM PDT 24 29367932 ps
T991 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2379358816 May 09 01:12:10 PM PDT 24 May 09 01:12:14 PM PDT 24 41870172 ps
T992 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1424512244 May 09 01:11:50 PM PDT 24 May 09 01:12:00 PM PDT 24 1014205459 ps
T127 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.947289319 May 09 01:11:47 PM PDT 24 May 09 01:11:51 PM PDT 24 429761919 ps
T993 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.389785890 May 09 01:12:05 PM PDT 24 May 09 01:12:08 PM PDT 24 134936307 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1691921097 May 09 01:11:47 PM PDT 24 May 09 01:11:49 PM PDT 24 41706006 ps
T995 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.229461764 May 09 01:12:06 PM PDT 24 May 09 01:12:08 PM PDT 24 88510435 ps
T996 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2169921937 May 09 01:11:51 PM PDT 24 May 09 01:11:54 PM PDT 24 21054754 ps
T997 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2219373930 May 09 01:11:39 PM PDT 24 May 09 01:11:43 PM PDT 24 1407882598 ps
T126 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.425826846 May 09 01:12:12 PM PDT 24 May 09 01:12:18 PM PDT 24 75258095 ps
T998 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1999580528 May 09 01:12:05 PM PDT 24 May 09 01:12:08 PM PDT 24 308119982 ps
T999 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4008508572 May 09 01:12:00 PM PDT 24 May 09 01:12:04 PM PDT 24 169662223 ps
T1000 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3809214986 May 09 01:12:00 PM PDT 24 May 09 01:12:06 PM PDT 24 186515820 ps

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2014033692
Short name T4
Test name
Test status
Simulation time 11077778846 ps
CPU time 481.18 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:21:46 PM PDT 24
Peak memory 422260 kb
Host smart-a1b2c9db-a9cd-486d-9441-9203575e76b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2014033692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2014033692
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4028426324
Short name T56
Test name
Test status
Simulation time 1663883378 ps
CPU time 10.06 seconds
Started May 09 01:15:23 PM PDT 24
Finished May 09 01:15:35 PM PDT 24
Peak memory 218372 kb
Host smart-7377898a-3b77-46b5-bfc2-5b4bf9615a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028426324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4028426324
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.523518195
Short name T3
Test name
Test status
Simulation time 931893536 ps
CPU time 9.18 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:44 PM PDT 24
Peak memory 218304 kb
Host smart-8b71ef62-9f5f-46a9-b728-645c21062ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523518195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.523518195
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3898747460
Short name T107
Test name
Test status
Simulation time 106440378 ps
CPU time 3.07 seconds
Started May 09 01:12:20 PM PDT 24
Finished May 09 01:12:24 PM PDT 24
Peak memory 217756 kb
Host smart-11b1ca6d-7a75-482a-ae09-814a280fff78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898747460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3898747460
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2226175564
Short name T39
Test name
Test status
Simulation time 13591776 ps
CPU time 0.84 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:14:17 PM PDT 24
Peak memory 208796 kb
Host smart-599f65df-3c56-4e14-9a4b-d49d8ee47a3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226175564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2226175564
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1742760586
Short name T2
Test name
Test status
Simulation time 460399947 ps
CPU time 39.56 seconds
Started May 09 01:13:01 PM PDT 24
Finished May 09 01:13:43 PM PDT 24
Peak memory 269744 kb
Host smart-a7aec402-41d5-48e0-8181-f07af82ea4f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742760586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1742760586
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1667868757
Short name T103
Test name
Test status
Simulation time 25496552871 ps
CPU time 424.78 seconds
Started May 09 01:15:02 PM PDT 24
Finished May 09 01:22:08 PM PDT 24
Peak memory 422244 kb
Host smart-cdaec57d-eacb-419f-a263-04f10935d2ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1667868757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1667868757
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2711882177
Short name T15
Test name
Test status
Simulation time 214361964810 ps
CPU time 716.89 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:25:31 PM PDT 24
Peak memory 333120 kb
Host smart-fe62edf5-517a-4cb3-928f-1a9e0f0182cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2711882177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2711882177
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3410639426
Short name T7
Test name
Test status
Simulation time 171340033 ps
CPU time 2.69 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:26 PM PDT 24
Peak memory 209788 kb
Host smart-331ffa4e-be83-4030-8d34-9f3ce162c3fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410639426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3410639426
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.414869090
Short name T111
Test name
Test status
Simulation time 39001865 ps
CPU time 1.84 seconds
Started May 09 01:12:21 PM PDT 24
Finished May 09 01:12:25 PM PDT 24
Peak memory 221856 kb
Host smart-1feea806-7e99-4e05-8598-25939b9af71d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414869090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.414869090
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.655241600
Short name T262
Test name
Test status
Simulation time 526377081 ps
CPU time 7.37 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:15:03 PM PDT 24
Peak memory 218296 kb
Host smart-ca245e4b-c6ed-43d9-bbfb-e69690fa0d76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655241600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.655241600
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4013519716
Short name T137
Test name
Test status
Simulation time 152917471 ps
CPU time 1.49 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:51 PM PDT 24
Peak memory 209388 kb
Host smart-c607cfd0-4437-43b0-ab9b-410421492d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013519716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4013519716
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1579357579
Short name T32
Test name
Test status
Simulation time 47514151 ps
CPU time 1.74 seconds
Started May 09 01:15:38 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 209800 kb
Host smart-4052ab11-407f-45a2-bccc-93bb974b7914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579357579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1579357579
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2678302135
Short name T203
Test name
Test status
Simulation time 89941900 ps
CPU time 1.36 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:51 PM PDT 24
Peak memory 209416 kb
Host smart-ec8d1e08-f481-4d5e-8f3d-be84b2ae2ac7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678302135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2678302135
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3249141905
Short name T122
Test name
Test status
Simulation time 264120598 ps
CPU time 3.25 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 221916 kb
Host smart-c7046c7a-95f8-439c-bfa9-6ab8e0b1188b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249141905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3249141905
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3492234788
Short name T16
Test name
Test status
Simulation time 67569937336 ps
CPU time 110.43 seconds
Started May 09 01:13:15 PM PDT 24
Finished May 09 01:15:08 PM PDT 24
Peak memory 230100 kb
Host smart-06c5ed8e-390c-41cf-941c-10090c41c323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492234788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3492234788
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.947289319
Short name T127
Test name
Test status
Simulation time 429761919 ps
CPU time 2.86 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:51 PM PDT 24
Peak memory 222228 kb
Host smart-6358f0b5-a286-4b14-a677-8048e5b4a69d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947289319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.947289319
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3255002818
Short name T343
Test name
Test status
Simulation time 310237403 ps
CPU time 10.27 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:09 PM PDT 24
Peak memory 218328 kb
Host smart-ddf26e3a-4a47-48e6-a936-3c8cc92b0fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255002818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3255002818
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3472345122
Short name T120
Test name
Test status
Simulation time 115128872 ps
CPU time 1.13 seconds
Started May 09 01:12:15 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 209452 kb
Host smart-98ee6506-e7e0-4730-b653-c2953df8a1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472345122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3472345122
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3444902320
Short name T121
Test name
Test status
Simulation time 115365951 ps
CPU time 2.8 seconds
Started May 09 01:11:39 PM PDT 24
Finished May 09 01:11:43 PM PDT 24
Peak memory 221856 kb
Host smart-775cc509-8572-4332-a2f1-58bd9b74a43f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444902320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3444902320
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2140026518
Short name T11
Test name
Test status
Simulation time 644937333 ps
CPU time 14.41 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:48 PM PDT 24
Peak memory 226336 kb
Host smart-0970ad97-3865-4889-90e8-6a0fcf2fb1f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140026518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2140026518
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3139076981
Short name T105
Test name
Test status
Simulation time 140701888096 ps
CPU time 1040.74 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:32:54 PM PDT 24
Peak memory 333108 kb
Host smart-a209e9fc-224c-4148-affb-9868785837cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3139076981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3139076981
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1042630760
Short name T170
Test name
Test status
Simulation time 3157635546 ps
CPU time 109.13 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 251172 kb
Host smart-679266b4-3b40-4248-be61-c8dbdc3da47c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042630760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1042630760
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.4063683581
Short name T186
Test name
Test status
Simulation time 24452747809 ps
CPU time 78.92 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 234896 kb
Host smart-4766893f-5b92-4d6a-812f-2dc4545aedea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063683581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.4063683581
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.154945672
Short name T91
Test name
Test status
Simulation time 85565601504 ps
CPU time 715.81 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:26:51 PM PDT 24
Peak memory 389548 kb
Host smart-79194c6a-128b-4349-bd8f-31f9b0d39268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=154945672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.154945672
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1216198194
Short name T113
Test name
Test status
Simulation time 80223992 ps
CPU time 3.45 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 222232 kb
Host smart-edcc4a05-41c8-4804-b339-9460cb4168c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216198194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1216198194
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.363949399
Short name T933
Test name
Test status
Simulation time 43942117 ps
CPU time 1.79 seconds
Started May 09 01:12:21 PM PDT 24
Finished May 09 01:12:24 PM PDT 24
Peak memory 217756 kb
Host smart-f093180b-2b13-4b19-8618-229ea4366845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363949399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.363949399
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.728784909
Short name T112
Test name
Test status
Simulation time 293973202 ps
CPU time 3.36 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 217792 kb
Host smart-f335e786-f4b8-4f65-80b9-5b229e346cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728784909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.728784909
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3491518330
Short name T224
Test name
Test status
Simulation time 13812899 ps
CPU time 0.85 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:01 PM PDT 24
Peak memory 209628 kb
Host smart-11ef8590-2f39-46d7-8cd1-21b7971f884c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491518330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3491518330
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.569691346
Short name T221
Test name
Test status
Simulation time 11087413 ps
CPU time 0.96 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:13:16 PM PDT 24
Peak memory 209744 kb
Host smart-82e8b4a9-510e-4797-966d-48c837ee5a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569691346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.569691346
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2021991437
Short name T223
Test name
Test status
Simulation time 17924946 ps
CPU time 0.94 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:35 PM PDT 24
Peak memory 209768 kb
Host smart-65deec8c-a4fb-40d2-b2ba-9a2c69657226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021991437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2021991437
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1928899967
Short name T222
Test name
Test status
Simulation time 13417696 ps
CPU time 0.87 seconds
Started May 09 01:13:55 PM PDT 24
Finished May 09 01:13:57 PM PDT 24
Peak memory 209640 kb
Host smart-ca0094c4-9f84-49df-8f7d-e4909958eee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928899967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1928899967
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1341187407
Short name T23
Test name
Test status
Simulation time 420237422 ps
CPU time 37.78 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:16:07 PM PDT 24
Peak memory 251212 kb
Host smart-3cea3286-1435-4bd8-9cc4-8912fab4c51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341187407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1341187407
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.636591885
Short name T125
Test name
Test status
Simulation time 801578413 ps
CPU time 3.49 seconds
Started May 09 01:12:16 PM PDT 24
Finished May 09 01:12:21 PM PDT 24
Peak memory 217636 kb
Host smart-1d2faaab-3dbc-472f-a676-077030b738bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636591885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.636591885
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4045697906
Short name T135
Test name
Test status
Simulation time 251362425 ps
CPU time 1.92 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 222116 kb
Host smart-c504c8f3-4957-4740-80a9-78afb2550736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045697906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4045697906
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.193993467
Short name T117
Test name
Test status
Simulation time 90011736 ps
CPU time 1.87 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 221848 kb
Host smart-dd5e2fab-81e7-4444-8f22-2c507ac3beef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193993467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.193993467
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1803010044
Short name T132
Test name
Test status
Simulation time 550333598 ps
CPU time 2.55 seconds
Started May 09 01:12:09 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 222044 kb
Host smart-f1a95b20-80f5-4bbd-b828-ff9696769826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803010044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1803010044
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.656103327
Short name T53
Test name
Test status
Simulation time 5331946537 ps
CPU time 94.1 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:15:21 PM PDT 24
Peak memory 283312 kb
Host smart-440b3bfa-1a50-4492-b190-6b54bbe2670e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656103327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.656103327
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.215128492
Short name T13
Test name
Test status
Simulation time 111232200 ps
CPU time 2.11 seconds
Started May 09 01:13:56 PM PDT 24
Finished May 09 01:14:00 PM PDT 24
Peak memory 218288 kb
Host smart-5872a5f2-2fc3-4cc7-8282-56652256d4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215128492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.215128492
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2756746108
Short name T988
Test name
Test status
Simulation time 101180121 ps
CPU time 1.29 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:49 PM PDT 24
Peak memory 209156 kb
Host smart-1482bb5a-6179-45e5-a83a-ba3e82d15f8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756746108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2756746108
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2921599681
Short name T208
Test name
Test status
Simulation time 81158141 ps
CPU time 0.95 seconds
Started May 09 01:11:53 PM PDT 24
Finished May 09 01:11:56 PM PDT 24
Peak memory 209768 kb
Host smart-bc6ba1f2-4178-4a19-84ab-e2b0ebd29f8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921599681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2921599681
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4105029447
Short name T928
Test name
Test status
Simulation time 21777489 ps
CPU time 1.4 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 218584 kb
Host smart-fd850609-8ed7-4a29-90c7-9cf80cb585a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105029447 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4105029447
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3504682360
Short name T990
Test name
Test status
Simulation time 29367932 ps
CPU time 0.86 seconds
Started May 09 01:11:51 PM PDT 24
Finished May 09 01:11:53 PM PDT 24
Peak memory 208956 kb
Host smart-39543d72-63c6-4cab-9575-674f79b1232b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504682360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3504682360
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1760958176
Short name T967
Test name
Test status
Simulation time 53557747 ps
CPU time 1.15 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:11:39 PM PDT 24
Peak memory 209336 kb
Host smart-4092b292-aa49-4f37-a56b-e2ce57df4019
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760958176 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1760958176
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1053068996
Short name T958
Test name
Test status
Simulation time 4813846913 ps
CPU time 13.58 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 209328 kb
Host smart-1d0d82b7-8899-4b49-8eaa-b91bdea11d4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053068996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1053068996
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1011692181
Short name T884
Test name
Test status
Simulation time 1492990428 ps
CPU time 9.73 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:11:47 PM PDT 24
Peak memory 209104 kb
Host smart-92b17d13-d990-437f-b6ef-a481b4f23e7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011692181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1011692181
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2302718074
Short name T908
Test name
Test status
Simulation time 770141436 ps
CPU time 5.07 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:42 PM PDT 24
Peak memory 210944 kb
Host smart-c2a18ee8-1307-4ae2-ae6e-17596da85aff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302718074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2302718074
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2219373930
Short name T997
Test name
Test status
Simulation time 1407882598 ps
CPU time 2.3 seconds
Started May 09 01:11:39 PM PDT 24
Finished May 09 01:11:43 PM PDT 24
Peak memory 218756 kb
Host smart-c7ee3d1f-806c-4ca0-b5c0-6326ef0ac22c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221937
3930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2219373930
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.256628845
Short name T949
Test name
Test status
Simulation time 36519422 ps
CPU time 1.11 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 209420 kb
Host smart-e867c66b-8dba-4388-8f36-e107dbae6ef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256628845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.256628845
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.742101948
Short name T947
Test name
Test status
Simulation time 80455581 ps
CPU time 1.48 seconds
Started May 09 01:11:40 PM PDT 24
Finished May 09 01:11:43 PM PDT 24
Peak memory 211604 kb
Host smart-22e023f6-d4bc-46dd-884e-c4109417697a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742101948 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.742101948
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3799989210
Short name T936
Test name
Test status
Simulation time 31107732 ps
CPU time 1.21 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 209128 kb
Host smart-06966bbb-21ce-4721-9261-accffc6cc011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799989210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3799989210
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3902269500
Short name T961
Test name
Test status
Simulation time 140530278 ps
CPU time 2.27 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:38 PM PDT 24
Peak memory 217692 kb
Host smart-868e7ed3-0996-47b7-a810-a9ae52b819e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902269500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3902269500
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1839982607
Short name T881
Test name
Test status
Simulation time 56723871 ps
CPU time 1.7 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:51 PM PDT 24
Peak memory 209448 kb
Host smart-a50921a5-ccbe-4e24-92bc-48547fe64298
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839982607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1839982607
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3588692552
Short name T901
Test name
Test status
Simulation time 26774762 ps
CPU time 2.01 seconds
Started May 09 01:11:46 PM PDT 24
Finished May 09 01:11:49 PM PDT 24
Peak memory 209436 kb
Host smart-681eeaa4-90aa-485a-8cf9-66ee31e36301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588692552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3588692552
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3284407624
Short name T975
Test name
Test status
Simulation time 15075045 ps
CPU time 1.15 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:50 PM PDT 24
Peak memory 210120 kb
Host smart-fc2e943f-77a0-4142-a50a-a6565926b5d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284407624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3284407624
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.592593131
Short name T896
Test name
Test status
Simulation time 19934364 ps
CPU time 1.45 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 218612 kb
Host smart-1e196e0e-b7b7-4476-a161-d3c686632885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592593131 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.592593131
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.310587769
Short name T982
Test name
Test status
Simulation time 81384686 ps
CPU time 0.89 seconds
Started May 09 01:11:50 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 209212 kb
Host smart-3856d2b4-b27d-4334-99c0-810f3eb3978f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310587769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.310587769
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2471215052
Short name T141
Test name
Test status
Simulation time 30792583 ps
CPU time 1.01 seconds
Started May 09 01:11:53 PM PDT 24
Finished May 09 01:11:55 PM PDT 24
Peak memory 207984 kb
Host smart-1acdd2fd-8af9-4eba-84bc-4cd5722c1a8e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471215052 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2471215052
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2341934154
Short name T911
Test name
Test status
Simulation time 2111464728 ps
CPU time 5.6 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:55 PM PDT 24
Peak memory 208556 kb
Host smart-ed5dedbf-b533-45a5-b72e-f78a89402fc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341934154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2341934154
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1670526814
Short name T939
Test name
Test status
Simulation time 5646362651 ps
CPU time 10.13 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:59 PM PDT 24
Peak memory 209344 kb
Host smart-bf26af9e-201b-4ccf-a62a-f7518e9e762c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670526814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1670526814
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2892926800
Short name T888
Test name
Test status
Simulation time 563923568 ps
CPU time 2 seconds
Started May 09 01:11:53 PM PDT 24
Finished May 09 01:11:57 PM PDT 24
Peak memory 211084 kb
Host smart-253498d5-847b-4f67-9edb-3777694a7dd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892926800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2892926800
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3835498005
Short name T963
Test name
Test status
Simulation time 752165710 ps
CPU time 2.32 seconds
Started May 09 01:11:53 PM PDT 24
Finished May 09 01:11:57 PM PDT 24
Peak memory 217860 kb
Host smart-408be44d-ceca-43d9-9dda-c5c83e9c7586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383549
8005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3835498005
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.134652388
Short name T898
Test name
Test status
Simulation time 127822654 ps
CPU time 1.02 seconds
Started May 09 01:11:51 PM PDT 24
Finished May 09 01:11:54 PM PDT 24
Peak memory 209516 kb
Host smart-e71c09f2-a1aa-4227-9b3c-fb18ce951936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134652388 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.134652388
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2169921937
Short name T996
Test name
Test status
Simulation time 21054754 ps
CPU time 1.34 seconds
Started May 09 01:11:51 PM PDT 24
Finished May 09 01:11:54 PM PDT 24
Peak memory 211532 kb
Host smart-40263fad-214d-4309-b889-ba1f6e74a7d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169921937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2169921937
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2028330064
Short name T895
Test name
Test status
Simulation time 409068633 ps
CPU time 3.66 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:53 PM PDT 24
Peak memory 217760 kb
Host smart-c5f1c5b0-e675-4288-b01e-1e766251ba9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028330064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2028330064
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4131908815
Short name T932
Test name
Test status
Simulation time 85259882 ps
CPU time 1.25 seconds
Started May 09 01:12:15 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 217744 kb
Host smart-81a44f4a-25ca-4b21-8a60-c8645afdce13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131908815 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4131908815
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1322957528
Short name T152
Test name
Test status
Simulation time 13313804 ps
CPU time 0.93 seconds
Started May 09 01:12:14 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 209472 kb
Host smart-80682b38-f18b-45e4-949b-c02fa40df254
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322957528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1322957528
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2337901341
Short name T219
Test name
Test status
Simulation time 77338556 ps
CPU time 1.91 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 211440 kb
Host smart-6d561502-3b4e-4eb6-a0ab-2ea510b14427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337901341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2337901341
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2740375917
Short name T942
Test name
Test status
Simulation time 273433145 ps
CPU time 4.7 seconds
Started May 09 01:12:16 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 217704 kb
Host smart-8d1265f7-5ab7-4a7f-b12f-4347dda32e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740375917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2740375917
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.515632015
Short name T131
Test name
Test status
Simulation time 76592070 ps
CPU time 3.1 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 221952 kb
Host smart-2ca6a1c4-8f7c-432c-a180-652ff18fa6be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515632015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.515632015
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3420884769
Short name T966
Test name
Test status
Simulation time 105027254 ps
CPU time 1.82 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 221864 kb
Host smart-e2855074-01c7-44e7-8ed2-32a361210ef7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420884769 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3420884769
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4163218902
Short name T212
Test name
Test status
Simulation time 32595306 ps
CPU time 1.14 seconds
Started May 09 01:12:09 PM PDT 24
Finished May 09 01:12:11 PM PDT 24
Peak memory 209472 kb
Host smart-355e0eb5-3f08-4f1d-beed-b84caf539282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163218902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.4163218902
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2757164500
Short name T953
Test name
Test status
Simulation time 152917593 ps
CPU time 1.82 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:16 PM PDT 24
Peak memory 209500 kb
Host smart-d7009a5a-1549-4048-8f1c-41aebcb8af5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757164500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2757164500
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2892025516
Short name T903
Test name
Test status
Simulation time 584061741 ps
CPU time 5.25 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:20 PM PDT 24
Peak memory 217756 kb
Host smart-86883763-a2d5-4bba-b177-3b11060c420e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892025516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2892025516
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1806725074
Short name T130
Test name
Test status
Simulation time 375127842 ps
CPU time 1.95 seconds
Started May 09 01:12:08 PM PDT 24
Finished May 09 01:12:11 PM PDT 24
Peak memory 217704 kb
Host smart-6930f875-9c32-434c-b2f1-6bc41e6e0504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806725074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1806725074
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1170896781
Short name T920
Test name
Test status
Simulation time 208028618 ps
CPU time 1.67 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 223236 kb
Host smart-dc451a70-b864-4fcf-8d5a-b277b59b7f4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170896781 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1170896781
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2831032450
Short name T879
Test name
Test status
Simulation time 76251424 ps
CPU time 1.14 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 209456 kb
Host smart-0f5eea74-4293-4546-b176-d5b43f6f09a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831032450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2831032450
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3246248758
Short name T977
Test name
Test status
Simulation time 33462393 ps
CPU time 1.38 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 217680 kb
Host smart-1e998643-fc13-4505-b296-f109d2c47b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246248758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3246248758
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1253361134
Short name T952
Test name
Test status
Simulation time 237504451 ps
CPU time 3.66 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 217756 kb
Host smart-828ee00c-e803-444a-b4f6-b45e6ad16fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253361134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1253361134
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3133506933
Short name T110
Test name
Test status
Simulation time 36873348 ps
CPU time 1.73 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 218016 kb
Host smart-6f4ec1e5-761e-4916-a0eb-6efaa6a72b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133506933 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3133506933
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3498346927
Short name T916
Test name
Test status
Simulation time 13245411 ps
CPU time 1.06 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:14 PM PDT 24
Peak memory 209280 kb
Host smart-6e9c3c2d-14de-44e2-96e4-59eb743ea182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498346927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3498346927
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.707364519
Short name T217
Test name
Test status
Simulation time 379696543 ps
CPU time 1.36 seconds
Started May 09 01:12:15 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 211304 kb
Host smart-70f38912-cbdf-4397-ba60-a71d4f76b415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707364519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.707364519
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.12824745
Short name T124
Test name
Test status
Simulation time 1819888777 ps
CPU time 4.14 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 217716 kb
Host smart-cf2091ba-abd6-4718-928b-a4056ae9c88a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12824745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.12824745
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.497975502
Short name T134
Test name
Test status
Simulation time 45480473 ps
CPU time 2.4 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 222212 kb
Host smart-f7d53c67-bb78-4ea2-a3e5-c6c9ded28d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497975502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.497975502
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3679714575
Short name T922
Test name
Test status
Simulation time 52971062 ps
CPU time 1.28 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 217824 kb
Host smart-eb8b6213-bdd9-4d6f-b006-dfd3b54f67a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679714575 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3679714575
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2368330316
Short name T918
Test name
Test status
Simulation time 17242308 ps
CPU time 0.87 seconds
Started May 09 01:12:15 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 209436 kb
Host smart-ef09da2a-36dc-4f7e-b72e-fbd5078e4b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368330316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2368330316
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.838235930
Short name T910
Test name
Test status
Simulation time 17528560 ps
CPU time 1.2 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 209468 kb
Host smart-f9190f85-0d8f-42a9-a483-2f9e560362d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838235930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.838235930
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2379358816
Short name T991
Test name
Test status
Simulation time 41870172 ps
CPU time 1.77 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:14 PM PDT 24
Peak memory 217900 kb
Host smart-eb272932-0591-4fb5-97f1-1efc3da8c317
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379358816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2379358816
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.425826846
Short name T126
Test name
Test status
Simulation time 75258095 ps
CPU time 3.53 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 222068 kb
Host smart-0bb8526c-bf79-473a-8b5b-443cb8b9746d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425826846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.425826846
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.65827510
Short name T926
Test name
Test status
Simulation time 177918002 ps
CPU time 1.06 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:16 PM PDT 24
Peak memory 219132 kb
Host smart-7a5624a1-5649-48c2-9964-0ffa6904a50f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65827510 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.65827510
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.321887264
Short name T974
Test name
Test status
Simulation time 19728854 ps
CPU time 1.23 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 209428 kb
Host smart-f44a0419-790f-4c55-b5cf-fafd507fc571
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321887264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.321887264
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1037216153
Short name T915
Test name
Test status
Simulation time 39749424 ps
CPU time 1.57 seconds
Started May 09 01:12:09 PM PDT 24
Finished May 09 01:12:12 PM PDT 24
Peak memory 217996 kb
Host smart-1601199f-8e0e-4203-9e62-b978d807970a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037216153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1037216153
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.750500694
Short name T133
Test name
Test status
Simulation time 80152500 ps
CPU time 1.83 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 221688 kb
Host smart-67d5d410-04e7-469e-a139-65c68f8c2f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750500694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.750500694
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1047244188
Short name T108
Test name
Test status
Simulation time 48002675 ps
CPU time 1.42 seconds
Started May 09 01:12:22 PM PDT 24
Finished May 09 01:12:25 PM PDT 24
Peak memory 219848 kb
Host smart-91d93b52-cac9-4723-9341-b014d880e019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047244188 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1047244188
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1671858689
Short name T913
Test name
Test status
Simulation time 56811872 ps
CPU time 0.84 seconds
Started May 09 01:12:15 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 208688 kb
Host smart-c79f1758-a68b-47c0-b963-d0da62eed8af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671858689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1671858689
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3258714316
Short name T215
Test name
Test status
Simulation time 22422126 ps
CPU time 1.2 seconds
Started May 09 01:12:14 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 209456 kb
Host smart-ed48c21a-f39a-4dc5-b5e0-af8d02aa77d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258714316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3258714316
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2016464385
Short name T986
Test name
Test status
Simulation time 78745492 ps
CPU time 3.38 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:16 PM PDT 24
Peak memory 217696 kb
Host smart-88d388c7-a242-443c-be44-352ff4092a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016464385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2016464385
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.58098412
Short name T149
Test name
Test status
Simulation time 124348077 ps
CPU time 1.17 seconds
Started May 09 01:12:21 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 217828 kb
Host smart-4d05ca60-f4aa-4c0f-ac86-cc0aaee49742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58098412 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.58098412
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1800521174
Short name T906
Test name
Test status
Simulation time 15938972 ps
CPU time 0.87 seconds
Started May 09 01:12:22 PM PDT 24
Finished May 09 01:12:26 PM PDT 24
Peak memory 209408 kb
Host smart-b77c808e-e465-4b0e-9097-3a91e857a1f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800521174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1800521174
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2460491984
Short name T115
Test name
Test status
Simulation time 233828400 ps
CPU time 1.88 seconds
Started May 09 01:12:20 PM PDT 24
Finished May 09 01:12:22 PM PDT 24
Peak memory 209492 kb
Host smart-11e9bedd-de63-4437-a694-7138c6f8ec7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460491984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2460491984
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.52660488
Short name T128
Test name
Test status
Simulation time 91322674 ps
CPU time 2.7 seconds
Started May 09 01:12:21 PM PDT 24
Finished May 09 01:12:25 PM PDT 24
Peak memory 217632 kb
Host smart-c3fc3290-7a60-4883-b68f-35b586d875a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52660488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_e
rr.52660488
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1449848470
Short name T985
Test name
Test status
Simulation time 26453059 ps
CPU time 1.29 seconds
Started May 09 01:12:21 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 222092 kb
Host smart-adb009fb-5321-4192-a645-dd2e799302c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449848470 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1449848470
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3047846878
Short name T205
Test name
Test status
Simulation time 12080773 ps
CPU time 0.89 seconds
Started May 09 01:12:20 PM PDT 24
Finished May 09 01:12:22 PM PDT 24
Peak memory 209472 kb
Host smart-6bd7fbd7-c2b1-4ceb-b753-01fb42efbca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047846878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3047846878
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1638671539
Short name T927
Test name
Test status
Simulation time 114534885 ps
CPU time 1.93 seconds
Started May 09 01:12:21 PM PDT 24
Finished May 09 01:12:24 PM PDT 24
Peak memory 209448 kb
Host smart-e023fa12-f2e3-48ea-a66b-da9938cab7fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638671539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1638671539
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2040237640
Short name T902
Test name
Test status
Simulation time 25796042 ps
CPU time 1.54 seconds
Started May 09 01:12:19 PM PDT 24
Finished May 09 01:12:22 PM PDT 24
Peak memory 217760 kb
Host smart-af1d01cb-44cb-426f-a2c9-9318a0dd61f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040237640 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2040237640
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3202819577
Short name T202
Test name
Test status
Simulation time 15644204 ps
CPU time 0.85 seconds
Started May 09 01:12:22 PM PDT 24
Finished May 09 01:12:25 PM PDT 24
Peak memory 209376 kb
Host smart-f3c076e3-e52b-4ff6-ae2e-d7f6156689c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202819577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3202819577
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3923090136
Short name T983
Test name
Test status
Simulation time 38560935 ps
CPU time 1.35 seconds
Started May 09 01:12:20 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 209464 kb
Host smart-6c49dbb6-8733-47b5-b933-e6741bdba37a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923090136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3923090136
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1031804068
Short name T894
Test name
Test status
Simulation time 151145042 ps
CPU time 4.43 seconds
Started May 09 01:12:22 PM PDT 24
Finished May 09 01:12:28 PM PDT 24
Peak memory 217772 kb
Host smart-0e974136-8d7a-4e02-826a-e9a6e5b13288
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031804068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1031804068
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2582317144
Short name T129
Test name
Test status
Simulation time 135874802 ps
CPU time 1.84 seconds
Started May 09 01:12:20 PM PDT 24
Finished May 09 01:12:23 PM PDT 24
Peak memory 221648 kb
Host smart-8b740ea8-244d-41f4-be72-9a8946c35a69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582317144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2582317144
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.741203282
Short name T209
Test name
Test status
Simulation time 144142838 ps
CPU time 1.57 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 209400 kb
Host smart-df0ae4ae-0e7c-4e69-87db-e1a7a4ecd60c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741203282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.741203282
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1932166801
Short name T931
Test name
Test status
Simulation time 365271363 ps
CPU time 2.01 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 209504 kb
Host smart-6a3eb19b-5ab5-4184-8d48-500740629dc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932166801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1932166801
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3196270479
Short name T207
Test name
Test status
Simulation time 19707335 ps
CPU time 1.36 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:49 PM PDT 24
Peak memory 218124 kb
Host smart-0da4b61d-0117-4d1d-a032-d2108f0f86d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196270479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3196270479
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.610143137
Short name T148
Test name
Test status
Simulation time 36361012 ps
CPU time 1.13 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:50 PM PDT 24
Peak memory 218724 kb
Host smart-8a00bb54-981a-4293-a7e1-a1491e292b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610143137 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.610143137
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.728783402
Short name T889
Test name
Test status
Simulation time 15236308 ps
CPU time 1.09 seconds
Started May 09 01:11:54 PM PDT 24
Finished May 09 01:11:56 PM PDT 24
Peak memory 209488 kb
Host smart-bfc81587-38da-478b-ac0f-027347b31a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728783402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.728783402
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3457410934
Short name T880
Test name
Test status
Simulation time 562739916 ps
CPU time 1.68 seconds
Started May 09 01:11:50 PM PDT 24
Finished May 09 01:11:53 PM PDT 24
Peak memory 209324 kb
Host smart-deb75c42-d511-4af9-9246-319890e38d0b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457410934 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3457410934
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1064363522
Short name T140
Test name
Test status
Simulation time 951101831 ps
CPU time 6.26 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:56 PM PDT 24
Peak memory 208560 kb
Host smart-9fecf71d-dcc6-43d4-be07-4e7bc1c2001d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064363522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1064363522
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.658328277
Short name T900
Test name
Test status
Simulation time 1665850870 ps
CPU time 7.83 seconds
Started May 09 01:11:46 PM PDT 24
Finished May 09 01:11:54 PM PDT 24
Peak memory 209048 kb
Host smart-5d5d6b64-fad4-4f5d-a1ff-62d84aa5028f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658328277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.658328277
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.42467181
Short name T138
Test name
Test status
Simulation time 92692846 ps
CPU time 2.75 seconds
Started May 09 01:11:53 PM PDT 24
Finished May 09 01:11:58 PM PDT 24
Peak memory 210908 kb
Host smart-70166b5d-46be-4063-abfb-22280dc4b166
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.42467181
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.232863969
Short name T984
Test name
Test status
Simulation time 501477863 ps
CPU time 1.63 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 219356 kb
Host smart-d594e98a-b221-4bf1-9ec1-f3ae281662be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232863
969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.232863969
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3382257358
Short name T962
Test name
Test status
Simulation time 360574628 ps
CPU time 3.85 seconds
Started May 09 01:11:54 PM PDT 24
Finished May 09 01:11:59 PM PDT 24
Peak memory 209400 kb
Host smart-36ca1993-6beb-4b7b-8ab2-d38b099e5ef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382257358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3382257358
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3363545341
Short name T987
Test name
Test status
Simulation time 93191808 ps
CPU time 1.63 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:50 PM PDT 24
Peak memory 209508 kb
Host smart-1703b820-c5c7-4b82-a325-329623e13da4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363545341 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3363545341
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1691921097
Short name T994
Test name
Test status
Simulation time 41706006 ps
CPU time 1.51 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:49 PM PDT 24
Peak memory 211580 kb
Host smart-ce698b8d-acf9-471b-9b90-461a214fe860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691921097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1691921097
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1626130993
Short name T948
Test name
Test status
Simulation time 221835834 ps
CPU time 2.83 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:51 PM PDT 24
Peak memory 217756 kb
Host smart-65ab97ac-a46a-4cc2-9d92-4b8c09091ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626130993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1626130993
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2047348587
Short name T123
Test name
Test status
Simulation time 103675504 ps
CPU time 2.99 seconds
Started May 09 01:11:51 PM PDT 24
Finished May 09 01:11:55 PM PDT 24
Peak memory 221700 kb
Host smart-f483b254-2cd0-418a-8c03-2592615baed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047348587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2047348587
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.899735957
Short name T210
Test name
Test status
Simulation time 57053316 ps
CPU time 1.37 seconds
Started May 09 01:11:58 PM PDT 24
Finished May 09 01:12:01 PM PDT 24
Peak memory 209480 kb
Host smart-0f2abbe0-936c-4bd0-aaf0-1ea4b1dea8a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899735957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.899735957
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.513629165
Short name T957
Test name
Test status
Simulation time 70721340 ps
CPU time 1.86 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 209700 kb
Host smart-56263b5f-1952-4857-9fe3-9f542e89c0af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513629165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.513629165
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1128294152
Short name T909
Test name
Test status
Simulation time 36452259 ps
CPU time 1.11 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:03 PM PDT 24
Peak memory 211432 kb
Host smart-9de3dc3d-6ff8-49ab-9e78-45b9c360d562
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128294152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1128294152
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2956123435
Short name T955
Test name
Test status
Simulation time 257956214 ps
CPU time 1.29 seconds
Started May 09 01:11:58 PM PDT 24
Finished May 09 01:12:00 PM PDT 24
Peak memory 217764 kb
Host smart-e5c70adf-18f0-4e7f-9093-7cbe894a0ba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956123435 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2956123435
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3491846382
Short name T204
Test name
Test status
Simulation time 43737834 ps
CPU time 0.82 seconds
Started May 09 01:12:03 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 209348 kb
Host smart-fd2bc84b-d885-476f-9bd8-2cc7f0effc3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491846382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3491846382
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4273832701
Short name T940
Test name
Test status
Simulation time 32487090 ps
CPU time 1.48 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:50 PM PDT 24
Peak memory 209340 kb
Host smart-54dce2da-f2fa-48cb-8160-03d02e1ff518
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273832701 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.4273832701
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.616269852
Short name T964
Test name
Test status
Simulation time 185870244 ps
CPU time 5.34 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:56 PM PDT 24
Peak memory 209200 kb
Host smart-9fcfa8ac-fc03-43ce-804d-d56a6f555fc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616269852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.616269852
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1424512244
Short name T992
Test name
Test status
Simulation time 1014205459 ps
CPU time 8.55 seconds
Started May 09 01:11:50 PM PDT 24
Finished May 09 01:12:00 PM PDT 24
Peak memory 209372 kb
Host smart-124578d8-6e56-4af6-9a02-3302c29be328
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424512244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1424512244
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3828558364
Short name T917
Test name
Test status
Simulation time 141423092 ps
CPU time 1.8 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 210928 kb
Host smart-15712f40-bdd9-4840-8889-7ebb9afaabb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828558364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3828558364
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1964449722
Short name T905
Test name
Test status
Simulation time 383323334 ps
CPU time 1.52 seconds
Started May 09 01:11:48 PM PDT 24
Finished May 09 01:11:51 PM PDT 24
Peak memory 218744 kb
Host smart-7160c929-c181-4356-8446-44f9f9da9eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196444
9722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1964449722
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2903283836
Short name T887
Test name
Test status
Simulation time 78261343 ps
CPU time 1.53 seconds
Started May 09 01:11:49 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 209284 kb
Host smart-6636ac9a-18a4-4dcb-beba-06027a7b34c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903283836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2903283836
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1040852858
Short name T891
Test name
Test status
Simulation time 15446686 ps
CPU time 1.02 seconds
Started May 09 01:11:47 PM PDT 24
Finished May 09 01:11:49 PM PDT 24
Peak memory 209512 kb
Host smart-f9e44d7a-76b3-4a74-a304-415ddc8cfea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040852858 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1040852858
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.640274065
Short name T216
Test name
Test status
Simulation time 67652077 ps
CPU time 1.46 seconds
Started May 09 01:11:59 PM PDT 24
Finished May 09 01:12:02 PM PDT 24
Peak memory 209416 kb
Host smart-6109c9cd-9226-48e6-bca4-602f01a64e9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640274065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.640274065
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.211163817
Short name T980
Test name
Test status
Simulation time 245799937 ps
CPU time 3.41 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 218148 kb
Host smart-b45f405e-7852-480e-b284-d6a24c7da71d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211163817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.211163817
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.63864667
Short name T969
Test name
Test status
Simulation time 45979825 ps
CPU time 2.45 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 217688 kb
Host smart-f07c7c7c-401c-4296-8efa-290953736d63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63864667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er
r.63864667
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2264673914
Short name T211
Test name
Test status
Simulation time 42745205 ps
CPU time 1.99 seconds
Started May 09 01:11:59 PM PDT 24
Finished May 09 01:12:03 PM PDT 24
Peak memory 209528 kb
Host smart-54f6b166-b2dd-4053-8500-6a23aba0bfc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264673914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2264673914
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.389785890
Short name T993
Test name
Test status
Simulation time 134936307 ps
CPU time 1.35 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 209456 kb
Host smart-a26b5a87-e0f2-4cd9-b4c9-bdd0e451d8dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389785890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.389785890
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1547809502
Short name T989
Test name
Test status
Simulation time 52129276 ps
CPU time 0.95 seconds
Started May 09 01:11:58 PM PDT 24
Finished May 09 01:12:00 PM PDT 24
Peak memory 209856 kb
Host smart-c4d869e3-af88-425f-ab11-c66ba67c0e82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547809502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1547809502
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2722916917
Short name T945
Test name
Test status
Simulation time 45290267 ps
CPU time 1.44 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:02 PM PDT 24
Peak memory 219740 kb
Host smart-7c3c1bc7-0aaa-422c-8824-e03bfb9c5e04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722916917 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2722916917
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.253590807
Short name T886
Test name
Test status
Simulation time 15585606 ps
CPU time 1.06 seconds
Started May 09 01:12:03 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 209456 kb
Host smart-e4ab6340-6440-4243-b54e-2eb96a003a0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253590807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.253590807
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.774041028
Short name T951
Test name
Test status
Simulation time 129798101 ps
CPU time 1.47 seconds
Started May 09 01:11:59 PM PDT 24
Finished May 09 01:12:02 PM PDT 24
Peak memory 208076 kb
Host smart-119b49a6-9755-465e-99cc-c09905b5fc4f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774041028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.774041028
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3809214986
Short name T1000
Test name
Test status
Simulation time 186515820 ps
CPU time 5 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:06 PM PDT 24
Peak memory 209260 kb
Host smart-10aae2bc-746a-428b-86b2-e63f041e4b12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809214986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3809214986
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3046619827
Short name T885
Test name
Test status
Simulation time 4978285665 ps
CPU time 12.15 seconds
Started May 09 01:12:03 PM PDT 24
Finished May 09 01:12:16 PM PDT 24
Peak memory 208632 kb
Host smart-56c057ee-4a79-49b0-8e1d-e2a509ef86ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046619827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3046619827
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2092380779
Short name T959
Test name
Test status
Simulation time 247410465 ps
CPU time 2.6 seconds
Started May 09 01:12:03 PM PDT 24
Finished May 09 01:12:07 PM PDT 24
Peak memory 210940 kb
Host smart-ebc78502-883e-4e9e-a2af-06101d543a1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092380779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2092380779
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1926940442
Short name T925
Test name
Test status
Simulation time 192324305 ps
CPU time 5.1 seconds
Started May 09 01:11:59 PM PDT 24
Finished May 09 01:12:06 PM PDT 24
Peak memory 218572 kb
Host smart-1e3e37f8-3632-40f7-83e7-f661565c8c81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192694
0442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1926940442
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2022422791
Short name T139
Test name
Test status
Simulation time 45583356 ps
CPU time 1.6 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 209388 kb
Host smart-6a817846-894c-4b84-bf88-e8dd13a674f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022422791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2022422791
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1303804760
Short name T981
Test name
Test status
Simulation time 210436814 ps
CPU time 1.04 seconds
Started May 09 01:12:04 PM PDT 24
Finished May 09 01:12:07 PM PDT 24
Peak memory 209504 kb
Host smart-fa2cfb9d-6136-4690-b027-a50487a716bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303804760 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1303804760
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2696585110
Short name T914
Test name
Test status
Simulation time 63491038 ps
CPU time 1.24 seconds
Started May 09 01:12:02 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 209488 kb
Host smart-ead81741-09f3-4747-a1a7-2d0e122b5d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696585110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2696585110
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2161954282
Short name T924
Test name
Test status
Simulation time 110453533 ps
CPU time 3.36 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 217744 kb
Host smart-635f452e-df60-4245-903f-7a2ce8522d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161954282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2161954282
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4008508572
Short name T999
Test name
Test status
Simulation time 169662223 ps
CPU time 1.52 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 217960 kb
Host smart-00db8e12-cb6d-4d58-95bf-a08ea53f165c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008508572 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4008508572
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2791129199
Short name T930
Test name
Test status
Simulation time 79064803 ps
CPU time 0.89 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:07 PM PDT 24
Peak memory 209420 kb
Host smart-2d8178c5-9106-4188-a49e-a5559cea6c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791129199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2791129199
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2269793796
Short name T973
Test name
Test status
Simulation time 36683231 ps
CPU time 1.05 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:03 PM PDT 24
Peak memory 207940 kb
Host smart-70b929cf-276a-407f-ac1d-6335f6ba1e91
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269793796 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2269793796
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.158407056
Short name T921
Test name
Test status
Simulation time 568892319 ps
CPU time 14.07 seconds
Started May 09 01:11:59 PM PDT 24
Finished May 09 01:12:14 PM PDT 24
Peak memory 209088 kb
Host smart-4e3a4c04-1b9c-48a4-8628-a21908d65956
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158407056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.158407056
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4037628013
Short name T950
Test name
Test status
Simulation time 14769205114 ps
CPU time 10.88 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 209424 kb
Host smart-632ca4d7-f0e2-43dd-9168-66588b50a7d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037628013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4037628013
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3003085238
Short name T882
Test name
Test status
Simulation time 195038628 ps
CPU time 3.94 seconds
Started May 09 01:12:04 PM PDT 24
Finished May 09 01:12:09 PM PDT 24
Peak memory 211012 kb
Host smart-a244dac4-4586-4c92-946b-c3ffe691c8db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003085238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3003085238
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2711770831
Short name T912
Test name
Test status
Simulation time 204215957 ps
CPU time 5.71 seconds
Started May 09 01:12:07 PM PDT 24
Finished May 09 01:12:14 PM PDT 24
Peak memory 218572 kb
Host smart-c3e2705f-0ce4-487b-bccd-81878c91389f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271177
0831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2711770831
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2838782792
Short name T136
Test name
Test status
Simulation time 65125883 ps
CPU time 1.34 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 208440 kb
Host smart-2703e7fd-731f-4093-afbc-442c6e8b8036
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838782792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2838782792
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2783667395
Short name T970
Test name
Test status
Simulation time 17611004 ps
CPU time 1.1 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:07 PM PDT 24
Peak memory 217688 kb
Host smart-bfce69e9-899d-44d4-88ff-11f01acbbc9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783667395 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2783667395
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1223998678
Short name T935
Test name
Test status
Simulation time 25813637 ps
CPU time 1.06 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:07 PM PDT 24
Peak memory 209464 kb
Host smart-9a3d402d-b21b-4cd6-8caa-00a9dfd51a84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223998678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1223998678
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2997775639
Short name T929
Test name
Test status
Simulation time 76206860 ps
CPU time 1.43 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 217740 kb
Host smart-396cdf01-cfaf-4938-b705-dc45721f4514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997775639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2997775639
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.524230041
Short name T116
Test name
Test status
Simulation time 41592207 ps
CPU time 1.75 seconds
Started May 09 01:12:07 PM PDT 24
Finished May 09 01:12:10 PM PDT 24
Peak memory 219244 kb
Host smart-44b9ca1b-0899-42d5-a79d-d9d9f828005c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524230041 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.524230041
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3915137579
Short name T206
Test name
Test status
Simulation time 13424341 ps
CPU time 0.87 seconds
Started May 09 01:12:06 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 209488 kb
Host smart-a000ae2f-420d-4675-860d-263816fb1316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915137579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3915137579
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.259203730
Short name T142
Test name
Test status
Simulation time 305868382 ps
CPU time 2.65 seconds
Started May 09 01:11:58 PM PDT 24
Finished May 09 01:12:02 PM PDT 24
Peak memory 209336 kb
Host smart-df9d6a94-a3e5-4e86-b814-b4c03aa38cb2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259203730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.259203730
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3993653540
Short name T919
Test name
Test status
Simulation time 330664792 ps
CPU time 7.81 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:11 PM PDT 24
Peak memory 207896 kb
Host smart-d0193fde-eb4d-467d-8db9-ed94b427c580
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993653540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3993653540
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.583086471
Short name T143
Test name
Test status
Simulation time 1890722767 ps
CPU time 21.66 seconds
Started May 09 01:12:01 PM PDT 24
Finished May 09 01:12:24 PM PDT 24
Peak memory 209296 kb
Host smart-dadc583e-ca52-4756-bbc2-19efd87a76fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583086471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.583086471
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1266383145
Short name T890
Test name
Test status
Simulation time 44965366 ps
CPU time 1.92 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:03 PM PDT 24
Peak memory 210828 kb
Host smart-31f0d3e5-064d-4117-b6a8-b89e28fb24ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266383145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1266383145
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4108997386
Short name T161
Test name
Test status
Simulation time 157539728 ps
CPU time 3.05 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 218740 kb
Host smart-630e1a95-cb78-403b-8f6d-3071aac9a7cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410899
7386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4108997386
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1999580528
Short name T998
Test name
Test status
Simulation time 308119982 ps
CPU time 2.12 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 209320 kb
Host smart-56037f01-5c69-44e5-afdb-9d1b68ef315b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999580528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1999580528
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2566985410
Short name T213
Test name
Test status
Simulation time 19353503 ps
CPU time 1.49 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 211404 kb
Host smart-a21c1f47-9c5a-4552-9677-672e06b334ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566985410 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2566985410
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3000818762
Short name T150
Test name
Test status
Simulation time 27489041 ps
CPU time 1.4 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 209444 kb
Host smart-29714c7f-958c-4601-aff5-d9e9cf8a52de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000818762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3000818762
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1666072392
Short name T118
Test name
Test status
Simulation time 210947215 ps
CPU time 4.5 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:06 PM PDT 24
Peak memory 217748 kb
Host smart-cdf4cde0-88a5-429d-9af3-3a01ee495e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666072392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1666072392
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3300603898
Short name T226
Test name
Test status
Simulation time 153950179 ps
CPU time 1.77 seconds
Started May 09 01:12:06 PM PDT 24
Finished May 09 01:12:09 PM PDT 24
Peak memory 221684 kb
Host smart-7a599d30-8533-4ff5-8ee6-299e8d935ced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300603898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3300603898
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.599889674
Short name T897
Test name
Test status
Simulation time 33575106 ps
CPU time 1.29 seconds
Started May 09 01:12:06 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 218896 kb
Host smart-1f9792ad-4aca-4a22-a199-2342e51d2433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599889674 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.599889674
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2838096654
Short name T201
Test name
Test status
Simulation time 71918909 ps
CPU time 0.84 seconds
Started May 09 01:12:06 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 209316 kb
Host smart-53070ee8-d92a-4f32-b810-eeaab83df583
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838096654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2838096654
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.229461764
Short name T995
Test name
Test status
Simulation time 88510435 ps
CPU time 1.41 seconds
Started May 09 01:12:06 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 209412 kb
Host smart-355bb3a4-15cb-44a5-8e50-27667d72ad41
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229461764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.229461764
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1365029794
Short name T943
Test name
Test status
Simulation time 362891944 ps
CPU time 4.8 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:12 PM PDT 24
Peak memory 208560 kb
Host smart-6f14647c-9d0a-4504-817f-6e850871c14c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365029794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1365029794
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.984522777
Short name T883
Test name
Test status
Simulation time 1778623416 ps
CPU time 9.42 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:16 PM PDT 24
Peak memory 209352 kb
Host smart-f6a15387-738d-4667-9b6e-831cbb933cfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984522777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.984522777
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.676835961
Short name T978
Test name
Test status
Simulation time 156768446 ps
CPU time 2.25 seconds
Started May 09 01:11:59 PM PDT 24
Finished May 09 01:12:02 PM PDT 24
Peak memory 210960 kb
Host smart-dc05dc67-ba88-4822-a658-87ee6e6cfe0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676835961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.676835961
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3056856364
Short name T899
Test name
Test status
Simulation time 436939517 ps
CPU time 3.45 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:10 PM PDT 24
Peak memory 223172 kb
Host smart-7f7260ac-54f6-4a94-bb20-9f43462c6fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305685
6364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3056856364
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3173590253
Short name T923
Test name
Test status
Simulation time 84226540 ps
CPU time 1.5 seconds
Started May 09 01:12:02 PM PDT 24
Finished May 09 01:12:05 PM PDT 24
Peak memory 209448 kb
Host smart-29d2db2e-a13e-4ca7-93ee-070cf0568ec2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173590253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3173590253
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2236042240
Short name T214
Test name
Test status
Simulation time 71054418 ps
CPU time 1.44 seconds
Started May 09 01:12:07 PM PDT 24
Finished May 09 01:12:09 PM PDT 24
Peak memory 211204 kb
Host smart-8f0d813d-e412-4364-b58d-93ceba07a6b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236042240 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2236042240
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2439213426
Short name T960
Test name
Test status
Simulation time 49021333 ps
CPU time 0.99 seconds
Started May 09 01:12:07 PM PDT 24
Finished May 09 01:12:09 PM PDT 24
Peak memory 209572 kb
Host smart-0a291381-054b-4578-9963-b71416a5973d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439213426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2439213426
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3127432410
Short name T119
Test name
Test status
Simulation time 121593392 ps
CPU time 2.32 seconds
Started May 09 01:12:00 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 217780 kb
Host smart-4165747c-3610-4ccb-89e9-fce8298962ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127432410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3127432410
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3579807993
Short name T971
Test name
Test status
Simulation time 155050787 ps
CPU time 1.34 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 217752 kb
Host smart-8a3702de-6767-4bc8-9134-cea4ecec3dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579807993 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3579807993
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3616753513
Short name T892
Test name
Test status
Simulation time 14673568 ps
CPU time 1.09 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 209328 kb
Host smart-e0f96a5f-a4a8-4ba5-86c2-8ce04a011647
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616753513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3616753513
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3564619350
Short name T976
Test name
Test status
Simulation time 46680919 ps
CPU time 1.22 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:14 PM PDT 24
Peak memory 208080 kb
Host smart-4ca09402-f272-47cd-b894-180c224779fb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564619350 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3564619350
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3571752804
Short name T954
Test name
Test status
Simulation time 1400813245 ps
CPU time 7.22 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:21 PM PDT 24
Peak memory 209200 kb
Host smart-5d6f8a7f-2d96-47e3-89c7-feb60b887b05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571752804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3571752804
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2031107760
Short name T893
Test name
Test status
Simulation time 947579098 ps
CPU time 8.24 seconds
Started May 09 01:12:02 PM PDT 24
Finished May 09 01:12:12 PM PDT 24
Peak memory 209108 kb
Host smart-b6073734-bb7f-49ad-9659-147132ffad7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031107760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2031107760
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3992014570
Short name T907
Test name
Test status
Simulation time 728522017 ps
CPU time 2.25 seconds
Started May 09 01:12:05 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 211000 kb
Host smart-80421154-330b-4012-a5b3-615e9567246f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992014570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3992014570
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.919811884
Short name T972
Test name
Test status
Simulation time 220956105 ps
CPU time 1.97 seconds
Started May 09 01:12:16 PM PDT 24
Finished May 09 01:12:19 PM PDT 24
Peak memory 217688 kb
Host smart-572e5865-08b7-429f-a7e7-6a1d02eced77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919811
884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.919811884
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1508813188
Short name T965
Test name
Test status
Simulation time 91465795 ps
CPU time 1.12 seconds
Started May 09 01:12:04 PM PDT 24
Finished May 09 01:12:07 PM PDT 24
Peak memory 209424 kb
Host smart-b5249c47-aec4-41d5-b51e-dc79064fec4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508813188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1508813188
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3145435172
Short name T218
Test name
Test status
Simulation time 25573660 ps
CPU time 1.21 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 209404 kb
Host smart-e3c18804-fb24-4308-9fbf-5d7479e71f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145435172 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3145435172
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2830323382
Short name T968
Test name
Test status
Simulation time 163924464 ps
CPU time 1.87 seconds
Started May 09 01:12:09 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 211444 kb
Host smart-9c135404-e774-4047-bd72-52d839fb9365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830323382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2830323382
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3637727784
Short name T106
Test name
Test status
Simulation time 142409936 ps
CPU time 2.04 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 217992 kb
Host smart-d78cab34-5d34-4ca7-99e6-fd4830d5ffca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637727784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3637727784
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2545191079
Short name T941
Test name
Test status
Simulation time 18840032 ps
CPU time 1.39 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 217852 kb
Host smart-1c735f3f-0f46-44ff-836e-7ebd36ca1c53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545191079 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2545191079
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.560674446
Short name T114
Test name
Test status
Simulation time 13931560 ps
CPU time 1.1 seconds
Started May 09 01:12:12 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 209496 kb
Host smart-6d74375c-fa5c-4d31-9b26-b90aaa15735a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560674446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.560674446
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.986098333
Short name T938
Test name
Test status
Simulation time 65972569 ps
CPU time 1.38 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:16 PM PDT 24
Peak memory 209384 kb
Host smart-0cefc901-88f7-4062-88c7-7bb95201b823
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986098333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.986098333
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1247667996
Short name T904
Test name
Test status
Simulation time 897030855 ps
CPU time 5.82 seconds
Started May 09 01:12:11 PM PDT 24
Finished May 09 01:12:19 PM PDT 24
Peak memory 209184 kb
Host smart-933f299d-3ed6-4be8-a450-0bb154fd2b61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247667996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1247667996
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3827998387
Short name T946
Test name
Test status
Simulation time 678868704 ps
CPU time 9.47 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:25 PM PDT 24
Peak memory 209128 kb
Host smart-083253e0-51ee-46e4-9806-112051971b53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827998387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3827998387
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2093459972
Short name T956
Test name
Test status
Simulation time 537244107 ps
CPU time 1.47 seconds
Started May 09 01:12:14 PM PDT 24
Finished May 09 01:12:17 PM PDT 24
Peak memory 210712 kb
Host smart-f1ee478b-fc81-428c-ab96-d374eadcc7c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093459972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2093459972
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1380657947
Short name T937
Test name
Test status
Simulation time 221607023 ps
CPU time 2.17 seconds
Started May 09 01:12:09 PM PDT 24
Finished May 09 01:12:12 PM PDT 24
Peak memory 218208 kb
Host smart-489b57ca-c08c-42de-a3f9-2630ebbae996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138065
7947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1380657947
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1977838739
Short name T979
Test name
Test status
Simulation time 1617201935 ps
CPU time 2.86 seconds
Started May 09 01:12:13 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 209400 kb
Host smart-a0e382ca-9a6f-470d-8a72-7a6f9bcacf1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977838739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1977838739
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.752484336
Short name T934
Test name
Test status
Simulation time 101758841 ps
CPU time 1.41 seconds
Started May 09 01:12:10 PM PDT 24
Finished May 09 01:12:13 PM PDT 24
Peak memory 209520 kb
Host smart-b53d417f-6c73-4c8e-8e19-c8c31cdf6954
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752484336 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.752484336
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4117726105
Short name T151
Test name
Test status
Simulation time 101021489 ps
CPU time 1.42 seconds
Started May 09 01:12:14 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 209540 kb
Host smart-7d2c6482-cafe-401e-b0f0-36e72b061c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117726105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4117726105
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.201038770
Short name T944
Test name
Test status
Simulation time 46408738 ps
CPU time 2.79 seconds
Started May 09 01:12:18 PM PDT 24
Finished May 09 01:12:21 PM PDT 24
Peak memory 217760 kb
Host smart-3adb8f01-9c9e-4e5a-81a5-9e47c1dbaf43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201038770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.201038770
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2952215945
Short name T792
Test name
Test status
Simulation time 20798471 ps
CPU time 1.21 seconds
Started May 09 01:13:05 PM PDT 24
Finished May 09 01:13:08 PM PDT 24
Peak memory 210056 kb
Host smart-fbadbbb4-35db-4e29-8e41-7e00e0611e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952215945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2952215945
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2842468784
Short name T677
Test name
Test status
Simulation time 3275821412 ps
CPU time 7.96 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:09 PM PDT 24
Peak memory 218612 kb
Host smart-ea8a6d9d-3a10-4df8-b26c-4c4d31b83a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842468784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2842468784
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1392920052
Short name T791
Test name
Test status
Simulation time 1238131397 ps
CPU time 8.17 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:10 PM PDT 24
Peak memory 217200 kb
Host smart-71e2bd6d-9592-4ad5-b074-3a0b5a018231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392920052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1392920052
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1872372663
Short name T656
Test name
Test status
Simulation time 7688275277 ps
CPU time 26.42 seconds
Started May 09 01:13:00 PM PDT 24
Finished May 09 01:13:29 PM PDT 24
Peak memory 219180 kb
Host smart-4f6c87dc-5e22-45ce-b856-e4b0ccdfbe95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872372663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1872372663
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2835442235
Short name T450
Test name
Test status
Simulation time 3638077776 ps
CPU time 11.34 seconds
Started May 09 01:13:04 PM PDT 24
Finished May 09 01:13:18 PM PDT 24
Peak memory 217956 kb
Host smart-d78fce33-7e70-4eb0-9546-2bc4a22d0251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835442235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
835442235
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1287103978
Short name T6
Test name
Test status
Simulation time 381192951 ps
CPU time 11.27 seconds
Started May 09 01:12:59 PM PDT 24
Finished May 09 01:13:13 PM PDT 24
Peak memory 218160 kb
Host smart-ad51e879-95d9-4b93-b343-b61a02dae96b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287103978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1287103978
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.347440846
Short name T234
Test name
Test status
Simulation time 1113325579 ps
CPU time 32.99 seconds
Started May 09 01:13:04 PM PDT 24
Finished May 09 01:13:40 PM PDT 24
Peak memory 213488 kb
Host smart-9cb5e39a-0835-4599-8936-5ab047839ed4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347440846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.347440846
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2089370954
Short name T655
Test name
Test status
Simulation time 167958121 ps
CPU time 3.57 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:05 PM PDT 24
Peak memory 213720 kb
Host smart-23b8c113-9470-4339-81c4-36afbbaba081
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089370954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2089370954
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3008315714
Short name T761
Test name
Test status
Simulation time 9258980046 ps
CPU time 36.32 seconds
Started May 09 01:12:59 PM PDT 24
Finished May 09 01:13:38 PM PDT 24
Peak memory 267504 kb
Host smart-c3483cf6-b39e-47de-bde3-05712a01e354
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008315714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3008315714
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1808752018
Short name T862
Test name
Test status
Simulation time 432651643 ps
CPU time 11.26 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:12 PM PDT 24
Peak memory 250976 kb
Host smart-fadce5f2-b119-454a-82af-dceee32be633
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808752018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1808752018
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.4119447547
Short name T359
Test name
Test status
Simulation time 36705089 ps
CPU time 1.62 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:02 PM PDT 24
Peak memory 218184 kb
Host smart-8b5d4eeb-fb5b-4eee-86fb-4552680bc19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119447547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.4119447547
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3119558410
Short name T187
Test name
Test status
Simulation time 1452213933 ps
CPU time 11.7 seconds
Started May 09 01:12:59 PM PDT 24
Finished May 09 01:13:13 PM PDT 24
Peak memory 214596 kb
Host smart-edefca3b-04bb-4a61-9a6e-8aefda267d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119558410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3119558410
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1238586405
Short name T281
Test name
Test status
Simulation time 231392487 ps
CPU time 12.57 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:13 PM PDT 24
Peak memory 218276 kb
Host smart-6375a512-da58-42de-a20b-38505831d342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238586405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1238586405
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.863361005
Short name T780
Test name
Test status
Simulation time 2948988091 ps
CPU time 16.85 seconds
Started May 09 01:13:03 PM PDT 24
Finished May 09 01:13:22 PM PDT 24
Peak memory 218312 kb
Host smart-c597697c-825b-433e-ae50-af151f87891b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863361005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.863361005
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2831960201
Short name T820
Test name
Test status
Simulation time 277491210 ps
CPU time 7.88 seconds
Started May 09 01:13:03 PM PDT 24
Finished May 09 01:13:14 PM PDT 24
Peak memory 218180 kb
Host smart-65170702-9754-4b55-ba34-a74806d6a909
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831960201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
831960201
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1436176823
Short name T817
Test name
Test status
Simulation time 232651176 ps
CPU time 6.6 seconds
Started May 09 01:13:01 PM PDT 24
Finished May 09 01:13:10 PM PDT 24
Peak memory 218308 kb
Host smart-a4ee99a0-dc35-4021-a0ef-543b723f85f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436176823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1436176823
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.820306933
Short name T68
Test name
Test status
Simulation time 58713314 ps
CPU time 2.6 seconds
Started May 09 01:12:55 PM PDT 24
Finished May 09 01:12:58 PM PDT 24
Peak memory 214312 kb
Host smart-10cf1a9c-a77b-4a6f-a88e-1b523b7241ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820306933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.820306933
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2661986291
Short name T693
Test name
Test status
Simulation time 1992969388 ps
CPU time 28.02 seconds
Started May 09 01:12:57 PM PDT 24
Finished May 09 01:13:28 PM PDT 24
Peak memory 251084 kb
Host smart-a4a3de14-ea65-4fe1-ae65-98994d332960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661986291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2661986291
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1101242275
Short name T633
Test name
Test status
Simulation time 85880959 ps
CPU time 2.52 seconds
Started May 09 01:12:57 PM PDT 24
Finished May 09 01:13:02 PM PDT 24
Peak memory 222328 kb
Host smart-2236e7ce-cf83-427d-a119-e690961808f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101242275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1101242275
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1722267965
Short name T639
Test name
Test status
Simulation time 35164299879 ps
CPU time 76.97 seconds
Started May 09 01:13:06 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 251136 kb
Host smart-9510f23c-d876-403f-bdb8-3ae2213e89d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722267965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1722267965
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1875784005
Short name T273
Test name
Test status
Simulation time 21852298 ps
CPU time 1.03 seconds
Started May 09 01:12:57 PM PDT 24
Finished May 09 01:13:00 PM PDT 24
Peak memory 211868 kb
Host smart-1b6691b2-81ca-45aa-b609-c0d03bea141c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875784005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1875784005
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3830856820
Short name T480
Test name
Test status
Simulation time 13730955 ps
CPU time 0.99 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:16 PM PDT 24
Peak memory 209768 kb
Host smart-7d687460-26d1-499b-94bc-c67a5268fa45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830856820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3830856820
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1937558800
Short name T153
Test name
Test status
Simulation time 12925099 ps
CPU time 0.85 seconds
Started May 09 01:13:04 PM PDT 24
Finished May 09 01:13:07 PM PDT 24
Peak memory 209884 kb
Host smart-a1454bbd-04b0-4b51-acc5-f3fbae731e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937558800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1937558800
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3986642301
Short name T867
Test name
Test status
Simulation time 1750339715 ps
CPU time 18.04 seconds
Started May 09 01:13:06 PM PDT 24
Finished May 09 01:13:26 PM PDT 24
Peak memory 218400 kb
Host smart-b4e3e3bd-0465-4e3f-9d50-7f62936c65ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986642301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3986642301
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.942962915
Short name T606
Test name
Test status
Simulation time 1302333003 ps
CPU time 9.34 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:23 PM PDT 24
Peak memory 217408 kb
Host smart-1a956b04-586d-430f-b442-15c091e0220a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942962915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.942962915
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1599225668
Short name T827
Test name
Test status
Simulation time 3485854427 ps
CPU time 51.94 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:14:05 PM PDT 24
Peak memory 220168 kb
Host smart-4d098856-57d0-4721-8715-70c05bd0b307
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599225668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1599225668
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.541420751
Short name T430
Test name
Test status
Simulation time 2067784205 ps
CPU time 9.84 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:25 PM PDT 24
Peak memory 217280 kb
Host smart-e1823586-1828-482b-8e26-775a6e59bba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541420751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.541420751
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2549187608
Short name T638
Test name
Test status
Simulation time 221143141 ps
CPU time 7.2 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:22 PM PDT 24
Peak memory 218168 kb
Host smart-3318f497-4ded-4c42-b4d0-a40de8ec29cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549187608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2549187608
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1845651490
Short name T788
Test name
Test status
Simulation time 5071037148 ps
CPU time 34.67 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 214204 kb
Host smart-334f3b28-43db-4cc0-bf09-1e5d8d3feaa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845651490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1845651490
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.814362259
Short name T351
Test name
Test status
Simulation time 213504720 ps
CPU time 6.5 seconds
Started May 09 01:12:58 PM PDT 24
Finished May 09 01:13:07 PM PDT 24
Peak memory 213464 kb
Host smart-7803c76e-9176-46fb-8299-049b32cd4bf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814362259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.814362259
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3635653598
Short name T657
Test name
Test status
Simulation time 8837298692 ps
CPU time 67.07 seconds
Started May 09 01:12:59 PM PDT 24
Finished May 09 01:14:09 PM PDT 24
Peak memory 273084 kb
Host smart-64025aee-cbcc-4f51-9120-d1418e576df1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635653598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3635653598
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2300329552
Short name T863
Test name
Test status
Simulation time 9381031287 ps
CPU time 21.51 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:37 PM PDT 24
Peak memory 251068 kb
Host smart-49396bbf-8be9-4e5f-8a5d-f841e7cd3362
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300329552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2300329552
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1570528715
Short name T529
Test name
Test status
Simulation time 241674122 ps
CPU time 3.44 seconds
Started May 09 01:13:05 PM PDT 24
Finished May 09 01:13:11 PM PDT 24
Peak memory 218476 kb
Host smart-8f5c2fa1-9aea-4e7d-8ac9-0bdb4c2a57bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570528715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1570528715
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.645510634
Short name T83
Test name
Test status
Simulation time 242209633 ps
CPU time 16.45 seconds
Started May 09 01:13:06 PM PDT 24
Finished May 09 01:13:24 PM PDT 24
Peak memory 214856 kb
Host smart-0b1f8865-b743-4ad9-b9db-3cf7d46b4936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645510634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.645510634
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2248401760
Short name T100
Test name
Test status
Simulation time 119580116 ps
CPU time 24.41 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:41 PM PDT 24
Peak memory 280668 kb
Host smart-b6a8c2fc-c60e-4388-9a67-a445f074d821
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248401760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2248401760
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2634486364
Short name T684
Test name
Test status
Simulation time 3316431945 ps
CPU time 19.85 seconds
Started May 09 01:13:10 PM PDT 24
Finished May 09 01:13:32 PM PDT 24
Peak memory 220540 kb
Host smart-4bf6147e-7b24-47ce-b661-c4877e136265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634486364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2634486364
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3310647459
Short name T650
Test name
Test status
Simulation time 233261582 ps
CPU time 7.25 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:21 PM PDT 24
Peak memory 218300 kb
Host smart-f8cf1ecc-9bf2-4119-867d-92fdf43be6f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310647459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3310647459
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2694563241
Short name T779
Test name
Test status
Simulation time 244219136 ps
CPU time 10.09 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:23 PM PDT 24
Peak memory 218248 kb
Host smart-cf2152b3-c173-443e-83b1-767b7e9b63aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694563241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
694563241
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3232628558
Short name T477
Test name
Test status
Simulation time 328453937 ps
CPU time 8.71 seconds
Started May 09 01:12:59 PM PDT 24
Finished May 09 01:13:10 PM PDT 24
Peak memory 218284 kb
Host smart-2f1db082-b5c7-47bb-ab96-85c4a3c7549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232628558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3232628558
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2011449128
Short name T349
Test name
Test status
Simulation time 26089920 ps
CPU time 0.99 seconds
Started May 09 01:12:57 PM PDT 24
Finished May 09 01:13:00 PM PDT 24
Peak memory 212176 kb
Host smart-49bd4209-4528-488f-a1a3-055f38036828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011449128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2011449128
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.574062485
Short name T377
Test name
Test status
Simulation time 231837975 ps
CPU time 20.81 seconds
Started May 09 01:13:03 PM PDT 24
Finished May 09 01:13:26 PM PDT 24
Peak memory 248740 kb
Host smart-8240e9b1-5a55-4583-be14-586835dec6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574062485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.574062485
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2627800847
Short name T575
Test name
Test status
Simulation time 115257881 ps
CPU time 6.52 seconds
Started May 09 01:13:01 PM PDT 24
Finished May 09 01:13:11 PM PDT 24
Peak memory 246672 kb
Host smart-10c983d1-de14-4dc9-a46e-0c161f0ad36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627800847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2627800847
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2794343836
Short name T104
Test name
Test status
Simulation time 25714857219 ps
CPU time 260.01 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:17:34 PM PDT 24
Peak memory 268196 kb
Host smart-478e3c6b-0ae6-4a8f-a0ef-682454225071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794343836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2794343836
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1631423877
Short name T46
Test name
Test status
Simulation time 16491102 ps
CPU time 1.22 seconds
Started May 09 01:13:03 PM PDT 24
Finished May 09 01:13:07 PM PDT 24
Peak memory 212952 kb
Host smart-7ffdb89d-40db-452f-b361-c027c2020953
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631423877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1631423877
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2121450
Short name T602
Test name
Test status
Simulation time 32220747 ps
CPU time 1.1 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:01 PM PDT 24
Peak memory 209820 kb
Host smart-a79a558f-fdbe-4dba-81c8-3f7a4a9042c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2121450
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.61366063
Short name T566
Test name
Test status
Simulation time 70016489 ps
CPU time 1.61 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:01 PM PDT 24
Peak memory 217160 kb
Host smart-01e29d1b-a79a-4140-9462-be8a888b3331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61366063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.61366063
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1535123066
Short name T811
Test name
Test status
Simulation time 2757188070 ps
CPU time 44.65 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:50 PM PDT 24
Peak memory 219064 kb
Host smart-5c85c949-6130-447f-b26a-d0f481e0bfba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535123066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1535123066
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1656209219
Short name T476
Test name
Test status
Simulation time 3359638900 ps
CPU time 16.8 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:16 PM PDT 24
Peak memory 220756 kb
Host smart-92614011-cfbf-4a18-9f39-f6f6a3697ea6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656209219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1656209219
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4257641122
Short name T76
Test name
Test status
Simulation time 204653865 ps
CPU time 3.29 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:05 PM PDT 24
Peak memory 213140 kb
Host smart-f6b43b45-28c9-4f02-8197-b140f866fd24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257641122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.4257641122
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3276734396
Short name T796
Test name
Test status
Simulation time 2763504390 ps
CPU time 40.31 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 267464 kb
Host smart-3c1eff32-b1bb-4864-a119-34ebb3e4ea3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276734396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3276734396
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1074898495
Short name T648
Test name
Test status
Simulation time 315178003 ps
CPU time 6.53 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:05 PM PDT 24
Peak memory 221992 kb
Host smart-ba1fe4c7-1886-4911-995b-9da082b7d610
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074898495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1074898495
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1519334834
Short name T250
Test name
Test status
Simulation time 64419185 ps
CPU time 3.02 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 218288 kb
Host smart-7bed1658-7b4d-4969-975f-5df6efc1bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519334834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1519334834
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1679732952
Short name T664
Test name
Test status
Simulation time 262742722 ps
CPU time 12.41 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 219152 kb
Host smart-8c4edf90-6b3f-4499-a7f4-81c8e229c022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679732952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1679732952
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.306900243
Short name T410
Test name
Test status
Simulation time 366233312 ps
CPU time 10.6 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 218240 kb
Host smart-8f41b76c-4e76-4e56-96a3-7fe5562973d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306900243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.306900243
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2625493906
Short name T762
Test name
Test status
Simulation time 219952302 ps
CPU time 6.47 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 218172 kb
Host smart-84d05ac3-4952-4dc9-9163-c8ea23f359ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625493906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2625493906
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1742327782
Short name T59
Test name
Test status
Simulation time 295940922 ps
CPU time 8.24 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:08 PM PDT 24
Peak memory 218240 kb
Host smart-1e178de6-b723-4176-ab44-4bfae3aa7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742327782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1742327782
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2061557142
Short name T85
Test name
Test status
Simulation time 152212465 ps
CPU time 2.73 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:03 PM PDT 24
Peak memory 214476 kb
Host smart-5c79dc70-d23e-43ab-b3d9-3a7aa72d7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061557142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2061557142
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.889235316
Short name T288
Test name
Test status
Simulation time 332755844 ps
CPU time 33.56 seconds
Started May 09 01:13:56 PM PDT 24
Finished May 09 01:14:30 PM PDT 24
Peak memory 248804 kb
Host smart-d2d5fcd6-8e57-40b3-9c46-0574709413e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889235316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.889235316
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2168187538
Short name T833
Test name
Test status
Simulation time 86573385 ps
CPU time 4.36 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:03 PM PDT 24
Peak memory 218100 kb
Host smart-c55d16ff-dfe0-4198-83fe-e6242d41be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168187538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2168187538
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2132156169
Short name T508
Test name
Test status
Simulation time 25267923193 ps
CPU time 878.23 seconds
Started May 09 01:13:55 PM PDT 24
Finished May 09 01:28:35 PM PDT 24
Peak memory 405556 kb
Host smart-b5e3136a-bf1c-43b1-b270-7965a3dcd1c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132156169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2132156169
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3408072555
Short name T414
Test name
Test status
Simulation time 14484533 ps
CPU time 1.25 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:04 PM PDT 24
Peak memory 212936 kb
Host smart-b05c029f-1ed5-4236-947c-0d4555afb04c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408072555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3408072555
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.604765568
Short name T758
Test name
Test status
Simulation time 61119818 ps
CPU time 1 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 209812 kb
Host smart-d6ce31ab-0273-4663-a240-87d0274ddf39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604765568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.604765568
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3540984640
Short name T724
Test name
Test status
Simulation time 2738125010 ps
CPU time 9.32 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:09 PM PDT 24
Peak memory 218240 kb
Host smart-451babd0-eb3e-463d-b1dd-f95a623ba87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540984640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3540984640
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1852499901
Short name T689
Test name
Test status
Simulation time 104699193 ps
CPU time 3.28 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:01 PM PDT 24
Peak memory 217164 kb
Host smart-0062771c-20ed-4308-81d4-66bc62055773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852499901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1852499901
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4170521520
Short name T47
Test name
Test status
Simulation time 2612845984 ps
CPU time 39.89 seconds
Started May 09 01:14:16 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 218516 kb
Host smart-2372e00d-cea6-4f9f-a97a-f7738cdf2297
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170521520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4170521520
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2722058761
Short name T239
Test name
Test status
Simulation time 67807043 ps
CPU time 2.24 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:03 PM PDT 24
Peak memory 218080 kb
Host smart-9d7be256-c2b1-4cee-9116-edced7f68c07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722058761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2722058761
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3499397988
Short name T445
Test name
Test status
Simulation time 182527986 ps
CPU time 3.23 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:04 PM PDT 24
Peak memory 213684 kb
Host smart-34f9578b-231f-44d3-b76b-439310fa38cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499397988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3499397988
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.4101097499
Short name T483
Test name
Test status
Simulation time 7034693619 ps
CPU time 41.97 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:46 PM PDT 24
Peak memory 271700 kb
Host smart-96a52b5d-422d-491a-9c60-6f849b6ac85e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101097499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.4101097499
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3504742546
Short name T277
Test name
Test status
Simulation time 249412558 ps
CPU time 9.15 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:12 PM PDT 24
Peak memory 218416 kb
Host smart-998f1dd9-a747-41c7-b906-5b2e8431113a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504742546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3504742546
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3518413847
Short name T449
Test name
Test status
Simulation time 349318587 ps
CPU time 10.79 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 219084 kb
Host smart-5fd91ccb-4b4c-4acf-ba57-571607d2af1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518413847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3518413847
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2508844722
Short name T484
Test name
Test status
Simulation time 444348895 ps
CPU time 11.44 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:15 PM PDT 24
Peak memory 218200 kb
Host smart-a6e7681e-7d6e-4190-9695-beac6c4b2a9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508844722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2508844722
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3381819407
Short name T772
Test name
Test status
Simulation time 2926886992 ps
CPU time 13.67 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:17 PM PDT 24
Peak memory 218312 kb
Host smart-2ad3ea21-5add-4513-9769-bf48c3f39522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381819407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3381819407
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3329190001
Short name T492
Test name
Test status
Simulation time 1032762608 ps
CPU time 7.13 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:08 PM PDT 24
Peak memory 218252 kb
Host smart-c6914992-f56a-45c4-9337-338f174364c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329190001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3329190001
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3767110905
Short name T415
Test name
Test status
Simulation time 38627889 ps
CPU time 2.97 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:02 PM PDT 24
Peak memory 214520 kb
Host smart-692d5de4-ac0c-4446-8588-bbc8ee6d6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767110905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3767110905
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2345466765
Short name T856
Test name
Test status
Simulation time 943764444 ps
CPU time 18.55 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:17 PM PDT 24
Peak memory 251072 kb
Host smart-35457f80-d2b3-4146-94f6-f70f628dee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345466765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2345466765
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.866345841
Short name T386
Test name
Test status
Simulation time 61400348 ps
CPU time 8.41 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:12 PM PDT 24
Peak memory 251024 kb
Host smart-ffb6eeff-ab26-403e-9125-b0766dfe2a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866345841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.866345841
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3133465110
Short name T816
Test name
Test status
Simulation time 21637903432 ps
CPU time 242.08 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:18:04 PM PDT 24
Peak memory 422240 kb
Host smart-e046cc97-9b94-4641-894c-bfe04c76cb70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133465110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3133465110
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2332970135
Short name T663
Test name
Test status
Simulation time 15811393 ps
CPU time 1.04 seconds
Started May 09 01:13:56 PM PDT 24
Finished May 09 01:13:58 PM PDT 24
Peak memory 208896 kb
Host smart-c7ada7de-cf77-48e7-bc0e-53185e66cc7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332970135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2332970135
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2806025679
Short name T850
Test name
Test status
Simulation time 66625397 ps
CPU time 0.94 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:05 PM PDT 24
Peak memory 209796 kb
Host smart-e77a96d2-8ece-4066-9970-dab17d3a17e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806025679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2806025679
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3292577670
Short name T417
Test name
Test status
Simulation time 1469419820 ps
CPU time 13.8 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 218156 kb
Host smart-13837338-31af-4906-8fcb-29cb1a9a3e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292577670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3292577670
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.474260093
Short name T763
Test name
Test status
Simulation time 283992944 ps
CPU time 7.27 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:11 PM PDT 24
Peak memory 209804 kb
Host smart-be83dead-bf5a-41e5-b1ca-661221c7af46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474260093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.474260093
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3284774234
Short name T475
Test name
Test status
Simulation time 8031485607 ps
CPU time 38.81 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:44 PM PDT 24
Peak memory 219272 kb
Host smart-e8a86fdc-845c-460b-8ec0-edfe035f823e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284774234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3284774234
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2691973029
Short name T548
Test name
Test status
Simulation time 1473523640 ps
CPU time 7.44 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:08 PM PDT 24
Peak memory 218256 kb
Host smart-aff67f25-118d-4e8d-ae64-71a56999131c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691973029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2691973029
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1594365455
Short name T403
Test name
Test status
Simulation time 1165681069 ps
CPU time 5.62 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 213824 kb
Host smart-2619c174-7014-43e3-a0b9-626d6998be06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594365455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1594365455
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3741941336
Short name T599
Test name
Test status
Simulation time 2183231472 ps
CPU time 52.37 seconds
Started May 09 01:14:17 PM PDT 24
Finished May 09 01:15:12 PM PDT 24
Peak memory 278244 kb
Host smart-3fa18a8d-41e0-45b1-9c26-341b5e8b7b82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741941336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3741941336
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3893455832
Short name T393
Test name
Test status
Simulation time 1619919367 ps
CPU time 20.41 seconds
Started May 09 01:13:57 PM PDT 24
Finished May 09 01:14:19 PM PDT 24
Peak memory 251180 kb
Host smart-927cc61e-1bfc-4c84-aff4-8af14b3fc30c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893455832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3893455832
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3245115402
Short name T253
Test name
Test status
Simulation time 99116790 ps
CPU time 2.46 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:03 PM PDT 24
Peak memory 218268 kb
Host smart-e01dde42-943a-40ea-bdcf-88182ec5a7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245115402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3245115402
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1292208727
Short name T22
Test name
Test status
Simulation time 265943631 ps
CPU time 9.68 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:11 PM PDT 24
Peak memory 226108 kb
Host smart-5f1fb64e-7df8-4a5b-ac2b-6d7df76651c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292208727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1292208727
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2311142878
Short name T855
Test name
Test status
Simulation time 2088861966 ps
CPU time 15.32 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:19 PM PDT 24
Peak memory 218280 kb
Host smart-da931b48-a219-4b4e-b8c9-3052c6986082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311142878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2311142878
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.133660800
Short name T154
Test name
Test status
Simulation time 855366981 ps
CPU time 7.61 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 218200 kb
Host smart-1053d90b-12bd-478b-a947-2824f5ef3604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133660800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.133660800
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2176275405
Short name T747
Test name
Test status
Simulation time 449236690 ps
CPU time 11.59 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:13 PM PDT 24
Peak memory 218132 kb
Host smart-3759526e-7b99-4e40-ae5f-e08a6b64beaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176275405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2176275405
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.797742996
Short name T395
Test name
Test status
Simulation time 47368137 ps
CPU time 2.24 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 213960 kb
Host smart-cc93af8e-d11b-477c-b6b4-ac3955af86ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797742996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.797742996
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.753471078
Short name T232
Test name
Test status
Simulation time 1887070605 ps
CPU time 30.02 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 248808 kb
Host smart-c7186054-8c50-46de-abeb-02186914ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753471078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.753471078
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3947351766
Short name T175
Test name
Test status
Simulation time 52363047 ps
CPU time 2.7 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 222292 kb
Host smart-ea1fde2e-249b-4468-8cf6-f9982007d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947351766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3947351766
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.442914786
Short name T41
Test name
Test status
Simulation time 36921340 ps
CPU time 0.91 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:05 PM PDT 24
Peak memory 211868 kb
Host smart-c3832ac0-88ba-4a6b-9972-dd8a06fd08c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442914786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.442914786
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.4005829196
Short name T874
Test name
Test status
Simulation time 18535611 ps
CPU time 1.14 seconds
Started May 09 01:14:03 PM PDT 24
Finished May 09 01:14:07 PM PDT 24
Peak memory 209728 kb
Host smart-47a62e39-8db4-47ab-b658-0c186d829090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005829196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4005829196
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.968258673
Short name T574
Test name
Test status
Simulation time 563173921 ps
CPU time 15.74 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:21 PM PDT 24
Peak memory 218176 kb
Host smart-bc0d54ae-d42b-4faa-bdb1-122924602940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968258673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.968258673
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3848997235
Short name T25
Test name
Test status
Simulation time 114482948 ps
CPU time 2.1 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:07 PM PDT 24
Peak memory 209832 kb
Host smart-290faf75-c154-4f13-9670-a3ff53134d96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848997235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3848997235
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3766310115
Short name T586
Test name
Test status
Simulation time 6303274038 ps
CPU time 49.65 seconds
Started May 09 01:14:04 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 219116 kb
Host smart-92bf9d3e-0e0f-4552-b05c-dbe71ceff47c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766310115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3766310115
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.173474637
Short name T785
Test name
Test status
Simulation time 737420888 ps
CPU time 6.99 seconds
Started May 09 01:14:07 PM PDT 24
Finished May 09 01:14:15 PM PDT 24
Peak memory 218124 kb
Host smart-19392678-d797-495d-a05b-a97a4035cad9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173474637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.173474637
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2140489708
Short name T75
Test name
Test status
Simulation time 318182293 ps
CPU time 9.22 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:15 PM PDT 24
Peak memory 214076 kb
Host smart-25cc053a-d11e-4fbc-8ebd-e4fa33c81323
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140489708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2140489708
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.13343466
Short name T532
Test name
Test status
Simulation time 2200887444 ps
CPU time 80.49 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:15:24 PM PDT 24
Peak memory 275980 kb
Host smart-6e160c65-ca81-4002-b144-217e37a67656
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_state_failure.13343466
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3039756369
Short name T571
Test name
Test status
Simulation time 355429135 ps
CPU time 10.57 seconds
Started May 09 01:14:04 PM PDT 24
Finished May 09 01:14:17 PM PDT 24
Peak memory 247908 kb
Host smart-823727e1-8269-4a9d-9975-5a1dd4a2513b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039756369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3039756369
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2288088022
Short name T847
Test name
Test status
Simulation time 368918840 ps
CPU time 2.54 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 218324 kb
Host smart-0f044e11-0d6e-4b24-90b1-ca53ea2185f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288088022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2288088022
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2390552334
Short name T596
Test name
Test status
Simulation time 310801084 ps
CPU time 13.5 seconds
Started May 09 01:14:04 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 219108 kb
Host smart-21b037e4-cc03-4cf4-baea-e73ff20ceee0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390552334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2390552334
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.269975048
Short name T188
Test name
Test status
Simulation time 3208790664 ps
CPU time 10.04 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:14 PM PDT 24
Peak memory 218292 kb
Host smart-b552fb0e-2aba-4825-91e2-cdde4fc1a9fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269975048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.269975048
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2265833730
Short name T526
Test name
Test status
Simulation time 1773487183 ps
CPU time 15.09 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 218300 kb
Host smart-1ffd5455-cd3e-4eb6-b549-7d7d3191ac74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265833730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2265833730
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.935976179
Short name T713
Test name
Test status
Simulation time 6250777240 ps
CPU time 9.36 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:11 PM PDT 24
Peak memory 218332 kb
Host smart-4374ca0c-062c-4338-b67a-2356916a5790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935976179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.935976179
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1922386501
Short name T680
Test name
Test status
Simulation time 182665863 ps
CPU time 2.32 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:07 PM PDT 24
Peak memory 214400 kb
Host smart-f6d46541-f7ff-4b54-9fbf-1adc0df15c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922386501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1922386501
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2955331113
Short name T298
Test name
Test status
Simulation time 466738263 ps
CPU time 20 seconds
Started May 09 01:14:02 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 251112 kb
Host smart-74916739-1513-4659-a94d-7a1670aeab81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955331113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2955331113
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2355664719
Short name T261
Test name
Test status
Simulation time 72837450 ps
CPU time 7.39 seconds
Started May 09 01:14:01 PM PDT 24
Finished May 09 01:14:12 PM PDT 24
Peak memory 246768 kb
Host smart-509005b6-baba-45fb-bcb5-cc33878ffa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355664719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2355664719
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.714002550
Short name T18
Test name
Test status
Simulation time 19356908394 ps
CPU time 88.59 seconds
Started May 09 01:14:05 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 251212 kb
Host smart-3bacd6f2-5260-46d6-8c4d-446617a7f923
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714002550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.714002550
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.794712826
Short name T45
Test name
Test status
Simulation time 44221641 ps
CPU time 0.81 seconds
Started May 09 01:13:59 PM PDT 24
Finished May 09 01:14:02 PM PDT 24
Peak memory 208832 kb
Host smart-338ac75c-a357-4c73-822b-f9c18cc106ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794712826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.794712826
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3188967375
Short name T838
Test name
Test status
Simulation time 22319736 ps
CPU time 1.22 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:19 PM PDT 24
Peak memory 209804 kb
Host smart-96101726-1d18-4eae-9977-6f178b5acfd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188967375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3188967375
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3854680125
Short name T426
Test name
Test status
Simulation time 963218510 ps
CPU time 7.7 seconds
Started May 09 01:14:06 PM PDT 24
Finished May 09 01:14:15 PM PDT 24
Peak memory 218200 kb
Host smart-8721f5f3-b1d4-430d-bbc9-c97e5caa3bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854680125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3854680125
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.849173523
Short name T29
Test name
Test status
Simulation time 103564363 ps
CPU time 3.3 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 209808 kb
Host smart-c907f889-17b5-48b4-a6b4-7c7da54f6ab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849173523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.849173523
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3075073810
Short name T784
Test name
Test status
Simulation time 9273922210 ps
CPU time 66.08 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 219148 kb
Host smart-54cb62ca-dc7c-4336-ab85-f69eec3de6bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075073810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3075073810
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2983609373
Short name T653
Test name
Test status
Simulation time 597634388 ps
CPU time 15.97 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:28 PM PDT 24
Peak memory 218236 kb
Host smart-deb4c6d6-2145-48a9-b18a-8401b35db905
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983609373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2983609373
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2251888693
Short name T727
Test name
Test status
Simulation time 2401701091 ps
CPU time 5.95 seconds
Started May 09 01:14:08 PM PDT 24
Finished May 09 01:14:15 PM PDT 24
Peak memory 214272 kb
Host smart-49ed4b7c-daff-42e1-9173-8f94dce5ddb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251888693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2251888693
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1089192527
Short name T830
Test name
Test status
Simulation time 14692022646 ps
CPU time 67.34 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:15:19 PM PDT 24
Peak memory 273892 kb
Host smart-c685fbda-0d67-450d-a048-a947283348b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089192527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1089192527
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3883838222
Short name T233
Test name
Test status
Simulation time 2753063972 ps
CPU time 24.38 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:37 PM PDT 24
Peak memory 251176 kb
Host smart-9a79b50d-4b58-4bcc-bbce-08be6058dedd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883838222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3883838222
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3327858296
Short name T468
Test name
Test status
Simulation time 61784951 ps
CPU time 3.25 seconds
Started May 09 01:14:04 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 218476 kb
Host smart-d267109c-8f21-44f4-852f-30c3b4fd05bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327858296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3327858296
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.271305071
Short name T247
Test name
Test status
Simulation time 4166751558 ps
CPU time 10.84 seconds
Started May 09 01:14:12 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 219296 kb
Host smart-3249a94b-702c-4675-96ae-1bb526f7335f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271305071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.271305071
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1515214154
Short name T425
Test name
Test status
Simulation time 590927382 ps
CPU time 15.56 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:14:32 PM PDT 24
Peak memory 218172 kb
Host smart-51e53e19-6b1e-4743-96b6-a627f39f144e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515214154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1515214154
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1092449150
Short name T270
Test name
Test status
Simulation time 406369554 ps
CPU time 9.66 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:27 PM PDT 24
Peak memory 218084 kb
Host smart-57e93771-7c7a-490c-a052-02e2f16817a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092449150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1092449150
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4018473808
Short name T58
Test name
Test status
Simulation time 461689091 ps
CPU time 10.36 seconds
Started May 09 01:14:00 PM PDT 24
Finished May 09 01:14:14 PM PDT 24
Peak memory 218324 kb
Host smart-2ddf1d6e-5dfa-49c7-8dfe-b0d33e524907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018473808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4018473808
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3140037347
Short name T320
Test name
Test status
Simulation time 17889871 ps
CPU time 1.48 seconds
Started May 09 01:14:06 PM PDT 24
Finished May 09 01:14:09 PM PDT 24
Peak memory 213728 kb
Host smart-1f5c12be-ad1c-46f4-86b5-a6e1863ffb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140037347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3140037347
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2126103843
Short name T873
Test name
Test status
Simulation time 970619667 ps
CPU time 18.91 seconds
Started May 09 01:14:03 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 251060 kb
Host smart-cb7f3704-d53b-48c6-bda1-f73fdd6d1c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126103843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2126103843
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2603561923
Short name T764
Test name
Test status
Simulation time 99289473 ps
CPU time 6.62 seconds
Started May 09 01:14:05 PM PDT 24
Finished May 09 01:14:14 PM PDT 24
Peak memory 246336 kb
Host smart-405c57b0-8600-4cd1-b9e9-a16ceaa1f5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603561923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2603561923
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.935271827
Short name T20
Test name
Test status
Simulation time 9607467456 ps
CPU time 275.35 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:18:50 PM PDT 24
Peak memory 251228 kb
Host smart-1c7e95dc-c0ba-4416-98e5-819d7ff4f854
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935271827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.935271827
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1217143013
Short name T99
Test name
Test status
Simulation time 108422320836 ps
CPU time 1723.05 seconds
Started May 09 01:14:11 PM PDT 24
Finished May 09 01:42:56 PM PDT 24
Peak memory 529684 kb
Host smart-1f29cba4-1b23-4d4b-a454-e80ff91e9d13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1217143013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1217143013
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1203865448
Short name T487
Test name
Test status
Simulation time 17061845 ps
CPU time 0.79 seconds
Started May 09 01:14:07 PM PDT 24
Finished May 09 01:14:09 PM PDT 24
Peak memory 208028 kb
Host smart-a3cf6fa2-b260-44c0-a9ba-817cb0ca7cc6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203865448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1203865448
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3672794026
Short name T840
Test name
Test status
Simulation time 20259921 ps
CPU time 1.17 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 209744 kb
Host smart-faec6caf-4951-4867-8563-4ffc43cf6591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672794026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3672794026
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.219143079
Short name T77
Test name
Test status
Simulation time 1257437448 ps
CPU time 21.76 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 218404 kb
Host smart-e5cd8f2e-ffa1-4747-8413-2151c9d32009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219143079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.219143079
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3549767105
Short name T24
Test name
Test status
Simulation time 11443616028 ps
CPU time 14.72 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:14:31 PM PDT 24
Peak memory 217868 kb
Host smart-01ef2a14-dbc2-4e55-8511-86054f76d569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549767105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3549767105
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2017003208
Short name T442
Test name
Test status
Simulation time 6148309693 ps
CPU time 45.8 seconds
Started May 09 01:14:07 PM PDT 24
Finished May 09 01:14:55 PM PDT 24
Peak memory 218304 kb
Host smart-026ace26-8ccc-4902-9588-76b0ef4139d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017003208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2017003208
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.341782192
Short name T521
Test name
Test status
Simulation time 150772353 ps
CPU time 3.41 seconds
Started May 09 01:14:08 PM PDT 24
Finished May 09 01:14:13 PM PDT 24
Peak memory 218160 kb
Host smart-b7900ab4-caa8-4520-9571-4d515b924601
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341782192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.341782192
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3448347549
Short name T846
Test name
Test status
Simulation time 264640877 ps
CPU time 7.94 seconds
Started May 09 01:14:08 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 213752 kb
Host smart-aa2cc07c-c56f-4c79-b8bf-ae3be27062a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448347549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3448347549
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1916946924
Short name T435
Test name
Test status
Simulation time 2229158902 ps
CPU time 66.18 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:15:27 PM PDT 24
Peak memory 272604 kb
Host smart-41a29ea1-2d4a-4005-a90f-3bb421c03e5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916946924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1916946924
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2820501035
Short name T807
Test name
Test status
Simulation time 665317427 ps
CPU time 11.52 seconds
Started May 09 01:14:07 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 222120 kb
Host smart-c1482ee4-8d6d-45dc-9c46-47f5fc5207fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820501035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2820501035
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2374714858
Short name T181
Test name
Test status
Simulation time 137407780 ps
CPU time 2.3 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:24 PM PDT 24
Peak memory 218076 kb
Host smart-7bb0d68e-ca81-4206-a064-7230683c6c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374714858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2374714858
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.957844903
Short name T155
Test name
Test status
Simulation time 2463566715 ps
CPU time 25.25 seconds
Started May 09 01:14:12 PM PDT 24
Finished May 09 01:14:39 PM PDT 24
Peak memory 226656 kb
Host smart-134afa6c-494a-4486-9887-8e19aa6b9804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957844903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.957844903
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2348493140
Short name T705
Test name
Test status
Simulation time 278819000 ps
CPU time 10.26 seconds
Started May 09 01:14:11 PM PDT 24
Finished May 09 01:14:24 PM PDT 24
Peak memory 218488 kb
Host smart-462f28ff-b231-401c-8632-c6e72b6597a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348493140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2348493140
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3802092253
Short name T778
Test name
Test status
Simulation time 480458808 ps
CPU time 7.37 seconds
Started May 09 01:14:12 PM PDT 24
Finished May 09 01:14:21 PM PDT 24
Peak memory 218252 kb
Host smart-c8b4353c-59cc-4a97-acff-0da9fc3ec12d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802092253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3802092253
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.367502756
Short name T583
Test name
Test status
Simulation time 1032869542 ps
CPU time 7.95 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 218276 kb
Host smart-b23664c0-1f77-4d7e-9659-51a1eee7868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367502756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.367502756
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.523586246
Short name T865
Test name
Test status
Simulation time 90610644 ps
CPU time 1.67 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:17 PM PDT 24
Peak memory 217976 kb
Host smart-1e42a20f-093c-4102-9718-e15438e9895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523586246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.523586246
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.276502104
Short name T849
Test name
Test status
Simulation time 379782292 ps
CPU time 18.7 seconds
Started May 09 01:14:08 PM PDT 24
Finished May 09 01:14:29 PM PDT 24
Peak memory 251032 kb
Host smart-90ecbc92-47ee-4141-9638-314c55a838e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276502104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.276502104
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3179952573
Short name T824
Test name
Test status
Simulation time 175235752 ps
CPU time 9.24 seconds
Started May 09 01:14:07 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 251128 kb
Host smart-1f5892d1-f496-4113-b654-1a08836ea578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179952573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3179952573
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1652627510
Short name T392
Test name
Test status
Simulation time 9290037796 ps
CPU time 155.27 seconds
Started May 09 01:14:08 PM PDT 24
Finished May 09 01:16:44 PM PDT 24
Peak memory 281436 kb
Host smart-1a497dc5-f25e-486c-b91e-7fc4d97defcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652627510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1652627510
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2227680814
Short name T50
Test name
Test status
Simulation time 34997301797 ps
CPU time 779.5 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:27:16 PM PDT 24
Peak memory 312376 kb
Host smart-5894962f-d0a3-4d1c-8089-37af3a651d21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2227680814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2227680814
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3827185909
Short name T543
Test name
Test status
Simulation time 24342175 ps
CPU time 0.87 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:16 PM PDT 24
Peak memory 209600 kb
Host smart-336af51f-c369-4536-aa45-1baa00964a67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827185909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3827185909
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.806832516
Short name T173
Test name
Test status
Simulation time 6163540044 ps
CPU time 20.59 seconds
Started May 09 01:14:09 PM PDT 24
Finished May 09 01:14:32 PM PDT 24
Peak memory 218528 kb
Host smart-4a72d81d-8d70-4a16-8ecc-cf550749ffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806832516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.806832516
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1122326813
Short name T523
Test name
Test status
Simulation time 12930543253 ps
CPU time 15.93 seconds
Started May 09 01:14:11 PM PDT 24
Finished May 09 01:14:29 PM PDT 24
Peak memory 209884 kb
Host smart-fc408d6e-1803-411f-b866-da7fec406d3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122326813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1122326813
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3173138110
Short name T310
Test name
Test status
Simulation time 1761926622 ps
CPU time 37.27 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:54 PM PDT 24
Peak memory 218264 kb
Host smart-f12ff587-0ae7-4ad6-8b35-a60c564a17cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173138110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3173138110
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3031205492
Short name T189
Test name
Test status
Simulation time 294036184 ps
CPU time 5.26 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:23 PM PDT 24
Peak memory 218248 kb
Host smart-7be0dd9f-65d7-49dc-a9e5-1ea1abfc305d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031205492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3031205492
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3144409669
Short name T708
Test name
Test status
Simulation time 176260347 ps
CPU time 5.87 seconds
Started May 09 01:14:09 PM PDT 24
Finished May 09 01:14:17 PM PDT 24
Peak memory 213656 kb
Host smart-c44ca9e9-8538-4b6b-a958-9f014f84b60a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144409669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3144409669
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2367804189
Short name T235
Test name
Test status
Simulation time 7608899977 ps
CPU time 42.07 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:59 PM PDT 24
Peak memory 277532 kb
Host smart-231c846d-ee13-4734-9ceb-1a37692354da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367804189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2367804189
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1910970965
Short name T98
Test name
Test status
Simulation time 2170764593 ps
CPU time 14.33 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:26 PM PDT 24
Peak memory 251000 kb
Host smart-364460cc-525f-419d-bf22-d4fa61f63b67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910970965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1910970965
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1509679213
Short name T836
Test name
Test status
Simulation time 256970599 ps
CPU time 3.59 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:21 PM PDT 24
Peak memory 218288 kb
Host smart-9bc12679-5ebb-4cc9-82c8-4853cffc033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509679213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1509679213
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3456443743
Short name T237
Test name
Test status
Simulation time 259798451 ps
CPU time 8.33 seconds
Started May 09 01:14:11 PM PDT 24
Finished May 09 01:14:21 PM PDT 24
Peak memory 226180 kb
Host smart-010d91f6-e7d3-419d-8013-5f13b47d8b3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456443743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3456443743
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2250670850
Short name T1
Test name
Test status
Simulation time 4797209062 ps
CPU time 17.14 seconds
Started May 09 01:14:08 PM PDT 24
Finished May 09 01:14:27 PM PDT 24
Peak memory 218668 kb
Host smart-aaff7b52-4111-4c44-80bc-bf28bb41e3e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250670850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2250670850
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1886807057
Short name T634
Test name
Test status
Simulation time 3004906861 ps
CPU time 7.46 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:22 PM PDT 24
Peak memory 218332 kb
Host smart-3755f910-8996-4710-8863-87a52b76d3ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886807057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1886807057
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1254703124
Short name T842
Test name
Test status
Simulation time 250308160 ps
CPU time 9.4 seconds
Started May 09 01:14:09 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 218100 kb
Host smart-fc80aea9-3b46-432e-adf7-a02a904c5f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254703124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1254703124
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3885952061
Short name T613
Test name
Test status
Simulation time 62393094 ps
CPU time 1.65 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:16 PM PDT 24
Peak memory 213780 kb
Host smart-69e4e2f4-23ac-4bdd-867b-d34ca16f1707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885952061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3885952061
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2005686156
Short name T192
Test name
Test status
Simulation time 259055323 ps
CPU time 27 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:39 PM PDT 24
Peak memory 251176 kb
Host smart-b7806acf-f812-4dab-ae38-5973f5c00482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005686156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2005686156
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.149662771
Short name T240
Test name
Test status
Simulation time 163188681 ps
CPU time 7.39 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:22 PM PDT 24
Peak memory 251160 kb
Host smart-c169659a-9afe-4517-93c1-730b585851a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149662771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.149662771
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1128220530
Short name T793
Test name
Test status
Simulation time 9226471018 ps
CPU time 226.78 seconds
Started May 09 01:14:12 PM PDT 24
Finished May 09 01:18:00 PM PDT 24
Peak memory 273048 kb
Host smart-5b59357d-9f13-41a5-b7de-431d8463484a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128220530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1128220530
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2868643368
Short name T169
Test name
Test status
Simulation time 18378772669 ps
CPU time 331.1 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:19:43 PM PDT 24
Peak memory 282972 kb
Host smart-8b7a6a71-413b-42bc-a6e4-d295da1593d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2868643368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2868643368
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3167066751
Short name T612
Test name
Test status
Simulation time 66667144 ps
CPU time 0.9 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 211796 kb
Host smart-a0b1c70e-0326-44ed-8206-202789e227aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167066751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3167066751
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3093664819
Short name T373
Test name
Test status
Simulation time 20838612 ps
CPU time 1.18 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:23 PM PDT 24
Peak memory 209744 kb
Host smart-7a23fa5d-e4e1-47e7-8cb7-ba49ac9a5b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093664819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3093664819
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3236203029
Short name T461
Test name
Test status
Simulation time 5676383027 ps
CPU time 16.9 seconds
Started May 09 01:14:12 PM PDT 24
Finished May 09 01:14:31 PM PDT 24
Peak memory 219236 kb
Host smart-fe901780-4212-4a86-ab1c-71e2e10ece4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236203029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3236203029
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.554315582
Short name T730
Test name
Test status
Simulation time 3566041589 ps
CPU time 12.98 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 218016 kb
Host smart-975500a9-548a-48d6-a4cd-fe2cfb705dde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554315582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.554315582
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3594724932
Short name T685
Test name
Test status
Simulation time 1344845014 ps
CPU time 23.32 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:14:40 PM PDT 24
Peak memory 218144 kb
Host smart-c096b5ee-715f-45be-a705-1049b214d685
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594724932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3594724932
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.632268356
Short name T651
Test name
Test status
Simulation time 4041446156 ps
CPU time 14.92 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:30 PM PDT 24
Peak memory 219140 kb
Host smart-fc205705-04e1-4613-a8ec-b92223eeb1c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632268356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.632268356
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2082540236
Short name T5
Test name
Test status
Simulation time 1766922426 ps
CPU time 6.39 seconds
Started May 09 01:14:11 PM PDT 24
Finished May 09 01:14:19 PM PDT 24
Peak memory 213968 kb
Host smart-4dab45be-af78-4f2e-b594-03f30e1f9c6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082540236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2082540236
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3852004010
Short name T528
Test name
Test status
Simulation time 1069635162 ps
CPU time 38.76 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:54 PM PDT 24
Peak memory 251144 kb
Host smart-ca55779e-798f-4bb7-a366-b33adb24f664
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852004010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3852004010
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3705161643
Short name T573
Test name
Test status
Simulation time 2156410006 ps
CPU time 10.08 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:31 PM PDT 24
Peak memory 248420 kb
Host smart-3e1a10df-c159-4035-a071-ffce7ce533b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705161643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3705161643
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2014833115
Short name T711
Test name
Test status
Simulation time 48985041 ps
CPU time 2.84 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 218220 kb
Host smart-74c96f0c-e75f-45d5-8a65-f22993942d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014833115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2014833115
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3998095525
Short name T852
Test name
Test status
Simulation time 285496256 ps
CPU time 9.3 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 226324 kb
Host smart-d7b753d4-81f5-46ab-b60c-6f125249d3da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998095525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3998095525
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1671404692
Short name T340
Test name
Test status
Simulation time 226897969 ps
CPU time 7.63 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:32 PM PDT 24
Peak memory 218316 kb
Host smart-7b5503b3-d056-4747-a099-174e00044bd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671404692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1671404692
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3694268122
Short name T539
Test name
Test status
Simulation time 1562326611 ps
CPU time 9.7 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 218200 kb
Host smart-332854f6-0a3e-4e2f-b0b4-a5e96bfb4beb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694268122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3694268122
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.447547570
Short name T431
Test name
Test status
Simulation time 1916962471 ps
CPU time 11.9 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:24 PM PDT 24
Peak memory 218260 kb
Host smart-8881e7ed-ca74-4044-8eb7-f92e97a0ffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447547570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.447547570
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3202468454
Short name T378
Test name
Test status
Simulation time 25524636 ps
CPU time 1.13 seconds
Started May 09 01:14:11 PM PDT 24
Finished May 09 01:14:14 PM PDT 24
Peak memory 218124 kb
Host smart-285192c4-3259-4382-b4e9-fa49e3963f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202468454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3202468454
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3087196792
Short name T609
Test name
Test status
Simulation time 907943168 ps
CPU time 17.94 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 251100 kb
Host smart-8678988b-3716-46e8-aae3-44ac17f1a67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087196792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3087196792
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3357295097
Short name T702
Test name
Test status
Simulation time 389058538 ps
CPU time 3.36 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 226576 kb
Host smart-864e01f9-e4b2-445e-a8bb-6df089f2bd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357295097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3357295097
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.904353169
Short name T370
Test name
Test status
Simulation time 94947587 ps
CPU time 0.92 seconds
Started May 09 01:14:10 PM PDT 24
Finished May 09 01:14:13 PM PDT 24
Peak memory 211824 kb
Host smart-0f7eae75-c719-4129-b236-a3e7ccbdf81c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904353169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.904353169
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2682940659
Short name T344
Test name
Test status
Simulation time 98475584 ps
CPU time 0.94 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 209800 kb
Host smart-c6b4b226-42e9-4ef8-a517-77d87da3034a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682940659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2682940659
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.4207769498
Short name T345
Test name
Test status
Simulation time 1191852381 ps
CPU time 13.92 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:38 PM PDT 24
Peak memory 218288 kb
Host smart-13a15957-7ea6-4025-b1df-826b52bdf810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207769498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.4207769498
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1535071160
Short name T507
Test name
Test status
Simulation time 169873096 ps
CPU time 4.84 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:28 PM PDT 24
Peak memory 217064 kb
Host smart-146e7fd6-88f9-4f72-8868-c3edb94764ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535071160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1535071160
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.505064155
Short name T194
Test name
Test status
Simulation time 6018375434 ps
CPU time 25.28 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:49 PM PDT 24
Peak memory 218416 kb
Host smart-29c720f4-41ea-4c69-9565-cb10e76b2290
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505064155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.505064155
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.658151828
Short name T588
Test name
Test status
Simulation time 3161306021 ps
CPU time 12.36 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 218188 kb
Host smart-57b06fb2-e72e-45d4-8177-44ea0fc0f04a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658151828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.658151828
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.329954034
Short name T690
Test name
Test status
Simulation time 319788772 ps
CPU time 8.54 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:26 PM PDT 24
Peak memory 213864 kb
Host smart-c381ff8a-5b55-41e7-ace3-d08f33bf8962
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329954034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
329954034
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.488427328
Short name T242
Test name
Test status
Simulation time 1767035026 ps
CPU time 66.75 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:15:31 PM PDT 24
Peak memory 275736 kb
Host smart-b20e01e4-b0d9-4749-8e20-9f6ca09ffeaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488427328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.488427328
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1331626015
Short name T813
Test name
Test status
Simulation time 272050991 ps
CPU time 9.1 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 250816 kb
Host smart-d3e53cd0-623c-4da3-9faa-fe3dbf803920
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331626015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1331626015
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2602416063
Short name T313
Test name
Test status
Simulation time 90845618 ps
CPU time 2.97 seconds
Started May 09 01:14:16 PM PDT 24
Finished May 09 01:14:21 PM PDT 24
Peak memory 218232 kb
Host smart-d64b92f9-8258-4383-b02b-e0c40615fdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602416063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2602416063
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3602528206
Short name T628
Test name
Test status
Simulation time 530185398 ps
CPU time 15.88 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:40 PM PDT 24
Peak memory 226328 kb
Host smart-be0885b7-88a6-4175-bde8-74796b19ba30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602528206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3602528206
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1314836403
Short name T31
Test name
Test status
Simulation time 503790062 ps
CPU time 11.19 seconds
Started May 09 01:14:15 PM PDT 24
Finished May 09 01:14:29 PM PDT 24
Peak memory 218244 kb
Host smart-e76445f2-e0d2-4edf-a39c-b9848e5a2747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314836403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1314836403
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3813740533
Short name T818
Test name
Test status
Simulation time 843697915 ps
CPU time 7.83 seconds
Started May 09 01:14:12 PM PDT 24
Finished May 09 01:14:21 PM PDT 24
Peak memory 218256 kb
Host smart-d69da615-4d72-478a-b170-73bffd58c4dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813740533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3813740533
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1691094760
Short name T321
Test name
Test status
Simulation time 748101841 ps
CPU time 10.06 seconds
Started May 09 01:14:16 PM PDT 24
Finished May 09 01:14:28 PM PDT 24
Peak memory 218372 kb
Host smart-25115058-3716-452f-9707-51823eaa1377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691094760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1691094760
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1803916524
Short name T259
Test name
Test status
Simulation time 23291713 ps
CPU time 1.05 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 213124 kb
Host smart-50154fdd-5947-40d1-adcb-564becfb4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803916524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1803916524
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3391851523
Short name T275
Test name
Test status
Simulation time 783255144 ps
CPU time 19 seconds
Started May 09 01:14:16 PM PDT 24
Finished May 09 01:14:37 PM PDT 24
Peak memory 251216 kb
Host smart-503d3173-6745-4845-8cd9-7bac02144b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391851523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3391851523
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3732047696
Short name T230
Test name
Test status
Simulation time 243381541 ps
CPU time 6.31 seconds
Started May 09 01:14:14 PM PDT 24
Finished May 09 01:14:22 PM PDT 24
Peak memory 250792 kb
Host smart-6c0715b3-ee64-42d8-b0af-199c182a34b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732047696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3732047696
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2869366585
Short name T354
Test name
Test status
Simulation time 32966586720 ps
CPU time 370.14 seconds
Started May 09 01:14:09 PM PDT 24
Finished May 09 01:20:21 PM PDT 24
Peak memory 276044 kb
Host smart-227612c1-5793-451d-bce3-50d046f54324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869366585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2869366585
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3870340760
Short name T700
Test name
Test status
Simulation time 24261762976 ps
CPU time 207.81 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:17:52 PM PDT 24
Peak memory 300432 kb
Host smart-3deff995-738b-4faf-9489-4d25287dd330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3870340760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3870340760
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.83634649
Short name T652
Test name
Test status
Simulation time 15028663 ps
CPU time 0.82 seconds
Started May 09 01:14:09 PM PDT 24
Finished May 09 01:14:12 PM PDT 24
Peak memory 208748 kb
Host smart-0fa8b576-df04-4564-b27e-b1676664e7fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83634649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_volatile_unlock_smoke.83634649
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1395253725
Short name T325
Test name
Test status
Simulation time 58889556 ps
CPU time 1.03 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 209776 kb
Host smart-da97093e-b240-4066-9531-ba9845959870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395253725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1395253725
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2816128137
Short name T647
Test name
Test status
Simulation time 1432612249 ps
CPU time 17.13 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:14:42 PM PDT 24
Peak memory 218288 kb
Host smart-7543353c-6e27-494e-92b8-54c1c5e6b3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816128137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2816128137
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.580068655
Short name T795
Test name
Test status
Simulation time 3101342708 ps
CPU time 19.19 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:42 PM PDT 24
Peak memory 209920 kb
Host smart-c0392d96-348a-4043-aaa0-56cce9eb1f44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580068655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.580068655
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.71655694
Short name T496
Test name
Test status
Simulation time 3812262121 ps
CPU time 55 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:15:18 PM PDT 24
Peak memory 220184 kb
Host smart-fe68f384-1aa1-4d8b-ba0a-4a9abd0bffe9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71655694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_err
ors.71655694
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3940964543
Short name T524
Test name
Test status
Simulation time 710577097 ps
CPU time 7.68 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:31 PM PDT 24
Peak memory 218208 kb
Host smart-8e6b64fc-7dfd-4a7c-b3d9-758a31fde80a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940964543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3940964543
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3051916847
Short name T229
Test name
Test status
Simulation time 651666642 ps
CPU time 5.47 seconds
Started May 09 01:14:22 PM PDT 24
Finished May 09 01:14:30 PM PDT 24
Peak memory 213612 kb
Host smart-162c24a0-d470-4a61-812b-0489dccc3aec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051916847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3051916847
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3451194137
Short name T335
Test name
Test status
Simulation time 2131809593 ps
CPU time 49.38 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:15:14 PM PDT 24
Peak memory 251112 kb
Host smart-a74021f3-ac22-47d8-a9a3-adc5d6463529
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451194137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3451194137
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1962915473
Short name T296
Test name
Test status
Simulation time 746007701 ps
CPU time 11.83 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 251028 kb
Host smart-145a24d9-eb4c-4847-88ce-1ccb39972a3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962915473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1962915473
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4177326626
Short name T876
Test name
Test status
Simulation time 69184807 ps
CPU time 3.51 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:27 PM PDT 24
Peak memory 218248 kb
Host smart-622a2426-c445-48f8-b49c-27a73eed813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177326626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4177326626
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3912842148
Short name T179
Test name
Test status
Simulation time 415740395 ps
CPU time 13.31 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:14:38 PM PDT 24
Peak memory 226284 kb
Host smart-00e14506-e749-4ee3-b4ea-2f8bd701d4e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912842148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3912842148
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1273695491
Short name T424
Test name
Test status
Simulation time 1948977551 ps
CPU time 14.03 seconds
Started May 09 01:14:22 PM PDT 24
Finished May 09 01:14:39 PM PDT 24
Peak memory 218292 kb
Host smart-d7ebbe5c-7636-4d02-9622-695e9ac4b62a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273695491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1273695491
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.476329772
Short name T805
Test name
Test status
Simulation time 208761812 ps
CPU time 8.65 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 218236 kb
Host smart-5d0eab47-3fda-4be6-9792-f758f8475b09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476329772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.476329772
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2544842023
Short name T454
Test name
Test status
Simulation time 367490171 ps
CPU time 14.9 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:39 PM PDT 24
Peak memory 218328 kb
Host smart-fadd5c15-6131-4eca-adc6-296a74645816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544842023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2544842023
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1777506655
Short name T695
Test name
Test status
Simulation time 87762597 ps
CPU time 1.43 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:24 PM PDT 24
Peak memory 218136 kb
Host smart-e1c5b43b-63c6-406f-8c2e-1a74f408339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777506655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1777506655
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2840016404
Short name T777
Test name
Test status
Simulation time 605655776 ps
CPU time 25.21 seconds
Started May 09 01:14:13 PM PDT 24
Finished May 09 01:14:40 PM PDT 24
Peak memory 251156 kb
Host smart-27501196-50c1-4542-a1d0-c0f2cfc0dd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840016404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2840016404
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1572771598
Short name T565
Test name
Test status
Simulation time 292271015 ps
CPU time 7.7 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:32 PM PDT 24
Peak memory 251024 kb
Host smart-87d05489-d90e-4e27-82a1-a133786d39fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572771598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1572771598
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2936729705
Short name T198
Test name
Test status
Simulation time 5476122028 ps
CPU time 193.29 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:17:35 PM PDT 24
Peak memory 226396 kb
Host smart-081a71be-2460-4272-916e-3c20d8428dd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936729705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2936729705
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2198540172
Short name T146
Test name
Test status
Simulation time 44136968114 ps
CPU time 198.56 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:17:43 PM PDT 24
Peak memory 259608 kb
Host smart-1a305e6b-e9c4-4099-9d1d-5153fc344458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2198540172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2198540172
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2372764035
Short name T742
Test name
Test status
Simulation time 33292568 ps
CPU time 0.94 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:24 PM PDT 24
Peak memory 213008 kb
Host smart-3c5cd7a8-1fe5-4810-9687-60601b019582
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372764035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2372764035
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3535842921
Short name T561
Test name
Test status
Simulation time 217586120 ps
CPU time 0.9 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:13:16 PM PDT 24
Peak memory 209736 kb
Host smart-eba2d20a-cda4-45f2-92e0-2c3ca7e782b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535842921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3535842921
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2361397131
Short name T579
Test name
Test status
Simulation time 946981264 ps
CPU time 12.74 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:29 PM PDT 24
Peak memory 218192 kb
Host smart-0ccb5d02-2f7b-448a-8968-4f69893a4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361397131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2361397131
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1561057968
Short name T745
Test name
Test status
Simulation time 2644803905 ps
CPU time 5.21 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:13:20 PM PDT 24
Peak memory 209812 kb
Host smart-3ee86610-29a5-41da-be31-6b7b2de687ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561057968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1561057968
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1419404880
Short name T289
Test name
Test status
Simulation time 4940669202 ps
CPU time 55.3 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 218720 kb
Host smart-17e0dffc-46a8-4864-a24e-c8cb16668fa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419404880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1419404880
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.4069130259
Short name T857
Test name
Test status
Simulation time 419463931 ps
CPU time 2.89 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:17 PM PDT 24
Peak memory 218004 kb
Host smart-ee92697f-4ef3-4020-84b9-c67929a23b52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069130259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.4
069130259
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2315278853
Short name T459
Test name
Test status
Simulation time 955711887 ps
CPU time 6.59 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:23 PM PDT 24
Peak memory 218264 kb
Host smart-fc17723b-878a-4844-8282-90957b6a1651
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315278853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2315278853
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.498683481
Short name T790
Test name
Test status
Simulation time 1416506716 ps
CPU time 38.97 seconds
Started May 09 01:13:17 PM PDT 24
Finished May 09 01:13:58 PM PDT 24
Peak memory 213876 kb
Host smart-73d4a0f7-c4ff-4f20-9c5e-d4157c2d705e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498683481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.498683481
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1096693311
Short name T80
Test name
Test status
Simulation time 156532813 ps
CPU time 2.82 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:18 PM PDT 24
Peak memory 213336 kb
Host smart-993d7c00-34a3-4352-942d-9b7875667b25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096693311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1096693311
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1618108089
Short name T512
Test name
Test status
Simulation time 1681597194 ps
CPU time 73.28 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:14:30 PM PDT 24
Peak memory 275020 kb
Host smart-e1e74f45-c3be-4445-802c-bf99efa9d3f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618108089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1618108089
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2037452462
Short name T556
Test name
Test status
Simulation time 1104058659 ps
CPU time 10.91 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:28 PM PDT 24
Peak memory 218044 kb
Host smart-1b0c9bf3-234e-4eda-a7d1-54fdf1821454
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037452462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2037452462
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.431348414
Short name T501
Test name
Test status
Simulation time 67669652 ps
CPU time 2.02 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:17 PM PDT 24
Peak memory 218220 kb
Host smart-00922f7d-34ad-4665-a136-43ae97adaf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431348414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.431348414
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.497473104
Short name T691
Test name
Test status
Simulation time 1977994794 ps
CPU time 12.76 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:29 PM PDT 24
Peak memory 218012 kb
Host smart-97f2f210-ffc0-4b96-a088-740d708022e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497473104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.497473104
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2952133197
Short name T101
Test name
Test status
Simulation time 539628706 ps
CPU time 23.34 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:39 PM PDT 24
Peak memory 281460 kb
Host smart-868a8b0b-28c0-4dae-9db9-b28773bbe5f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952133197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2952133197
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.33289779
Short name T308
Test name
Test status
Simulation time 262113691 ps
CPU time 9.8 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:26 PM PDT 24
Peak memory 226276 kb
Host smart-ec3ed9f1-e3f8-4946-8946-0fd45fa21fb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33289779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.33289779
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.616022473
Short name T866
Test name
Test status
Simulation time 473153780 ps
CPU time 12.6 seconds
Started May 09 01:13:16 PM PDT 24
Finished May 09 01:13:31 PM PDT 24
Peak memory 218484 kb
Host smart-6632f307-8fcd-453e-862f-9e727a597859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616022473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.616022473
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.55661494
Short name T93
Test name
Test status
Simulation time 208495737 ps
CPU time 8.07 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:22 PM PDT 24
Peak memory 218216 kb
Host smart-0bf51b6e-ad0c-4e3f-a27d-aa434348686a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55661494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.55661494
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2433726962
Short name T738
Test name
Test status
Simulation time 3043545948 ps
CPU time 10.81 seconds
Started May 09 01:13:17 PM PDT 24
Finished May 09 01:13:29 PM PDT 24
Peak memory 218612 kb
Host smart-b385112f-251d-442e-a108-0b10811aa1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433726962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2433726962
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.488209512
Short name T72
Test name
Test status
Simulation time 35152729 ps
CPU time 1.11 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:13:16 PM PDT 24
Peak memory 213392 kb
Host smart-3c50b28a-fe10-4d7a-b3d3-a056fa5caf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488209512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.488209512
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1830257086
Short name T585
Test name
Test status
Simulation time 1018269671 ps
CPU time 19.24 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:13:34 PM PDT 24
Peak memory 251112 kb
Host smart-6b2ae181-ad44-4dbb-acd9-a48345d03de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830257086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1830257086
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1807170412
Short name T254
Test name
Test status
Simulation time 181411173 ps
CPU time 4.58 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:21 PM PDT 24
Peak memory 226652 kb
Host smart-5a600133-8188-4acd-8936-4983242ff16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807170412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1807170412
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1635459300
Short name T366
Test name
Test status
Simulation time 16772685483 ps
CPU time 129.6 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:15:23 PM PDT 24
Peak memory 250848 kb
Host smart-a824020c-d391-4d52-ab82-7113fee916e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635459300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1635459300
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.987464467
Short name T299
Test name
Test status
Simulation time 31750777 ps
CPU time 0.99 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:17 PM PDT 24
Peak memory 208900 kb
Host smart-5c90b500-5513-42fa-863f-571d5769a6fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987464467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.987464467
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1450293081
Short name T604
Test name
Test status
Simulation time 53903784 ps
CPU time 1.12 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:23 PM PDT 24
Peak memory 209728 kb
Host smart-d1986ea1-ae1d-45d9-b155-72423291dd4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450293081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1450293081
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2807873931
Short name T743
Test name
Test status
Simulation time 287775531 ps
CPU time 13.61 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:37 PM PDT 24
Peak memory 218236 kb
Host smart-05344e42-4263-479f-b471-9044a451d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807873931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2807873931
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2278495835
Short name T26
Test name
Test status
Simulation time 698497662 ps
CPU time 3.27 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:26 PM PDT 24
Peak memory 209676 kb
Host smart-2e3341ac-08c9-4f0d-909e-751d816307a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278495835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2278495835
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2635743095
Short name T576
Test name
Test status
Simulation time 170762283 ps
CPU time 2.35 seconds
Started May 09 01:14:26 PM PDT 24
Finished May 09 01:14:29 PM PDT 24
Peak memory 218068 kb
Host smart-cb3ed2ad-c5e9-49db-bc15-80a75e570bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635743095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2635743095
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3432809160
Short name T720
Test name
Test status
Simulation time 536435511 ps
CPU time 11.41 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 226340 kb
Host smart-2f98ad17-00c5-4eed-92b5-02b5e27026b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432809160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3432809160
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.145932700
Short name T156
Test name
Test status
Simulation time 1698569499 ps
CPU time 14.73 seconds
Started May 09 01:14:17 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 218276 kb
Host smart-6e220c5a-f8bf-4f3a-94e3-4e66feb74b6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145932700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.145932700
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.480038329
Short name T616
Test name
Test status
Simulation time 344350803 ps
CPU time 10.19 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 218284 kb
Host smart-853c48c8-2c84-4d39-9b62-0c345a434478
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480038329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.480038329
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1718728440
Short name T600
Test name
Test status
Simulation time 210439688 ps
CPU time 6.94 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:30 PM PDT 24
Peak memory 218280 kb
Host smart-5580dc8f-85a1-4c04-8ed1-ecb7e3e6e28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718728440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1718728440
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3254922128
Short name T740
Test name
Test status
Simulation time 20506216 ps
CPU time 1.2 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:24 PM PDT 24
Peak memory 213628 kb
Host smart-438e4d09-f4d4-4589-8f47-aee599626b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254922128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3254922128
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3489405215
Short name T339
Test name
Test status
Simulation time 247261342 ps
CPU time 25.63 seconds
Started May 09 01:14:24 PM PDT 24
Finished May 09 01:14:52 PM PDT 24
Peak memory 245820 kb
Host smart-b9ab0672-249b-47db-8ce9-ac8799b10ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489405215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3489405215
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3842003091
Short name T465
Test name
Test status
Simulation time 211167380 ps
CPU time 6.95 seconds
Started May 09 01:14:26 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 246088 kb
Host smart-a2517133-6c85-43d5-905b-b6ef07a916f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842003091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3842003091
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.203653984
Short name T704
Test name
Test status
Simulation time 3312829570 ps
CPU time 48.42 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:15:11 PM PDT 24
Peak memory 226380 kb
Host smart-1e3226f1-becb-4aa6-9fc1-dde6f5fe5ecf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203653984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.203653984
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4182543732
Short name T166
Test name
Test status
Simulation time 17217111 ps
CPU time 1.06 seconds
Started May 09 01:14:20 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 213032 kb
Host smart-638eaa68-e9d6-41b2-aa12-1169b84afe43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182543732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.4182543732
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3778089371
Short name T318
Test name
Test status
Simulation time 13562567 ps
CPU time 1.05 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:23 PM PDT 24
Peak memory 209804 kb
Host smart-54704f27-4941-4350-84a7-0befd2f23c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778089371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3778089371
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.670960621
Short name T457
Test name
Test status
Simulation time 1044963567 ps
CPU time 10.86 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 218228 kb
Host smart-08e8e034-ff7a-434f-a5b0-0be4e0628cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670960621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.670960621
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4106155029
Short name T553
Test name
Test status
Simulation time 2620128729 ps
CPU time 16.9 seconds
Started May 09 01:14:22 PM PDT 24
Finished May 09 01:14:42 PM PDT 24
Peak memory 209848 kb
Host smart-6b4db725-ab53-4064-bb6d-68fa88fe2f66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106155029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4106155029
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2525838021
Short name T317
Test name
Test status
Simulation time 53737092 ps
CPU time 2.15 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 218172 kb
Host smart-b82519ab-fbdf-4efb-abd9-bc57161843fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525838021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2525838021
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1180468955
Short name T701
Test name
Test status
Simulation time 430939064 ps
CPU time 8.92 seconds
Started May 09 01:14:22 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 218236 kb
Host smart-fbea1968-9c53-4bc5-8707-d0465e8ebca3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180468955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1180468955
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2427998322
Short name T649
Test name
Test status
Simulation time 1091829151 ps
CPU time 18.6 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:14:43 PM PDT 24
Peak memory 218260 kb
Host smart-8e808494-559a-4b73-8c0c-691fb28c39aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427998322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2427998322
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3053476891
Short name T593
Test name
Test status
Simulation time 1246730748 ps
CPU time 9.9 seconds
Started May 09 01:14:22 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 218276 kb
Host smart-36bf7864-7b3c-4c21-b78a-97748ba63b5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053476891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3053476891
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3021537910
Short name T629
Test name
Test status
Simulation time 1014663879 ps
CPU time 7.41 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:14:32 PM PDT 24
Peak memory 218352 kb
Host smart-a4d5b3c2-e4b2-4b9e-805b-d1b463f5c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021537910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3021537910
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3638083234
Short name T380
Test name
Test status
Simulation time 34294422 ps
CPU time 2.06 seconds
Started May 09 01:14:25 PM PDT 24
Finished May 09 01:14:28 PM PDT 24
Peak memory 218004 kb
Host smart-56fde969-4eae-4afc-aabd-0bf40656630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638083234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3638083234
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1334082977
Short name T437
Test name
Test status
Simulation time 1838685552 ps
CPU time 27.79 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:50 PM PDT 24
Peak memory 251168 kb
Host smart-cfa1954b-4c78-4a19-b01f-064c65896d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334082977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1334082977
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1522926840
Short name T786
Test name
Test status
Simulation time 51710905 ps
CPU time 8.68 seconds
Started May 09 01:14:18 PM PDT 24
Finished May 09 01:14:30 PM PDT 24
Peak memory 250956 kb
Host smart-e093df61-f854-490a-948f-63b7fbe03121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522926840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1522926840
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1787991665
Short name T736
Test name
Test status
Simulation time 764153983 ps
CPU time 30.36 seconds
Started May 09 01:14:26 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 219364 kb
Host smart-6f298aec-bf54-444a-9ff8-cdb032938745
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787991665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1787991665
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3490596822
Short name T411
Test name
Test status
Simulation time 29058335 ps
CPU time 0.74 seconds
Started May 09 01:14:21 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 207432 kb
Host smart-8412a95d-e7fe-4055-a580-549f1854f0dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490596822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3490596822
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3463392371
Short name T877
Test name
Test status
Simulation time 295551640 ps
CPU time 1.18 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:14:38 PM PDT 24
Peak memory 209812 kb
Host smart-ec1aae1b-1436-46f1-9303-ded7cff19c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463392371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3463392371
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3820715775
Short name T346
Test name
Test status
Simulation time 523265247 ps
CPU time 10.44 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 218152 kb
Host smart-7dd7e800-0699-4efb-8997-9fcb8661a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820715775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3820715775
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3119131800
Short name T517
Test name
Test status
Simulation time 847259994 ps
CPU time 5.78 seconds
Started May 09 01:14:29 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 209716 kb
Host smart-a44361f9-5485-40e5-b546-b10b9bc5f90a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119131800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3119131800
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2299423502
Short name T381
Test name
Test status
Simulation time 69552235 ps
CPU time 3.36 seconds
Started May 09 01:14:37 PM PDT 24
Finished May 09 01:14:42 PM PDT 24
Peak memory 218272 kb
Host smart-b1d21cc0-b937-4ff9-80bc-6b96969d8c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299423502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2299423502
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3898455076
Short name T771
Test name
Test status
Simulation time 1357208581 ps
CPU time 16.42 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:50 PM PDT 24
Peak memory 218188 kb
Host smart-07bf6004-f814-434b-9470-612f97aa988f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898455076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3898455076
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3109120779
Short name T794
Test name
Test status
Simulation time 632077602 ps
CPU time 9.71 seconds
Started May 09 01:14:32 PM PDT 24
Finished May 09 01:14:44 PM PDT 24
Peak memory 218204 kb
Host smart-5f2d2da4-08e0-415c-80c8-e2b0d21cce8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109120779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3109120779
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2345102412
Short name T95
Test name
Test status
Simulation time 284829706 ps
CPU time 7.95 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:41 PM PDT 24
Peak memory 218308 kb
Host smart-59e4e9c2-aa98-49ac-ba28-5e170ba02f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345102412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2345102412
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3468025525
Short name T352
Test name
Test status
Simulation time 158617538 ps
CPU time 2.76 seconds
Started May 09 01:14:19 PM PDT 24
Finished May 09 01:14:25 PM PDT 24
Peak memory 218004 kb
Host smart-1699b16f-375a-4dba-b905-89397130a3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468025525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3468025525
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1763764787
Short name T569
Test name
Test status
Simulation time 248280725 ps
CPU time 26.32 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:15:04 PM PDT 24
Peak memory 251196 kb
Host smart-23c8a07e-9484-4560-a332-badddce591a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763764787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1763764787
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.312811034
Short name T802
Test name
Test status
Simulation time 87137734 ps
CPU time 8.95 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:43 PM PDT 24
Peak memory 251200 kb
Host smart-16935dec-ae9e-4d72-8547-421bc4c3fb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312811034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.312811034
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.511944298
Short name T92
Test name
Test status
Simulation time 54451395962 ps
CPU time 322.43 seconds
Started May 09 01:14:32 PM PDT 24
Finished May 09 01:19:56 PM PDT 24
Peak memory 278016 kb
Host smart-6c1af54e-de38-4597-b6d8-1ddab9d2407e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511944298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.511944298
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1512290787
Short name T102
Test name
Test status
Simulation time 28416111017 ps
CPU time 471.74 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:22:28 PM PDT 24
Peak memory 333232 kb
Host smart-110fdada-5706-4284-ab8b-a6be04483fc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1512290787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1512290787
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3169027599
Short name T737
Test name
Test status
Simulation time 16478134 ps
CPU time 0.86 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 208888 kb
Host smart-668275a7-6ae3-49e0-a213-8f6bc36083a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169027599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3169027599
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.933445625
Short name T760
Test name
Test status
Simulation time 25312800 ps
CPU time 1.05 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:14:37 PM PDT 24
Peak memory 209792 kb
Host smart-08a866e9-5fab-4f37-816c-70b9cadd47fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933445625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.933445625
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.4227011293
Short name T631
Test name
Test status
Simulation time 321771431 ps
CPU time 14.92 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 218108 kb
Host smart-1a56df1f-e91a-45d5-8113-b4c7f80e73f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227011293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4227011293
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2157887477
Short name T199
Test name
Test status
Simulation time 467193395 ps
CPU time 12.34 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 209824 kb
Host smart-5d635ea0-be02-4d4e-8d6d-4171f892b108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157887477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2157887477
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1105279792
Short name T319
Test name
Test status
Simulation time 59711868 ps
CPU time 1.71 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:37 PM PDT 24
Peak memory 218056 kb
Host smart-6c7dffca-a0d8-4a9c-8993-ce77e1749233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105279792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1105279792
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1543348737
Short name T157
Test name
Test status
Simulation time 1888807477 ps
CPU time 14.42 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:49 PM PDT 24
Peak memory 226196 kb
Host smart-54a4f2f7-133d-47db-ab38-1a88b7625bd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543348737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1543348737
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3311974606
Short name T525
Test name
Test status
Simulation time 197690952 ps
CPU time 8.45 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:43 PM PDT 24
Peak memory 218284 kb
Host smart-dde58b53-c8e4-4b7e-b4d3-3bba0e70e894
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311974606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3311974606
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2035131284
Short name T598
Test name
Test status
Simulation time 2433074590 ps
CPU time 13.78 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:49 PM PDT 24
Peak memory 218232 kb
Host smart-06663fd6-345a-4a6d-a0d0-f903ad82c865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035131284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2035131284
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1043979943
Short name T55
Test name
Test status
Simulation time 1451662286 ps
CPU time 9.78 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 218300 kb
Host smart-cf3e7b76-acbe-4b30-8cbb-e994d46003e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043979943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1043979943
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1064716877
Short name T306
Test name
Test status
Simulation time 142330350 ps
CPU time 2.16 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 213984 kb
Host smart-30d2050e-321c-4ab8-ad9c-b15eb16b7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064716877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1064716877
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1311556421
Short name T674
Test name
Test status
Simulation time 258729451 ps
CPU time 30.94 seconds
Started May 09 01:14:34 PM PDT 24
Finished May 09 01:15:06 PM PDT 24
Peak memory 248940 kb
Host smart-99fd6794-9c9e-4717-bbe4-3dd0c49e0eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311556421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1311556421
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.422245121
Short name T246
Test name
Test status
Simulation time 70402369 ps
CPU time 8.18 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:46 PM PDT 24
Peak memory 251032 kb
Host smart-668db78d-82d0-40c0-822f-6e082deedbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422245121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.422245121
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2339680733
Short name T787
Test name
Test status
Simulation time 10678287689 ps
CPU time 68 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 271404 kb
Host smart-02076982-f775-433d-bd31-98fb6873b58e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339680733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2339680733
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.336609847
Short name T314
Test name
Test status
Simulation time 12546529 ps
CPU time 0.79 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:36 PM PDT 24
Peak memory 209068 kb
Host smart-8f986266-920a-4ed8-a2e7-b89d2656e720
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336609847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.336609847
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2995101065
Short name T497
Test name
Test status
Simulation time 17044163 ps
CPU time 0.9 seconds
Started May 09 01:14:32 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 209780 kb
Host smart-bb0d8955-951c-4fe5-a42f-d52612d7bdee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995101065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2995101065
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2358294151
Short name T171
Test name
Test status
Simulation time 261870150 ps
CPU time 11.06 seconds
Started May 09 01:14:34 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 218220 kb
Host smart-a34b8210-530e-4966-b357-09a9d76cecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358294151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2358294151
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1972641309
Short name T451
Test name
Test status
Simulation time 930120269 ps
CPU time 13.2 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:46 PM PDT 24
Peak memory 209804 kb
Host smart-1c6f66b4-b7f1-4447-a446-b1b6fd1502c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972641309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1972641309
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2799224329
Short name T823
Test name
Test status
Simulation time 344276960 ps
CPU time 3.28 seconds
Started May 09 01:14:34 PM PDT 24
Finished May 09 01:14:39 PM PDT 24
Peak memory 218208 kb
Host smart-655cc711-6941-431d-877a-88e362c597fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799224329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2799224329
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.539866952
Short name T635
Test name
Test status
Simulation time 819834463 ps
CPU time 16.93 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:50 PM PDT 24
Peak memory 218388 kb
Host smart-62be0a72-810e-427d-9d50-fe6d5b697c09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539866952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.539866952
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1865650340
Short name T220
Test name
Test status
Simulation time 1317777714 ps
CPU time 12.41 seconds
Started May 09 01:14:30 PM PDT 24
Finished May 09 01:14:43 PM PDT 24
Peak memory 218228 kb
Host smart-6253630e-dcf1-4bcb-ac67-d261cdec8996
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865650340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1865650340
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.924310052
Short name T632
Test name
Test status
Simulation time 1206530867 ps
CPU time 9.68 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:42 PM PDT 24
Peak memory 218308 kb
Host smart-d916845a-4cf2-4624-aca2-c3be459b3086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924310052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.924310052
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1522253761
Short name T382
Test name
Test status
Simulation time 252200144 ps
CPU time 10.7 seconds
Started May 09 01:14:32 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 218304 kb
Host smart-3c4ee202-bdde-49e2-96bc-d100e9cb8b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522253761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1522253761
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1273106739
Short name T82
Test name
Test status
Simulation time 37280247 ps
CPU time 2.03 seconds
Started May 09 01:14:30 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 218004 kb
Host smart-01cb3cad-b148-4f97-94c4-1d4fe265315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273106739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1273106739
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1232799085
Short name T826
Test name
Test status
Simulation time 1059400038 ps
CPU time 23.9 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 251256 kb
Host smart-c9a4dbb0-9010-4962-93a1-dbd8d926defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232799085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1232799085
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3485639227
Short name T87
Test name
Test status
Simulation time 281723990 ps
CPU time 6.26 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:44 PM PDT 24
Peak memory 246072 kb
Host smart-1fef9d64-ec8a-4fd6-a1b7-8e87b5fc7680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485639227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3485639227
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1877584032
Short name T274
Test name
Test status
Simulation time 6150204049 ps
CPU time 67.18 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 268024 kb
Host smart-e3bfd08a-7b78-432b-b56e-1b08203c63b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877584032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1877584032
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3369925222
Short name T810
Test name
Test status
Simulation time 12313217 ps
CPU time 0.97 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 208900 kb
Host smart-c9141bf4-d283-4e79-a19f-9283f47f4db0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369925222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3369925222
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1078019613
Short name T739
Test name
Test status
Simulation time 177935674 ps
CPU time 0.99 seconds
Started May 09 01:14:32 PM PDT 24
Finished May 09 01:14:35 PM PDT 24
Peak memory 209896 kb
Host smart-f7f5a0f8-2289-40e7-b985-a244630637a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078019613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1078019613
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1744154065
Short name T769
Test name
Test status
Simulation time 946558831 ps
CPU time 7.6 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 218292 kb
Host smart-21f38fc3-4574-4286-a07b-43bbfe41e77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744154065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1744154065
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1522282951
Short name T733
Test name
Test status
Simulation time 437093982 ps
CPU time 6.1 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:14:43 PM PDT 24
Peak memory 217248 kb
Host smart-015c5635-b296-4b6a-ac22-3bb2c9971556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522282951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1522282951
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2596839112
Short name T678
Test name
Test status
Simulation time 65982317 ps
CPU time 1.51 seconds
Started May 09 01:14:32 PM PDT 24
Finished May 09 01:14:36 PM PDT 24
Peak memory 218192 kb
Host smart-83a2231e-c851-4f3f-a12b-ef19b7f6d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596839112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2596839112
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2224355883
Short name T636
Test name
Test status
Simulation time 367434698 ps
CPU time 13.21 seconds
Started May 09 01:14:32 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 226348 kb
Host smart-9e72e4ef-07af-4365-ab26-651b4ae5f94c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224355883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2224355883
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1509638535
Short name T474
Test name
Test status
Simulation time 685256792 ps
CPU time 8.21 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 218224 kb
Host smart-e1fad6aa-e626-4cdd-a247-2f8ab5eb64df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509638535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1509638535
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4094488676
Short name T265
Test name
Test status
Simulation time 639520991 ps
CPU time 7 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:44 PM PDT 24
Peak memory 218224 kb
Host smart-524144e6-427e-44bd-bfee-6e8c709e96c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094488676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
4094488676
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4178629628
Short name T605
Test name
Test status
Simulation time 231928324 ps
CPU time 6.93 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 218232 kb
Host smart-0754fa72-ed16-4147-81b0-89ae79edf224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178629628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4178629628
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3850784818
Short name T433
Test name
Test status
Simulation time 453929117 ps
CPU time 2.31 seconds
Started May 09 01:14:30 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 214072 kb
Host smart-472a057b-9eae-4bbc-acb6-82ee90e735c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850784818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3850784818
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.63577550
Short name T515
Test name
Test status
Simulation time 438574075 ps
CPU time 24.72 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:59 PM PDT 24
Peak memory 250972 kb
Host smart-acc55a00-ac5c-412a-bb74-88ebce3d4fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63577550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.63577550
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3407472936
Short name T416
Test name
Test status
Simulation time 89438901 ps
CPU time 6.82 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:40 PM PDT 24
Peak memory 243024 kb
Host smart-6ed5687f-c2e6-4fa9-adc5-f0fbec7ee786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407472936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3407472936
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.253139080
Short name T304
Test name
Test status
Simulation time 9765793194 ps
CPU time 174.41 seconds
Started May 09 01:14:37 PM PDT 24
Finished May 09 01:17:33 PM PDT 24
Peak memory 288284 kb
Host smart-0cdc5d2d-6ea5-412c-b7e9-e70798a2a27d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253139080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.253139080
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1760881441
Short name T375
Test name
Test status
Simulation time 20947579 ps
CPU time 0.81 seconds
Started May 09 01:14:31 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 208788 kb
Host smart-7aca4d5e-80b1-4f1c-882d-b9422250816f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760881441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1760881441
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3185681143
Short name T757
Test name
Test status
Simulation time 57601158 ps
CPU time 2 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:46 PM PDT 24
Peak memory 209748 kb
Host smart-d501f5ff-1af1-4c06-a987-67aeedc9c23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185681143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3185681143
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1468114102
Short name T591
Test name
Test status
Simulation time 303488248 ps
CPU time 11.15 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:49 PM PDT 24
Peak memory 217968 kb
Host smart-1951ad04-8793-4d66-94d4-d2139826e803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468114102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1468114102
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3440970761
Short name T562
Test name
Test status
Simulation time 75887284 ps
CPU time 1.78 seconds
Started May 09 01:14:35 PM PDT 24
Finished May 09 01:14:39 PM PDT 24
Peak memory 209836 kb
Host smart-bcf596ef-f2e2-4526-99b7-95622dfeb584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440970761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3440970761
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3277551658
Short name T797
Test name
Test status
Simulation time 178583303 ps
CPU time 3.25 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:41 PM PDT 24
Peak memory 218352 kb
Host smart-56d5ddb0-59e7-48f7-a9c8-1e82fc01e819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277551658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3277551658
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3740594141
Short name T618
Test name
Test status
Simulation time 1013317278 ps
CPU time 10.33 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 219212 kb
Host smart-fe13a555-c61c-4c4c-bc98-14e7e25c2837
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740594141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3740594141
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2581936588
Short name T799
Test name
Test status
Simulation time 1980918013 ps
CPU time 12.63 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 218300 kb
Host smart-5dccfce0-2255-4300-905d-2329f6a4cc60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581936588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2581936588
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3806977494
Short name T439
Test name
Test status
Simulation time 306669703 ps
CPU time 11.89 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 218156 kb
Host smart-a6bcc78d-6b29-414c-b01e-00df49a311b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806977494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3806977494
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2592039062
Short name T835
Test name
Test status
Simulation time 384529056 ps
CPU time 13.67 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:51 PM PDT 24
Peak memory 218332 kb
Host smart-6e7ac845-e306-4c66-a063-cc74858e2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592039062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2592039062
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3934830825
Short name T859
Test name
Test status
Simulation time 93627556 ps
CPU time 1.88 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:40 PM PDT 24
Peak memory 214148 kb
Host smart-065f8535-cfa1-43d0-95b9-0efa03e24c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934830825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3934830825
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.612452472
Short name T753
Test name
Test status
Simulation time 168877514 ps
CPU time 19.78 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 250928 kb
Host smart-bb8d50d4-a7c8-4c0f-af01-195b9aba628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612452472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.612452472
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1020091323
Short name T266
Test name
Test status
Simulation time 293058796 ps
CPU time 6.82 seconds
Started May 09 01:14:36 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 251180 kb
Host smart-ee6e44db-2dd2-4856-bafe-a04992f604c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020091323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1020091323
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1096695898
Short name T361
Test name
Test status
Simulation time 12316259713 ps
CPU time 144.57 seconds
Started May 09 01:14:41 PM PDT 24
Finished May 09 01:17:08 PM PDT 24
Peak memory 276520 kb
Host smart-a8f44e73-b96d-4bae-accf-e0ca9463b77f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096695898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1096695898
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.592343856
Short name T94
Test name
Test status
Simulation time 39774100 ps
CPU time 0.87 seconds
Started May 09 01:14:33 PM PDT 24
Finished May 09 01:14:36 PM PDT 24
Peak memory 208904 kb
Host smart-94a14c4a-b111-44a1-9af1-065146cbc3d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592343856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.592343856
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2331840214
Short name T264
Test name
Test status
Simulation time 21351847 ps
CPU time 1.18 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:46 PM PDT 24
Peak memory 209704 kb
Host smart-d7ecc059-c974-465d-86a5-71d38c1ff3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331840214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2331840214
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2185225695
Short name T536
Test name
Test status
Simulation time 784884429 ps
CPU time 7.86 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:51 PM PDT 24
Peak memory 218188 kb
Host smart-db12a768-f58d-4050-b2dd-afb95be0b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185225695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2185225695
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1406593137
Short name T8
Test name
Test status
Simulation time 2473130345 ps
CPU time 3.52 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 209868 kb
Host smart-62af409b-0028-4658-88a9-fefb29b9c8bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406593137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1406593137
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4007919641
Short name T620
Test name
Test status
Simulation time 26803056 ps
CPU time 1.68 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 218124 kb
Host smart-6d22c30f-715b-4546-8aff-31affb3e452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007919641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4007919641
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3157003866
Short name T328
Test name
Test status
Simulation time 1906992433 ps
CPU time 12.81 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 226244 kb
Host smart-e8649d84-e38a-4157-9677-1c94b2216214
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157003866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3157003866
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1184436054
Short name T611
Test name
Test status
Simulation time 233986474 ps
CPU time 11.44 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 218208 kb
Host smart-3bf22cee-d721-42c2-ab61-653e410ef8de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184436054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1184436054
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1074031332
Short name T710
Test name
Test status
Simulation time 4743908688 ps
CPU time 15.67 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:15:00 PM PDT 24
Peak memory 218268 kb
Host smart-c1077da3-5e75-4b34-bad4-b942f8820448
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074031332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1074031332
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1892246334
Short name T307
Test name
Test status
Simulation time 2005609701 ps
CPU time 10.17 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 217980 kb
Host smart-66782115-ebbc-41fb-b83b-6268b00004b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892246334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1892246334
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3128540374
Short name T504
Test name
Test status
Simulation time 63454490 ps
CPU time 2.47 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 218072 kb
Host smart-72c78c8d-1b44-4df9-b9fb-390df7e53a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128540374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3128540374
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.141896517
Short name T36
Test name
Test status
Simulation time 1300241143 ps
CPU time 20.49 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:15:05 PM PDT 24
Peak memory 251216 kb
Host smart-95d0e485-741c-4005-84eb-ecc0bba17de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141896517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.141896517
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.393378363
Short name T353
Test name
Test status
Simulation time 61792868 ps
CPU time 7.7 seconds
Started May 09 01:14:45 PM PDT 24
Finished May 09 01:14:55 PM PDT 24
Peak memory 251220 kb
Host smart-6fddb13e-2843-4633-8f53-c80b788d2012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393378363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.393378363
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2878119018
Short name T401
Test name
Test status
Simulation time 19978208218 ps
CPU time 326.82 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:20:13 PM PDT 24
Peak memory 273732 kb
Host smart-ce7cf009-2268-476a-8ea8-2ee4070aaa0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878119018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2878119018
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1140648043
Short name T164
Test name
Test status
Simulation time 47732554 ps
CPU time 1.13 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 212824 kb
Host smart-4cc0a25d-71a5-48c8-ba31-803e80f96dda
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140648043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1140648043
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3232595518
Short name T640
Test name
Test status
Simulation time 27719475 ps
CPU time 0.83 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:46 PM PDT 24
Peak memory 209612 kb
Host smart-6d8a45c0-2db7-4646-8613-f3082efb53b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232595518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3232595518
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2026232425
Short name T801
Test name
Test status
Simulation time 1768787434 ps
CPU time 17.99 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:15:04 PM PDT 24
Peak memory 218128 kb
Host smart-6f6bfc73-306d-4ba6-8d8b-af8119f129d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026232425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2026232425
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2228628272
Short name T658
Test name
Test status
Simulation time 624106689 ps
CPU time 8.84 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 217300 kb
Host smart-f985a3d9-20e9-4601-81ef-518b9e657dce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228628272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2228628272
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3614179561
Short name T669
Test name
Test status
Simulation time 415657813 ps
CPU time 2.32 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 218188 kb
Host smart-09e71ce0-75a0-414f-82f6-b0b71b3e330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614179561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3614179561
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.564539935
Short name T564
Test name
Test status
Simulation time 354226226 ps
CPU time 10.74 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 218712 kb
Host smart-681a4f4b-8988-4c24-a82a-d12c94fcaa43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564539935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.564539935
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1595502493
Short name T182
Test name
Test status
Simulation time 642628435 ps
CPU time 12.98 seconds
Started May 09 01:14:41 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 218228 kb
Host smart-e6a24ded-43df-4a97-a003-f3ac0e710c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595502493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1595502493
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.858726386
Short name T376
Test name
Test status
Simulation time 313741746 ps
CPU time 11.6 seconds
Started May 09 01:14:41 PM PDT 24
Finished May 09 01:14:55 PM PDT 24
Peak memory 218224 kb
Host smart-37e038b5-12e3-43ed-83f6-9145650e22ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858726386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.858726386
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1435740100
Short name T767
Test name
Test status
Simulation time 1687340608 ps
CPU time 8.55 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:53 PM PDT 24
Peak memory 218300 kb
Host smart-cf377fee-1d77-4b75-81ed-eb4ea2dcda59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435740100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1435740100
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.739911686
Short name T358
Test name
Test status
Simulation time 51105468 ps
CPU time 2.9 seconds
Started May 09 01:14:41 PM PDT 24
Finished May 09 01:14:44 PM PDT 24
Peak memory 214476 kb
Host smart-94f66101-308d-41f9-b7f9-62c13f7abd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739911686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.739911686
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.530069519
Short name T545
Test name
Test status
Simulation time 871877809 ps
CPU time 27.74 seconds
Started May 09 01:14:41 PM PDT 24
Finished May 09 01:15:11 PM PDT 24
Peak memory 247164 kb
Host smart-efcd87cc-868b-4c67-9f82-27990a8e2f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530069519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.530069519
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1704573581
Short name T350
Test name
Test status
Simulation time 153080721 ps
CPU time 6.24 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:50 PM PDT 24
Peak memory 251028 kb
Host smart-6894023d-71f7-4a7b-bd2f-67e8ffebfd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704573581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1704573581
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2662238867
Short name T495
Test name
Test status
Simulation time 5913214431 ps
CPU time 99.6 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:16:24 PM PDT 24
Peak memory 273584 kb
Host smart-096204e0-1b53-4364-83f8-f7804007968d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662238867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2662238867
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.30879959
Short name T809
Test name
Test status
Simulation time 76613539 ps
CPU time 0.99 seconds
Started May 09 01:14:45 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 212068 kb
Host smart-1222c6a3-e165-46d3-9467-6dc9b6b6ce49
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctr
l_volatile_unlock_smoke.30879959
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.548692009
Short name T458
Test name
Test status
Simulation time 55763204 ps
CPU time 1.08 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 209704 kb
Host smart-f7f2bc7a-39bc-4ab8-ac45-2a6289df6d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548692009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.548692009
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3153483379
Short name T488
Test name
Test status
Simulation time 279359487 ps
CPU time 11.59 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 218224 kb
Host smart-e9454e2b-13c4-4db5-8665-7ba003b583d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153483379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3153483379
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1325693910
Short name T841
Test name
Test status
Simulation time 105331390 ps
CPU time 3.69 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 217284 kb
Host smart-3bc7d838-047d-4815-bcc5-a0b086b80890
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325693910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1325693910
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1938011540
Short name T550
Test name
Test status
Simulation time 318857814 ps
CPU time 3.06 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:49 PM PDT 24
Peak memory 218216 kb
Host smart-8430d834-752c-4962-abc0-bab42f7faf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938011540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1938011540
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1109458380
Short name T268
Test name
Test status
Simulation time 511700982 ps
CPU time 10.03 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 226328 kb
Host smart-6df59577-ee6c-43f0-8ce9-734c217c989e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109458380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1109458380
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2073959
Short name T167
Test name
Test status
Simulation time 1249901559 ps
CPU time 15.04 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:15:02 PM PDT 24
Peak memory 218428 kb
Host smart-c70f17e0-ef70-4163-9650-d9bebe03f30c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_dige
st.2073959
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1566524263
Short name T362
Test name
Test status
Simulation time 498596540 ps
CPU time 8.06 seconds
Started May 09 01:14:44 PM PDT 24
Finished May 09 01:14:55 PM PDT 24
Peak memory 218572 kb
Host smart-02b57a67-4cf7-4d07-aba6-17d7f2c06e3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566524263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1566524263
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.70102391
Short name T731
Test name
Test status
Simulation time 1937001250 ps
CPU time 6.45 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:51 PM PDT 24
Peak memory 218340 kb
Host smart-5aa2d86d-9b2a-4e6a-8c1b-46c1884c2ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70102391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.70102391
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2225797521
Short name T70
Test name
Test status
Simulation time 27971675 ps
CPU time 2.06 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 214024 kb
Host smart-3cc2ace4-5ce4-4d8e-bf69-fecaaa27ffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225797521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2225797521
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2346879752
Short name T309
Test name
Test status
Simulation time 277716447 ps
CPU time 25.29 seconds
Started May 09 01:14:43 PM PDT 24
Finished May 09 01:15:11 PM PDT 24
Peak memory 251152 kb
Host smart-06195347-111c-417a-9f04-d1dbbd50405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346879752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2346879752
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2028924408
Short name T580
Test name
Test status
Simulation time 515163296 ps
CPU time 6.23 seconds
Started May 09 01:14:45 PM PDT 24
Finished May 09 01:14:54 PM PDT 24
Peak memory 246996 kb
Host smart-baeb1a22-2c8f-47d5-9344-0d540fe99838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028924408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2028924408
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1312401894
Short name T707
Test name
Test status
Simulation time 9693925930 ps
CPU time 102.15 seconds
Started May 09 01:14:41 PM PDT 24
Finished May 09 01:16:26 PM PDT 24
Peak memory 283960 kb
Host smart-66f73c38-0458-4310-b619-f505c0348c45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312401894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1312401894
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3609900915
Short name T469
Test name
Test status
Simulation time 15686375 ps
CPU time 1.12 seconds
Started May 09 01:14:42 PM PDT 24
Finished May 09 01:14:46 PM PDT 24
Peak memory 209056 kb
Host smart-d5d1a999-0639-42f4-9ed9-59323896d1b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609900915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3609900915
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3515935904
Short name T621
Test name
Test status
Simulation time 29586518 ps
CPU time 1.1 seconds
Started May 09 01:13:15 PM PDT 24
Finished May 09 01:13:18 PM PDT 24
Peak memory 209824 kb
Host smart-ff239b7c-ee7c-402b-a724-eaf246e4f2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515935904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3515935904
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1798893219
Short name T163
Test name
Test status
Simulation time 31728002 ps
CPU time 0.79 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:15 PM PDT 24
Peak memory 209532 kb
Host smart-7dfabf10-f906-4709-b15a-e45e3ba09de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798893219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1798893219
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2723702992
Short name T825
Test name
Test status
Simulation time 3100441529 ps
CPU time 12.09 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:26 PM PDT 24
Peak memory 218256 kb
Host smart-749c1705-2ce4-4009-bc1f-7cad26d94471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723702992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2723702992
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3055619585
Short name T806
Test name
Test status
Simulation time 730336351 ps
CPU time 16.13 seconds
Started May 09 01:13:15 PM PDT 24
Finished May 09 01:13:33 PM PDT 24
Peak memory 209792 kb
Host smart-af3c82a4-ed7d-4c6a-9faa-2e98b324d247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055619585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3055619585
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1070150613
Short name T303
Test name
Test status
Simulation time 14308590259 ps
CPU time 50.65 seconds
Started May 09 01:13:15 PM PDT 24
Finished May 09 01:14:08 PM PDT 24
Peak memory 220668 kb
Host smart-7d33de9e-1c90-48be-85c6-ee8be4b943b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070150613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1070150613
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.642051535
Short name T447
Test name
Test status
Simulation time 2007241162 ps
CPU time 6.1 seconds
Started May 09 01:13:26 PM PDT 24
Finished May 09 01:13:33 PM PDT 24
Peak memory 217252 kb
Host smart-224fb017-915a-4d0b-ab8f-74abfbcd0e39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642051535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.642051535
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1769675783
Short name T482
Test name
Test status
Simulation time 1037020068 ps
CPU time 8.14 seconds
Started May 09 01:13:24 PM PDT 24
Finished May 09 01:13:34 PM PDT 24
Peak memory 218060 kb
Host smart-34ca4e65-1a33-49fa-a672-2a124ce945c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769675783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1769675783
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2379067279
Short name T493
Test name
Test status
Simulation time 1881005082 ps
CPU time 13.8 seconds
Started May 09 01:13:26 PM PDT 24
Finished May 09 01:13:41 PM PDT 24
Peak memory 213284 kb
Host smart-2d9551c2-e7eb-42d5-8611-062bbe4339c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379067279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2379067279
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1374471408
Short name T679
Test name
Test status
Simulation time 146773572 ps
CPU time 4.48 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:21 PM PDT 24
Peak memory 213296 kb
Host smart-dabf1163-1388-4508-bb1e-7bff1a40accf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374471408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1374471408
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.256702251
Short name T744
Test name
Test status
Simulation time 11762494682 ps
CPU time 52.87 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:14:09 PM PDT 24
Peak memory 269712 kb
Host smart-0b7de65c-ed65-4350-8690-cd5a530063ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256702251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.256702251
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2113643324
Short name T455
Test name
Test status
Simulation time 2308270303 ps
CPU time 12.16 seconds
Started May 09 01:13:16 PM PDT 24
Finished May 09 01:13:30 PM PDT 24
Peak memory 226608 kb
Host smart-95349568-e05d-4097-b4f3-d8cad8612058
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113643324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2113643324
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.66525911
Short name T360
Test name
Test status
Simulation time 41143421 ps
CPU time 2.31 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:18 PM PDT 24
Peak memory 218300 kb
Host smart-1a58684a-781b-4d67-9be6-0e96d02a5304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66525911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.66525911
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2821744400
Short name T774
Test name
Test status
Simulation time 1350960544 ps
CPU time 20.49 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:34 PM PDT 24
Peak memory 217892 kb
Host smart-d51cd84a-3b16-4443-a4d9-5171a688113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821744400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2821744400
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3618529310
Short name T61
Test name
Test status
Simulation time 407038102 ps
CPU time 36.72 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:53 PM PDT 24
Peak memory 284364 kb
Host smart-7cea5657-cd34-4697-9407-82abae8c7583
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618529310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3618529310
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.816701261
Short name T597
Test name
Test status
Simulation time 657684691 ps
CPU time 10.58 seconds
Started May 09 01:13:26 PM PDT 24
Finished May 09 01:13:38 PM PDT 24
Peak memory 218836 kb
Host smart-6e2dcf3c-5a7c-475f-8736-9d7c1c2e2bca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816701261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.816701261
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3972254845
Short name T14
Test name
Test status
Simulation time 898139729 ps
CPU time 11.94 seconds
Started May 09 01:13:25 PM PDT 24
Finished May 09 01:13:38 PM PDT 24
Peak memory 218056 kb
Host smart-0950ec33-3641-454f-8c62-9ac27dee8122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972254845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3972254845
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4094438776
Short name T505
Test name
Test status
Simulation time 343815925 ps
CPU time 12.95 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:13:28 PM PDT 24
Peak memory 218260 kb
Host smart-4a438e4d-b677-4bcb-8405-fc1a0e13306b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094438776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
094438776
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3224917391
Short name T527
Test name
Test status
Simulation time 413389913 ps
CPU time 14.37 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:30 PM PDT 24
Peak memory 218280 kb
Host smart-4a17f142-714f-42c4-bbea-941bdf2e4e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224917391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3224917391
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2765915061
Short name T614
Test name
Test status
Simulation time 117911103 ps
CPU time 2.52 seconds
Started May 09 01:13:12 PM PDT 24
Finished May 09 01:13:17 PM PDT 24
Peak memory 214200 kb
Host smart-9e46619a-5cde-40ca-9b38-9549015b3dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765915061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2765915061
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3042833744
Short name T185
Test name
Test status
Simulation time 486510737 ps
CPU time 25.11 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:38 PM PDT 24
Peak memory 249012 kb
Host smart-507828fe-e110-446c-9e7a-902b8d6fe635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042833744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3042833744
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3468205141
Short name T519
Test name
Test status
Simulation time 195902194 ps
CPU time 8.44 seconds
Started May 09 01:13:11 PM PDT 24
Finished May 09 01:13:22 PM PDT 24
Peak memory 248532 kb
Host smart-02f04d83-239d-4037-9c89-c6fd976ee114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468205141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3468205141
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3702821138
Short name T326
Test name
Test status
Simulation time 13409530 ps
CPU time 0.75 seconds
Started May 09 01:13:14 PM PDT 24
Finished May 09 01:13:18 PM PDT 24
Peak memory 207416 kb
Host smart-e0080531-b4e8-424b-94a9-d20c275851f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702821138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3702821138
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.4220174904
Short name T89
Test name
Test status
Simulation time 34039359 ps
CPU time 1.08 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 209824 kb
Host smart-9472faa1-8424-49cf-859c-882307df3685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220174904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4220174904
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4138569847
Short name T572
Test name
Test status
Simulation time 392341139 ps
CPU time 12.84 seconds
Started May 09 01:14:54 PM PDT 24
Finished May 09 01:15:11 PM PDT 24
Peak memory 218260 kb
Host smart-dbf660bb-35fc-4d47-880d-c66e6ca0f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138569847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4138569847
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.166715491
Short name T552
Test name
Test status
Simulation time 215272216 ps
CPU time 3.22 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 209812 kb
Host smart-242d05d4-6c47-4d86-8e12-5715735e58ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166715491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.166715491
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.867217076
Short name T391
Test name
Test status
Simulation time 424296090 ps
CPU time 3.74 seconds
Started May 09 01:14:51 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 218276 kb
Host smart-cfe87173-10de-4113-b0bf-44a4ca383207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867217076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.867217076
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4240509357
Short name T357
Test name
Test status
Simulation time 481794823 ps
CPU time 10.24 seconds
Started May 09 01:14:57 PM PDT 24
Finished May 09 01:15:10 PM PDT 24
Peak memory 226588 kb
Host smart-b3ce2b79-f42a-47b5-baf1-607cf0c01dc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240509357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4240509357
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1556243307
Short name T692
Test name
Test status
Simulation time 593374357 ps
CPU time 14.58 seconds
Started May 09 01:14:54 PM PDT 24
Finished May 09 01:15:12 PM PDT 24
Peak memory 218288 kb
Host smart-94dfb41a-317d-4ad1-9557-05b2e8db3aff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556243307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1556243307
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4126901081
Short name T64
Test name
Test status
Simulation time 401631460 ps
CPU time 14.24 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:15:09 PM PDT 24
Peak memory 218300 kb
Host smart-9c599a38-0853-4a79-a6ce-a66a5aa0ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126901081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4126901081
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2783276756
Short name T712
Test name
Test status
Simulation time 555413955 ps
CPU time 3.06 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:02 PM PDT 24
Peak memory 214568 kb
Host smart-6464cbd9-7c2a-4981-8740-6f3f3d13171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783276756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2783276756
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.197086780
Short name T412
Test name
Test status
Simulation time 495497640 ps
CPU time 26.29 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 251176 kb
Host smart-2586d301-c064-4240-a7dd-858a97671b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197086780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.197086780
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3762113994
Short name T404
Test name
Test status
Simulation time 191990116 ps
CPU time 3.35 seconds
Started May 09 01:14:56 PM PDT 24
Finished May 09 01:15:03 PM PDT 24
Peak memory 226628 kb
Host smart-503e4f6b-33e6-4253-a63a-828e738850ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762113994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3762113994
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.875498565
Short name T327
Test name
Test status
Simulation time 39421055179 ps
CPU time 266.12 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:19:21 PM PDT 24
Peak memory 279280 kb
Host smart-30076037-68f7-4bbb-8303-6618c756b53c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875498565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.875498565
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.566111181
Short name T717
Test name
Test status
Simulation time 19569700 ps
CPU time 1.1 seconds
Started May 09 01:14:57 PM PDT 24
Finished May 09 01:15:01 PM PDT 24
Peak memory 212136 kb
Host smart-626bd73a-1c05-4dfb-8c07-1bacddf33fb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566111181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.566111181
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3917502159
Short name T158
Test name
Test status
Simulation time 93231695 ps
CPU time 1.16 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 209796 kb
Host smart-afa65904-462a-47e5-bd78-7ddc1991671c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917502159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3917502159
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1335847272
Short name T513
Test name
Test status
Simulation time 497583590 ps
CPU time 12.9 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:15:08 PM PDT 24
Peak memory 218128 kb
Host smart-6807643a-7267-4112-857d-a0d0b6384e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335847272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1335847272
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.674800382
Short name T672
Test name
Test status
Simulation time 183151467 ps
CPU time 5 seconds
Started May 09 01:14:56 PM PDT 24
Finished May 09 01:15:05 PM PDT 24
Peak memory 217176 kb
Host smart-436020b8-44d8-493a-bcb6-429034184d32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674800382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.674800382
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1316979005
Short name T511
Test name
Test status
Simulation time 134595496 ps
CPU time 2.58 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 218236 kb
Host smart-5f573ed5-c144-455f-958b-cc0a40475ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316979005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1316979005
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3071300214
Short name T494
Test name
Test status
Simulation time 348219670 ps
CPU time 11.43 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:15:06 PM PDT 24
Peak memory 218152 kb
Host smart-aa7eb748-ea72-49fd-8bf0-61aa90f69895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071300214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3071300214
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3794481138
Short name T582
Test name
Test status
Simulation time 1807295446 ps
CPU time 11.88 seconds
Started May 09 01:14:54 PM PDT 24
Finished May 09 01:15:09 PM PDT 24
Peak memory 218224 kb
Host smart-f4b0d524-adde-4314-989d-eb95e80bf05e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794481138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3794481138
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4145289857
Short name T440
Test name
Test status
Simulation time 1754776520 ps
CPU time 14.96 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:15:11 PM PDT 24
Peak memory 218296 kb
Host smart-91e8c3ee-acbc-468c-b9e3-4bf72ef8b090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145289857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4145289857
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2335502727
Short name T878
Test name
Test status
Simulation time 129755777 ps
CPU time 2.16 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 214052 kb
Host smart-90fd061d-51c6-42a9-b376-56ad3cde1c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335502727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2335502727
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2207103015
Short name T681
Test name
Test status
Simulation time 962624693 ps
CPU time 18.32 seconds
Started May 09 01:14:51 PM PDT 24
Finished May 09 01:15:11 PM PDT 24
Peak memory 249372 kb
Host smart-11110a20-f31c-4535-8071-b0339843bc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207103015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2207103015
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3999433532
Short name T798
Test name
Test status
Simulation time 78229469 ps
CPU time 6.43 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:15:01 PM PDT 24
Peak memory 244228 kb
Host smart-106a11b8-3915-40b7-aecd-15c8feae9f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999433532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3999433532
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1034227889
Short name T331
Test name
Test status
Simulation time 153734408970 ps
CPU time 260.41 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:19:19 PM PDT 24
Peak memory 252892 kb
Host smart-5a8fd84f-fc20-42cf-8cf5-c213069a9cd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034227889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1034227889
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1863654521
Short name T498
Test name
Test status
Simulation time 15187983240 ps
CPU time 349.35 seconds
Started May 09 01:14:57 PM PDT 24
Finished May 09 01:20:50 PM PDT 24
Peak memory 438952 kb
Host smart-7df1a21e-30e1-4a81-970e-bbf5f2a9cfae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1863654521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1863654521
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1027956403
Short name T180
Test name
Test status
Simulation time 47942106 ps
CPU time 0.95 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:00 PM PDT 24
Peak memory 209088 kb
Host smart-978b2a62-3f6c-4274-ba3c-9f71aac38a62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027956403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1027956403
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2600182283
Short name T347
Test name
Test status
Simulation time 31239221 ps
CPU time 1.09 seconds
Started May 09 01:15:00 PM PDT 24
Finished May 09 01:15:03 PM PDT 24
Peak memory 209708 kb
Host smart-c9d7b20c-d738-4580-a5d2-a29510e93162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600182283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2600182283
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.125183502
Short name T184
Test name
Test status
Simulation time 328995463 ps
CPU time 12.91 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:12 PM PDT 24
Peak memory 218308 kb
Host smart-227021eb-0f71-4c43-b496-b136a0e693da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125183502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.125183502
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2734775130
Short name T195
Test name
Test status
Simulation time 347818464 ps
CPU time 1.9 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:01 PM PDT 24
Peak memory 209832 kb
Host smart-4cd2669a-3730-434c-8f48-bdf39cceb58f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734775130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2734775130
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1620882825
Short name T688
Test name
Test status
Simulation time 24906775 ps
CPU time 2.02 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 218140 kb
Host smart-cf25f346-f752-46bd-9738-3e28c8661f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620882825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1620882825
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.470521274
Short name T336
Test name
Test status
Simulation time 291894669 ps
CPU time 13.38 seconds
Started May 09 01:14:56 PM PDT 24
Finished May 09 01:15:13 PM PDT 24
Peak memory 225816 kb
Host smart-11d42df4-d734-45d1-aa9f-ba1d95fa2f97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470521274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.470521274
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4171867734
Short name T387
Test name
Test status
Simulation time 1268962692 ps
CPU time 13.84 seconds
Started May 09 01:14:56 PM PDT 24
Finished May 09 01:15:13 PM PDT 24
Peak memory 218200 kb
Host smart-b55cc1d4-6205-4243-bfee-7013734f7544
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171867734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4171867734
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1170443558
Short name T551
Test name
Test status
Simulation time 848102101 ps
CPU time 6.8 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:15:02 PM PDT 24
Peak memory 218320 kb
Host smart-8d4f818e-72aa-44ed-aa82-63e6442fd289
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170443558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1170443558
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3455375254
Short name T406
Test name
Test status
Simulation time 281121210 ps
CPU time 9.17 seconds
Started May 09 01:14:54 PM PDT 24
Finished May 09 01:15:07 PM PDT 24
Peak memory 218328 kb
Host smart-2207be5c-739d-47cf-9f01-0e42acc441dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455375254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3455375254
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3884993341
Short name T531
Test name
Test status
Simulation time 29768378 ps
CPU time 1.62 seconds
Started May 09 01:14:54 PM PDT 24
Finished May 09 01:14:59 PM PDT 24
Peak memory 218512 kb
Host smart-d311c43f-56ef-4848-860b-eac5a095504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884993341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3884993341
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.289148096
Short name T500
Test name
Test status
Simulation time 452665033 ps
CPU time 29.96 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 250004 kb
Host smart-3bd19351-1777-4c3b-8919-55bc58b5d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289148096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.289148096
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3605648293
Short name T659
Test name
Test status
Simulation time 664421864 ps
CPU time 12.08 seconds
Started May 09 01:14:52 PM PDT 24
Finished May 09 01:15:06 PM PDT 24
Peak memory 251212 kb
Host smart-798916f5-5e7b-4dbd-b233-af6cc768f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605648293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3605648293
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.845504272
Short name T17
Test name
Test status
Simulation time 57377554854 ps
CPU time 151.2 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:17:28 PM PDT 24
Peak memory 245720 kb
Host smart-4f0084f0-3739-4959-9cbb-8559a7771312
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845504272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.845504272
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.11645762
Short name T567
Test name
Test status
Simulation time 12081752 ps
CPU time 0.92 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 209012 kb
Host smart-fe6341f8-4fa6-4626-9bd2-b88f90464b71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctr
l_volatile_unlock_smoke.11645762
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2699874092
Short name T728
Test name
Test status
Simulation time 21362528 ps
CPU time 0.95 seconds
Started May 09 01:15:01 PM PDT 24
Finished May 09 01:15:04 PM PDT 24
Peak memory 209760 kb
Host smart-f115fb68-87f6-4ebc-9a34-734e1e0f20db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699874092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2699874092
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3466687685
Short name T258
Test name
Test status
Simulation time 474002156 ps
CPU time 15.09 seconds
Started May 09 01:15:05 PM PDT 24
Finished May 09 01:15:21 PM PDT 24
Peak memory 218216 kb
Host smart-b5f616e7-a6d3-42a7-b5a3-5463c6bce8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466687685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3466687685
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1863496960
Short name T660
Test name
Test status
Simulation time 156318686 ps
CPU time 2.5 seconds
Started May 09 01:15:00 PM PDT 24
Finished May 09 01:15:04 PM PDT 24
Peak memory 209808 kb
Host smart-10a84215-d926-4817-b488-15d7b107d31d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863496960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1863496960
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.226378612
Short name T383
Test name
Test status
Simulation time 610836183 ps
CPU time 4.23 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:03 PM PDT 24
Peak memory 218232 kb
Host smart-6b67f576-642c-4a61-8b7e-e0083a7ca29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226378612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.226378612
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2246841586
Short name T706
Test name
Test status
Simulation time 324154579 ps
CPU time 16.71 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:15:13 PM PDT 24
Peak memory 226332 kb
Host smart-c0b836f5-a2ec-45c4-90ef-454dd6d6b9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246841586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2246841586
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2455130142
Short name T623
Test name
Test status
Simulation time 192059924 ps
CPU time 8.68 seconds
Started May 09 01:15:06 PM PDT 24
Finished May 09 01:15:16 PM PDT 24
Peak memory 218224 kb
Host smart-ddf1620a-33e3-42b9-b8ca-3e15a5625efc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455130142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2455130142
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2409727034
Short name T540
Test name
Test status
Simulation time 991490662 ps
CPU time 7.9 seconds
Started May 09 01:14:54 PM PDT 24
Finished May 09 01:15:06 PM PDT 24
Peak memory 218224 kb
Host smart-a579ddfc-9930-4781-9508-481311ddf8cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409727034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2409727034
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.962237037
Short name T722
Test name
Test status
Simulation time 5987015065 ps
CPU time 13.21 seconds
Started May 09 01:15:02 PM PDT 24
Finished May 09 01:15:17 PM PDT 24
Peak memory 218264 kb
Host smart-9abe1cb8-eedc-42da-82ff-be591eb08702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962237037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.962237037
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3947815280
Short name T453
Test name
Test status
Simulation time 168475477 ps
CPU time 2.27 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:14:57 PM PDT 24
Peak memory 214068 kb
Host smart-988332d8-e5b5-4027-a8c3-a9ae4d981dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947815280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3947815280
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3091475007
Short name T267
Test name
Test status
Simulation time 331936005 ps
CPU time 30.36 seconds
Started May 09 01:15:01 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 251124 kb
Host smart-c8ba7957-3c98-40a6-b23f-68c5d2824787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091475007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3091475007
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1604361457
Short name T610
Test name
Test status
Simulation time 108000145 ps
CPU time 3.38 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:15:00 PM PDT 24
Peak memory 224152 kb
Host smart-a58b2b8f-2b61-401d-ad68-512ab4ac26b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604361457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1604361457
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1394725553
Short name T384
Test name
Test status
Simulation time 14184745527 ps
CPU time 29.7 seconds
Started May 09 01:15:01 PM PDT 24
Finished May 09 01:15:33 PM PDT 24
Peak memory 226468 kb
Host smart-48b1a55c-bf5e-4256-abb0-3109bcce5d30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394725553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1394725553
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2334089107
Short name T147
Test name
Test status
Simulation time 10139305064 ps
CPU time 116.28 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:16:55 PM PDT 24
Peak memory 276096 kb
Host smart-2b44ffc5-1a73-4c6a-ae5b-ae25e2d53cbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2334089107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2334089107
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2268046905
Short name T755
Test name
Test status
Simulation time 33968810 ps
CPU time 1.02 seconds
Started May 09 01:14:54 PM PDT 24
Finished May 09 01:14:58 PM PDT 24
Peak memory 209124 kb
Host smart-e10ddc5a-1581-410b-a599-846c609373bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268046905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2268046905
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3144379503
Short name T721
Test name
Test status
Simulation time 33106909 ps
CPU time 0.81 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:31 PM PDT 24
Peak memory 209492 kb
Host smart-530f8255-444b-4910-95ce-2e04da9a73dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144379503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3144379503
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3279453230
Short name T63
Test name
Test status
Simulation time 345577482 ps
CPU time 16.51 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:15 PM PDT 24
Peak memory 218320 kb
Host smart-5759d5ce-5165-4b06-8c7a-f689b6137e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279453230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3279453230
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3949039011
Short name T594
Test name
Test status
Simulation time 523908517 ps
CPU time 4.64 seconds
Started May 09 01:15:05 PM PDT 24
Finished May 09 01:15:10 PM PDT 24
Peak memory 209808 kb
Host smart-d9f21fe6-2ed9-4a62-a37f-2752e2aee996
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949039011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3949039011
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1231948519
Short name T231
Test name
Test status
Simulation time 27466101 ps
CPU time 1.87 seconds
Started May 09 01:14:55 PM PDT 24
Finished May 09 01:15:01 PM PDT 24
Peak memory 218232 kb
Host smart-4e4b93cd-f09d-4de6-9160-616b996eea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231948519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1231948519
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2866509135
Short name T49
Test name
Test status
Simulation time 314778135 ps
CPU time 13.17 seconds
Started May 09 01:15:08 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 219136 kb
Host smart-94afd63b-eaa2-4e6c-98c6-5e55d1569658
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866509135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2866509135
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.822717737
Short name T193
Test name
Test status
Simulation time 405616308 ps
CPU time 12.28 seconds
Started May 09 01:15:06 PM PDT 24
Finished May 09 01:15:19 PM PDT 24
Peak memory 218276 kb
Host smart-8eeb13ce-8d04-4968-b538-7553cddc4d28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822717737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.822717737
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.5826804
Short name T490
Test name
Test status
Simulation time 1225668953 ps
CPU time 12.35 seconds
Started May 09 01:15:07 PM PDT 24
Finished May 09 01:15:20 PM PDT 24
Peak memory 218260 kb
Host smart-95f9cb49-38d7-4661-a8bf-6eb992059978
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5826804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.5826804
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1966003949
Short name T385
Test name
Test status
Simulation time 1153154659 ps
CPU time 11.44 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:15:07 PM PDT 24
Peak memory 218236 kb
Host smart-047e9092-6c2d-4682-9168-2120ea222e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966003949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1966003949
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3427352071
Short name T436
Test name
Test status
Simulation time 47750420 ps
CPU time 2.77 seconds
Started May 09 01:14:58 PM PDT 24
Finished May 09 01:15:03 PM PDT 24
Peak memory 218508 kb
Host smart-0b6f3203-8282-46b7-88fd-626d83bdc9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427352071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3427352071
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.661258723
Short name T587
Test name
Test status
Simulation time 1076065671 ps
CPU time 31.4 seconds
Started May 09 01:14:53 PM PDT 24
Finished May 09 01:15:27 PM PDT 24
Peak memory 250720 kb
Host smart-198ae6cf-4dae-4a7a-ad1e-54289ecf4256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661258723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.661258723
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.480518597
Short name T159
Test name
Test status
Simulation time 115687727 ps
CPU time 7.07 seconds
Started May 09 01:14:58 PM PDT 24
Finished May 09 01:15:07 PM PDT 24
Peak memory 250788 kb
Host smart-a2315d74-e983-4be9-8a35-4d8d4292a9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480518597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.480518597
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3324012875
Short name T37
Test name
Test status
Simulation time 5570753972 ps
CPU time 89.5 seconds
Started May 09 01:15:07 PM PDT 24
Finished May 09 01:16:37 PM PDT 24
Peak memory 273388 kb
Host smart-f3e00c27-1728-43c2-a2e4-232c4303c454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324012875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3324012875
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.717090902
Short name T734
Test name
Test status
Simulation time 38522647703 ps
CPU time 847.01 seconds
Started May 09 01:15:08 PM PDT 24
Finished May 09 01:29:16 PM PDT 24
Peak memory 282604 kb
Host smart-396eaec7-2572-4d2d-86bc-d3890de9cd40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=717090902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.717090902
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.805605585
Short name T40
Test name
Test status
Simulation time 13393751 ps
CPU time 0.97 seconds
Started May 09 01:15:02 PM PDT 24
Finished May 09 01:15:05 PM PDT 24
Peak memory 211864 kb
Host smart-5e255bc6-942a-4a39-92da-e7af0f5a0945
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805605585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.805605585
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2802498609
Short name T292
Test name
Test status
Simulation time 17050721 ps
CPU time 0.86 seconds
Started May 09 01:15:17 PM PDT 24
Finished May 09 01:15:19 PM PDT 24
Peak memory 209768 kb
Host smart-5a400c4f-6638-406e-8cfb-7d90416457a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802498609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2802498609
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.814987094
Short name T666
Test name
Test status
Simulation time 334237355 ps
CPU time 9.86 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:30 PM PDT 24
Peak memory 218080 kb
Host smart-102c800b-cd8f-42d0-a1ef-ed012d85a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814987094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.814987094
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.35071207
Short name T485
Test name
Test status
Simulation time 338486151 ps
CPU time 2.87 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 218184 kb
Host smart-86f42308-475b-4a08-8047-1e947be6235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35071207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.35071207
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3795726488
Short name T752
Test name
Test status
Simulation time 793293733 ps
CPU time 17.4 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 219188 kb
Host smart-711d38c7-c98f-4e3d-a0c6-73003d04c662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795726488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3795726488
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2440696238
Short name T549
Test name
Test status
Simulation time 1950295944 ps
CPU time 13.94 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:15:38 PM PDT 24
Peak memory 218244 kb
Host smart-531fc540-219d-4cce-99ee-447c86871a53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440696238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2440696238
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3804717579
Short name T642
Test name
Test status
Simulation time 788323707 ps
CPU time 7.12 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:29 PM PDT 24
Peak memory 218260 kb
Host smart-359d50ed-b62e-4668-8516-2643377ae3e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804717579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3804717579
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.911144206
Short name T759
Test name
Test status
Simulation time 406268101 ps
CPU time 9.8 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 218304 kb
Host smart-66a96ce2-9c5e-4921-87f6-716e48e7f285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911144206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.911144206
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4141322838
Short name T256
Test name
Test status
Simulation time 45831990 ps
CPU time 2 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 214040 kb
Host smart-25a89208-e381-444c-b7db-d32c1f799910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141322838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4141322838
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.341402043
Short name T316
Test name
Test status
Simulation time 152607486 ps
CPU time 18.75 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:15:43 PM PDT 24
Peak memory 249900 kb
Host smart-013f5605-e794-4574-922c-41e7fd40c389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341402043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.341402043
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1994373574
Short name T413
Test name
Test status
Simulation time 87374553 ps
CPU time 3.41 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:23 PM PDT 24
Peak memory 222728 kb
Host smart-0cb3e1dd-1735-4931-93b8-781ae12d9b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994373574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1994373574
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.183493732
Short name T478
Test name
Test status
Simulation time 27745041821 ps
CPU time 188.61 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:18:33 PM PDT 24
Peak memory 281896 kb
Host smart-b3389f3c-51d0-43fd-921b-b6522107e359
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183493732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.183493732
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3471588728
Short name T51
Test name
Test status
Simulation time 662933566983 ps
CPU time 1199.13 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:35:21 PM PDT 24
Peak memory 513500 kb
Host smart-8c88c3ac-6921-41b6-bdb2-208bae2e0f23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3471588728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3471588728
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2838804153
Short name T97
Test name
Test status
Simulation time 36069358 ps
CPU time 0.79 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:20 PM PDT 24
Peak memory 208668 kb
Host smart-b7d9418d-9fb6-4354-8888-dd1ae9cd4b1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838804153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2838804153
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.4026750889
Short name T418
Test name
Test status
Simulation time 54966062 ps
CPU time 0.93 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 209768 kb
Host smart-44598ca7-7dff-4696-908d-6529a04a540d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026750889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4026750889
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3850667604
Short name T96
Test name
Test status
Simulation time 1223416588 ps
CPU time 12.36 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 218120 kb
Host smart-2ee2fb51-144b-4b8a-8bc4-de7b9b183eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850667604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3850667604
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3286485147
Short name T530
Test name
Test status
Simulation time 477913388 ps
CPU time 2.11 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 209824 kb
Host smart-376e6033-4099-4974-a2ac-e47494e110cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286485147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3286485147
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.651323153
Short name T646
Test name
Test status
Simulation time 39185461 ps
CPU time 2.79 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 218296 kb
Host smart-347d030e-ca7f-4501-82bc-26c6e1971c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651323153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.651323153
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.827183349
Short name T263
Test name
Test status
Simulation time 556320012 ps
CPU time 13 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:35 PM PDT 24
Peak memory 219144 kb
Host smart-5ee68dd5-192d-4f24-b3d7-ef181b8d1a13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827183349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.827183349
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.100015078
Short name T473
Test name
Test status
Simulation time 279074013 ps
CPU time 8 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:28 PM PDT 24
Peak memory 218288 kb
Host smart-06de40bf-31a2-4313-8c33-e9954be73e01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100015078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.100015078
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2307455803
Short name T470
Test name
Test status
Simulation time 1871263220 ps
CPU time 10.35 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:33 PM PDT 24
Peak memory 217976 kb
Host smart-c1e360e4-b327-431c-b95e-5e59d60fdd0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307455803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2307455803
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3642381295
Short name T62
Test name
Test status
Simulation time 1239618743 ps
CPU time 12.33 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:31 PM PDT 24
Peak memory 218304 kb
Host smart-90c0a6f6-d342-4cba-a843-46ffaac1e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642381295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3642381295
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2603665577
Short name T735
Test name
Test status
Simulation time 71885544 ps
CPU time 1.47 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:23 PM PDT 24
Peak memory 218132 kb
Host smart-9aa39776-069a-4e31-ade3-e09d2c554430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603665577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2603665577
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.171121673
Short name T756
Test name
Test status
Simulation time 1035360555 ps
CPU time 24.91 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 250092 kb
Host smart-508edc2c-aec3-4a2b-99dd-5253ed870a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171121673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.171121673
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3969010650
Short name T686
Test name
Test status
Simulation time 57487422 ps
CPU time 2.95 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:24 PM PDT 24
Peak memory 222484 kb
Host smart-7033ac40-526b-4d11-99bc-fd02246731a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969010650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3969010650
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4016724674
Short name T79
Test name
Test status
Simulation time 2218702132 ps
CPU time 10.71 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:35 PM PDT 24
Peak memory 215648 kb
Host smart-e01bdffb-6212-467c-8495-29ed37f23dea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016724674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4016724674
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3042553750
Short name T42
Test name
Test status
Simulation time 47524539 ps
CPU time 0.85 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:20 PM PDT 24
Peak memory 209052 kb
Host smart-ba532ba6-9932-4b08-961f-d293d318894d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042553750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3042553750
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.144329907
Short name T295
Test name
Test status
Simulation time 68339777 ps
CPU time 1.14 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:23 PM PDT 24
Peak memory 209876 kb
Host smart-53673743-84eb-46ce-b5e3-6946ecbce20c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144329907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.144329907
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.4290044432
Short name T619
Test name
Test status
Simulation time 353028784 ps
CPU time 12.04 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:32 PM PDT 24
Peak memory 218184 kb
Host smart-f7ca1b75-1c2b-474c-b902-018f85bc6e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290044432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.4290044432
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3594967226
Short name T486
Test name
Test status
Simulation time 942028589 ps
CPU time 4.65 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 209828 kb
Host smart-f5af61fc-c1f2-47ae-a630-4e32a406581c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594967226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3594967226
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3382761572
Short name T368
Test name
Test status
Simulation time 400362386 ps
CPU time 4.04 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:27 PM PDT 24
Peak memory 218256 kb
Host smart-ba583605-dd05-4ace-80a0-26b414744034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382761572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3382761572
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1784113993
Short name T675
Test name
Test status
Simulation time 1285257149 ps
CPU time 10.64 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:32 PM PDT 24
Peak memory 219416 kb
Host smart-d399ac64-795b-4dd2-bfce-c970b0db7848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784113993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1784113993
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2062608096
Short name T65
Test name
Test status
Simulation time 1060191040 ps
CPU time 15.66 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 218272 kb
Host smart-7508a380-6ba5-4442-b6aa-2e262f10be3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062608096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2062608096
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2503640542
Short name T522
Test name
Test status
Simulation time 1117436174 ps
CPU time 10.94 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 218244 kb
Host smart-674c1cde-f756-47eb-942d-45d221f8b52d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503640542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2503640542
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2174277965
Short name T589
Test name
Test status
Simulation time 265556443 ps
CPU time 7.1 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:30 PM PDT 24
Peak memory 218380 kb
Host smart-54a58d18-6a9f-49d8-bbe0-6300d2e44364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174277965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2174277965
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2338728222
Short name T641
Test name
Test status
Simulation time 38247469 ps
CPU time 2.28 seconds
Started May 09 01:15:17 PM PDT 24
Finished May 09 01:15:21 PM PDT 24
Peak memory 214236 kb
Host smart-8a7a0a69-8cef-4958-b296-9f3edfba95e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338728222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2338728222
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.264304688
Short name T162
Test name
Test status
Simulation time 2448475155 ps
CPU time 27.04 seconds
Started May 09 01:15:18 PM PDT 24
Finished May 09 01:15:47 PM PDT 24
Peak memory 247716 kb
Host smart-a5ae002b-ff5e-4f50-aed5-96d69c2666f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264304688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.264304688
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1532798348
Short name T754
Test name
Test status
Simulation time 46382780 ps
CPU time 9.57 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:32 PM PDT 24
Peak memory 251164 kb
Host smart-b08ed306-a4e8-40dd-86c3-2c75ddf2b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532798348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1532798348
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.583119826
Short name T625
Test name
Test status
Simulation time 23418446735 ps
CPU time 147.94 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:17:49 PM PDT 24
Peak memory 277472 kb
Host smart-46a71a56-b329-4e1d-984c-167eb7532e50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583119826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.583119826
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3822057301
Short name T547
Test name
Test status
Simulation time 73228577436 ps
CPU time 828.62 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:29:13 PM PDT 24
Peak memory 644636 kb
Host smart-64909db1-6f12-439c-bac8-e35baa09d21c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3822057301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3822057301
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1239042371
Short name T577
Test name
Test status
Simulation time 26299326 ps
CPU time 0.96 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:22 PM PDT 24
Peak memory 213148 kb
Host smart-c444e6c0-8ae0-46c4-9958-15c81e1416aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239042371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1239042371
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3715962987
Short name T257
Test name
Test status
Simulation time 16653974 ps
CPU time 1.15 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:24 PM PDT 24
Peak memory 209804 kb
Host smart-34f88185-a68f-4067-bc86-a0f25daf6474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715962987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3715962987
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3809012832
Short name T405
Test name
Test status
Simulation time 226392584 ps
CPU time 8.51 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:32 PM PDT 24
Peak memory 218140 kb
Host smart-68a27337-06df-41b3-85c6-5c1cee0ae3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809012832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3809012832
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1340192612
Short name T9
Test name
Test status
Simulation time 774799955 ps
CPU time 2.26 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 209640 kb
Host smart-d9bd0169-a063-42c2-9a43-da8f84eae229
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340192612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1340192612
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3749124785
Short name T294
Test name
Test status
Simulation time 100442601 ps
CPU time 2.08 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:24 PM PDT 24
Peak memory 218136 kb
Host smart-a2ddfcd5-5ad7-4723-8634-edb0574d4a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749124785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3749124785
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1281028100
Short name T363
Test name
Test status
Simulation time 339949315 ps
CPU time 15.78 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:49 PM PDT 24
Peak memory 226088 kb
Host smart-cca49e6e-5726-4f17-9a24-92a48953bcc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281028100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1281028100
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1198793446
Short name T438
Test name
Test status
Simulation time 4900466223 ps
CPU time 10.48 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 218300 kb
Host smart-27033e0d-d14c-41cc-9cb1-a08e1d93fa18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198793446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1198793446
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.930670501
Short name T324
Test name
Test status
Simulation time 2897334492 ps
CPU time 9.56 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 218244 kb
Host smart-1091ce27-7f27-4e86-8147-b80770cd91ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930670501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.930670501
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3875702744
Short name T815
Test name
Test status
Simulation time 127455767 ps
CPU time 1.96 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:24 PM PDT 24
Peak memory 214284 kb
Host smart-2b86249f-9842-4f5c-9002-09c20c84bc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875702744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3875702744
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2826591007
Short name T645
Test name
Test status
Simulation time 1552761188 ps
CPU time 30.19 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:51 PM PDT 24
Peak memory 251200 kb
Host smart-c764a64f-0749-478b-9b18-14eaaeae006f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826591007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2826591007
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3091253598
Short name T832
Test name
Test status
Simulation time 153770466 ps
CPU time 8.6 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:29 PM PDT 24
Peak memory 251156 kb
Host smart-cf273a65-58a9-447b-9d87-eba5e869e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091253598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3091253598
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2981317523
Short name T608
Test name
Test status
Simulation time 69225605013 ps
CPU time 127.13 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:17:37 PM PDT 24
Peak memory 271736 kb
Host smart-1e8f7601-a890-44a8-b133-99c367885db8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981317523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2981317523
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.988371794
Short name T443
Test name
Test status
Simulation time 45650043 ps
CPU time 0.83 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 208696 kb
Host smart-89e492dc-f1dd-45fa-ab14-0241b2507c7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988371794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.988371794
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1690962234
Short name T441
Test name
Test status
Simulation time 48315276 ps
CPU time 0.89 seconds
Started May 09 01:15:44 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 209804 kb
Host smart-38b96968-6328-482b-843f-431c9b8b22c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690962234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1690962234
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2918342167
Short name T617
Test name
Test status
Simulation time 265169523 ps
CPU time 9.34 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 218208 kb
Host smart-114b437d-b9f3-4ee5-9b4c-ea4780f49dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918342167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2918342167
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3802012418
Short name T30
Test name
Test status
Simulation time 523205085 ps
CPU time 7.21 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:31 PM PDT 24
Peak memory 217460 kb
Host smart-aec32d90-b81b-4185-b958-702aa4565f78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802012418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3802012418
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.727885160
Short name T746
Test name
Test status
Simulation time 101668971 ps
CPU time 2.29 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 218132 kb
Host smart-f513a2b8-0550-4035-8e98-24dbe9faa7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727885160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.727885160
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1837729252
Short name T729
Test name
Test status
Simulation time 230786778 ps
CPU time 11.09 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 217952 kb
Host smart-ca9d79a2-0d78-42fd-b44e-68c8ecefa9a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837729252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1837729252
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3454194643
Short name T703
Test name
Test status
Simulation time 565293962 ps
CPU time 13.86 seconds
Started May 09 01:15:23 PM PDT 24
Finished May 09 01:15:39 PM PDT 24
Peak memory 218240 kb
Host smart-2a2214fe-5fbe-4cd7-87bd-173df55c8537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454194643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3454194643
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.436652597
Short name T875
Test name
Test status
Simulation time 481740010 ps
CPU time 9.92 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:33 PM PDT 24
Peak memory 218120 kb
Host smart-0660600b-1302-47e1-ac9f-613ef0f0cd4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436652597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.436652597
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4167943252
Short name T872
Test name
Test status
Simulation time 906442004 ps
CPU time 11.4 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 218372 kb
Host smart-8634a50b-0bac-4657-bb56-a0e2958d830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167943252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4167943252
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.647524291
Short name T848
Test name
Test status
Simulation time 60275532 ps
CPU time 2.1 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:15:27 PM PDT 24
Peak memory 218000 kb
Host smart-e5c13054-0249-490e-8eb5-58793014e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647524291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.647524291
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.621907041
Short name T782
Test name
Test status
Simulation time 472982573 ps
CPU time 30.81 seconds
Started May 09 01:15:26 PM PDT 24
Finished May 09 01:15:59 PM PDT 24
Peak memory 251208 kb
Host smart-f3b7cb50-fd9e-41f6-82e7-0878d1ac8a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621907041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.621907041
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.582094896
Short name T687
Test name
Test status
Simulation time 234433529 ps
CPU time 7.62 seconds
Started May 09 01:15:23 PM PDT 24
Finished May 09 01:15:33 PM PDT 24
Peak memory 247104 kb
Host smart-ab0827b2-29d4-4e91-bbbd-78bafbef8db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582094896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.582094896
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4021257628
Short name T808
Test name
Test status
Simulation time 14742518442 ps
CPU time 106.27 seconds
Started May 09 01:15:24 PM PDT 24
Finished May 09 01:17:12 PM PDT 24
Peak memory 251036 kb
Host smart-cb73f633-b835-4d23-bd4d-f13560e43ae4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021257628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4021257628
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.982602779
Short name T43
Test name
Test status
Simulation time 41582617 ps
CPU time 0.84 seconds
Started May 09 01:15:22 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 208688 kb
Host smart-36365d29-2118-4f76-bdff-c4ce19d8d5f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982602779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.982602779
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3287344220
Short name T590
Test name
Test status
Simulation time 15815690 ps
CPU time 0.96 seconds
Started May 09 01:13:22 PM PDT 24
Finished May 09 01:13:24 PM PDT 24
Peak memory 209768 kb
Host smart-9831f7cc-3027-4abf-bd97-d451c12c062c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287344220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3287344220
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2753052476
Short name T379
Test name
Test status
Simulation time 10738978 ps
CPU time 0.82 seconds
Started May 09 01:13:22 PM PDT 24
Finished May 09 01:13:24 PM PDT 24
Peak memory 209488 kb
Host smart-b18ac305-1e99-45b3-91d1-82e539848b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753052476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2753052476
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1540779757
Short name T280
Test name
Test status
Simulation time 824067338 ps
CPU time 13.26 seconds
Started May 09 01:13:21 PM PDT 24
Finished May 09 01:13:35 PM PDT 24
Peak memory 218128 kb
Host smart-dc5cc620-c977-4bda-84a4-38b71c45afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540779757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1540779757
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3977058596
Short name T665
Test name
Test status
Simulation time 2894389429 ps
CPU time 15.38 seconds
Started May 09 01:13:24 PM PDT 24
Finished May 09 01:13:41 PM PDT 24
Peak memory 209816 kb
Host smart-4ca39c53-c16b-40e2-8924-38d8c9ba9b98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977058596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3977058596
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1927615093
Short name T603
Test name
Test status
Simulation time 1537085191 ps
CPU time 21.38 seconds
Started May 09 01:13:24 PM PDT 24
Finished May 09 01:13:46 PM PDT 24
Peak memory 218116 kb
Host smart-1f168916-d8b0-41b4-94ac-ec6fe7a5dad1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927615093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1927615093
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1453948446
Short name T535
Test name
Test status
Simulation time 748579308 ps
CPU time 2.2 seconds
Started May 09 01:13:19 PM PDT 24
Finished May 09 01:13:23 PM PDT 24
Peak memory 217396 kb
Host smart-6724bce0-e888-472d-ad8c-406ab78b079a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453948446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
453948446
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3175670267
Short name T630
Test name
Test status
Simulation time 1199839679 ps
CPU time 5.55 seconds
Started May 09 01:13:19 PM PDT 24
Finished May 09 01:13:26 PM PDT 24
Peak memory 218168 kb
Host smart-8182f5fc-2d30-4c8a-b77f-b6dd0dc4a18a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175670267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3175670267
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2454579650
Short name T627
Test name
Test status
Simulation time 657601796 ps
CPU time 20.63 seconds
Started May 09 01:13:22 PM PDT 24
Finished May 09 01:13:44 PM PDT 24
Peak memory 213280 kb
Host smart-1b320734-cd79-4931-995a-aba40d67bec3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454579650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2454579650
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1334434877
Short name T251
Test name
Test status
Simulation time 782476060 ps
CPU time 3.46 seconds
Started May 09 01:13:19 PM PDT 24
Finished May 09 01:13:24 PM PDT 24
Peak memory 213544 kb
Host smart-6d054ac7-e859-418c-8790-026127c81e06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334434877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1334434877
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1652121614
Short name T868
Test name
Test status
Simulation time 4064176117 ps
CPU time 37.29 seconds
Started May 09 01:13:20 PM PDT 24
Finished May 09 01:13:59 PM PDT 24
Peak memory 249432 kb
Host smart-52332677-ea5e-4cb0-ba1a-661c8b3fd87e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652121614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1652121614
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.686796808
Short name T34
Test name
Test status
Simulation time 650999836 ps
CPU time 17.6 seconds
Started May 09 01:13:18 PM PDT 24
Finished May 09 01:13:37 PM PDT 24
Peak memory 224260 kb
Host smart-3167e35a-57ee-4940-b779-b77e6673b571
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686796808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.686796808
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4232574174
Short name T12
Test name
Test status
Simulation time 186085626 ps
CPU time 2.39 seconds
Started May 09 01:13:19 PM PDT 24
Finished May 09 01:13:23 PM PDT 24
Peak memory 218176 kb
Host smart-82ee6614-70c4-4f80-9ecd-2aa45f2da6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232574174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4232574174
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1572507658
Short name T197
Test name
Test status
Simulation time 449464284 ps
CPU time 30.17 seconds
Started May 09 01:13:20 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 217944 kb
Host smart-0d6c3199-6dbd-4556-a3e8-34f0cdaf74ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572507658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1572507658
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.952756571
Short name T60
Test name
Test status
Simulation time 157098177 ps
CPU time 25.77 seconds
Started May 09 01:13:24 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 284288 kb
Host smart-61216b9c-d5bd-4b6d-896e-6c78cc2bcc31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952756571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.952756571
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2070714541
Short name T595
Test name
Test status
Simulation time 773814227 ps
CPU time 18.3 seconds
Started May 09 01:13:25 PM PDT 24
Finished May 09 01:13:45 PM PDT 24
Peak memory 218300 kb
Host smart-3dba1825-0d28-483e-bb91-52a03e2620f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070714541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2070714541
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2186062793
Short name T775
Test name
Test status
Simulation time 1231610260 ps
CPU time 11.86 seconds
Started May 09 01:13:20 PM PDT 24
Finished May 09 01:13:33 PM PDT 24
Peak memory 218184 kb
Host smart-d5bdd250-f84f-4dfa-9eee-b81ef2e1d11f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186062793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2186062793
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.577846437
Short name T291
Test name
Test status
Simulation time 647955398 ps
CPU time 9.99 seconds
Started May 09 01:13:26 PM PDT 24
Finished May 09 01:13:37 PM PDT 24
Peak memory 218056 kb
Host smart-e56b6b47-f46e-4cfe-8757-5b7b45ff0d17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577846437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.577846437
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3498306366
Short name T510
Test name
Test status
Simulation time 832256638 ps
CPU time 9.02 seconds
Started May 09 01:13:21 PM PDT 24
Finished May 09 01:13:32 PM PDT 24
Peak memory 218368 kb
Host smart-8745bfe5-831e-469b-b735-b36138e3c93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498306366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3498306366
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3259496258
Short name T35
Test name
Test status
Simulation time 393380908 ps
CPU time 3.51 seconds
Started May 09 01:13:13 PM PDT 24
Finished May 09 01:13:19 PM PDT 24
Peak memory 217972 kb
Host smart-a092a2c9-5e11-4bab-960d-c8e5b8ccca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259496258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3259496258
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4140073951
Short name T858
Test name
Test status
Simulation time 886669279 ps
CPU time 23.12 seconds
Started May 09 01:13:20 PM PDT 24
Finished May 09 01:13:45 PM PDT 24
Peak memory 249192 kb
Host smart-47b855a2-a623-452d-9fc7-4a2d1990b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140073951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4140073951
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.7069147
Short name T285
Test name
Test status
Simulation time 54043680 ps
CPU time 6.02 seconds
Started May 09 01:13:19 PM PDT 24
Finished May 09 01:13:27 PM PDT 24
Peak memory 246984 kb
Host smart-d41645dd-8ec4-4f93-ba93-b05eee479261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7069147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.7069147
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.553197395
Short name T533
Test name
Test status
Simulation time 58338538150 ps
CPU time 310.03 seconds
Started May 09 01:13:23 PM PDT 24
Finished May 09 01:18:34 PM PDT 24
Peak memory 280804 kb
Host smart-22ff81ce-c5f1-4499-b9fa-b20daab6efbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553197395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.553197395
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1974251153
Short name T682
Test name
Test status
Simulation time 38075820882 ps
CPU time 618.31 seconds
Started May 09 01:13:25 PM PDT 24
Finished May 09 01:23:45 PM PDT 24
Peak memory 284068 kb
Host smart-6b63bfee-f042-42cc-8bf3-2d49acc6cfad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1974251153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1974251153
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.251349887
Short name T283
Test name
Test status
Simulation time 11343398 ps
CPU time 0.88 seconds
Started May 09 01:13:26 PM PDT 24
Finished May 09 01:13:28 PM PDT 24
Peak memory 208096 kb
Host smart-f50f5690-8811-4013-a971-7178a0493d9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251349887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.251349887
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1144686094
Short name T869
Test name
Test status
Simulation time 22699386 ps
CPU time 0.91 seconds
Started May 09 01:15:23 PM PDT 24
Finished May 09 01:15:26 PM PDT 24
Peak memory 209780 kb
Host smart-2e301dee-b8c4-4086-9166-de22a1efd4da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144686094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1144686094
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1190433044
Short name T427
Test name
Test status
Simulation time 2077471352 ps
CPU time 13.21 seconds
Started May 09 01:15:23 PM PDT 24
Finished May 09 01:15:39 PM PDT 24
Peak memory 218084 kb
Host smart-d208b7c9-bc34-43c9-aeb2-150937972f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190433044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1190433044
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1293608726
Short name T28
Test name
Test status
Simulation time 2702603911 ps
CPU time 16.21 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 209876 kb
Host smart-b93bc062-1b77-4bf5-9cd9-edabdafc1e9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293608726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1293608726
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.940154307
Short name T581
Test name
Test status
Simulation time 30186185 ps
CPU time 2.13 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 218016 kb
Host smart-909d221a-1760-4c47-9d16-475ed96e7360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940154307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.940154307
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1986207072
Short name T584
Test name
Test status
Simulation time 2262044949 ps
CPU time 15.42 seconds
Started May 09 01:15:23 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 226320 kb
Host smart-fe7f5102-5061-44f1-8a90-03cfb574cb9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986207072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1986207072
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2130443429
Short name T305
Test name
Test status
Simulation time 373416558 ps
CPU time 14.74 seconds
Started May 09 01:15:26 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 218232 kb
Host smart-6e442720-5f77-47d1-8eef-3256ba6a1aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130443429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2130443429
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.145845745
Short name T434
Test name
Test status
Simulation time 352574796 ps
CPU time 7.93 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 218152 kb
Host smart-3acebe65-add5-43f8-82ea-639fb32b167b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145845745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.145845745
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.773731609
Short name T698
Test name
Test status
Simulation time 1070012948 ps
CPU time 7.21 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:37 PM PDT 24
Peak memory 218292 kb
Host smart-34639523-2924-40d0-b4a2-afc58b0aa114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773731609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.773731609
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.815423337
Short name T260
Test name
Test status
Simulation time 545426544 ps
CPU time 9.5 seconds
Started May 09 01:15:20 PM PDT 24
Finished May 09 01:15:31 PM PDT 24
Peak memory 215048 kb
Host smart-5deeef45-4e40-41b2-9915-41a1c7d1146d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815423337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.815423337
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3866488567
Short name T555
Test name
Test status
Simulation time 746250504 ps
CPU time 17.09 seconds
Started May 09 01:15:19 PM PDT 24
Finished May 09 01:15:38 PM PDT 24
Peak memory 251140 kb
Host smart-07c2db97-9447-4ce9-9c65-0caca21edd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866488567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3866488567
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.659723099
Short name T765
Test name
Test status
Simulation time 61113597 ps
CPU time 8.03 seconds
Started May 09 01:15:24 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 246444 kb
Host smart-33da3a29-f098-43dc-b9a2-9c66f4182640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659723099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.659723099
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.932186376
Short name T356
Test name
Test status
Simulation time 10539676118 ps
CPU time 50.97 seconds
Started May 09 01:15:26 PM PDT 24
Finished May 09 01:16:18 PM PDT 24
Peak memory 221144 kb
Host smart-89ccb2dd-9d2b-4c29-9824-62a81e2616d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932186376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.932186376
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2750019866
Short name T86
Test name
Test status
Simulation time 71108455 ps
CPU time 1.23 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 212944 kb
Host smart-86d931c8-9991-499b-a231-068a6f607797
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750019866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2750019866
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.4079900143
Short name T803
Test name
Test status
Simulation time 38620183 ps
CPU time 0.87 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:31 PM PDT 24
Peak memory 209820 kb
Host smart-8c2124aa-c589-4a66-93e2-48e7c43eca7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079900143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.4079900143
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2820310607
Short name T341
Test name
Test status
Simulation time 2114754229 ps
CPU time 13.1 seconds
Started May 09 01:15:21 PM PDT 24
Finished May 09 01:15:37 PM PDT 24
Peak memory 218200 kb
Host smart-e9e99cc2-9cf3-486b-9177-4029d8b24094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820310607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2820310607
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.4292466182
Short name T563
Test name
Test status
Simulation time 212695386 ps
CPU time 3.4 seconds
Started May 09 01:15:29 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 209824 kb
Host smart-568468a5-d43a-4a3f-b652-4ae29ea6270c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292466182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.4292466182
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4260530121
Short name T241
Test name
Test status
Simulation time 414941196 ps
CPU time 2.87 seconds
Started May 09 01:15:24 PM PDT 24
Finished May 09 01:15:29 PM PDT 24
Peak memory 218300 kb
Host smart-ebbd17f9-922a-42ae-8827-09516f667ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260530121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4260530121
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.712281753
Short name T676
Test name
Test status
Simulation time 349462335 ps
CPU time 15.09 seconds
Started May 09 01:15:29 PM PDT 24
Finished May 09 01:15:47 PM PDT 24
Peak memory 219156 kb
Host smart-0a25abbf-d207-466d-994a-e1008dc8181d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712281753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.712281753
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1412353384
Short name T44
Test name
Test status
Simulation time 468035891 ps
CPU time 15.59 seconds
Started May 09 01:15:29 PM PDT 24
Finished May 09 01:15:47 PM PDT 24
Peak memory 218136 kb
Host smart-9ee6bdb9-5815-4151-bcd1-829bda0a372f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412353384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1412353384
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4227254221
Short name T54
Test name
Test status
Simulation time 930773381 ps
CPU time 8.42 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:44 PM PDT 24
Peak memory 218256 kb
Host smart-55ff9787-10b4-41dc-a511-67283eedf4d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227254221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4227254221
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2850113180
Short name T673
Test name
Test status
Simulation time 275607164 ps
CPU time 11.18 seconds
Started May 09 01:15:27 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 218352 kb
Host smart-a80c6877-61ce-4727-8a1c-eec1a767b53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850113180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2850113180
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1509544707
Short name T637
Test name
Test status
Simulation time 47484501 ps
CPU time 2.35 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:33 PM PDT 24
Peak memory 214236 kb
Host smart-b085c4ee-284a-45e9-883f-6779e91cbd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509544707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1509544707
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3662282816
Short name T238
Test name
Test status
Simulation time 690096434 ps
CPU time 31.87 seconds
Started May 09 01:15:26 PM PDT 24
Finished May 09 01:15:59 PM PDT 24
Peak memory 251196 kb
Host smart-4680f9ab-10c2-4aa7-9bff-792a2347b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662282816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3662282816
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1271075688
Short name T394
Test name
Test status
Simulation time 103308851 ps
CPU time 8.27 seconds
Started May 09 01:15:26 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 251084 kb
Host smart-62b509c4-8f5e-421d-8763-d5fbb4266457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271075688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1271075688
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2988264565
Short name T558
Test name
Test status
Simulation time 14206752450 ps
CPU time 79.04 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:16:51 PM PDT 24
Peak memory 273252 kb
Host smart-3ad55d71-c6e0-4067-a601-350a5f42e1cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988264565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2988264565
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3017020239
Short name T388
Test name
Test status
Simulation time 36315060 ps
CPU time 1.01 seconds
Started May 09 01:15:26 PM PDT 24
Finished May 09 01:15:28 PM PDT 24
Peak memory 211904 kb
Host smart-0eb08656-ec87-4cf9-b6c8-3edb3953c791
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017020239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3017020239
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.4282281437
Short name T287
Test name
Test status
Simulation time 31481715 ps
CPU time 0.92 seconds
Started May 09 01:15:27 PM PDT 24
Finished May 09 01:15:30 PM PDT 24
Peak memory 209824 kb
Host smart-29e56b2d-d293-436e-b320-7ba8317e3581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282281437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.4282281437
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1801928231
Short name T243
Test name
Test status
Simulation time 1909890566 ps
CPU time 15.72 seconds
Started May 09 01:15:29 PM PDT 24
Finished May 09 01:15:48 PM PDT 24
Peak memory 218232 kb
Host smart-d2c9f25f-bd46-487f-8e10-a9ee60e4d661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801928231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1801928231
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.680476004
Short name T643
Test name
Test status
Simulation time 1028547173 ps
CPU time 23.27 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:59 PM PDT 24
Peak memory 217612 kb
Host smart-89a6904f-c9f1-481a-8007-2e438df97d2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680476004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.680476004
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.594179781
Short name T544
Test name
Test status
Simulation time 386532535 ps
CPU time 2.76 seconds
Started May 09 01:15:29 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 218156 kb
Host smart-f5b2f9c4-4073-4d27-9220-0536a65a50c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594179781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.594179781
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2876775939
Short name T538
Test name
Test status
Simulation time 1419823714 ps
CPU time 11.98 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:44 PM PDT 24
Peak memory 226212 kb
Host smart-43778c67-4256-4ec7-b7a6-25533095543b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876775939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2876775939
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1265119435
Short name T534
Test name
Test status
Simulation time 217137842 ps
CPU time 8.75 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 218108 kb
Host smart-8bde79ea-72ba-4cfd-beb8-0e9f7397ffa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265119435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1265119435
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.548956613
Short name T446
Test name
Test status
Simulation time 610987008 ps
CPU time 9.37 seconds
Started May 09 01:15:27 PM PDT 24
Finished May 09 01:15:38 PM PDT 24
Peak memory 218256 kb
Host smart-17caae99-0b15-422b-ac21-d6801a8937e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548956613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.548956613
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1420726957
Short name T227
Test name
Test status
Simulation time 233067386 ps
CPU time 10.43 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 218332 kb
Host smart-bde7c691-3523-45cc-bc9c-d175a7adf360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420726957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1420726957
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3883641581
Short name T174
Test name
Test status
Simulation time 84142804 ps
CPU time 2.91 seconds
Started May 09 01:15:33 PM PDT 24
Finished May 09 01:15:38 PM PDT 24
Peak memory 214256 kb
Host smart-3368dc0f-4e11-4bc9-9354-80e2c904c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883641581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3883641581
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.207116078
Short name T165
Test name
Test status
Simulation time 361602856 ps
CPU time 3.03 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:39 PM PDT 24
Peak memory 222564 kb
Host smart-6a25d393-26c8-4cfd-8a54-3a09076eb53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207116078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.207116078
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3235670032
Short name T52
Test name
Test status
Simulation time 77201182000 ps
CPU time 107.96 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:17:21 PM PDT 24
Peak memory 239304 kb
Host smart-035c9ee3-1d94-4e2d-95ec-fba98bd5ea9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235670032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3235670032
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1330218940
Short name T144
Test name
Test status
Simulation time 321283312099 ps
CPU time 809.07 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:28:59 PM PDT 24
Peak memory 279784 kb
Host smart-7b37bccd-256f-4d4b-bdaa-a72682d2769d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1330218940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.1330218940
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.524404025
Short name T348
Test name
Test status
Simulation time 124116243 ps
CPU time 0.82 seconds
Started May 09 01:15:29 PM PDT 24
Finished May 09 01:15:32 PM PDT 24
Peak memory 208844 kb
Host smart-5dcbab6a-1571-459e-87a7-f9fdc0e8157c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524404025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.524404025
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2037710278
Short name T88
Test name
Test status
Simulation time 68744868 ps
CPU time 1.14 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:32 PM PDT 24
Peak memory 209840 kb
Host smart-191c4826-2a4c-4fd3-a155-c2439165cfdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037710278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2037710278
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2097739549
Short name T502
Test name
Test status
Simulation time 604981113 ps
CPU time 9.2 seconds
Started May 09 01:15:27 PM PDT 24
Finished May 09 01:15:37 PM PDT 24
Peak memory 218284 kb
Host smart-411dd4c7-d197-44dd-8538-5431e887c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097739549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2097739549
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.229336926
Short name T10
Test name
Test status
Simulation time 395637227 ps
CPU time 6.19 seconds
Started May 09 01:15:26 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 209812 kb
Host smart-f1751aea-4c77-43ff-8712-64d3f6a0dae6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229336926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.229336926
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2340031948
Short name T448
Test name
Test status
Simulation time 101344690 ps
CPU time 3.08 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 218236 kb
Host smart-5c7dbadb-3946-4009-a5e6-175a2498c225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340031948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2340031948
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1033831989
Short name T489
Test name
Test status
Simulation time 1084455478 ps
CPU time 14.01 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:44 PM PDT 24
Peak memory 218152 kb
Host smart-cf6ba4c4-a7e3-48c3-adce-63f6d5d8e153
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033831989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1033831989
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2966912111
Short name T67
Test name
Test status
Simulation time 1109782771 ps
CPU time 9.36 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 218228 kb
Host smart-72d46a3c-d025-4c01-aee0-0aa506921640
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966912111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2966912111
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3214794703
Short name T466
Test name
Test status
Simulation time 761491024 ps
CPU time 14.36 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 218260 kb
Host smart-8db412f3-d875-45e3-83ed-5f34c5af0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214794703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3214794703
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.707539594
Short name T372
Test name
Test status
Simulation time 84934167 ps
CPU time 2.54 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:32 PM PDT 24
Peak memory 218000 kb
Host smart-f633b36c-3887-4653-b676-18bc2593dda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707539594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.707539594
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1085134474
Short name T371
Test name
Test status
Simulation time 182772926 ps
CPU time 17.57 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 251204 kb
Host smart-5531b7bc-dd3f-4587-95b6-ed70f11c0562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085134474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1085134474
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3404732504
Short name T323
Test name
Test status
Simulation time 63263629 ps
CPU time 3.74 seconds
Started May 09 01:15:35 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 222544 kb
Host smart-9d4235a6-0055-4da1-9faf-e7945256b10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404732504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3404732504
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.866475509
Short name T369
Test name
Test status
Simulation time 13550263827 ps
CPU time 117.83 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:17:35 PM PDT 24
Peak memory 284036 kb
Host smart-8919d972-f85c-48f9-ab4e-660164e0d225
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866475509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.866475509
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2061359462
Short name T168
Test name
Test status
Simulation time 33753971536 ps
CPU time 778.61 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:28:32 PM PDT 24
Peak memory 389512 kb
Host smart-d30d6195-5b27-4d4c-a849-e78993ca2822
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2061359462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2061359462
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1597166864
Short name T367
Test name
Test status
Simulation time 70470567 ps
CPU time 1.04 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 213084 kb
Host smart-9518d638-bbe5-414c-9ce3-300c59da6e5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597166864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1597166864
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2034434217
Short name T479
Test name
Test status
Simulation time 22935884 ps
CPU time 1.21 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:39 PM PDT 24
Peak memory 209124 kb
Host smart-c1640ab9-2a7a-454c-9dda-4e22fb690f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034434217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2034434217
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2480646142
Short name T460
Test name
Test status
Simulation time 615583768 ps
CPU time 10.48 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:47 PM PDT 24
Peak memory 218248 kb
Host smart-cbfb3036-c7e4-4679-bc25-50ca7fae1324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480646142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2480646142
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3283521550
Short name T709
Test name
Test status
Simulation time 2132659978 ps
CPU time 13.97 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:44 PM PDT 24
Peak memory 209768 kb
Host smart-96ab7237-ce9c-4aba-8948-31b41c972dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283521550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3283521550
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4101808348
Short name T398
Test name
Test status
Simulation time 341987904 ps
CPU time 1.83 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 218116 kb
Host smart-3876d0e3-4b39-4f27-bdfa-26e25e3cadae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101808348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4101808348
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.297177200
Short name T276
Test name
Test status
Simulation time 2095061402 ps
CPU time 15.56 seconds
Started May 09 01:15:35 PM PDT 24
Finished May 09 01:15:53 PM PDT 24
Peak memory 218440 kb
Host smart-47f32c12-cbf5-4577-8261-d00d5f0b128a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297177200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.297177200
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3006344802
Short name T697
Test name
Test status
Simulation time 577847538 ps
CPU time 19.57 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:52 PM PDT 24
Peak memory 218176 kb
Host smart-826e6cd5-3324-4f5a-98e2-34811b6d6a08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006344802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3006344802
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.899510577
Short name T861
Test name
Test status
Simulation time 1222360633 ps
CPU time 11.7 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 218304 kb
Host smart-b55cf63f-634b-49c6-9479-12bbb7e3e645
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899510577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.899510577
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.373605032
Short name T33
Test name
Test status
Simulation time 719540511 ps
CPU time 8.09 seconds
Started May 09 01:15:33 PM PDT 24
Finished May 09 01:15:43 PM PDT 24
Peak memory 218304 kb
Host smart-85e01e34-faa7-4730-99ac-af145da6b1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373605032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.373605032
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.849057951
Short name T668
Test name
Test status
Simulation time 174593526 ps
CPU time 9.51 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 218020 kb
Host smart-4e09a79d-e84d-4baa-a654-34e6d77254e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849057951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.849057951
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1904663967
Short name T819
Test name
Test status
Simulation time 169505292 ps
CPU time 19.74 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:53 PM PDT 24
Peak memory 246144 kb
Host smart-12598845-1c04-4d35-b9c6-625577c163f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904663967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1904663967
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3835923426
Short name T471
Test name
Test status
Simulation time 286117858 ps
CPU time 6.95 seconds
Started May 09 01:15:34 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 246312 kb
Host smart-3c6c1813-aaf0-470e-a49c-8b0f7897ec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835923426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3835923426
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4139512357
Short name T518
Test name
Test status
Simulation time 11067241634 ps
CPU time 250.89 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:19:43 PM PDT 24
Peak memory 275420 kb
Host smart-9a4efe10-540e-4df1-a3f4-68508dd7b00c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139512357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4139512357
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.932502537
Short name T244
Test name
Test status
Simulation time 23161488 ps
CPU time 1.21 seconds
Started May 09 01:15:31 PM PDT 24
Finished May 09 01:15:34 PM PDT 24
Peak memory 213240 kb
Host smart-fd8fdec5-70f6-4385-8cde-7f5f9124c33f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932502537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.932502537
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1386507934
Short name T716
Test name
Test status
Simulation time 14713573 ps
CPU time 1.05 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:39 PM PDT 24
Peak memory 209764 kb
Host smart-4d383365-d49b-4c13-9ad6-67bf4d897c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386507934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1386507934
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1652378609
Short name T286
Test name
Test status
Simulation time 488705446 ps
CPU time 12.58 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:51 PM PDT 24
Peak memory 218152 kb
Host smart-0d9cc9fe-b6eb-438f-93f5-7eede053fc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652378609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1652378609
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2176326490
Short name T560
Test name
Test status
Simulation time 260950403 ps
CPU time 3.74 seconds
Started May 09 01:15:35 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 209932 kb
Host smart-3718ce4b-6f6c-441e-920e-9eff76def027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176326490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2176326490
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.606408801
Short name T423
Test name
Test status
Simulation time 84924379 ps
CPU time 3.12 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:36 PM PDT 24
Peak memory 218120 kb
Host smart-03702a0c-9bd9-4c86-a0e9-957c0c9e0aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606408801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.606408801
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2295768126
Short name T829
Test name
Test status
Simulation time 528932799 ps
CPU time 12.03 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 218444 kb
Host smart-98ebca34-0305-4208-8728-64299829e237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295768126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2295768126
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1666802455
Short name T520
Test name
Test status
Simulation time 2452919900 ps
CPU time 11.81 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 218292 kb
Host smart-4415bf2f-7240-485c-8aeb-cae3893b39ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666802455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1666802455
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1262874311
Short name T400
Test name
Test status
Simulation time 287228902 ps
CPU time 8.81 seconds
Started May 09 01:15:35 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 218244 kb
Host smart-dc1379a4-723e-4c0c-91fb-121d427219d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262874311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1262874311
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.69670483
Short name T831
Test name
Test status
Simulation time 326672061 ps
CPU time 11.85 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 218308 kb
Host smart-63904e77-34d1-4804-9b8b-3c68e3a74aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69670483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.69670483
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.946881706
Short name T78
Test name
Test status
Simulation time 260425405 ps
CPU time 2.3 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:35 PM PDT 24
Peak memory 214276 kb
Host smart-9de461c6-b907-4521-8f37-138a1ae8d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946881706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.946881706
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3743928949
Short name T397
Test name
Test status
Simulation time 1077085904 ps
CPU time 30.19 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:16:08 PM PDT 24
Peak memory 251092 kb
Host smart-17e62bf6-0dc2-4468-a4c7-8d71ef1907bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743928949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3743928949
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.573917180
Short name T421
Test name
Test status
Simulation time 211062653 ps
CPU time 6.56 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 251216 kb
Host smart-fe00b9f6-b216-47d2-8fa0-0007928b58e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573917180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.573917180
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4112065900
Short name T48
Test name
Test status
Simulation time 2710013325 ps
CPU time 135.04 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:17:53 PM PDT 24
Peak memory 333180 kb
Host smart-e64a67a9-ed86-4628-bcb6-141572e061ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112065900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4112065900
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3504024915
Short name T109
Test name
Test status
Simulation time 72729623987 ps
CPU time 600.82 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:25:31 PM PDT 24
Peak memory 283976 kb
Host smart-4db68620-3bf4-4ac5-a020-a18cdc707f66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3504024915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3504024915
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.373274927
Short name T822
Test name
Test status
Simulation time 13114913 ps
CPU time 1.06 seconds
Started May 09 01:15:35 PM PDT 24
Finished May 09 01:15:38 PM PDT 24
Peak memory 211888 kb
Host smart-f4202635-66dc-4f32-bcde-b2dadc1e343c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373274927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.373274927
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.422475702
Short name T338
Test name
Test status
Simulation time 37279637 ps
CPU time 1 seconds
Started May 09 01:15:37 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 209792 kb
Host smart-530e301b-363d-4e07-84ee-a4c6b97cd2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422475702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.422475702
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2480466821
Short name T278
Test name
Test status
Simulation time 556019069 ps
CPU time 13.24 seconds
Started May 09 01:15:38 PM PDT 24
Finished May 09 01:15:52 PM PDT 24
Peak memory 218188 kb
Host smart-6b89c00d-d941-4a90-a1bc-968a96f06c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480466821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2480466821
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2782357988
Short name T723
Test name
Test status
Simulation time 752186434 ps
CPU time 4.42 seconds
Started May 09 01:15:28 PM PDT 24
Finished May 09 01:15:35 PM PDT 24
Peak memory 209804 kb
Host smart-abf5e9fa-080e-4c03-a810-cc699dc19f34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782357988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2782357988
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3668054117
Short name T272
Test name
Test status
Simulation time 174970331 ps
CPU time 2.4 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 218204 kb
Host smart-8f0ea10b-af2d-4d55-8246-e657c484da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668054117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3668054117
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1935495421
Short name T557
Test name
Test status
Simulation time 4455450134 ps
CPU time 9.84 seconds
Started May 09 01:15:37 PM PDT 24
Finished May 09 01:15:49 PM PDT 24
Peak memory 218448 kb
Host smart-7bb31540-ecb2-4125-8d84-4f98c24dd7c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935495421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1935495421
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.557023728
Short name T860
Test name
Test status
Simulation time 1930997276 ps
CPU time 20.09 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 218264 kb
Host smart-0a8b80b3-ff8e-417e-8148-5f623d6d68a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557023728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.557023728
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1313232263
Short name T282
Test name
Test status
Simulation time 1211401386 ps
CPU time 7.58 seconds
Started May 09 01:15:35 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 218216 kb
Host smart-4752ce39-8ab3-4876-9cb8-54c6448ea74f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313232263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1313232263
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4036204628
Short name T57
Test name
Test status
Simulation time 187527480 ps
CPU time 5.89 seconds
Started May 09 01:15:29 PM PDT 24
Finished May 09 01:15:37 PM PDT 24
Peak memory 218240 kb
Host smart-017c9221-17b2-4dc5-a1d9-2bb1cad6ea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036204628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4036204628
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1336398816
Short name T554
Test name
Test status
Simulation time 117374090 ps
CPU time 1.35 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 213532 kb
Host smart-c878bf08-456a-45f8-8e75-2e85f6843d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336398816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1336398816
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1589848672
Short name T503
Test name
Test status
Simulation time 980604257 ps
CPU time 19.73 seconds
Started May 09 01:15:35 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 250912 kb
Host smart-6de7c4dd-dea3-4e05-b467-76beb328c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589848672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1589848672
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.768372276
Short name T592
Test name
Test status
Simulation time 184752694 ps
CPU time 7.86 seconds
Started May 09 01:15:30 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 248484 kb
Host smart-a8713454-7cb3-4c6c-93ca-17eb04c810ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768372276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.768372276
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1574820196
Short name T661
Test name
Test status
Simulation time 854569325 ps
CPU time 17.3 seconds
Started May 09 01:15:36 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 218116 kb
Host smart-326cb95c-12df-4399-92d4-259b29b54479
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574820196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1574820196
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1204260903
Short name T750
Test name
Test status
Simulation time 14338507 ps
CPU time 0.97 seconds
Started May 09 01:15:37 PM PDT 24
Finished May 09 01:15:40 PM PDT 24
Peak memory 208840 kb
Host smart-b515cb3d-e259-4f87-a1b8-817a0d2d4c86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204260903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1204260903
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.941431777
Short name T748
Test name
Test status
Simulation time 41611480 ps
CPU time 0.96 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:44 PM PDT 24
Peak memory 209804 kb
Host smart-11ef6df4-5334-4e45-89b6-126e6260027b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941431777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.941431777
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.796095469
Short name T843
Test name
Test status
Simulation time 288533118 ps
CPU time 13.23 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:56 PM PDT 24
Peak memory 218200 kb
Host smart-c537d733-2701-4134-91e5-e385d7b12cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796095469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.796095469
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.58901133
Short name T804
Test name
Test status
Simulation time 123779469 ps
CPU time 1.96 seconds
Started May 09 01:15:38 PM PDT 24
Finished May 09 01:15:42 PM PDT 24
Peak memory 217120 kb
Host smart-180a574b-d523-405f-b75c-6e20aa7e2997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58901133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.58901133
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3940408513
Short name T537
Test name
Test status
Simulation time 130923491 ps
CPU time 2.57 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:43 PM PDT 24
Peak memory 218212 kb
Host smart-8967a0fd-e107-44b8-b1b6-483e81f59a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940408513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3940408513
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2315509512
Short name T467
Test name
Test status
Simulation time 246586117 ps
CPU time 11.48 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 219196 kb
Host smart-dcead32f-1f47-46bf-88b8-3f114cb9a86c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315509512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2315509512
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4240191557
Short name T422
Test name
Test status
Simulation time 2245667856 ps
CPU time 16.97 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:16:00 PM PDT 24
Peak memory 218300 kb
Host smart-e89b70a8-6ba1-4d34-9a45-140066d80236
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240191557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4240191557
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3074998000
Short name T800
Test name
Test status
Simulation time 2391173874 ps
CPU time 14.93 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:58 PM PDT 24
Peak memory 218288 kb
Host smart-4ca2458d-010a-48af-bf96-096def76c732
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074998000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3074998000
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3068610325
Short name T456
Test name
Test status
Simulation time 399122752 ps
CPU time 8.98 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:51 PM PDT 24
Peak memory 218280 kb
Host smart-48203005-ded4-4309-9813-2b6fa5258caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068610325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3068610325
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2102481055
Short name T607
Test name
Test status
Simulation time 26158182 ps
CPU time 1.75 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 213908 kb
Host smart-b106b70d-4cd4-4347-b50f-4ced1e5bb9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102481055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2102481055
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.724529045
Short name T236
Test name
Test status
Simulation time 2293849440 ps
CPU time 25.08 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:16:06 PM PDT 24
Peak memory 247284 kb
Host smart-7ed8e428-afdd-43a4-8051-342b9bdfeefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724529045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.724529045
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3416618484
Short name T837
Test name
Test status
Simulation time 253010396 ps
CPU time 3.28 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:43 PM PDT 24
Peak memory 222908 kb
Host smart-b146a55f-4c08-4b0a-8a8b-76fe9fdebfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416618484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3416618484
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.875031818
Short name T90
Test name
Test status
Simulation time 4491503511 ps
CPU time 23.88 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:16:06 PM PDT 24
Peak memory 220628 kb
Host smart-883ff00d-a118-4469-bf6d-2d812064d927
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875031818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.875031818
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.740803097
Short name T322
Test name
Test status
Simulation time 60083689 ps
CPU time 0.9 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:43 PM PDT 24
Peak memory 208892 kb
Host smart-0a6fc6fd-8566-4551-a521-ace7852e77bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740803097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.740803097
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1618666996
Short name T300
Test name
Test status
Simulation time 246090106 ps
CPU time 10.23 seconds
Started May 09 01:15:42 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 218304 kb
Host smart-4a11c7d1-eb3b-4411-85db-c3ff36cee43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618666996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1618666996
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.327017016
Short name T200
Test name
Test status
Simulation time 293665758 ps
CPU time 4.28 seconds
Started May 09 03:02:44 PM PDT 24
Finished May 09 03:02:51 PM PDT 24
Peak memory 209744 kb
Host smart-0b22f477-9043-45d7-bcf0-9895bf8927b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327017016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.327017016
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.109070482
Short name T622
Test name
Test status
Simulation time 96022195 ps
CPU time 3.68 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 218180 kb
Host smart-f8a4656e-f58d-4fec-8a38-54f9a87a5743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109070482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.109070482
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2392702620
Short name T249
Test name
Test status
Simulation time 352493634 ps
CPU time 15.22 seconds
Started May 09 02:48:52 PM PDT 24
Finished May 09 02:49:13 PM PDT 24
Peak memory 226368 kb
Host smart-d2547019-b427-4939-aedc-567d00355b20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392702620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2392702620
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1002432376
Short name T269
Test name
Test status
Simulation time 269596041 ps
CPU time 12.41 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:54 PM PDT 24
Peak memory 218212 kb
Host smart-e1dc6683-2c89-40f2-9274-3e1f607a41b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002432376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1002432376
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1482033573
Short name T506
Test name
Test status
Simulation time 387504951 ps
CPU time 13.51 seconds
Started May 09 03:32:05 PM PDT 24
Finished May 09 03:32:22 PM PDT 24
Peak memory 218184 kb
Host smart-bb156fdf-455e-443b-a118-daca1056363d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482033573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1482033573
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3125008631
Short name T402
Test name
Test status
Simulation time 234151455 ps
CPU time 5.62 seconds
Started May 09 03:56:28 PM PDT 24
Finished May 09 03:56:35 PM PDT 24
Peak memory 218392 kb
Host smart-af40abdf-2fc2-4e61-8df2-8ad4319f7352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125008631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3125008631
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3879126235
Short name T69
Test name
Test status
Simulation time 153463368 ps
CPU time 10.44 seconds
Started May 09 01:15:38 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 218028 kb
Host smart-4443d886-3c5d-4ac6-90f3-13e79b9417f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879126235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3879126235
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1399474577
Short name T773
Test name
Test status
Simulation time 1107491912 ps
CPU time 21.03 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:16:02 PM PDT 24
Peak memory 251212 kb
Host smart-bdc7e6a0-90be-428d-b95f-a14c1cecd16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399474577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1399474577
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3932881699
Short name T301
Test name
Test status
Simulation time 114611514 ps
CPU time 3.06 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 223700 kb
Host smart-12b43655-f828-4b04-bb09-b33533d97ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932881699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3932881699
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1031805376
Short name T312
Test name
Test status
Simulation time 20440494247 ps
CPU time 399.49 seconds
Started May 09 01:15:42 PM PDT 24
Finished May 09 01:22:24 PM PDT 24
Peak memory 284000 kb
Host smart-522247d0-e5dc-418c-8b7d-1377caeb3d84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031805376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1031805376
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1480684924
Short name T145
Test name
Test status
Simulation time 32425361358 ps
CPU time 1226.71 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:36:08 PM PDT 24
Peak memory 438736 kb
Host smart-43a8309a-9a72-4dc5-bcd2-28d8fe21f1e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1480684924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1480684924
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3045020514
Short name T429
Test name
Test status
Simulation time 44117326 ps
CPU time 1.03 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:45 PM PDT 24
Peak memory 211864 kb
Host smart-ab11f4cf-62f4-4680-8c1d-1b4445131ef5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045020514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3045020514
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.870199384
Short name T834
Test name
Test status
Simulation time 33073216 ps
CPU time 1.15 seconds
Started May 09 01:15:43 PM PDT 24
Finished May 09 01:15:46 PM PDT 24
Peak memory 209804 kb
Host smart-e5b4e9db-8f0c-43fe-b349-7008ab4b4b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870199384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.870199384
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1588273506
Short name T789
Test name
Test status
Simulation time 1740902381 ps
CPU time 13.35 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 218164 kb
Host smart-bb1441ee-629d-4f48-969e-24c7e6f83dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588273506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1588273506
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1315493818
Short name T719
Test name
Test status
Simulation time 1833509433 ps
CPU time 5.98 seconds
Started May 09 01:15:41 PM PDT 24
Finished May 09 01:15:49 PM PDT 24
Peak memory 209772 kb
Host smart-c45babc6-5f46-4d40-9d62-1c8a08c65b0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315493818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1315493818
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3395101284
Short name T812
Test name
Test status
Simulation time 125356011 ps
CPU time 3.81 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:44 PM PDT 24
Peak memory 218212 kb
Host smart-cf9112a1-1abd-4a9a-84ab-5a9e60c6b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395101284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3395101284
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2797229585
Short name T190
Test name
Test status
Simulation time 2448336370 ps
CPU time 16 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:57 PM PDT 24
Peak memory 219192 kb
Host smart-9f25cd43-9246-41a0-af6e-de510a5a5591
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797229585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2797229585
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3194332630
Short name T396
Test name
Test status
Simulation time 2205822266 ps
CPU time 12.75 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:55 PM PDT 24
Peak memory 218292 kb
Host smart-cbb5c01b-b5fc-4318-9381-7137514045b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194332630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3194332630
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2968319062
Short name T667
Test name
Test status
Simulation time 2043219179 ps
CPU time 9.1 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:51 PM PDT 24
Peak memory 218252 kb
Host smart-ac5e2055-db1f-4eee-8190-240d7fe9ca99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968319062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2968319062
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2201986893
Short name T462
Test name
Test status
Simulation time 238562505 ps
CPU time 9.28 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 218340 kb
Host smart-cd647394-c2a4-492f-9891-a14f8e13db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201986893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2201986893
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3426186481
Short name T509
Test name
Test status
Simulation time 145009061 ps
CPU time 2.04 seconds
Started May 09 01:15:45 PM PDT 24
Finished May 09 01:15:48 PM PDT 24
Peak memory 214060 kb
Host smart-e0876824-8ba8-48f1-a183-f4fbe8214930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426186481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3426186481
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2335452236
Short name T839
Test name
Test status
Simulation time 488001389 ps
CPU time 35.07 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:16:18 PM PDT 24
Peak memory 246828 kb
Host smart-2337eb7d-86fc-48cb-83e6-754ed08ad092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335452236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2335452236
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1589057018
Short name T419
Test name
Test status
Simulation time 125778436 ps
CPU time 8.06 seconds
Started May 09 01:15:40 PM PDT 24
Finished May 09 01:15:49 PM PDT 24
Peak memory 251180 kb
Host smart-791cd856-0ddf-410f-9b9c-c23687bb3ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589057018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1589057018
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2569938182
Short name T342
Test name
Test status
Simulation time 4406083276 ps
CPU time 158.33 seconds
Started May 09 01:15:43 PM PDT 24
Finished May 09 01:18:23 PM PDT 24
Peak memory 251776 kb
Host smart-571bd7d7-3964-442e-bc26-d65b991351ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569938182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2569938182
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4218195249
Short name T696
Test name
Test status
Simulation time 62463272 ps
CPU time 0.92 seconds
Started May 09 01:15:39 PM PDT 24
Finished May 09 01:15:41 PM PDT 24
Peak memory 213004 kb
Host smart-cd820609-c4ca-4ae5-94db-723f3afe70d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218195249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.4218195249
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1402779037
Short name T814
Test name
Test status
Simulation time 125833624 ps
CPU time 1.05 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:33 PM PDT 24
Peak memory 209728 kb
Host smart-f52b413f-da74-4f39-aff2-d02e7bbb3dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402779037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1402779037
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3810813227
Short name T864
Test name
Test status
Simulation time 2718405427 ps
CPU time 13.33 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:47 PM PDT 24
Peak memory 218212 kb
Host smart-30a0e8ff-8062-4d95-ae11-6d6b18ef67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810813227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3810813227
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1354449272
Short name T578
Test name
Test status
Simulation time 264892029 ps
CPU time 2.83 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:36 PM PDT 24
Peak memory 209720 kb
Host smart-d7ef4cf4-3f12-46f7-bcde-aefbafd819ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354449272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1354449272
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.4147607521
Short name T644
Test name
Test status
Simulation time 1462950339 ps
CPU time 27.17 seconds
Started May 09 01:13:38 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 218148 kb
Host smart-5ccb42e0-156e-40d6-88a4-c4b37bf019cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147607521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.4147607521
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2208030620
Short name T329
Test name
Test status
Simulation time 6338376622 ps
CPU time 5.79 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:40 PM PDT 24
Peak memory 217632 kb
Host smart-021d7d3f-8d14-441d-8b7b-6266a79acda2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208030620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
208030620
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1735978122
Short name T420
Test name
Test status
Simulation time 838181587 ps
CPU time 6.28 seconds
Started May 09 01:13:37 PM PDT 24
Finished May 09 01:13:45 PM PDT 24
Peak memory 218140 kb
Host smart-7c27be57-435a-42f1-8c54-7f89cef9f9c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735978122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1735978122
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2769174753
Short name T290
Test name
Test status
Simulation time 1322246906 ps
CPU time 8.92 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:43 PM PDT 24
Peak memory 213280 kb
Host smart-2f61fc09-3e04-48e3-8be1-af09685365a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769174753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2769174753
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3541764343
Short name T183
Test name
Test status
Simulation time 4122944766 ps
CPU time 14.16 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:47 PM PDT 24
Peak memory 214868 kb
Host smart-a920e12f-1469-4824-8df7-152f75737ee7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541764343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3541764343
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.64871630
Short name T407
Test name
Test status
Simulation time 1855532574 ps
CPU time 62.19 seconds
Started May 09 01:13:37 PM PDT 24
Finished May 09 01:14:40 PM PDT 24
Peak memory 278584 kb
Host smart-fd1819c0-b506-42ac-a746-aa7cc44230f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64871630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
state_failure.64871630
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1469571074
Short name T714
Test name
Test status
Simulation time 2880869709 ps
CPU time 24.94 seconds
Started May 09 01:13:29 PM PDT 24
Finished May 09 01:13:55 PM PDT 24
Peak memory 251068 kb
Host smart-075c0040-c830-4bf8-98f7-6a04357e9187
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469571074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1469571074
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3044078850
Short name T255
Test name
Test status
Simulation time 110785530 ps
CPU time 1.76 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:34 PM PDT 24
Peak memory 218204 kb
Host smart-51b16fbb-be4a-4a32-b6df-6d1152a9faa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044078850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3044078850
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.773742611
Short name T84
Test name
Test status
Simulation time 470850055 ps
CPU time 8.97 seconds
Started May 09 01:13:34 PM PDT 24
Finished May 09 01:13:45 PM PDT 24
Peak memory 214220 kb
Host smart-8497bd46-c662-42a1-b50b-3ad659fde25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773742611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.773742611
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1088173855
Short name T845
Test name
Test status
Simulation time 161118256 ps
CPU time 8.3 seconds
Started May 09 01:13:34 PM PDT 24
Finished May 09 01:13:43 PM PDT 24
Peak memory 218240 kb
Host smart-5fa8f0bb-b00c-4d87-9a36-b44dd15a1f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088173855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1088173855
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2120187379
Short name T514
Test name
Test status
Simulation time 302324361 ps
CPU time 10.68 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:45 PM PDT 24
Peak memory 218184 kb
Host smart-9430c44f-e731-44ea-bee8-823fc65fb930
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120187379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2120187379
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1892165307
Short name T66
Test name
Test status
Simulation time 538843202 ps
CPU time 7.14 seconds
Started May 09 01:13:39 PM PDT 24
Finished May 09 01:13:47 PM PDT 24
Peak memory 218080 kb
Host smart-6b87c3ad-e0ce-4f9e-a49d-f2a346a6e5a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892165307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
892165307
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.886166897
Short name T570
Test name
Test status
Simulation time 250412385 ps
CPU time 9.64 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:44 PM PDT 24
Peak memory 218280 kb
Host smart-38afaa4e-558e-4b9f-9154-1267eb52e1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886166897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.886166897
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2584830035
Short name T870
Test name
Test status
Simulation time 36345712 ps
CPU time 1.5 seconds
Started May 09 01:13:24 PM PDT 24
Finished May 09 01:13:27 PM PDT 24
Peak memory 213728 kb
Host smart-c428bd1e-2b89-47ec-9463-c71b732abe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584830035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2584830035
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4057121665
Short name T315
Test name
Test status
Simulation time 3614453933 ps
CPU time 29.02 seconds
Started May 09 01:13:26 PM PDT 24
Finished May 09 01:13:56 PM PDT 24
Peak memory 251084 kb
Host smart-4c1e68a9-e8a5-4ffd-9d55-38724aba4d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057121665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4057121665
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3200299796
Short name T546
Test name
Test status
Simulation time 144504568 ps
CPU time 8.13 seconds
Started May 09 01:13:23 PM PDT 24
Finished May 09 01:13:32 PM PDT 24
Peak memory 251200 kb
Host smart-63406e41-c0fa-460d-bf8a-5774a18d215c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200299796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3200299796
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2769285689
Short name T851
Test name
Test status
Simulation time 18312411846 ps
CPU time 100.98 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:15:14 PM PDT 24
Peak memory 278744 kb
Host smart-295a68bb-6c63-4204-9e06-bf6f62e8a97b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769285689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2769285689
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.204207460
Short name T428
Test name
Test status
Simulation time 13205687 ps
CPU time 0.78 seconds
Started May 09 01:13:23 PM PDT 24
Finished May 09 01:13:25 PM PDT 24
Peak memory 208808 kb
Host smart-358b1985-f8b5-42da-9bcc-5348b03500d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204207460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.204207460
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3732490400
Short name T662
Test name
Test status
Simulation time 17824351 ps
CPU time 0.9 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:35 PM PDT 24
Peak memory 209804 kb
Host smart-f1929c0f-8eb1-438f-9bc4-986df63871e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732490400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3732490400
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.75974198
Short name T225
Test name
Test status
Simulation time 97749983 ps
CPU time 0.9 seconds
Started May 09 01:13:30 PM PDT 24
Finished May 09 01:13:32 PM PDT 24
Peak memory 209796 kb
Host smart-c771dceb-952a-4783-b7fb-9bf26a8ae6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75974198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.75974198
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3278972891
Short name T464
Test name
Test status
Simulation time 172092047 ps
CPU time 8.88 seconds
Started May 09 01:13:36 PM PDT 24
Finished May 09 01:13:46 PM PDT 24
Peak memory 218180 kb
Host smart-167e13fd-3b45-42f2-b6fc-26196860b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278972891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3278972891
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.4147480997
Short name T871
Test name
Test status
Simulation time 737283693 ps
CPU time 17.82 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 209752 kb
Host smart-8ba25841-7167-4f74-a720-900d029edb90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147480997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.4147480997
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2322058595
Short name T732
Test name
Test status
Simulation time 2642989341 ps
CPU time 36.22 seconds
Started May 09 01:13:36 PM PDT 24
Finished May 09 01:14:14 PM PDT 24
Peak memory 218320 kb
Host smart-6b3e57e2-1d8e-403d-b649-b81c418fc0f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322058595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2322058595
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1196406012
Short name T718
Test name
Test status
Simulation time 755534563 ps
CPU time 8.66 seconds
Started May 09 01:13:33 PM PDT 24
Finished May 09 01:13:43 PM PDT 24
Peak memory 217820 kb
Host smart-3f8ad66e-536e-4136-a6d1-8e17c2fa12b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196406012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
196406012
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2822657220
Short name T248
Test name
Test status
Simulation time 4780226222 ps
CPU time 12.47 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:46 PM PDT 24
Peak memory 218360 kb
Host smart-dc51f774-1a61-457d-a615-648a2f60990e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822657220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2822657220
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1895277804
Short name T715
Test name
Test status
Simulation time 1567888239 ps
CPU time 23.76 seconds
Started May 09 01:13:34 PM PDT 24
Finished May 09 01:13:59 PM PDT 24
Peak memory 213364 kb
Host smart-b91fc981-2d6a-40b2-b164-71cad665c3ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895277804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1895277804
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4247435323
Short name T279
Test name
Test status
Simulation time 486647962 ps
CPU time 5.24 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:38 PM PDT 24
Peak memory 213464 kb
Host smart-412670b1-5a60-43b5-9e5e-46fbe4c92508
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247435323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4247435323
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1929786361
Short name T768
Test name
Test status
Simulation time 3755223992 ps
CPU time 68.02 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:14:42 PM PDT 24
Peak memory 267592 kb
Host smart-42584e52-64ee-465c-887a-06789f1866c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929786361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1929786361
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.600508796
Short name T365
Test name
Test status
Simulation time 1050919368 ps
CPU time 5.91 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:40 PM PDT 24
Peak memory 218172 kb
Host smart-a3f5bbf5-915d-43ee-a568-78efb34bb284
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600508796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.600508796
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1193851394
Short name T828
Test name
Test status
Simulation time 106884884 ps
CPU time 1.43 seconds
Started May 09 01:13:33 PM PDT 24
Finished May 09 01:13:36 PM PDT 24
Peak memory 218164 kb
Host smart-25ee5f9d-c50b-45dd-a5f6-2f570f56f3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193851394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1193851394
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3186887820
Short name T196
Test name
Test status
Simulation time 1125845079 ps
CPU time 18.34 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:52 PM PDT 24
Peak memory 214732 kb
Host smart-6140c62f-a45a-441f-a2a5-37b1a18be7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186887820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3186887820
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2241179761
Short name T176
Test name
Test status
Simulation time 585217739 ps
CPU time 8.82 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:42 PM PDT 24
Peak memory 218248 kb
Host smart-45ac0bd2-18b8-49cd-884a-f0c27f39cb95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241179761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2241179761
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4030155583
Short name T374
Test name
Test status
Simulation time 1256757239 ps
CPU time 9.09 seconds
Started May 09 01:13:38 PM PDT 24
Finished May 09 01:13:48 PM PDT 24
Peak memory 218152 kb
Host smart-60b9771c-abeb-4d89-8c99-60a7c298d331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030155583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4030155583
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.760842629
Short name T333
Test name
Test status
Simulation time 248486768 ps
CPU time 9.72 seconds
Started May 09 01:13:37 PM PDT 24
Finished May 09 01:13:48 PM PDT 24
Peak memory 218216 kb
Host smart-fac795a7-fe7a-4d39-b12f-7899cd324aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760842629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.760842629
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.682495595
Short name T228
Test name
Test status
Simulation time 1294875099 ps
CPU time 8.19 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:43 PM PDT 24
Peak memory 218276 kb
Host smart-5ba7e041-3384-45b2-a7a1-84e49867da77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682495595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.682495595
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1616492856
Short name T334
Test name
Test status
Simulation time 40277918 ps
CPU time 1.44 seconds
Started May 09 01:13:37 PM PDT 24
Finished May 09 01:13:40 PM PDT 24
Peak memory 213672 kb
Host smart-a1281cf6-ea6f-48e9-9c72-1a0a674cc1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616492856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1616492856
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1875308520
Short name T177
Test name
Test status
Simulation time 626161017 ps
CPU time 31.78 seconds
Started May 09 01:13:38 PM PDT 24
Finished May 09 01:14:11 PM PDT 24
Peak memory 248844 kb
Host smart-d087df9d-39d7-411d-92f6-96c51ae4f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875308520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1875308520
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2719286238
Short name T781
Test name
Test status
Simulation time 63038161 ps
CPU time 6.52 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:41 PM PDT 24
Peak memory 250592 kb
Host smart-18429879-130f-4278-b36a-f35a635ed56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719286238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2719286238
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1504166984
Short name T568
Test name
Test status
Simulation time 16063548086 ps
CPU time 74.07 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 251060 kb
Host smart-40a9b550-34de-4416-8a62-11d221998432
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504166984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1504166984
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2323872123
Short name T726
Test name
Test status
Simulation time 23428267 ps
CPU time 0.93 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:35 PM PDT 24
Peak memory 211848 kb
Host smart-10de56f5-4a2a-4a51-8e01-6b4d76ff303d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323872123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2323872123
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.252031987
Short name T694
Test name
Test status
Simulation time 21520777 ps
CPU time 0.89 seconds
Started May 09 01:13:41 PM PDT 24
Finished May 09 01:13:43 PM PDT 24
Peak memory 209728 kb
Host smart-691fff8b-e228-4300-8d95-c359ff207373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252031987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.252031987
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3070308800
Short name T252
Test name
Test status
Simulation time 17779197 ps
CPU time 0.85 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:13:47 PM PDT 24
Peak memory 209648 kb
Host smart-76c6e9d1-af8c-470e-8b68-98cf4d9ff7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070308800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3070308800
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1759039654
Short name T854
Test name
Test status
Simulation time 1146439199 ps
CPU time 7.88 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:13:56 PM PDT 24
Peak memory 218304 kb
Host smart-23c3939f-e8e7-408c-b7fe-f16148067b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759039654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1759039654
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.988905522
Short name T27
Test name
Test status
Simulation time 111578294 ps
CPU time 2.1 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:13:48 PM PDT 24
Peak memory 209840 kb
Host smart-e2bba69e-4cbd-48a5-975e-cdd31a7dd855
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988905522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.988905522
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.570335427
Short name T541
Test name
Test status
Simulation time 3005823877 ps
CPU time 82.53 seconds
Started May 09 01:13:42 PM PDT 24
Finished May 09 01:15:05 PM PDT 24
Peak memory 219112 kb
Host smart-8fd7d918-5102-461f-8f79-c52406b8be54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570335427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.570335427
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.106892181
Short name T472
Test name
Test status
Simulation time 948744395 ps
CPU time 6.59 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:13:55 PM PDT 24
Peak memory 217516 kb
Host smart-1c93ba65-4f09-43ec-8f7f-7fbca69acf13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106892181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.106892181
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1927642184
Short name T293
Test name
Test status
Simulation time 1659055968 ps
CPU time 13.19 seconds
Started May 09 01:13:47 PM PDT 24
Finished May 09 01:14:02 PM PDT 24
Peak memory 218236 kb
Host smart-f3cc94a1-3b0c-455b-92c9-99bb14949e63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927642184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1927642184
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3427225535
Short name T776
Test name
Test status
Simulation time 11674489279 ps
CPU time 33.99 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:14:22 PM PDT 24
Peak memory 214312 kb
Host smart-de20e405-6645-4b04-93bc-e02681990ce2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427225535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3427225535
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.281605267
Short name T21
Test name
Test status
Simulation time 261820162 ps
CPU time 8.21 seconds
Started May 09 01:13:43 PM PDT 24
Finished May 09 01:13:52 PM PDT 24
Peak memory 214016 kb
Host smart-b226758b-60bc-4097-88c1-1b6a4f35e68a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281605267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.281605267
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1171676892
Short name T452
Test name
Test status
Simulation time 1546771864 ps
CPU time 59.96 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:14:49 PM PDT 24
Peak memory 251160 kb
Host smart-637e8d13-6e7c-4a69-a121-7a86645c120d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171676892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1171676892
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2821790647
Short name T624
Test name
Test status
Simulation time 1802481664 ps
CPU time 14.72 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:14:02 PM PDT 24
Peak memory 251084 kb
Host smart-542027c1-0102-4713-ad0e-0f38eee9550a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821790647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2821790647
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1138281809
Short name T297
Test name
Test status
Simulation time 61858123 ps
CPU time 3.34 seconds
Started May 09 01:13:37 PM PDT 24
Finished May 09 01:13:42 PM PDT 24
Peak memory 218276 kb
Host smart-ff876086-0398-411b-9ecc-867bd78978c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138281809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1138281809
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2514192636
Short name T332
Test name
Test status
Simulation time 1140934247 ps
CPU time 16.81 seconds
Started May 09 01:13:48 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 214652 kb
Host smart-91513f26-7938-4086-8c39-263e3df933bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514192636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2514192636
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.100684310
Short name T559
Test name
Test status
Simulation time 824765934 ps
CPU time 9.6 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:13:58 PM PDT 24
Peak memory 218248 kb
Host smart-d484ff39-ba91-45bb-b13e-693f1fddd51b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100684310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.100684310
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3547927313
Short name T670
Test name
Test status
Simulation time 2156857414 ps
CPU time 12.41 seconds
Started May 09 01:13:41 PM PDT 24
Finished May 09 01:13:54 PM PDT 24
Peak memory 218320 kb
Host smart-0bc7e208-e74c-4d74-acdb-220b77f3945a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547927313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3547927313
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1523089825
Short name T389
Test name
Test status
Simulation time 1017134528 ps
CPU time 10.72 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:13:59 PM PDT 24
Peak memory 218220 kb
Host smart-a5210c95-7f09-4414-b045-d7d47537f79e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523089825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
523089825
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3592356693
Short name T783
Test name
Test status
Simulation time 470825443 ps
CPU time 9.02 seconds
Started May 09 01:13:43 PM PDT 24
Finished May 09 01:13:53 PM PDT 24
Peak memory 218256 kb
Host smart-afb65d39-0cf4-4c6f-b6b1-e561a4d92c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592356693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3592356693
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3427116245
Short name T741
Test name
Test status
Simulation time 72516773 ps
CPU time 2.85 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:37 PM PDT 24
Peak memory 214652 kb
Host smart-199473c9-aa51-48de-a15d-4258f9226f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427116245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3427116245
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1263100289
Short name T699
Test name
Test status
Simulation time 268188417 ps
CPU time 23.39 seconds
Started May 09 01:13:32 PM PDT 24
Finished May 09 01:13:57 PM PDT 24
Peak memory 251180 kb
Host smart-b909c6d6-17bd-48d5-a066-705b2aa72077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263100289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1263100289
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1627071140
Short name T491
Test name
Test status
Simulation time 147781880 ps
CPU time 8.72 seconds
Started May 09 01:13:31 PM PDT 24
Finished May 09 01:13:42 PM PDT 24
Peak memory 250840 kb
Host smart-9d6e56e1-aa2a-4323-9b38-fdeb6b137cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627071140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1627071140
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.27810150
Short name T615
Test name
Test status
Simulation time 6592419305 ps
CPU time 45.67 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:14:33 PM PDT 24
Peak memory 226396 kb
Host smart-93a9940a-b1b6-4291-87c8-65c9bf3f036c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27810150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.lc_ctrl_stress_all.27810150
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2205056593
Short name T821
Test name
Test status
Simulation time 44513059 ps
CPU time 0.75 seconds
Started May 09 01:13:33 PM PDT 24
Finished May 09 01:13:35 PM PDT 24
Peak memory 208672 kb
Host smart-533dc739-4d4c-471d-a83c-f7999a7aaf13
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205056593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2205056593
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3942230432
Short name T191
Test name
Test status
Simulation time 58954318 ps
CPU time 1.07 seconds
Started May 09 01:13:47 PM PDT 24
Finished May 09 01:13:50 PM PDT 24
Peak memory 209792 kb
Host smart-60f5b3f6-acae-4f41-a330-be2acc052e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942230432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3942230432
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3201812188
Short name T626
Test name
Test status
Simulation time 1018271080 ps
CPU time 13.15 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:14:01 PM PDT 24
Peak memory 218304 kb
Host smart-7952f1b1-55fd-4a8d-af13-325efbb30b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201812188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3201812188
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2786791999
Short name T725
Test name
Test status
Simulation time 4664656025 ps
CPU time 12.98 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:14:01 PM PDT 24
Peak memory 209864 kb
Host smart-31837a72-d7b1-4427-93cb-48b516dea825
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786791999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2786791999
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.727240443
Short name T683
Test name
Test status
Simulation time 2688601275 ps
CPU time 21.67 seconds
Started May 09 01:13:40 PM PDT 24
Finished May 09 01:14:03 PM PDT 24
Peak memory 218164 kb
Host smart-f4851911-b14d-4f1f-ac72-48230ad425c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727240443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.727240443
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.24226134
Short name T71
Test name
Test status
Simulation time 329862946 ps
CPU time 2.02 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 217268 kb
Host smart-88143d74-c676-44c4-90d0-c2d5be2ad652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24226134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.24226134
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2200185660
Short name T408
Test name
Test status
Simulation time 73227804 ps
CPU time 1.87 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:50 PM PDT 24
Peak memory 218140 kb
Host smart-f61dcc41-644a-48eb-94d8-37e9ea81756f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200185660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2200185660
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2233594593
Short name T74
Test name
Test status
Simulation time 2845983386 ps
CPU time 31.59 seconds
Started May 09 01:13:43 PM PDT 24
Finished May 09 01:14:16 PM PDT 24
Peak memory 213880 kb
Host smart-9c1a8069-8c3e-47c5-91f0-2dd69f2a46e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233594593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2233594593
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1901250029
Short name T770
Test name
Test status
Simulation time 544863782 ps
CPU time 7.11 seconds
Started May 09 01:13:41 PM PDT 24
Finished May 09 01:13:49 PM PDT 24
Peak memory 213812 kb
Host smart-d7f07b6d-76b9-4df4-81fc-8a716c2c366c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901250029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1901250029
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.95743433
Short name T271
Test name
Test status
Simulation time 8969229093 ps
CPU time 72.15 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:15:00 PM PDT 24
Peak memory 273684 kb
Host smart-487379e9-dd4d-42f9-8d03-ebfde51de015
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95743433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
state_failure.95743433
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2612557076
Short name T749
Test name
Test status
Simulation time 994436027 ps
CPU time 12.63 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:14:01 PM PDT 24
Peak memory 245796 kb
Host smart-c9b8eedf-2448-4c40-a4c1-385f93bc71d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612557076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2612557076
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2317983831
Short name T654
Test name
Test status
Simulation time 79879091 ps
CPU time 2.59 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:50 PM PDT 24
Peak memory 218080 kb
Host smart-ad9331fd-892a-45ff-9760-0d3b7d695d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317983831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2317983831
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4267099317
Short name T81
Test name
Test status
Simulation time 1118028112 ps
CPU time 5.63 seconds
Started May 09 01:13:43 PM PDT 24
Finished May 09 01:13:49 PM PDT 24
Peak memory 217892 kb
Host smart-14c5f217-10e3-41aa-8e05-7f1729191eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267099317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4267099317
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.288030417
Short name T751
Test name
Test status
Simulation time 534779483 ps
CPU time 23.17 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:14:11 PM PDT 24
Peak memory 226268 kb
Host smart-25d9ce45-8fee-4fb1-b5d3-700654fa99f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288030417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.288030417
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2632494848
Short name T284
Test name
Test status
Simulation time 322081796 ps
CPU time 8.31 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:56 PM PDT 24
Peak memory 218304 kb
Host smart-581032b6-8c38-4196-8bba-904a20428a85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632494848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2632494848
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.124413606
Short name T409
Test name
Test status
Simulation time 1225605435 ps
CPU time 12.73 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:13:58 PM PDT 24
Peak memory 218136 kb
Host smart-ce563c1e-629f-4fb2-8fe7-b50f2721c978
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124413606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.124413606
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.476273291
Short name T766
Test name
Test status
Simulation time 341088764 ps
CPU time 10 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:13:55 PM PDT 24
Peak memory 218284 kb
Host smart-7a3eff03-e1b8-456b-971f-d0f9bb14af2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476273291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.476273291
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1027775228
Short name T38
Test name
Test status
Simulation time 44434312 ps
CPU time 3.16 seconds
Started May 09 01:13:49 PM PDT 24
Finished May 09 01:13:53 PM PDT 24
Peak memory 214888 kb
Host smart-3e6946bf-544d-4241-99df-3678871357b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027775228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1027775228
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2974898572
Short name T355
Test name
Test status
Simulation time 4306314850 ps
CPU time 32.54 seconds
Started May 09 01:13:41 PM PDT 24
Finished May 09 01:14:15 PM PDT 24
Peak memory 251100 kb
Host smart-38f46732-b22d-4ad0-bf8e-e2e5ebabb2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974898572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2974898572
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1658255681
Short name T399
Test name
Test status
Simulation time 118775316 ps
CPU time 8.21 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:55 PM PDT 24
Peak memory 251212 kb
Host smart-c2d5390a-ee9c-497b-a7c3-11048133628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658255681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1658255681
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3813741399
Short name T499
Test name
Test status
Simulation time 21597034 ps
CPU time 1.02 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:48 PM PDT 24
Peak memory 211776 kb
Host smart-9e3e2ee5-3ad7-4069-bbd3-b0e1e895abc9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813741399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3813741399
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2066812418
Short name T178
Test name
Test status
Simulation time 53703937 ps
CPU time 0.92 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:14:01 PM PDT 24
Peak memory 209724 kb
Host smart-bd88f866-a45c-47f5-84da-9a45c5a62537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066812418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2066812418
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1432340791
Short name T516
Test name
Test status
Simulation time 24758001 ps
CPU time 0.82 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:48 PM PDT 24
Peak memory 209604 kb
Host smart-9c1b1856-59d9-4b97-897c-b4efeb078c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432340791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1432340791
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1503200748
Short name T172
Test name
Test status
Simulation time 796692741 ps
CPU time 10.74 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:58 PM PDT 24
Peak memory 218128 kb
Host smart-e15260c5-7b71-4419-afd3-54a06f46712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503200748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1503200748
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1868895460
Short name T245
Test name
Test status
Simulation time 476746035 ps
CPU time 3.03 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 209808 kb
Host smart-5d60ef91-314b-492d-9a2a-e9d62f9a0c8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868895460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1868895460
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3758334370
Short name T601
Test name
Test status
Simulation time 6980021922 ps
CPU time 29.15 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:14:18 PM PDT 24
Peak memory 218652 kb
Host smart-14c3c8b7-17e2-4d85-b589-c7f33899c30f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758334370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3758334370
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.573058342
Short name T364
Test name
Test status
Simulation time 1510663404 ps
CPU time 4.75 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 217264 kb
Host smart-bb8eb9ef-75fe-43f8-a6ce-efac31772573
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573058342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.573058342
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2171794094
Short name T19
Test name
Test status
Simulation time 4982400368 ps
CPU time 18.33 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:14:07 PM PDT 24
Peak memory 218212 kb
Host smart-c534edac-de69-4ffd-8277-bd1a9a81197f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171794094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2171794094
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3746825595
Short name T463
Test name
Test status
Simulation time 712763512 ps
CPU time 20 seconds
Started May 09 01:13:49 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 213368 kb
Host smart-6e42901e-ed47-442d-a3ac-30ac6b5dd5f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746825595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3746825595
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1621220858
Short name T311
Test name
Test status
Simulation time 1103737759 ps
CPU time 4.72 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 213836 kb
Host smart-ad8a4159-f463-4fb7-81ca-143c8da30509
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621220858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1621220858
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.212570112
Short name T481
Test name
Test status
Simulation time 3652740169 ps
CPU time 76.77 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:15:02 PM PDT 24
Peak memory 273664 kb
Host smart-274969ea-6eeb-44ba-8a97-424e6cb33048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212570112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.212570112
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.73721239
Short name T432
Test name
Test status
Simulation time 1548966126 ps
CPU time 18.2 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:14:06 PM PDT 24
Peak memory 251144 kb
Host smart-9ca78124-3867-4a90-988e-766c3e380e0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73721239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt
ag_state_post_trans.73721239
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3800163820
Short name T844
Test name
Test status
Simulation time 30554115 ps
CPU time 2.26 seconds
Started May 09 01:13:47 PM PDT 24
Finished May 09 01:13:51 PM PDT 24
Peak memory 218204 kb
Host smart-6f2b2297-e3d0-4636-b86b-e788fa408ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800163820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3800163820
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2021760010
Short name T160
Test name
Test status
Simulation time 1281838420 ps
CPU time 7.44 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:54 PM PDT 24
Peak memory 214604 kb
Host smart-df97ccda-dd69-41e4-99cd-82e808de4934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021760010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2021760010
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1545905292
Short name T330
Test name
Test status
Simulation time 3166574935 ps
CPU time 29.38 seconds
Started May 09 01:13:49 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 226388 kb
Host smart-f893770b-08b2-4eb5-aae1-b9aa59b44091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545905292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1545905292
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3983324071
Short name T302
Test name
Test status
Simulation time 2757604415 ps
CPU time 9.76 seconds
Started May 09 01:13:47 PM PDT 24
Finished May 09 01:13:59 PM PDT 24
Peak memory 218272 kb
Host smart-347ba6a3-2f88-4247-82a5-01e589c52571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983324071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3983324071
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3934408220
Short name T853
Test name
Test status
Simulation time 547735069 ps
CPU time 16.67 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:14:04 PM PDT 24
Peak memory 218212 kb
Host smart-1aa995d1-0abb-40a8-8436-ea6c847ac3f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934408220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
934408220
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.592914460
Short name T390
Test name
Test status
Simulation time 2160615302 ps
CPU time 9.98 seconds
Started May 09 01:13:43 PM PDT 24
Finished May 09 01:13:54 PM PDT 24
Peak memory 218364 kb
Host smart-c9871a45-d07c-4945-97d5-b456172db665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592914460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.592914460
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2009710851
Short name T73
Test name
Test status
Simulation time 14492201 ps
CPU time 0.87 seconds
Started May 09 01:13:46 PM PDT 24
Finished May 09 01:13:49 PM PDT 24
Peak memory 209792 kb
Host smart-5bb438fa-7b4b-4ffd-8782-65b553f0386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009710851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2009710851
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3308158324
Short name T444
Test name
Test status
Simulation time 232464396 ps
CPU time 31.08 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:14:19 PM PDT 24
Peak memory 251196 kb
Host smart-1985c12e-6902-4c60-a3dd-98868dd19cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308158324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3308158324
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2162317583
Short name T542
Test name
Test status
Simulation time 307486557 ps
CPU time 7.38 seconds
Started May 09 01:13:45 PM PDT 24
Finished May 09 01:13:55 PM PDT 24
Peak memory 248756 kb
Host smart-36dd9765-8d9d-477a-89e8-3746d2902055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162317583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2162317583
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2382135549
Short name T671
Test name
Test status
Simulation time 19974654636 ps
CPU time 85.87 seconds
Started May 09 01:13:58 PM PDT 24
Finished May 09 01:15:25 PM PDT 24
Peak memory 219788 kb
Host smart-ac0e08c7-2984-4078-8f15-7eb680820fd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382135549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2382135549
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.124232360
Short name T337
Test name
Test status
Simulation time 12102000 ps
CPU time 0.97 seconds
Started May 09 01:13:44 PM PDT 24
Finished May 09 01:13:47 PM PDT 24
Peak memory 209092 kb
Host smart-954f36d8-b6be-4fe6-8a31-cc01a338bb7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124232360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.124232360
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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