Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54502 |
1 |
|
|
T1 |
92 |
|
T3 |
61 |
|
T4 |
90 |
auto[1] |
1866 |
1 |
|
|
T3 |
9 |
|
T6 |
11 |
|
T7 |
10 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55586 |
1 |
|
|
T1 |
72 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
782 |
1 |
|
|
T1 |
20 |
|
T45 |
12 |
|
T46 |
8 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54317 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2051 |
1 |
|
|
T5 |
3 |
|
T14 |
1 |
|
T16 |
10 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54394 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
1974 |
1 |
|
|
T14 |
1 |
|
T16 |
8 |
|
T19 |
17 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54307 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2061 |
1 |
|
|
T5 |
1 |
|
T14 |
2 |
|
T15 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51116 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
no_err_inj |
5252 |
1 |
|
|
T5 |
4 |
|
T14 |
6 |
|
T15 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54422 |
1 |
|
|
T1 |
92 |
|
T3 |
64 |
|
T4 |
90 |
auto[1] |
1946 |
1 |
|
|
T3 |
6 |
|
T6 |
4 |
|
T7 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55624 |
1 |
|
|
T1 |
77 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
744 |
1 |
|
|
T1 |
15 |
|
T45 |
12 |
|
T46 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38306 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
18062 |
1 |
|
|
T5 |
13 |
|
T6 |
51 |
|
T7 |
68 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54332 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2036 |
1 |
|
|
T14 |
1 |
|
T16 |
9 |
|
T19 |
17 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54330 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2038 |
1 |
|
|
T5 |
1 |
|
T16 |
13 |
|
T31 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54321 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2047 |
1 |
|
|
T5 |
2 |
|
T15 |
2 |
|
T16 |
17 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54421 |
1 |
|
|
T1 |
92 |
|
T3 |
65 |
|
T4 |
90 |
auto[1] |
1947 |
1 |
|
|
T3 |
5 |
|
T6 |
9 |
|
T7 |
7 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54239 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2129 |
1 |
|
|
T60 |
12 |
|
T30 |
7 |
|
T19 |
20 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55607 |
1 |
|
|
T1 |
78 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
761 |
1 |
|
|
T1 |
14 |
|
T45 |
8 |
|
T46 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55623 |
1 |
|
|
T1 |
75 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
745 |
1 |
|
|
T1 |
17 |
|
T45 |
16 |
|
T46 |
9 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55617 |
1 |
|
|
T1 |
66 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
751 |
1 |
|
|
T1 |
26 |
|
T45 |
16 |
|
T46 |
10 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53538 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2830 |
1 |
|
|
T5 |
13 |
|
T14 |
12 |
|
T15 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52629 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
3739 |
1 |
|
|
T39 |
72 |
|
T50 |
96 |
|
T51 |
94 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54315 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2053 |
1 |
|
|
T5 |
1 |
|
T16 |
9 |
|
T18 |
2 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54310 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2058 |
1 |
|
|
T5 |
1 |
|
T16 |
9 |
|
T18 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54320 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
2048 |
1 |
|
|
T14 |
1 |
|
T15 |
2 |
|
T16 |
13 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54388 |
1 |
|
|
T1 |
92 |
|
T3 |
58 |
|
T4 |
90 |
auto[1] |
1980 |
1 |
|
|
T3 |
12 |
|
T6 |
6 |
|
T7 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50549 |
1 |
|
|
T1 |
92 |
|
T3 |
59 |
|
T5 |
13 |
auto[1] |
5819 |
1 |
|
|
T3 |
11 |
|
T4 |
90 |
|
T6 |
9 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52613 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[1] |
3755 |
1 |
|
|
T13 |
70 |
|
T37 |
64 |
|
T29 |
92 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56368 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54405 |
1 |
|
|
T1 |
92 |
|
T3 |
59 |
|
T4 |
90 |
auto[1] |
1963 |
1 |
|
|
T3 |
11 |
|
T6 |
2 |
|
T7 |
13 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54432 |
1 |
|
|
T1 |
92 |
|
T3 |
60 |
|
T4 |
90 |
auto[1] |
1936 |
1 |
|
|
T3 |
10 |
|
T6 |
6 |
|
T7 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54481 |
1 |
|
|
T1 |
92 |
|
T3 |
64 |
|
T4 |
90 |
auto[1] |
1887 |
1 |
|
|
T3 |
6 |
|
T6 |
4 |
|
T7 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49669 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
no_err_inj |
3869 |
1 |
|
|
T59 |
13 |
|
T17 |
15 |
|
T19 |
42 |
auto[1] |
err_inj |
1447 |
1 |
|
|
T5 |
9 |
|
T14 |
6 |
|
T15 |
5 |
auto[1] |
no_err_inj |
1383 |
1 |
|
|
T5 |
4 |
|
T14 |
6 |
|
T15 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51651 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1887 |
1 |
|
|
T16 |
9 |
|
T19 |
20 |
|
T38 |
10 |
auto[1] |
auto[0] |
2659 |
1 |
|
|
T5 |
12 |
|
T14 |
12 |
|
T15 |
10 |
auto[1] |
auto[1] |
171 |
1 |
|
|
T5 |
1 |
|
T18 |
1 |
|
T19 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51660 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1878 |
1 |
|
|
T16 |
13 |
|
T19 |
12 |
|
T38 |
12 |
auto[1] |
auto[0] |
2670 |
1 |
|
|
T5 |
12 |
|
T14 |
12 |
|
T15 |
10 |
auto[1] |
auto[1] |
160 |
1 |
|
|
T5 |
1 |
|
T31 |
1 |
|
T19 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51652 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1886 |
1 |
|
|
T16 |
13 |
|
T19 |
15 |
|
T38 |
10 |
auto[1] |
auto[0] |
2668 |
1 |
|
|
T5 |
13 |
|
T14 |
11 |
|
T15 |
8 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T14 |
1 |
|
T15 |
2 |
|
T18 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51710 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1828 |
1 |
|
|
T16 |
8 |
|
T19 |
17 |
|
T38 |
12 |
auto[1] |
auto[0] |
2684 |
1 |
|
|
T5 |
13 |
|
T14 |
11 |
|
T15 |
10 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T14 |
1 |
|
T115 |
2 |
|
T222 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51644 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1894 |
1 |
|
|
T16 |
11 |
|
T19 |
16 |
|
T38 |
21 |
auto[1] |
auto[0] |
2663 |
1 |
|
|
T5 |
12 |
|
T14 |
10 |
|
T15 |
9 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T5 |
1 |
|
T14 |
2 |
|
T15 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51633 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1905 |
1 |
|
|
T16 |
10 |
|
T19 |
23 |
|
T38 |
15 |
auto[1] |
auto[0] |
2684 |
1 |
|
|
T5 |
10 |
|
T14 |
11 |
|
T15 |
10 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T5 |
3 |
|
T14 |
1 |
|
T19 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37268 |
1 |
|
|
T1 |
92 |
|
T3 |
61 |
|
T4 |
90 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T3 |
9 |
|
T223 |
11 |
|
T47 |
10 |
auto[1] |
auto[0] |
17234 |
1 |
|
|
T5 |
13 |
|
T6 |
40 |
|
T7 |
58 |
auto[1] |
auto[1] |
828 |
1 |
|
|
T6 |
11 |
|
T7 |
10 |
|
T38 |
5 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37207 |
1 |
|
|
T1 |
92 |
|
T3 |
64 |
|
T4 |
90 |
auto[0] |
auto[1] |
1099 |
1 |
|
|
T3 |
6 |
|
T223 |
9 |
|
T47 |
13 |
auto[1] |
auto[0] |
17215 |
1 |
|
|
T5 |
13 |
|
T6 |
47 |
|
T7 |
62 |
auto[1] |
auto[1] |
847 |
1 |
|
|
T6 |
4 |
|
T7 |
6 |
|
T38 |
10 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37146 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1160 |
1 |
|
|
T60 |
12 |
|
T30 |
7 |
|
T19 |
20 |
auto[1] |
auto[0] |
17093 |
1 |
|
|
T5 |
13 |
|
T6 |
51 |
|
T7 |
68 |
auto[1] |
auto[1] |
969 |
1 |
|
|
T88 |
4 |
|
T224 |
17 |
|
T94 |
14 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37218 |
1 |
|
|
T1 |
92 |
|
T3 |
65 |
|
T4 |
90 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T3 |
5 |
|
T223 |
1 |
|
T47 |
9 |
auto[1] |
auto[0] |
17203 |
1 |
|
|
T5 |
13 |
|
T6 |
42 |
|
T7 |
61 |
auto[1] |
auto[1] |
859 |
1 |
|
|
T6 |
9 |
|
T7 |
7 |
|
T38 |
7 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33356 |
1 |
|
|
T1 |
92 |
|
T3 |
59 |
|
T13 |
70 |
auto[0] |
auto[1] |
4950 |
1 |
|
|
T3 |
11 |
|
T4 |
90 |
|
T223 |
11 |
auto[1] |
auto[0] |
17193 |
1 |
|
|
T5 |
13 |
|
T6 |
42 |
|
T7 |
59 |
auto[1] |
auto[1] |
869 |
1 |
|
|
T6 |
9 |
|
T7 |
9 |
|
T38 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37131 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1175 |
1 |
|
|
T16 |
9 |
|
T19 |
21 |
|
T38 |
6 |
auto[1] |
auto[0] |
17179 |
1 |
|
|
T5 |
12 |
|
T6 |
51 |
|
T7 |
68 |
auto[1] |
auto[1] |
883 |
1 |
|
|
T5 |
1 |
|
T18 |
1 |
|
T38 |
4 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37170 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1136 |
1 |
|
|
T16 |
9 |
|
T19 |
11 |
|
T38 |
5 |
auto[1] |
auto[0] |
17145 |
1 |
|
|
T5 |
12 |
|
T6 |
51 |
|
T7 |
68 |
auto[1] |
auto[1] |
917 |
1 |
|
|
T5 |
1 |
|
T18 |
2 |
|
T38 |
7 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37173 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1133 |
1 |
|
|
T16 |
13 |
|
T31 |
1 |
|
T19 |
13 |
auto[1] |
auto[0] |
17157 |
1 |
|
|
T5 |
12 |
|
T6 |
51 |
|
T7 |
68 |
auto[1] |
auto[1] |
905 |
1 |
|
|
T5 |
1 |
|
T38 |
3 |
|
T87 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37123 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1183 |
1 |
|
|
T14 |
1 |
|
T16 |
9 |
|
T19 |
17 |
auto[1] |
auto[0] |
17209 |
1 |
|
|
T5 |
13 |
|
T6 |
51 |
|
T7 |
68 |
auto[1] |
auto[1] |
853 |
1 |
|
|
T38 |
5 |
|
T87 |
1 |
|
T82 |
32 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37187 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1119 |
1 |
|
|
T14 |
1 |
|
T16 |
8 |
|
T19 |
17 |
auto[1] |
auto[0] |
17207 |
1 |
|
|
T5 |
13 |
|
T6 |
51 |
|
T7 |
68 |
auto[1] |
auto[1] |
855 |
1 |
|
|
T38 |
4 |
|
T94 |
1 |
|
T82 |
39 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37142 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1164 |
1 |
|
|
T14 |
1 |
|
T16 |
10 |
|
T19 |
25 |
auto[1] |
auto[0] |
17175 |
1 |
|
|
T5 |
10 |
|
T6 |
51 |
|
T7 |
68 |
auto[1] |
auto[1] |
887 |
1 |
|
|
T5 |
3 |
|
T38 |
5 |
|
T87 |
2 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37244 |
1 |
|
|
T1 |
92 |
|
T3 |
64 |
|
T4 |
90 |
auto[0] |
auto[1] |
1062 |
1 |
|
|
T3 |
6 |
|
T223 |
7 |
|
T47 |
10 |
auto[1] |
auto[0] |
17237 |
1 |
|
|
T5 |
13 |
|
T6 |
47 |
|
T7 |
60 |
auto[1] |
auto[1] |
825 |
1 |
|
|
T6 |
4 |
|
T7 |
8 |
|
T38 |
1 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37238 |
1 |
|
|
T1 |
92 |
|
T3 |
60 |
|
T4 |
90 |
auto[0] |
auto[1] |
1068 |
1 |
|
|
T3 |
10 |
|
T223 |
14 |
|
T47 |
13 |
auto[1] |
auto[0] |
17194 |
1 |
|
|
T5 |
13 |
|
T6 |
45 |
|
T7 |
58 |
auto[1] |
auto[1] |
868 |
1 |
|
|
T6 |
6 |
|
T7 |
10 |
|
T38 |
7 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36637 |
1 |
|
|
T1 |
92 |
|
T3 |
70 |
|
T4 |
90 |
auto[0] |
auto[1] |
1669 |
1 |
|
|
T14 |
12 |
|
T31 |
10 |
|
T19 |
14 |
auto[1] |
auto[0] |
16901 |
1 |
|
|
T6 |
51 |
|
T7 |
68 |
|
T17 |
15 |
auto[1] |
auto[1] |
1161 |
1 |
|
|
T5 |
13 |
|
T15 |
10 |
|
T18 |
11 |