Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114586485

1

T1

56722

T2

1388

T3

28076

auto[1]

1433844

1

T1

2376

T3

495

T5

392

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114582135

1

T1

57811

T2

1388

T3

28175

auto[1]

1438194

1

T1

1287

T3

396

T5

294

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7804799	1			T1	8418		T2	91		T3	6862
auto[IdleSt]	23496909	1			T1	6502		T2	1297		T3	6025
auto[ClkMuxSt]	36894	1			T1	75		T3	70		T4	90
auto[CntIncrSt]	36638	1			T1	75		T3	70		T4	90
auto[CntProgSt]	2163172	1			T1	14633		T3	404		T4	39980
auto[TransCheckSt]	28820	1			T1	55		T3	51		T4	90
auto[TokenHashSt]	47808541	1			T1	1945		T3	2435		T4	6263
auto[FlashRmaSt]	30022	1			T1	94		T3	50		T5	4
auto[TokenCheck0St]	13415	1			T1	49		T3	11		T5	4
auto[TokenCheck1St]	9987	1			T1	35		T3	5		T5	4
auto[TransProgSt]	630195	1			T1	8468		T3	45		T5	8
auto[PostTransSt]	13950197	1			T1	10971		T3	11289		T4	13777
auto[ScrapSt]	155530	1			T19	19		T38	615		T39	3
auto[EscalateSt]	7203737	1			T1	5299		T3	1254		T5	15361
auto[InvalidSt]	12649385	1			T1	2479		T5	15045		T14	378

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2088	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12649385	1			T1	2479		T5	15045		T14	378
EscalateSt	7203737	1			T1	5299		T3	1254		T5	15361
ScrapSt	155530	1			T19	19		T38	615		T39	3
PostTransSt	13950197	1			T1	10971		T3	11289		T4	13777
TransProgSt	630195	1			T1	8468		T3	45		T5	8
TokenCheck1St	9987	1			T1	35		T3	5		T5	4
TokenCheck0St	13415	1			T1	49		T3	11		T5	4
FlashRmaSt	30022	1			T1	94		T3	50		T5	4
TokenHashSt	47808541	1			T1	1945		T3	2435		T4	6263
TransCheckSt	28820	1			T1	55		T3	51		T4	90
CntProgSt	2163172	1			T1	14633		T3	404		T4	39980
CntIncrSt	36638	1			T1	75		T3	70		T4	90
ClkMuxSt	36894	1			T1	75		T3	70		T4	90
IdleSt	23496909	1			T1	6502		T2	1297		T3	6025
ResetSt	7804799	1			T1	8418		T2	91		T3	6862
arcs[ResetSt=>IdleSt]	56375	1			T1	93		T2	1		T3	71
arcs[IdleSt=>ScrapSt]	279	1			T19	2		T38	1		T39	1
arcs[IdleSt=>ClkMuxSt]	36690	1			T1	75		T3	70		T4	90
arcs[ClkMuxSt=>CntIncrSt]	36638	1			T1	75		T3	70		T4	90
arcs[CntIncrSt=>PostTransSt]	1939	1			T3	10		T6	6		T7	10
arcs[CntIncrSt=>CntProgSt]	34637	1			T1	75		T3	60		T4	90
arcs[CntProgSt=>PostTransSt]	4748	1			T1	20		T3	9		T6	11
arcs[CntProgSt=>TransCheckSt]	28820	1			T1	55		T3	51		T4	90
arcs[TransCheckSt=>PostTransSt]	3760	1			T3	6		T6	4		T13	30
arcs[TransCheckSt=>TokenHashSt]	24935	1			T1	55		T3	45		T4	90
arcs[TokenHashSt=>PostTransSt]	10726	1			T1	6		T3	34		T4	90
arcs[TokenHashSt=>FlashRmaSt]	13526	1			T1	49		T3	11		T5	4
arcs[FlashRmaSt=>TokenCheck0St]	13415	1			T1	49		T3	11		T5	4
arcs[TokenCheck0St=>PostTransSt]	3406	1			T1	14		T3	6		T6	4
arcs[TokenCheck0St=>TokenCheck1St]	9987	1			T1	35		T3	5		T5	4
arcs[TokenCheck1St=>PostTransSt]	612	1			T13	6		T37	4		T29	9
arcs[TransProgSt=>PostTransSt]	8461	1			T1	35		T3	5		T5	4
arcs[IdleSt=>EscalateSt]	176	1			T50	9		T51	5		T52	8
arcs[ClkMuxSt=>EscalateSt]	52	1			T39	1		T50	2		T51	3
arcs[CntIncrSt=>EscalateSt]	62	1			T39	1		T50	4		T51	2
arcs[CntProgSt=>EscalateSt]	1069	1			T39	33		T50	22		T51	14
arcs[TransCheckSt=>EscalateSt]	125	1			T51	8		T52	5		T56	2
arcs[TokenHashSt=>EscalateSt]	683	1			T39	8		T50	14		T51	16
arcs[FlashRmaSt=>EscalateSt]	111	1			T39	2		T50	3		T51	1
arcs[TokenCheck0St=>EscalateSt]	22	1			T39	2		T50	1		T55	1
arcs[TokenCheck1St=>EscalateSt]	152	1			T39	2		T50	6		T51	5
arcs[TransProgSt=>EscalateSt]	762	1			T39	15		T50	20		T51	23
arcs[PostTransSt=>EscalateSt]	5005	1			T1	20		T3	9		T6	11
arcs[InvalidSt=>EscalateSt]	15031	1			T1	17		T5	7		T14	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7804636	1			T1	8418		T2	91		T3	6862
auto[0]	auto[IdleSt]	23496789	1			T1	6502		T2	1297		T3	6025
auto[0]	auto[ClkMuxSt]	36863	1			T1	75		T3	70		T4	90
auto[0]	auto[CntIncrSt]	36595	1			T1	75		T3	70		T4	90
auto[0]	auto[CntProgSt]	2162449	1			T1	14633		T3	404		T4	39980
auto[0]	auto[TransCheckSt]	28734	1			T1	55		T3	51		T4	90
auto[0]	auto[TokenHashSt]	47808071	1			T1	1945		T3	2435		T4	6263
auto[0]	auto[FlashRmaSt]	29945	1			T1	94		T3	50		T5	4
auto[0]	auto[TokenCheck0St]	13398	1			T1	49		T3	11		T5	4
auto[0]	auto[TokenCheck1St]	9881	1			T1	35		T3	5		T5	4
auto[0]	auto[TransProgSt]	629654	1			T1	8468		T3	45		T5	8
auto[0]	auto[PostTransSt]	13947657	1			T1	10955		T3	11284		T4	13777
auto[0]	auto[ScrapSt]	155491	1			T19	19		T38	615		T39	2
auto[0]	auto[EscalateSt]	5782274	1			T1	2947		T3	764		T5	14973
auto[0]	auto[InvalidSt]	12641960	1			T1	2471		T5	15041		T14	375
auto[1]	auto[ResetSt]	163	1			T39	4		T50	3		T51	1
auto[1]	auto[IdleSt]	120	1			T50	6		T51	2		T52	6
auto[1]	auto[ClkMuxSt]	31	1			T50	1		T51	1		T220	1
auto[1]	auto[CntIncrSt]	43	1			T50	1		T51	2		T220	3
auto[1]	auto[CntProgSt]	723	1			T39	19		T50	15		T51	10
auto[1]	auto[TransCheckSt]	86	1			T51	6		T52	4		T56	2
auto[1]	auto[TokenHashSt]	470	1			T39	5		T50	9		T51	13
auto[1]	auto[FlashRmaSt]	77	1			T39	2		T50	2		T51	1
auto[1]	auto[TokenCheck0St]	17	1			T39	2		T50	1		T55	1
auto[1]	auto[TokenCheck1St]	106	1			T39	1		T50	5		T51	4
auto[1]	auto[TransProgSt]	541	1			T39	10		T50	17		T51	18
auto[1]	auto[PostTransSt]	2540	1			T1	16		T3	5		T6	8
auto[1]	auto[ScrapSt]	39	1			T39	1		T50	3		T51	2
auto[1]	auto[EscalateSt]	1421463	1			T1	2352		T3	490		T5	388
auto[1]	auto[InvalidSt]	7425	1			T1	8		T5	4		T14	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7804635	1			T1	8418		T2	91		T3	6862
auto[0]	auto[IdleSt]	23496807	1			T1	6502		T2	1297		T3	6025
auto[0]	auto[ClkMuxSt]	36859	1			T1	75		T3	70		T4	90
auto[0]	auto[CntIncrSt]	36599	1			T1	75		T3	70		T4	90
auto[0]	auto[CntProgSt]	2162446	1			T1	14633		T3	404		T4	39980
auto[0]	auto[TransCheckSt]	28732	1			T1	55		T3	51		T4	90
auto[0]	auto[TokenHashSt]	47808086	1			T1	1945		T3	2435		T4	6263
auto[0]	auto[FlashRmaSt]	29943	1			T1	94		T3	50		T5	4
auto[0]	auto[TokenCheck0St]	13402	1			T1	49		T3	11		T5	4
auto[0]	auto[TokenCheck1St]	9882	1			T1	35		T3	5		T5	4
auto[0]	auto[TransProgSt]	629692	1			T1	8468		T3	45		T5	8
auto[0]	auto[PostTransSt]	13947656	1			T1	10967		T3	11285		T4	13777
auto[0]	auto[ScrapSt]	155498	1			T19	19		T38	615		T39	3
auto[0]	auto[EscalateSt]	5778031	1			T1	4025		T3	862		T5	15070
auto[0]	auto[InvalidSt]	12641779	1			T1	2470		T5	15042		T14	376
auto[1]	auto[ResetSt]	164	1			T39	2		T50	5		T51	2
auto[1]	auto[IdleSt]	102	1			T50	5		T51	4		T52	4
auto[1]	auto[ClkMuxSt]	35	1			T39	1		T50	2		T51	3
auto[1]	auto[CntIncrSt]	39	1			T39	1		T50	3		T51	1
auto[1]	auto[CntProgSt]	726	1			T39	23		T50	15		T51	10
auto[1]	auto[TransCheckSt]	88	1			T51	7		T52	2		T55	3
auto[1]	auto[TokenHashSt]	455	1			T39	5		T50	13		T51	8
auto[1]	auto[FlashRmaSt]	79	1			T39	1		T50	2		T52	3
auto[1]	auto[TokenCheck0St]	13	1			T39	1		T55	1		T221	1
auto[1]	auto[TokenCheck1St]	105	1			T39	1		T50	2		T51	5
auto[1]	auto[TransProgSt]	503	1			T39	13		T50	12		T51	7
auto[1]	auto[PostTransSt]	2541	1			T1	4		T3	4		T6	3
auto[1]	auto[ScrapSt]	32	1			T50	2		T51	1		T52	2
auto[1]	auto[EscalateSt]	1425706	1			T1	1274		T3	392		T5	291
auto[1]	auto[InvalidSt]	7606	1			T1	9		T5	3		T14	2