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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.89 95.59 93.31 100.00 98.55 98.76 96.11


Total test records in report: 1007
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T822 /workspace/coverage/default/9.lc_ctrl_sec_mubi.3302476628 May 12 01:16:04 PM PDT 24 May 12 01:16:18 PM PDT 24 452510227 ps
T823 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3994105277 May 12 01:15:27 PM PDT 24 May 12 01:15:40 PM PDT 24 276913789 ps
T824 /workspace/coverage/default/24.lc_ctrl_state_failure.3833152723 May 12 01:17:01 PM PDT 24 May 12 01:17:24 PM PDT 24 569031317 ps
T825 /workspace/coverage/default/44.lc_ctrl_alert_test.2949602700 May 12 01:18:00 PM PDT 24 May 12 01:18:02 PM PDT 24 69912638 ps
T826 /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3512586286 May 12 01:17:18 PM PDT 24 May 12 01:20:16 PM PDT 24 35805412046 ps
T827 /workspace/coverage/default/26.lc_ctrl_state_failure.1248269043 May 12 01:17:15 PM PDT 24 May 12 01:17:40 PM PDT 24 774642920 ps
T828 /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3815055169 May 12 01:16:13 PM PDT 24 May 12 01:25:39 PM PDT 24 33800374526 ps
T829 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.113146531 May 12 01:16:22 PM PDT 24 May 12 01:16:24 PM PDT 24 36931818 ps
T830 /workspace/coverage/default/39.lc_ctrl_sec_mubi.2061568303 May 12 01:17:51 PM PDT 24 May 12 01:18:15 PM PDT 24 1602301471 ps
T831 /workspace/coverage/default/19.lc_ctrl_jtag_access.767901493 May 12 01:16:49 PM PDT 24 May 12 01:16:56 PM PDT 24 424954940 ps
T832 /workspace/coverage/default/32.lc_ctrl_state_post_trans.707730531 May 12 01:17:23 PM PDT 24 May 12 01:17:31 PM PDT 24 66180602 ps
T833 /workspace/coverage/default/6.lc_ctrl_security_escalation.3637986976 May 12 01:15:40 PM PDT 24 May 12 01:15:50 PM PDT 24 372937159 ps
T834 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2833313605 May 12 01:16:55 PM PDT 24 May 12 01:16:57 PM PDT 24 13782811 ps
T835 /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1925372143 May 12 01:15:34 PM PDT 24 May 12 01:15:37 PM PDT 24 174051591 ps
T836 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2813359391 May 12 01:15:56 PM PDT 24 May 12 01:16:02 PM PDT 24 1378258354 ps
T837 /workspace/coverage/default/15.lc_ctrl_stress_all.3582845655 May 12 01:16:27 PM PDT 24 May 12 01:18:11 PM PDT 24 3386638074 ps
T838 /workspace/coverage/default/41.lc_ctrl_prog_failure.4166536587 May 12 01:17:53 PM PDT 24 May 12 01:17:55 PM PDT 24 35029171 ps
T839 /workspace/coverage/default/30.lc_ctrl_errors.1060815547 May 12 01:17:24 PM PDT 24 May 12 01:17:37 PM PDT 24 385063442 ps
T840 /workspace/coverage/default/42.lc_ctrl_sec_mubi.2937484779 May 12 01:17:57 PM PDT 24 May 12 01:18:09 PM PDT 24 350652499 ps
T841 /workspace/coverage/default/1.lc_ctrl_jtag_priority.259202137 May 12 01:15:20 PM PDT 24 May 12 01:15:25 PM PDT 24 164832965 ps
T842 /workspace/coverage/default/40.lc_ctrl_sec_mubi.873442223 May 12 01:17:51 PM PDT 24 May 12 01:18:06 PM PDT 24 1406150624 ps
T843 /workspace/coverage/default/9.lc_ctrl_alert_test.3558094663 May 12 01:16:03 PM PDT 24 May 12 01:16:04 PM PDT 24 21454924 ps
T844 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2148808160 May 12 01:17:06 PM PDT 24 May 12 01:17:07 PM PDT 24 13792869 ps
T845 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1309619690 May 12 01:16:00 PM PDT 24 May 12 01:16:06 PM PDT 24 752422419 ps
T846 /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.498758201 May 12 01:18:04 PM PDT 24 May 12 01:24:47 PM PDT 24 89918294976 ps
T847 /workspace/coverage/default/18.lc_ctrl_sec_mubi.1800994382 May 12 01:16:39 PM PDT 24 May 12 01:16:56 PM PDT 24 2014462380 ps
T848 /workspace/coverage/default/12.lc_ctrl_jtag_errors.3787102244 May 12 01:16:15 PM PDT 24 May 12 01:17:21 PM PDT 24 21594708339 ps
T849 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.21083157 May 12 01:15:18 PM PDT 24 May 12 01:15:42 PM PDT 24 342494822 ps
T850 /workspace/coverage/default/20.lc_ctrl_security_escalation.201521944 May 12 01:16:49 PM PDT 24 May 12 01:16:59 PM PDT 24 1555920461 ps
T851 /workspace/coverage/default/19.lc_ctrl_smoke.1616982178 May 12 01:16:44 PM PDT 24 May 12 01:16:46 PM PDT 24 23704133 ps
T852 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2418583859 May 12 01:15:15 PM PDT 24 May 12 01:15:17 PM PDT 24 13464027 ps
T853 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3565606655 May 12 01:16:14 PM PDT 24 May 12 01:16:26 PM PDT 24 1209712182 ps
T854 /workspace/coverage/default/24.lc_ctrl_stress_all.805628700 May 12 01:17:01 PM PDT 24 May 12 01:18:23 PM PDT 24 10990496525 ps
T855 /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1370650043 May 12 01:15:24 PM PDT 24 May 12 01:30:03 PM PDT 24 43706977607 ps
T856 /workspace/coverage/default/22.lc_ctrl_sec_mubi.3236894355 May 12 01:16:56 PM PDT 24 May 12 01:17:06 PM PDT 24 239258057 ps
T857 /workspace/coverage/default/40.lc_ctrl_state_post_trans.773837723 May 12 01:17:53 PM PDT 24 May 12 01:18:01 PM PDT 24 233375701 ps
T858 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3461232783 May 12 01:17:50 PM PDT 24 May 12 01:17:52 PM PDT 24 27536524 ps
T859 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3343899152 May 12 01:15:12 PM PDT 24 May 12 01:15:21 PM PDT 24 267489931 ps
T860 /workspace/coverage/default/7.lc_ctrl_prog_failure.2392229650 May 12 01:15:42 PM PDT 24 May 12 01:15:47 PM PDT 24 143453990 ps
T95 /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.255797674 May 12 01:18:13 PM PDT 24 May 12 01:23:49 PM PDT 24 18188358644 ps
T96 /workspace/coverage/default/21.lc_ctrl_errors.3873378358 May 12 01:16:57 PM PDT 24 May 12 01:17:08 PM PDT 24 2617593654 ps
T97 /workspace/coverage/default/4.lc_ctrl_jtag_priority.3815110835 May 12 01:15:39 PM PDT 24 May 12 01:15:42 PM PDT 24 139096934 ps
T98 /workspace/coverage/default/18.lc_ctrl_security_escalation.416660652 May 12 01:16:39 PM PDT 24 May 12 01:16:50 PM PDT 24 1468682817 ps
T99 /workspace/coverage/default/46.lc_ctrl_stress_all.3613942658 May 12 01:18:08 PM PDT 24 May 12 01:19:57 PM PDT 24 2193018940 ps
T100 /workspace/coverage/default/29.lc_ctrl_jtag_access.1123111981 May 12 01:17:16 PM PDT 24 May 12 01:17:20 PM PDT 24 138456170 ps
T101 /workspace/coverage/default/10.lc_ctrl_alert_test.1346327046 May 12 01:16:17 PM PDT 24 May 12 01:16:19 PM PDT 24 18503581 ps
T102 /workspace/coverage/default/16.lc_ctrl_prog_failure.1676053001 May 12 01:16:29 PM PDT 24 May 12 01:16:33 PM PDT 24 54965250 ps
T103 /workspace/coverage/default/42.lc_ctrl_jtag_access.2461344847 May 12 01:17:59 PM PDT 24 May 12 01:18:01 PM PDT 24 219641806 ps
T104 /workspace/coverage/default/8.lc_ctrl_jtag_priority.437508457 May 12 01:15:56 PM PDT 24 May 12 01:15:59 PM PDT 24 2221360153 ps
T861 /workspace/coverage/default/39.lc_ctrl_state_failure.2954239693 May 12 01:17:46 PM PDT 24 May 12 01:18:06 PM PDT 24 615280019 ps
T862 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3337045422 May 12 01:18:12 PM PDT 24 May 12 01:18:26 PM PDT 24 338178870 ps
T863 /workspace/coverage/default/32.lc_ctrl_smoke.3251377786 May 12 01:17:29 PM PDT 24 May 12 01:17:33 PM PDT 24 432989685 ps
T864 /workspace/coverage/default/1.lc_ctrl_state_failure.3210955774 May 12 01:15:12 PM PDT 24 May 12 01:15:32 PM PDT 24 188678526 ps
T865 /workspace/coverage/default/33.lc_ctrl_errors.343633989 May 12 01:17:30 PM PDT 24 May 12 01:17:50 PM PDT 24 1146850903 ps
T866 /workspace/coverage/default/12.lc_ctrl_alert_test.1645862360 May 12 01:16:16 PM PDT 24 May 12 01:16:17 PM PDT 24 56747019 ps
T867 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2219407053 May 12 01:16:45 PM PDT 24 May 12 01:16:48 PM PDT 24 321987629 ps
T868 /workspace/coverage/default/30.lc_ctrl_state_post_trans.1327988789 May 12 01:17:23 PM PDT 24 May 12 01:17:30 PM PDT 24 169973552 ps
T869 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.469961781 May 12 01:15:12 PM PDT 24 May 12 01:15:19 PM PDT 24 410954416 ps
T870 /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3698267210 May 12 01:15:41 PM PDT 24 May 12 01:15:53 PM PDT 24 695145071 ps
T871 /workspace/coverage/default/21.lc_ctrl_stress_all.1518893810 May 12 01:16:56 PM PDT 24 May 12 01:19:12 PM PDT 24 17432310801 ps
T872 /workspace/coverage/default/5.lc_ctrl_prog_failure.442378991 May 12 01:15:32 PM PDT 24 May 12 01:15:35 PM PDT 24 71374043 ps
T873 /workspace/coverage/default/21.lc_ctrl_smoke.1963875494 May 12 01:16:56 PM PDT 24 May 12 01:17:00 PM PDT 24 45024888 ps
T874 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3436058188 May 12 01:16:47 PM PDT 24 May 12 01:17:01 PM PDT 24 6677948256 ps
T875 /workspace/coverage/default/47.lc_ctrl_jtag_access.225202032 May 12 01:18:13 PM PDT 24 May 12 01:18:22 PM PDT 24 619792043 ps
T876 /workspace/coverage/default/27.lc_ctrl_smoke.2827708924 May 12 01:17:12 PM PDT 24 May 12 01:17:14 PM PDT 24 82913224 ps
T877 /workspace/coverage/default/48.lc_ctrl_security_escalation.1397033787 May 12 01:18:11 PM PDT 24 May 12 01:18:20 PM PDT 24 549745652 ps
T878 /workspace/coverage/default/21.lc_ctrl_prog_failure.4203249986 May 12 01:17:00 PM PDT 24 May 12 01:17:04 PM PDT 24 304551161 ps
T879 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2727887951 May 12 01:17:13 PM PDT 24 May 12 01:17:15 PM PDT 24 18807888 ps
T880 /workspace/coverage/default/32.lc_ctrl_sec_mubi.4072282971 May 12 01:17:29 PM PDT 24 May 12 01:17:43 PM PDT 24 966562243 ps
T881 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1660455196 May 12 01:15:18 PM PDT 24 May 12 01:15:37 PM PDT 24 1309660520 ps
T882 /workspace/coverage/default/46.lc_ctrl_state_failure.939147095 May 12 01:18:07 PM PDT 24 May 12 01:18:31 PM PDT 24 411678264 ps
T883 /workspace/coverage/default/2.lc_ctrl_jtag_errors.2824413647 May 12 01:15:26 PM PDT 24 May 12 01:16:20 PM PDT 24 3786620955 ps
T119 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2848068105 May 12 01:14:19 PM PDT 24 May 12 01:14:22 PM PDT 24 90083346 ps
T127 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3403163155 May 12 01:14:20 PM PDT 24 May 12 01:14:22 PM PDT 24 24475292 ps
T120 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3301438261 May 12 01:13:18 PM PDT 24 May 12 01:13:19 PM PDT 24 93527374 ps
T121 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3537384557 May 12 01:14:07 PM PDT 24 May 12 01:14:12 PM PDT 24 1126278447 ps
T128 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1717966674 May 12 01:14:16 PM PDT 24 May 12 01:14:17 PM PDT 24 32209259 ps
T156 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.227691664 May 12 01:14:15 PM PDT 24 May 12 01:14:17 PM PDT 24 58174433 ps
T199 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1801319 May 12 01:14:15 PM PDT 24 May 12 01:14:17 PM PDT 24 13374510 ps
T160 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.278540710 May 12 01:13:32 PM PDT 24 May 12 01:13:34 PM PDT 24 249611129 ps
T123 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1250834848 May 12 01:13:57 PM PDT 24 May 12 01:14:01 PM PDT 24 1636790444 ps
T124 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.184740528 May 12 01:14:10 PM PDT 24 May 12 01:14:13 PM PDT 24 112169695 ps
T144 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3919426781 May 12 01:14:24 PM PDT 24 May 12 01:14:26 PM PDT 24 145034188 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1304973060 May 12 01:13:52 PM PDT 24 May 12 01:13:53 PM PDT 24 119507633 ps
T885 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.619303933 May 12 01:13:17 PM PDT 24 May 12 01:13:19 PM PDT 24 16579032 ps
T216 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1864235245 May 12 01:13:41 PM PDT 24 May 12 01:14:29 PM PDT 24 2278885325 ps
T157 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1972490579 May 12 01:13:13 PM PDT 24 May 12 01:13:20 PM PDT 24 256813409 ps
T171 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1122725434 May 12 01:13:22 PM PDT 24 May 12 01:13:24 PM PDT 24 25984032 ps
T886 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1067374740 May 12 01:13:58 PM PDT 24 May 12 01:14:06 PM PDT 24 1316271690 ps
T136 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2888923126 May 12 01:14:06 PM PDT 24 May 12 01:14:08 PM PDT 24 81115744 ps
T887 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2987344507 May 12 01:14:24 PM PDT 24 May 12 01:14:25 PM PDT 24 15721983 ps
T888 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1678680916 May 12 01:14:09 PM PDT 24 May 12 01:14:11 PM PDT 24 14665006 ps
T889 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1159385573 May 12 01:13:41 PM PDT 24 May 12 01:13:42 PM PDT 24 36936504 ps
T172 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3839310822 May 12 01:14:22 PM PDT 24 May 12 01:14:23 PM PDT 24 81951516 ps
T125 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3031709856 May 12 01:13:26 PM PDT 24 May 12 01:13:29 PM PDT 24 135181196 ps
T126 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2556551305 May 12 01:13:16 PM PDT 24 May 12 01:13:19 PM PDT 24 246613993 ps
T137 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1184920049 May 12 01:13:07 PM PDT 24 May 12 01:13:11 PM PDT 24 83260679 ps
T200 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2075333758 May 12 01:14:12 PM PDT 24 May 12 01:14:13 PM PDT 24 64885935 ps
T134 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1243500492 May 12 01:14:15 PM PDT 24 May 12 01:14:18 PM PDT 24 207032527 ps
T890 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3232981800 May 12 01:13:02 PM PDT 24 May 12 01:13:07 PM PDT 24 491571903 ps
T211 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3127437816 May 12 01:14:07 PM PDT 24 May 12 01:14:09 PM PDT 24 154053887 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.577965687 May 12 01:14:00 PM PDT 24 May 12 01:14:02 PM PDT 24 196854418 ps
T149 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2408974727 May 12 01:13:37 PM PDT 24 May 12 01:13:42 PM PDT 24 224893370 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3819240679 May 12 01:13:33 PM PDT 24 May 12 01:13:43 PM PDT 24 802290040 ps
T212 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3812333573 May 12 01:14:08 PM PDT 24 May 12 01:14:10 PM PDT 24 16990765 ps
T129 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2859553216 May 12 01:13:45 PM PDT 24 May 12 01:13:47 PM PDT 24 68106070 ps
T130 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1872206204 May 12 01:14:19 PM PDT 24 May 12 01:14:22 PM PDT 24 43462015 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1117218721 May 12 01:13:24 PM PDT 24 May 12 01:13:29 PM PDT 24 361287869 ps
T213 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3390377051 May 12 01:14:09 PM PDT 24 May 12 01:14:10 PM PDT 24 12739320 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2052241052 May 12 01:13:17 PM PDT 24 May 12 01:13:18 PM PDT 24 415545614 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3818110029 May 12 01:13:09 PM PDT 24 May 12 01:13:10 PM PDT 24 16269158 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1119583019 May 12 01:14:05 PM PDT 24 May 12 01:14:07 PM PDT 24 359730176 ps
T131 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2505455875 May 12 01:13:12 PM PDT 24 May 12 01:13:15 PM PDT 24 33540079 ps
T214 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3446188189 May 12 01:13:52 PM PDT 24 May 12 01:13:53 PM PDT 24 46343830 ps
T215 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2864128041 May 12 01:13:44 PM PDT 24 May 12 01:13:46 PM PDT 24 90027935 ps
T897 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2415370140 May 12 01:14:26 PM PDT 24 May 12 01:14:28 PM PDT 24 100591393 ps
T145 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.656500613 May 12 01:14:16 PM PDT 24 May 12 01:14:18 PM PDT 24 1171536235 ps
T898 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1506730280 May 12 01:13:54 PM PDT 24 May 12 01:14:00 PM PDT 24 185979544 ps
T132 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1998551945 May 12 01:14:14 PM PDT 24 May 12 01:14:17 PM PDT 24 57598606 ps
T141 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4230241658 May 12 01:13:16 PM PDT 24 May 12 01:13:18 PM PDT 24 78171379 ps
T147 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2546139799 May 12 01:13:43 PM PDT 24 May 12 01:13:46 PM PDT 24 63233447 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3423765077 May 12 01:14:08 PM PDT 24 May 12 01:14:10 PM PDT 24 29611289 ps
T900 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.876426169 May 12 01:13:57 PM PDT 24 May 12 01:13:59 PM PDT 24 234831086 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3393765977 May 12 01:13:12 PM PDT 24 May 12 01:13:13 PM PDT 24 409315451 ps
T151 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2906794309 May 12 01:14:19 PM PDT 24 May 12 01:14:21 PM PDT 24 176250896 ps
T902 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2423001989 May 12 01:13:41 PM PDT 24 May 12 01:13:43 PM PDT 24 160147339 ps
T142 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1264229632 May 12 01:13:57 PM PDT 24 May 12 01:14:01 PM PDT 24 149682888 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2784664041 May 12 01:13:49 PM PDT 24 May 12 01:13:52 PM PDT 24 657620131 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2405282977 May 12 01:14:02 PM PDT 24 May 12 01:14:03 PM PDT 24 23324723 ps
T904 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2305791592 May 12 01:13:27 PM PDT 24 May 12 01:13:29 PM PDT 24 23077468 ps
T905 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2429061857 May 12 01:14:19 PM PDT 24 May 12 01:14:21 PM PDT 24 33711892 ps
T135 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4247577987 May 12 01:14:21 PM PDT 24 May 12 01:14:25 PM PDT 24 495285838 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4207751107 May 12 01:13:53 PM PDT 24 May 12 01:14:08 PM PDT 24 3220059275 ps
T907 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.192909945 May 12 01:14:23 PM PDT 24 May 12 01:14:25 PM PDT 24 210544841 ps
T158 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.982832866 May 12 01:13:34 PM PDT 24 May 12 01:13:50 PM PDT 24 569659008 ps
T908 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2499251608 May 12 01:14:21 PM PDT 24 May 12 01:14:22 PM PDT 24 18038376 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3283673820 May 12 01:13:12 PM PDT 24 May 12 01:13:47 PM PDT 24 1474755551 ps
T155 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.289298264 May 12 01:13:47 PM PDT 24 May 12 01:13:50 PM PDT 24 114675653 ps
T910 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1838251248 May 12 01:14:14 PM PDT 24 May 12 01:14:17 PM PDT 24 94495295 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1006498202 May 12 01:13:25 PM PDT 24 May 12 01:13:27 PM PDT 24 95560091 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1236117835 May 12 01:13:09 PM PDT 24 May 12 01:13:11 PM PDT 24 272034614 ps
T913 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3132954210 May 12 01:14:16 PM PDT 24 May 12 01:14:18 PM PDT 24 419573605 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1953499975 May 12 01:13:49 PM PDT 24 May 12 01:13:50 PM PDT 24 19800270 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2340743619 May 12 01:13:17 PM PDT 24 May 12 01:13:18 PM PDT 24 74633376 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3204121048 May 12 01:13:55 PM PDT 24 May 12 01:13:57 PM PDT 24 86896057 ps
T133 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2517869827 May 12 01:14:15 PM PDT 24 May 12 01:14:21 PM PDT 24 107530714 ps
T159 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4047021320 May 12 01:13:20 PM PDT 24 May 12 01:13:23 PM PDT 24 1332886290 ps
T917 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4041728310 May 12 01:14:21 PM PDT 24 May 12 01:14:24 PM PDT 24 27341739 ps
T918 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1839866505 May 12 01:13:30 PM PDT 24 May 12 01:13:32 PM PDT 24 73579216 ps
T919 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.658812156 May 12 01:14:11 PM PDT 24 May 12 01:14:16 PM PDT 24 1297718539 ps
T920 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.634325486 May 12 01:13:46 PM PDT 24 May 12 01:13:50 PM PDT 24 367422030 ps
T921 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3314112414 May 12 01:13:44 PM PDT 24 May 12 01:13:47 PM PDT 24 254384993 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2925134480 May 12 01:14:04 PM PDT 24 May 12 01:14:07 PM PDT 24 539912293 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3497027465 May 12 01:13:11 PM PDT 24 May 12 01:13:36 PM PDT 24 2128755943 ps
T924 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.37875763 May 12 01:14:04 PM PDT 24 May 12 01:14:22 PM PDT 24 676093671 ps
T201 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1829433137 May 12 01:14:24 PM PDT 24 May 12 01:14:26 PM PDT 24 37916690 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3351935182 May 12 01:13:48 PM PDT 24 May 12 01:13:50 PM PDT 24 812021569 ps
T153 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2081032647 May 12 01:14:21 PM PDT 24 May 12 01:14:24 PM PDT 24 134425343 ps
T926 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3968821962 May 12 01:14:25 PM PDT 24 May 12 01:14:28 PM PDT 24 357629804 ps
T927 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1392858505 May 12 01:14:08 PM PDT 24 May 12 01:14:10 PM PDT 24 135187934 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.762981988 May 12 01:14:00 PM PDT 24 May 12 01:14:06 PM PDT 24 718960847 ps
T202 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2830653725 May 12 01:14:20 PM PDT 24 May 12 01:14:22 PM PDT 24 18189295 ps
T929 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1212663245 May 12 01:14:03 PM PDT 24 May 12 01:14:05 PM PDT 24 275996811 ps
T930 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1756591217 May 12 01:14:08 PM PDT 24 May 12 01:14:10 PM PDT 24 65373220 ps
T931 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3286449276 May 12 01:14:07 PM PDT 24 May 12 01:14:09 PM PDT 24 38962426 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3635691906 May 12 01:13:42 PM PDT 24 May 12 01:13:43 PM PDT 24 31615013 ps
T933 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.839583704 May 12 01:13:23 PM PDT 24 May 12 01:13:25 PM PDT 24 106284023 ps
T934 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.744769790 May 12 01:14:23 PM PDT 24 May 12 01:14:29 PM PDT 24 353725145 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2097347351 May 12 01:13:33 PM PDT 24 May 12 01:13:36 PM PDT 24 90844294 ps
T936 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.89487162 May 12 01:14:22 PM PDT 24 May 12 01:14:24 PM PDT 24 20611014 ps
T154 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1976725930 May 12 01:14:09 PM PDT 24 May 12 01:14:12 PM PDT 24 359638760 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3609888573 May 12 01:13:56 PM PDT 24 May 12 01:13:59 PM PDT 24 24524217 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1647196121 May 12 01:13:45 PM PDT 24 May 12 01:13:49 PM PDT 24 191997746 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3941162976 May 12 01:13:23 PM PDT 24 May 12 01:13:35 PM PDT 24 1200789456 ps
T203 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2632155180 May 12 01:13:59 PM PDT 24 May 12 01:14:01 PM PDT 24 46276173 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1412669284 May 12 01:14:08 PM PDT 24 May 12 01:14:12 PM PDT 24 692730178 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2956044288 May 12 01:13:08 PM PDT 24 May 12 01:13:09 PM PDT 24 31779775 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.741169335 May 12 01:13:24 PM PDT 24 May 12 01:13:26 PM PDT 24 211942593 ps
T943 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2855641742 May 12 01:14:20 PM PDT 24 May 12 01:14:22 PM PDT 24 81956899 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3314431039 May 12 01:13:20 PM PDT 24 May 12 01:13:22 PM PDT 24 19232722 ps
T945 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4062316625 May 12 01:13:42 PM PDT 24 May 12 01:13:44 PM PDT 24 26207457 ps
T204 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1103420931 May 12 01:14:16 PM PDT 24 May 12 01:14:18 PM PDT 24 17448362 ps
T205 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2142088305 May 12 01:14:22 PM PDT 24 May 12 01:14:23 PM PDT 24 46399370 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.745409072 May 12 01:13:29 PM PDT 24 May 12 01:13:31 PM PDT 24 43973089 ps
T947 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2002422430 May 12 01:14:21 PM PDT 24 May 12 01:14:24 PM PDT 24 75217025 ps
T948 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.939767822 May 12 01:13:50 PM PDT 24 May 12 01:13:52 PM PDT 24 22039013 ps
T949 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.246694352 May 12 01:13:50 PM PDT 24 May 12 01:13:59 PM PDT 24 548085973 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3855412497 May 12 01:13:07 PM PDT 24 May 12 01:13:09 PM PDT 24 25161082 ps
T951 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2679385412 May 12 01:13:26 PM PDT 24 May 12 01:13:28 PM PDT 24 351777894 ps
T952 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4131974925 May 12 01:13:33 PM PDT 24 May 12 01:13:34 PM PDT 24 31006324 ps
T206 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2572360811 May 12 01:13:45 PM PDT 24 May 12 01:13:46 PM PDT 24 18283938 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4257823732 May 12 01:14:04 PM PDT 24 May 12 01:14:10 PM PDT 24 124625313 ps
T139 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2193686259 May 12 01:14:15 PM PDT 24 May 12 01:14:20 PM PDT 24 220499413 ps
T954 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1869557185 May 12 01:13:52 PM PDT 24 May 12 01:13:55 PM PDT 24 79756679 ps
T955 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3038400434 May 12 01:13:48 PM PDT 24 May 12 01:13:50 PM PDT 24 23208023 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2261497585 May 12 01:13:12 PM PDT 24 May 12 01:13:14 PM PDT 24 196000986 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1412958464 May 12 01:13:12 PM PDT 24 May 12 01:13:14 PM PDT 24 101096722 ps
T958 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.172387587 May 12 01:13:34 PM PDT 24 May 12 01:13:36 PM PDT 24 113165632 ps
T959 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2297109587 May 12 01:14:15 PM PDT 24 May 12 01:14:17 PM PDT 24 53768847 ps
T960 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.165002314 May 12 01:13:24 PM PDT 24 May 12 01:13:25 PM PDT 24 140800586 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1966802611 May 12 01:13:36 PM PDT 24 May 12 01:13:37 PM PDT 24 18177373 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1814716928 May 12 01:13:21 PM PDT 24 May 12 01:13:23 PM PDT 24 33652685 ps
T963 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2745277808 May 12 01:13:49 PM PDT 24 May 12 01:13:50 PM PDT 24 43854200 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.334563966 May 12 01:13:09 PM PDT 24 May 12 01:13:11 PM PDT 24 85354690 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3512682031 May 12 01:13:36 PM PDT 24 May 12 01:13:39 PM PDT 24 56567629 ps
T140 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1287193908 May 12 01:14:24 PM PDT 24 May 12 01:14:27 PM PDT 24 186284099 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3262593056 May 12 01:13:41 PM PDT 24 May 12 01:13:42 PM PDT 24 19836461 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2784082770 May 12 01:13:32 PM PDT 24 May 12 01:13:35 PM PDT 24 2285410871 ps
T968 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.892010323 May 12 01:13:59 PM PDT 24 May 12 01:14:06 PM PDT 24 3096261088 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1618131390 May 12 01:13:46 PM PDT 24 May 12 01:13:48 PM PDT 24 94075626 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2615183559 May 12 01:13:49 PM PDT 24 May 12 01:13:55 PM PDT 24 877507949 ps
T207 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3300532035 May 12 01:13:35 PM PDT 24 May 12 01:13:36 PM PDT 24 33583645 ps
T971 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1806503863 May 12 01:13:12 PM PDT 24 May 12 01:13:14 PM PDT 24 49598299 ps
T972 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3289822953 May 12 01:14:19 PM PDT 24 May 12 01:14:22 PM PDT 24 88967205 ps
T973 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3989717719 May 12 01:13:08 PM PDT 24 May 12 01:13:25 PM PDT 24 7576258781 ps
T974 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1046661246 May 12 01:13:59 PM PDT 24 May 12 01:14:01 PM PDT 24 357308405 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2769243509 May 12 01:13:52 PM PDT 24 May 12 01:13:55 PM PDT 24 63380912 ps
T148 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4001254873 May 12 01:13:59 PM PDT 24 May 12 01:14:01 PM PDT 24 80041863 ps
T152 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1687985357 May 12 01:13:57 PM PDT 24 May 12 01:14:00 PM PDT 24 115314561 ps
T976 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2370980940 May 12 01:13:41 PM PDT 24 May 12 01:13:43 PM PDT 24 845796371 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3165477932 May 12 01:13:44 PM PDT 24 May 12 01:13:45 PM PDT 24 78774596 ps
T146 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3705090385 May 12 01:14:24 PM PDT 24 May 12 01:14:26 PM PDT 24 69902001 ps
T978 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2872386311 May 12 01:14:15 PM PDT 24 May 12 01:14:19 PM PDT 24 113256152 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3648480336 May 12 01:14:06 PM PDT 24 May 12 01:14:07 PM PDT 24 57514945 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.78901521 May 12 01:13:56 PM PDT 24 May 12 01:13:58 PM PDT 24 94974550 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1040574676 May 12 01:14:07 PM PDT 24 May 12 01:14:09 PM PDT 24 171790581 ps
T982 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2278034254 May 12 01:14:12 PM PDT 24 May 12 01:14:14 PM PDT 24 38698869 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.821501619 May 12 01:13:49 PM PDT 24 May 12 01:13:52 PM PDT 24 104049292 ps
T984 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3797301055 May 12 01:13:03 PM PDT 24 May 12 01:13:04 PM PDT 24 202511478 ps
T985 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1750764907 May 12 01:13:56 PM PDT 24 May 12 01:13:59 PM PDT 24 596488102 ps
T208 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.301412670 May 12 01:13:22 PM PDT 24 May 12 01:13:23 PM PDT 24 85812529 ps
T986 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.815508082 May 12 01:14:25 PM PDT 24 May 12 01:14:27 PM PDT 24 152570740 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3794139907 May 12 01:13:29 PM PDT 24 May 12 01:13:31 PM PDT 24 98374247 ps
T988 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1099440973 May 12 01:14:15 PM PDT 24 May 12 01:14:17 PM PDT 24 16665217 ps
T209 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.607103669 May 12 01:13:43 PM PDT 24 May 12 01:13:45 PM PDT 24 22470997 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3410458574 May 12 01:14:00 PM PDT 24 May 12 01:14:02 PM PDT 24 311275672 ps
T990 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1494480634 May 12 01:13:45 PM PDT 24 May 12 01:13:46 PM PDT 24 29238355 ps
T991 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2305272263 May 12 01:13:49 PM PDT 24 May 12 01:13:52 PM PDT 24 206801205 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1594159857 May 12 01:13:10 PM PDT 24 May 12 01:13:11 PM PDT 24 47983935 ps
T993 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.124306914 May 12 01:14:03 PM PDT 24 May 12 01:14:05 PM PDT 24 74195443 ps
T138 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3891410329 May 12 01:14:07 PM PDT 24 May 12 01:14:10 PM PDT 24 153130930 ps
T994 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3066755793 May 12 01:13:17 PM PDT 24 May 12 01:13:18 PM PDT 24 41035626 ps
T995 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3031448049 May 12 01:14:09 PM PDT 24 May 12 01:14:13 PM PDT 24 204419471 ps
T996 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.601383548 May 12 01:14:04 PM PDT 24 May 12 01:14:05 PM PDT 24 56178006 ps
T997 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3640992248 May 12 01:14:00 PM PDT 24 May 12 01:14:18 PM PDT 24 7696052774 ps
T998 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.524273114 May 12 01:14:13 PM PDT 24 May 12 01:14:15 PM PDT 24 29135591 ps
T210 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2787874995 May 12 01:13:29 PM PDT 24 May 12 01:13:30 PM PDT 24 55908519 ps
T999 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1992899098 May 12 01:13:52 PM PDT 24 May 12 01:13:54 PM PDT 24 180916063 ps
T1000 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.500592765 May 12 01:13:59 PM PDT 24 May 12 01:14:01 PM PDT 24 18110607 ps
T1001 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3344114055 May 12 01:13:52 PM PDT 24 May 12 01:13:55 PM PDT 24 291256254 ps
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