Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114286708

1

T1

7674

T2

57044

T3

157863

auto[1]

1478029

1

T1

198

T3

2058

T9

2277

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114257972

1

T1

7674

T2

57044

T3

157275

auto[1]

1506765

1

T1

198

T3

2646

T9

2772

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8126002	1			T1	1274		T2	7927		T3	31311
auto[IdleSt]	24175233	1			T1	1899		T2	7622		T3	4586
auto[ClkMuxSt]	37743	1			T1	8		T2	87		T11	60
auto[CntIncrSt]	37484	1			T1	8		T2	87		T11	60
auto[CntProgSt]	1517781	1			T1	320		T2	2924		T11	19745
auto[TransCheckSt]	28833	1			T1	8		T2	87		T11	48
auto[TokenHashSt]	44714703	1			T1	555		T2	23100		T11	462
auto[FlashRmaSt]	29245	1			T1	22		T11	111		T4	37
auto[TokenCheck0St]	13123	1			T1	8		T11	15		T4	37
auto[TokenCheck1St]	9749	1			T1	8		T11	9		T4	20
auto[TransProgSt]	361654	1			T1	183		T11	3619		T4	644
auto[PostTransSt]	14860015	1			T1	2003		T2	15210		T11	8638
auto[ScrapSt]	113925	1			T13	3		T17	611		T35	3
auto[EscalateSt]	7828495	1			T1	1026		T3	27312		T9	7205
auto[InvalidSt]	13908569	1			T1	549		T3	96705		T9	9761

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2183	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13908569	1			T1	549		T3	96705		T9	9761
EscalateSt	7828495	1			T1	1026		T3	27312		T9	7205
ScrapSt	113925	1			T13	3		T17	611		T35	3
PostTransSt	14860015	1			T1	2003		T2	15210		T11	8638
TransProgSt	361654	1			T1	183		T11	3619		T4	644
TokenCheck1St	9749	1			T1	8		T11	9		T4	20
TokenCheck0St	13123	1			T1	8		T11	15		T4	37
FlashRmaSt	29245	1			T1	22		T11	111		T4	37
TokenHashSt	44714703	1			T1	555		T2	23100		T11	462
TransCheckSt	28833	1			T1	8		T2	87		T11	48
CntProgSt	1517781	1			T1	320		T2	2924		T11	19745
CntIncrSt	37484	1			T1	8		T2	87		T11	60
ClkMuxSt	37743	1			T1	8		T2	87		T11	60
IdleSt	24175233	1			T1	1899		T2	7622		T3	4586
ResetSt	8126002	1			T1	1274		T2	7927		T3	31311
arcs[ResetSt=>IdleSt]	58097	1			T1	14		T2	88		T3	58
arcs[IdleSt=>ScrapSt]	285	1			T13	1		T17	2		T35	1
arcs[IdleSt=>ClkMuxSt]	37547	1			T1	8		T2	87		T11	60
arcs[ClkMuxSt=>CntIncrSt]	37484	1			T1	8		T2	87		T11	60
arcs[CntIncrSt=>PostTransSt]	2072	1			T11	7		T4	19		T18	9
arcs[CntIncrSt=>CntProgSt]	35346	1			T1	8		T2	87		T11	53
arcs[CntProgSt=>PostTransSt]	5314	1			T11	5		T4	14		T14	22
arcs[CntProgSt=>TransCheckSt]	28833	1			T1	8		T2	87		T11	48
arcs[TransCheckSt=>PostTransSt]	4034	1			T11	6		T4	22		T43	55
arcs[TransCheckSt=>TokenHashSt]	24673	1			T1	8		T2	87		T11	42
arcs[TokenHashSt=>PostTransSt]	10762	1			T2	87		T11	27		T4	47
arcs[TokenHashSt=>FlashRmaSt]	13223	1			T1	8		T11	15		T4	37
arcs[FlashRmaSt=>TokenCheck0St]	13123	1			T1	8		T11	15		T4	37
arcs[TokenCheck0St=>PostTransSt]	3348	1			T11	6		T4	17		T14	15
arcs[TokenCheck0St=>TokenCheck1St]	9749	1			T1	8		T11	9		T4	20
arcs[TokenCheck1St=>PostTransSt]	626	1			T4	3		T14	1		T43	10
arcs[TransProgSt=>PostTransSt]	8191	1			T1	8		T11	9		T4	17
arcs[IdleSt=>EscalateSt]	120	1			T21	7		T32	3		T52	2
arcs[ClkMuxSt=>EscalateSt]	63	1			T13	1		T21	1		T35	1
arcs[CntIncrSt=>EscalateSt]	66	1			T35	2		T49	3		T50	1
arcs[CntProgSt=>EscalateSt]	1199	1			T13	23		T21	19		T51	39
arcs[TransCheckSt=>EscalateSt]	126	1			T13	5		T50	11		T56	1
arcs[TokenHashSt=>EscalateSt]	687	1			T13	15		T21	8		T51	10
arcs[FlashRmaSt=>EscalateSt]	100	1			T13	3		T21	1		T32	2
arcs[TokenCheck0St=>EscalateSt]	26	1			T51	1		T32	1		T35	1
arcs[TokenCheck1St=>EscalateSt]	161	1			T13	5		T21	5		T51	3
arcs[TransProgSt=>EscalateSt]	771	1			T13	27		T21	9		T51	21
arcs[PostTransSt=>EscalateSt]	5543	1			T11	5		T4	14		T13	2
arcs[InvalidSt=>EscalateSt]	15643	1			T1	4		T3	48		T9	51

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8125861	1			T1	1274		T2	7927		T3	31311
auto[0]	auto[IdleSt]	24175156	1			T1	1899		T2	7622		T3	4586
auto[0]	auto[ClkMuxSt]	37705	1			T1	8		T2	87		T11	60
auto[0]	auto[CntIncrSt]	37440	1			T1	8		T2	87		T11	60
auto[0]	auto[CntProgSt]	1516997	1			T1	320		T2	2924		T11	19745
auto[0]	auto[TransCheckSt]	28744	1			T1	8		T2	87		T11	48
auto[0]	auto[TokenHashSt]	44714258	1			T1	555		T2	23100		T11	462
auto[0]	auto[FlashRmaSt]	29183	1			T1	22		T11	111		T4	37
auto[0]	auto[TokenCheck0St]	13107	1			T1	8		T11	15		T4	37
auto[0]	auto[TokenCheck1St]	9637	1			T1	8		T11	9		T4	20
auto[0]	auto[TransProgSt]	361163	1			T1	183		T11	3619		T4	644
auto[0]	auto[PostTransSt]	14857214	1			T1	2003		T2	15210		T11	8636
auto[0]	auto[ScrapSt]	113880	1			T13	2		T17	611		T35	3
auto[0]	auto[EscalateSt]	6363428	1			T1	830		T3	25275		T9	4951
auto[0]	auto[InvalidSt]	13900752	1			T1	547		T3	96684		T9	9738
auto[1]	auto[ResetSt]	141	1			T21	3		T51	4		T32	1
auto[1]	auto[IdleSt]	77	1			T21	3		T32	3		T223	6
auto[1]	auto[ClkMuxSt]	38	1			T21	1		T50	1		T105	3
auto[1]	auto[CntIncrSt]	44	1			T35	2		T49	2		T50	1
auto[1]	auto[CntProgSt]	784	1			T13	17		T21	14		T51	26
auto[1]	auto[TransCheckSt]	89	1			T13	5		T50	11		T224	1
auto[1]	auto[TokenHashSt]	445	1			T13	11		T21	4		T51	7
auto[1]	auto[FlashRmaSt]	62	1			T13	1		T32	1		T35	2
auto[1]	auto[TokenCheck0St]	16	1			T50	1		T224	1		T225	1
auto[1]	auto[TokenCheck1St]	112	1			T13	5		T21	4		T51	1
auto[1]	auto[TransProgSt]	491	1			T13	17		T21	7		T51	14
auto[1]	auto[PostTransSt]	2801	1			T11	2		T4	7		T13	1
auto[1]	auto[ScrapSt]	45	1			T13	1		T49	1		T50	1
auto[1]	auto[EscalateSt]	1465067	1			T1	196		T3	2037		T9	2254
auto[1]	auto[InvalidSt]	7817	1			T1	2		T3	21		T9	23

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8125839	1			T1	1274		T2	7927		T3	31311
auto[0]	auto[IdleSt]	24175138	1			T1	1899		T2	7622		T3	4586
auto[0]	auto[ClkMuxSt]	37698	1			T1	8		T2	87		T11	60
auto[0]	auto[CntIncrSt]	37445	1			T1	8		T2	87		T11	60
auto[0]	auto[CntProgSt]	1516966	1			T1	320		T2	2924		T11	19745
auto[0]	auto[TransCheckSt]	28746	1			T1	8		T2	87		T11	48
auto[0]	auto[TokenHashSt]	44714247	1			T1	555		T2	23100		T11	462
auto[0]	auto[FlashRmaSt]	29179	1			T1	22		T11	111		T4	37
auto[0]	auto[TokenCheck0St]	13104	1			T1	8		T11	15		T4	37
auto[0]	auto[TokenCheck1St]	9650	1			T1	8		T11	9		T4	20
auto[0]	auto[TransProgSt]	361105	1			T1	183		T11	3619		T4	644
auto[0]	auto[PostTransSt]	14857196	1			T1	2003		T2	15210		T11	8635
auto[0]	auto[ScrapSt]	113880	1			T13	2		T17	611		T35	2
auto[0]	auto[EscalateSt]	6334853	1			T1	830		T3	24693		T9	4461
auto[0]	auto[InvalidSt]	13900743	1			T1	547		T3	96678		T9	9733
auto[1]	auto[ResetSt]	163	1			T13	2		T21	4		T51	3
auto[1]	auto[IdleSt]	95	1			T21	7		T32	1		T52	2
auto[1]	auto[ClkMuxSt]	45	1			T13	1		T21	1		T35	1
auto[1]	auto[CntIncrSt]	39	1			T35	1		T49	1		T50	1
auto[1]	auto[CntProgSt]	815	1			T13	14		T21	14		T51	29
auto[1]	auto[TransCheckSt]	87	1			T13	5		T50	6		T56	1
auto[1]	auto[TokenHashSt]	456	1			T13	9		T21	6		T51	4
auto[1]	auto[FlashRmaSt]	66	1			T13	3		T21	1		T32	1
auto[1]	auto[TokenCheck0St]	19	1			T51	1		T32	1		T35	1
auto[1]	auto[TokenCheck1St]	99	1			T13	3		T21	3		T51	3
auto[1]	auto[TransProgSt]	549	1			T13	19		T21	5		T51	14
auto[1]	auto[PostTransSt]	2819	1			T11	3		T4	7		T13	2
auto[1]	auto[ScrapSt]	45	1			T13	1		T35	1		T56	1
auto[1]	auto[EscalateSt]	1493642	1			T1	196		T3	2619		T9	2744
auto[1]	auto[InvalidSt]	7826	1			T1	2		T3	27		T9	28