Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 97.89 96.13 93.31 100.00 98.55 99.00 96.11


Total test records in report: 1000
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T813 /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1085051774 May 14 12:53:06 PM PDT 24 May 14 12:53:35 PM PDT 24 870706891 ps
T814 /workspace/coverage/default/4.lc_ctrl_jtag_priority.3711068498 May 14 12:52:36 PM PDT 24 May 14 12:52:45 PM PDT 24 1036888694 ps
T815 /workspace/coverage/default/17.lc_ctrl_sec_mubi.3059733380 May 14 12:53:09 PM PDT 24 May 14 12:53:31 PM PDT 24 6748304993 ps
T816 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.503292843 May 14 12:53:09 PM PDT 24 May 14 12:53:23 PM PDT 24 526881624 ps
T817 /workspace/coverage/default/44.lc_ctrl_security_escalation.1061337670 May 14 12:54:24 PM PDT 24 May 14 12:54:39 PM PDT 24 812291518 ps
T818 /workspace/coverage/default/35.lc_ctrl_state_failure.1516466821 May 14 12:54:03 PM PDT 24 May 14 12:54:40 PM PDT 24 343049804 ps
T819 /workspace/coverage/default/37.lc_ctrl_smoke.3395555820 May 14 12:53:55 PM PDT 24 May 14 12:54:02 PM PDT 24 327232209 ps
T820 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.443773105 May 14 12:52:19 PM PDT 24 May 14 12:52:31 PM PDT 24 612167540 ps
T821 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2622687943 May 14 12:52:54 PM PDT 24 May 14 12:53:35 PM PDT 24 1126683396 ps
T822 /workspace/coverage/default/30.lc_ctrl_state_post_trans.2031889264 May 14 12:53:50 PM PDT 24 May 14 12:54:00 PM PDT 24 47275461 ps
T823 /workspace/coverage/default/7.lc_ctrl_jtag_access.1642559961 May 14 12:52:53 PM PDT 24 May 14 12:53:00 PM PDT 24 68884130 ps
T824 /workspace/coverage/default/25.lc_ctrl_errors.2230610967 May 14 12:53:33 PM PDT 24 May 14 12:53:44 PM PDT 24 2500058282 ps
T825 /workspace/coverage/default/23.lc_ctrl_errors.1336535878 May 14 12:53:29 PM PDT 24 May 14 12:53:41 PM PDT 24 305909888 ps
T826 /workspace/coverage/default/0.lc_ctrl_stress_all.166427701 May 14 12:52:16 PM PDT 24 May 14 01:04:23 PM PDT 24 88671254784 ps
T827 /workspace/coverage/default/38.lc_ctrl_smoke.1384501163 May 14 12:53:56 PM PDT 24 May 14 12:54:01 PM PDT 24 58238191 ps
T828 /workspace/coverage/default/17.lc_ctrl_smoke.2853053005 May 14 12:53:08 PM PDT 24 May 14 12:53:13 PM PDT 24 26729446 ps
T829 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3725140234 May 14 12:52:38 PM PDT 24 May 14 12:53:02 PM PDT 24 560922268 ps
T830 /workspace/coverage/default/26.lc_ctrl_prog_failure.4166358120 May 14 12:53:39 PM PDT 24 May 14 12:53:43 PM PDT 24 67096402 ps
T831 /workspace/coverage/default/34.lc_ctrl_jtag_access.4121877983 May 14 12:54:03 PM PDT 24 May 14 12:54:13 PM PDT 24 995829736 ps
T832 /workspace/coverage/default/17.lc_ctrl_state_failure.607878366 May 14 12:53:08 PM PDT 24 May 14 12:53:39 PM PDT 24 384884255 ps
T833 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1994072150 May 14 12:52:53 PM PDT 24 May 14 12:53:14 PM PDT 24 3312127128 ps
T834 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2732787362 May 14 12:52:18 PM PDT 24 May 14 12:52:37 PM PDT 24 2804872557 ps
T835 /workspace/coverage/default/31.lc_ctrl_security_escalation.719822203 May 14 12:53:48 PM PDT 24 May 14 12:54:03 PM PDT 24 673675082 ps
T836 /workspace/coverage/default/16.lc_ctrl_security_escalation.2075197278 May 14 12:53:12 PM PDT 24 May 14 12:53:32 PM PDT 24 870833527 ps
T837 /workspace/coverage/default/37.lc_ctrl_jtag_access.333358996 May 14 12:53:57 PM PDT 24 May 14 12:54:08 PM PDT 24 1006410968 ps
T838 /workspace/coverage/default/19.lc_ctrl_stress_all.1822180822 May 14 12:53:19 PM PDT 24 May 14 12:54:58 PM PDT 24 13260694774 ps
T839 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.577175413 May 14 12:53:47 PM PDT 24 May 14 12:53:59 PM PDT 24 1147267191 ps
T840 /workspace/coverage/default/0.lc_ctrl_state_failure.128986190 May 14 12:52:09 PM PDT 24 May 14 12:52:33 PM PDT 24 200046182 ps
T841 /workspace/coverage/default/41.lc_ctrl_state_failure.1186046886 May 14 12:54:15 PM PDT 24 May 14 12:54:55 PM PDT 24 2340095330 ps
T842 /workspace/coverage/default/17.lc_ctrl_state_post_trans.3408148147 May 14 12:53:09 PM PDT 24 May 14 12:53:17 PM PDT 24 61734447 ps
T843 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3880362193 May 14 12:52:50 PM PDT 24 May 14 12:53:04 PM PDT 24 12637432335 ps
T844 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.884669602 May 14 12:52:49 PM PDT 24 May 14 12:53:00 PM PDT 24 309950852 ps
T845 /workspace/coverage/default/48.lc_ctrl_stress_all.2012999787 May 14 12:54:20 PM PDT 24 May 14 12:56:56 PM PDT 24 15130033794 ps
T846 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3583070586 May 14 12:52:54 PM PDT 24 May 14 12:53:00 PM PDT 24 47163508 ps
T847 /workspace/coverage/default/38.lc_ctrl_errors.2487247072 May 14 12:53:57 PM PDT 24 May 14 12:54:12 PM PDT 24 1629118115 ps
T848 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3947175232 May 14 12:54:00 PM PDT 24 May 14 12:54:19 PM PDT 24 776668569 ps
T849 /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4126853498 May 14 12:52:59 PM PDT 24 May 14 12:53:18 PM PDT 24 4528548163 ps
T850 /workspace/coverage/default/23.lc_ctrl_smoke.638067856 May 14 12:53:32 PM PDT 24 May 14 12:53:37 PM PDT 24 39266203 ps
T851 /workspace/coverage/default/39.lc_ctrl_prog_failure.3800906540 May 14 12:54:00 PM PDT 24 May 14 12:54:09 PM PDT 24 327577273 ps
T852 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2757167649 May 14 12:52:26 PM PDT 24 May 14 12:52:37 PM PDT 24 169309505 ps
T853 /workspace/coverage/default/44.lc_ctrl_prog_failure.3250037287 May 14 12:54:20 PM PDT 24 May 14 12:54:26 PM PDT 24 89380291 ps
T854 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.999229878 May 14 12:52:47 PM PDT 24 May 14 12:52:51 PM PDT 24 42007942 ps
T855 /workspace/coverage/default/30.lc_ctrl_alert_test.2509261068 May 14 12:53:49 PM PDT 24 May 14 12:53:53 PM PDT 24 21590957 ps
T856 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2380961853 May 14 12:52:46 PM PDT 24 May 14 12:53:02 PM PDT 24 7235518338 ps
T857 /workspace/coverage/default/35.lc_ctrl_sec_mubi.1831651913 May 14 12:53:53 PM PDT 24 May 14 12:54:09 PM PDT 24 1494181148 ps
T858 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.223348482 May 14 12:52:22 PM PDT 24 May 14 12:52:33 PM PDT 24 289468356 ps
T859 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3986948507 May 14 12:54:07 PM PDT 24 May 14 12:54:21 PM PDT 24 1551281678 ps
T860 /workspace/coverage/default/7.lc_ctrl_sec_mubi.2074548090 May 14 12:52:44 PM PDT 24 May 14 12:53:02 PM PDT 24 1604926735 ps
T861 /workspace/coverage/default/14.lc_ctrl_sec_mubi.2715804253 May 14 12:53:02 PM PDT 24 May 14 12:53:25 PM PDT 24 560757666 ps
T862 /workspace/coverage/default/21.lc_ctrl_stress_all.3419307316 May 14 12:53:32 PM PDT 24 May 14 12:57:00 PM PDT 24 18976162826 ps
T118 /workspace/coverage/default/34.lc_ctrl_stress_all.3516091672 May 14 12:54:02 PM PDT 24 May 14 12:57:39 PM PDT 24 49421193222 ps
T863 /workspace/coverage/default/13.lc_ctrl_prog_failure.1509459771 May 14 12:53:03 PM PDT 24 May 14 12:53:09 PM PDT 24 350842715 ps
T864 /workspace/coverage/default/47.lc_ctrl_state_post_trans.2335243087 May 14 12:54:19 PM PDT 24 May 14 12:54:28 PM PDT 24 1048238242 ps
T865 /workspace/coverage/default/3.lc_ctrl_jtag_access.322557666 May 14 12:52:29 PM PDT 24 May 14 12:52:34 PM PDT 24 647389326 ps
T866 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2798413401 May 14 12:52:37 PM PDT 24 May 14 12:53:18 PM PDT 24 2317585335 ps
T867 /workspace/coverage/default/24.lc_ctrl_jtag_access.648596252 May 14 12:53:38 PM PDT 24 May 14 12:53:45 PM PDT 24 178481325 ps
T868 /workspace/coverage/default/18.lc_ctrl_sec_mubi.3353606256 May 14 12:53:16 PM PDT 24 May 14 12:53:29 PM PDT 24 448216300 ps
T869 /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.307026057 May 14 12:53:17 PM PDT 24 May 14 12:53:24 PM PDT 24 138762821 ps
T870 /workspace/coverage/default/27.lc_ctrl_state_post_trans.2208279679 May 14 12:53:40 PM PDT 24 May 14 12:53:48 PM PDT 24 431257977 ps
T871 /workspace/coverage/default/16.lc_ctrl_prog_failure.3140746890 May 14 12:53:06 PM PDT 24 May 14 12:53:11 PM PDT 24 62967305 ps
T872 /workspace/coverage/default/22.lc_ctrl_smoke.1198198233 May 14 12:53:31 PM PDT 24 May 14 12:53:37 PM PDT 24 309253231 ps
T873 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.233833246 May 14 12:52:26 PM PDT 24 May 14 12:52:36 PM PDT 24 446901518 ps
T874 /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.512750582 May 14 12:52:47 PM PDT 24 May 14 12:57:29 PM PDT 24 30373832159 ps
T875 /workspace/coverage/default/37.lc_ctrl_alert_test.2301910954 May 14 12:54:03 PM PDT 24 May 14 12:54:08 PM PDT 24 134679350 ps
T876 /workspace/coverage/default/24.lc_ctrl_security_escalation.3631790430 May 14 12:53:32 PM PDT 24 May 14 12:53:45 PM PDT 24 1494946452 ps
T130 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1302842505 May 14 12:50:43 PM PDT 24 May 14 12:50:46 PM PDT 24 64425909 ps
T136 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1494003268 May 14 12:50:25 PM PDT 24 May 14 12:50:27 PM PDT 24 23905500 ps
T131 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1194280393 May 14 12:50:47 PM PDT 24 May 14 12:50:50 PM PDT 24 75661683 ps
T123 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3158310988 May 14 12:50:28 PM PDT 24 May 14 12:50:30 PM PDT 24 65653846 ps
T171 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1673197712 May 14 12:50:28 PM PDT 24 May 14 12:50:31 PM PDT 24 108178466 ps
T212 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.625110097 May 14 12:51:06 PM PDT 24 May 14 12:51:09 PM PDT 24 25136845 ps
T124 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.822054552 May 14 12:51:03 PM PDT 24 May 14 12:51:06 PM PDT 24 48825528 ps
T213 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2215523535 May 14 12:50:47 PM PDT 24 May 14 12:50:50 PM PDT 24 18556789 ps
T158 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3604413352 May 14 12:50:43 PM PDT 24 May 14 12:51:00 PM PDT 24 1613915657 ps
T153 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.928938742 May 14 12:50:56 PM PDT 24 May 14 12:50:59 PM PDT 24 160550287 ps
T172 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1629866594 May 14 12:50:53 PM PDT 24 May 14 12:50:56 PM PDT 24 71775483 ps
T119 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.136454830 May 14 12:51:08 PM PDT 24 May 14 12:51:11 PM PDT 24 22970039 ps
T183 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3877907460 May 14 12:50:41 PM PDT 24 May 14 12:50:44 PM PDT 24 42881488 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2162116754 May 14 12:50:35 PM PDT 24 May 14 12:50:38 PM PDT 24 47324204 ps
T125 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2822315235 May 14 12:50:43 PM PDT 24 May 14 12:50:47 PM PDT 24 176123825 ps
T157 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.739286486 May 14 12:50:48 PM PDT 24 May 14 12:50:53 PM PDT 24 288671322 ps
T120 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1905133115 May 14 12:50:30 PM PDT 24 May 14 12:50:34 PM PDT 24 32105233 ps
T121 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.668047575 May 14 12:50:51 PM PDT 24 May 14 12:50:56 PM PDT 24 122871078 ps
T878 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2230877825 May 14 12:50:45 PM PDT 24 May 14 12:50:55 PM PDT 24 851246364 ps
T218 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.649029036 May 14 12:50:39 PM PDT 24 May 14 12:50:41 PM PDT 24 290330904 ps
T154 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.261934188 May 14 12:50:29 PM PDT 24 May 14 12:50:32 PM PDT 24 301728668 ps
T126 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2877900654 May 14 12:50:43 PM PDT 24 May 14 12:50:47 PM PDT 24 225599175 ps
T155 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2464855844 May 14 12:50:45 PM PDT 24 May 14 12:50:48 PM PDT 24 101477031 ps
T879 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3350443176 May 14 12:50:51 PM PDT 24 May 14 12:50:54 PM PDT 24 226160908 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2151737563 May 14 12:50:38 PM PDT 24 May 14 12:50:40 PM PDT 24 354901622 ps
T127 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2307519486 May 14 12:50:41 PM PDT 24 May 14 12:50:46 PM PDT 24 432089533 ps
T881 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3273016989 May 14 12:50:56 PM PDT 24 May 14 12:50:59 PM PDT 24 22813915 ps
T137 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.764424611 May 14 12:50:51 PM PDT 24 May 14 12:50:54 PM PDT 24 104091108 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1185391177 May 14 12:50:33 PM PDT 24 May 14 12:50:38 PM PDT 24 133841943 ps
T132 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4022357474 May 14 12:50:38 PM PDT 24 May 14 12:50:42 PM PDT 24 50668680 ps
T214 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4230421930 May 14 12:50:52 PM PDT 24 May 14 12:50:55 PM PDT 24 42031412 ps
T883 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3597012820 May 14 12:50:34 PM PDT 24 May 14 12:50:46 PM PDT 24 851856337 ps
T884 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1562754282 May 14 12:50:47 PM PDT 24 May 14 12:51:15 PM PDT 24 4905157891 ps
T885 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3271830002 May 14 12:50:51 PM PDT 24 May 14 12:50:54 PM PDT 24 30611965 ps
T200 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3705892755 May 14 12:50:53 PM PDT 24 May 14 12:50:56 PM PDT 24 13751866 ps
T215 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2747058064 May 14 12:50:40 PM PDT 24 May 14 12:50:43 PM PDT 24 36881268 ps
T216 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.524657053 May 14 12:50:41 PM PDT 24 May 14 12:50:43 PM PDT 24 28194871 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2232472952 May 14 12:50:40 PM PDT 24 May 14 12:50:43 PM PDT 24 1609596774 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.190558934 May 14 12:50:29 PM PDT 24 May 14 12:50:33 PM PDT 24 4056919460 ps
T139 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1630307967 May 14 12:50:30 PM PDT 24 May 14 12:50:35 PM PDT 24 195069701 ps
T888 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3639599626 May 14 12:50:56 PM PDT 24 May 14 12:51:01 PM PDT 24 109910954 ps
T173 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1518044235 May 14 12:50:55 PM PDT 24 May 14 12:51:00 PM PDT 24 134838600 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1893543489 May 14 12:50:51 PM PDT 24 May 14 12:50:54 PM PDT 24 46257683 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1595435574 May 14 12:50:35 PM PDT 24 May 14 12:50:39 PM PDT 24 342866213 ps
T891 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2003028535 May 14 12:50:52 PM PDT 24 May 14 12:50:55 PM PDT 24 19511914 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2671082158 May 14 12:50:25 PM PDT 24 May 14 12:50:27 PM PDT 24 14108790 ps
T892 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.719356313 May 14 12:50:47 PM PDT 24 May 14 12:50:50 PM PDT 24 418511429 ps
T893 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1301606961 May 14 12:50:39 PM PDT 24 May 14 12:50:41 PM PDT 24 38377175 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3816553900 May 14 12:50:41 PM PDT 24 May 14 12:50:44 PM PDT 24 39771847 ps
T895 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3995568708 May 14 12:50:41 PM PDT 24 May 14 12:50:43 PM PDT 24 404147603 ps
T128 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.978690985 May 14 12:50:42 PM PDT 24 May 14 12:50:46 PM PDT 24 655966801 ps
T217 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.347701073 May 14 12:50:44 PM PDT 24 May 14 12:50:47 PM PDT 24 19573864 ps
T896 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1332811350 May 14 12:51:12 PM PDT 24 May 14 12:51:18 PM PDT 24 227918278 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2012987432 May 14 12:50:42 PM PDT 24 May 14 12:50:45 PM PDT 24 272101375 ps
T898 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4053419426 May 14 12:50:49 PM PDT 24 May 14 12:50:55 PM PDT 24 144915787 ps
T899 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1094658856 May 14 12:50:44 PM PDT 24 May 14 12:50:48 PM PDT 24 63030362 ps
T900 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3542521908 May 14 12:50:51 PM PDT 24 May 14 12:50:55 PM PDT 24 99893661 ps
T901 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2093793724 May 14 12:50:43 PM PDT 24 May 14 12:50:46 PM PDT 24 23827351 ps
T902 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2911446995 May 14 12:50:31 PM PDT 24 May 14 12:50:38 PM PDT 24 390228788 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3033201025 May 14 12:50:59 PM PDT 24 May 14 12:51:03 PM PDT 24 271617305 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.146738505 May 14 12:50:30 PM PDT 24 May 14 12:50:33 PM PDT 24 33775981 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2042093780 May 14 12:50:33 PM PDT 24 May 14 12:50:36 PM PDT 24 40808850 ps
T129 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4002458735 May 14 12:50:53 PM PDT 24 May 14 12:50:57 PM PDT 24 246355394 ps
T143 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3967525132 May 14 12:50:49 PM PDT 24 May 14 12:50:55 PM PDT 24 126849905 ps
T202 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3032215608 May 14 12:51:05 PM PDT 24 May 14 12:51:07 PM PDT 24 13522297 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1953898355 May 14 12:50:43 PM PDT 24 May 14 12:50:54 PM PDT 24 339088251 ps
T907 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.325725810 May 14 12:50:50 PM PDT 24 May 14 12:50:53 PM PDT 24 551938836 ps
T908 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4243603574 May 14 12:50:51 PM PDT 24 May 14 12:50:59 PM PDT 24 203307992 ps
T909 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3583685919 May 14 12:50:27 PM PDT 24 May 14 12:50:30 PM PDT 24 37287298 ps
T910 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2530677026 May 14 12:51:04 PM PDT 24 May 14 12:51:14 PM PDT 24 392828692 ps
T911 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.744070504 May 14 12:50:29 PM PDT 24 May 14 12:50:31 PM PDT 24 24198829 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4090105865 May 14 12:50:32 PM PDT 24 May 14 12:50:57 PM PDT 24 1084663591 ps
T913 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3994555799 May 14 12:50:59 PM PDT 24 May 14 12:51:03 PM PDT 24 31427767 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3695571698 May 14 12:50:39 PM PDT 24 May 14 12:50:43 PM PDT 24 276340985 ps
T915 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3051945118 May 14 12:50:25 PM PDT 24 May 14 12:50:37 PM PDT 24 990490037 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.235662282 May 14 12:50:45 PM PDT 24 May 14 12:50:49 PM PDT 24 74671929 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4257086865 May 14 12:50:28 PM PDT 24 May 14 12:50:30 PM PDT 24 75656210 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1201688736 May 14 12:50:29 PM PDT 24 May 14 12:50:54 PM PDT 24 3855190231 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2613916281 May 14 12:50:30 PM PDT 24 May 14 12:50:39 PM PDT 24 3084370730 ps
T920 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.547311914 May 14 12:50:52 PM PDT 24 May 14 12:50:55 PM PDT 24 15581072 ps
T921 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2160504592 May 14 12:50:35 PM PDT 24 May 14 12:50:47 PM PDT 24 2393626249 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3621115356 May 14 12:50:47 PM PDT 24 May 14 12:50:52 PM PDT 24 83206688 ps
T142 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1522956726 May 14 12:50:54 PM PDT 24 May 14 12:50:58 PM PDT 24 140765879 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3910056114 May 14 12:50:33 PM PDT 24 May 14 12:50:35 PM PDT 24 68852983 ps
T924 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.72576041 May 14 12:50:58 PM PDT 24 May 14 12:51:02 PM PDT 24 37782450 ps
T925 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4164389575 May 14 12:50:55 PM PDT 24 May 14 12:50:57 PM PDT 24 118002418 ps
T138 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2915813857 May 14 12:50:55 PM PDT 24 May 14 12:51:00 PM PDT 24 119039514 ps
T926 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.529935799 May 14 12:50:49 PM PDT 24 May 14 12:50:52 PM PDT 24 33249327 ps
T927 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3307090772 May 14 12:51:19 PM PDT 24 May 14 12:51:24 PM PDT 24 109718713 ps
T928 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2501493126 May 14 12:50:55 PM PDT 24 May 14 12:50:57 PM PDT 24 55233723 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2445986568 May 14 12:50:42 PM PDT 24 May 14 12:50:46 PM PDT 24 46138046 ps
T144 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3171536557 May 14 12:51:08 PM PDT 24 May 14 12:51:14 PM PDT 24 114831238 ps
T930 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.79271929 May 14 12:50:38 PM PDT 24 May 14 12:50:48 PM PDT 24 13360104342 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1039576666 May 14 12:50:33 PM PDT 24 May 14 12:50:35 PM PDT 24 14013807 ps
T932 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.395871561 May 14 12:51:01 PM PDT 24 May 14 12:51:04 PM PDT 24 108486410 ps
T933 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4127380329 May 14 12:50:43 PM PDT 24 May 14 12:50:48 PM PDT 24 105225121 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1460052655 May 14 12:50:32 PM PDT 24 May 14 12:50:34 PM PDT 24 66653369 ps
T145 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.373940454 May 14 12:51:03 PM PDT 24 May 14 12:51:07 PM PDT 24 429807780 ps
T935 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3976383206 May 14 12:50:42 PM PDT 24 May 14 12:50:45 PM PDT 24 55785075 ps
T936 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3620759118 May 14 12:50:30 PM PDT 24 May 14 12:50:33 PM PDT 24 16711881 ps
T937 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4137811594 May 14 12:50:54 PM PDT 24 May 14 12:50:56 PM PDT 24 13076868 ps
T938 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1061277563 May 14 12:50:43 PM PDT 24 May 14 12:50:46 PM PDT 24 100456324 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3874789283 May 14 12:50:28 PM PDT 24 May 14 12:50:30 PM PDT 24 18202460 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.408704203 May 14 12:50:26 PM PDT 24 May 14 12:50:29 PM PDT 24 67235271 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1450151855 May 14 12:50:31 PM PDT 24 May 14 12:50:35 PM PDT 24 66904234 ps
T133 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3418804853 May 14 12:50:54 PM PDT 24 May 14 12:50:59 PM PDT 24 84745030 ps
T942 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3595695493 May 14 12:50:45 PM PDT 24 May 14 12:50:50 PM PDT 24 105018122 ps
T147 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1199990712 May 14 12:51:06 PM PDT 24 May 14 12:51:10 PM PDT 24 68249347 ps
T203 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2088388048 May 14 12:50:29 PM PDT 24 May 14 12:50:32 PM PDT 24 77772018 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3227634278 May 14 12:50:34 PM PDT 24 May 14 12:50:38 PM PDT 24 662293855 ps
T944 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1959191600 May 14 12:50:39 PM PDT 24 May 14 12:50:41 PM PDT 24 31062250 ps
T945 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3095904357 May 14 12:50:50 PM PDT 24 May 14 12:51:11 PM PDT 24 3465491272 ps
T946 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2895278632 May 14 12:51:06 PM PDT 24 May 14 12:51:10 PM PDT 24 31117397 ps
T947 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2993818140 May 14 12:50:55 PM PDT 24 May 14 12:50:58 PM PDT 24 21817072 ps
T152 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2819675094 May 14 12:50:42 PM PDT 24 May 14 12:50:46 PM PDT 24 429651935 ps
T948 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2615001447 May 14 12:51:05 PM PDT 24 May 14 12:51:12 PM PDT 24 310857408 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4111496839 May 14 12:50:45 PM PDT 24 May 14 12:50:49 PM PDT 24 169994152 ps
T204 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1333167873 May 14 12:50:48 PM PDT 24 May 14 12:50:50 PM PDT 24 35420161 ps
T134 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3906364549 May 14 12:50:48 PM PDT 24 May 14 12:50:53 PM PDT 24 298381617 ps
T950 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.231957361 May 14 12:50:59 PM PDT 24 May 14 12:51:06 PM PDT 24 623413623 ps
T951 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4148228259 May 14 12:50:58 PM PDT 24 May 14 12:51:01 PM PDT 24 26427404 ps
T952 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3022642131 May 14 12:50:42 PM PDT 24 May 14 12:50:44 PM PDT 24 78546768 ps
T205 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.695940743 May 14 12:50:50 PM PDT 24 May 14 12:50:52 PM PDT 24 19433778 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2003999944 May 14 12:50:36 PM PDT 24 May 14 12:50:38 PM PDT 24 46027812 ps
T954 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4200865640 May 14 12:50:41 PM PDT 24 May 14 12:50:45 PM PDT 24 45789286 ps
T955 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1769574746 May 14 12:50:42 PM PDT 24 May 14 12:50:46 PM PDT 24 18880320 ps
T956 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2290475592 May 14 12:50:50 PM PDT 24 May 14 12:50:53 PM PDT 24 57384936 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3476214986 May 14 12:50:42 PM PDT 24 May 14 12:50:48 PM PDT 24 436896456 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3645974208 May 14 12:50:57 PM PDT 24 May 14 12:51:07 PM PDT 24 808723189 ps
T959 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3631710098 May 14 12:51:05 PM PDT 24 May 14 12:51:07 PM PDT 24 15824130 ps
T149 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.43852902 May 14 12:50:56 PM PDT 24 May 14 12:51:01 PM PDT 24 353168334 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2609613904 May 14 12:50:42 PM PDT 24 May 14 12:50:45 PM PDT 24 137134528 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1794640818 May 14 12:50:32 PM PDT 24 May 14 12:50:34 PM PDT 24 87509732 ps
T962 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1543453599 May 14 12:50:33 PM PDT 24 May 14 12:50:42 PM PDT 24 811300679 ps
T963 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.304275921 May 14 12:50:35 PM PDT 24 May 14 12:50:38 PM PDT 24 407406164 ps
T140 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2814128493 May 14 12:50:30 PM PDT 24 May 14 12:50:34 PM PDT 24 196354962 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.438661246 May 14 12:50:33 PM PDT 24 May 14 12:50:35 PM PDT 24 244732701 ps
T965 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.48696800 May 14 12:50:40 PM PDT 24 May 14 12:50:42 PM PDT 24 52809840 ps
T966 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.487315660 May 14 12:50:55 PM PDT 24 May 14 12:50:58 PM PDT 24 147942629 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3098162141 May 14 12:50:35 PM PDT 24 May 14 12:50:37 PM PDT 24 14073879 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1381821910 May 14 12:50:31 PM PDT 24 May 14 12:50:34 PM PDT 24 130205447 ps
T969 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3153519986 May 14 12:50:50 PM PDT 24 May 14 12:50:53 PM PDT 24 71950667 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2857691208 May 14 12:50:27 PM PDT 24 May 14 12:50:29 PM PDT 24 24647798 ps
T971 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3872540202 May 14 12:50:59 PM PDT 24 May 14 12:51:24 PM PDT 24 3763614919 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4246228938 May 14 12:50:41 PM PDT 24 May 14 12:50:50 PM PDT 24 2087143973 ps
T973 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2550798540 May 14 12:50:46 PM PDT 24 May 14 12:50:53 PM PDT 24 994537717 ps
T974 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2830946188 May 14 12:50:49 PM PDT 24 May 14 12:50:52 PM PDT 24 143067158 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2391031581 May 14 12:50:36 PM PDT 24 May 14 12:50:41 PM PDT 24 90927496 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3750300676 May 14 12:50:34 PM PDT 24 May 14 12:50:39 PM PDT 24 119549087 ps
T209 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1215380664 May 14 12:50:26 PM PDT 24 May 14 12:50:29 PM PDT 24 105180650 ps
T977 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.653328603 May 14 12:50:42 PM PDT 24 May 14 12:50:46 PM PDT 24 33186733 ps
T206 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.267633940 May 14 12:50:54 PM PDT 24 May 14 12:50:56 PM PDT 24 54685605 ps
T978 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1649379594 May 14 12:50:48 PM PDT 24 May 14 12:50:51 PM PDT 24 206184035 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2757803109 May 14 12:50:46 PM PDT 24 May 14 12:50:50 PM PDT 24 147754417 ps
T980 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1913875043 May 14 12:50:39 PM PDT 24 May 14 12:50:42 PM PDT 24 81794546 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1413466944 May 14 12:50:51 PM PDT 24 May 14 12:50:55 PM PDT 24 42927011 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.992304543 May 14 12:50:39 PM PDT 24 May 14 12:50:42 PM PDT 24 90250735 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1418805065 May 14 12:50:54 PM PDT 24 May 14 12:50:57 PM PDT 24 44927472 ps
T148 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1617062442 May 14 12:50:41 PM PDT 24 May 14 12:50:47 PM PDT 24 309644156 ps
T146 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2781136104 May 14 12:50:54 PM PDT 24 May 14 12:50:58 PM PDT 24 60878670 ps
T207 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2740374549 May 14 12:50:42 PM PDT 24 May 14 12:50:45 PM PDT 24 14544297 ps
T984 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.63707829 May 14 12:50:56 PM PDT 24 May 14 12:50:59 PM PDT 24 42496114 ps
T985 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3168751809 May 14 12:50:42 PM PDT 24 May 14 12:50:45 PM PDT 24 55797705 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2499082922 May 14 12:50:45 PM PDT 24 May 14 12:50:49 PM PDT 24 383273877 ps
T987 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4111840254 May 14 12:50:53 PM PDT 24 May 14 12:50:56 PM PDT 24 100455253 ps
T988 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.446236193 May 14 12:50:42 PM PDT 24 May 14 12:50:45 PM PDT 24 21122250 ps
T989 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.35630595 May 14 12:50:39 PM PDT 24 May 14 12:50:43 PM PDT 24 236643626 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1686375103 May 14 12:50:33 PM PDT 24 May 14 12:50:42 PM PDT 24 1002519639 ps
T991 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3026161071 May 14 12:50:44 PM PDT 24 May 14 12:50:48 PM PDT 24 276465233 ps
T992 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2907631706 May 14 12:50:49 PM PDT 24 May 14 12:50:51 PM PDT 24 50194133 ps
T993 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.217669150 May 14 12:50:26 PM PDT 24 May 14 12:50:28 PM PDT 24 149590496 ps
T994 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.890032859 May 14 12:50:42 PM PDT 24 May 14 12:50:59 PM PDT 24 2760053497 ps
T995 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3379838632 May 14 12:50:35 PM PDT 24 May 14 12:50:39 PM PDT 24 81090414 ps
T996 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1924888898 May 14 12:50:28 PM PDT 24 May 14 12:50:30 PM PDT 24 16645427 ps
T997 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2644760536 May 14 12:50:45 PM PDT 24 May 14 12:50:48 PM PDT 24 56777701 ps
T135 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2084125906 May 14 12:50:52 PM PDT 24 May 14 12:50:56 PM PDT 24 445995942 ps
T141 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2818368937 May 14 12:50:30 PM PDT 24 May 14 12:50:34 PM PDT 24 54185347 ps
T208 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3247067005 May 14 12:50:33 PM PDT 24 May 14 12:50:36 PM PDT 24 173162592 ps
T151 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2614167292 May 14 12:50:51 PM PDT 24 May 14 12:50:56 PM PDT 24 256247785 ps
T998 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3022054669 May 14 12:50:45 PM PDT 24 May 14 12:50:49 PM PDT 24 352056052 ps
T210 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2796348894 May 14 12:50:35 PM PDT 24 May 14 12:50:38 PM PDT 24 19277364 ps
T999 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3492363084 May 14 12:50:50 PM PDT 24 May 14 12:50:53 PM PDT 24 88659677 ps
T150 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1311672172 May 14 12:50:26 PM PDT 24 May 14 12:50:29 PM PDT 24 1223874198 ps
T211 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1317833347 May 14 12:50:33 PM PDT 24 May 14 12:50:35 PM PDT 24 13566253 ps
T1000 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1505391735 May 14 12:50:26 PM PDT 24 May 14 12:50:29 PM PDT 24 135663636 ps

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1388439966
Short name T4
Test name
Test status
Simulation time 2119473870 ps
CPU time 81.93 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:54:22 PM PDT 24
Peak memory 273708 kb
Host smart-5a08cf55-1ab7-4cb9-847b-737026a8fdea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388439966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1388439966
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1468059011
Short name T13
Test name
Test status
Simulation time 356615806 ps
CPU time 10.45 seconds
Started May 14 12:53:44 PM PDT 24
Finished May 14 12:53:56 PM PDT 24
Peak memory 225304 kb
Host smart-7c42b946-cbdd-42d3-822f-2b18a32ea4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468059011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1468059011
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3353466977
Short name T89
Test name
Test status
Simulation time 11958263663 ps
CPU time 481.34 seconds
Started May 14 12:52:16 PM PDT 24
Finished May 14 01:00:20 PM PDT 24
Peak memory 294420 kb
Host smart-5b688877-2a5c-4d28-8f90-02279085dafc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3353466977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3353466977
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3505684846
Short name T14
Test name
Test status
Simulation time 418731980 ps
CPU time 13.04 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 218840 kb
Host smart-688a267f-4d72-4ef6-98c1-7017d42fe452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505684846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3505684846
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.993935642
Short name T31
Test name
Test status
Simulation time 14908808 ps
CPU time 1.02 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:53:55 PM PDT 24
Peak memory 208872 kb
Host smart-65df17bc-7217-4a1f-bd05-f5e659e3664e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993935642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.993935642
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3158310988
Short name T123
Test name
Test status
Simulation time 65653846 ps
CPU time 1.38 seconds
Started May 14 12:50:28 PM PDT 24
Finished May 14 12:50:30 PM PDT 24
Peak memory 219852 kb
Host smart-1c6666f8-e9e9-40ee-91fa-288f51643aad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315831
0988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3158310988
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1927436048
Short name T40
Test name
Test status
Simulation time 403173832 ps
CPU time 10.38 seconds
Started May 14 12:54:13 PM PDT 24
Finished May 14 12:54:25 PM PDT 24
Peak memory 217952 kb
Host smart-455409c2-2665-4f00-9fbc-581c53450606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927436048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1927436048
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.454386591
Short name T50
Test name
Test status
Simulation time 224471805 ps
CPU time 7.19 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 224964 kb
Host smart-76082a3d-a651-4d41-ab6c-25f9a84695a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454386591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.454386591
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1587757494
Short name T53
Test name
Test status
Simulation time 451089024 ps
CPU time 23.81 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:46 PM PDT 24
Peak memory 282128 kb
Host smart-be92a877-a7b9-4110-9769-bbd350a13798
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587757494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1587757494
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.709772163
Short name T181
Test name
Test status
Simulation time 381415267 ps
CPU time 8.75 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 224352 kb
Host smart-9fdb2004-b0ab-4d85-9198-999dd838c7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709772163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.709772163
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1769183146
Short name T93
Test name
Test status
Simulation time 32000806893 ps
CPU time 526.33 seconds
Started May 14 12:52:28 PM PDT 24
Finished May 14 01:01:16 PM PDT 24
Peak memory 330992 kb
Host smart-58399d6f-9e5c-4581-972a-27b453aa05e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1769183146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.1769183146
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1357259362
Short name T42
Test name
Test status
Simulation time 5946480268 ps
CPU time 271.06 seconds
Started May 14 12:52:43 PM PDT 24
Finished May 14 12:57:17 PM PDT 24
Peak memory 316456 kb
Host smart-c04649d0-6755-43b9-907e-b5811fdfda28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357259362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1357259362
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.978690985
Short name T128
Test name
Test status
Simulation time 655966801 ps
CPU time 3.14 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 221976 kb
Host smart-d1786c36-a0cf-4247-b5ef-3e411015bfb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978690985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.978690985
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1302842505
Short name T130
Test name
Test status
Simulation time 64425909 ps
CPU time 1.11 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 209220 kb
Host smart-02dfb9ac-d93d-4dff-a42b-4152ca476b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302842505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1302842505
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1851059876
Short name T6
Test name
Test status
Simulation time 166621040 ps
CPU time 2.53 seconds
Started May 14 12:53:23 PM PDT 24
Finished May 14 12:53:26 PM PDT 24
Peak memory 209464 kb
Host smart-e6bb85d5-e414-4224-ba80-c0ce63fbc506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851059876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1851059876
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1645238937
Short name T10
Test name
Test status
Simulation time 18363146 ps
CPU time 1.16 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 209452 kb
Host smart-6a45c89b-a63d-41b6-9aef-4cf6f509121f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645238937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1645238937
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.668047575
Short name T121
Test name
Test status
Simulation time 122871078 ps
CPU time 3.75 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 217396 kb
Host smart-65f5b887-a48b-49e0-817b-440de9522b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668047575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.668047575
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1252219568
Short name T46
Test name
Test status
Simulation time 7590010464 ps
CPU time 137.97 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:56:03 PM PDT 24
Peak memory 267728 kb
Host smart-4d078cf2-3cbf-4d0a-8229-18e4cf6f1753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252219568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1252219568
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2671082158
Short name T201
Test name
Test status
Simulation time 14108790 ps
CPU time 0.87 seconds
Started May 14 12:50:25 PM PDT 24
Finished May 14 12:50:27 PM PDT 24
Peak memory 209200 kb
Host smart-1ad205ae-fb5d-48e5-8f11-e75a8919b64e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671082158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2671082158
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.861473135
Short name T15
Test name
Test status
Simulation time 232691679 ps
CPU time 8 seconds
Started May 14 12:53:06 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 217948 kb
Host smart-de155d5e-b708-45c4-8b86-fa4ce46685ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861473135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.861473135
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1199990712
Short name T147
Test name
Test status
Simulation time 68249347 ps
CPU time 2.79 seconds
Started May 14 12:51:06 PM PDT 24
Finished May 14 12:51:10 PM PDT 24
Peak memory 217420 kb
Host smart-d3db912b-40e6-425e-8d96-e05b8acc699e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199990712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1199990712
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1522956726
Short name T142
Test name
Test status
Simulation time 140765879 ps
CPU time 2.52 seconds
Started May 14 12:50:54 PM PDT 24
Finished May 14 12:50:58 PM PDT 24
Peak memory 221968 kb
Host smart-78c2dbbb-4560-4ded-a583-d10096f808f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522956726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1522956726
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.373940454
Short name T145
Test name
Test status
Simulation time 429807780 ps
CPU time 3 seconds
Started May 14 12:51:03 PM PDT 24
Finished May 14 12:51:07 PM PDT 24
Peak memory 221812 kb
Host smart-f55c13db-6d9e-4294-b9a0-9543fea844a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373940454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.373940454
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1830997835
Short name T116
Test name
Test status
Simulation time 192701319211 ps
CPU time 254.36 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:57:46 PM PDT 24
Peak memory 272908 kb
Host smart-0dc42a27-f7de-4dea-8ddf-350d801495f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830997835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1830997835
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.261934188
Short name T154
Test name
Test status
Simulation time 301728668 ps
CPU time 1.99 seconds
Started May 14 12:50:29 PM PDT 24
Finished May 14 12:50:32 PM PDT 24
Peak memory 209028 kb
Host smart-19f3de72-0014-42e6-9628-60031b6ba0bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261934188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.261934188
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2915813857
Short name T138
Test name
Test status
Simulation time 119039514 ps
CPU time 2.93 seconds
Started May 14 12:50:55 PM PDT 24
Finished May 14 12:51:00 PM PDT 24
Peak memory 222212 kb
Host smart-5cb3cdd6-9336-43cc-ab9d-39d5945cb53e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915813857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2915813857
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1652006424
Short name T92
Test name
Test status
Simulation time 41786174728 ps
CPU time 2582.64 seconds
Started May 14 12:53:55 PM PDT 24
Finished May 14 01:37:02 PM PDT 24
Peak memory 1517920 kb
Host smart-d92223c6-3c5c-4c5a-bbf3-f68946a3f8fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1652006424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1652006424
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.54503716
Short name T95
Test name
Test status
Simulation time 25321975070 ps
CPU time 3445.63 seconds
Started May 14 12:54:33 PM PDT 24
Finished May 14 01:52:02 PM PDT 24
Peak memory 644464 kb
Host smart-eeea3ac4-47eb-4e2d-ac81-69ee40b3e0e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=54503716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.54503716
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2855765298
Short name T11
Test name
Test status
Simulation time 464473460 ps
CPU time 17.02 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:40 PM PDT 24
Peak memory 217952 kb
Host smart-a7fa9263-0c54-426a-bf46-db0bb428070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855765298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2855765298
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2818368937
Short name T141
Test name
Test status
Simulation time 54185347 ps
CPU time 2.75 seconds
Started May 14 12:50:30 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 217548 kb
Host smart-6135c6e3-fa19-43a6-af9e-3001b233aba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818368937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2818368937
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3906364549
Short name T134
Test name
Test status
Simulation time 298381617 ps
CPU time 3.41 seconds
Started May 14 12:50:48 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 217296 kb
Host smart-265b7e83-0cc1-487b-9bb8-18eb78131dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906364549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3906364549
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2819675094
Short name T152
Test name
Test status
Simulation time 429651935 ps
CPU time 2.02 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 221716 kb
Host smart-1e477fd2-1e70-42c2-bfbb-37395c26572b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819675094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2819675094
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.770719449
Short name T221
Test name
Test status
Simulation time 22513149 ps
CPU time 0.94 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 209416 kb
Host smart-733a6a7b-254c-48c7-acbd-1806e78a62f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770719449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.770719449
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.334666452
Short name T222
Test name
Test status
Simulation time 18633694 ps
CPU time 0.83 seconds
Started May 14 12:52:16 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 209400 kb
Host smart-162e25f2-cf43-4ed0-89e0-b7a01f085ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334666452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.334666452
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3132062898
Short name T220
Test name
Test status
Simulation time 31081479 ps
CPU time 0.78 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:52:50 PM PDT 24
Peak memory 209416 kb
Host smart-e6f0a427-9888-4a7e-b1c9-879a09d86e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132062898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3132062898
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2307519486
Short name T127
Test name
Test status
Simulation time 432089533 ps
CPU time 3.05 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 221888 kb
Host smart-6cf05a51-a406-4b0d-883e-e36d5b02c989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307519486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2307519486
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3967525132
Short name T143
Test name
Test status
Simulation time 126849905 ps
CPU time 4.11 seconds
Started May 14 12:50:49 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 217488 kb
Host smart-0f334e00-2608-4794-a73e-db1c49e26c96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967525132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3967525132
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2614167292
Short name T151
Test name
Test status
Simulation time 256247785 ps
CPU time 2.61 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 217432 kb
Host smart-d1e7c75a-f8ee-4885-9583-45b9168d6d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614167292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2614167292
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2699198893
Short name T32
Test name
Test status
Simulation time 1135999654 ps
CPU time 7.56 seconds
Started May 14 12:53:36 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 225336 kb
Host smart-fcf5d27e-d9a7-4ad5-879d-e02c4c499123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699198893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2699198893
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1702846431
Short name T20
Test name
Test status
Simulation time 7957424051 ps
CPU time 29.15 seconds
Started May 14 12:52:16 PM PDT 24
Finished May 14 12:52:48 PM PDT 24
Peak memory 218944 kb
Host smart-08f9d30e-46df-4fbe-8ca2-e3a3ad6e1ce4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702846431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1702846431
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3620759118
Short name T936
Test name
Test status
Simulation time 16711881 ps
CPU time 0.95 seconds
Started May 14 12:50:30 PM PDT 24
Finished May 14 12:50:33 PM PDT 24
Peak memory 208548 kb
Host smart-98bd1e5d-5442-4d7d-af9a-27680b4b6a20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620759118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3620759118
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1215380664
Short name T209
Test name
Test status
Simulation time 105180650 ps
CPU time 1.82 seconds
Started May 14 12:50:26 PM PDT 24
Finished May 14 12:50:29 PM PDT 24
Peak memory 208316 kb
Host smart-e79b4ee5-cb6b-45fa-887c-7c883a863fcc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215380664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1215380664
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2003999944
Short name T953
Test name
Test status
Simulation time 46027812 ps
CPU time 1.02 seconds
Started May 14 12:50:36 PM PDT 24
Finished May 14 12:50:38 PM PDT 24
Peak memory 209668 kb
Host smart-b39b9039-0073-481d-8a5c-9777ef455f34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003999944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2003999944
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1905133115
Short name T120
Test name
Test status
Simulation time 32105233 ps
CPU time 2.41 seconds
Started May 14 12:50:30 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 225092 kb
Host smart-16374499-472f-41cb-b098-581bdc562f2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905133115 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1905133115
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3583685919
Short name T909
Test name
Test status
Simulation time 37287298 ps
CPU time 1.11 seconds
Started May 14 12:50:27 PM PDT 24
Finished May 14 12:50:30 PM PDT 24
Peak memory 209064 kb
Host smart-17c37fcf-3f9b-4bc2-8bfb-c9bbbf309235
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583685919 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3583685919
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2613916281
Short name T919
Test name
Test status
Simulation time 3084370730 ps
CPU time 7.66 seconds
Started May 14 12:50:30 PM PDT 24
Finished May 14 12:50:39 PM PDT 24
Peak memory 208556 kb
Host smart-10040678-83fd-4580-8c12-d5766ba9e553
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613916281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2613916281
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4090105865
Short name T912
Test name
Test status
Simulation time 1084663591 ps
CPU time 23.72 seconds
Started May 14 12:50:32 PM PDT 24
Finished May 14 12:50:57 PM PDT 24
Peak memory 209108 kb
Host smart-3ce09c59-fd89-4b4f-aab6-3e3ec9a881e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090105865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4090105865
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.408704203
Short name T940
Test name
Test status
Simulation time 67235271 ps
CPU time 1.39 seconds
Started May 14 12:50:26 PM PDT 24
Finished May 14 12:50:29 PM PDT 24
Peak memory 210320 kb
Host smart-d7ca17ee-b440-449c-8416-9d4b39c4d4a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408704203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.408704203
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1185391177
Short name T882
Test name
Test status
Simulation time 133841943 ps
CPU time 3.99 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:38 PM PDT 24
Peak memory 217612 kb
Host smart-105ed90a-633d-4d44-b0d4-496a1fb8b3d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118539
1177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1185391177
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1673197712
Short name T171
Test name
Test status
Simulation time 108178466 ps
CPU time 1.46 seconds
Started May 14 12:50:28 PM PDT 24
Finished May 14 12:50:31 PM PDT 24
Peak memory 209184 kb
Host smart-7c67b0f4-8131-4a5d-9c22-f4666dd9bf8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673197712 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1673197712
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1505391735
Short name T1000
Test name
Test status
Simulation time 135663636 ps
CPU time 1.88 seconds
Started May 14 12:50:26 PM PDT 24
Finished May 14 12:50:29 PM PDT 24
Peak memory 210880 kb
Host smart-c760f9c0-836f-4dba-b1fe-cc20a3f67b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505391735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1505391735
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.35630595
Short name T989
Test name
Test status
Simulation time 236643626 ps
CPU time 2.61 seconds
Started May 14 12:50:39 PM PDT 24
Finished May 14 12:50:43 PM PDT 24
Peak memory 217464 kb
Host smart-397f63fb-83e8-4229-946b-e6dd67322747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35630595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.35630595
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2857691208
Short name T970
Test name
Test status
Simulation time 24647798 ps
CPU time 1.16 seconds
Started May 14 12:50:27 PM PDT 24
Finished May 14 12:50:29 PM PDT 24
Peak memory 209188 kb
Host smart-cf0710fa-9c4e-444f-aa93-8e96093713d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857691208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2857691208
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1450151855
Short name T941
Test name
Test status
Simulation time 66904234 ps
CPU time 2.63 seconds
Started May 14 12:50:31 PM PDT 24
Finished May 14 12:50:35 PM PDT 24
Peak memory 208880 kb
Host smart-6820e0e6-61ff-4631-a62c-03a7be3f574c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450151855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1450151855
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.695940743
Short name T205
Test name
Test status
Simulation time 19433778 ps
CPU time 1.01 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:50:52 PM PDT 24
Peak memory 210804 kb
Host smart-cdbe51e3-ad26-429d-820a-a012c36846ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695940743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.695940743
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3639599626
Short name T888
Test name
Test status
Simulation time 109910954 ps
CPU time 2.14 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:51:01 PM PDT 24
Peak memory 217408 kb
Host smart-d29b1edd-dc1a-4229-baec-31c5cd6380ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639599626 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3639599626
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3976383206
Short name T935
Test name
Test status
Simulation time 55785075 ps
CPU time 1.12 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:45 PM PDT 24
Peak memory 209164 kb
Host smart-134abd7f-1e58-46e1-8cac-d60b4c8fc01d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976383206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3976383206
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1301606961
Short name T893
Test name
Test status
Simulation time 38377175 ps
CPU time 1.01 seconds
Started May 14 12:50:39 PM PDT 24
Finished May 14 12:50:41 PM PDT 24
Peak memory 209104 kb
Host smart-6c25fbf5-e102-4fb6-994c-ec777f46a023
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301606961 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1301606961
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1201688736
Short name T918
Test name
Test status
Simulation time 3855190231 ps
CPU time 23.48 seconds
Started May 14 12:50:29 PM PDT 24
Finished May 14 12:50:54 PM PDT 24
Peak memory 209224 kb
Host smart-72632d32-7f84-48ba-9a32-e46cc379fbd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201688736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1201688736
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.79271929
Short name T930
Test name
Test status
Simulation time 13360104342 ps
CPU time 9.29 seconds
Started May 14 12:50:38 PM PDT 24
Finished May 14 12:50:48 PM PDT 24
Peak memory 209164 kb
Host smart-faf44dfe-c4f4-413d-97b8-3934c5ee2367
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79271929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.79271929
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3026161071
Short name T991
Test name
Test status
Simulation time 276465233 ps
CPU time 2 seconds
Started May 14 12:50:44 PM PDT 24
Finished May 14 12:50:48 PM PDT 24
Peak memory 210496 kb
Host smart-90790d28-9497-40e1-b050-0ffdb5376cb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026161071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3026161071
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1595435574
Short name T890
Test name
Test status
Simulation time 342866213 ps
CPU time 2.94 seconds
Started May 14 12:50:35 PM PDT 24
Finished May 14 12:50:39 PM PDT 24
Peak memory 222812 kb
Host smart-22c22bf4-753a-4d2a-a595-10aa2421719d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159543
5574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1595435574
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3695571698
Short name T914
Test name
Test status
Simulation time 276340985 ps
CPU time 2.23 seconds
Started May 14 12:50:39 PM PDT 24
Finished May 14 12:50:43 PM PDT 24
Peak memory 209080 kb
Host smart-3fe54d1d-85bb-4689-a8a6-302a7be6c4bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695571698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3695571698
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1381821910
Short name T968
Test name
Test status
Simulation time 130205447 ps
CPU time 1.94 seconds
Started May 14 12:50:31 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 211260 kb
Host smart-496b94bc-19e5-455b-a608-d1f602c2c718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381821910 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1381821910
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3874789283
Short name T939
Test name
Test status
Simulation time 18202460 ps
CPU time 1.36 seconds
Started May 14 12:50:28 PM PDT 24
Finished May 14 12:50:30 PM PDT 24
Peak memory 209168 kb
Host smart-29b21256-4aac-4c46-9c1f-25def0219fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874789283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3874789283
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1630307967
Short name T139
Test name
Test status
Simulation time 195069701 ps
CPU time 4.18 seconds
Started May 14 12:50:30 PM PDT 24
Finished May 14 12:50:35 PM PDT 24
Peak memory 217512 kb
Host smart-0d8a1b03-e0c6-4948-90b5-b78ebba6970e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630307967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1630307967
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1061277563
Short name T938
Test name
Test status
Simulation time 100456324 ps
CPU time 1.23 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 218476 kb
Host smart-451c82bc-b73e-48db-aca6-1d6dacba6890
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061277563 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1061277563
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3271830002
Short name T885
Test name
Test status
Simulation time 30611965 ps
CPU time 1.05 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:54 PM PDT 24
Peak memory 217220 kb
Host smart-49ebb484-7d68-4a6b-8b38-131689fcbbff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271830002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3271830002
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4148228259
Short name T951
Test name
Test status
Simulation time 26427404 ps
CPU time 0.95 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:01 PM PDT 24
Peak memory 209348 kb
Host smart-bdb5757c-9806-455f-bb60-48ff6e68a580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148228259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.4148228259
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1769574746
Short name T955
Test name
Test status
Simulation time 18880320 ps
CPU time 1.06 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 218536 kb
Host smart-000bbdb6-3270-495c-9c4e-e6ee39f2c7c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769574746 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1769574746
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.653328603
Short name T977
Test name
Test status
Simulation time 33186733 ps
CPU time 1.6 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 209324 kb
Host smart-def10b95-8ae7-45ef-8e9b-e869d21e5e0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653328603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.653328603
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2550798540
Short name T973
Test name
Test status
Simulation time 994537717 ps
CPU time 5.62 seconds
Started May 14 12:50:46 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 217488 kb
Host smart-833b4eda-8b83-4678-8abe-52e6ae7804bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550798540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2550798540
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3877907460
Short name T183
Test name
Test status
Simulation time 42881488 ps
CPU time 1.16 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:44 PM PDT 24
Peak memory 219192 kb
Host smart-14344783-dfe9-4390-891e-2f170654f9c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877907460 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3877907460
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.446236193
Short name T988
Test name
Test status
Simulation time 21122250 ps
CPU time 1.03 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:45 PM PDT 24
Peak memory 209232 kb
Host smart-d6ea6a3e-e5c3-48fa-8fe2-f4debed12994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446236193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.446236193
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2501493126
Short name T928
Test name
Test status
Simulation time 55233723 ps
CPU time 0.98 seconds
Started May 14 12:50:55 PM PDT 24
Finished May 14 12:50:57 PM PDT 24
Peak memory 209104 kb
Host smart-9714cd2a-2404-4706-b2fc-efc0e1cd6921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501493126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2501493126
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3595695493
Short name T942
Test name
Test status
Simulation time 105018122 ps
CPU time 3.06 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 217480 kb
Host smart-32aa2113-e5d9-4c05-aa6d-c0c734a936bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595695493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3595695493
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.136454830
Short name T119
Test name
Test status
Simulation time 22970039 ps
CPU time 1.54 seconds
Started May 14 12:51:08 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 219212 kb
Host smart-efe3a839-0bcd-4adb-8a36-b9a46d31eac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136454830 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.136454830
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.547311914
Short name T920
Test name
Test status
Simulation time 15581072 ps
CPU time 1.06 seconds
Started May 14 12:50:52 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 209224 kb
Host smart-35b5e62d-a510-4879-b76a-c6faae3cbd6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547311914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.547311914
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.625110097
Short name T212
Test name
Test status
Simulation time 25136845 ps
CPU time 1.11 seconds
Started May 14 12:51:06 PM PDT 24
Finished May 14 12:51:09 PM PDT 24
Peak memory 209312 kb
Host smart-b632c7c3-5f0d-4c5d-8c3e-e4e441fa2069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625110097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.625110097
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4127380329
Short name T933
Test name
Test status
Simulation time 105225121 ps
CPU time 2.51 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:50:48 PM PDT 24
Peak memory 217976 kb
Host smart-71f1e678-ede0-4c15-a3f1-84c471cf6c28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127380329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.4127380329
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3418804853
Short name T133
Test name
Test status
Simulation time 84745030 ps
CPU time 3.65 seconds
Started May 14 12:50:54 PM PDT 24
Finished May 14 12:50:59 PM PDT 24
Peak memory 222136 kb
Host smart-47667fc5-da93-4c8b-aefa-bae47735a9ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418804853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3418804853
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.63707829
Short name T984
Test name
Test status
Simulation time 42496114 ps
CPU time 1.13 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:50:59 PM PDT 24
Peak memory 219464 kb
Host smart-bbd6f6bb-d2c7-465b-a502-1314bb297839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63707829 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.63707829
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3032215608
Short name T202
Test name
Test status
Simulation time 13522297 ps
CPU time 1 seconds
Started May 14 12:51:05 PM PDT 24
Finished May 14 12:51:07 PM PDT 24
Peak memory 208664 kb
Host smart-2c450793-819e-412e-91eb-88fa4710dd83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032215608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3032215608
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2830946188
Short name T974
Test name
Test status
Simulation time 143067158 ps
CPU time 1.47 seconds
Started May 14 12:50:49 PM PDT 24
Finished May 14 12:50:52 PM PDT 24
Peak memory 211232 kb
Host smart-b9116b5c-303d-4b02-8f4b-44bc78a901f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830946188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2830946188
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2895278632
Short name T946
Test name
Test status
Simulation time 31117397 ps
CPU time 1.98 seconds
Started May 14 12:51:06 PM PDT 24
Finished May 14 12:51:10 PM PDT 24
Peak memory 217508 kb
Host smart-1c1add44-7838-4ebc-945d-ba86083b48c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895278632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2895278632
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4002458735
Short name T129
Test name
Test status
Simulation time 246355394 ps
CPU time 2.63 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:50:57 PM PDT 24
Peak memory 221864 kb
Host smart-32fe995e-7a2d-4e70-b1b0-2e08d4331618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002458735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.4002458735
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2993818140
Short name T947
Test name
Test status
Simulation time 21817072 ps
CPU time 1.64 seconds
Started May 14 12:50:55 PM PDT 24
Finished May 14 12:50:58 PM PDT 24
Peak memory 219048 kb
Host smart-2815551e-975d-412a-b4a1-1372b8ef78ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993818140 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2993818140
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3631710098
Short name T959
Test name
Test status
Simulation time 15824130 ps
CPU time 0.86 seconds
Started May 14 12:51:05 PM PDT 24
Finished May 14 12:51:07 PM PDT 24
Peak memory 209228 kb
Host smart-02e7023a-6710-47f7-a918-6d6853ba1405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631710098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3631710098
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.529935799
Short name T926
Test name
Test status
Simulation time 33249327 ps
CPU time 1.46 seconds
Started May 14 12:50:49 PM PDT 24
Finished May 14 12:50:52 PM PDT 24
Peak memory 209232 kb
Host smart-cf563e25-de31-45b9-a480-a19e003edfac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529935799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.529935799
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2615001447
Short name T948
Test name
Test status
Simulation time 310857408 ps
CPU time 5.71 seconds
Started May 14 12:51:05 PM PDT 24
Finished May 14 12:51:12 PM PDT 24
Peak memory 217476 kb
Host smart-7c1ae904-1873-429e-bc3f-009da4e1083d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615001447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2615001447
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2003028535
Short name T891
Test name
Test status
Simulation time 19511914 ps
CPU time 1.26 seconds
Started May 14 12:50:52 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 217496 kb
Host smart-8959a2cb-3a09-49ad-a285-e35dcc2b77c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003028535 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2003028535
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.267633940
Short name T206
Test name
Test status
Simulation time 54685605 ps
CPU time 0.84 seconds
Started May 14 12:50:54 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 209212 kb
Host smart-4c5c1b51-a49f-4aaa-8bdb-6425accdef92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267633940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.267633940
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2290475592
Short name T956
Test name
Test status
Simulation time 57384936 ps
CPU time 1.16 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 209120 kb
Host smart-05382b8a-3ec9-46ec-ad37-383a4271144c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290475592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2290475592
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1518044235
Short name T173
Test name
Test status
Simulation time 134838600 ps
CPU time 3.6 seconds
Started May 14 12:50:55 PM PDT 24
Finished May 14 12:51:00 PM PDT 24
Peak memory 217548 kb
Host smart-631b6598-4f7e-49e9-9e84-03211eaba01e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518044235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1518044235
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3994555799
Short name T913
Test name
Test status
Simulation time 31427767 ps
CPU time 1.41 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:51:03 PM PDT 24
Peak memory 217568 kb
Host smart-a405d85d-ec74-474c-8458-13782dfd3706
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994555799 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3994555799
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4137811594
Short name T937
Test name
Test status
Simulation time 13076868 ps
CPU time 0.9 seconds
Started May 14 12:50:54 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 209192 kb
Host smart-e92f95a5-6136-4bac-a6c9-a877c39fee47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137811594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4137811594
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3153519986
Short name T969
Test name
Test status
Simulation time 71950667 ps
CPU time 1.25 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 209144 kb
Host smart-f69e0a4d-96de-4d68-b921-bac605265d85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153519986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3153519986
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2530677026
Short name T910
Test name
Test status
Simulation time 392828692 ps
CPU time 3.4 seconds
Started May 14 12:51:04 PM PDT 24
Finished May 14 12:51:14 PM PDT 24
Peak memory 217452 kb
Host smart-708728b5-753a-497a-af37-1b69809c04a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530677026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2530677026
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3171536557
Short name T144
Test name
Test status
Simulation time 114831238 ps
CPU time 4.23 seconds
Started May 14 12:51:08 PM PDT 24
Finished May 14 12:51:14 PM PDT 24
Peak memory 217372 kb
Host smart-71ad1345-1bf4-48b2-8761-20048cf5c00d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171536557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3171536557
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.822054552
Short name T124
Test name
Test status
Simulation time 48825528 ps
CPU time 1.59 seconds
Started May 14 12:51:03 PM PDT 24
Finished May 14 12:51:06 PM PDT 24
Peak memory 222360 kb
Host smart-32860ddd-731d-42b8-8d0b-91d3066ab0cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822054552 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.822054552
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3705892755
Short name T200
Test name
Test status
Simulation time 13751866 ps
CPU time 1.01 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 209180 kb
Host smart-b2a06276-9294-46b6-850d-1659a26c6241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705892755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3705892755
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.487315660
Short name T966
Test name
Test status
Simulation time 147942629 ps
CPU time 1.31 seconds
Started May 14 12:50:55 PM PDT 24
Finished May 14 12:50:58 PM PDT 24
Peak memory 209204 kb
Host smart-0d806479-ce85-4f8b-a135-f2cbb4cd44f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487315660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.487315660
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4053419426
Short name T898
Test name
Test status
Simulation time 144915787 ps
CPU time 3.98 seconds
Started May 14 12:50:49 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 217536 kb
Host smart-675dc5c4-bf51-4624-9289-c3f0ffeae925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053419426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4053419426
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2084125906
Short name T135
Test name
Test status
Simulation time 445995942 ps
CPU time 2.88 seconds
Started May 14 12:50:52 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 221780 kb
Host smart-e3654bca-781a-49cf-8b5e-9b6bc6955496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084125906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2084125906
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1629866594
Short name T172
Test name
Test status
Simulation time 71775483 ps
CPU time 1.01 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 217472 kb
Host smart-a2f79eb9-ed59-4276-9e5d-ecaefc0c909a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629866594 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1629866594
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4164389575
Short name T925
Test name
Test status
Simulation time 118002418 ps
CPU time 0.91 seconds
Started May 14 12:50:55 PM PDT 24
Finished May 14 12:50:57 PM PDT 24
Peak memory 209196 kb
Host smart-814ab013-d6d1-4104-81f3-88bf71cbb271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164389575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.4164389575
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4111840254
Short name T987
Test name
Test status
Simulation time 100455253 ps
CPU time 1.22 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:50:56 PM PDT 24
Peak memory 209192 kb
Host smart-e9bdbfe8-5b5a-45dc-9d7d-4c4ec3b4baee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111840254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.4111840254
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1332811350
Short name T896
Test name
Test status
Simulation time 227918278 ps
CPU time 3.54 seconds
Started May 14 12:51:12 PM PDT 24
Finished May 14 12:51:18 PM PDT 24
Peak memory 217540 kb
Host smart-d01d9dc9-1511-47fc-a249-b4fba9f60349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332811350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1332811350
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1794640818
Short name T961
Test name
Test status
Simulation time 87509732 ps
CPU time 1.33 seconds
Started May 14 12:50:32 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 209088 kb
Host smart-c62bdb36-f9f4-459d-b610-6e33cb2f661a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794640818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1794640818
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3816553900
Short name T894
Test name
Test status
Simulation time 39771847 ps
CPU time 1.39 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:44 PM PDT 24
Peak memory 208800 kb
Host smart-ac1591a8-4df2-4816-8e2f-ae812d8d01e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816553900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3816553900
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1494003268
Short name T136
Test name
Test status
Simulation time 23905500 ps
CPU time 0.91 seconds
Started May 14 12:50:25 PM PDT 24
Finished May 14 12:50:27 PM PDT 24
Peak memory 209348 kb
Host smart-e0d64f9e-b61d-4b80-892c-3ca9b0614db3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494003268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1494003268
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1924888898
Short name T996
Test name
Test status
Simulation time 16645427 ps
CPU time 1.27 seconds
Started May 14 12:50:28 PM PDT 24
Finished May 14 12:50:30 PM PDT 24
Peak memory 218460 kb
Host smart-eb119e01-0453-4505-95d8-4d399037d68d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924888898 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1924888898
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1317833347
Short name T211
Test name
Test status
Simulation time 13566253 ps
CPU time 1.06 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:35 PM PDT 24
Peak memory 209088 kb
Host smart-595fbdda-dba5-4f3f-a0dc-ca7c46694437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317833347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1317833347
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1913875043
Short name T980
Test name
Test status
Simulation time 81794546 ps
CPU time 1.57 seconds
Started May 14 12:50:39 PM PDT 24
Finished May 14 12:50:42 PM PDT 24
Peak memory 209080 kb
Host smart-7520ffae-b11f-4a56-a461-87f042b94994
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913875043 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1913875043
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3051945118
Short name T915
Test name
Test status
Simulation time 990490037 ps
CPU time 11.52 seconds
Started May 14 12:50:25 PM PDT 24
Finished May 14 12:50:37 PM PDT 24
Peak memory 208916 kb
Host smart-2a4489de-082f-4d17-9bca-5640e3f87a57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051945118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3051945118
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1543453599
Short name T962
Test name
Test status
Simulation time 811300679 ps
CPU time 8.66 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:42 PM PDT 24
Peak memory 208784 kb
Host smart-2b6f7829-d9f1-40e2-80ef-c397bc5a8666
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543453599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1543453599
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.190558934
Short name T887
Test name
Test status
Simulation time 4056919460 ps
CPU time 2.93 seconds
Started May 14 12:50:29 PM PDT 24
Finished May 14 12:50:33 PM PDT 24
Peak memory 210768 kb
Host smart-8422ec82-0113-4787-bbbb-b51095a46373
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190558934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.190558934
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.217669150
Short name T993
Test name
Test status
Simulation time 149590496 ps
CPU time 1.14 seconds
Started May 14 12:50:26 PM PDT 24
Finished May 14 12:50:28 PM PDT 24
Peak memory 209076 kb
Host smart-33aee0ae-c08b-4a8f-b285-bfe247fb95d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217669150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.217669150
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.235662282
Short name T916
Test name
Test status
Simulation time 74671929 ps
CPU time 1.88 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:49 PM PDT 24
Peak memory 211008 kb
Host smart-bb07cb8b-e457-419c-9af6-462d48e40dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235662282 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.235662282
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2012987432
Short name T897
Test name
Test status
Simulation time 272101375 ps
CPU time 1.06 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:45 PM PDT 24
Peak memory 209144 kb
Host smart-ec500bf3-d514-4444-9fbd-664100f11e7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012987432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2012987432
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2093793724
Short name T901
Test name
Test status
Simulation time 23827351 ps
CPU time 1.58 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 217560 kb
Host smart-c32b19cd-e0fc-4921-8d94-316578a81fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093793724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2093793724
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1311672172
Short name T150
Test name
Test status
Simulation time 1223874198 ps
CPU time 2.14 seconds
Started May 14 12:50:26 PM PDT 24
Finished May 14 12:50:29 PM PDT 24
Peak memory 221732 kb
Host smart-e439a953-5720-49d0-bff0-d8561940d141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311672172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1311672172
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2088388048
Short name T203
Test name
Test status
Simulation time 77772018 ps
CPU time 1.14 seconds
Started May 14 12:50:29 PM PDT 24
Finished May 14 12:50:32 PM PDT 24
Peak memory 209156 kb
Host smart-407d0185-2afb-4357-9752-3618633d534d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088388048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2088388048
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.146738505
Short name T904
Test name
Test status
Simulation time 33775981 ps
CPU time 1.82 seconds
Started May 14 12:50:30 PM PDT 24
Finished May 14 12:50:33 PM PDT 24
Peak memory 208332 kb
Host smart-b6e4365c-7b2f-4283-86b7-5dec64b9277b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146738505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.146738505
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3910056114
Short name T923
Test name
Test status
Simulation time 68852983 ps
CPU time 0.94 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:35 PM PDT 24
Peak memory 209448 kb
Host smart-7638dd69-bd5a-49b6-a5ba-ed82741d0c7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910056114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3910056114
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3098162141
Short name T967
Test name
Test status
Simulation time 14073879 ps
CPU time 1.15 seconds
Started May 14 12:50:35 PM PDT 24
Finished May 14 12:50:37 PM PDT 24
Peak memory 217600 kb
Host smart-35703aa9-a5c1-41bd-9cbd-ef340ea48cc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098162141 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3098162141
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.744070504
Short name T911
Test name
Test status
Simulation time 24198829 ps
CPU time 0.83 seconds
Started May 14 12:50:29 PM PDT 24
Finished May 14 12:50:31 PM PDT 24
Peak memory 209180 kb
Host smart-e5eb0d83-33cb-4098-b734-02af233498fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744070504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.744070504
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1460052655
Short name T934
Test name
Test status
Simulation time 66653369 ps
CPU time 1.39 seconds
Started May 14 12:50:32 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 209212 kb
Host smart-2c4c569c-395e-4404-87cc-d5e5f99e4400
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460052655 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1460052655
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3227634278
Short name T943
Test name
Test status
Simulation time 662293855 ps
CPU time 2.82 seconds
Started May 14 12:50:34 PM PDT 24
Finished May 14 12:50:38 PM PDT 24
Peak memory 208912 kb
Host smart-3f2e9e44-1b4d-44af-a14c-2772d6828831
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227634278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3227634278
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1953898355
Short name T906
Test name
Test status
Simulation time 339088251 ps
CPU time 8.66 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:50:54 PM PDT 24
Peak memory 208868 kb
Host smart-1a867510-7776-4c5d-ae2e-b79312db4f9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953898355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1953898355
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2499082922
Short name T986
Test name
Test status
Simulation time 383273877 ps
CPU time 2.7 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:49 PM PDT 24
Peak memory 210620 kb
Host smart-d3acf06a-358a-4c91-b7be-e89e2bd0e925
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499082922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2499082922
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2911446995
Short name T902
Test name
Test status
Simulation time 390228788 ps
CPU time 5.86 seconds
Started May 14 12:50:31 PM PDT 24
Finished May 14 12:50:38 PM PDT 24
Peak memory 219156 kb
Host smart-cae4442e-b926-4573-bbc5-8b25745d94ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291144
6995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2911446995
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.438661246
Short name T964
Test name
Test status
Simulation time 244732701 ps
CPU time 1.08 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:35 PM PDT 24
Peak memory 209000 kb
Host smart-bba67067-f3f2-47ae-9648-9911e8777c97
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438661246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.438661246
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4257086865
Short name T917
Test name
Test status
Simulation time 75656210 ps
CPU time 1.13 seconds
Started May 14 12:50:28 PM PDT 24
Finished May 14 12:50:30 PM PDT 24
Peak memory 209180 kb
Host smart-9187a9ba-d087-4ca7-8cb8-c066dc3301fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257086865 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.4257086865
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2757803109
Short name T979
Test name
Test status
Simulation time 147754417 ps
CPU time 1.91 seconds
Started May 14 12:50:46 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 211276 kb
Host smart-a13027f8-b69c-4566-ae16-7d21be4e2942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757803109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2757803109
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2391031581
Short name T975
Test name
Test status
Simulation time 90927496 ps
CPU time 3.43 seconds
Started May 14 12:50:36 PM PDT 24
Finished May 14 12:50:41 PM PDT 24
Peak memory 219152 kb
Host smart-907194c8-27db-4905-94a5-007925427a05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391031581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2391031581
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2814128493
Short name T140
Test name
Test status
Simulation time 196354962 ps
CPU time 2.44 seconds
Started May 14 12:50:30 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 217648 kb
Host smart-479ef17c-48b0-4221-89ef-5df09bb80bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814128493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2814128493
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2796348894
Short name T210
Test name
Test status
Simulation time 19277364 ps
CPU time 1.23 seconds
Started May 14 12:50:35 PM PDT 24
Finished May 14 12:50:38 PM PDT 24
Peak memory 209256 kb
Host smart-ecbe71c9-d0ef-42f1-85ef-94624eb7d6b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796348894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2796348894
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2162116754
Short name T877
Test name
Test status
Simulation time 47324204 ps
CPU time 1.58 seconds
Started May 14 12:50:35 PM PDT 24
Finished May 14 12:50:38 PM PDT 24
Peak memory 209156 kb
Host smart-0aa15786-47f5-43e7-a6ef-e825d84bb566
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162116754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2162116754
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3247067005
Short name T208
Test name
Test status
Simulation time 173162592 ps
CPU time 1.08 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:36 PM PDT 24
Peak memory 209728 kb
Host smart-65a16319-03bb-459d-8b04-b0db0cc81940
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247067005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3247067005
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1959191600
Short name T944
Test name
Test status
Simulation time 31062250 ps
CPU time 1.36 seconds
Started May 14 12:50:39 PM PDT 24
Finished May 14 12:50:41 PM PDT 24
Peak memory 223220 kb
Host smart-a87f0c5f-a0cf-4262-b248-bf1110d75363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959191600 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1959191600
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1039576666
Short name T931
Test name
Test status
Simulation time 14013807 ps
CPU time 0.91 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:35 PM PDT 24
Peak memory 209204 kb
Host smart-cb71c202-9a1a-4334-8c5d-c5f7d9948a7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039576666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1039576666
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3022054669
Short name T998
Test name
Test status
Simulation time 352056052 ps
CPU time 1.45 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:49 PM PDT 24
Peak memory 209024 kb
Host smart-84351a1c-f9a4-40ee-b78e-a3b1aa454c69
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022054669 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3022054669
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2160504592
Short name T921
Test name
Test status
Simulation time 2393626249 ps
CPU time 10.03 seconds
Started May 14 12:50:35 PM PDT 24
Finished May 14 12:50:47 PM PDT 24
Peak memory 209228 kb
Host smart-854ae2cc-337a-47b6-98ac-a80d714c8d07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160504592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2160504592
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4246228938
Short name T972
Test name
Test status
Simulation time 2087143973 ps
CPU time 8.52 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 208788 kb
Host smart-4e74159e-2fe7-443f-8863-6d9d9b3ecde5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246228938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4246228938
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.928938742
Short name T153
Test name
Test status
Simulation time 160550287 ps
CPU time 1.72 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:50:59 PM PDT 24
Peak memory 210512 kb
Host smart-4e2529f2-cc2d-4a6c-8e9b-f254c49ec75e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928938742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.928938742
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2151737563
Short name T880
Test name
Test status
Simulation time 354901622 ps
CPU time 1.55 seconds
Started May 14 12:50:38 PM PDT 24
Finished May 14 12:50:40 PM PDT 24
Peak memory 219624 kb
Host smart-99843ff7-0f94-4207-b72e-7b8c73b2ed9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215173
7563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2151737563
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2232472952
Short name T886
Test name
Test status
Simulation time 1609596774 ps
CPU time 1.99 seconds
Started May 14 12:50:40 PM PDT 24
Finished May 14 12:50:43 PM PDT 24
Peak memory 209096 kb
Host smart-f05a703c-fc2a-41b7-a15f-16c7ae608236
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232472952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2232472952
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.347701073
Short name T217
Test name
Test status
Simulation time 19573864 ps
CPU time 1.05 seconds
Started May 14 12:50:44 PM PDT 24
Finished May 14 12:50:47 PM PDT 24
Peak memory 217516 kb
Host smart-b2c18671-17aa-481d-9576-bb2d142a9c37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347701073 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.347701073
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.304275921
Short name T963
Test name
Test status
Simulation time 407406164 ps
CPU time 1.39 seconds
Started May 14 12:50:35 PM PDT 24
Finished May 14 12:50:38 PM PDT 24
Peak memory 209296 kb
Host smart-0414b6e2-4559-4097-a7d8-7685b9db2c3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304275921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.304275921
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4022357474
Short name T132
Test name
Test status
Simulation time 50668680 ps
CPU time 2.76 seconds
Started May 14 12:50:38 PM PDT 24
Finished May 14 12:50:42 PM PDT 24
Peak memory 217504 kb
Host smart-623e0221-e393-4a08-822a-481275739bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022357474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.4022357474
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2781136104
Short name T146
Test name
Test status
Simulation time 60878670 ps
CPU time 2.58 seconds
Started May 14 12:50:54 PM PDT 24
Finished May 14 12:50:58 PM PDT 24
Peak memory 217408 kb
Host smart-c887880d-3229-4e36-b13b-fd766033a3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781136104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2781136104
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1649379594
Short name T978
Test name
Test status
Simulation time 206184035 ps
CPU time 1.34 seconds
Started May 14 12:50:48 PM PDT 24
Finished May 14 12:50:51 PM PDT 24
Peak memory 217468 kb
Host smart-493e5bc9-7ca4-4ae2-8811-91b20133b50d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649379594 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1649379594
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2042093780
Short name T905
Test name
Test status
Simulation time 40808850 ps
CPU time 0.83 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:36 PM PDT 24
Peak memory 209012 kb
Host smart-730edd81-0840-490a-9584-b2beb3676c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042093780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2042093780
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1418805065
Short name T983
Test name
Test status
Simulation time 44927472 ps
CPU time 0.84 seconds
Started May 14 12:50:54 PM PDT 24
Finished May 14 12:50:57 PM PDT 24
Peak memory 208952 kb
Host smart-e6a08fcf-2e75-4c64-9ce3-97c9136e3f13
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418805065 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1418805065
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3597012820
Short name T883
Test name
Test status
Simulation time 851856337 ps
CPU time 11 seconds
Started May 14 12:50:34 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 208984 kb
Host smart-e5d72b49-aea1-4375-8071-b3ab91f5c619
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597012820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3597012820
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3872540202
Short name T971
Test name
Test status
Simulation time 3763614919 ps
CPU time 22.58 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:51:24 PM PDT 24
Peak memory 208176 kb
Host smart-b38ad224-6569-45f7-8e08-f701dfc4e5bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872540202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3872540202
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4200865640
Short name T954
Test name
Test status
Simulation time 45789286 ps
CPU time 1.9 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:45 PM PDT 24
Peak memory 210508 kb
Host smart-d334fd08-7160-41a6-a565-347c57d008da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200865640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4200865640
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.719356313
Short name T892
Test name
Test status
Simulation time 418511429 ps
CPU time 1.7 seconds
Started May 14 12:50:47 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 218172 kb
Host smart-5c05e85d-b342-4ddf-b1d5-823a90eaa165
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719356
313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.719356313
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.649029036
Short name T218
Test name
Test status
Simulation time 290330904 ps
CPU time 1.38 seconds
Started May 14 12:50:39 PM PDT 24
Finished May 14 12:50:41 PM PDT 24
Peak memory 209032 kb
Host smart-17b74552-4e10-4608-9902-fdfcba079aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649029036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.649029036
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2644760536
Short name T997
Test name
Test status
Simulation time 56777701 ps
CPU time 0.98 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:48 PM PDT 24
Peak memory 209200 kb
Host smart-6231e090-5ce0-40de-b702-96bc2745f851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644760536 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2644760536
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4230421930
Short name T214
Test name
Test status
Simulation time 42031412 ps
CPU time 1.06 seconds
Started May 14 12:50:52 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 209208 kb
Host smart-82ef38d1-7c2c-44a0-90ca-828049b1f100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230421930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.4230421930
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3379838632
Short name T995
Test name
Test status
Simulation time 81090414 ps
CPU time 2.47 seconds
Started May 14 12:50:35 PM PDT 24
Finished May 14 12:50:39 PM PDT 24
Peak memory 217436 kb
Host smart-2a1d596f-5629-428d-9c00-59ffc7d9da56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379838632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3379838632
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3350443176
Short name T879
Test name
Test status
Simulation time 226160908 ps
CPU time 1.16 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:54 PM PDT 24
Peak memory 217556 kb
Host smart-7d08aea7-5706-49c0-a0ec-e8b4f89beb89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350443176 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3350443176
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3273016989
Short name T881
Test name
Test status
Simulation time 22813915 ps
CPU time 0.88 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:50:59 PM PDT 24
Peak memory 209176 kb
Host smart-c785f494-1465-4dc1-9ac5-001be68360a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273016989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3273016989
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3542521908
Short name T900
Test name
Test status
Simulation time 99893661 ps
CPU time 2.79 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 209004 kb
Host smart-8068af29-6c21-4c40-ada9-0dc765fdf33d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542521908 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3542521908
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1686375103
Short name T990
Test name
Test status
Simulation time 1002519639 ps
CPU time 6.84 seconds
Started May 14 12:50:33 PM PDT 24
Finished May 14 12:50:42 PM PDT 24
Peak memory 208864 kb
Host smart-29efa5a1-91a4-4d9d-921a-ea17c5e76039
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686375103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1686375103
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3604413352
Short name T158
Test name
Test status
Simulation time 1613915657 ps
CPU time 15.11 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:51:00 PM PDT 24
Peak memory 208864 kb
Host smart-d2b1d1e9-a6b0-497d-b363-6c2cd4fc5bfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604413352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3604413352
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1094658856
Short name T899
Test name
Test status
Simulation time 63030362 ps
CPU time 2.2 seconds
Started May 14 12:50:44 PM PDT 24
Finished May 14 12:50:48 PM PDT 24
Peak memory 210516 kb
Host smart-87b74f26-b67c-4b4a-8ce2-b64eafa2eb82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094658856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1094658856
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3750300676
Short name T976
Test name
Test status
Simulation time 119549087 ps
CPU time 3.83 seconds
Started May 14 12:50:34 PM PDT 24
Finished May 14 12:50:39 PM PDT 24
Peak memory 218948 kb
Host smart-af62bf54-8d27-481b-b244-f34cc9ff1bd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375030
0676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3750300676
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3995568708
Short name T895
Test name
Test status
Simulation time 404147603 ps
CPU time 1.25 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:43 PM PDT 24
Peak memory 209148 kb
Host smart-0d7c7e19-533f-4acc-ac1c-a928b3e4ef59
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995568708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3995568708
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2215523535
Short name T213
Test name
Test status
Simulation time 18556789 ps
CPU time 1.02 seconds
Started May 14 12:50:47 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 209140 kb
Host smart-81fbb89d-5ed1-44ea-bee4-971c4a428088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215523535 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2215523535
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.72576041
Short name T924
Test name
Test status
Simulation time 37782450 ps
CPU time 1.38 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:02 PM PDT 24
Peak memory 209240 kb
Host smart-b29a869f-fcbd-47c4-91f2-77ccc4e81b41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72576041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_s
ame_csr_outstanding.72576041
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1413466944
Short name T981
Test name
Test status
Simulation time 42927011 ps
CPU time 2.83 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 217484 kb
Host smart-fb878c8f-cb76-41ed-946a-33079a05936c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413466944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1413466944
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.764424611
Short name T137
Test name
Test status
Simulation time 104091108 ps
CPU time 1.65 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:54 PM PDT 24
Peak memory 217628 kb
Host smart-05a756bb-62c5-4677-b13b-3eb28b4f5c8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764424611 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.764424611
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1333167873
Short name T204
Test name
Test status
Simulation time 35420161 ps
CPU time 0.83 seconds
Started May 14 12:50:48 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 209168 kb
Host smart-f60771b7-4981-446c-acfd-35e3dd81863e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333167873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1333167873
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4111496839
Short name T949
Test name
Test status
Simulation time 169994152 ps
CPU time 1.54 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:49 PM PDT 24
Peak memory 209092 kb
Host smart-66993da4-3c71-4481-945d-afd6771f3f47
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111496839 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4111496839
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1562754282
Short name T884
Test name
Test status
Simulation time 4905157891 ps
CPU time 26.17 seconds
Started May 14 12:50:47 PM PDT 24
Finished May 14 12:51:15 PM PDT 24
Peak memory 209280 kb
Host smart-d7467dce-a426-403a-a400-16140614375b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562754282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1562754282
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3645974208
Short name T958
Test name
Test status
Simulation time 808723189 ps
CPU time 7.92 seconds
Started May 14 12:50:57 PM PDT 24
Finished May 14 12:51:07 PM PDT 24
Peak memory 208764 kb
Host smart-bd61c77b-8859-4f86-ad7a-d415bb5834d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645974208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3645974208
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3033201025
Short name T903
Test name
Test status
Simulation time 271617305 ps
CPU time 2.33 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:51:03 PM PDT 24
Peak memory 210572 kb
Host smart-739601a3-226d-49d4-ba51-4b19d82c763d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033201025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3033201025
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3621115356
Short name T922
Test name
Test status
Simulation time 83206688 ps
CPU time 3.02 seconds
Started May 14 12:50:47 PM PDT 24
Finished May 14 12:50:52 PM PDT 24
Peak memory 217984 kb
Host smart-7e53f740-7ea1-415f-b94e-633fc516c701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362111
5356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3621115356
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3492363084
Short name T999
Test name
Test status
Simulation time 88659677 ps
CPU time 1.56 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 209096 kb
Host smart-b0ac0140-ee69-4b4e-a75d-7c8c24b8a2c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492363084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3492363084
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2609613904
Short name T960
Test name
Test status
Simulation time 137134528 ps
CPU time 1.27 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:45 PM PDT 24
Peak memory 211176 kb
Host smart-cd18e6b5-363c-4821-bde0-600cef92457e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609613904 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2609613904
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2747058064
Short name T215
Test name
Test status
Simulation time 36881268 ps
CPU time 1.4 seconds
Started May 14 12:50:40 PM PDT 24
Finished May 14 12:50:43 PM PDT 24
Peak memory 209196 kb
Host smart-585fa822-012c-4f2d-9f00-0af589b3ba16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747058064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2747058064
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2877900654
Short name T126
Test name
Test status
Simulation time 225599175 ps
CPU time 2.02 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:50:47 PM PDT 24
Peak memory 217516 kb
Host smart-b3e2f3c8-2ae2-4fdc-8021-598f89d407e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877900654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2877900654
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.325725810
Short name T907
Test name
Test status
Simulation time 551938836 ps
CPU time 1.46 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 218720 kb
Host smart-cbbb9a10-7c40-4187-abef-347da7fda6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325725810 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.325725810
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2740374549
Short name T207
Test name
Test status
Simulation time 14544297 ps
CPU time 0.87 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:45 PM PDT 24
Peak memory 209208 kb
Host smart-f680c251-052f-41c9-80f3-5f01cec9ef31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740374549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2740374549
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2445986568
Short name T929
Test name
Test status
Simulation time 46138046 ps
CPU time 1.78 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:46 PM PDT 24
Peak memory 209056 kb
Host smart-8da9b0e7-4d6c-4a72-ad96-daafec527c17
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445986568 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2445986568
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.739286486
Short name T157
Test name
Test status
Simulation time 288671322 ps
CPU time 3.28 seconds
Started May 14 12:50:48 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 208892 kb
Host smart-7c6a564c-8a20-4d51-b8cc-58d39b2e5ff1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739286486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.739286486
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3095904357
Short name T945
Test name
Test status
Simulation time 3465491272 ps
CPU time 19.57 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 209276 kb
Host smart-4751b488-f967-4425-867d-879d3c6d8262
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095904357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3095904357
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3307090772
Short name T927
Test name
Test status
Simulation time 109718713 ps
CPU time 2.21 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:24 PM PDT 24
Peak memory 210848 kb
Host smart-9e79174f-bb05-4705-8dce-83aa226739a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307090772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3307090772
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3476214986
Short name T957
Test name
Test status
Simulation time 436896456 ps
CPU time 3.54 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:48 PM PDT 24
Peak memory 217904 kb
Host smart-5b1824f9-d7ce-4ba3-a883-c522ad35c92d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347621
4986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3476214986
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3168751809
Short name T985
Test name
Test status
Simulation time 55797705 ps
CPU time 1.29 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:45 PM PDT 24
Peak memory 209076 kb
Host smart-443cfe77-5423-4e00-8cd9-4ed8ea2e93c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168751809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3168751809
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1194280393
Short name T131
Test name
Test status
Simulation time 75661683 ps
CPU time 1.56 seconds
Started May 14 12:50:47 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 211460 kb
Host smart-cf6a0bd4-bfd2-43c9-88a9-76159160a4ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194280393 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1194280393
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.395871561
Short name T932
Test name
Test status
Simulation time 108486410 ps
CPU time 1.16 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:51:04 PM PDT 24
Peak memory 209184 kb
Host smart-1bf3e2f3-1675-451a-8f5a-7c2a7fadf851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395871561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.395871561
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2822315235
Short name T125
Test name
Test status
Simulation time 176123825 ps
CPU time 1.9 seconds
Started May 14 12:50:43 PM PDT 24
Finished May 14 12:50:47 PM PDT 24
Peak memory 217640 kb
Host smart-c963ae10-fdee-48ff-9ce4-002636b916bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822315235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2822315235
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1617062442
Short name T148
Test name
Test status
Simulation time 309644156 ps
CPU time 4.45 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:47 PM PDT 24
Peak memory 217376 kb
Host smart-ac6ca50c-2901-4320-8cfe-e7876a2c86e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617062442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1617062442
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.992304543
Short name T982
Test name
Test status
Simulation time 90250735 ps
CPU time 1.23 seconds
Started May 14 12:50:39 PM PDT 24
Finished May 14 12:50:42 PM PDT 24
Peak memory 221500 kb
Host smart-ed67641f-3aed-4c0f-a02a-aff631a59b65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992304543 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.992304543
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.48696800
Short name T965
Test name
Test status
Simulation time 52809840 ps
CPU time 1.05 seconds
Started May 14 12:50:40 PM PDT 24
Finished May 14 12:50:42 PM PDT 24
Peak memory 209216 kb
Host smart-537b9330-9996-44b6-b2d8-0d18ac302cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48696800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.48696800
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3022642131
Short name T952
Test name
Test status
Simulation time 78546768 ps
CPU time 1 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:44 PM PDT 24
Peak memory 207648 kb
Host smart-f4cef38f-4fcd-4016-bc36-82a7028884b8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022642131 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3022642131
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2230877825
Short name T878
Test name
Test status
Simulation time 851246364 ps
CPU time 8.16 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 208284 kb
Host smart-9cafeceb-4606-407a-b7c0-fd2561235892
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230877825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2230877825
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.890032859
Short name T994
Test name
Test status
Simulation time 2760053497 ps
CPU time 15.65 seconds
Started May 14 12:50:42 PM PDT 24
Finished May 14 12:50:59 PM PDT 24
Peak memory 209080 kb
Host smart-f445b469-d537-47c5-bb8b-7ef159622020
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890032859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.890032859
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1893543489
Short name T889
Test name
Test status
Simulation time 46257683 ps
CPU time 1.78 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:54 PM PDT 24
Peak memory 210452 kb
Host smart-1bccb03f-74a4-4d17-adb9-117e71afd336
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893543489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1893543489
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4243603574
Short name T908
Test name
Test status
Simulation time 203307992 ps
CPU time 5.95 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:59 PM PDT 24
Peak memory 218844 kb
Host smart-4ebadf36-b857-4a3f-9b13-93c11878dddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424360
3574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4243603574
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2464855844
Short name T155
Test name
Test status
Simulation time 101477031 ps
CPU time 1.49 seconds
Started May 14 12:50:45 PM PDT 24
Finished May 14 12:50:48 PM PDT 24
Peak memory 209112 kb
Host smart-9da176d5-a3a2-44c0-b657-ee05285eca26
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464855844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2464855844
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.524657053
Short name T216
Test name
Test status
Simulation time 28194871 ps
CPU time 0.95 seconds
Started May 14 12:50:41 PM PDT 24
Finished May 14 12:50:43 PM PDT 24
Peak memory 208640 kb
Host smart-5653bbbb-fa06-49bd-b74d-42aab2905a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524657053 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.524657053
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2907631706
Short name T992
Test name
Test status
Simulation time 50194133 ps
CPU time 1.12 seconds
Started May 14 12:50:49 PM PDT 24
Finished May 14 12:50:51 PM PDT 24
Peak memory 209212 kb
Host smart-c78b2680-4ecf-426a-9a46-48745f660d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907631706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2907631706
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.231957361
Short name T950
Test name
Test status
Simulation time 623413623 ps
CPU time 3.96 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:51:06 PM PDT 24
Peak memory 217560 kb
Host smart-cf20f5b5-782a-4655-825f-fea0c822b0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231957361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.231957361
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.43852902
Short name T149
Test name
Test status
Simulation time 353168334 ps
CPU time 3.44 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:51:01 PM PDT 24
Peak memory 222136 kb
Host smart-a27c3055-25a1-4c33-98c0-3120c5d6c9db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43852902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_er
r.43852902
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2729675850
Short name T454
Test name
Test status
Simulation time 2547229525 ps
CPU time 14.56 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:26 PM PDT 24
Peak memory 218040 kb
Host smart-83f10c71-1355-42ba-83b5-d6e1a70efd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729675850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2729675850
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.673096253
Short name T490
Test name
Test status
Simulation time 198156640 ps
CPU time 3.05 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 209456 kb
Host smart-879aa008-1592-46c9-8dd7-7e2ed79b7d7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673096253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.673096253
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.83458510
Short name T437
Test name
Test status
Simulation time 3100984060 ps
CPU time 5.93 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:28 PM PDT 24
Peak memory 217344 kb
Host smart-dae2643d-151a-4f17-9626-e5c30138cc0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83458510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.83458510
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3248649578
Short name T573
Test name
Test status
Simulation time 359834283 ps
CPU time 7.01 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:28 PM PDT 24
Peak memory 217840 kb
Host smart-3eec1e90-91db-451c-a874-19fefb845c1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248649578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3248649578
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3310248107
Short name T408
Test name
Test status
Simulation time 1911388552 ps
CPU time 17.6 seconds
Started May 14 12:52:22 PM PDT 24
Finished May 14 12:52:42 PM PDT 24
Peak memory 213200 kb
Host smart-6585d75d-6a68-422f-981a-69f966c41fc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310248107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3310248107
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.631806693
Short name T87
Test name
Test status
Simulation time 247906285 ps
CPU time 2.45 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:24 PM PDT 24
Peak memory 212988 kb
Host smart-293b91ae-c9f3-4608-bdee-78dd99dac048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631806693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.631806693
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1177432523
Short name T184
Test name
Test status
Simulation time 8606028297 ps
CPU time 46.37 seconds
Started May 14 12:52:21 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 269892 kb
Host smart-14465264-4398-457e-8479-dca5f64a8d12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177432523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1177432523
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.443773105
Short name T820
Test name
Test status
Simulation time 612167540 ps
CPU time 8.73 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:31 PM PDT 24
Peak memory 247176 kb
Host smart-5fb1390c-8523-454f-83cf-cf74bd8d9ac1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443773105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.443773105
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2777816630
Short name T554
Test name
Test status
Simulation time 84401555 ps
CPU time 2.25 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 221812 kb
Host smart-ca49eea9-a07d-46e6-8d34-4b84d218dd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777816630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2777816630
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.745480741
Short name T324
Test name
Test status
Simulation time 331765625 ps
CPU time 22.04 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:44 PM PDT 24
Peak memory 214612 kb
Host smart-682ea370-108f-459c-a543-0009e05e8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745480741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.745480741
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1404817953
Short name T54
Test name
Test status
Simulation time 272527874 ps
CPU time 25.64 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:52:46 PM PDT 24
Peak memory 282184 kb
Host smart-57f6ac69-8c0e-4f66-acaf-b2b7b304a637
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404817953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1404817953
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3373781080
Short name T364
Test name
Test status
Simulation time 1981394591 ps
CPU time 13.82 seconds
Started May 14 12:52:20 PM PDT 24
Finished May 14 12:52:37 PM PDT 24
Peak memory 218600 kb
Host smart-8e80cdf1-87e1-4382-a592-d54ba5efe453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373781080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3373781080
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.665965884
Short name T763
Test name
Test status
Simulation time 300919406 ps
CPU time 11.81 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 217952 kb
Host smart-e4be73ea-ed07-4b79-920f-83e13f2937d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665965884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.665965884
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1412949290
Short name T60
Test name
Test status
Simulation time 447618243 ps
CPU time 16.22 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:52:36 PM PDT 24
Peak memory 217932 kb
Host smart-5e66011f-744b-4d52-88f0-32cbf52cc190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412949290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
412949290
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1541347387
Short name T51
Test name
Test status
Simulation time 1929270370 ps
CPU time 11.8 seconds
Started May 14 12:52:20 PM PDT 24
Finished May 14 12:52:35 PM PDT 24
Peak memory 225092 kb
Host smart-236cffe5-8565-4fa3-a6b4-84aeca0e48ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541347387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1541347387
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.312654803
Short name T645
Test name
Test status
Simulation time 67410994 ps
CPU time 2.35 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 217804 kb
Host smart-3e78f8d2-31e7-402c-a8ec-f9933c4b5c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312654803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.312654803
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.128986190
Short name T840
Test name
Test status
Simulation time 200046182 ps
CPU time 22.86 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 250992 kb
Host smart-11985c87-fbfe-4bf4-90ef-e5b3cad83522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128986190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.128986190
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.978174488
Short name T360
Test name
Test status
Simulation time 101074565 ps
CPU time 7.9 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:18 PM PDT 24
Peak memory 251052 kb
Host smart-82a0d405-7fe5-43d5-b9f6-48ecefec2853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978174488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.978174488
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.166427701
Short name T826
Test name
Test status
Simulation time 88671254784 ps
CPU time 724.96 seconds
Started May 14 12:52:16 PM PDT 24
Finished May 14 01:04:23 PM PDT 24
Peak memory 269148 kb
Host smart-6d04c425-eb89-4dd7-b11c-a7aa24fb2cb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166427701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.166427701
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.925851978
Short name T161
Test name
Test status
Simulation time 99883099847 ps
CPU time 2228.96 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 01:29:31 PM PDT 24
Peak memory 938468 kb
Host smart-9a88ea9b-55df-4920-8868-c0bf56ca7e0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=925851978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.925851978
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.976861440
Short name T564
Test name
Test status
Simulation time 34860456 ps
CPU time 1.34 seconds
Started May 14 12:52:11 PM PDT 24
Finished May 14 12:52:15 PM PDT 24
Peak memory 212624 kb
Host smart-9b3b81dc-79dd-457f-a4cb-fa59f865d6b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976861440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.976861440
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.152516479
Short name T110
Test name
Test status
Simulation time 16424867 ps
CPU time 1.14 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 209624 kb
Host smart-64b6a86c-9ced-42c6-9af0-8ebc2d242e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152516479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.152516479
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.47884086
Short name T407
Test name
Test status
Simulation time 1045082445 ps
CPU time 11.8 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 218004 kb
Host smart-bb12173e-cdc5-480a-bc5e-d1914b855d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47884086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.47884086
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3112233020
Short name T199
Test name
Test status
Simulation time 384978792 ps
CPU time 10.52 seconds
Started May 14 12:52:21 PM PDT 24
Finished May 14 12:52:34 PM PDT 24
Peak memory 217004 kb
Host smart-13b57454-d9d3-480e-ae31-8d80bc18dc3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112233020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3112233020
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1422678422
Short name T734
Test name
Test status
Simulation time 6301790617 ps
CPU time 27.9 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 218544 kb
Host smart-3b111f4e-35cd-4332-993c-c8eb19aea343
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422678422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1422678422
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2203908193
Short name T783
Test name
Test status
Simulation time 222871635 ps
CPU time 6.33 seconds
Started May 14 12:52:20 PM PDT 24
Finished May 14 12:52:29 PM PDT 24
Peak memory 217644 kb
Host smart-a7e1404c-33f3-4f14-889a-a2c427a32363
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203908193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
203908193
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3281069853
Short name T462
Test name
Test status
Simulation time 268061087 ps
CPU time 7.8 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:30 PM PDT 24
Peak memory 217900 kb
Host smart-40532750-806c-4550-8a44-6d8d94f033dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281069853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3281069853
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1424515233
Short name T389
Test name
Test status
Simulation time 2173902898 ps
CPU time 13.39 seconds
Started May 14 12:52:22 PM PDT 24
Finished May 14 12:52:38 PM PDT 24
Peak memory 213160 kb
Host smart-09c91da0-9058-412b-9f80-d21346ab897b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424515233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1424515233
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2732787362
Short name T834
Test name
Test status
Simulation time 2804872557 ps
CPU time 15.45 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:37 PM PDT 24
Peak memory 213772 kb
Host smart-efae9e68-c600-427e-bffa-10a83cd31217
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732787362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2732787362
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.889192314
Short name T549
Test name
Test status
Simulation time 3598829996 ps
CPU time 116.02 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:54:16 PM PDT 24
Peak memory 283580 kb
Host smart-196f6027-d045-4c15-8f0c-d69e47c48d2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889192314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.889192314
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1694310671
Short name T464
Test name
Test status
Simulation time 439515815 ps
CPU time 10.74 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:32 PM PDT 24
Peak memory 250940 kb
Host smart-8c6e8844-2b1c-48fd-b2b4-6367f72106f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694310671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1694310671
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.765034567
Short name T778
Test name
Test status
Simulation time 178337935 ps
CPU time 7.26 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:52:28 PM PDT 24
Peak memory 222180 kb
Host smart-7abf4f08-4589-4583-86bf-df0fe41786dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765034567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.765034567
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.641894771
Short name T109
Test name
Test status
Simulation time 1781144221 ps
CPU time 9.67 seconds
Started May 14 12:52:16 PM PDT 24
Finished May 14 12:52:29 PM PDT 24
Peak memory 213956 kb
Host smart-bf810d84-6be7-431f-93b7-46ee8318e8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641894771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.641894771
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3524727435
Short name T428
Test name
Test status
Simulation time 2113214286 ps
CPU time 14.85 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:52:35 PM PDT 24
Peak memory 218428 kb
Host smart-752d811b-10e1-40c7-91c8-92c140db78cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524727435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3524727435
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1219861502
Short name T388
Test name
Test status
Simulation time 1084863627 ps
CPU time 9.3 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:31 PM PDT 24
Peak memory 217900 kb
Host smart-7a08239b-f0fa-4ca1-a197-c5130282d1dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219861502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1219861502
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3222628139
Short name T410
Test name
Test status
Simulation time 772761121 ps
CPU time 8.3 seconds
Started May 14 12:52:22 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 217940 kb
Host smart-a801abc0-159c-4a81-9edd-3f00e1b69812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222628139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
222628139
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3703558813
Short name T463
Test name
Test status
Simulation time 332722187 ps
CPU time 8.75 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:31 PM PDT 24
Peak memory 224172 kb
Host smart-1e695fd4-1369-497b-9d1b-4adbcecc738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703558813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3703558813
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2848623753
Short name T61
Test name
Test status
Simulation time 56922752 ps
CPU time 3.11 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 214324 kb
Host smart-c6ec6f98-1d8d-4182-b2c6-4a04f7ec7675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848623753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2848623753
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3386415590
Short name T338
Test name
Test status
Simulation time 387642710 ps
CPU time 22.94 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:46 PM PDT 24
Peak memory 250796 kb
Host smart-993cf8d5-bae8-4f51-abf7-e7e6e13972e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386415590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3386415590
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4171532737
Short name T688
Test name
Test status
Simulation time 178580622 ps
CPU time 6.14 seconds
Started May 14 12:52:16 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 246592 kb
Host smart-e6bc80cf-7097-4904-b1d1-e0c8f3bbc570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171532737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4171532737
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3833082429
Short name T434
Test name
Test status
Simulation time 16972733369 ps
CPU time 66.06 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:53:28 PM PDT 24
Peak memory 277688 kb
Host smart-a0095bf6-5fe3-4950-a363-17864a0bf50a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833082429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3833082429
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1335757909
Short name T715
Test name
Test status
Simulation time 29428879 ps
CPU time 1 seconds
Started May 14 12:52:21 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 212632 kb
Host smart-27b05fe8-7ebb-4910-be41-d9eea713ee90
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335757909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1335757909
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.555520619
Short name T252
Test name
Test status
Simulation time 17006880 ps
CPU time 1.13 seconds
Started May 14 12:52:50 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 209552 kb
Host smart-0ac187d0-18be-4458-8f52-bd24ce2fc8b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555520619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.555520619
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1420420610
Short name T509
Test name
Test status
Simulation time 308390623 ps
CPU time 12.6 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:53:07 PM PDT 24
Peak memory 218000 kb
Host smart-2c03cd40-e112-41c1-ad9e-8e61cfb690be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420420610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1420420610
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.909295839
Short name T717
Test name
Test status
Simulation time 177660270 ps
CPU time 1.13 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 209652 kb
Host smart-1a165083-1fd0-428b-a50b-4adda4384ee1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909295839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.909295839
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.243163491
Short name T354
Test name
Test status
Simulation time 1340175176 ps
CPU time 23.56 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 217852 kb
Host smart-97d87675-ffd1-4001-a760-672e12d49262
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243163491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.243163491
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.375969955
Short name T362
Test name
Test status
Simulation time 1293222563 ps
CPU time 10.57 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 217908 kb
Host smart-5860febb-5272-4e7d-b5d1-477fb4f560b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375969955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.375969955
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1106036489
Short name T16
Test name
Test status
Simulation time 246456766 ps
CPU time 1.45 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:01 PM PDT 24
Peak memory 212564 kb
Host smart-46a23dfe-dbdd-4944-857e-f817b5a2437f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106036489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1106036489
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2480891011
Short name T711
Test name
Test status
Simulation time 1735093487 ps
CPU time 42.81 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 250948 kb
Host smart-1f76da36-55eb-4bdf-b78f-1ccc4e8ea397
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480891011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2480891011
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4259765859
Short name T340
Test name
Test status
Simulation time 318954768 ps
CPU time 6.31 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 222588 kb
Host smart-852e7e1b-c4d3-4892-ba17-60ed8379701e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259765859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.4259765859
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1128555568
Short name T608
Test name
Test status
Simulation time 87163548 ps
CPU time 4.06 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 221680 kb
Host smart-982f1c38-39e2-487a-9562-25907fd4c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128555568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1128555568
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1580113574
Short name T348
Test name
Test status
Simulation time 797433990 ps
CPU time 9.41 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 218044 kb
Host smart-25ce0889-c5ee-4fd5-8e38-23b8e926273c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580113574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1580113574
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.618570587
Short name T619
Test name
Test status
Simulation time 2301947967 ps
CPU time 14.08 seconds
Started May 14 12:53:03 PM PDT 24
Finished May 14 12:53:20 PM PDT 24
Peak memory 218064 kb
Host smart-b00ecd81-ea4b-49e5-98f9-2b830ebef9a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618570587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.618570587
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.63588096
Short name T491
Test name
Test status
Simulation time 595859395 ps
CPU time 9.4 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 217976 kb
Host smart-e6ddc20e-7a6f-42a1-ad14-eadfde9f2875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63588096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.63588096
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1759734191
Short name T347
Test name
Test status
Simulation time 895127957 ps
CPU time 10 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 225336 kb
Host smart-eb491880-8264-49dd-933b-86be225d4a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759734191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1759734191
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.900186738
Short name T176
Test name
Test status
Simulation time 326954796 ps
CPU time 2.92 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 214560 kb
Host smart-b599951f-9177-4b79-9574-5e9b79623727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900186738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.900186738
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1373236744
Short name T568
Test name
Test status
Simulation time 190835476 ps
CPU time 17.24 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 250960 kb
Host smart-ec83b9e3-59da-4197-884b-113a425ccdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373236744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1373236744
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1518150423
Short name T229
Test name
Test status
Simulation time 296033623 ps
CPU time 3.6 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:53:01 PM PDT 24
Peak memory 222960 kb
Host smart-14fe3cae-d08d-4fb4-9d0c-4e8bc0c7891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518150423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1518150423
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2177916883
Short name T656
Test name
Test status
Simulation time 65076823098 ps
CPU time 319.07 seconds
Started May 14 12:52:51 PM PDT 24
Finished May 14 12:58:14 PM PDT 24
Peak memory 300256 kb
Host smart-201f4530-eeb2-445d-9a07-fc887e64d1f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2177916883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2177916883
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3583070586
Short name T846
Test name
Test status
Simulation time 47163508 ps
CPU time 0.98 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:00 PM PDT 24
Peak memory 211580 kb
Host smart-76564fcf-eee0-4cbd-b7ea-6fdb7e47d7cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583070586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3583070586
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.174277521
Short name T786
Test name
Test status
Simulation time 17356369 ps
CPU time 1.18 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:00 PM PDT 24
Peak memory 209548 kb
Host smart-c60fb268-27ad-4092-b4a2-866859b0143b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174277521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.174277521
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.57126788
Short name T759
Test name
Test status
Simulation time 2257073947 ps
CPU time 12.21 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:12 PM PDT 24
Peak memory 217892 kb
Host smart-d8d142c3-4d86-410e-a363-d07b6031603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57126788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.57126788
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1816452649
Short name T795
Test name
Test status
Simulation time 519053188 ps
CPU time 5.51 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:53:01 PM PDT 24
Peak memory 209580 kb
Host smart-c52dc094-54ff-4959-a1dd-9797b7cc23b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816452649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1816452649
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2755314846
Short name T233
Test name
Test status
Simulation time 4171967473 ps
CPU time 30.12 seconds
Started May 14 12:52:51 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 218252 kb
Host smart-acf751fa-b0f2-461c-ab43-811381ea5a38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755314846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2755314846
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1865755076
Short name T293
Test name
Test status
Simulation time 2174812592 ps
CPU time 9.41 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 217952 kb
Host smart-0ed87a0b-f655-4f1f-ad40-2d05c5ba5a4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865755076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1865755076
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.552317618
Short name T758
Test name
Test status
Simulation time 2094248635 ps
CPU time 5.29 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:53:00 PM PDT 24
Peak memory 213184 kb
Host smart-86f0cbf3-1cad-428a-b66f-58871ba6ea9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552317618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
552317618
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3292593565
Short name T281
Test name
Test status
Simulation time 4754333698 ps
CPU time 55.7 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:56 PM PDT 24
Peak memory 252176 kb
Host smart-19d8f432-c581-4986-b71b-22774c67d6e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292593565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3292593565
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.839185361
Short name T514
Test name
Test status
Simulation time 2125594552 ps
CPU time 8.41 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 223936 kb
Host smart-1f89b1da-a15e-4811-9c79-eb246e416f27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839185361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.839185361
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2575320893
Short name T794
Test name
Test status
Simulation time 502424472 ps
CPU time 3.55 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:06 PM PDT 24
Peak memory 222180 kb
Host smart-a53de57e-373f-481c-a32e-626dbe6bd53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575320893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2575320893
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4088216653
Short name T325
Test name
Test status
Simulation time 311977336 ps
CPU time 9.41 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 218120 kb
Host smart-0b84b24b-d371-40dc-8229-26f7c1120e37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088216653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4088216653
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2594734332
Short name T393
Test name
Test status
Simulation time 1145266806 ps
CPU time 10.08 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 218000 kb
Host smart-390167a6-a38e-446d-ac78-9fda5661b950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594734332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2594734332
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.343004719
Short name T371
Test name
Test status
Simulation time 1046678274 ps
CPU time 9.76 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 217816 kb
Host smart-444ec1ab-acf4-40da-b422-b8e49ed47874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343004719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.343004719
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2324898545
Short name T81
Test name
Test status
Simulation time 77837259 ps
CPU time 2.83 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 214184 kb
Host smart-91dac736-6fb0-42fe-abb8-ecd2ada45117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324898545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2324898545
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2783728100
Short name T699
Test name
Test status
Simulation time 1636246632 ps
CPU time 19.05 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:53:15 PM PDT 24
Peak memory 248772 kb
Host smart-89117b3a-d2de-494f-9902-eb9aba6d22ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783728100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2783728100
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3737721329
Short name T598
Test name
Test status
Simulation time 117196052 ps
CPU time 8.66 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 250624 kb
Host smart-8bd7e518-1245-41a1-865f-c3f58b6fa22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737721329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3737721329
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.104790598
Short name T336
Test name
Test status
Simulation time 62913974872 ps
CPU time 193.63 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:56:17 PM PDT 24
Peak memory 267496 kb
Host smart-dd05d391-e2af-4ed9-baea-0e1a33b44fee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104790598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.104790598
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3453255558
Short name T68
Test name
Test status
Simulation time 40580436 ps
CPU time 0.96 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 211608 kb
Host smart-0c74753c-3898-4f9d-9592-82d443b64d96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453255558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3453255558
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.150283780
Short name T613
Test name
Test status
Simulation time 24057404 ps
CPU time 0.97 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:52:58 PM PDT 24
Peak memory 209588 kb
Host smart-6be68894-1759-48a2-a6a8-26a80f78967d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150283780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.150283780
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2524346102
Short name T616
Test name
Test status
Simulation time 1837921633 ps
CPU time 10.34 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 217968 kb
Host smart-60d7dfc9-0035-478d-a670-f5674eb8c747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524346102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2524346102
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2887129057
Short name T703
Test name
Test status
Simulation time 999518459 ps
CPU time 6.03 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 209572 kb
Host smart-8be9d523-3f3f-4842-94fd-f0d71f7b32fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887129057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2887129057
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.898698996
Short name T346
Test name
Test status
Simulation time 2071621517 ps
CPU time 32.97 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 217976 kb
Host smart-a9b7d364-b355-4220-ade4-2244cf4993f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898698996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.898698996
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3754978056
Short name T235
Test name
Test status
Simulation time 509885939 ps
CPU time 3.42 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 217840 kb
Host smart-eda4f71d-1f7e-4754-baf8-46091936a355
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754978056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3754978056
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3325826766
Short name T476
Test name
Test status
Simulation time 338409688 ps
CPU time 2.42 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 212804 kb
Host smart-806e80d3-da71-4412-9cf8-09c8eae2eac6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325826766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3325826766
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.236159547
Short name T642
Test name
Test status
Simulation time 1878760319 ps
CPU time 45.01 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 273144 kb
Host smart-df7397dd-7878-4e52-bdc0-85606d3d9076
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236159547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.236159547
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4118488584
Short name T589
Test name
Test status
Simulation time 7324827377 ps
CPU time 17.05 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 250576 kb
Host smart-4c579fcc-1cf0-4952-a221-c71674165ae7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118488584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4118488584
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3172619652
Short name T807
Test name
Test status
Simulation time 78244884 ps
CPU time 1.76 seconds
Started May 14 12:52:58 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 221540 kb
Host smart-935d549d-9b5a-4dc7-9b5e-cced047844b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172619652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3172619652
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.524367214
Short name T630
Test name
Test status
Simulation time 630365935 ps
CPU time 10.61 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:16 PM PDT 24
Peak memory 218932 kb
Host smart-c4255b2c-fe58-40d1-b30d-b3b6c2322bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524367214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.524367214
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1582637639
Short name T106
Test name
Test status
Simulation time 261886019 ps
CPU time 9.56 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 217960 kb
Host smart-808b7523-def4-4263-9f5e-6fc766da9ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582637639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1582637639
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1177487046
Short name T396
Test name
Test status
Simulation time 2732708196 ps
CPU time 9.69 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 218152 kb
Host smart-42c552a8-2c44-4b8f-9320-30658694dd76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177487046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1177487046
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2461602846
Short name T105
Test name
Test status
Simulation time 513655454 ps
CPU time 14.44 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:13 PM PDT 24
Peak memory 225284 kb
Host smart-9446a317-be61-4c16-97dd-475f9e1df1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461602846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2461602846
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2206180818
Short name T317
Test name
Test status
Simulation time 33860470 ps
CPU time 1.45 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 213424 kb
Host smart-e50259f1-0679-43c7-b198-766dfb25aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206180818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2206180818
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.573833540
Short name T327
Test name
Test status
Simulation time 884400727 ps
CPU time 12.83 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 250908 kb
Host smart-69aa16d2-2440-4c6c-ac25-cee44ef3f9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573833540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.573833540
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.608929766
Short name T658
Test name
Test status
Simulation time 259621305 ps
CPU time 7 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 250976 kb
Host smart-f1ab4e7e-1056-45ad-912b-ddcac7ac3928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608929766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.608929766
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1059460886
Short name T397
Test name
Test status
Simulation time 68649545254 ps
CPU time 324.06 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:58:29 PM PDT 24
Peak memory 267484 kb
Host smart-7a6bd8aa-2a7a-4a15-90e5-91213814bcba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059460886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1059460886
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1919612580
Short name T66
Test name
Test status
Simulation time 14502449 ps
CPU time 0.92 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:01 PM PDT 24
Peak memory 211540 kb
Host smart-3de382ef-8987-47bc-95c6-f38cfb54e601
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919612580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1919612580
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2160930198
Short name T555
Test name
Test status
Simulation time 58430041 ps
CPU time 1 seconds
Started May 14 12:53:06 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 209592 kb
Host smart-2e499522-3486-432b-97c1-9540b5c3c8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160930198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2160930198
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3106581451
Short name T537
Test name
Test status
Simulation time 878398927 ps
CPU time 8.69 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:21 PM PDT 24
Peak memory 217908 kb
Host smart-5771dc19-a717-4ada-bde6-8bce3e870c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106581451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3106581451
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.170989028
Short name T419
Test name
Test status
Simulation time 1102409961 ps
CPU time 18.76 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:22 PM PDT 24
Peak memory 209556 kb
Host smart-4f71186f-0359-495f-a71d-849d817a215a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170989028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.170989028
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.46869687
Short name T18
Test name
Test status
Simulation time 5544612918 ps
CPU time 75.39 seconds
Started May 14 12:53:06 PM PDT 24
Finished May 14 12:54:24 PM PDT 24
Peak memory 219916 kb
Host smart-ae4e4970-9f92-4cba-9371-53b91d1e4e73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46869687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_err
ors.46869687
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.744949568
Short name T370
Test name
Test status
Simulation time 726729147 ps
CPU time 10.89 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 217964 kb
Host smart-da439e40-79cf-44a7-a99a-5ca3b8b564fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744949568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.744949568
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1550465964
Short name T633
Test name
Test status
Simulation time 1963368901 ps
CPU time 6.41 seconds
Started May 14 12:53:05 PM PDT 24
Finished May 14 12:53:14 PM PDT 24
Peak memory 213636 kb
Host smart-8dfe9fad-5017-4b52-9fc3-10e5527ce379
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550465964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1550465964
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1085051774
Short name T813
Test name
Test status
Simulation time 870706891 ps
CPU time 26.43 seconds
Started May 14 12:53:06 PM PDT 24
Finished May 14 12:53:35 PM PDT 24
Peak memory 250888 kb
Host smart-eb511e9d-41a8-4c54-8d1c-5dc7d7004c18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085051774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1085051774
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4258097311
Short name T651
Test name
Test status
Simulation time 1267436989 ps
CPU time 9.93 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 221904 kb
Host smart-8a38012d-eecd-4604-afd0-0e603c8285f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258097311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.4258097311
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1509459771
Short name T863
Test name
Test status
Simulation time 350842715 ps
CPU time 2.41 seconds
Started May 14 12:53:03 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 221720 kb
Host smart-e1d9fd6a-1b79-4d90-8787-cdb630a90935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509459771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1509459771
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3589916750
Short name T808
Test name
Test status
Simulation time 508742933 ps
CPU time 13.82 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:27 PM PDT 24
Peak memory 219228 kb
Host smart-b3723195-b907-4dfd-9c45-241a816ec24f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589916750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3589916750
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2355387877
Short name T504
Test name
Test status
Simulation time 4155648796 ps
CPU time 11.51 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 218028 kb
Host smart-7d06a687-f2da-478d-9a50-4685928f7f2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355387877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2355387877
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1928978858
Short name T618
Test name
Test status
Simulation time 402997476 ps
CPU time 7.14 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 217956 kb
Host smart-550c19dc-9da9-47b4-9981-69eebc1015d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928978858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1928978858
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3351306901
Short name T592
Test name
Test status
Simulation time 289940510 ps
CPU time 11.95 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 225392 kb
Host smart-132fb5b6-dc62-4371-be16-69c677a15d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351306901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3351306901
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1833793179
Short name T682
Test name
Test status
Simulation time 40756402 ps
CPU time 1.53 seconds
Started May 14 12:53:00 PM PDT 24
Finished May 14 12:53:06 PM PDT 24
Peak memory 217860 kb
Host smart-0be15d05-a923-4155-99cb-793add0b4385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833793179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1833793179
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.482297844
Short name T661
Test name
Test status
Simulation time 1342214187 ps
CPU time 27.18 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:29 PM PDT 24
Peak memory 251036 kb
Host smart-6c996c6b-da88-4988-9568-4de67a178b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482297844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.482297844
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3857965263
Short name T328
Test name
Test status
Simulation time 183016558 ps
CPU time 6.31 seconds
Started May 14 12:53:00 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 250540 kb
Host smart-b009bd07-392e-4549-8a4e-b3eb3bceaa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857965263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3857965263
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3451454787
Short name T457
Test name
Test status
Simulation time 8163902876 ps
CPU time 81.56 seconds
Started May 14 12:53:06 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 250960 kb
Host smart-74159695-2335-4d86-be0d-8e1eafedb2c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451454787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3451454787
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1838324446
Short name T667
Test name
Test status
Simulation time 81208415 ps
CPU time 0.79 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 208808 kb
Host smart-20fe9ca5-ba2f-4bcd-a46c-562a93e532f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838324446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1838324446
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.630819225
Short name T594
Test name
Test status
Simulation time 37169237 ps
CPU time 0.91 seconds
Started May 14 12:53:01 PM PDT 24
Finished May 14 12:53:06 PM PDT 24
Peak memory 209624 kb
Host smart-fcc8b30f-cfa8-4b87-a41c-321bf6d7908e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630819225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.630819225
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2127610597
Short name T739
Test name
Test status
Simulation time 445482276 ps
CPU time 13.98 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 217988 kb
Host smart-4ce420af-28e2-4cee-92a3-2d91ed1854eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127610597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2127610597
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3187977600
Short name T545
Test name
Test status
Simulation time 475089255 ps
CPU time 12.02 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 209624 kb
Host smart-9ccb0e34-57c0-41c1-8a9d-671187fd58aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187977600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3187977600
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1535776008
Short name T649
Test name
Test status
Simulation time 2496051892 ps
CPU time 40.33 seconds
Started May 14 12:53:01 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 218920 kb
Host smart-dfec5965-db40-44d5-908f-78043a4e845d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535776008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1535776008
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1867776390
Short name T253
Test name
Test status
Simulation time 145893565 ps
CPU time 2.35 seconds
Started May 14 12:53:05 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 217852 kb
Host smart-4230f0e8-f398-44d0-a6fc-7a5e690b1bcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867776390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1867776390
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1091551957
Short name T107
Test name
Test status
Simulation time 148212688 ps
CPU time 2.73 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:53:12 PM PDT 24
Peak memory 213092 kb
Host smart-fb39b0fb-6573-43b1-bc74-32fee204dcbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091551957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1091551957
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1031751964
Short name T102
Test name
Test status
Simulation time 10620704989 ps
CPU time 58.18 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 270568 kb
Host smart-f6ea2030-81a0-4bcb-88f1-00043c75d6e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031751964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1031751964
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4126853498
Short name T849
Test name
Test status
Simulation time 4528548163 ps
CPU time 14.85 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 226348 kb
Host smart-2e7471b2-3872-48dd-9d47-06e3125c7140
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126853498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4126853498
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3296899102
Short name T456
Test name
Test status
Simulation time 73968489 ps
CPU time 3.73 seconds
Started May 14 12:53:03 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 221728 kb
Host smart-9a04c78e-4b54-4fb9-801f-8741d3736223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296899102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3296899102
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2715804253
Short name T861
Test name
Test status
Simulation time 560757666 ps
CPU time 18.78 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:25 PM PDT 24
Peak memory 218944 kb
Host smart-61543655-c794-49d3-a4b1-5cca041efe49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715804253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2715804253
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3183732615
Short name T752
Test name
Test status
Simulation time 480464201 ps
CPU time 12.06 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 218004 kb
Host smart-7fef4076-56f5-45ca-ba26-81950cee8a50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183732615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3183732615
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1542820828
Short name T433
Test name
Test status
Simulation time 1015779636 ps
CPU time 9.93 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:25 PM PDT 24
Peak memory 217868 kb
Host smart-5341f238-9485-48c8-949d-bcb0b0628e11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542820828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1542820828
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2745168262
Short name T604
Test name
Test status
Simulation time 848682621 ps
CPU time 14.74 seconds
Started May 14 12:53:05 PM PDT 24
Finished May 14 12:53:22 PM PDT 24
Peak memory 226180 kb
Host smart-7fe9108b-d0b1-4ec9-8a0c-e1306c87aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745168262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2745168262
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.439827869
Short name T597
Test name
Test status
Simulation time 192706047 ps
CPU time 3.17 seconds
Started May 14 12:53:04 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 217696 kb
Host smart-b16935fe-e60c-4dc2-bce3-b23776182eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439827869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.439827869
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1195362456
Short name T744
Test name
Test status
Simulation time 207986927 ps
CPU time 22.47 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 245904 kb
Host smart-a845ca2a-f2e7-4fde-8c68-2f83e9954d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195362456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1195362456
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3152770812
Short name T796
Test name
Test status
Simulation time 62415040 ps
CPU time 6.49 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 246180 kb
Host smart-c9412831-d584-44c6-91f5-fcaa002a5544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152770812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3152770812
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2459296781
Short name T448
Test name
Test status
Simulation time 5606832227 ps
CPU time 60.1 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 251080 kb
Host smart-6066f461-095d-4aec-9f44-27438bdd6053
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459296781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2459296781
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1832636094
Short name T767
Test name
Test status
Simulation time 26579604 ps
CPU time 0.78 seconds
Started May 14 12:53:03 PM PDT 24
Finished May 14 12:53:07 PM PDT 24
Peak memory 208508 kb
Host smart-f23f95f5-db73-424f-ad0e-453dc0bfe9cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832636094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1832636094
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2003265747
Short name T372
Test name
Test status
Simulation time 16793020 ps
CPU time 0.94 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:15 PM PDT 24
Peak memory 209532 kb
Host smart-fc5dd617-d47c-40a4-8ed4-25c8eaab21b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003265747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2003265747
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4115127480
Short name T245
Test name
Test status
Simulation time 3853548962 ps
CPU time 12.08 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 218232 kb
Host smart-98651cd0-811d-41c0-9337-fbdb747e906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115127480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4115127480
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2983017055
Short name T423
Test name
Test status
Simulation time 828606215 ps
CPU time 2.49 seconds
Started May 14 12:53:01 PM PDT 24
Finished May 14 12:53:07 PM PDT 24
Peak memory 209536 kb
Host smart-a4fd3d71-c3ac-41ca-99e6-5d835e98f7c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983017055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2983017055
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3836361198
Short name T527
Test name
Test status
Simulation time 7300609853 ps
CPU time 29.24 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 218364 kb
Host smart-2eece0ab-9a40-4511-ab60-07a6bd7979e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836361198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3836361198
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.811077493
Short name T676
Test name
Test status
Simulation time 554004317 ps
CPU time 3.29 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 213316 kb
Host smart-a1973adb-632e-4538-9585-84e21e04c2e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811077493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
811077493
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.319946652
Short name T638
Test name
Test status
Simulation time 1330818039 ps
CPU time 43.21 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:49 PM PDT 24
Peak memory 250804 kb
Host smart-a3f6e665-d87c-4e26-9489-827649273532
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319946652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.319946652
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.889132675
Short name T799
Test name
Test status
Simulation time 2279349039 ps
CPU time 16.83 seconds
Started May 14 12:53:00 PM PDT 24
Finished May 14 12:53:21 PM PDT 24
Peak memory 244192 kb
Host smart-5b36e3f2-4f28-4323-b0a4-22ab07af1d4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889132675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.889132675
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1391293073
Short name T113
Test name
Test status
Simulation time 254165859 ps
CPU time 3.84 seconds
Started May 14 12:53:04 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 222036 kb
Host smart-21481f73-fa45-4c21-b9fa-bc57188eabba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391293073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1391293073
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.794356248
Short name T710
Test name
Test status
Simulation time 1343126336 ps
CPU time 12.97 seconds
Started May 14 12:53:12 PM PDT 24
Finished May 14 12:53:32 PM PDT 24
Peak memory 225648 kb
Host smart-da69d53e-4b75-4137-975d-0c15cd703867
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794356248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.794356248
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.503292843
Short name T816
Test name
Test status
Simulation time 526881624 ps
CPU time 9.92 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 217980 kb
Host smart-6faad8a5-d043-4460-a638-34fd0b4ecad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503292843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.503292843
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1865841602
Short name T166
Test name
Test status
Simulation time 1305373774 ps
CPU time 7.82 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 218012 kb
Host smart-32778de3-4ace-4411-adfb-bf95c78528aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865841602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1865841602
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2123932124
Short name T425
Test name
Test status
Simulation time 979078233 ps
CPU time 8.55 seconds
Started May 14 12:53:00 PM PDT 24
Finished May 14 12:53:13 PM PDT 24
Peak memory 224004 kb
Host smart-2ca8bc92-b67b-47f4-b6d0-b38ca3969960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123932124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2123932124
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1648493590
Short name T339
Test name
Test status
Simulation time 30499000 ps
CPU time 1.5 seconds
Started May 14 12:53:02 PM PDT 24
Finished May 14 12:53:07 PM PDT 24
Peak memory 213656 kb
Host smart-7e2da34b-16fe-4477-89bc-57f0383ae287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648493590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1648493590
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3141353651
Short name T431
Test name
Test status
Simulation time 474192101 ps
CPU time 29.36 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 248712 kb
Host smart-f00db266-eecc-413e-9703-9e9bec2a4bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141353651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3141353651
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.788332959
Short name T480
Test name
Test status
Simulation time 277003759 ps
CPU time 3.23 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 222300 kb
Host smart-dbba3f25-8eab-409a-8098-91b5b0b0edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788332959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.788332959
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.251481044
Short name T90
Test name
Test status
Simulation time 138092623736 ps
CPU time 370.68 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:59:26 PM PDT 24
Peak memory 278296 kb
Host smart-757407b9-5407-4dcb-b086-98861a9c3530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251481044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.251481044
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.120893718
Short name T677
Test name
Test status
Simulation time 171408345227 ps
CPU time 1069.02 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 01:10:58 PM PDT 24
Peak memory 440640 kb
Host smart-28544f77-1174-4a27-b804-0ee8683ac02e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=120893718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.120893718
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2923014981
Short name T736
Test name
Test status
Simulation time 38388949 ps
CPU time 0.75 seconds
Started May 14 12:53:05 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 208656 kb
Host smart-61d0348c-d813-4dfc-807c-e8c201b00ec9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923014981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2923014981
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2819906298
Short name T64
Test name
Test status
Simulation time 29687503 ps
CPU time 0.94 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:15 PM PDT 24
Peak memory 209572 kb
Host smart-93087e67-abe3-47d0-9876-9ac4dae5b80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819906298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2819906298
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3419768870
Short name T39
Test name
Test status
Simulation time 2773416993 ps
CPU time 13.82 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:27 PM PDT 24
Peak memory 226096 kb
Host smart-29a8c733-3fc2-4643-8d0a-60ce485672e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419768870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3419768870
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.494853303
Short name T8
Test name
Test status
Simulation time 834570134 ps
CPU time 4.79 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 217020 kb
Host smart-608a92fb-21cc-4ece-996b-f204f0cfd33b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494853303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.494853303
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.4121964108
Short name T47
Test name
Test status
Simulation time 4519507200 ps
CPU time 44.23 seconds
Started May 14 12:53:13 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 218896 kb
Host smart-06d1912b-ea3c-4e1b-9724-725ff515dbcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121964108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.4121964108
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4229050467
Short name T416
Test name
Test status
Simulation time 898667204 ps
CPU time 4.6 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 217812 kb
Host smart-eedcd015-a457-424b-9cd3-0b6436763acf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229050467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4229050467
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3011215421
Short name T662
Test name
Test status
Simulation time 115535901 ps
CPU time 1.77 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:15 PM PDT 24
Peak memory 212456 kb
Host smart-cda47301-a6fd-4956-a62b-f5cd423f79e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011215421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3011215421
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3606631607
Short name T3
Test name
Test status
Simulation time 26653982285 ps
CPU time 57.72 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 267436 kb
Host smart-01e73881-b261-4836-b4fd-cee2f14dcf3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606631607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3606631607
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.4187573340
Short name T751
Test name
Test status
Simulation time 718475339 ps
CPU time 25.72 seconds
Started May 14 12:53:10 PM PDT 24
Finished May 14 12:53:40 PM PDT 24
Peak memory 250920 kb
Host smart-a0bb3131-6af7-468e-8452-afde530939c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187573340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.4187573340
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3140746890
Short name T871
Test name
Test status
Simulation time 62967305 ps
CPU time 2.67 seconds
Started May 14 12:53:06 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 222076 kb
Host smart-17f0f9d3-06d8-487e-923a-1985ad0fa47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140746890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3140746890
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1761744399
Short name T429
Test name
Test status
Simulation time 371914625 ps
CPU time 10.66 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 217948 kb
Host smart-bbc22036-8653-4720-82e1-61fd03c1736c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761744399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1761744399
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.53859717
Short name T295
Test name
Test status
Simulation time 1623847215 ps
CPU time 13.42 seconds
Started May 14 12:53:13 PM PDT 24
Finished May 14 12:53:29 PM PDT 24
Peak memory 217956 kb
Host smart-6af16bda-0376-484c-a6d9-f65fbfa8fab5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53859717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_dig
est.53859717
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3683563838
Short name T602
Test name
Test status
Simulation time 527407855 ps
CPU time 10.56 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 217972 kb
Host smart-641a04d6-bc36-4195-b5c9-075883e6be55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683563838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3683563838
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2075197278
Short name T836
Test name
Test status
Simulation time 870833527 ps
CPU time 16.96 seconds
Started May 14 12:53:12 PM PDT 24
Finished May 14 12:53:32 PM PDT 24
Peak memory 225612 kb
Host smart-08525788-d532-4aff-b8b7-814fd9ac3994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075197278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2075197278
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2856892627
Short name T83
Test name
Test status
Simulation time 47981889 ps
CPU time 2.97 seconds
Started May 14 12:53:12 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 217932 kb
Host smart-949178d1-1fd2-46fc-abb4-b0e77bd7a238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856892627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2856892627
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2250630692
Short name T441
Test name
Test status
Simulation time 313828913 ps
CPU time 24.07 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:37 PM PDT 24
Peak memory 251024 kb
Host smart-6719ff85-8283-4cc1-8cfa-b5576f51ebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250630692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2250630692
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3157534687
Short name T452
Test name
Test status
Simulation time 281907841 ps
CPU time 6.48 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:20 PM PDT 24
Peak memory 243916 kb
Host smart-d44d3827-a29d-45cc-910d-f7647392ba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157534687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3157534687
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3652731598
Short name T475
Test name
Test status
Simulation time 3371943356 ps
CPU time 33.21 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:53:44 PM PDT 24
Peak memory 251080 kb
Host smart-b428f7b8-b8f2-4e3a-8a76-1f1dc7d64d86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652731598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3652731598
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.950223876
Short name T465
Test name
Test status
Simulation time 15582552 ps
CPU time 0.94 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:14 PM PDT 24
Peak memory 211516 kb
Host smart-cd920e2f-d38a-4061-9d22-4ee4b4dafdae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950223876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.950223876
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1702443658
Short name T639
Test name
Test status
Simulation time 40373859 ps
CPU time 1.21 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:14 PM PDT 24
Peak memory 209564 kb
Host smart-d95766e3-fa85-47ed-a59b-7a5441f7ae7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702443658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1702443658
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2863913381
Short name T358
Test name
Test status
Simulation time 1357310067 ps
CPU time 16.65 seconds
Started May 14 12:53:07 PM PDT 24
Finished May 14 12:53:28 PM PDT 24
Peak memory 217900 kb
Host smart-65c90a1b-c1c1-4c68-a1c8-54b9924405ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863913381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2863913381
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1858801286
Short name T27
Test name
Test status
Simulation time 2713669101 ps
CPU time 5.52 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 209664 kb
Host smart-5960f0ba-b8c5-4c2c-b47d-fb912cf845d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858801286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1858801286
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3894091808
Short name T787
Test name
Test status
Simulation time 4547411034 ps
CPU time 37.6 seconds
Started May 14 12:53:10 PM PDT 24
Finished May 14 12:53:52 PM PDT 24
Peak memory 218844 kb
Host smart-aa788ed6-89bc-4eca-be2e-fb16b64963a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894091808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3894091808
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.285276112
Short name T541
Test name
Test status
Simulation time 1675229286 ps
CPU time 11.33 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 217776 kb
Host smart-63856aa0-e58e-40d7-9b53-633ea66407d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285276112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.285276112
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2053623490
Short name T689
Test name
Test status
Simulation time 182359044 ps
CPU time 3.32 seconds
Started May 14 12:53:11 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 213084 kb
Host smart-e657a231-7090-40f6-adac-678f543bbf6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053623490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2053623490
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3994245685
Short name T188
Test name
Test status
Simulation time 13438510787 ps
CPU time 55.67 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 283792 kb
Host smart-a7611999-27a0-412b-8089-03360bc95164
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994245685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3994245685
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3315122583
Short name T335
Test name
Test status
Simulation time 723631891 ps
CPU time 12.08 seconds
Started May 14 12:53:11 PM PDT 24
Finished May 14 12:53:27 PM PDT 24
Peak memory 250944 kb
Host smart-2c9b03b5-7220-4a0b-b6fc-6006a9a7cfd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315122583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3315122583
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2146100611
Short name T178
Test name
Test status
Simulation time 54533705 ps
CPU time 2.3 seconds
Started May 14 12:53:12 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 221616 kb
Host smart-6b9ee766-5656-4915-ac0f-4ee07a437ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146100611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2146100611
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3059733380
Short name T815
Test name
Test status
Simulation time 6748304993 ps
CPU time 18.09 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:31 PM PDT 24
Peak memory 220096 kb
Host smart-d3e5dda9-6371-4032-8906-bce08c998ce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059733380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3059733380
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.976604935
Short name T294
Test name
Test status
Simulation time 2905672464 ps
CPU time 16.01 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:30 PM PDT 24
Peak memory 218244 kb
Host smart-856fb77e-3202-4662-a87a-510ea03aae23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976604935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.976604935
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2130787296
Short name T716
Test name
Test status
Simulation time 205647433 ps
CPU time 5.75 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 217956 kb
Host smart-ae79c70c-7824-4809-8c29-a0ca448faa71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130787296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2130787296
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3069987458
Short name T101
Test name
Test status
Simulation time 397769881 ps
CPU time 9.64 seconds
Started May 14 12:53:10 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 224688 kb
Host smart-0b97e02c-9c38-4edc-a431-9f931959b98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069987458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3069987458
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2853053005
Short name T828
Test name
Test status
Simulation time 26729446 ps
CPU time 1.79 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:13 PM PDT 24
Peak memory 213548 kb
Host smart-73cd849d-96d0-498e-b007-1310ca409f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853053005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2853053005
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.607878366
Short name T832
Test name
Test status
Simulation time 384884255 ps
CPU time 25.81 seconds
Started May 14 12:53:08 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 250876 kb
Host smart-4ee12892-3e02-4d82-a7f6-b30e6cfa8a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607878366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.607878366
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3408148147
Short name T842
Test name
Test status
Simulation time 61734447 ps
CPU time 2.76 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 222152 kb
Host smart-0c67ee51-4817-4475-b3e1-0bc40ac193bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408148147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3408148147
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.375844475
Short name T186
Test name
Test status
Simulation time 15199870774 ps
CPU time 268.37 seconds
Started May 14 12:53:10 PM PDT 24
Finished May 14 12:57:43 PM PDT 24
Peak memory 279860 kb
Host smart-c1dde462-7d1d-46e4-8a13-0b2e63ab2c5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375844475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.375844475
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3969639929
Short name T693
Test name
Test status
Simulation time 21822947 ps
CPU time 0.79 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:14 PM PDT 24
Peak memory 208532 kb
Host smart-26f60e8a-8203-44b9-b1c2-f6934c1a1886
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969639929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3969639929
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1904314957
Short name T576
Test name
Test status
Simulation time 98863611 ps
CPU time 1 seconds
Started May 14 12:53:14 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 209616 kb
Host smart-5bbbfa0c-fb14-4e9e-92a1-b8ff15612d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904314957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1904314957
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1519419531
Short name T621
Test name
Test status
Simulation time 1253714257 ps
CPU time 10.89 seconds
Started May 14 12:53:10 PM PDT 24
Finished May 14 12:53:25 PM PDT 24
Peak memory 217876 kb
Host smart-c689666c-b173-4f59-ba7f-c8e814c52140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519419531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1519419531
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.615624873
Short name T510
Test name
Test status
Simulation time 1746717408 ps
CPU time 3.91 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 209616 kb
Host smart-9de54645-7c03-4186-b166-f8c8f09c42d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615624873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.615624873
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2327500716
Short name T259
Test name
Test status
Simulation time 1510394420 ps
CPU time 28.79 seconds
Started May 14 12:53:24 PM PDT 24
Finished May 14 12:53:55 PM PDT 24
Peak memory 217844 kb
Host smart-690d93d9-b493-4d54-a69c-10fb51e4493f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327500716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2327500716
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1324073370
Short name T305
Test name
Test status
Simulation time 112598575 ps
CPU time 4.42 seconds
Started May 14 12:53:16 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 217956 kb
Host smart-7ce81e9e-2adb-48ca-afe1-34fefeec71bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324073370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1324073370
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.164455717
Short name T319
Test name
Test status
Simulation time 206811483 ps
CPU time 5.57 seconds
Started May 14 12:53:25 PM PDT 24
Finished May 14 12:53:32 PM PDT 24
Peak memory 213096 kb
Host smart-5b5af5ae-364b-4167-94f0-fa3d99e184ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164455717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
164455717
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1615678158
Short name T261
Test name
Test status
Simulation time 15450564931 ps
CPU time 59.3 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 267408 kb
Host smart-3a2ce130-0011-46e7-bcd6-b4dccb5a3f37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615678158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1615678158
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4071468106
Short name T5
Test name
Test status
Simulation time 520558612 ps
CPU time 12.36 seconds
Started May 14 12:53:20 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 250808 kb
Host smart-d1c1c9eb-e5f1-4404-a262-d418a6c023f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071468106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4071468106
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1366446495
Short name T473
Test name
Test status
Simulation time 105355752 ps
CPU time 4.5 seconds
Started May 14 12:53:13 PM PDT 24
Finished May 14 12:53:20 PM PDT 24
Peak memory 221796 kb
Host smart-1630097c-f679-4bb1-bca6-4771a648f8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366446495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1366446495
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3353606256
Short name T868
Test name
Test status
Simulation time 448216300 ps
CPU time 11.22 seconds
Started May 14 12:53:16 PM PDT 24
Finished May 14 12:53:29 PM PDT 24
Peak memory 226056 kb
Host smart-9f11845e-c78b-423c-ad21-c2ac2b6d7452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353606256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3353606256
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3769101196
Short name T757
Test name
Test status
Simulation time 353152687 ps
CPU time 9.78 seconds
Started May 14 12:53:19 PM PDT 24
Finished May 14 12:53:30 PM PDT 24
Peak memory 217928 kb
Host smart-eaeb8fa0-16ff-4a9c-9286-2a5ecff6d4a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769101196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3769101196
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3434914297
Short name T59
Test name
Test status
Simulation time 2114504205 ps
CPU time 16.75 seconds
Started May 14 12:53:15 PM PDT 24
Finished May 14 12:53:33 PM PDT 24
Peak memory 217976 kb
Host smart-ba0347c9-3297-4ded-802e-ae6bc5861eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434914297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3434914297
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.638967428
Short name T637
Test name
Test status
Simulation time 749286044 ps
CPU time 9.52 seconds
Started May 14 12:53:16 PM PDT 24
Finished May 14 12:53:26 PM PDT 24
Peak memory 224328 kb
Host smart-2a2133a9-24c6-47fe-a847-e3524a89069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638967428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.638967428
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.786386479
Short name T73
Test name
Test status
Simulation time 104304643 ps
CPU time 2.19 seconds
Started May 14 12:53:11 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 213772 kb
Host smart-4a3d2bac-00e7-47fa-ad01-7bd85b2c2eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786386479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.786386479
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1766964761
Short name T169
Test name
Test status
Simulation time 1051801327 ps
CPU time 24.69 seconds
Started May 14 12:53:09 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 246352 kb
Host smart-8eb79e96-8546-4483-8f4c-f7cfd112b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766964761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1766964761
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1908086366
Short name T424
Test name
Test status
Simulation time 348551970 ps
CPU time 8.22 seconds
Started May 14 12:53:11 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 243388 kb
Host smart-62544696-fc03-43e6-96ea-4b8288cc6937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908086366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1908086366
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3065959172
Short name T737
Test name
Test status
Simulation time 5001137152 ps
CPU time 71.39 seconds
Started May 14 12:53:26 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 276356 kb
Host smart-ff66d99f-b67e-4241-9978-1263af1272f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065959172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3065959172
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3339942544
Short name T382
Test name
Test status
Simulation time 53305029 ps
CPU time 1.1 seconds
Started May 14 12:53:10 PM PDT 24
Finished May 14 12:53:15 PM PDT 24
Peak memory 211516 kb
Host smart-c489f32e-5e91-44b3-a34b-63b7380a26e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339942544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3339942544
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.4017622033
Short name T243
Test name
Test status
Simulation time 20403570 ps
CPU time 0.91 seconds
Started May 14 12:53:28 PM PDT 24
Finished May 14 12:53:30 PM PDT 24
Peak memory 209548 kb
Host smart-de5be935-0648-4878-b552-c743da9925ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017622033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.4017622033
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2420334083
Short name T515
Test name
Test status
Simulation time 857006141 ps
CPU time 11.75 seconds
Started May 14 12:53:16 PM PDT 24
Finished May 14 12:53:28 PM PDT 24
Peak memory 217976 kb
Host smart-44627367-fdd7-488a-89f4-87be60630a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420334083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2420334083
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1616056188
Short name T735
Test name
Test status
Simulation time 1674730200 ps
CPU time 7.74 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:53:41 PM PDT 24
Peak memory 209464 kb
Host smart-00167b5f-4083-43bf-a44a-cada8f66c6df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616056188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1616056188
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.731606996
Short name T404
Test name
Test status
Simulation time 2096637277 ps
CPU time 36.55 seconds
Started May 14 12:53:21 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 217964 kb
Host smart-851f2fbc-8838-41fb-8d34-d6b821ed68fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731606996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.731606996
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.307026057
Short name T869
Test name
Test status
Simulation time 138762821 ps
CPU time 5.03 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:24 PM PDT 24
Peak memory 217744 kb
Host smart-5b5a07e7-445e-4f3d-9946-17edff8b5d3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307026057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.307026057
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1859116427
Short name T88
Test name
Test status
Simulation time 5654033250 ps
CPU time 5.3 seconds
Started May 14 12:53:26 PM PDT 24
Finished May 14 12:53:32 PM PDT 24
Peak memory 214140 kb
Host smart-46aca802-819f-4ed2-9b0e-94290a0a7334
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859116427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1859116427
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.282668122
Short name T577
Test name
Test status
Simulation time 2907005997 ps
CPU time 97.35 seconds
Started May 14 12:53:21 PM PDT 24
Finished May 14 12:54:59 PM PDT 24
Peak memory 273464 kb
Host smart-5c7153c5-074f-4300-97ff-e12c7acf68b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282668122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.282668122
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3935741085
Short name T244
Test name
Test status
Simulation time 1632786316 ps
CPU time 12.07 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:31 PM PDT 24
Peak memory 247908 kb
Host smart-f9a523c7-8e4a-4bf7-b94e-8ee7de89e837
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935741085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3935741085
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3981879482
Short name T270
Test name
Test status
Simulation time 94273695 ps
CPU time 4.28 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 222084 kb
Host smart-80c63983-d99a-478b-955e-aef38c501cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981879482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3981879482
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.51227090
Short name T771
Test name
Test status
Simulation time 1898057087 ps
CPU time 18.94 seconds
Started May 14 12:53:22 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 226092 kb
Host smart-37748915-22b4-4715-8cc6-fad78aafe334
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51227090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.51227090
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.363260440
Short name T502
Test name
Test status
Simulation time 1046936240 ps
CPU time 11 seconds
Started May 14 12:53:19 PM PDT 24
Finished May 14 12:53:32 PM PDT 24
Peak memory 217956 kb
Host smart-1d593584-d24f-45aa-9fd9-9be803b99c16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363260440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.363260440
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1832616170
Short name T469
Test name
Test status
Simulation time 322725296 ps
CPU time 12.19 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:47 PM PDT 24
Peak memory 218008 kb
Host smart-7ca620d8-4ca2-4429-a155-80c56bcc99ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832616170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1832616170
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3633285513
Short name T760
Test name
Test status
Simulation time 210686573 ps
CPU time 9.9 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:29 PM PDT 24
Peak memory 225056 kb
Host smart-f6a2b2fb-bc33-498d-aaf7-1b1a38657b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633285513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3633285513
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3656885331
Short name T705
Test name
Test status
Simulation time 73377981 ps
CPU time 3.11 seconds
Started May 14 12:53:18 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 214188 kb
Host smart-3034ca0d-20ee-4229-9c1b-88a515d9bfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656885331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3656885331
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.219292462
Short name T9
Test name
Test status
Simulation time 1338039175 ps
CPU time 29.49 seconds
Started May 14 12:53:27 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 250900 kb
Host smart-106d069f-79e9-489a-8475-890921ecfe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219292462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.219292462
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2939408810
Short name T629
Test name
Test status
Simulation time 349705696 ps
CPU time 8.17 seconds
Started May 14 12:53:18 PM PDT 24
Finished May 14 12:53:28 PM PDT 24
Peak memory 244464 kb
Host smart-19c67905-f566-4f56-80e1-e09234c3d05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939408810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2939408810
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1822180822
Short name T838
Test name
Test status
Simulation time 13260694774 ps
CPU time 98.05 seconds
Started May 14 12:53:19 PM PDT 24
Finished May 14 12:54:58 PM PDT 24
Peak memory 250984 kb
Host smart-d66fec6a-5eef-4032-9471-72d3cc98bc69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822180822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1822180822
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3290177606
Short name T622
Test name
Test status
Simulation time 21088618567 ps
CPU time 743.96 seconds
Started May 14 12:53:25 PM PDT 24
Finished May 14 01:05:51 PM PDT 24
Peak memory 284092 kb
Host smart-94a7785e-5627-43ee-a886-1d847f026f78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3290177606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3290177606
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1329749066
Short name T86
Test name
Test status
Simulation time 16544812 ps
CPU time 1.14 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:21 PM PDT 24
Peak memory 211576 kb
Host smart-abcac8f8-b1f5-466b-b968-b0b2f45c408e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329749066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1329749066
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3243531993
Short name T278
Test name
Test status
Simulation time 31158467 ps
CPU time 0.94 seconds
Started May 14 12:52:30 PM PDT 24
Finished May 14 12:52:32 PM PDT 24
Peak memory 209324 kb
Host smart-6b0f3108-931a-4971-81dc-eee0d93e1be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243531993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3243531993
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1954813302
Short name T330
Test name
Test status
Simulation time 33229506 ps
CPU time 0.91 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 209512 kb
Host smart-fe1b31ea-2fd6-4e88-b714-2c0d2f03a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954813302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1954813302
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.370209559
Short name T296
Test name
Test status
Simulation time 838880393 ps
CPU time 16.88 seconds
Started May 14 12:52:22 PM PDT 24
Finished May 14 12:52:41 PM PDT 24
Peak memory 217944 kb
Host smart-1f1aa29e-c9f3-407d-8542-69abbe58d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370209559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.370209559
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1482216930
Short name T805
Test name
Test status
Simulation time 2696279165 ps
CPU time 8.41 seconds
Started May 14 12:52:27 PM PDT 24
Finished May 14 12:52:38 PM PDT 24
Peak memory 209464 kb
Host smart-04939187-cbb7-477c-ab19-fedc1c22d563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482216930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1482216930
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3549578291
Short name T375
Test name
Test status
Simulation time 4507330577 ps
CPU time 33.33 seconds
Started May 14 12:52:27 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 218212 kb
Host smart-f867574a-9da4-4da6-8ac7-2b8b660091dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549578291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3549578291
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1815296534
Short name T697
Test name
Test status
Simulation time 1074411304 ps
CPU time 3.11 seconds
Started May 14 12:52:29 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 217104 kb
Host smart-e819e285-e0a1-40bd-918c-fb99b4a08683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815296534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
815296534
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3402905777
Short name T495
Test name
Test status
Simulation time 840827521 ps
CPU time 5.54 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:28 PM PDT 24
Peak memory 217772 kb
Host smart-5ab98f42-aaba-42e0-94f2-c278e0525892
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402905777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3402905777
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2615603452
Short name T307
Test name
Test status
Simulation time 1275980549 ps
CPU time 37.97 seconds
Started May 14 12:52:24 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 213416 kb
Host smart-4348f38e-5e39-4d4b-970b-fa39b58a17a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615603452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2615603452
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.223348482
Short name T858
Test name
Test status
Simulation time 289468356 ps
CPU time 8.35 seconds
Started May 14 12:52:22 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 213560 kb
Host smart-cf494e74-a9bf-469e-8ce8-0785371faff2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223348482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.223348482
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1318297648
Short name T478
Test name
Test status
Simulation time 4367454020 ps
CPU time 78.51 seconds
Started May 14 12:52:21 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 283748 kb
Host smart-be56c833-8ba8-449c-b2c5-94e767d5e2a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318297648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1318297648
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.261136210
Short name T470
Test name
Test status
Simulation time 1066154106 ps
CPU time 17.3 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:38 PM PDT 24
Peak memory 226416 kb
Host smart-adb2d1e7-2422-4df8-ba9b-7c3d42ab7f7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261136210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.261136210
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2774695874
Short name T700
Test name
Test status
Simulation time 91923850 ps
CPU time 3.21 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:24 PM PDT 24
Peak memory 222088 kb
Host smart-e57ee033-a635-42d8-ad9b-a84db0f364a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774695874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2774695874
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3348353641
Short name T587
Test name
Test status
Simulation time 1388856180 ps
CPU time 8.22 seconds
Started May 14 12:52:17 PM PDT 24
Finished May 14 12:52:28 PM PDT 24
Peak memory 214708 kb
Host smart-1f065577-0fd6-4d94-b9ec-40abbce4d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348353641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3348353641
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2674115489
Short name T111
Test name
Test status
Simulation time 203364485 ps
CPU time 37.48 seconds
Started May 14 12:52:25 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 282108 kb
Host smart-60b14cfd-9bff-45d7-a7cb-b1c9d53862d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674115489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2674115489
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2916848458
Short name T669
Test name
Test status
Simulation time 372113897 ps
CPU time 12.59 seconds
Started May 14 12:52:25 PM PDT 24
Finished May 14 12:52:40 PM PDT 24
Peak memory 218000 kb
Host smart-d90f1cf7-cfaf-4a7b-a160-d796f81afffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916848458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2916848458
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.233833246
Short name T873
Test name
Test status
Simulation time 446901518 ps
CPU time 7.95 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:36 PM PDT 24
Peak memory 217960 kb
Host smart-12860176-81ff-4def-b5c0-1d9fc4fcd3cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233833246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.233833246
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2952907961
Short name T365
Test name
Test status
Simulation time 2532693145 ps
CPU time 6.93 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:36 PM PDT 24
Peak memory 218184 kb
Host smart-2ea0c418-7158-4d59-ac8f-9b1cf55a9ed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952907961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
952907961
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.24315174
Short name T21
Test name
Test status
Simulation time 833030654 ps
CPU time 9.51 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:32 PM PDT 24
Peak memory 224540 kb
Host smart-d21011dd-c6f0-4a91-9823-dc707a8e262c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24315174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.24315174
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.906057522
Short name T395
Test name
Test status
Simulation time 168730409 ps
CPU time 1.91 seconds
Started May 14 12:52:23 PM PDT 24
Finished May 14 12:52:26 PM PDT 24
Peak memory 213536 kb
Host smart-515b0156-f36c-4bae-9861-de435dde05c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906057522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.906057522
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1506428366
Short name T754
Test name
Test status
Simulation time 284062862 ps
CPU time 24.57 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:48 PM PDT 24
Peak memory 251000 kb
Host smart-f4776cfe-0e5c-4afc-be4a-fc45df649f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506428366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1506428366
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.978914012
Short name T274
Test name
Test status
Simulation time 1561955632 ps
CPU time 7.43 seconds
Started May 14 12:52:18 PM PDT 24
Finished May 14 12:52:29 PM PDT 24
Peak memory 242860 kb
Host smart-94864e02-7f75-42a1-9650-92d75b6392e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978914012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.978914012
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1425997669
Short name T322
Test name
Test status
Simulation time 30367114615 ps
CPU time 203.74 seconds
Started May 14 12:52:27 PM PDT 24
Finished May 14 12:55:53 PM PDT 24
Peak memory 282132 kb
Host smart-4e9d61aa-4943-49f0-80e0-51e1d2e10e49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425997669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1425997669
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3699476908
Short name T271
Test name
Test status
Simulation time 20414735 ps
CPU time 0.88 seconds
Started May 14 12:52:19 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 208808 kb
Host smart-1256f638-35d2-41e7-92b7-9cd2a59e4c59
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699476908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3699476908
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3774174927
Short name T766
Test name
Test status
Simulation time 15845632 ps
CPU time 0.86 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:36 PM PDT 24
Peak memory 209528 kb
Host smart-eb694868-5a8a-44e3-be70-a565d1db8b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774174927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3774174927
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1075248522
Short name T440
Test name
Test status
Simulation time 731455242 ps
CPU time 11.44 seconds
Started May 14 12:53:21 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 218004 kb
Host smart-13364858-8df7-4c30-89d1-953493421b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075248522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1075248522
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1620520941
Short name T312
Test name
Test status
Simulation time 27055693 ps
CPU time 2.04 seconds
Started May 14 12:53:20 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 221500 kb
Host smart-ed489bbd-dc3a-4b0b-a330-af5d2f65a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620520941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1620520941
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2642905192
Short name T436
Test name
Test status
Simulation time 1475849676 ps
CPU time 15.94 seconds
Started May 14 12:53:17 PM PDT 24
Finished May 14 12:53:35 PM PDT 24
Peak memory 226084 kb
Host smart-767b918b-7acb-48ef-b0e3-190080de96d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642905192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2642905192
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.848369448
Short name T165
Test name
Test status
Simulation time 660300483 ps
CPU time 23.47 seconds
Started May 14 12:53:28 PM PDT 24
Finished May 14 12:53:53 PM PDT 24
Peak memory 217900 kb
Host smart-12e2dcc1-b5f6-4a02-b669-c3161a4f7fa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848369448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.848369448
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1067248544
Short name T43
Test name
Test status
Simulation time 1399095854 ps
CPU time 8.66 seconds
Started May 14 12:53:24 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 218024 kb
Host smart-f4a20be2-e90a-492e-b7e8-bbdd1cd66315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067248544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1067248544
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.494899301
Short name T698
Test name
Test status
Simulation time 542542734 ps
CPU time 9.84 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 224904 kb
Host smart-a859706f-4cdc-4600-bde1-729df4d8e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494899301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.494899301
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1071110094
Short name T350
Test name
Test status
Simulation time 30540488 ps
CPU time 1.51 seconds
Started May 14 12:53:14 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 213384 kb
Host smart-de659fab-326d-483a-9ff6-e45221aaefca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071110094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1071110094
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3370546372
Short name T228
Test name
Test status
Simulation time 396615043 ps
CPU time 28.77 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 250968 kb
Host smart-415cb3f7-0ce2-4445-91d6-8adaafa35b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370546372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3370546372
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4190399748
Short name T520
Test name
Test status
Simulation time 89182290 ps
CPU time 7.5 seconds
Started May 14 12:53:25 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 246880 kb
Host smart-8977789f-448a-4b58-9b7f-2600a6a90a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190399748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4190399748
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1210617166
Short name T611
Test name
Test status
Simulation time 19189053702 ps
CPU time 185.04 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 283520 kb
Host smart-e5f3a840-4d0f-4cef-8303-eba0c37226ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210617166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1210617166
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2034218593
Short name T640
Test name
Test status
Simulation time 11609985 ps
CPU time 0.95 seconds
Started May 14 12:53:16 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 208856 kb
Host smart-e920f905-3651-401e-ad43-fddf503e6c4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034218593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2034218593
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3791754350
Short name T320
Test name
Test status
Simulation time 14941080 ps
CPU time 0.83 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:36 PM PDT 24
Peak memory 209460 kb
Host smart-87721e9d-28e1-43f6-a845-73484cc2605e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791754350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3791754350
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2469729012
Short name T680
Test name
Test status
Simulation time 1009116026 ps
CPU time 9.87 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:53:41 PM PDT 24
Peak memory 217972 kb
Host smart-ec868cfc-f4c6-497f-a81d-0bdc2b556520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469729012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2469729012
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3958276501
Short name T634
Test name
Test status
Simulation time 2607368472 ps
CPU time 2.18 seconds
Started May 14 12:53:25 PM PDT 24
Finished May 14 12:53:28 PM PDT 24
Peak memory 217028 kb
Host smart-6cdfc07f-1db3-4393-9fc3-6c954f9a9546
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958276501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3958276501
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3231839398
Short name T586
Test name
Test status
Simulation time 94916656 ps
CPU time 3.37 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:38 PM PDT 24
Peak memory 217956 kb
Host smart-6f98c91f-7470-4f89-99d1-acf430e506b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231839398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3231839398
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1315971497
Short name T724
Test name
Test status
Simulation time 973760560 ps
CPU time 14.59 seconds
Started May 14 12:53:32 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 218916 kb
Host smart-49a88594-397d-47d2-82f2-adb9348e1c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315971497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1315971497
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.625129292
Short name T180
Test name
Test status
Simulation time 423644395 ps
CPU time 13.32 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 218004 kb
Host smart-8893a8ee-549b-4f60-ba5c-cd911d7fd257
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625129292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.625129292
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4268170579
Short name T439
Test name
Test status
Simulation time 1455567191 ps
CPU time 8.85 seconds
Started May 14 12:53:30 PM PDT 24
Finished May 14 12:53:41 PM PDT 24
Peak memory 217956 kb
Host smart-de47b149-a21c-440a-a877-ea63026ee1df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268170579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4268170579
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.161776438
Short name T405
Test name
Test status
Simulation time 1647314153 ps
CPU time 9.74 seconds
Started May 14 12:53:27 PM PDT 24
Finished May 14 12:53:38 PM PDT 24
Peak memory 224900 kb
Host smart-b47b3dbb-7e0a-4eb0-98c7-598826bcb650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161776438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.161776438
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3494083936
Short name T780
Test name
Test status
Simulation time 68435859 ps
CPU time 3.36 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:53:36 PM PDT 24
Peak memory 217832 kb
Host smart-d4cc77a2-dd8f-4603-a033-ed19aa974b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494083936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3494083936
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.128883282
Short name T696
Test name
Test status
Simulation time 792193414 ps
CPU time 24.8 seconds
Started May 14 12:53:24 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 245668 kb
Host smart-a2a4fb2e-a491-475c-a45e-7009aea21680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128883282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.128883282
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1893188411
Short name T444
Test name
Test status
Simulation time 307137297 ps
CPU time 3.74 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:53:37 PM PDT 24
Peak memory 222224 kb
Host smart-2f276ff4-e5d1-4dff-b5f5-08a6127ad000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893188411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1893188411
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3419307316
Short name T862
Test name
Test status
Simulation time 18976162826 ps
CPU time 206.5 seconds
Started May 14 12:53:32 PM PDT 24
Finished May 14 12:57:00 PM PDT 24
Peak memory 282652 kb
Host smart-95b994a8-81f8-4b80-9e92-2391181cb2a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419307316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3419307316
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.673648814
Short name T672
Test name
Test status
Simulation time 19085960827 ps
CPU time 159 seconds
Started May 14 12:53:30 PM PDT 24
Finished May 14 12:56:11 PM PDT 24
Peak memory 282312 kb
Host smart-f1520040-c218-418d-997c-c0cf8f8fd94d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=673648814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.673648814
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3943724589
Short name T704
Test name
Test status
Simulation time 11260696 ps
CPU time 0.73 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:36 PM PDT 24
Peak memory 207836 kb
Host smart-86e38be2-eb1e-4d3d-8a87-d7bcf3d37611
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943724589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3943724589
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2792246037
Short name T232
Test name
Test status
Simulation time 18613604 ps
CPU time 1.18 seconds
Started May 14 12:53:28 PM PDT 24
Finished May 14 12:53:30 PM PDT 24
Peak memory 209628 kb
Host smart-6ea139f4-72d6-4662-9bf8-0c8061859523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792246037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2792246037
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2157491368
Short name T749
Test name
Test status
Simulation time 766161277 ps
CPU time 7.14 seconds
Started May 14 12:53:27 PM PDT 24
Finished May 14 12:53:36 PM PDT 24
Peak memory 217944 kb
Host smart-559cc375-52fe-4971-950a-5773bdb37354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157491368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2157491368
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2223201984
Short name T670
Test name
Test status
Simulation time 716258614 ps
CPU time 17.2 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 209556 kb
Host smart-8434e6a8-de53-404b-91c4-12d270a677ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223201984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2223201984
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1501615748
Short name T415
Test name
Test status
Simulation time 67758784 ps
CPU time 2.27 seconds
Started May 14 12:53:26 PM PDT 24
Finished May 14 12:53:29 PM PDT 24
Peak memory 221808 kb
Host smart-82f19333-ce7e-4058-9e52-1d63c25ce401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501615748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1501615748
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2431918370
Short name T418
Test name
Test status
Simulation time 716922377 ps
CPU time 16.66 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 218904 kb
Host smart-ae6ff152-8484-4547-ae38-3362ec1df1eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431918370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2431918370
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1173425399
Short name T351
Test name
Test status
Simulation time 423876302 ps
CPU time 16.13 seconds
Started May 14 12:53:32 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 217956 kb
Host smart-c6bb7746-cba8-4675-949d-5c4c9e96889c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173425399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1173425399
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3821824631
Short name T581
Test name
Test status
Simulation time 1008200422 ps
CPU time 9.45 seconds
Started May 14 12:53:30 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 218008 kb
Host smart-eae48a00-1ebb-48d8-b61c-b83d593aaf63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821824631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3821824631
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2519847727
Short name T746
Test name
Test status
Simulation time 239193071 ps
CPU time 8.33 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 224448 kb
Host smart-ab48af1f-178d-44fc-a913-1cc24905e9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519847727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2519847727
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1198198233
Short name T872
Test name
Test status
Simulation time 309253231 ps
CPU time 3.88 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:53:37 PM PDT 24
Peak memory 217788 kb
Host smart-4ec3bafb-50c6-4268-8596-3f10fe6adb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198198233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1198198233
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3934560450
Short name T733
Test name
Test status
Simulation time 1238203013 ps
CPU time 29.33 seconds
Started May 14 12:53:30 PM PDT 24
Finished May 14 12:54:01 PM PDT 24
Peak memory 250880 kb
Host smart-55026d8b-482a-4c31-871a-9d56e970438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934560450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3934560450
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1225106578
Short name T406
Test name
Test status
Simulation time 238463183 ps
CPU time 2.8 seconds
Started May 14 12:53:34 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 226428 kb
Host smart-e0eb0744-6285-4f77-96f6-265bcd7fb77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225106578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1225106578
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3522155737
Short name T702
Test name
Test status
Simulation time 33185267767 ps
CPU time 98.54 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:55:12 PM PDT 24
Peak memory 251240 kb
Host smart-db15597d-b3d8-4e19-a017-618cb82a2d58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3522155737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3522155737
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.904119594
Short name T411
Test name
Test status
Simulation time 25632284 ps
CPU time 1.19 seconds
Started May 14 12:53:30 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 212916 kb
Host smart-8aaba5ca-94c7-40b8-81c2-3af6afa4dd53
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904119594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.904119594
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2149721062
Short name T708
Test name
Test status
Simulation time 41561658 ps
CPU time 0.92 seconds
Started May 14 12:53:36 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 209592 kb
Host smart-5878fa03-d6b4-43ac-b627-6b58a4185add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149721062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2149721062
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1336535878
Short name T825
Test name
Test status
Simulation time 305909888 ps
CPU time 9.59 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:53:41 PM PDT 24
Peak memory 217952 kb
Host smart-91f26e9c-eb7f-4a43-8538-d579cc8d1e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336535878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1336535878
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.57654988
Short name T507
Test name
Test status
Simulation time 1860135197 ps
CPU time 5.02 seconds
Started May 14 12:53:28 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 209656 kb
Host smart-970aaaed-bdc4-4a49-befc-73700ce0d14d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57654988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.57654988
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3912909626
Short name T279
Test name
Test status
Simulation time 74635976 ps
CPU time 2.78 seconds
Started May 14 12:53:26 PM PDT 24
Finished May 14 12:53:30 PM PDT 24
Peak memory 221916 kb
Host smart-47b23c7c-d743-4e42-a0f0-5de99443badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912909626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3912909626
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.490930939
Short name T612
Test name
Test status
Simulation time 1104453183 ps
CPU time 12.93 seconds
Started May 14 12:53:30 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 218076 kb
Host smart-c865881a-880a-4f42-b33c-9d13d858186c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490930939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.490930939
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.223892126
Short name T525
Test name
Test status
Simulation time 1135875672 ps
CPU time 8.94 seconds
Started May 14 12:53:31 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 218028 kb
Host smart-7b25b6ac-e954-484f-b511-228b5658390c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223892126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.223892126
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2832502976
Short name T387
Test name
Test status
Simulation time 830366418 ps
CPU time 13.86 seconds
Started May 14 12:53:29 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 218040 kb
Host smart-53aa047d-5782-4ac1-915f-1565fe3c7609
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832502976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2832502976
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1811429690
Short name T313
Test name
Test status
Simulation time 281230543 ps
CPU time 9.93 seconds
Started May 14 12:53:30 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 224720 kb
Host smart-4e8fd3f3-af63-48ed-9b95-169e00decdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811429690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1811429690
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.638067856
Short name T850
Test name
Test status
Simulation time 39266203 ps
CPU time 3.02 seconds
Started May 14 12:53:32 PM PDT 24
Finished May 14 12:53:37 PM PDT 24
Peak memory 214332 kb
Host smart-b24ff2c3-7475-4afe-beae-5412f429003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638067856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.638067856
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.940106448
Short name T761
Test name
Test status
Simulation time 455367746 ps
CPU time 26.36 seconds
Started May 14 12:53:26 PM PDT 24
Finished May 14 12:53:54 PM PDT 24
Peak memory 244720 kb
Host smart-ef454bb7-eff6-4b71-b890-115adef33617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940106448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.940106448
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2243709348
Short name T666
Test name
Test status
Simulation time 137960601 ps
CPU time 7.03 seconds
Started May 14 12:53:34 PM PDT 24
Finished May 14 12:53:43 PM PDT 24
Peak memory 250888 kb
Host smart-ff269c5f-d309-4c2e-a846-fbb1d6f2ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243709348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2243709348
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.248372473
Short name T380
Test name
Test status
Simulation time 19978915972 ps
CPU time 436.3 seconds
Started May 14 12:53:40 PM PDT 24
Finished May 14 01:00:58 PM PDT 24
Peak memory 267484 kb
Host smart-03a115c1-25df-4393-a89c-16939bc1a60a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248372473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.248372473
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3736462609
Short name T122
Test name
Test status
Simulation time 42521820464 ps
CPU time 754.72 seconds
Started May 14 12:53:38 PM PDT 24
Finished May 14 01:06:14 PM PDT 24
Peak memory 330356 kb
Host smart-1e171ab6-89d4-48f8-8d83-b897366a3a49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3736462609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3736462609
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2020420439
Short name T600
Test name
Test status
Simulation time 134596597 ps
CPU time 0.99 seconds
Started May 14 12:53:32 PM PDT 24
Finished May 14 12:53:35 PM PDT 24
Peak memory 211656 kb
Host smart-1389d0a5-146e-40c9-96a6-b612107080d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020420439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2020420439
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3531313160
Short name T435
Test name
Test status
Simulation time 61490869 ps
CPU time 0.84 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 209536 kb
Host smart-aede7d24-89aa-4d8a-b8b5-166ca31f23f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531313160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3531313160
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1207189264
Short name T174
Test name
Test status
Simulation time 295382754 ps
CPU time 12.6 seconds
Started May 14 12:53:40 PM PDT 24
Finished May 14 12:53:55 PM PDT 24
Peak memory 218004 kb
Host smart-c36f43fb-11e0-4d58-9750-98978900029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207189264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1207189264
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.648596252
Short name T867
Test name
Test status
Simulation time 178481325 ps
CPU time 4.94 seconds
Started May 14 12:53:38 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 209472 kb
Host smart-6b7e2d70-4ac1-4b2e-baf5-3ace61c7031a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648596252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.648596252
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3644565817
Short name T315
Test name
Test status
Simulation time 59284584 ps
CPU time 2.58 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:43 PM PDT 24
Peak memory 221808 kb
Host smart-f266a1ff-77af-415a-b505-940b3918e122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644565817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3644565817
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2357222869
Short name T567
Test name
Test status
Simulation time 1211650301 ps
CPU time 13.67 seconds
Started May 14 12:53:37 PM PDT 24
Finished May 14 12:53:52 PM PDT 24
Peak memory 218312 kb
Host smart-7fb3b6a0-8d36-4336-abed-7a650e16e8b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357222869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2357222869
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2376590797
Short name T275
Test name
Test status
Simulation time 366084906 ps
CPU time 13.05 seconds
Started May 14 12:53:34 PM PDT 24
Finished May 14 12:53:49 PM PDT 24
Peak memory 218008 kb
Host smart-070b370e-daa4-494a-b8a1-232ceed65b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376590797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2376590797
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1581890549
Short name T304
Test name
Test status
Simulation time 350053232 ps
CPU time 8.28 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:49 PM PDT 24
Peak memory 217952 kb
Host smart-f211ff24-243c-40d8-89f4-04526f1c9f6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581890549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1581890549
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3631790430
Short name T876
Test name
Test status
Simulation time 1494946452 ps
CPU time 11.57 seconds
Started May 14 12:53:32 PM PDT 24
Finished May 14 12:53:45 PM PDT 24
Peak memory 225284 kb
Host smart-462f97e1-cc5c-4ac8-bc2a-3a2af46df51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631790430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3631790430
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2794805414
Short name T76
Test name
Test status
Simulation time 779188125 ps
CPU time 4.87 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:46 PM PDT 24
Peak memory 217728 kb
Host smart-4425870f-20ef-413e-8238-d5d4a3f1ff99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794805414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2794805414
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.230044376
Short name T363
Test name
Test status
Simulation time 338369642 ps
CPU time 29.81 seconds
Started May 14 12:53:34 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 247000 kb
Host smart-61e8f6a4-1735-426c-bd56-5a0277ffe4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230044376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.230044376
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3672880328
Short name T115
Test name
Test status
Simulation time 82708989 ps
CPU time 9.77 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:51 PM PDT 24
Peak memory 251000 kb
Host smart-5d791069-6ac4-4964-949f-89b75aed0611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672880328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3672880328
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3237765460
Short name T485
Test name
Test status
Simulation time 3329048111 ps
CPU time 98 seconds
Started May 14 12:53:36 PM PDT 24
Finished May 14 12:55:15 PM PDT 24
Peak memory 277960 kb
Host smart-4e97174c-ffcb-4562-b04f-236f6a20c45f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237765460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3237765460
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1342616840
Short name T539
Test name
Test status
Simulation time 26464432 ps
CPU time 0.83 seconds
Started May 14 12:53:40 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 208776 kb
Host smart-9280984f-4c66-4b61-bb2d-7cbe61c0a9fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342616840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1342616840
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.4027721612
Short name T189
Test name
Test status
Simulation time 138338114 ps
CPU time 0.81 seconds
Started May 14 12:53:36 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 209524 kb
Host smart-610d0644-35af-4203-a74a-b3dffb27aa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027721612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.4027721612
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2230610967
Short name T824
Test name
Test status
Simulation time 2500058282 ps
CPU time 8.64 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:44 PM PDT 24
Peak memory 218012 kb
Host smart-cb669d55-ad8d-4ef0-a329-2b1781fe79ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230610967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2230610967
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.477875414
Short name T24
Test name
Test status
Simulation time 739875976 ps
CPU time 9.02 seconds
Started May 14 12:53:37 PM PDT 24
Finished May 14 12:53:49 PM PDT 24
Peak memory 209508 kb
Host smart-8ce415d4-1a44-4889-a9cb-caaaa52d282d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477875414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.477875414
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.993932650
Short name T607
Test name
Test status
Simulation time 55738137 ps
CPU time 2.51 seconds
Started May 14 12:53:38 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 221636 kb
Host smart-cb90c365-b1ae-4fec-bf1c-897ad4108d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993932650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.993932650
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1932390684
Short name T575
Test name
Test status
Simulation time 1325475552 ps
CPU time 11.93 seconds
Started May 14 12:53:41 PM PDT 24
Finished May 14 12:53:55 PM PDT 24
Peak memory 219208 kb
Host smart-d951906e-8478-45b3-a707-1af6cc36e617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932390684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1932390684
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1277652295
Short name T591
Test name
Test status
Simulation time 364857950 ps
CPU time 10.97 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:53:46 PM PDT 24
Peak memory 217964 kb
Host smart-936650da-8485-4139-b7dd-1fbe2fa077e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277652295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1277652295
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.149568532
Short name T497
Test name
Test status
Simulation time 200704709 ps
CPU time 6.66 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 217944 kb
Host smart-fae32068-c100-4951-91c3-51da86545b23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149568532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.149568532
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.104497352
Short name T655
Test name
Test status
Simulation time 30010216 ps
CPU time 2.14 seconds
Started May 14 12:53:42 PM PDT 24
Finished May 14 12:53:46 PM PDT 24
Peak memory 218436 kb
Host smart-c17f76dd-dd04-4989-8f47-a8b63c1e9dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104497352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.104497352
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.433027014
Short name T97
Test name
Test status
Simulation time 215954100 ps
CPU time 25.71 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 250988 kb
Host smart-e6e3868f-eca9-4620-923f-80ee2d3f554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433027014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.433027014
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1363797544
Short name T644
Test name
Test status
Simulation time 365668849 ps
CPU time 6.25 seconds
Started May 14 12:53:38 PM PDT 24
Finished May 14 12:53:46 PM PDT 24
Peak memory 250828 kb
Host smart-cb8461c5-5ea8-4059-9473-ae86717a26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363797544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1363797544
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.301301662
Short name T420
Test name
Test status
Simulation time 46959881092 ps
CPU time 173.84 seconds
Started May 14 12:53:36 PM PDT 24
Finished May 14 12:56:32 PM PDT 24
Peak memory 276140 kb
Host smart-353b0525-343e-468a-a70e-a00ebdd8f5bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301301662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.301301662
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.512072666
Short name T164
Test name
Test status
Simulation time 36964735128 ps
CPU time 1311.89 seconds
Started May 14 12:53:40 PM PDT 24
Finished May 14 01:15:34 PM PDT 24
Peak memory 496932 kb
Host smart-48f42f5f-928f-4904-9d02-55b8b385281d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=512072666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.512072666
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1187511986
Short name T516
Test name
Test status
Simulation time 39512856 ps
CPU time 0.93 seconds
Started May 14 12:53:41 PM PDT 24
Finished May 14 12:53:44 PM PDT 24
Peak memory 211568 kb
Host smart-1d750c78-f0c5-4e0a-b23f-41cc0077e300
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187511986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1187511986
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.260856653
Short name T665
Test name
Test status
Simulation time 106794222 ps
CPU time 1.05 seconds
Started May 14 12:53:37 PM PDT 24
Finished May 14 12:53:40 PM PDT 24
Peak memory 209612 kb
Host smart-15f5f4bd-85b1-426e-ae84-48672d113b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260856653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.260856653
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4006006267
Short name T314
Test name
Test status
Simulation time 546674322 ps
CPU time 20.82 seconds
Started May 14 12:53:37 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 217992 kb
Host smart-b14f2439-9a1b-4e12-8a9e-ccbca96bb8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006006267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4006006267
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.787936466
Short name T804
Test name
Test status
Simulation time 2960211492 ps
CPU time 4.27 seconds
Started May 14 12:53:36 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 217288 kb
Host smart-4ac3099f-63a5-4ddc-9d72-b29a0e43fb80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787936466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.787936466
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.4166358120
Short name T830
Test name
Test status
Simulation time 67096402 ps
CPU time 2.36 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:43 PM PDT 24
Peak memory 217872 kb
Host smart-4093a73a-2483-4d53-bb41-726e964a7c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166358120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.4166358120
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2500156258
Short name T442
Test name
Test status
Simulation time 748935645 ps
CPU time 9.91 seconds
Started May 14 12:53:38 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 218204 kb
Host smart-ad22b53e-49c0-4b1b-9921-f1418586e565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500156258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2500156258
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1039611527
Short name T366
Test name
Test status
Simulation time 889588901 ps
CPU time 7.95 seconds
Started May 14 12:53:38 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 217896 kb
Host smart-5c96654f-0bf9-41a4-b1f8-d8f47365ec59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039611527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1039611527
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3077692873
Short name T646
Test name
Test status
Simulation time 1014271395 ps
CPU time 9.3 seconds
Started May 14 12:53:38 PM PDT 24
Finished May 14 12:53:49 PM PDT 24
Peak memory 217976 kb
Host smart-50f364bb-b6ce-4916-8435-697106f55b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077692873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3077692873
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1971497478
Short name T773
Test name
Test status
Simulation time 255133053 ps
CPU time 8.73 seconds
Started May 14 12:53:37 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 225268 kb
Host smart-b64e8e9f-43f7-4d3d-88c7-71110d938b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971497478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1971497478
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.92618689
Short name T776
Test name
Test status
Simulation time 290254675 ps
CPU time 5.3 seconds
Started May 14 12:53:36 PM PDT 24
Finished May 14 12:53:43 PM PDT 24
Peak memory 217644 kb
Host smart-2d7dcdb5-44ba-4b2f-8aff-3234385ce986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92618689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.92618689
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3905107875
Short name T430
Test name
Test status
Simulation time 227585012 ps
CPU time 26.64 seconds
Started May 14 12:53:41 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 245844 kb
Host smart-cb457870-54dc-4f10-aabc-c03dab03f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905107875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3905107875
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2811744503
Short name T254
Test name
Test status
Simulation time 130666624 ps
CPU time 3.97 seconds
Started May 14 12:53:37 PM PDT 24
Finished May 14 12:53:43 PM PDT 24
Peak memory 222632 kb
Host smart-7921ff78-34b3-4963-8709-b3b60c392be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811744503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2811744503
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.996286030
Short name T707
Test name
Test status
Simulation time 15093063600 ps
CPU time 95.72 seconds
Started May 14 12:53:33 PM PDT 24
Finished May 14 12:55:11 PM PDT 24
Peak memory 251104 kb
Host smart-ae650c17-754c-4cc3-a709-62d3675278a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996286030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.996286030
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.216322556
Short name T624
Test name
Test status
Simulation time 15379644 ps
CPU time 0.95 seconds
Started May 14 12:53:34 PM PDT 24
Finished May 14 12:53:37 PM PDT 24
Peak memory 211544 kb
Host smart-e9db857c-fef4-4939-8efb-1d5418e6d75e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216322556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.216322556
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1367366596
Short name T790
Test name
Test status
Simulation time 51185548 ps
CPU time 0.99 seconds
Started May 14 12:53:44 PM PDT 24
Finished May 14 12:53:46 PM PDT 24
Peak memory 209624 kb
Host smart-a8b90bbb-b9af-4181-8ce2-2fce2d0bab6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367366596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1367366596
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3728260776
Short name T269
Test name
Test status
Simulation time 1752778573 ps
CPU time 13.46 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:54:02 PM PDT 24
Peak memory 217988 kb
Host smart-0b33ef0d-712f-4312-9002-ee84c4586fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728260776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3728260776
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2818345849
Short name T810
Test name
Test status
Simulation time 2568280152 ps
CPU time 5.82 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 209624 kb
Host smart-8d70e803-f3bf-4c8b-aa28-04f6e31f0b16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818345849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2818345849
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2783535727
Short name T523
Test name
Test status
Simulation time 249810664 ps
CPU time 2.61 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 221968 kb
Host smart-a76c512a-c066-45bf-a4b7-04dcd410b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783535727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2783535727
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4013638281
Short name T310
Test name
Test status
Simulation time 824329643 ps
CPU time 8.71 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:53:57 PM PDT 24
Peak memory 217928 kb
Host smart-2fa7b037-a1ea-4a3c-8df3-8700e9c533d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013638281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4013638281
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.577175413
Short name T839
Test name
Test status
Simulation time 1147267191 ps
CPU time 9.7 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 217956 kb
Host smart-8ab51838-4511-42e1-abd6-3f8573001dbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577175413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.577175413
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2818399569
Short name T627
Test name
Test status
Simulation time 756650970 ps
CPU time 9.88 seconds
Started May 14 12:53:44 PM PDT 24
Finished May 14 12:53:56 PM PDT 24
Peak memory 217856 kb
Host smart-eddc79f2-b889-40ce-8898-15fce0541f61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818399569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2818399569
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.656510728
Short name T246
Test name
Test status
Simulation time 233532405 ps
CPU time 7.51 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:54:02 PM PDT 24
Peak memory 226084 kb
Host smart-99f65299-496c-4014-b9c8-9e72b3df6162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656510728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.656510728
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3555000599
Short name T414
Test name
Test status
Simulation time 37792734 ps
CPU time 1.65 seconds
Started May 14 12:53:34 PM PDT 24
Finished May 14 12:53:37 PM PDT 24
Peak memory 217896 kb
Host smart-ea1676f1-7d26-4d8e-b4f3-4adb0e14a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555000599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3555000599
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3581899897
Short name T782
Test name
Test status
Simulation time 334357626 ps
CPU time 34.57 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:54:24 PM PDT 24
Peak memory 248564 kb
Host smart-d6cfb73e-6ef5-4f52-9dfe-e780369080f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581899897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3581899897
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2208279679
Short name T870
Test name
Test status
Simulation time 431257977 ps
CPU time 6.68 seconds
Started May 14 12:53:40 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 250428 kb
Host smart-0b0c8ba5-6768-4c03-96ad-09ae8c09b81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208279679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2208279679
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2846502967
Short name T80
Test name
Test status
Simulation time 27887922 ps
CPU time 1.14 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 211524 kb
Host smart-8acbfade-197d-4101-bd91-36b02a7bb188
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846502967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2846502967
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2976351117
Short name T738
Test name
Test status
Simulation time 17289140 ps
CPU time 1.06 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:53:46 PM PDT 24
Peak memory 209376 kb
Host smart-6ffea273-13d2-4b67-a6d2-1cec6d0e856f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976351117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2976351117
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3236237801
Short name T610
Test name
Test status
Simulation time 3703088929 ps
CPU time 21.92 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 218040 kb
Host smart-dd4d642a-5283-4b88-8ee9-5a0f4bc28e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236237801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3236237801
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1843587436
Short name T499
Test name
Test status
Simulation time 53627574 ps
CPU time 1.44 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:53:55 PM PDT 24
Peak memory 216956 kb
Host smart-0acc7547-86eb-4e6a-8427-7542fde4175b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843587436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1843587436
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3653508548
Short name T571
Test name
Test status
Simulation time 77499036 ps
CPU time 1.82 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 221584 kb
Host smart-26c5dd39-6f76-4a26-9d54-2ab8389a773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653508548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3653508548
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3116078533
Short name T756
Test name
Test status
Simulation time 766617689 ps
CPU time 13.72 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 218032 kb
Host smart-bf12ea1c-f092-4b66-afe2-9fc6c203647a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116078533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3116078533
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2400364700
Short name T104
Test name
Test status
Simulation time 202406706 ps
CPU time 9.08 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 217980 kb
Host smart-d72b219d-6417-4759-a3eb-20d3d33a7d71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400364700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2400364700
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.272476486
Short name T247
Test name
Test status
Simulation time 427283791 ps
CPU time 10.32 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:54:01 PM PDT 24
Peak memory 217872 kb
Host smart-ecc6cd28-0566-429b-844a-d6c86f22b525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272476486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.272476486
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1894662158
Short name T560
Test name
Test status
Simulation time 268219908 ps
CPU time 3.86 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:53:52 PM PDT 24
Peak memory 217972 kb
Host smart-89d3727f-e139-4447-a003-c1dc6f9d1b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894662158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1894662158
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3241725902
Short name T277
Test name
Test status
Simulation time 966735859 ps
CPU time 24.01 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 247356 kb
Host smart-9c425b05-2b62-4c63-a443-d89f704004de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241725902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3241725902
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.131880899
Short name T187
Test name
Test status
Simulation time 308239525 ps
CPU time 7.58 seconds
Started May 14 12:53:48 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 250456 kb
Host smart-626a6e61-fdb6-4670-9d04-0f83e72bcfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131880899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.131880899
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.254445268
Short name T198
Test name
Test status
Simulation time 9817775233 ps
CPU time 179.52 seconds
Started May 14 12:53:39 PM PDT 24
Finished May 14 12:56:40 PM PDT 24
Peak memory 253340 kb
Host smart-98e8d84b-fdc7-4b59-8f83-6eb89100cca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254445268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.254445268
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3895788215
Short name T265
Test name
Test status
Simulation time 11148631 ps
CPU time 0.92 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:53:53 PM PDT 24
Peak memory 211692 kb
Host smart-332dda4f-4732-48f5-b342-289be317fccf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895788215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3895788215
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2128366375
Short name T345
Test name
Test status
Simulation time 53600805 ps
CPU time 1.02 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 209584 kb
Host smart-77521a59-72c2-4a00-b8e4-fde80fb9a512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128366375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2128366375
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1213912111
Short name T301
Test name
Test status
Simulation time 1656420186 ps
CPU time 12.72 seconds
Started May 14 12:53:55 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 226020 kb
Host smart-359f84ff-4a31-4a55-a9c5-c093e1f16654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213912111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1213912111
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3263000719
Short name T552
Test name
Test status
Simulation time 2856253960 ps
CPU time 11.86 seconds
Started May 14 12:53:46 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 209624 kb
Host smart-af168a0d-1786-4f11-a078-8fb2264736d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263000719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3263000719
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3263406471
Short name T484
Test name
Test status
Simulation time 201994202 ps
CPU time 2.73 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 221872 kb
Host smart-cc70b3ae-a179-42da-b4b6-36218665646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263406471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3263406471
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1176705461
Short name T226
Test name
Test status
Simulation time 1731885102 ps
CPU time 14.74 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 218872 kb
Host smart-81ec6c46-9e2d-4928-b581-1b6875313f55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176705461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1176705461
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1656187658
Short name T557
Test name
Test status
Simulation time 1683303727 ps
CPU time 14.74 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:54:03 PM PDT 24
Peak memory 217996 kb
Host smart-de119fad-c71e-4afe-846f-8239e7494c7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656187658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1656187658
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3838584132
Short name T727
Test name
Test status
Simulation time 1348593380 ps
CPU time 13.64 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 217988 kb
Host smart-a0e06146-e793-48cb-803f-1adc85389ed4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838584132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3838584132
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1354266968
Short name T56
Test name
Test status
Simulation time 187829779 ps
CPU time 7.27 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:53:52 PM PDT 24
Peak memory 224124 kb
Host smart-cdcab897-28d0-4bc5-b4ea-cd572f6d1d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354266968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1354266968
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3770493237
Short name T306
Test name
Test status
Simulation time 15509404 ps
CPU time 1.03 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:53:54 PM PDT 24
Peak memory 211940 kb
Host smart-aa7d512f-8ef0-4f93-980e-2c63d3c41d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770493237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3770493237
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3093011441
Short name T329
Test name
Test status
Simulation time 2900268015 ps
CPU time 28.14 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:54:17 PM PDT 24
Peak memory 248712 kb
Host smart-86be7983-b395-4bd7-8ef9-2cf8726db30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093011441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3093011441
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1426962019
Short name T617
Test name
Test status
Simulation time 49669370 ps
CPU time 2.9 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 226196 kb
Host smart-2d960dd6-cc7e-41ec-b918-028ce376860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426962019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1426962019
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.42066406
Short name T538
Test name
Test status
Simulation time 3160644307 ps
CPU time 51.73 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 226252 kb
Host smart-3144e826-b153-48ff-8ab1-aed2e7e3f826
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42066406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.lc_ctrl_stress_all.42066406
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3902259278
Short name T298
Test name
Test status
Simulation time 38382312 ps
CPU time 0.97 seconds
Started May 14 12:53:56 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 211600 kb
Host smart-9254f568-faf4-4f3b-a61c-2f851b1309ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902259278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3902259278
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1899212250
Short name T742
Test name
Test status
Simulation time 37138994 ps
CPU time 0.96 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:29 PM PDT 24
Peak memory 209608 kb
Host smart-0014ac5a-2da2-4c46-b56b-e23f8456b759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899212250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1899212250
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.696181409
Short name T286
Test name
Test status
Simulation time 20814971 ps
CPU time 0.9 seconds
Started May 14 12:52:28 PM PDT 24
Finished May 14 12:52:31 PM PDT 24
Peak memory 209400 kb
Host smart-221c576b-6ab5-49e4-8558-047a2030e32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696181409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.696181409
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.632800243
Short name T563
Test name
Test status
Simulation time 272266255 ps
CPU time 10.56 seconds
Started May 14 12:52:27 PM PDT 24
Finished May 14 12:52:40 PM PDT 24
Peak memory 218236 kb
Host smart-009cfd92-3d02-4891-9161-a588dde4d0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632800243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.632800243
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.322557666
Short name T865
Test name
Test status
Simulation time 647389326 ps
CPU time 2.95 seconds
Started May 14 12:52:29 PM PDT 24
Finished May 14 12:52:34 PM PDT 24
Peak memory 216880 kb
Host smart-9d9a54e7-cae6-4de9-a077-ee96c7fa0d56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322557666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.322557666
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1021845132
Short name T801
Test name
Test status
Simulation time 367654355 ps
CPU time 1.66 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:30 PM PDT 24
Peak memory 217828 kb
Host smart-bd2bb262-a75c-448b-84f8-c3e5dcbc97e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021845132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
021845132
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2779957178
Short name T196
Test name
Test status
Simulation time 295306992 ps
CPU time 5.89 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:35 PM PDT 24
Peak memory 217932 kb
Host smart-a1438441-21e4-4f2d-aa43-4994f62a5a94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779957178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2779957178
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2730899849
Short name T449
Test name
Test status
Simulation time 4107706894 ps
CPU time 30.33 seconds
Started May 14 12:52:25 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 213904 kb
Host smart-31b4142c-2f4e-4359-81ab-c5c6e2305f55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730899849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2730899849
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2794067102
Short name T308
Test name
Test status
Simulation time 1009268507 ps
CPU time 3.83 seconds
Started May 14 12:52:24 PM PDT 24
Finished May 14 12:52:30 PM PDT 24
Peak memory 212900 kb
Host smart-8a45df6a-d6ec-47a1-8f5a-fed0300dae03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794067102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2794067102
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1195931068
Short name T566
Test name
Test status
Simulation time 2228357290 ps
CPU time 47.32 seconds
Started May 14 12:52:31 PM PDT 24
Finished May 14 12:53:20 PM PDT 24
Peak memory 276000 kb
Host smart-86f6aad8-40a6-4fc3-a7ba-e038deab690f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195931068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1195931068
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2355676329
Short name T472
Test name
Test status
Simulation time 2406333637 ps
CPU time 20.01 seconds
Started May 14 12:52:29 PM PDT 24
Finished May 14 12:52:51 PM PDT 24
Peak memory 250984 kb
Host smart-78374749-b1d8-4fcd-8f61-4fc08d1301cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355676329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2355676329
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1326026536
Short name T663
Test name
Test status
Simulation time 176232565 ps
CPU time 1.54 seconds
Started May 14 12:52:25 PM PDT 24
Finished May 14 12:52:28 PM PDT 24
Peak memory 217760 kb
Host smart-85c5d755-8c71-4a39-97b4-4eeccd1e533f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326026536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1326026536
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.690408483
Short name T741
Test name
Test status
Simulation time 405351312 ps
CPU time 15.55 seconds
Started May 14 12:52:24 PM PDT 24
Finished May 14 12:52:41 PM PDT 24
Peak memory 217764 kb
Host smart-0f71734b-cd06-4ce6-a552-ae8140beaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690408483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.690408483
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1275449495
Short name T91
Test name
Test status
Simulation time 235852085 ps
CPU time 36.89 seconds
Started May 14 12:52:24 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 282440 kb
Host smart-20cd55eb-3c05-4ce8-92ff-d09214a17f6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275449495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1275449495
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.393159760
Short name T192
Test name
Test status
Simulation time 907384398 ps
CPU time 13.46 seconds
Started May 14 12:52:29 PM PDT 24
Finished May 14 12:52:44 PM PDT 24
Peak memory 218020 kb
Host smart-fe5017ff-9f33-4d21-9bbb-354b279dab93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393159760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.393159760
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2757167649
Short name T852
Test name
Test status
Simulation time 169309505 ps
CPU time 9.02 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:37 PM PDT 24
Peak memory 226076 kb
Host smart-252f441c-2487-42a5-958c-b840106978ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757167649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2757167649
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2945649917
Short name T450
Test name
Test status
Simulation time 3038691126 ps
CPU time 11.34 seconds
Started May 14 12:52:32 PM PDT 24
Finished May 14 12:52:45 PM PDT 24
Peak memory 217944 kb
Host smart-abdb2bb8-5738-4fc9-b52b-7c5e14072d42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945649917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
945649917
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1667920366
Short name T723
Test name
Test status
Simulation time 190716804 ps
CPU time 8.5 seconds
Started May 14 12:52:25 PM PDT 24
Finished May 14 12:52:35 PM PDT 24
Peak memory 225120 kb
Host smart-975eab49-8f54-4a4e-8d9f-9c6e324c4b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667920366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1667920366
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.29264315
Short name T753
Test name
Test status
Simulation time 35815003 ps
CPU time 2.4 seconds
Started May 14 12:52:32 PM PDT 24
Finished May 14 12:52:36 PM PDT 24
Peak memory 214048 kb
Host smart-308cac32-a2ce-4244-a9a5-388b39cfadb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29264315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.29264315
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1569816225
Short name T468
Test name
Test status
Simulation time 894056143 ps
CPU time 31.13 seconds
Started May 14 12:52:29 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 250880 kb
Host smart-559f35e0-d7f4-403d-8e45-41785a1dd5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569816225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1569816225
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3828256310
Short name T1
Test name
Test status
Simulation time 82027719 ps
CPU time 6.83 seconds
Started May 14 12:52:25 PM PDT 24
Finished May 14 12:52:34 PM PDT 24
Peak memory 250412 kb
Host smart-41ec8a56-5ec4-40f6-a413-77d64b6b6ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828256310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3828256310
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.367160471
Short name T481
Test name
Test status
Simulation time 2427454649 ps
CPU time 80.21 seconds
Started May 14 12:52:28 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 250832 kb
Host smart-cdf291b9-3286-4c2c-ba4a-4bcaa027ec24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367160471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.367160471
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1567051741
Short name T263
Test name
Test status
Simulation time 12348948 ps
CPU time 0.85 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:29 PM PDT 24
Peak memory 208812 kb
Host smart-232e662f-dade-4d8e-9496-073709ac49ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567051741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1567051741
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2509261068
Short name T855
Test name
Test status
Simulation time 21590957 ps
CPU time 1.17 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:53:53 PM PDT 24
Peak memory 209576 kb
Host smart-9a5b66b7-5ca8-48aa-94a1-49d3cd9300f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509261068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2509261068
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1676461018
Short name T44
Test name
Test status
Simulation time 303755170 ps
CPU time 14.7 seconds
Started May 14 12:53:46 PM PDT 24
Finished May 14 12:54:02 PM PDT 24
Peak memory 217916 kb
Host smart-8e5f20a4-38fd-4ff1-b6cc-43e877bffed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676461018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1676461018
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4041377447
Short name T451
Test name
Test status
Simulation time 2094944011 ps
CPU time 8.97 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:01 PM PDT 24
Peak memory 209560 kb
Host smart-bc021c29-9ec7-4ffa-ac19-ebc3689fa706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041377447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4041377447
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1629519630
Short name T238
Test name
Test status
Simulation time 63168047 ps
CPU time 3.52 seconds
Started May 14 12:53:41 PM PDT 24
Finished May 14 12:53:47 PM PDT 24
Peak memory 221808 kb
Host smart-95192c54-5391-47a3-a905-d20375ad71e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629519630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1629519630
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3023258649
Short name T48
Test name
Test status
Simulation time 5648400821 ps
CPU time 20.67 seconds
Started May 14 12:53:41 PM PDT 24
Finished May 14 12:54:03 PM PDT 24
Peak memory 218980 kb
Host smart-17f2198c-941b-4461-ab05-e3ec61aea55f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023258649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3023258649
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4048457167
Short name T96
Test name
Test status
Simulation time 313364661 ps
CPU time 13.67 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 218092 kb
Host smart-931f02ec-e1c1-4d40-8063-d1f2767953e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048457167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4048457167
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.476243424
Short name T731
Test name
Test status
Simulation time 333986660 ps
CPU time 8.18 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 217868 kb
Host smart-f845de49-e7d1-4221-9b87-21eed9aea9b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476243424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.476243424
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.450769405
Short name T500
Test name
Test status
Simulation time 1412065691 ps
CPU time 10.08 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:03 PM PDT 24
Peak memory 226112 kb
Host smart-73741efc-49c9-4ac4-b9e4-9964c7422b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450769405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.450769405
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.60378982
Short name T85
Test name
Test status
Simulation time 96181024 ps
CPU time 6.24 seconds
Started May 14 12:53:46 PM PDT 24
Finished May 14 12:53:53 PM PDT 24
Peak memory 217736 kb
Host smart-ba845f9f-8b95-4715-a07c-b1bc171fcb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60378982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.60378982
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.4027530122
Short name T355
Test name
Test status
Simulation time 390705190 ps
CPU time 22.61 seconds
Started May 14 12:53:46 PM PDT 24
Finished May 14 12:54:10 PM PDT 24
Peak memory 246464 kb
Host smart-5d477744-9ea0-400b-ba42-a235e4a1ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027530122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4027530122
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2031889264
Short name T822
Test name
Test status
Simulation time 47275461 ps
CPU time 6.16 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 244152 kb
Host smart-445184cd-e06a-4e26-9b0d-ca1a3370650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031889264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2031889264
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3092179034
Short name T190
Test name
Test status
Simulation time 15119249260 ps
CPU time 79.96 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:55:15 PM PDT 24
Peak memory 281524 kb
Host smart-71c7c064-61cb-4f38-98e2-b98f4b158fc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092179034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3092179034
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3250370270
Short name T156
Test name
Test status
Simulation time 51086948142 ps
CPU time 326.8 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:59:20 PM PDT 24
Peak memory 316784 kb
Host smart-8cb52726-6359-4702-b56b-f2c0399e5a69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3250370270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3250370270
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2492015157
Short name T36
Test name
Test status
Simulation time 86739856 ps
CPU time 0.94 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 208660 kb
Host smart-487d6380-ee71-4240-8022-6360e29e55c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492015157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2492015157
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3503698372
Short name T29
Test name
Test status
Simulation time 16503672 ps
CPU time 1.25 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:53:56 PM PDT 24
Peak memory 209864 kb
Host smart-3c9278d2-e730-4d42-b369-fed62831bc58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503698372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3503698372
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1082827605
Short name T194
Test name
Test status
Simulation time 258874873 ps
CPU time 12.77 seconds
Started May 14 12:53:43 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 217928 kb
Host smart-831fd71e-2828-4283-b671-acb72323ab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082827605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1082827605
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2208163753
Short name T412
Test name
Test status
Simulation time 1453611099 ps
CPU time 5.09 seconds
Started May 14 12:53:44 PM PDT 24
Finished May 14 12:53:51 PM PDT 24
Peak memory 209600 kb
Host smart-87ed2996-6bb7-4ada-b3df-bd1db0cafb65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208163753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2208163753
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.289220278
Short name T674
Test name
Test status
Simulation time 31523959 ps
CPU time 2.22 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:53:55 PM PDT 24
Peak memory 221676 kb
Host smart-478ae9d2-87b6-4a37-9f1b-2f4131b0ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289220278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.289220278
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2816776181
Short name T432
Test name
Test status
Simulation time 1468889134 ps
CPU time 11.77 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:17 PM PDT 24
Peak memory 218092 kb
Host smart-92e3a351-6b54-4b82-bd03-ce149cffe276
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816776181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2816776181
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2436825905
Short name T332
Test name
Test status
Simulation time 2640440808 ps
CPU time 16.91 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 218040 kb
Host smart-40ba8d93-4f6e-4563-8884-35dabec337c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436825905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2436825905
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1686466267
Short name T579
Test name
Test status
Simulation time 710516169 ps
CPU time 11.76 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:04 PM PDT 24
Peak memory 217912 kb
Host smart-23698cd4-dbec-4508-a468-6c4e94a363d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686466267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1686466267
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.719822203
Short name T835
Test name
Test status
Simulation time 673675082 ps
CPU time 12.67 seconds
Started May 14 12:53:48 PM PDT 24
Finished May 14 12:54:03 PM PDT 24
Peak memory 224736 kb
Host smart-8e3993c5-7d05-466c-b432-cb8946f4ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719822203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.719822203
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4275069711
Short name T770
Test name
Test status
Simulation time 32357065 ps
CPU time 2.21 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:53:54 PM PDT 24
Peak memory 213996 kb
Host smart-6a329734-9a32-49e7-ac27-f425fedf2e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275069711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4275069711
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1509201394
Short name T337
Test name
Test status
Simulation time 2420963079 ps
CPU time 22.59 seconds
Started May 14 12:53:46 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 246444 kb
Host smart-b03c4f5d-9c30-4358-8697-ab3a5ec56378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509201394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1509201394
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1742623841
Short name T34
Test name
Test status
Simulation time 118264266 ps
CPU time 8.06 seconds
Started May 14 12:53:41 PM PDT 24
Finished May 14 12:53:51 PM PDT 24
Peak memory 247440 kb
Host smart-bd8ccb4b-7dd8-4735-891b-2a2f25c08c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742623841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1742623841
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.403390653
Short name T373
Test name
Test status
Simulation time 3576617687 ps
CPU time 136.8 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:56:12 PM PDT 24
Peak memory 283712 kb
Host smart-c88d2c50-b981-41b7-901b-795b80980416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403390653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.403390653
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.819572820
Short name T162
Test name
Test status
Simulation time 22373683486 ps
CPU time 384.33 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 01:00:18 PM PDT 24
Peak memory 300332 kb
Host smart-def66cc5-9349-4d97-8b90-76ae1aad3f2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=819572820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.819572820
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1924698470
Short name T570
Test name
Test status
Simulation time 40996615 ps
CPU time 0.93 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:53:56 PM PDT 24
Peak memory 208804 kb
Host smart-fe4f2423-e24e-444c-900a-05a49e494b70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924698470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1924698470
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4254630552
Short name T417
Test name
Test status
Simulation time 160684380 ps
CPU time 1.05 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:53:54 PM PDT 24
Peak memory 209584 kb
Host smart-04154f51-83b5-49b2-8446-33bee3a955da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254630552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4254630552
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3105880088
Short name T550
Test name
Test status
Simulation time 878607495 ps
CPU time 10.53 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:04 PM PDT 24
Peak memory 217916 kb
Host smart-fd6951e2-a728-4821-aee3-a15fc61d2fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105880088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3105880088
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2787342241
Short name T496
Test name
Test status
Simulation time 714127983 ps
CPU time 16.63 seconds
Started May 14 12:53:58 PM PDT 24
Finished May 14 12:54:18 PM PDT 24
Peak memory 209564 kb
Host smart-84a262b8-6057-4d3f-8f7a-1855ab7503b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787342241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2787342241
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1628831095
Short name T605
Test name
Test status
Simulation time 24394042 ps
CPU time 2.01 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:53:57 PM PDT 24
Peak memory 221420 kb
Host smart-9c6ed5f7-b30f-4bd8-9fe6-ed92cbfd19d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628831095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1628831095
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1805553153
Short name T643
Test name
Test status
Simulation time 564444515 ps
CPU time 11.52 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 217968 kb
Host smart-68410c09-6185-4e63-8e86-e858bb219be1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805553153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1805553153
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2508326377
Short name T648
Test name
Test status
Simulation time 2102249750 ps
CPU time 10.18 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 217928 kb
Host smart-2d8aa3ef-f6cb-4164-8340-2b51df2ce70d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508326377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2508326377
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4020245472
Short name T403
Test name
Test status
Simulation time 884061831 ps
CPU time 9.24 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:02 PM PDT 24
Peak memory 218016 kb
Host smart-b8c5aa48-8c7b-4bc1-a5b0-26340ee5a082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020245472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4020245472
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3972182051
Short name T679
Test name
Test status
Simulation time 509916934 ps
CPU time 11.16 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 226092 kb
Host smart-0eadb5e8-4860-4bca-8cf2-2fd911959271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972182051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3972182051
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.956716017
Short name T548
Test name
Test status
Simulation time 131867394 ps
CPU time 7.51 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:54:03 PM PDT 24
Peak memory 217704 kb
Host smart-b4daf6ab-66b0-4303-868c-40155374cf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956716017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.956716017
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3928572256
Short name T479
Test name
Test status
Simulation time 156508245 ps
CPU time 21.78 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 250880 kb
Host smart-4feeb013-ac8b-46a4-9bf0-96a8622ff443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928572256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3928572256
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1690408861
Short name T65
Test name
Test status
Simulation time 45803353 ps
CPU time 9.3 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 250388 kb
Host smart-249399cc-cf14-4b50-8bd0-ab9d15d0e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690408861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1690408861
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4273472993
Short name T94
Test name
Test status
Simulation time 1682895979 ps
CPU time 45.03 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 251024 kb
Host smart-03714ad4-0557-4a50-be91-fde0a642f5be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273472993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4273472993
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2382252857
Short name T291
Test name
Test status
Simulation time 152704884 ps
CPU time 0.87 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 207924 kb
Host smart-5e25c658-7b0c-41b0-b8cc-c7d1a0085f5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382252857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2382252857
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2562075891
Short name T802
Test name
Test status
Simulation time 13368015 ps
CPU time 1.06 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 209660 kb
Host smart-3f45b1fb-01b7-4815-8db1-b0149a374c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562075891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2562075891
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.284459212
Short name T175
Test name
Test status
Simulation time 973304771 ps
CPU time 16.9 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 225968 kb
Host smart-cae5aee7-d300-4e30-aefb-58e57de1e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284459212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.284459212
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1141482477
Short name T461
Test name
Test status
Simulation time 1993259063 ps
CPU time 13.11 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:54:05 PM PDT 24
Peak memory 216884 kb
Host smart-76fcd062-534f-497f-bdd1-2b08dcaa85df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141482477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1141482477
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.283882302
Short name T650
Test name
Test status
Simulation time 270494030 ps
CPU time 3.51 seconds
Started May 14 12:53:47 PM PDT 24
Finished May 14 12:53:53 PM PDT 24
Peak memory 221928 kb
Host smart-d70dc064-a82c-440d-b4c4-054fe32c367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283882302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.283882302
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1357167391
Short name T302
Test name
Test status
Simulation time 247522042 ps
CPU time 10.7 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 217996 kb
Host smart-e42921e7-1c9a-4d47-9987-f2f199067562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357167391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1357167391
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.116797249
Short name T809
Test name
Test status
Simulation time 1136390785 ps
CPU time 9.29 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 218072 kb
Host smart-db60f9a4-d401-4199-8c92-ec84f7d68f36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116797249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.116797249
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2148019499
Short name T793
Test name
Test status
Simulation time 259215699 ps
CPU time 9.7 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:54:04 PM PDT 24
Peak memory 217960 kb
Host smart-7ed93ec4-aa1e-4293-9882-d9a10a843b9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148019499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2148019499
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2978218425
Short name T671
Test name
Test status
Simulation time 279310768 ps
CPU time 10.29 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 224660 kb
Host smart-c29d7f37-3cf0-4127-b9cd-076a1d4f2483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978218425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2978218425
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.815796448
Short name T811
Test name
Test status
Simulation time 246076622 ps
CPU time 5.02 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:54:01 PM PDT 24
Peak memory 213916 kb
Host smart-b5c01d1c-c8ce-4fd2-afab-c0f4f8e3a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815796448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.815796448
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.145640571
Short name T631
Test name
Test status
Simulation time 236062271 ps
CPU time 25.74 seconds
Started May 14 12:53:48 PM PDT 24
Finished May 14 12:54:16 PM PDT 24
Peak memory 251100 kb
Host smart-f9132ec0-0066-40ab-9568-726325f469a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145640571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.145640571
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2326942114
Short name T588
Test name
Test status
Simulation time 2074144063 ps
CPU time 3.75 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:53:55 PM PDT 24
Peak memory 222056 kb
Host smart-4df64a03-f775-4fc6-b3e5-64c768d54f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326942114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2326942114
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3315497483
Short name T524
Test name
Test status
Simulation time 2786623825 ps
CPU time 89.61 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:55:22 PM PDT 24
Peak memory 250772 kb
Host smart-9efe34b6-e308-4e8a-8ae6-757cd30ccebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315497483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3315497483
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2559782550
Short name T182
Test name
Test status
Simulation time 15538002215 ps
CPU time 346.33 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:59:43 PM PDT 24
Peak memory 316720 kb
Host smart-bd4a99cd-bc70-48f9-b83a-6ba61560814b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2559782550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2559782550
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.13181017
Short name T67
Test name
Test status
Simulation time 63147647 ps
CPU time 1.15 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:53:57 PM PDT 24
Peak memory 212664 kb
Host smart-3aee53cc-77b0-4b03-a095-39b10a9ada69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13181017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctr
l_volatile_unlock_smoke.13181017
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1521430473
Short name T384
Test name
Test status
Simulation time 31200291 ps
CPU time 1.04 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 209596 kb
Host smart-d86c892f-f749-40fa-b55c-f7f4e59dfbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521430473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1521430473
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2829380869
Short name T30
Test name
Test status
Simulation time 2174324549 ps
CPU time 22.88 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:20 PM PDT 24
Peak memory 218072 kb
Host smart-b235d5f6-6c78-4a42-a524-f20dcdb090de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829380869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2829380869
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4121877983
Short name T831
Test name
Test status
Simulation time 995829736 ps
CPU time 5.67 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 209544 kb
Host smart-072b226d-e0ed-41ab-84a9-e70eadd2bf4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121877983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4121877983
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.730233991
Short name T775
Test name
Test status
Simulation time 210299199 ps
CPU time 2.36 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:53:57 PM PDT 24
Peak memory 221636 kb
Host smart-e31f9402-bfe0-4fc0-bf69-21766534abfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730233991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.730233991
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4204522286
Short name T288
Test name
Test status
Simulation time 2028657379 ps
CPU time 17.27 seconds
Started May 14 12:53:55 PM PDT 24
Finished May 14 12:54:16 PM PDT 24
Peak memory 218068 kb
Host smart-1527909e-7668-41c9-9424-3727eacbfbcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204522286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4204522286
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1872218069
Short name T292
Test name
Test status
Simulation time 3619353258 ps
CPU time 11.63 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 218104 kb
Host smart-b829ca05-b7c5-406b-80e2-8fc53236cac3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872218069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1872218069
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2582997383
Short name T287
Test name
Test status
Simulation time 1286666172 ps
CPU time 7.8 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 218096 kb
Host smart-c2d69f35-8023-4658-af29-09244caa74b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582997383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2582997383
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4142279254
Short name T556
Test name
Test status
Simulation time 1280402582 ps
CPU time 9.82 seconds
Started May 14 12:53:58 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 225020 kb
Host smart-9c30befd-98e7-44e1-afb2-54d63daa5873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142279254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4142279254
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3862490606
Short name T438
Test name
Test status
Simulation time 36994766 ps
CPU time 1.97 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 213376 kb
Host smart-2d2b12e8-1633-4810-874d-f3fc6c9504b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862490606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3862490606
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1244138332
Short name T385
Test name
Test status
Simulation time 421078551 ps
CPU time 17.5 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 250944 kb
Host smart-931f0aeb-1730-452c-844a-4fe23966b970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244138332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1244138332
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2821696783
Short name T762
Test name
Test status
Simulation time 82120064 ps
CPU time 7.47 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:05 PM PDT 24
Peak memory 250920 kb
Host smart-ff4967d3-5834-458b-95ea-f187fb363ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821696783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2821696783
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3516091672
Short name T118
Test name
Test status
Simulation time 49421193222 ps
CPU time 212.83 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:57:39 PM PDT 24
Peak memory 267464 kb
Host smart-84176b80-c7c6-4000-bfda-618878cb8081
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516091672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3516091672
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2773776956
Short name T383
Test name
Test status
Simulation time 45594122 ps
CPU time 0.9 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:53:54 PM PDT 24
Peak memory 208628 kb
Host smart-b274aa8a-042a-4d5c-80d8-e6e9cdb39fb4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773776956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2773776956
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1318773346
Short name T108
Test name
Test status
Simulation time 23279346 ps
CPU time 0.98 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:53:59 PM PDT 24
Peak memory 209596 kb
Host smart-2f443138-e58e-49de-9897-827c7bcad82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318773346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1318773346
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3477191474
Short name T540
Test name
Test status
Simulation time 410336816 ps
CPU time 12.83 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 217876 kb
Host smart-b2879bcd-59d5-411c-99c1-71b34a3d14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477191474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3477191474
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4195250656
Short name T22
Test name
Test status
Simulation time 348741503 ps
CPU time 5.12 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 209548 kb
Host smart-05c20963-5765-4bae-9f28-43cc9054076c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195250656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4195250656
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2967333794
Short name T466
Test name
Test status
Simulation time 69852119 ps
CPU time 1.82 seconds
Started May 14 12:53:52 PM PDT 24
Finished May 14 12:53:58 PM PDT 24
Peak memory 221536 kb
Host smart-28c35a92-1333-4cd0-95d1-2be06f9348fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967333794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2967333794
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1831651913
Short name T857
Test name
Test status
Simulation time 1494181148 ps
CPU time 11.86 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 225924 kb
Host smart-9b9ea11d-33a9-48bb-87e2-0e7fb776586c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831651913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1831651913
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1552602249
Short name T732
Test name
Test status
Simulation time 1124881461 ps
CPU time 9.7 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 218044 kb
Host smart-6aae4500-4844-4053-b7eb-ed538f9bb1d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552602249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1552602249
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1126013914
Short name T333
Test name
Test status
Simulation time 928299645 ps
CPU time 9.24 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:54:03 PM PDT 24
Peak memory 217972 kb
Host smart-6d8312ea-8e63-4835-87e6-0bf2823b3bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126013914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1126013914
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.808653552
Short name T223
Test name
Test status
Simulation time 1421421707 ps
CPU time 9.39 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 224860 kb
Host smart-1398020c-14c7-457f-a9c2-d66c571810ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808653552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.808653552
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4162553639
Short name T712
Test name
Test status
Simulation time 897196080 ps
CPU time 3.94 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 217768 kb
Host smart-0969e0f9-5cf8-47d3-968d-659130437d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162553639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4162553639
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1516466821
Short name T818
Test name
Test status
Simulation time 343049804 ps
CPU time 33.28 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:40 PM PDT 24
Peak memory 251000 kb
Host smart-b339a910-1cba-48c2-90d7-f939a5e6fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516466821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1516466821
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2618735372
Short name T505
Test name
Test status
Simulation time 181246188 ps
CPU time 3.21 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 217952 kb
Host smart-a24de01f-2e25-49ac-923f-4371dfde3c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618735372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2618735372
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3781866278
Short name T569
Test name
Test status
Simulation time 36643422825 ps
CPU time 269.52 seconds
Started May 14 12:53:55 PM PDT 24
Finished May 14 12:58:28 PM PDT 24
Peak memory 276348 kb
Host smart-879b556c-b87a-4c01-a85b-bf6d7b8e174a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781866278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3781866278
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1342782681
Short name T45
Test name
Test status
Simulation time 16269993 ps
CPU time 1.03 seconds
Started May 14 12:53:50 PM PDT 24
Finished May 14 12:53:54 PM PDT 24
Peak memory 211588 kb
Host smart-d301a51b-4151-4805-a7c6-c1d69b708188
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342782681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1342782681
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2020097563
Short name T673
Test name
Test status
Simulation time 12879263 ps
CPU time 1.01 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 209588 kb
Host smart-6e11bcee-c81b-4054-b66d-abab0f658e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020097563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2020097563
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2037996340
Short name T367
Test name
Test status
Simulation time 2991244716 ps
CPU time 17.94 seconds
Started May 14 12:53:59 PM PDT 24
Finished May 14 12:54:21 PM PDT 24
Peak memory 226128 kb
Host smart-1649a92d-a83c-4170-bf10-7c4f358a50d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037996340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2037996340
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1269841427
Short name T299
Test name
Test status
Simulation time 508867644 ps
CPU time 2.14 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 209532 kb
Host smart-04129fbd-9320-402b-a35b-d91da4ad43ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269841427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1269841427
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.743492054
Short name T492
Test name
Test status
Simulation time 29387228 ps
CPU time 1.94 seconds
Started May 14 12:53:54 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 221516 kb
Host smart-f0ff491e-571d-4ed7-bd96-dc2d1beca2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743492054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.743492054
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.320730050
Short name T583
Test name
Test status
Simulation time 1685284696 ps
CPU time 16.09 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:21 PM PDT 24
Peak memory 218904 kb
Host smart-9997f867-9360-41b8-93ba-6a8ac5aa8fd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320730050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.320730050
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3808119641
Short name T657
Test name
Test status
Simulation time 1595902864 ps
CPU time 10.92 seconds
Started May 14 12:53:59 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 218004 kb
Host smart-bef13ace-a387-4029-ba37-0e1c263f0fdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808119641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3808119641
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.833082661
Short name T236
Test name
Test status
Simulation time 567580161 ps
CPU time 6.95 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 217832 kb
Host smart-8d530b58-0d6c-4165-b4e1-d3d7b0850043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833082661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.833082661
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2529060499
Short name T225
Test name
Test status
Simulation time 365011697 ps
CPU time 13.44 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:18 PM PDT 24
Peak memory 225972 kb
Host smart-6a7b6cb3-9371-4276-91af-96b19c0befd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529060499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2529060499
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.391921306
Short name T356
Test name
Test status
Simulation time 52244928 ps
CPU time 2.41 seconds
Started May 14 12:53:51 PM PDT 24
Finished May 14 12:53:57 PM PDT 24
Peak memory 213960 kb
Host smart-14efe446-2372-45f2-97f0-a7a7a81e3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391921306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.391921306
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3631098532
Short name T582
Test name
Test status
Simulation time 221691060 ps
CPU time 19.97 seconds
Started May 14 12:53:49 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 250888 kb
Host smart-cfb6b76a-2b4a-4cbe-a05f-87282d50a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631098532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3631098532
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.429210244
Short name T256
Test name
Test status
Simulation time 552903379 ps
CPU time 2.95 seconds
Started May 14 12:53:53 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 222280 kb
Host smart-f04fcec4-5ac9-462a-af87-165803d46fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429210244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.429210244
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2137274461
Short name T19
Test name
Test status
Simulation time 30255319299 ps
CPU time 181.18 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:57:07 PM PDT 24
Peak memory 250896 kb
Host smart-d02ec8e9-9f5d-44ae-9e4c-174164181264
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137274461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2137274461
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2301910954
Short name T875
Test name
Test status
Simulation time 134679350 ps
CPU time 0.95 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 209588 kb
Host smart-d7ad8434-89ef-47a4-922d-9311be54a2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301910954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2301910954
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1972807638
Short name T590
Test name
Test status
Simulation time 302413861 ps
CPU time 11.06 seconds
Started May 14 12:53:57 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 217972 kb
Host smart-1175e441-5924-4395-892d-1fe0f6b6ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972807638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1972807638
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.333358996
Short name T837
Test name
Test status
Simulation time 1006410968 ps
CPU time 7.17 seconds
Started May 14 12:53:57 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 209500 kb
Host smart-eb2ed81a-fff1-4b43-b62b-9406c9178330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333358996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.333358996
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4092287031
Short name T755
Test name
Test status
Simulation time 469602272 ps
CPU time 4.12 seconds
Started May 14 12:53:57 PM PDT 24
Finished May 14 12:54:05 PM PDT 24
Peak memory 221928 kb
Host smart-c2280c21-ee57-4965-a8a6-4d27c1263018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092287031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4092287031
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3696629919
Short name T791
Test name
Test status
Simulation time 990112440 ps
CPU time 11.8 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:16 PM PDT 24
Peak memory 218924 kb
Host smart-0dbd6a53-da06-4a26-afd5-4d1fa7ab5761
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696629919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3696629919
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3629167921
Short name T359
Test name
Test status
Simulation time 312047187 ps
CPU time 10.93 seconds
Started May 14 12:54:05 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 218012 kb
Host smart-ae633f36-8f00-49f3-bddd-37691127cf38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629167921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3629167921
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2759822319
Short name T784
Test name
Test status
Simulation time 449021634 ps
CPU time 10.3 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:16 PM PDT 24
Peak memory 217944 kb
Host smart-60d2f335-2ae7-43d2-8d58-3c271f85ee3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759822319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2759822319
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1471887343
Short name T681
Test name
Test status
Simulation time 2568050067 ps
CPU time 6.38 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 224656 kb
Host smart-05f358fd-7b58-4686-a38d-83571cb93e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471887343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1471887343
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3395555820
Short name T819
Test name
Test status
Simulation time 327232209 ps
CPU time 3.34 seconds
Started May 14 12:53:55 PM PDT 24
Finished May 14 12:54:02 PM PDT 24
Peak memory 217888 kb
Host smart-96ec4968-8a4d-4429-9106-d1460ff2f059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395555820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3395555820
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3746365471
Short name T378
Test name
Test status
Simulation time 282696365 ps
CPU time 35.86 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:41 PM PDT 24
Peak memory 246208 kb
Host smart-e821f536-c189-44ef-a9c3-4081effb4520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746365471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3746365471
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2399233753
Short name T268
Test name
Test status
Simulation time 415170525 ps
CPU time 3.86 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 222112 kb
Host smart-2b3d3dd7-b918-492a-a536-4823b91d6705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399233753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2399233753
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2197066262
Short name T553
Test name
Test status
Simulation time 59605880505 ps
CPU time 452.82 seconds
Started May 14 12:53:59 PM PDT 24
Finished May 14 01:01:35 PM PDT 24
Peak memory 283728 kb
Host smart-00af880b-ede0-4730-b64b-65113320b92d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197066262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2197066262
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1739932010
Short name T565
Test name
Test status
Simulation time 40707277 ps
CPU time 0.77 seconds
Started May 14 12:53:59 PM PDT 24
Finished May 14 12:54:03 PM PDT 24
Peak memory 208584 kb
Host smart-e9a23321-a1e8-4ba5-985a-2e076539f330
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739932010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1739932010
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2152239942
Short name T559
Test name
Test status
Simulation time 16721903 ps
CPU time 1.03 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 209584 kb
Host smart-6863d31d-36f0-4de2-864d-4ce58e3596b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152239942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2152239942
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2487247072
Short name T847
Test name
Test status
Simulation time 1629118115 ps
CPU time 12.02 seconds
Started May 14 12:53:57 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 225988 kb
Host smart-4e914868-1229-437d-a954-98f7c7230003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487247072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2487247072
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2723740296
Short name T551
Test name
Test status
Simulation time 98193705 ps
CPU time 1.17 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 209476 kb
Host smart-521b87c0-0776-4b52-ad58-9a0121404537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723740296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2723740296
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.374709481
Short name T400
Test name
Test status
Simulation time 32878169 ps
CPU time 1.41 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 221152 kb
Host smart-da133a0f-e2c5-4010-b2c6-c818f59d955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374709481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.374709481
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.540069685
Short name T675
Test name
Test status
Simulation time 938980326 ps
CPU time 13.01 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:20 PM PDT 24
Peak memory 218960 kb
Host smart-1481aad9-fccd-4759-b429-cb596d65e566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540069685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.540069685
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1245829746
Short name T725
Test name
Test status
Simulation time 1445673425 ps
CPU time 12.1 seconds
Started May 14 12:54:04 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 217888 kb
Host smart-dc5c7f62-401d-4b93-9aac-7f5a1b3a8dfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245829746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1245829746
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3947175232
Short name T848
Test name
Test status
Simulation time 776668569 ps
CPU time 15.02 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 217956 kb
Host smart-89110bf5-9a90-469c-ad9c-1c7bdc30a55f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947175232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3947175232
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3785557122
Short name T798
Test name
Test status
Simulation time 324717008 ps
CPU time 12.08 seconds
Started May 14 12:53:59 PM PDT 24
Finished May 14 12:54:14 PM PDT 24
Peak memory 225400 kb
Host smart-5334bb0b-8a0f-4c11-93ac-aa1758b16392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785557122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3785557122
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1384501163
Short name T827
Test name
Test status
Simulation time 58238191 ps
CPU time 1.38 seconds
Started May 14 12:53:56 PM PDT 24
Finished May 14 12:54:01 PM PDT 24
Peak memory 213548 kb
Host smart-ab9e2aab-0e6c-4d9e-a644-7c07063924ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384501163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1384501163
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.4047130030
Short name T519
Test name
Test status
Simulation time 246670918 ps
CPU time 27.15 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:33 PM PDT 24
Peak memory 251028 kb
Host smart-5a64fab2-66f0-4be1-b22e-7da94a67cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047130030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.4047130030
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3763576000
Short name T517
Test name
Test status
Simulation time 677344270 ps
CPU time 7.12 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 250976 kb
Host smart-74499b12-4334-4dda-9b39-c1de9a3d9590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763576000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3763576000
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1486949476
Short name T483
Test name
Test status
Simulation time 2187545545 ps
CPU time 33.66 seconds
Started May 14 12:53:59 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 251032 kb
Host smart-cabe5733-ebb9-486e-a312-5ebe42542739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486949476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1486949476
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2243098075
Short name T399
Test name
Test status
Simulation time 83219505 ps
CPU time 0.87 seconds
Started May 14 12:54:06 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 211488 kb
Host smart-d75404af-0bbb-4b41-b5f3-667433bd8c4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243098075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2243098075
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2282948661
Short name T177
Test name
Test status
Simulation time 86028426 ps
CPU time 0.87 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 209520 kb
Host smart-d9ec208e-d61b-444e-a22f-34ceeeb5aa42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282948661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2282948661
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3397710642
Short name T726
Test name
Test status
Simulation time 465275746 ps
CPU time 13.47 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 217992 kb
Host smart-2a936202-887d-49a2-ad74-b8d7d747938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397710642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3397710642
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.4061433616
Short name T797
Test name
Test status
Simulation time 444973515 ps
CPU time 12.4 seconds
Started May 14 12:53:59 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 217268 kb
Host smart-df129bff-22e2-4c4c-a73c-d20f11e33bfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061433616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.4061433616
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3800906540
Short name T851
Test name
Test status
Simulation time 327577273 ps
CPU time 4.72 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 221912 kb
Host smart-1a661c7c-076c-4924-84cd-a6b7a31259f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800906540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3800906540
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1940529714
Short name T511
Test name
Test status
Simulation time 289951586 ps
CPU time 9.57 seconds
Started May 14 12:54:12 PM PDT 24
Finished May 14 12:54:22 PM PDT 24
Peak memory 218948 kb
Host smart-1c7c8093-2ff9-4534-87ed-8a5dc15bed24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940529714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1940529714
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1804626665
Short name T318
Test name
Test status
Simulation time 813237097 ps
CPU time 10.74 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:17 PM PDT 24
Peak memory 217980 kb
Host smart-ab818035-46b1-4919-ab9b-7e4d81b387a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804626665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1804626665
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1644878554
Short name T596
Test name
Test status
Simulation time 3104277138 ps
CPU time 8.76 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:14 PM PDT 24
Peak memory 218052 kb
Host smart-fb1927a8-1b82-4ab3-800d-f636fa2840a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644878554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1644878554
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4196474199
Short name T35
Test name
Test status
Simulation time 856669216 ps
CPU time 9.38 seconds
Started May 14 12:53:57 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 224940 kb
Host smart-1efe27bc-f3a9-4e63-8234-40f279743d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196474199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4196474199
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1071459835
Short name T421
Test name
Test status
Simulation time 15701800 ps
CPU time 1 seconds
Started May 14 12:53:56 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 211880 kb
Host smart-16681e08-e24d-470d-b571-38108c7aa7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071459835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1071459835
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2379111921
Short name T678
Test name
Test status
Simulation time 1138983618 ps
CPU time 29.51 seconds
Started May 14 12:53:58 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 249088 kb
Host smart-1fb0f193-99cd-47fd-9687-c5e335f531d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379111921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2379111921
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.4293217842
Short name T453
Test name
Test status
Simulation time 100825378 ps
CPU time 6.93 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 246848 kb
Host smart-9e446baa-7ef0-4eaa-bc5b-fdc7b4b975a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293217842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4293217842
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.909392735
Short name T668
Test name
Test status
Simulation time 51054998076 ps
CPU time 330.55 seconds
Started May 14 12:53:58 PM PDT 24
Finished May 14 12:59:32 PM PDT 24
Peak memory 251140 kb
Host smart-c0f6c4a7-28c4-41d0-91d2-a8e7bf8279af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909392735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.909392735
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4175073961
Short name T37
Test name
Test status
Simulation time 51244919 ps
CPU time 0.78 seconds
Started May 14 12:54:04 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 208624 kb
Host smart-cf28bdd2-6881-42af-a2fe-5bec00d252bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175073961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4175073961
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.4071182337
Short name T620
Test name
Test status
Simulation time 17958269 ps
CPU time 1.09 seconds
Started May 14 12:52:40 PM PDT 24
Finished May 14 12:52:42 PM PDT 24
Peak memory 209520 kb
Host smart-0eb0fe54-93d5-4bb4-bdaf-8d74c3b06c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071182337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.4071182337
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3607672455
Short name T722
Test name
Test status
Simulation time 33704849 ps
CPU time 0.82 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:29 PM PDT 24
Peak memory 209404 kb
Host smart-36e2ac70-1699-4eeb-bb09-0ea0b0459d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607672455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3607672455
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1107630879
Short name T357
Test name
Test status
Simulation time 5022239755 ps
CPU time 13.69 seconds
Started May 14 12:52:27 PM PDT 24
Finished May 14 12:52:43 PM PDT 24
Peak memory 218228 kb
Host smart-fef26b19-5973-4080-9972-5bfcd4ac34a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107630879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1107630879
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2461312903
Short name T185
Test name
Test status
Simulation time 666218341 ps
CPU time 9.15 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:52:47 PM PDT 24
Peak memory 217124 kb
Host smart-89192acf-6305-4ea3-a52f-7f38298931f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461312903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2461312903
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.932358072
Short name T584
Test name
Test status
Simulation time 5422002545 ps
CPU time 28.83 seconds
Started May 14 12:52:40 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 218828 kb
Host smart-b77b54f1-0384-435a-97dc-d02fc0ba793f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932358072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.932358072
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3711068498
Short name T814
Test name
Test status
Simulation time 1036888694 ps
CPU time 7.05 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:45 PM PDT 24
Peak memory 217808 kb
Host smart-b9fd45d9-8186-4ec6-9ed0-022ccda75297
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711068498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
711068498
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2772986463
Short name T344
Test name
Test status
Simulation time 564638078 ps
CPU time 8.99 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:52:47 PM PDT 24
Peak memory 217936 kb
Host smart-4c46226c-afc0-4fd0-97f6-76efa03a3332
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772986463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2772986463
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1456962097
Short name T401
Test name
Test status
Simulation time 4058179281 ps
CPU time 27.11 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:53:06 PM PDT 24
Peak memory 213924 kb
Host smart-4614dfb3-4a80-415f-9491-81a56d001ba6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456962097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1456962097
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1903783898
Short name T493
Test name
Test status
Simulation time 75693959 ps
CPU time 1.74 seconds
Started May 14 12:52:30 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 212500 kb
Host smart-90cfba03-aa29-4eca-9ebf-c9da4c9cf97a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903783898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1903783898
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.774373208
Short name T635
Test name
Test status
Simulation time 3734804061 ps
CPU time 52.45 seconds
Started May 14 12:52:28 PM PDT 24
Finished May 14 12:53:22 PM PDT 24
Peak memory 277040 kb
Host smart-1111ad69-049d-43af-a243-ec440dae8630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774373208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.774373208
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.144858411
Short name T546
Test name
Test status
Simulation time 779894806 ps
CPU time 13.18 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:51 PM PDT 24
Peak memory 226400 kb
Host smart-93e5c6bb-4637-42b4-97d0-874f7429087a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144858411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.144858411
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4064361605
Short name T687
Test name
Test status
Simulation time 351074354 ps
CPU time 3.35 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:31 PM PDT 24
Peak memory 222008 kb
Host smart-23f49057-23ee-437d-9a49-e0bfbd7221c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064361605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4064361605
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1525347108
Short name T197
Test name
Test status
Simulation time 2444646451 ps
CPU time 10.12 seconds
Started May 14 12:52:28 PM PDT 24
Finished May 14 12:52:40 PM PDT 24
Peak memory 217824 kb
Host smart-579a8d90-38b9-4d1b-a663-c015bfce1ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525347108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1525347108
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.484688387
Short name T55
Test name
Test status
Simulation time 219109017 ps
CPU time 35.78 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:53:14 PM PDT 24
Peak memory 268652 kb
Host smart-afba8eb1-f562-4f32-a1ab-7e4382897531
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484688387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.484688387
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1437752377
Short name T506
Test name
Test status
Simulation time 2878311889 ps
CPU time 9.19 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:47 PM PDT 24
Peak memory 217944 kb
Host smart-3f45ce44-36ea-454d-abcd-1370459de438
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437752377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1437752377
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3691253848
Short name T289
Test name
Test status
Simulation time 1495089711 ps
CPU time 18.35 seconds
Started May 14 12:52:35 PM PDT 24
Finished May 14 12:52:54 PM PDT 24
Peak memory 218124 kb
Host smart-190c1c1b-7ef9-4146-8768-58904c4e8df7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691253848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3691253848
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1372148180
Short name T290
Test name
Test status
Simulation time 540421955 ps
CPU time 14.66 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:52 PM PDT 24
Peak memory 217992 kb
Host smart-3e0f6f6d-3e44-40c2-a93a-dbadaaf72796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372148180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
372148180
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.178088944
Short name T224
Test name
Test status
Simulation time 190406567 ps
CPU time 6.47 seconds
Started May 14 12:52:25 PM PDT 24
Finished May 14 12:52:34 PM PDT 24
Peak memory 224400 kb
Host smart-f6f31d40-a368-4350-9ec3-7dad3e814d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178088944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.178088944
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3964881037
Short name T231
Test name
Test status
Simulation time 41914851 ps
CPU time 1.89 seconds
Started May 14 12:52:32 PM PDT 24
Finished May 14 12:52:35 PM PDT 24
Peak memory 213552 kb
Host smart-6416de42-395a-4bbc-bdf5-720a4d67a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964881037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3964881037
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1377208008
Short name T392
Test name
Test status
Simulation time 207141542 ps
CPU time 18.28 seconds
Started May 14 12:52:26 PM PDT 24
Finished May 14 12:52:47 PM PDT 24
Peak memory 246256 kb
Host smart-7b979db1-532c-44ce-8dc6-1c6f98891b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377208008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1377208008
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3083025371
Short name T777
Test name
Test status
Simulation time 99586334 ps
CPU time 7.66 seconds
Started May 14 12:52:24 PM PDT 24
Finished May 14 12:52:33 PM PDT 24
Peak memory 250808 kb
Host smart-b5a10ee9-9296-46e0-94e7-3f11f119c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083025371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3083025371
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2621688446
Short name T719
Test name
Test status
Simulation time 7053902443 ps
CPU time 199.2 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:55:57 PM PDT 24
Peak memory 283256 kb
Host smart-c0e72a58-5fbb-46a9-94cc-137307e84c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621688446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2621688446
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2832651113
Short name T792
Test name
Test status
Simulation time 31280231 ps
CPU time 1.04 seconds
Started May 14 12:52:29 PM PDT 24
Finished May 14 12:52:31 PM PDT 24
Peak memory 211656 kb
Host smart-f8056f1e-7e25-4c95-952c-3031a4729cad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832651113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2832651113
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3072696106
Short name T530
Test name
Test status
Simulation time 162354830 ps
CPU time 1.64 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:06 PM PDT 24
Peak memory 209584 kb
Host smart-08563409-bfa9-4ea9-952d-3c59e4bd251e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072696106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3072696106
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.671690813
Short name T654
Test name
Test status
Simulation time 409013416 ps
CPU time 10.14 seconds
Started May 14 12:54:05 PM PDT 24
Finished May 14 12:54:18 PM PDT 24
Peak memory 217808 kb
Host smart-fdc7fbd8-7911-4026-bcf7-8a395f6fae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671690813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.671690813
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3367056616
Short name T394
Test name
Test status
Simulation time 637050251 ps
CPU time 2.72 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 209612 kb
Host smart-147aca42-f06f-439c-bd0e-2c04f3544560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367056616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3367056616
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2324078105
Short name T273
Test name
Test status
Simulation time 782671974 ps
CPU time 3.26 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:10 PM PDT 24
Peak memory 221640 kb
Host smart-7f87a38c-7cf7-45e4-9513-3e30f174d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324078105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2324078105
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.579283932
Short name T641
Test name
Test status
Simulation time 1900293331 ps
CPU time 12.66 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:17 PM PDT 24
Peak memory 218132 kb
Host smart-eae1ec80-52ca-472c-b051-e4fdd066bbad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579283932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.579283932
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.4015146852
Short name T443
Test name
Test status
Simulation time 502310911 ps
CPU time 17.46 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:22 PM PDT 24
Peak memory 218028 kb
Host smart-d60c9979-19f3-4582-8785-124d5a69a2a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015146852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.4015146852
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3839145850
Short name T316
Test name
Test status
Simulation time 1926122429 ps
CPU time 8.33 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 218016 kb
Host smart-ba1ba3c4-52fc-43d8-8945-e3aab215f07d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839145850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3839145850
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1025000910
Short name T684
Test name
Test status
Simulation time 264207640 ps
CPU time 11.06 seconds
Started May 14 12:54:04 PM PDT 24
Finished May 14 12:54:18 PM PDT 24
Peak memory 224856 kb
Host smart-269039f8-7f60-49fc-a069-795355d36b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025000910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1025000910
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4076620349
Short name T343
Test name
Test status
Simulation time 417545932 ps
CPU time 2.82 seconds
Started May 14 12:54:00 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 214540 kb
Host smart-398ebbb3-e98b-4950-a765-c048d453354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076620349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4076620349
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2107485757
Short name T179
Test name
Test status
Simulation time 707344395 ps
CPU time 19.11 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:26 PM PDT 24
Peak memory 251008 kb
Host smart-252f6da6-5153-4519-ab62-1edd729244e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107485757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2107485757
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3660204207
Short name T692
Test name
Test status
Simulation time 73792114 ps
CPU time 6.47 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 250596 kb
Host smart-4a05f252-e115-42f5-a2d4-895dbc6823f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660204207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3660204207
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1086501510
Short name T615
Test name
Test status
Simulation time 25795721512 ps
CPU time 447.93 seconds
Started May 14 12:54:01 PM PDT 24
Finished May 14 01:01:33 PM PDT 24
Peak memory 314604 kb
Host smart-7c1335e2-4349-4a8d-8c42-12f9f24b3036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086501510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1086501510
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.564074181
Short name T321
Test name
Test status
Simulation time 114236233 ps
CPU time 0.98 seconds
Started May 14 12:54:03 PM PDT 24
Finished May 14 12:54:07 PM PDT 24
Peak memory 211612 kb
Host smart-6783990e-fa1c-4204-8d3c-9ca028af82b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564074181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.564074181
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2843500450
Short name T239
Test name
Test status
Simulation time 26729847 ps
CPU time 1.02 seconds
Started May 14 12:54:16 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 209636 kb
Host smart-cccc4d8b-5e9a-4a85-9e06-d59895f5546e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843500450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2843500450
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2826973263
Short name T623
Test name
Test status
Simulation time 1161698375 ps
CPU time 15.88 seconds
Started May 14 12:54:18 PM PDT 24
Finished May 14 12:54:36 PM PDT 24
Peak memory 217992 kb
Host smart-1a371451-4411-47eb-8f38-12bfae7d6df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826973263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2826973263
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3084589088
Short name T709
Test name
Test status
Simulation time 645423530 ps
CPU time 7.09 seconds
Started May 14 12:54:05 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 217036 kb
Host smart-d0ab718b-5586-4a0b-8920-cd52ca9aede6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084589088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3084589088
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.917866453
Short name T800
Test name
Test status
Simulation time 25023222 ps
CPU time 1.76 seconds
Started May 14 12:54:07 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 221404 kb
Host smart-928defab-b072-4900-bb17-ed907c202be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917866453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.917866453
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2001116910
Short name T191
Test name
Test status
Simulation time 1744201072 ps
CPU time 8.34 seconds
Started May 14 12:54:25 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 217984 kb
Host smart-64c2e70e-7715-4fa9-8e40-671a01968d7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001116910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2001116910
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3986948507
Short name T859
Test name
Test status
Simulation time 1551281678 ps
CPU time 11.13 seconds
Started May 14 12:54:07 PM PDT 24
Finished May 14 12:54:21 PM PDT 24
Peak memory 218048 kb
Host smart-8faefebb-9ddf-4918-a9bb-7cb13f0dc027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986948507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3986948507
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3217789689
Short name T303
Test name
Test status
Simulation time 11325440014 ps
CPU time 11.15 seconds
Started May 14 12:54:14 PM PDT 24
Finished May 14 12:54:27 PM PDT 24
Peak memory 218088 kb
Host smart-0695d096-40a1-4fef-8fa8-d373b5df8c71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217789689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3217789689
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3938732675
Short name T659
Test name
Test status
Simulation time 284337680 ps
CPU time 11.51 seconds
Started May 14 12:54:09 PM PDT 24
Finished May 14 12:54:22 PM PDT 24
Peak memory 224996 kb
Host smart-2642fe27-645e-4872-b36b-19916f92fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938732675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3938732675
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2573832914
Short name T282
Test name
Test status
Simulation time 110384715 ps
CPU time 5.03 seconds
Started May 14 12:54:02 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 217728 kb
Host smart-e0871cb5-a5e9-4958-b8b1-36b0e843ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573832914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2573832914
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1186046886
Short name T841
Test name
Test status
Simulation time 2340095330 ps
CPU time 38.35 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:54:55 PM PDT 24
Peak memory 251052 kb
Host smart-6c1cb88a-9406-4520-a040-3bfd1d77bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186046886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1186046886
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.426224804
Short name T283
Test name
Test status
Simulation time 90335399 ps
CPU time 10.49 seconds
Started May 14 12:54:09 PM PDT 24
Finished May 14 12:54:21 PM PDT 24
Peak memory 250868 kb
Host smart-bdd1ca0f-3e7f-48c7-9f6d-714d2c66e725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426224804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.426224804
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.965249663
Short name T714
Test name
Test status
Simulation time 15608942711 ps
CPU time 473.64 seconds
Started May 14 12:54:18 PM PDT 24
Finished May 14 01:02:14 PM PDT 24
Peak memory 271788 kb
Host smart-c2994661-9344-48b8-9326-9826d05a59dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965249663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.965249663
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.795208467
Short name T160
Test name
Test status
Simulation time 318383876707 ps
CPU time 665.78 seconds
Started May 14 12:54:18 PM PDT 24
Finished May 14 01:05:26 PM PDT 24
Peak memory 300248 kb
Host smart-b93c08bd-9b5f-4d07-a796-3cc121b73821
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=795208467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.795208467
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.869571750
Short name T84
Test name
Test status
Simulation time 14940928 ps
CPU time 1.23 seconds
Started May 14 12:54:08 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 212888 kb
Host smart-167074a4-5152-474a-8258-2004caff6dab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869571750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.869571750
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3194804448
Short name T626
Test name
Test status
Simulation time 43435646 ps
CPU time 1.18 seconds
Started May 14 12:54:06 PM PDT 24
Finished May 14 12:54:10 PM PDT 24
Peak memory 209548 kb
Host smart-e78cfa0d-ecc7-4f59-b990-f5a0ddc3d5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194804448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3194804448
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2307893053
Short name T728
Test name
Test status
Simulation time 1460831781 ps
CPU time 16.11 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 217948 kb
Host smart-c2f15118-f2be-449a-8012-1d29e82bc9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307893053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2307893053
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.402715467
Short name T349
Test name
Test status
Simulation time 303420058 ps
CPU time 2.15 seconds
Started May 14 12:54:06 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 216852 kb
Host smart-a23f3bc6-d4b0-4b5b-9418-302e661d42e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402715467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.402715467
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1398465904
Short name T743
Test name
Test status
Simulation time 108451855 ps
CPU time 1.99 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 221688 kb
Host smart-cc84cb19-9977-4731-9c59-d28e02c3e945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398465904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1398465904
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1760820489
Short name T33
Test name
Test status
Simulation time 343597626 ps
CPU time 14.61 seconds
Started May 14 12:54:06 PM PDT 24
Finished May 14 12:54:23 PM PDT 24
Peak memory 226092 kb
Host smart-42229118-44dc-419a-b5db-63a10c206f3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760820489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1760820489
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3418381073
Short name T248
Test name
Test status
Simulation time 288063702 ps
CPU time 10.08 seconds
Started May 14 12:54:12 PM PDT 24
Finished May 14 12:54:23 PM PDT 24
Peak memory 217956 kb
Host smart-1cd8bbfe-42a0-47b0-a1d2-d70b11882cbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418381073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3418381073
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1973915129
Short name T501
Test name
Test status
Simulation time 300725843 ps
CPU time 12.05 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:54:28 PM PDT 24
Peak memory 217912 kb
Host smart-18eae455-32ad-430b-a029-9ed3fe4efece
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973915129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1973915129
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2561621380
Short name T535
Test name
Test status
Simulation time 395937039 ps
CPU time 14.4 seconds
Started May 14 12:54:07 PM PDT 24
Finished May 14 12:54:24 PM PDT 24
Peak memory 224900 kb
Host smart-9f56e88e-6e74-42e8-a4fb-ef4acc7485e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561621380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2561621380
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.877555483
Short name T685
Test name
Test status
Simulation time 232636204 ps
CPU time 2.45 seconds
Started May 14 12:54:09 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 213568 kb
Host smart-69f4e27d-21a6-48b0-8ac3-96c21bdd3dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877555483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.877555483
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3301859004
Short name T730
Test name
Test status
Simulation time 1293327052 ps
CPU time 30.08 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:54:47 PM PDT 24
Peak memory 246560 kb
Host smart-1b76e012-4415-44ad-ad3e-96cdaf947a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301859004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3301859004
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3547911020
Short name T342
Test name
Test status
Simulation time 281993944 ps
CPU time 7.34 seconds
Started May 14 12:54:06 PM PDT 24
Finished May 14 12:54:16 PM PDT 24
Peak memory 251032 kb
Host smart-8ac94665-2b8e-41c3-a6a6-74984b5e2606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547911020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3547911020
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.4137778464
Short name T57
Test name
Test status
Simulation time 22272488650 ps
CPU time 193.26 seconds
Started May 14 12:54:06 PM PDT 24
Finished May 14 12:57:22 PM PDT 24
Peak memory 283804 kb
Host smart-af181068-8a54-4088-a2d3-d0ef551f06d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137778464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.4137778464
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2763245056
Short name T544
Test name
Test status
Simulation time 32286338 ps
CPU time 0.96 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:54:17 PM PDT 24
Peak memory 211572 kb
Host smart-714dfbd1-d248-4384-951f-af946c3156d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763245056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2763245056
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2886672408
Short name T664
Test name
Test status
Simulation time 30074935 ps
CPU time 1.09 seconds
Started May 14 12:54:13 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 209604 kb
Host smart-35905303-5add-4414-a6e6-709a82996a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886672408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2886672408
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.181197642
Short name T381
Test name
Test status
Simulation time 233076967 ps
CPU time 8.52 seconds
Started May 14 12:54:07 PM PDT 24
Finished May 14 12:54:18 PM PDT 24
Peak memory 217928 kb
Host smart-aaf80220-ae7c-4db8-a11d-36ad6d1f15e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181197642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.181197642
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1956000091
Short name T352
Test name
Test status
Simulation time 1957367505 ps
CPU time 3.5 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:54:20 PM PDT 24
Peak memory 209340 kb
Host smart-a96dce31-988d-4dd6-899e-8cf7f60b1c57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956000091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1956000091
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.375781621
Short name T331
Test name
Test status
Simulation time 22023363 ps
CPU time 1.41 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:24 PM PDT 24
Peak memory 221168 kb
Host smart-2b2092cb-6ab1-4fda-b524-e43ba5de53d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375781621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.375781621
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3899270886
Short name T747
Test name
Test status
Simulation time 506286373 ps
CPU time 10.45 seconds
Started May 14 12:54:13 PM PDT 24
Finished May 14 12:54:24 PM PDT 24
Peak memory 217996 kb
Host smart-dceaf67a-1453-440e-9e1b-48e757264a8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899270886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3899270886
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.127623899
Short name T534
Test name
Test status
Simulation time 973854089 ps
CPU time 11.1 seconds
Started May 14 12:54:14 PM PDT 24
Finished May 14 12:54:26 PM PDT 24
Peak memory 218028 kb
Host smart-49a51941-6c10-4349-8e49-677ab69d8819
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127623899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.127623899
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2449304936
Short name T574
Test name
Test status
Simulation time 837367865 ps
CPU time 10.19 seconds
Started May 14 12:54:17 PM PDT 24
Finished May 14 12:54:29 PM PDT 24
Peak memory 225088 kb
Host smart-7f74f7bc-f9b8-4bd5-a519-bae68ade243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449304936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2449304936
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2925022992
Short name T62
Test name
Test status
Simulation time 42985076 ps
CPU time 1.66 seconds
Started May 14 12:54:08 PM PDT 24
Finished May 14 12:54:12 PM PDT 24
Peak memory 213704 kb
Host smart-150c5b37-ade5-4088-91c2-2bcf7a9e547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925022992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2925022992
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4133545754
Short name T713
Test name
Test status
Simulation time 238111494 ps
CPU time 22.44 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 251012 kb
Host smart-a89d6713-4c91-48cd-92f8-c6f139fa2a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133545754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4133545754
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3857703359
Short name T512
Test name
Test status
Simulation time 225950264 ps
CPU time 5.93 seconds
Started May 14 12:54:21 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 250404 kb
Host smart-346f4677-65b4-475c-bce9-c6fe8751fbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857703359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3857703359
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2580931176
Short name T628
Test name
Test status
Simulation time 40807634730 ps
CPU time 75.19 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:55:32 PM PDT 24
Peak memory 273104 kb
Host smart-0c7f323e-b08e-41ae-987e-5c43c7654bf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580931176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2580931176
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3564872856
Short name T285
Test name
Test status
Simulation time 42287353 ps
CPU time 0.93 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:24 PM PDT 24
Peak memory 208768 kb
Host smart-4e4c7709-bc4e-4030-a610-46df7a09be7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564872856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3564872856
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1874531317
Short name T488
Test name
Test status
Simulation time 16722712 ps
CPU time 1.07 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:28 PM PDT 24
Peak memory 209416 kb
Host smart-bec2500e-1298-4645-9d3b-0a913f278ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874531317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1874531317
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2177077653
Short name T474
Test name
Test status
Simulation time 376623992 ps
CPU time 14.08 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:41 PM PDT 24
Peak memory 217948 kb
Host smart-f3e23dd7-4d9e-428a-99b6-d42daf3b6ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177077653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2177077653
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.853402423
Short name T487
Test name
Test status
Simulation time 841664778 ps
CPU time 8.97 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 209560 kb
Host smart-cff3a2c7-ada3-40e8-9640-1924ff160f59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853402423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.853402423
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3250037287
Short name T853
Test name
Test status
Simulation time 89380291 ps
CPU time 3.65 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:26 PM PDT 24
Peak memory 222056 kb
Host smart-6b17c6da-8648-4dfd-919c-851f8d02ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250037287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3250037287
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4278188493
Short name T694
Test name
Test status
Simulation time 1245068752 ps
CPU time 12.97 seconds
Started May 14 12:54:17 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 218032 kb
Host smart-e45c02ef-1718-4283-847b-9518267eeb71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278188493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4278188493
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4107235882
Short name T785
Test name
Test status
Simulation time 2040425405 ps
CPU time 19.87 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:47 PM PDT 24
Peak memory 218028 kb
Host smart-d281369b-5038-47df-8b9b-18ce47e49cf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107235882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4107235882
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1442759883
Short name T562
Test name
Test status
Simulation time 425954623 ps
CPU time 12.47 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 217928 kb
Host smart-65b7ce73-fbec-4de1-af54-8fee89a9e1b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442759883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1442759883
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1061337670
Short name T817
Test name
Test status
Simulation time 812291518 ps
CPU time 10.08 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 225276 kb
Host smart-43b9819c-a69c-41b1-b9d4-a5b288d25683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061337670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1061337670
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1825841372
Short name T768
Test name
Test status
Simulation time 36954280 ps
CPU time 1.29 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:24 PM PDT 24
Peak memory 218232 kb
Host smart-c15aeeea-1064-4ef7-95b9-4f7da074e05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825841372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1825841372
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3510309463
Short name T781
Test name
Test status
Simulation time 234280805 ps
CPU time 22.88 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 251024 kb
Host smart-0561b8e2-69d1-4e45-a37c-6bc3a5567060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510309463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3510309463
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.38200009
Short name T264
Test name
Test status
Simulation time 73471965 ps
CPU time 6.99 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:33 PM PDT 24
Peak memory 247124 kb
Host smart-3406218c-157f-4514-9c08-cb162ad75157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38200009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.38200009
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2971328565
Short name T522
Test name
Test status
Simulation time 4055449088 ps
CPU time 137.17 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:56:46 PM PDT 24
Peak memory 275760 kb
Host smart-d32b67c4-cd00-41a3-9ac4-3955020c3952
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971328565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2971328565
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.250856030
Short name T170
Test name
Test status
Simulation time 34159944596 ps
CPU time 521.26 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 01:03:17 PM PDT 24
Peak memory 300012 kb
Host smart-1de381c8-9391-4c53-9650-7d8fb932646a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=250856030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.250856030
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3511545107
Short name T498
Test name
Test status
Simulation time 14786602 ps
CPU time 0.95 seconds
Started May 14 12:54:07 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 208696 kb
Host smart-9c395910-22e3-4d55-862d-b01d8327b3dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511545107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3511545107
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3218529233
Short name T272
Test name
Test status
Simulation time 114239859 ps
CPU time 0.91 seconds
Started May 14 12:54:16 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 209664 kb
Host smart-55c3f037-51d9-4869-8180-2de1789cef49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218529233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3218529233
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1296002052
Short name T467
Test name
Test status
Simulation time 2449731288 ps
CPU time 18.21 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:50 PM PDT 24
Peak memory 219024 kb
Host smart-38e7ea5b-ed29-480f-83f4-b876b7b6411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296002052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1296002052
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.660251267
Short name T26
Test name
Test status
Simulation time 988082050 ps
CPU time 4.32 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 209564 kb
Host smart-f0121f99-2fb8-4969-ab09-2579976a1c88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660251267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.660251267
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2197477800
Short name T660
Test name
Test status
Simulation time 33407538 ps
CPU time 2.33 seconds
Started May 14 12:54:25 PM PDT 24
Finished May 14 12:54:32 PM PDT 24
Peak memory 221760 kb
Host smart-042e4956-e542-4bc9-9af1-c25fb2eb64c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197477800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2197477800
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.187467741
Short name T595
Test name
Test status
Simulation time 357256906 ps
CPU time 15.01 seconds
Started May 14 12:54:21 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 218900 kb
Host smart-77a29132-5ccf-4b0d-901d-fa6778a59118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187467741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.187467741
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3842832389
Short name T426
Test name
Test status
Simulation time 715204459 ps
CPU time 9.88 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 218028 kb
Host smart-5826f5f0-4b58-48a6-a769-7519919e87c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842832389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3842832389
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.855322509
Short name T445
Test name
Test status
Simulation time 363555635 ps
CPU time 8.72 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 217892 kb
Host smart-54171ab1-f550-4fc1-92af-f2edacd0f18d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855322509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.855322509
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2598097673
Short name T477
Test name
Test status
Simulation time 231926874 ps
CPU time 6.65 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 224860 kb
Host smart-459c588d-79e8-499c-9f0b-1576fb7c2088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598097673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2598097673
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4139450731
Short name T690
Test name
Test status
Simulation time 224816647 ps
CPU time 2.11 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:28 PM PDT 24
Peak memory 213808 kb
Host smart-ac037ec6-2c33-40a5-84ec-8244eaead2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139450731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4139450731
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.439329348
Short name T547
Test name
Test status
Simulation time 526579854 ps
CPU time 21.34 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:57 PM PDT 24
Peak memory 250804 kb
Host smart-9cc7c98d-071b-419f-8527-021af63d5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439329348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.439329348
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.825217173
Short name T427
Test name
Test status
Simulation time 462395396 ps
CPU time 10.76 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:40 PM PDT 24
Peak memory 250764 kb
Host smart-d7c6faca-73a3-481e-8084-eee5976e33f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825217173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.825217173
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3828055862
Short name T58
Test name
Test status
Simulation time 11330399439 ps
CPU time 74.11 seconds
Started May 14 12:54:21 PM PDT 24
Finished May 14 12:55:39 PM PDT 24
Peak memory 227780 kb
Host smart-b0ca11ec-23a2-447e-b29a-8c13ad60ed63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828055862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3828055862
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2324427238
Short name T159
Test name
Test status
Simulation time 29909570240 ps
CPU time 244.85 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:58:33 PM PDT 24
Peak memory 300336 kb
Host smart-433564b3-cbfc-41bb-ae88-dbecabcb343e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2324427238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2324427238
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1978084691
Short name T593
Test name
Test status
Simulation time 37089545 ps
CPU time 1.25 seconds
Started May 14 12:54:19 PM PDT 24
Finished May 14 12:54:23 PM PDT 24
Peak memory 212868 kb
Host smart-4bf63c42-4bfd-4144-b25b-e9a756f176e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978084691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1978084691
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2070383891
Short name T75
Test name
Test status
Simulation time 24607328 ps
CPU time 1.03 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:25 PM PDT 24
Peak memory 209588 kb
Host smart-f5f66963-0d24-4033-943a-069f5e9aca93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070383891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2070383891
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3913439677
Short name T446
Test name
Test status
Simulation time 438806879 ps
CPU time 17.23 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:41 PM PDT 24
Peak memory 217992 kb
Host smart-16047264-9969-4f9f-899b-e4c2dc5c0cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913439677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3913439677
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.4170840651
Short name T28
Test name
Test status
Simulation time 2103879184 ps
CPU time 11.8 seconds
Started May 14 12:54:21 PM PDT 24
Finished May 14 12:54:36 PM PDT 24
Peak memory 209540 kb
Host smart-533b4bf5-60b1-4a43-8753-55395d3b58e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170840651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4170840651
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1450627614
Short name T195
Test name
Test status
Simulation time 175235194 ps
CPU time 3.34 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 221996 kb
Host smart-bffa846c-9fdf-45d2-a9e1-06e1a35a48a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450627614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1450627614
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3820480651
Short name T513
Test name
Test status
Simulation time 446459775 ps
CPU time 15.84 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:42 PM PDT 24
Peak memory 218084 kb
Host smart-dc3f3c40-bcf3-4cdf-8083-a6317aebec4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820480651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3820480651
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2736156097
Short name T632
Test name
Test status
Simulation time 515298107 ps
CPU time 11.13 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 217972 kb
Host smart-b85d93f2-dcc9-4247-b5be-ca14c0d8cd36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736156097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2736156097
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.194484155
Short name T309
Test name
Test status
Simulation time 1075001816 ps
CPU time 9.46 seconds
Started May 14 12:54:17 PM PDT 24
Finished May 14 12:54:28 PM PDT 24
Peak memory 226084 kb
Host smart-6b138231-032d-420a-b9e5-0a17c0d370de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194484155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.194484155
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2054120989
Short name T769
Test name
Test status
Simulation time 422764226 ps
CPU time 2.84 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 214356 kb
Host smart-ee98a398-873e-4d25-bdf2-c44323cb8a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054120989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2054120989
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2628181777
Short name T460
Test name
Test status
Simulation time 1347073597 ps
CPU time 28.73 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:55 PM PDT 24
Peak memory 250960 kb
Host smart-b326f3d1-71be-4416-8a13-144503430432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628181777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2628181777
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2382617777
Short name T585
Test name
Test status
Simulation time 319098534 ps
CPU time 7.39 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 246100 kb
Host smart-0e97ddf9-7053-425f-80c7-106e0790a4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382617777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2382617777
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.861171189
Short name T117
Test name
Test status
Simulation time 58604616271 ps
CPU time 225.55 seconds
Started May 14 12:54:15 PM PDT 24
Finished May 14 12:58:02 PM PDT 24
Peak memory 283488 kb
Host smart-c65c3922-134e-4ac6-a2ab-323629c6c821
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861171189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.861171189
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.342846010
Short name T377
Test name
Test status
Simulation time 41202529 ps
CPU time 0.93 seconds
Started May 14 12:54:16 PM PDT 24
Finished May 14 12:54:19 PM PDT 24
Peak memory 208624 kb
Host smart-5ac94ee5-7562-4411-8dba-29ecbf13d565
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342846010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.342846010
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2620713113
Short name T718
Test name
Test status
Simulation time 18534155 ps
CPU time 1.06 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:33 PM PDT 24
Peak memory 209556 kb
Host smart-5f201d2f-34df-4b4a-b0d4-6c2b1d87a042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620713113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2620713113
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3008834426
Short name T341
Test name
Test status
Simulation time 2174256274 ps
CPU time 15.88 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:42 PM PDT 24
Peak memory 209620 kb
Host smart-d5e903b3-d0aa-4388-a0af-884c884a8469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008834426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3008834426
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.4207585596
Short name T398
Test name
Test status
Simulation time 371509299 ps
CPU time 2.71 seconds
Started May 14 12:54:22 PM PDT 24
Finished May 14 12:54:29 PM PDT 24
Peak memory 221868 kb
Host smart-4c5c1c83-e632-44c5-9cdc-8b253224a20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207585596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.4207585596
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.332206432
Short name T691
Test name
Test status
Simulation time 648434333 ps
CPU time 14.97 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:47 PM PDT 24
Peak memory 218908 kb
Host smart-ef5913f4-0739-42bc-beb4-72ebd316e52b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332206432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.332206432
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.687307294
Short name T258
Test name
Test status
Simulation time 1849385169 ps
CPU time 12.88 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 217968 kb
Host smart-dab012eb-861e-43ce-bd29-f2d77926bc78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687307294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.687307294
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.376510036
Short name T168
Test name
Test status
Simulation time 945345608 ps
CPU time 7.59 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:37 PM PDT 24
Peak memory 217992 kb
Host smart-b2c79a7a-6703-415a-a1de-f5cbeee1daf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376510036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.376510036
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2426625646
Short name T52
Test name
Test status
Simulation time 986734881 ps
CPU time 6.12 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:33 PM PDT 24
Peak memory 224152 kb
Host smart-89507c82-c1e2-478f-9420-7535ccf6c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426625646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2426625646
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.4163863351
Short name T99
Test name
Test status
Simulation time 20628700 ps
CPU time 1.54 seconds
Started May 14 12:54:23 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 213572 kb
Host smart-f0a73f00-117d-46e5-b6bc-7c5c95fc0b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163863351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.4163863351
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.600758271
Short name T255
Test name
Test status
Simulation time 274309013 ps
CPU time 22.83 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:46 PM PDT 24
Peak memory 250884 kb
Host smart-ac82a0f9-3eed-4714-99c5-42ee60f34df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600758271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.600758271
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2335243087
Short name T864
Test name
Test status
Simulation time 1048238242 ps
CPU time 6.23 seconds
Started May 14 12:54:19 PM PDT 24
Finished May 14 12:54:28 PM PDT 24
Peak memory 250400 kb
Host smart-67c85c2a-f897-44c1-b099-4d7cd4acbb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335243087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2335243087
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4275709381
Short name T17
Test name
Test status
Simulation time 1999854042 ps
CPU time 38.74 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:55:11 PM PDT 24
Peak memory 219012 kb
Host smart-2e8fffe7-99ea-4a7f-a886-d9132f641dc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275709381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4275709381
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1943914464
Short name T542
Test name
Test status
Simulation time 105964337876 ps
CPU time 657.99 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 01:05:20 PM PDT 24
Peak memory 389352 kb
Host smart-f8a02749-f435-4d9f-ac86-1abb55f88712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1943914464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1943914464
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1119738480
Short name T240
Test name
Test status
Simulation time 209414251 ps
CPU time 1 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:32 PM PDT 24
Peak memory 212628 kb
Host smart-130fb81a-2a94-4177-8f58-5fc246199f19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119738480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1119738480
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.887252559
Short name T748
Test name
Test status
Simulation time 27601710 ps
CPU time 1.02 seconds
Started May 14 12:54:48 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 209608 kb
Host smart-f2ae01cb-3a4e-427c-b8c7-2ced8f6de954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887252559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.887252559
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.121267558
Short name T609
Test name
Test status
Simulation time 1035299088 ps
CPU time 16.37 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:52 PM PDT 24
Peak memory 217944 kb
Host smart-a0dea950-06b9-4dc0-9680-8234712e1690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121267558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.121267558
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.601883805
Short name T625
Test name
Test status
Simulation time 255374338 ps
CPU time 3.03 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 209300 kb
Host smart-75631615-4d99-4d0b-88a0-f9c2ad073fea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601883805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.601883805
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.867295520
Short name T98
Test name
Test status
Simulation time 22720876 ps
CPU time 1.7 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 221512 kb
Host smart-165919c9-0804-43ba-b24a-a1a96dac49a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867295520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.867295520
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3032067490
Short name T614
Test name
Test status
Simulation time 479814156 ps
CPU time 13.88 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:49 PM PDT 24
Peak memory 217944 kb
Host smart-c481523f-f414-43c3-84eb-577bffe93255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032067490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3032067490
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.113348398
Short name T599
Test name
Test status
Simulation time 3108019793 ps
CPU time 11.99 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 217948 kb
Host smart-6df96a4e-d740-4889-a989-cd60472aefd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113348398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.113348398
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3663593065
Short name T720
Test name
Test status
Simulation time 836876804 ps
CPU time 7.39 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:43 PM PDT 24
Peak memory 217936 kb
Host smart-2d004418-de97-4040-9812-582adb943520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663593065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3663593065
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2934200436
Short name T390
Test name
Test status
Simulation time 305262164 ps
CPU time 11.9 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 225976 kb
Host smart-62bd6099-1c6a-45d4-ab86-e371408bd0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934200436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2934200436
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.4019389070
Short name T63
Test name
Test status
Simulation time 60888078 ps
CPU time 3.33 seconds
Started May 14 12:54:18 PM PDT 24
Finished May 14 12:54:23 PM PDT 24
Peak memory 218168 kb
Host smart-e25cd9dc-8dab-4c2c-9546-a504661985fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019389070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4019389070
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2978071536
Short name T508
Test name
Test status
Simulation time 305482524 ps
CPU time 28.63 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:55:04 PM PDT 24
Peak memory 250724 kb
Host smart-d41912f7-628a-4473-a3aa-adfed41c49d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978071536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2978071536
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1840849691
Short name T334
Test name
Test status
Simulation time 181986353 ps
CPU time 7.43 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:54:31 PM PDT 24
Peak memory 244884 kb
Host smart-eaed2fca-ab03-468b-9350-40bbc7bff7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840849691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1840849691
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2012999787
Short name T845
Test name
Test status
Simulation time 15130033794 ps
CPU time 152.5 seconds
Started May 14 12:54:20 PM PDT 24
Finished May 14 12:56:56 PM PDT 24
Peak memory 279312 kb
Host smart-8a933d4c-c2fd-4406-930e-402a8ce33d78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012999787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2012999787
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2623407194
Short name T683
Test name
Test status
Simulation time 24817707441 ps
CPU time 372.54 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 01:00:48 PM PDT 24
Peak memory 283152 kb
Host smart-ea360244-7c41-4066-a986-e786eaa1c70c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2623407194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2623407194
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3491891621
Short name T603
Test name
Test status
Simulation time 25307679 ps
CPU time 0.92 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:36 PM PDT 24
Peak memory 211596 kb
Host smart-e8ee27c4-c219-4138-8800-56ac93d5104b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491891621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3491891621
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.465418312
Short name T70
Test name
Test status
Simulation time 75438626 ps
CPU time 0.89 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:30 PM PDT 24
Peak memory 209456 kb
Host smart-626b772d-2ab8-42ef-9864-8d8d3a800711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465418312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.465418312
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2733782451
Short name T112
Test name
Test status
Simulation time 907782580 ps
CPU time 11.32 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:54:40 PM PDT 24
Peak memory 217952 kb
Host smart-182bf491-8ef6-4dc8-a8db-43ff0347b8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733782451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2733782451
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3910726316
Short name T23
Test name
Test status
Simulation time 3573703176 ps
CPU time 14.08 seconds
Started May 14 12:54:45 PM PDT 24
Finished May 14 12:55:03 PM PDT 24
Peak memory 209640 kb
Host smart-ca6329e6-2581-46c1-9819-742766a5d9b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910726316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3910726316
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.202129142
Short name T529
Test name
Test status
Simulation time 295802506 ps
CPU time 2.8 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 221572 kb
Host smart-459ec9bc-853a-4718-901d-4a4bdf763232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202129142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.202129142
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2303358236
Short name T601
Test name
Test status
Simulation time 1615461892 ps
CPU time 12.6 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 218044 kb
Host smart-d0bfd94a-f8d4-4a48-828d-4136d23e90cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303358236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2303358236
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1656326439
Short name T471
Test name
Test status
Simulation time 616074600 ps
CPU time 9 seconds
Started May 14 12:54:31 PM PDT 24
Finished May 14 12:54:44 PM PDT 24
Peak memory 226032 kb
Host smart-8e019579-8f6c-44de-9687-64edee1addc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656326439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1656326439
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2293079166
Short name T267
Test name
Test status
Simulation time 386213446 ps
CPU time 12.54 seconds
Started May 14 12:54:28 PM PDT 24
Finished May 14 12:54:45 PM PDT 24
Peak memory 217876 kb
Host smart-e29df2fb-d3ba-4e2e-8f4e-3af14af27c30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293079166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2293079166
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.14910786
Short name T49
Test name
Test status
Simulation time 238048303 ps
CPU time 7.75 seconds
Started May 14 12:54:25 PM PDT 24
Finished May 14 12:54:38 PM PDT 24
Peak memory 224264 kb
Host smart-9232280c-6eae-472f-aff9-5edafd0d1dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14910786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.14910786
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1712592104
Short name T72
Test name
Test status
Simulation time 192757172 ps
CPU time 2.32 seconds
Started May 14 12:54:26 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 214056 kb
Host smart-a95fae89-6ec5-4ef5-8f40-631486b9f8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712592104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1712592104
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.4237207246
Short name T193
Test name
Test status
Simulation time 1530118578 ps
CPU time 30.02 seconds
Started May 14 12:54:27 PM PDT 24
Finished May 14 12:55:02 PM PDT 24
Peak memory 249000 kb
Host smart-e9034e1b-de0d-4d1f-87ed-820ce5dbccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237207246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4237207246
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2037096763
Short name T12
Test name
Test status
Simulation time 60484643 ps
CPU time 5.89 seconds
Started May 14 12:54:28 PM PDT 24
Finished May 14 12:54:39 PM PDT 24
Peak memory 250880 kb
Host smart-abc35e5a-a328-4964-9a7b-c63a5a29eb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037096763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2037096763
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3158652685
Short name T386
Test name
Test status
Simulation time 19261821103 ps
CPU time 97.37 seconds
Started May 14 12:54:24 PM PDT 24
Finished May 14 12:56:06 PM PDT 24
Peak memory 267464 kb
Host smart-20879d9a-b753-455e-bf6b-fd0088bdd05e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158652685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3158652685
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3228071736
Short name T251
Test name
Test status
Simulation time 12511411 ps
CPU time 0.82 seconds
Started May 14 12:54:29 PM PDT 24
Finished May 14 12:54:34 PM PDT 24
Peak memory 208536 kb
Host smart-3ea2f04d-891b-42da-91f9-a685bc52b3a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228071736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3228071736
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2846731371
Short name T78
Test name
Test status
Simulation time 109741618 ps
CPU time 1.01 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 209836 kb
Host smart-90b67b8c-368a-440e-94a3-deb3bbcd4a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846731371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2846731371
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.838874838
Short name T536
Test name
Test status
Simulation time 13580064 ps
CPU time 0.99 seconds
Started May 14 12:52:35 PM PDT 24
Finished May 14 12:52:37 PM PDT 24
Peak memory 209528 kb
Host smart-7d1ca973-a646-4282-8cff-0bf57466b22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838874838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.838874838
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4082999335
Short name T774
Test name
Test status
Simulation time 1251746642 ps
CPU time 10.86 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 225532 kb
Host smart-9a87ffe6-f1e6-409e-bbde-67f5bf53d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082999335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4082999335
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2214847135
Short name T361
Test name
Test status
Simulation time 255638241 ps
CPU time 2.07 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:52:41 PM PDT 24
Peak memory 209528 kb
Host smart-5c4523f3-3401-40d5-9911-a15abd2d9db2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214847135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2214847135
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2329837343
Short name T250
Test name
Test status
Simulation time 6869702948 ps
CPU time 30.89 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 218856 kb
Host smart-3959edbc-637c-495a-9430-152aa2ffebc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329837343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2329837343
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.911211695
Short name T729
Test name
Test status
Simulation time 236149465 ps
CPU time 6.38 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:44 PM PDT 24
Peak memory 217148 kb
Host smart-28c11140-7b7b-4f85-9815-912f283363cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911211695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.911211695
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1186202877
Short name T561
Test name
Test status
Simulation time 1338337382 ps
CPU time 9.34 seconds
Started May 14 12:52:35 PM PDT 24
Finished May 14 12:52:45 PM PDT 24
Peak memory 218044 kb
Host smart-bfe2257e-02d5-4196-bc7b-92b1d057e319
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186202877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1186202877
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3245636273
Short name T234
Test name
Test status
Simulation time 5244447719 ps
CPU time 37.19 seconds
Started May 14 12:52:38 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 214020 kb
Host smart-3450d038-74eb-4e35-a281-605a665c60ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245636273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3245636273
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1097243838
Short name T79
Test name
Test status
Simulation time 494533660 ps
CPU time 12.83 seconds
Started May 14 12:52:35 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 213416 kb
Host smart-a67c1aa8-5e9b-4012-9ba9-d6f462345a27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097243838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1097243838
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2798413401
Short name T866
Test name
Test status
Simulation time 2317585335 ps
CPU time 39.41 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 276192 kb
Host smart-b3cf62a7-8bac-480f-a3f5-2f4c1806c159
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798413401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2798413401
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3725140234
Short name T829
Test name
Test status
Simulation time 560922268 ps
CPU time 22.6 seconds
Started May 14 12:52:38 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 248864 kb
Host smart-ad2c4c5a-b683-4d37-93f1-67ce1345e7f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725140234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3725140234
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.431751775
Short name T311
Test name
Test status
Simulation time 331001568 ps
CPU time 3.22 seconds
Started May 14 12:52:34 PM PDT 24
Finished May 14 12:52:39 PM PDT 24
Peak memory 221888 kb
Host smart-11c29986-beab-4a22-9174-997dbacf8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431751775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.431751775
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2616444937
Short name T647
Test name
Test status
Simulation time 409295146 ps
CPU time 5.6 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:43 PM PDT 24
Peak memory 214056 kb
Host smart-cf2ccb94-0be3-45a9-a1d6-fa4c97fe88c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616444937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2616444937
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3511302277
Short name T532
Test name
Test status
Simulation time 3967782847 ps
CPU time 9.93 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:52:48 PM PDT 24
Peak memory 219048 kb
Host smart-95fcee42-afe9-46ca-98e7-8da840ac6aec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511302277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3511302277
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1941243952
Short name T788
Test name
Test status
Simulation time 578710190 ps
CPU time 10.28 seconds
Started May 14 12:52:38 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 217988 kb
Host smart-f3594d4d-6508-4647-a1a3-ac631dcdae83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941243952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1941243952
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3748708222
Short name T686
Test name
Test status
Simulation time 1032211472 ps
CPU time 9.68 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:48 PM PDT 24
Peak memory 218056 kb
Host smart-3b76afa8-5c01-4a2d-a8ba-ab22309a77ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748708222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
748708222
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3256542578
Short name T489
Test name
Test status
Simulation time 713659464 ps
CPU time 14.55 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:52 PM PDT 24
Peak memory 225988 kb
Host smart-cec2ae50-db8d-43b9-a07b-d9e9e6b77b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256542578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3256542578
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.600217820
Short name T765
Test name
Test status
Simulation time 64570781 ps
CPU time 1.87 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:52:41 PM PDT 24
Peak memory 213744 kb
Host smart-bee4e1ff-3b39-43e6-aa24-94c485417028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600217820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.600217820
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2121054872
Short name T572
Test name
Test status
Simulation time 213451233 ps
CPU time 19.59 seconds
Started May 14 12:52:36 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 250924 kb
Host smart-15af7702-6a38-4866-be61-a878abd95bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121054872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2121054872
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1942011351
Short name T260
Test name
Test status
Simulation time 110183064 ps
CPU time 6.83 seconds
Started May 14 12:52:35 PM PDT 24
Finished May 14 12:52:42 PM PDT 24
Peak memory 246604 kb
Host smart-525ea400-98a3-4600-a2f0-e7ce8ec0770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942011351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1942011351
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2050045843
Short name T237
Test name
Test status
Simulation time 6003772201 ps
CPU time 225.26 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:56:31 PM PDT 24
Peak memory 275188 kb
Host smart-ba4c8dd4-970b-4869-a4e9-ca31b984f55b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050045843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2050045843
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3053690151
Short name T163
Test name
Test status
Simulation time 68654139556 ps
CPU time 3464.92 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 01:50:32 PM PDT 24
Peak memory 890184 kb
Host smart-12fd62bc-09af-4fef-bf7b-c29147d68074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3053690151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3053690151
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1777922109
Short name T803
Test name
Test status
Simulation time 13916458 ps
CPU time 0.96 seconds
Started May 14 12:52:37 PM PDT 24
Finished May 14 12:52:39 PM PDT 24
Peak memory 211516 kb
Host smart-d9206f25-875f-47da-b327-d82b80123696
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777922109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1777922109
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3286328306
Short name T721
Test name
Test status
Simulation time 52750260 ps
CPU time 0.83 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 209460 kb
Host smart-21432118-c4be-48b4-a5d7-d5d0db59e08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286328306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3286328306
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1068155696
Short name T518
Test name
Test status
Simulation time 1164853063 ps
CPU time 11.1 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 218012 kb
Host smart-5c60d603-4a39-4b8b-a028-4e3c94860835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068155696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1068155696
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3237692408
Short name T7
Test name
Test status
Simulation time 1039483114 ps
CPU time 6.31 seconds
Started May 14 12:52:43 PM PDT 24
Finished May 14 12:52:51 PM PDT 24
Peak memory 217288 kb
Host smart-5e4fea2a-fbdf-4eb1-bf94-f75b9ee37547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237692408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3237692408
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.892716754
Short name T369
Test name
Test status
Simulation time 1535024313 ps
CPU time 51.42 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 217936 kb
Host smart-a3a71d91-18b2-4540-a67f-35c65bcb49f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892716754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.892716754
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.614529922
Short name T374
Test name
Test status
Simulation time 2029932339 ps
CPU time 4.94 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:52:54 PM PDT 24
Peak memory 217844 kb
Host smart-a6300672-94e3-48b1-8dfc-a7420e45fec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614529922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.614529922
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4092378836
Short name T297
Test name
Test status
Simulation time 282120685 ps
CPU time 5.94 seconds
Started May 14 12:52:49 PM PDT 24
Finished May 14 12:52:58 PM PDT 24
Peak memory 218044 kb
Host smart-f7817e0a-20f5-4e2d-bcb7-9008f557821b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092378836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4092378836
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.11908304
Short name T114
Test name
Test status
Simulation time 2828249690 ps
CPU time 20.47 seconds
Started May 14 12:52:48 PM PDT 24
Finished May 14 12:53:12 PM PDT 24
Peak memory 213548 kb
Host smart-0adc4bf2-a789-4aea-9cfd-d8e8128d1481
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt
ag_regwen_during_op.11908304
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2121456439
Short name T636
Test name
Test status
Simulation time 1064390704 ps
CPU time 9.84 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 213844 kb
Host smart-1f562ca8-459b-4417-84d4-4afcc3507262
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121456439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2121456439
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1346454006
Short name T503
Test name
Test status
Simulation time 1853433595 ps
CPU time 30.32 seconds
Started May 14 12:52:42 PM PDT 24
Finished May 14 12:53:15 PM PDT 24
Peak memory 250912 kb
Host smart-f258d639-851a-48a8-936b-73674c67b44b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346454006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1346454006
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1598789230
Short name T280
Test name
Test status
Simulation time 664422359 ps
CPU time 15.98 seconds
Started May 14 12:52:50 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 247504 kb
Host smart-073da103-322f-41c9-a9f9-6619f4e6c387
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598789230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1598789230
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2464491290
Short name T262
Test name
Test status
Simulation time 339894944 ps
CPU time 3.23 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:52:52 PM PDT 24
Peak memory 222096 kb
Host smart-96700778-46c5-446e-bc5a-f39bcb3b35b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464491290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2464491290
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.461591239
Short name T71
Test name
Test status
Simulation time 295465074 ps
CPU time 8.09 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:52:56 PM PDT 24
Peak memory 213728 kb
Host smart-771982e1-1022-45be-98a9-b141f6464e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461591239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.461591239
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.943521801
Short name T368
Test name
Test status
Simulation time 976035174 ps
CPU time 27.62 seconds
Started May 14 12:52:48 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 218928 kb
Host smart-d57d1592-c2a7-4094-a5a7-d3a9f8131bc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943521801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.943521801
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3539757505
Short name T789
Test name
Test status
Simulation time 3156941951 ps
CPU time 8.54 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 218024 kb
Host smart-5815ec25-317b-49b5-8303-79380dcddfc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539757505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3539757505
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2380961853
Short name T856
Test name
Test status
Simulation time 7235518338 ps
CPU time 12.72 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 218092 kb
Host smart-794c8ae0-33c6-40d1-a72c-6ac3e5046a26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380961853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
380961853
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3383352156
Short name T701
Test name
Test status
Simulation time 35092408 ps
CPU time 1.42 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 217748 kb
Host smart-05fc8249-4e04-499d-b037-a9f979b24286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383352156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3383352156
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.956233993
Short name T533
Test name
Test status
Simulation time 2474380886 ps
CPU time 27.21 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 251000 kb
Host smart-b244260d-c3a4-4d1f-b08b-0c5be9f378f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956233993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.956233993
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.554758365
Short name T606
Test name
Test status
Simulation time 93433191 ps
CPU time 8.01 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 250744 kb
Host smart-38952922-a8ef-4aac-b3c4-4e79b6d24af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554758365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.554758365
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3273988371
Short name T695
Test name
Test status
Simulation time 35786212 ps
CPU time 0.99 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 211688 kb
Host smart-a4e3f4b5-c55d-4f6b-a3c7-e7bffd52920f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273988371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3273988371
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3618672056
Short name T242
Test name
Test status
Simulation time 22681513 ps
CPU time 1.29 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:52:50 PM PDT 24
Peak memory 209556 kb
Host smart-eec37b49-b43b-4ca6-81a6-08d25e3e1ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618672056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3618672056
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2520155150
Short name T447
Test name
Test status
Simulation time 33775715 ps
CPU time 0.88 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:52:51 PM PDT 24
Peak memory 209496 kb
Host smart-9c3a3735-8f7a-4e22-b64a-41622f4e2f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520155150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2520155150
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3523995889
Short name T409
Test name
Test status
Simulation time 1627276900 ps
CPU time 13.1 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 217980 kb
Host smart-09d6a76a-ddb6-44c6-a6fe-35f180059082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523995889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3523995889
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1642559961
Short name T823
Test name
Test status
Simulation time 68884130 ps
CPU time 2.28 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:53:00 PM PDT 24
Peak memory 209560 kb
Host smart-98904eba-e7c9-4ab8-a1f0-ced35ed06435
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642559961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1642559961
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.52838335
Short name T750
Test name
Test status
Simulation time 1560825340 ps
CPU time 30.26 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 217808 kb
Host smart-4bdc9231-a4d2-4dfd-b513-0dd4cf568a9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52838335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_erro
rs.52838335
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.994781069
Short name T531
Test name
Test status
Simulation time 1724612672 ps
CPU time 4.69 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:52:52 PM PDT 24
Peak memory 217816 kb
Host smart-a983137b-acfe-45ee-9ed8-9e54d5b943cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994781069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.994781069
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3880362193
Short name T843
Test name
Test status
Simulation time 12637432335 ps
CPU time 10.89 seconds
Started May 14 12:52:50 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 217948 kb
Host smart-c75bbec4-8c65-479e-a9f6-b1617aeebdf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880362193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3880362193
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.591732656
Short name T459
Test name
Test status
Simulation time 11787492670 ps
CPU time 17.51 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 213672 kb
Host smart-78927837-d1ed-4277-a238-31f621b562bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591732656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.591732656
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1655964739
Short name T772
Test name
Test status
Simulation time 834783645 ps
CPU time 11.22 seconds
Started May 14 12:52:48 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 213708 kb
Host smart-915a6adc-1ed8-4b97-935b-83a2dbb6f1f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655964739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1655964739
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1501071430
Short name T526
Test name
Test status
Simulation time 5447571601 ps
CPU time 57.14 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:53:48 PM PDT 24
Peak memory 267360 kb
Host smart-a57a9f52-a141-4f1e-bf62-8866caa925a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501071430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1501071430
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.508876600
Short name T812
Test name
Test status
Simulation time 1021802561 ps
CPU time 18.71 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 245160 kb
Host smart-7a921985-9695-42b1-b5fc-25a816877aa3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508876600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.508876600
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3739519589
Short name T779
Test name
Test status
Simulation time 413238359 ps
CPU time 4.03 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:52:54 PM PDT 24
Peak memory 221880 kb
Host smart-86bcdfc0-bb85-460f-817a-41995fcb2df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739519589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3739519589
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.883412596
Short name T69
Test name
Test status
Simulation time 930034473 ps
CPU time 13.25 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:53:01 PM PDT 24
Peak memory 213736 kb
Host smart-10d947d0-534d-4153-bf46-769c1e16d856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883412596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.883412596
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2074548090
Short name T860
Test name
Test status
Simulation time 1604926735 ps
CPU time 14.58 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 218844 kb
Host smart-d2e2d60f-bcb9-4cfa-be6f-8efb31b6fdf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074548090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2074548090
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2054834213
Short name T100
Test name
Test status
Simulation time 1149623626 ps
CPU time 11.8 seconds
Started May 14 12:52:48 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 218000 kb
Host smart-258aaa2f-7476-4a33-ae03-2ed1d356d303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054834213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2054834213
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2271533127
Short name T379
Test name
Test status
Simulation time 177182621 ps
CPU time 6.89 seconds
Started May 14 12:52:42 PM PDT 24
Finished May 14 12:52:50 PM PDT 24
Peak memory 217924 kb
Host smart-5c812af6-ca43-4016-bb38-2b9779139f41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271533127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
271533127
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2994845423
Short name T494
Test name
Test status
Simulation time 1008738590 ps
CPU time 6.56 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 224184 kb
Host smart-0c0fdccf-90b6-46e8-bf27-37e4d6df6c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994845423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2994845423
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2308387394
Short name T74
Test name
Test status
Simulation time 41890462 ps
CPU time 2.96 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:52:51 PM PDT 24
Peak memory 217960 kb
Host smart-323d504c-6732-4db3-9443-15a4d81a2967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308387394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2308387394
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3352277833
Short name T422
Test name
Test status
Simulation time 182281857 ps
CPU time 26.86 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:53:17 PM PDT 24
Peak memory 248672 kb
Host smart-94a17723-4c63-4448-922e-90220338d796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352277833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3352277833
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1164749460
Short name T230
Test name
Test status
Simulation time 96324623 ps
CPU time 9.36 seconds
Started May 14 12:52:43 PM PDT 24
Finished May 14 12:52:54 PM PDT 24
Peak memory 248624 kb
Host smart-8c1e0734-d509-44a3-91b6-8d6782a7bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164749460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1164749460
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.962665411
Short name T41
Test name
Test status
Simulation time 15659364356 ps
CPU time 65.62 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:54:05 PM PDT 24
Peak memory 229980 kb
Host smart-aea94e40-a46d-4b9f-bf12-ffcd684905bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962665411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.962665411
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.512750582
Short name T874
Test name
Test status
Simulation time 30373832159 ps
CPU time 278.34 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:57:29 PM PDT 24
Peak memory 514652 kb
Host smart-e31b0578-c794-4c09-8fc2-597a697844ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=512750582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.512750582
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1997961336
Short name T652
Test name
Test status
Simulation time 19134049 ps
CPU time 0.8 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:52:47 PM PDT 24
Peak memory 208440 kb
Host smart-e51f2593-9277-4804-b8cc-172695670191
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997961336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1997961336
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3790943439
Short name T276
Test name
Test status
Simulation time 18620144 ps
CPU time 0.86 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:52:52 PM PDT 24
Peak memory 209584 kb
Host smart-ad14e133-3776-4ab0-9177-ba5062922250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790943439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3790943439
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.4218704312
Short name T413
Test name
Test status
Simulation time 32290850 ps
CPU time 0.85 seconds
Started May 14 12:52:51 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 209556 kb
Host smart-30551838-80f3-4525-b656-d0d4ce0559e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218704312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4218704312
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.6244324
Short name T227
Test name
Test status
Simulation time 236213366 ps
CPU time 9.24 seconds
Started May 14 12:52:49 PM PDT 24
Finished May 14 12:53:01 PM PDT 24
Peak memory 226076 kb
Host smart-adc034a0-b403-4269-b53e-ee38c1e35a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6244324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.6244324
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.393670300
Short name T25
Test name
Test status
Simulation time 1427231570 ps
CPU time 17.25 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:53:07 PM PDT 24
Peak memory 209600 kb
Host smart-e1e37423-9c64-498e-b076-89309953177f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393670300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.393670300
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1720200887
Short name T38
Test name
Test status
Simulation time 7480440888 ps
CPU time 56.18 seconds
Started May 14 12:52:50 PM PDT 24
Finished May 14 12:53:50 PM PDT 24
Peak memory 218532 kb
Host smart-c9ad2a5d-a2dd-4578-b6c8-72d3ce961944
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720200887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1720200887
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2435768299
Short name T521
Test name
Test status
Simulation time 2414816003 ps
CPU time 7.92 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 217652 kb
Host smart-c7edecc2-e32d-429d-96f7-2e51844bca27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435768299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
435768299
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3574025786
Short name T353
Test name
Test status
Simulation time 353891548 ps
CPU time 11.11 seconds
Started May 14 12:52:50 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 217840 kb
Host smart-d4826703-798f-42d1-ad83-96b0123a13d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574025786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3574025786
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2293133708
Short name T82
Test name
Test status
Simulation time 1967839991 ps
CPU time 19.83 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 213148 kb
Host smart-5f65e4ed-881b-4bc7-a93e-9695ac2a0b2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293133708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2293133708
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.288786204
Short name T706
Test name
Test status
Simulation time 101604008 ps
CPU time 3.23 seconds
Started May 14 12:52:51 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 212952 kb
Host smart-9c8f5511-a375-4a41-8008-cedba8ffdc87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288786204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.288786204
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.4190671473
Short name T300
Test name
Test status
Simulation time 3182957347 ps
CPU time 38.88 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:53:26 PM PDT 24
Peak memory 251496 kb
Host smart-5b6841a3-5380-4e6b-a97f-8c2b7a6779a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190671473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.4190671473
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2085890243
Short name T740
Test name
Test status
Simulation time 1194092315 ps
CPU time 22.54 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 250824 kb
Host smart-3db83882-f5bc-45b8-8d3c-026f66b4ddab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085890243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2085890243
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2697865039
Short name T241
Test name
Test status
Simulation time 209536377 ps
CPU time 2.75 seconds
Started May 14 12:52:43 PM PDT 24
Finished May 14 12:52:48 PM PDT 24
Peak memory 221772 kb
Host smart-36cb46ce-cd7b-46ca-a582-3d220e889db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697865039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2697865039
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2466767747
Short name T77
Test name
Test status
Simulation time 1736961955 ps
CPU time 5.73 seconds
Started May 14 12:52:50 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 217732 kb
Host smart-a5919ba4-3fa9-4868-b449-97b7f40e8da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466767747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2466767747
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4027838843
Short name T323
Test name
Test status
Simulation time 916036488 ps
CPU time 8.83 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 217980 kb
Host smart-c0251132-b7c7-4dc0-a7de-f06c7841d6bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027838843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4027838843
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.506513096
Short name T167
Test name
Test status
Simulation time 326641629 ps
CPU time 12.55 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 217888 kb
Host smart-848a0f28-0137-49df-8724-f6b1d6d43603
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506513096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.506513096
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.884669602
Short name T844
Test name
Test status
Simulation time 309950852 ps
CPU time 8.24 seconds
Started May 14 12:52:49 PM PDT 24
Finished May 14 12:53:00 PM PDT 24
Peak memory 217952 kb
Host smart-25aed623-08ec-4223-8ce6-bba420875c6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884669602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.884669602
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3009301044
Short name T578
Test name
Test status
Simulation time 527862823 ps
CPU time 5.95 seconds
Started May 14 12:52:41 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 224260 kb
Host smart-c50b59e8-a9f1-4ad8-8389-8b0dbaee39e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009301044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3009301044
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2144574263
Short name T455
Test name
Test status
Simulation time 175737960 ps
CPU time 2.46 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:52:50 PM PDT 24
Peak memory 217944 kb
Host smart-8c4f0db8-d793-4731-b07d-e1089cd69468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144574263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2144574263
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2367947850
Short name T528
Test name
Test status
Simulation time 448969878 ps
CPU time 22.49 seconds
Started May 14 12:52:44 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 250972 kb
Host smart-799f4851-1dde-4ada-aff7-c254f80b166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367947850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2367947850
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4176110857
Short name T257
Test name
Test status
Simulation time 72674775 ps
CPU time 9.03 seconds
Started May 14 12:52:46 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 251028 kb
Host smart-38b67d41-3581-4bc9-91df-3dea4085dcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176110857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4176110857
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.999229878
Short name T854
Test name
Test status
Simulation time 42007942 ps
CPU time 0.77 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:52:51 PM PDT 24
Peak memory 208572 kb
Host smart-5d3a01bd-224e-470d-9d0d-38c85900aaab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999229878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.999229878
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.137061514
Short name T745
Test name
Test status
Simulation time 16707338 ps
CPU time 1.18 seconds
Started May 14 12:52:51 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 209452 kb
Host smart-2cf8f7f8-2001-4cc5-8d22-3a1e702593e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137061514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.137061514
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3870516189
Short name T219
Test name
Test status
Simulation time 12572259 ps
CPU time 0.82 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:52:58 PM PDT 24
Peak memory 209384 kb
Host smart-e6171c20-16d4-494e-9893-7140211aa5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870516189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3870516189
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3475395213
Short name T458
Test name
Test status
Simulation time 1381540744 ps
CPU time 12.38 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 217848 kb
Host smart-7272ac23-e339-4b6d-b488-5c25fd5d0582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475395213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3475395213
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3607482659
Short name T376
Test name
Test status
Simulation time 476427089 ps
CPU time 5.43 seconds
Started May 14 12:52:58 PM PDT 24
Finished May 14 12:53:07 PM PDT 24
Peak memory 209404 kb
Host smart-82df4107-749c-4b27-ab32-48ea80b67870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607482659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3607482659
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3418744046
Short name T486
Test name
Test status
Simulation time 3529711393 ps
CPU time 28.78 seconds
Started May 14 12:52:51 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 218888 kb
Host smart-137374f6-8c82-4356-92f9-aa4a7c85d2b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418744046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3418744046
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.145581463
Short name T391
Test name
Test status
Simulation time 1377496891 ps
CPU time 3.33 seconds
Started May 14 12:52:58 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 217768 kb
Host smart-a704cfdb-c83b-4a4c-9418-eb220593053c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145581463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.145581463
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2728478655
Short name T103
Test name
Test status
Simulation time 976748888 ps
CPU time 7.23 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:07 PM PDT 24
Peak memory 217944 kb
Host smart-b96536f9-83e1-4cf9-b706-456dd08e178c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728478655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2728478655
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1994072150
Short name T833
Test name
Test status
Simulation time 3312127128 ps
CPU time 16.04 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:53:14 PM PDT 24
Peak memory 213792 kb
Host smart-0ebd27d8-d582-4392-b284-4fff68af0749
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994072150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1994072150
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.264695524
Short name T580
Test name
Test status
Simulation time 1270064735 ps
CPU time 2.96 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 212920 kb
Host smart-ce22803c-f056-4c7d-9fdf-7faaf612abe8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264695524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.264695524
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2622687943
Short name T821
Test name
Test status
Simulation time 1126683396 ps
CPU time 36.43 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:35 PM PDT 24
Peak memory 276000 kb
Host smart-31490d6c-967d-46d8-9b0f-314700767ae2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622687943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2622687943
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2606698349
Short name T326
Test name
Test status
Simulation time 389799361 ps
CPU time 12.39 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:15 PM PDT 24
Peak memory 222852 kb
Host smart-c266a2ad-62c4-4c90-b057-6b186902f1f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606698349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2606698349
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.274184250
Short name T764
Test name
Test status
Simulation time 53315398 ps
CPU time 3.4 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 221956 kb
Host smart-fe4b01dd-1ab7-4bb0-8488-0fa318de5a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274184250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.274184250
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1443242852
Short name T249
Test name
Test status
Simulation time 549184506 ps
CPU time 6.63 seconds
Started May 14 12:52:54 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 217748 kb
Host smart-9a1eeb62-2d4f-4419-8401-2b88e3d0f6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443242852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1443242852
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.228782084
Short name T806
Test name
Test status
Simulation time 5537985601 ps
CPU time 13.18 seconds
Started May 14 12:52:59 PM PDT 24
Finished May 14 12:53:16 PM PDT 24
Peak memory 218180 kb
Host smart-184abce4-af1d-42e6-aff7-46bfadada0b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228782084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.228782084
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1500134943
Short name T2
Test name
Test status
Simulation time 570463838 ps
CPU time 14.34 seconds
Started May 14 12:52:52 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 218020 kb
Host smart-35283852-c4e7-444d-ac5b-aa49eeaf6168
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500134943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1500134943
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.499167111
Short name T266
Test name
Test status
Simulation time 295174192 ps
CPU time 9.1 seconds
Started May 14 12:52:56 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 218020 kb
Host smart-10fa9ad9-15a4-44e9-a165-b9740b8ac026
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499167111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.499167111
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.958193490
Short name T653
Test name
Test status
Simulation time 580918171 ps
CPU time 10.45 seconds
Started May 14 12:52:55 PM PDT 24
Finished May 14 12:53:10 PM PDT 24
Peak memory 225476 kb
Host smart-a7ec7db5-63a7-450c-9517-96538e19025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958193490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.958193490
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1672083268
Short name T558
Test name
Test status
Simulation time 18146982 ps
CPU time 1.2 seconds
Started May 14 12:52:47 PM PDT 24
Finished May 14 12:52:52 PM PDT 24
Peak memory 213324 kb
Host smart-760a5761-7be0-473a-8b26-a3d0053220c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672083268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1672083268
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2854417045
Short name T482
Test name
Test status
Simulation time 696436107 ps
CPU time 28.57 seconds
Started May 14 12:52:48 PM PDT 24
Finished May 14 12:53:20 PM PDT 24
Peak memory 244492 kb
Host smart-f974ac9f-dd4f-4897-990f-a019a8754d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854417045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2854417045
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1821721633
Short name T284
Test name
Test status
Simulation time 341287908 ps
CPU time 8.05 seconds
Started May 14 12:52:51 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 250992 kb
Host smart-44ddf4f7-b07d-414b-8f34-26e809014d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821721633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1821721633
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3236048066
Short name T543
Test name
Test status
Simulation time 32163773101 ps
CPU time 237.66 seconds
Started May 14 12:52:53 PM PDT 24
Finished May 14 12:56:55 PM PDT 24
Peak memory 270420 kb
Host smart-de8c8d1f-b226-4d94-8003-c86fa54543d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236048066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3236048066
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1896756219
Short name T402
Test name
Test status
Simulation time 82751851 ps
CPU time 0.79 seconds
Started May 14 12:52:45 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 208608 kb
Host smart-f9a34369-caf1-4f25-ad69-539c7d3f304b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896756219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1896756219
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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