Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51711 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
1780 |
1 |
|
|
T28 |
12 |
|
T29 |
10 |
|
T16 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52770 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
721 |
1 |
|
|
T30 |
15 |
|
T41 |
17 |
|
T63 |
9 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51572 |
1 |
|
|
T1 |
6 |
|
T2 |
96 |
|
T3 |
9 |
auto[1] |
1919 |
1 |
|
|
T2 |
11 |
|
T11 |
1 |
|
T13 |
2 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51562 |
1 |
|
|
T1 |
6 |
|
T2 |
98 |
|
T3 |
9 |
auto[1] |
1929 |
1 |
|
|
T2 |
9 |
|
T11 |
1 |
|
T87 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51523 |
1 |
|
|
T1 |
6 |
|
T2 |
99 |
|
T3 |
9 |
auto[1] |
1968 |
1 |
|
|
T2 |
8 |
|
T13 |
1 |
|
T34 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48757 |
1 |
|
|
T2 |
81 |
|
T10 |
89 |
|
T11 |
5 |
no_err_inj |
4734 |
1 |
|
|
T1 |
6 |
|
T2 |
26 |
|
T3 |
9 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51768 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
1723 |
1 |
|
|
T28 |
13 |
|
T29 |
11 |
|
T16 |
10 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52698 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
793 |
1 |
|
|
T30 |
7 |
|
T41 |
18 |
|
T63 |
23 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37157 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[1] |
16334 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51582 |
1 |
|
|
T1 |
6 |
|
T2 |
96 |
|
T3 |
9 |
auto[1] |
1909 |
1 |
|
|
T2 |
11 |
|
T12 |
1 |
|
T13 |
2 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51555 |
1 |
|
|
T1 |
6 |
|
T2 |
100 |
|
T3 |
9 |
auto[1] |
1936 |
1 |
|
|
T2 |
7 |
|
T12 |
1 |
|
T13 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51634 |
1 |
|
|
T1 |
6 |
|
T2 |
102 |
|
T3 |
9 |
auto[1] |
1857 |
1 |
|
|
T2 |
5 |
|
T11 |
1 |
|
T12 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51710 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
1781 |
1 |
|
|
T28 |
11 |
|
T29 |
6 |
|
T16 |
5 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51257 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
2234 |
1 |
|
|
T15 |
11 |
|
T32 |
3 |
|
T62 |
7 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52778 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
713 |
1 |
|
|
T30 |
17 |
|
T41 |
17 |
|
T63 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52733 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
758 |
1 |
|
|
T30 |
20 |
|
T41 |
24 |
|
T63 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52655 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
836 |
1 |
|
|
T30 |
8 |
|
T41 |
16 |
|
T63 |
15 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50692 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
2799 |
1 |
|
|
T11 |
12 |
|
T12 |
13 |
|
T13 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49730 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
3761 |
1 |
|
|
T31 |
77 |
|
T55 |
58 |
|
T56 |
99 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51530 |
1 |
|
|
T1 |
6 |
|
T2 |
97 |
|
T3 |
9 |
auto[1] |
1961 |
1 |
|
|
T2 |
10 |
|
T86 |
1 |
|
T18 |
29 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51576 |
1 |
|
|
T1 |
6 |
|
T2 |
97 |
|
T3 |
9 |
auto[1] |
1915 |
1 |
|
|
T2 |
10 |
|
T11 |
1 |
|
T12 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51564 |
1 |
|
|
T1 |
6 |
|
T2 |
97 |
|
T3 |
9 |
auto[1] |
1927 |
1 |
|
|
T2 |
10 |
|
T11 |
1 |
|
T12 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51691 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
1800 |
1 |
|
|
T28 |
9 |
|
T29 |
6 |
|
T16 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47891 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
5600 |
1 |
|
|
T10 |
89 |
|
T28 |
9 |
|
T29 |
3 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49838 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
3653 |
1 |
|
|
T33 |
66 |
|
T54 |
70 |
|
T44 |
98 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53491 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51745 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
1746 |
1 |
|
|
T28 |
8 |
|
T29 |
11 |
|
T16 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51701 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
1790 |
1 |
|
|
T28 |
11 |
|
T29 |
11 |
|
T16 |
7 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51744 |
1 |
|
|
T1 |
6 |
|
T2 |
107 |
|
T3 |
9 |
auto[1] |
1747 |
1 |
|
|
T28 |
10 |
|
T29 |
7 |
|
T16 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47375 |
1 |
|
|
T2 |
81 |
|
T10 |
89 |
|
T15 |
11 |
auto[0] |
no_err_inj |
3317 |
1 |
|
|
T1 |
6 |
|
T2 |
26 |
|
T3 |
9 |
auto[1] |
err_inj |
1382 |
1 |
|
|
T11 |
5 |
|
T12 |
5 |
|
T13 |
9 |
auto[1] |
no_err_inj |
1417 |
1 |
|
|
T11 |
7 |
|
T12 |
8 |
|
T13 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48934 |
1 |
|
|
T1 |
6 |
|
T2 |
97 |
|
T3 |
9 |
auto[0] |
auto[1] |
1758 |
1 |
|
|
T2 |
10 |
|
T18 |
15 |
|
T95 |
10 |
auto[1] |
auto[0] |
2642 |
1 |
|
|
T11 |
11 |
|
T12 |
12 |
|
T13 |
14 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T13 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48922 |
1 |
|
|
T1 |
6 |
|
T2 |
100 |
|
T3 |
9 |
auto[0] |
auto[1] |
1770 |
1 |
|
|
T2 |
7 |
|
T18 |
23 |
|
T95 |
14 |
auto[1] |
auto[0] |
2633 |
1 |
|
|
T11 |
12 |
|
T12 |
12 |
|
T13 |
14 |
auto[1] |
auto[1] |
166 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T86 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48930 |
1 |
|
|
T1 |
6 |
|
T2 |
97 |
|
T3 |
9 |
auto[0] |
auto[1] |
1762 |
1 |
|
|
T2 |
10 |
|
T18 |
21 |
|
T95 |
8 |
auto[1] |
auto[0] |
2634 |
1 |
|
|
T11 |
11 |
|
T12 |
12 |
|
T13 |
13 |
auto[1] |
auto[1] |
165 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T13 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48915 |
1 |
|
|
T1 |
6 |
|
T2 |
98 |
|
T3 |
9 |
auto[0] |
auto[1] |
1777 |
1 |
|
|
T2 |
9 |
|
T18 |
15 |
|
T95 |
6 |
auto[1] |
auto[0] |
2647 |
1 |
|
|
T11 |
11 |
|
T12 |
13 |
|
T13 |
15 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T11 |
1 |
|
T87 |
1 |
|
T18 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48887 |
1 |
|
|
T1 |
6 |
|
T2 |
99 |
|
T3 |
9 |
auto[0] |
auto[1] |
1805 |
1 |
|
|
T2 |
8 |
|
T18 |
16 |
|
T95 |
10 |
auto[1] |
auto[0] |
2636 |
1 |
|
|
T11 |
12 |
|
T12 |
13 |
|
T13 |
14 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T13 |
1 |
|
T34 |
1 |
|
T86 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48901 |
1 |
|
|
T1 |
6 |
|
T2 |
96 |
|
T3 |
9 |
auto[0] |
auto[1] |
1791 |
1 |
|
|
T2 |
11 |
|
T18 |
16 |
|
T95 |
10 |
auto[1] |
auto[0] |
2671 |
1 |
|
|
T11 |
11 |
|
T12 |
13 |
|
T13 |
13 |
auto[1] |
auto[1] |
128 |
1 |
|
|
T11 |
1 |
|
T13 |
2 |
|
T87 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36105 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T28 |
12 |
|
T29 |
10 |
|
T39 |
12 |
auto[1] |
auto[0] |
15606 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
auto[1] |
auto[1] |
728 |
1 |
|
|
T16 |
8 |
|
T19 |
6 |
|
T89 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36102 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1055 |
1 |
|
|
T28 |
13 |
|
T29 |
11 |
|
T39 |
19 |
auto[1] |
auto[0] |
15666 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
auto[1] |
auto[1] |
668 |
1 |
|
|
T16 |
10 |
|
T19 |
10 |
|
T89 |
10 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35763 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1394 |
1 |
|
|
T15 |
11 |
|
T32 |
3 |
|
T62 |
7 |
auto[1] |
auto[0] |
15494 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
auto[1] |
auto[1] |
840 |
1 |
|
|
T50 |
15 |
|
T210 |
7 |
|
T92 |
13 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36096 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1061 |
1 |
|
|
T28 |
11 |
|
T29 |
6 |
|
T39 |
13 |
auto[1] |
auto[0] |
15614 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
auto[1] |
auto[1] |
720 |
1 |
|
|
T16 |
5 |
|
T19 |
5 |
|
T89 |
12 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32313 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
4844 |
1 |
|
|
T10 |
89 |
|
T28 |
9 |
|
T29 |
3 |
auto[1] |
auto[0] |
15578 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
auto[1] |
auto[1] |
756 |
1 |
|
|
T16 |
6 |
|
T19 |
14 |
|
T89 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36100 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1057 |
1 |
|
|
T11 |
1 |
|
T13 |
1 |
|
T86 |
1 |
auto[1] |
auto[0] |
15476 |
1 |
|
|
T1 |
6 |
|
T2 |
81 |
|
T12 |
12 |
auto[1] |
auto[1] |
858 |
1 |
|
|
T2 |
10 |
|
T12 |
1 |
|
T17 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36055 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1102 |
1 |
|
|
T86 |
1 |
|
T18 |
18 |
|
T211 |
2 |
auto[1] |
auto[0] |
15475 |
1 |
|
|
T1 |
6 |
|
T2 |
81 |
|
T12 |
13 |
auto[1] |
auto[1] |
859 |
1 |
|
|
T2 |
10 |
|
T18 |
11 |
|
T50 |
38 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36094 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1063 |
1 |
|
|
T13 |
1 |
|
T86 |
2 |
|
T94 |
1 |
auto[1] |
auto[0] |
15461 |
1 |
|
|
T1 |
6 |
|
T2 |
84 |
|
T12 |
12 |
auto[1] |
auto[1] |
873 |
1 |
|
|
T2 |
7 |
|
T12 |
1 |
|
T17 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36115 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1042 |
1 |
|
|
T13 |
2 |
|
T34 |
1 |
|
T86 |
1 |
auto[1] |
auto[0] |
15467 |
1 |
|
|
T1 |
6 |
|
T2 |
80 |
|
T12 |
12 |
auto[1] |
auto[1] |
867 |
1 |
|
|
T2 |
11 |
|
T12 |
1 |
|
T17 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36132 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1025 |
1 |
|
|
T11 |
1 |
|
T87 |
1 |
|
T18 |
7 |
auto[1] |
auto[0] |
15430 |
1 |
|
|
T1 |
6 |
|
T2 |
82 |
|
T12 |
13 |
auto[1] |
auto[1] |
904 |
1 |
|
|
T2 |
9 |
|
T18 |
10 |
|
T50 |
35 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36076 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1081 |
1 |
|
|
T11 |
1 |
|
T13 |
2 |
|
T87 |
2 |
auto[1] |
auto[0] |
15496 |
1 |
|
|
T1 |
6 |
|
T2 |
80 |
|
T12 |
13 |
auto[1] |
auto[1] |
838 |
1 |
|
|
T2 |
11 |
|
T18 |
11 |
|
T50 |
24 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36119 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T28 |
10 |
|
T29 |
7 |
|
T39 |
10 |
auto[1] |
auto[0] |
15625 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
auto[1] |
auto[1] |
709 |
1 |
|
|
T16 |
8 |
|
T19 |
12 |
|
T89 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36086 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1071 |
1 |
|
|
T28 |
11 |
|
T29 |
11 |
|
T39 |
17 |
auto[1] |
auto[0] |
15615 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T12 |
13 |
auto[1] |
auto[1] |
719 |
1 |
|
|
T16 |
7 |
|
T19 |
6 |
|
T89 |
5 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35589 |
1 |
|
|
T2 |
16 |
|
T3 |
9 |
|
T9 |
9 |
auto[0] |
auto[1] |
1568 |
1 |
|
|
T11 |
12 |
|
T13 |
15 |
|
T34 |
10 |
auto[1] |
auto[0] |
15103 |
1 |
|
|
T1 |
6 |
|
T2 |
91 |
|
T16 |
60 |
auto[1] |
auto[1] |
1231 |
1 |
|
|
T12 |
13 |
|
T17 |
15 |
|
T50 |
41 |