Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103566975

1

T1

87644

T2

219356

T3

2967

auto[1]

1405231

1

T2

3332

T11

198

T12

98

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103565640

1

T1

87644

T2

219552

T3

2967

auto[1]

1406566

1

T2

3136

T11

99

T12

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7365969	1			T1	604		T2	21505		T3	926
auto[IdleSt]	21126849	1			T1	18167		T2	33303		T3	240
auto[ClkMuxSt]	34897	1			T1	6		T2	24		T3	18
auto[CntIncrSt]	34678	1			T1	6		T2	24		T3	9
auto[CntProgSt]	1760044	1			T1	471		T2	315		T3	82
auto[TransCheckSt]	27089	1			T1	6		T2	24		T3	9
auto[TokenHashSt]	40240693	1			T1	64568		T2	19004		T3	333
auto[FlashRmaSt]	28286	1			T1	18		T2	78		T3	9
auto[TokenCheck0St]	12528	1			T1	6		T2	24		T3	9
auto[TokenCheck1St]	9342	1			T1	6		T2	24		T3	9
auto[TransProgSt]	463261	1			T1	283		T2	403		T3	81
auto[PostTransSt]	12820633	1			T1	3503		T2	3885		T3	1242
auto[ScrapSt]	289373	1			T2	58		T14	43		T45	3
auto[EscalateSt]	7188026	1			T2	33313		T11	723		T12	4854
auto[InvalidSt]	13568551	1			T2	110697		T11	519		T12	9991

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1987	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13568551	1			T2	110697		T11	519		T12	9991
EscalateSt	7188026	1			T2	33313		T11	723		T12	4854
ScrapSt	289373	1			T2	58		T14	43		T45	3
PostTransSt	12820633	1			T1	3503		T2	3885		T3	1242
TransProgSt	463261	1			T1	283		T2	403		T3	81
TokenCheck1St	9342	1			T1	6		T2	24		T3	9
TokenCheck0St	12528	1			T1	6		T2	24		T3	9
FlashRmaSt	28286	1			T1	18		T2	78		T3	9
TokenHashSt	40240693	1			T1	64568		T2	19004		T3	333
TransCheckSt	27089	1			T1	6		T2	24		T3	9
CntProgSt	1760044	1			T1	471		T2	315		T3	82
CntIncrSt	34678	1			T1	6		T2	24		T3	9
ClkMuxSt	34897	1			T1	6		T2	24		T3	18
IdleSt	21126849	1			T1	18167		T2	33303		T3	240
ResetSt	7365969	1			T1	604		T2	21505		T3	926
arcs[ResetSt=>IdleSt]	53617	1			T1	6		T2	104		T3	9
arcs[IdleSt=>ScrapSt]	298	1			T2	3		T14	1		T45	2
arcs[IdleSt=>ClkMuxSt]	34750	1			T1	6		T2	24		T3	9
arcs[ClkMuxSt=>CntIncrSt]	34678	1			T1	6		T2	24		T3	9
arcs[CntIncrSt=>PostTransSt]	1790	1			T28	11		T29	11		T16	7
arcs[CntIncrSt=>CntProgSt]	32833	1			T1	6		T2	24		T3	9
arcs[CntProgSt=>PostTransSt]	4712	1			T15	11		T28	12		T29	10
arcs[CntProgSt=>TransCheckSt]	27089	1			T1	6		T2	24		T3	9
arcs[TransCheckSt=>PostTransSt]	3562	1			T28	10		T29	7		T16	8
arcs[TransCheckSt=>TokenHashSt]	23386	1			T1	6		T2	24		T3	9
arcs[TokenHashSt=>PostTransSt]	10066	1			T10	89		T28	26		T29	20
arcs[TokenHashSt=>FlashRmaSt]	12625	1			T1	6		T2	24		T3	9
arcs[FlashRmaSt=>TokenCheck0St]	12528	1			T1	6		T2	24		T3	9
arcs[TokenCheck0St=>PostTransSt]	3157	1			T28	13		T29	10		T30	6
arcs[TokenCheck0St=>TokenCheck1St]	9342	1			T1	6		T2	24		T3	9
arcs[TokenCheck1St=>PostTransSt]	683	1			T29	1		T33	10		T39	2
arcs[TransProgSt=>PostTransSt]	7783	1			T1	6		T2	24		T3	9
arcs[IdleSt=>EscalateSt]	205	1			T31	7		T55	3		T57	8
arcs[ClkMuxSt=>EscalateSt]	72	1			T31	1		T55	1		T56	1
arcs[CntIncrSt=>EscalateSt]	55	1			T31	2		T55	1		T56	1
arcs[CntProgSt=>EscalateSt]	1032	1			T31	27		T55	5		T56	46
arcs[TransCheckSt=>EscalateSt]	141	1			T55	2		T56	1		T57	8
arcs[TokenHashSt=>EscalateSt]	695	1			T31	5		T55	15		T56	10
arcs[FlashRmaSt=>EscalateSt]	97	1			T31	5		T55	3		T56	1
arcs[TokenCheck0St=>EscalateSt]	29	1			T55	1		T59	1		T60	1
arcs[TokenCheck1St=>EscalateSt]	158	1			T31	4		T55	2		T56	2
arcs[TransProgSt=>EscalateSt]	718	1			T31	16		T55	12		T56	25
arcs[PostTransSt=>EscalateSt]	4957	1			T15	11		T28	12		T29	10
arcs[InvalidSt=>EscalateSt]	14312	1			T2	66		T11	3		T12	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7365784	1			T1	604		T2	21505		T3	926
auto[0]	auto[IdleSt]	21126713	1			T1	18167		T2	33303		T3	240
auto[0]	auto[ClkMuxSt]	34851	1			T1	6		T2	24		T3	18
auto[0]	auto[CntIncrSt]	34636	1			T1	6		T2	24		T3	9
auto[0]	auto[CntProgSt]	1759362	1			T1	471		T2	315		T3	82
auto[0]	auto[TransCheckSt]	26982	1			T1	6		T2	24		T3	9
auto[0]	auto[TokenHashSt]	40240238	1			T1	64568		T2	19004		T3	333
auto[0]	auto[FlashRmaSt]	28223	1			T1	18		T2	78		T3	9
auto[0]	auto[TokenCheck0St]	12508	1			T1	6		T2	24		T3	9
auto[0]	auto[TokenCheck1St]	9239	1			T1	6		T2	24		T3	9
auto[0]	auto[TransProgSt]	462782	1			T1	283		T2	403		T3	81
auto[0]	auto[PostTransSt]	12818125	1			T1	3503		T2	3885		T3	1242
auto[0]	auto[ScrapSt]	289315	1			T2	58		T14	43		T45	3
auto[0]	auto[EscalateSt]	5794831	1			T2	30015		T11	527		T12	4757
auto[0]	auto[InvalidSt]	13561399	1			T2	110663		T11	517		T12	9990
auto[1]	auto[ResetSt]	185	1			T31	4		T55	5		T56	3
auto[1]	auto[IdleSt]	136	1			T31	4		T57	7		T207	3
auto[1]	auto[ClkMuxSt]	46	1			T31	1		T56	1		T57	1
auto[1]	auto[CntIncrSt]	42	1			T31	1		T55	1		T56	1
auto[1]	auto[CntProgSt]	682	1			T31	18		T55	3		T56	30
auto[1]	auto[TransCheckSt]	107	1			T55	1		T56	1		T57	6
auto[1]	auto[TokenHashSt]	455	1			T31	2		T55	10		T56	8
auto[1]	auto[FlashRmaSt]	63	1			T31	4		T55	2		T57	2
auto[1]	auto[TokenCheck0St]	20	1			T207	2		T208	1		T209	1
auto[1]	auto[TokenCheck1St]	103	1			T31	4		T55	2		T56	2
auto[1]	auto[TransProgSt]	479	1			T31	8		T55	10		T56	17
auto[1]	auto[PostTransSt]	2508	1			T15	6		T28	5		T29	2
auto[1]	auto[ScrapSt]	58	1			T55	2		T56	1		T57	2
auto[1]	auto[EscalateSt]	1393195	1			T2	3298		T11	196		T12	97
auto[1]	auto[InvalidSt]	7152	1			T2	34		T11	2		T12	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7365800	1			T1	604		T2	21505		T3	926
auto[0]	auto[IdleSt]	21126707	1			T1	18167		T2	33303		T3	240
auto[0]	auto[ClkMuxSt]	34853	1			T1	6		T2	24		T3	18
auto[0]	auto[CntIncrSt]	34645	1			T1	6		T2	24		T3	9
auto[0]	auto[CntProgSt]	1759345	1			T1	471		T2	315		T3	82
auto[0]	auto[TransCheckSt]	27002	1			T1	6		T2	24		T3	9
auto[0]	auto[TokenHashSt]	40240237	1			T1	64568		T2	19004		T3	333
auto[0]	auto[FlashRmaSt]	28219	1			T1	18		T2	78		T3	9
auto[0]	auto[TokenCheck0St]	12511	1			T1	6		T2	24		T3	9
auto[0]	auto[TokenCheck1St]	9231	1			T1	6		T2	24		T3	9
auto[0]	auto[TransProgSt]	462775	1			T1	283		T2	403		T3	81
auto[0]	auto[PostTransSt]	12818120	1			T1	3503		T2	3885		T3	1242
auto[0]	auto[ScrapSt]	289326	1			T2	58		T14	43		T45	3
auto[0]	auto[EscalateSt]	5793491	1			T2	30209		T11	625		T12	4660
auto[0]	auto[InvalidSt]	13561391	1			T2	110665		T11	518		T12	9989
auto[1]	auto[ResetSt]	169	1			T31	5		T55	2		T56	6
auto[1]	auto[IdleSt]	142	1			T31	7		T55	3		T57	8
auto[1]	auto[ClkMuxSt]	44	1			T31	1		T55	1		T56	1
auto[1]	auto[CntIncrSt]	33	1			T31	1		T55	1		T57	1
auto[1]	auto[CntProgSt]	699	1			T31	18		T55	3		T56	28
auto[1]	auto[TransCheckSt]	87	1			T55	1		T57	6		T163	8
auto[1]	auto[TokenHashSt]	456	1			T31	4		T55	12		T56	4
auto[1]	auto[FlashRmaSt]	67	1			T31	4		T55	2		T56	1
auto[1]	auto[TokenCheck0St]	17	1			T55	1		T59	1		T60	1
auto[1]	auto[TokenCheck1St]	111	1			T31	4		T55	1		T56	1
auto[1]	auto[TransProgSt]	486	1			T31	12		T55	8		T56	18
auto[1]	auto[PostTransSt]	2513	1			T15	5		T28	7		T29	8
auto[1]	auto[ScrapSt]	47	1			T55	3		T56	1		T57	1
auto[1]	auto[EscalateSt]	1394535	1			T2	3104		T11	98		T12	194
auto[1]	auto[InvalidSt]	7160	1			T2	32		T11	1		T12	2