Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87783958

1

T1

29435

T2

4333

T3

45669

auto[1]

1301544

1

T2

495

T3

294

T10

693

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87805085

1

T1

29435

T2

4234

T3

45767

auto[1]

1280417

1

T2

594

T3

196

T10

693

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6278336	1			T1	569		T2	1380		T3	3137
auto[IdleSt]	19109623	1			T1	508		T2	1351		T3	11451
auto[ClkMuxSt]	33082	1			T1	6		T2	11		T3	7
auto[CntIncrSt]	32780	1			T1	6		T2	11		T3	7
auto[CntProgSt]	1437512	1			T1	282		T2	22		T3	74
auto[TransCheckSt]	25726	1			T1	6		T3	7		T10	68
auto[TokenHashSt]	36134530	1			T1	26968		T3	561		T10	3264
auto[FlashRmaSt]	26670	1			T1	16		T3	35		T10	66
auto[TokenCheck0St]	11899	1			T1	6		T3	7		T10	24
auto[TokenCheck1St]	8790	1			T1	6		T3	7		T10	14
auto[TransProgSt]	394762	1			T1	209		T3	96		T10	249
auto[PostTransSt]	10803795	1			T1	710		T2	657		T3	15551
auto[ScrapSt]	128290	1			T1	143		T4	11		T46	6
auto[EscalateSt]	5627177	1			T2	1396		T3	7198		T10	1997
auto[InvalidSt]	9030837	1			T3	7825		T12	1266		T4	13572

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1693	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9030837	1			T3	7825		T12	1266		T4	13572
EscalateSt	5627177	1			T2	1396		T3	7198		T10	1997
ScrapSt	128290	1			T1	143		T4	11		T46	6
PostTransSt	10803795	1			T1	710		T2	657		T3	15551
TransProgSt	394762	1			T1	209		T3	96		T10	249
TokenCheck1St	8790	1			T1	6		T3	7		T10	14
TokenCheck0St	11899	1			T1	6		T3	7		T10	24
FlashRmaSt	26670	1			T1	16		T3	35		T10	66
TokenHashSt	36134530	1			T1	26968		T3	561		T10	3264
TransCheckSt	25726	1			T1	6		T3	7		T10	68
CntProgSt	1437512	1			T1	282		T2	22		T3	74
CntIncrSt	32780	1			T1	6		T2	11		T3	7
ClkMuxSt	33082	1			T1	6		T2	11		T3	7
IdleSt	19109623	1			T1	508		T2	1351		T3	11451
ResetSt	6278336	1			T1	569		T2	1380		T3	3137
arcs[ResetSt=>IdleSt]	49481	1			T1	7		T2	12		T3	14
arcs[IdleSt=>ScrapSt]	280	1			T1	1		T4	1		T46	2
arcs[IdleSt=>ClkMuxSt]	32845	1			T1	6		T2	11		T3	7
arcs[ClkMuxSt=>CntIncrSt]	32780	1			T1	6		T2	11		T3	7
arcs[CntIncrSt=>PostTransSt]	1607	1			T10	8		T4	8		T42	12
arcs[CntIncrSt=>CntProgSt]	31112	1			T1	6		T2	11		T3	7
arcs[CntProgSt=>PostTransSt]	4381	1			T2	11		T10	14		T4	51
arcs[CntProgSt=>TransCheckSt]	25726	1			T1	6		T3	7		T10	68
arcs[TransCheckSt=>PostTransSt]	3433	1			T10	12		T11	34		T4	10
arcs[TransCheckSt=>TokenHashSt]	22180	1			T1	6		T3	7		T10	56
arcs[TokenHashSt=>PostTransSt]	9469	1			T10	32		T11	18		T4	34
arcs[TokenHashSt=>FlashRmaSt]	11999	1			T1	6		T3	7		T10	24
arcs[FlashRmaSt=>TokenCheck0St]	11899	1			T1	6		T3	7		T10	24
arcs[TokenCheck0St=>PostTransSt]	3072	1			T10	10		T11	23		T4	10
arcs[TokenCheck0St=>TokenCheck1St]	8790	1			T1	6		T3	7		T10	14
arcs[TokenCheck1St=>PostTransSt]	655	1			T10	3		T11	10		T4	1
arcs[TransProgSt=>PostTransSt]	7269	1			T1	6		T3	7		T10	11
arcs[IdleSt=>EscalateSt]	212	1			T46	10		T29	11		T59	11
arcs[ClkMuxSt=>EscalateSt]	65	1			T29	2		T59	3		T60	2
arcs[CntIncrSt=>EscalateSt]	61	1			T46	2		T31	2		T59	1
arcs[CntProgSt=>EscalateSt]	1005	1			T46	9		T29	30		T31	30
arcs[TransCheckSt=>EscalateSt]	113	1			T46	7		T29	1		T31	2
arcs[TokenHashSt=>EscalateSt]	712	1			T46	26		T29	12		T31	6
arcs[FlashRmaSt=>EscalateSt]	100	1			T46	1		T29	1		T31	2
arcs[TokenCheck0St=>EscalateSt]	37	1			T29	1		T59	1		T60	2
arcs[TokenCheck1St=>EscalateSt]	137	1			T46	4		T29	2		T31	4
arcs[TransProgSt=>EscalateSt]	729	1			T46	12		T29	21		T31	20
arcs[PostTransSt=>EscalateSt]	4620	1			T2	11		T10	14		T4	51
arcs[InvalidSt=>EscalateSt]	12254	1			T3	5		T12	7		T4	50

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6278140	1			T1	569		T2	1380		T3	3137
auto[0]	auto[IdleSt]	19109475	1			T1	508		T2	1351		T3	11451
auto[0]	auto[ClkMuxSt]	33046	1			T1	6		T2	11		T3	7
auto[0]	auto[CntIncrSt]	32738	1			T1	6		T2	11		T3	7
auto[0]	auto[CntProgSt]	1436844	1			T1	282		T2	22		T3	74
auto[0]	auto[TransCheckSt]	25642	1			T1	6		T3	7		T10	68
auto[0]	auto[TokenHashSt]	36134069	1			T1	26968		T3	561		T10	3264
auto[0]	auto[FlashRmaSt]	26604	1			T1	16		T3	35		T10	66
auto[0]	auto[TokenCheck0St]	11873	1			T1	6		T3	7		T10	24
auto[0]	auto[TokenCheck1St]	8699	1			T1	6		T3	7		T10	14
auto[0]	auto[TransProgSt]	394261	1			T1	209		T3	96		T10	249
auto[0]	auto[PostTransSt]	10801501	1			T1	710		T2	652		T3	15551
auto[0]	auto[ScrapSt]	128240	1			T1	143		T4	11		T46	4
auto[0]	auto[EscalateSt]	4336529	1			T2	906		T3	6907		T10	1311
auto[0]	auto[InvalidSt]	9024604	1			T3	7822		T12	1264		T4	13538
auto[1]	auto[ResetSt]	196	1			T46	4		T29	6		T31	5
auto[1]	auto[IdleSt]	148	1			T46	6		T29	6		T59	7
auto[1]	auto[ClkMuxSt]	36	1			T29	1		T59	2		T60	1
auto[1]	auto[CntIncrSt]	42	1			T46	2		T31	1		T59	1
auto[1]	auto[CntProgSt]	668	1			T46	7		T29	22		T31	21
auto[1]	auto[TransCheckSt]	84	1			T46	5		T29	1		T31	1
auto[1]	auto[TokenHashSt]	461	1			T46	19		T29	10		T31	4
auto[1]	auto[FlashRmaSt]	66	1			T29	1		T31	1		T59	1
auto[1]	auto[TokenCheck0St]	26	1			T29	1		T60	1		T216	1
auto[1]	auto[TokenCheck1St]	91	1			T46	3		T29	1		T31	2
auto[1]	auto[TransProgSt]	501	1			T46	7		T29	16		T31	16
auto[1]	auto[PostTransSt]	2294	1			T2	5		T10	7		T4	26
auto[1]	auto[ScrapSt]	50	1			T46	2		T29	1		T31	1
auto[1]	auto[EscalateSt]	1290648	1			T2	490		T3	291		T10	686
auto[1]	auto[InvalidSt]	6233	1			T3	3		T12	2		T4	34

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6278158	1			T1	569		T2	1380		T3	3137
auto[0]	auto[IdleSt]	19109497	1			T1	508		T2	1351		T3	11451
auto[0]	auto[ClkMuxSt]	33031	1			T1	6		T2	11		T3	7
auto[0]	auto[CntIncrSt]	32741	1			T1	6		T2	11		T3	7
auto[0]	auto[CntProgSt]	1436851	1			T1	282		T2	22		T3	74
auto[0]	auto[TransCheckSt]	25656	1			T1	6		T3	7		T10	68
auto[0]	auto[TokenHashSt]	36134054	1			T1	26968		T3	561		T10	3264
auto[0]	auto[FlashRmaSt]	26604	1			T1	16		T3	35		T10	66
auto[0]	auto[TokenCheck0St]	11877	1			T1	6		T3	7		T10	24
auto[0]	auto[TokenCheck1St]	8695	1			T1	6		T3	7		T10	14
auto[0]	auto[TransProgSt]	394273	1			T1	209		T3	96		T10	249
auto[0]	auto[PostTransSt]	10801392	1			T1	710		T2	651		T3	15551
auto[0]	auto[ScrapSt]	128251	1			T1	143		T4	11		T46	6
auto[0]	auto[EscalateSt]	4357496	1			T2	808		T3	7004		T10	1311
auto[0]	auto[InvalidSt]	9024816	1			T3	7823		T12	1261		T4	13556
auto[1]	auto[ResetSt]	178	1			T46	1		T29	7		T31	6
auto[1]	auto[IdleSt]	126	1			T46	7		T29	10		T59	6
auto[1]	auto[ClkMuxSt]	51	1			T29	2		T59	3		T60	1
auto[1]	auto[CntIncrSt]	39	1			T46	1		T31	2		T60	2
auto[1]	auto[CntProgSt]	661	1			T46	4		T29	17		T31	22
auto[1]	auto[TransCheckSt]	70	1			T46	4		T31	1		T60	2
auto[1]	auto[TokenHashSt]	476	1			T46	16		T29	6		T31	2
auto[1]	auto[FlashRmaSt]	66	1			T46	1		T29	1		T31	1
auto[1]	auto[TokenCheck0St]	22	1			T29	1		T59	1		T60	1
auto[1]	auto[TokenCheck1St]	95	1			T46	2		T29	2		T31	3
auto[1]	auto[TransProgSt]	489	1			T46	8		T29	14		T31	10
auto[1]	auto[PostTransSt]	2403	1			T2	6		T10	7		T4	25
auto[1]	auto[ScrapSt]	39	1			T29	1		T31	1		T59	1
auto[1]	auto[EscalateSt]	1269681	1			T2	588		T3	194		T10	686
auto[1]	auto[InvalidSt]	6021	1			T3	2		T12	5		T4	16