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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 97.89 95.95 93.31 100.00 98.55 98.51 95.94


Total test records in report: 994
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T810 /workspace/coverage/default/16.lc_ctrl_state_failure.3228516575 May 19 01:04:39 PM PDT 24 May 19 01:05:01 PM PDT 24 198117615 ps
T811 /workspace/coverage/default/9.lc_ctrl_prog_failure.1886874853 May 19 01:03:58 PM PDT 24 May 19 01:04:04 PM PDT 24 111837529 ps
T812 /workspace/coverage/default/9.lc_ctrl_jtag_errors.3874437621 May 19 01:03:57 PM PDT 24 May 19 01:04:26 PM PDT 24 29729951048 ps
T813 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3639563014 May 19 01:04:06 PM PDT 24 May 19 01:04:17 PM PDT 24 3077289561 ps
T814 /workspace/coverage/default/44.lc_ctrl_jtag_access.136810917 May 19 01:06:13 PM PDT 24 May 19 01:06:18 PM PDT 24 750353818 ps
T815 /workspace/coverage/default/41.lc_ctrl_errors.824241064 May 19 01:06:05 PM PDT 24 May 19 01:06:24 PM PDT 24 377270429 ps
T816 /workspace/coverage/default/25.lc_ctrl_state_failure.3169878960 May 19 01:05:12 PM PDT 24 May 19 01:05:34 PM PDT 24 252257032 ps
T817 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2773759972 May 19 01:04:16 PM PDT 24 May 19 01:04:27 PM PDT 24 444923988 ps
T818 /workspace/coverage/default/48.lc_ctrl_security_escalation.4061001482 May 19 01:06:24 PM PDT 24 May 19 01:06:33 PM PDT 24 729283963 ps
T819 /workspace/coverage/default/8.lc_ctrl_jtag_errors.1899701416 May 19 01:03:53 PM PDT 24 May 19 01:04:21 PM PDT 24 6774113614 ps
T820 /workspace/coverage/default/39.lc_ctrl_security_escalation.3224522646 May 19 01:06:02 PM PDT 24 May 19 01:06:14 PM PDT 24 438789277 ps
T821 /workspace/coverage/default/33.lc_ctrl_prog_failure.2675508438 May 19 01:05:39 PM PDT 24 May 19 01:05:43 PM PDT 24 544287817 ps
T822 /workspace/coverage/default/34.lc_ctrl_errors.1201003847 May 19 01:05:46 PM PDT 24 May 19 01:05:55 PM PDT 24 636510032 ps
T823 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2596615596 May 19 01:05:51 PM PDT 24 May 19 01:06:00 PM PDT 24 808461888 ps
T824 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3719640947 May 19 01:05:54 PM PDT 24 May 19 01:05:56 PM PDT 24 43876694 ps
T825 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2146837076 May 19 01:02:42 PM PDT 24 May 19 01:02:43 PM PDT 24 12754072 ps
T826 /workspace/coverage/default/11.lc_ctrl_security_escalation.2610869870 May 19 01:04:07 PM PDT 24 May 19 01:04:16 PM PDT 24 212047849 ps
T827 /workspace/coverage/default/40.lc_ctrl_sec_mubi.1774179376 May 19 01:06:02 PM PDT 24 May 19 01:06:21 PM PDT 24 1444883900 ps
T828 /workspace/coverage/default/21.lc_ctrl_stress_all.2055054214 May 19 01:05:00 PM PDT 24 May 19 01:09:59 PM PDT 24 122085429292 ps
T829 /workspace/coverage/default/24.lc_ctrl_errors.195006379 May 19 01:05:05 PM PDT 24 May 19 01:05:19 PM PDT 24 859517886 ps
T830 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2963428112 May 19 01:04:10 PM PDT 24 May 19 01:04:22 PM PDT 24 534469848 ps
T831 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1712977358 May 19 01:03:58 PM PDT 24 May 19 01:04:11 PM PDT 24 2418567799 ps
T832 /workspace/coverage/default/45.lc_ctrl_smoke.4145152515 May 19 01:06:32 PM PDT 24 May 19 01:06:34 PM PDT 24 84544908 ps
T833 /workspace/coverage/default/11.lc_ctrl_jtag_access.2336684085 May 19 01:04:09 PM PDT 24 May 19 01:04:13 PM PDT 24 229155910 ps
T834 /workspace/coverage/default/32.lc_ctrl_smoke.1451294881 May 19 01:05:32 PM PDT 24 May 19 01:05:34 PM PDT 24 60865419 ps
T835 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.4109047765 May 19 01:04:15 PM PDT 24 May 19 01:04:18 PM PDT 24 41306260 ps
T836 /workspace/coverage/default/28.lc_ctrl_alert_test.2919492804 May 19 01:05:29 PM PDT 24 May 19 01:05:31 PM PDT 24 19681790 ps
T837 /workspace/coverage/default/47.lc_ctrl_state_failure.1252825913 May 19 01:06:25 PM PDT 24 May 19 01:06:49 PM PDT 24 267384542 ps
T838 /workspace/coverage/default/36.lc_ctrl_state_failure.3432966198 May 19 01:05:50 PM PDT 24 May 19 01:06:23 PM PDT 24 270219535 ps
T839 /workspace/coverage/default/32.lc_ctrl_alert_test.2965334308 May 19 01:05:41 PM PDT 24 May 19 01:05:42 PM PDT 24 19448303 ps
T840 /workspace/coverage/default/34.lc_ctrl_jtag_access.634866837 May 19 01:05:45 PM PDT 24 May 19 01:05:58 PM PDT 24 1754275878 ps
T841 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1880318158 May 19 01:03:58 PM PDT 24 May 19 01:04:19 PM PDT 24 539287265 ps
T842 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3894904549 May 19 01:03:11 PM PDT 24 May 19 01:03:25 PM PDT 24 729294795 ps
T843 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3926902135 May 19 01:05:02 PM PDT 24 May 19 01:06:05 PM PDT 24 1345606819 ps
T844 /workspace/coverage/default/1.lc_ctrl_prog_failure.1349351160 May 19 01:02:25 PM PDT 24 May 19 01:02:29 PM PDT 24 58929147 ps
T845 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1216792680 May 19 01:04:48 PM PDT 24 May 19 01:05:04 PM PDT 24 1213311383 ps
T846 /workspace/coverage/default/0.lc_ctrl_stress_all.1697622916 May 19 01:02:23 PM PDT 24 May 19 01:04:59 PM PDT 24 6765814393 ps
T847 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.936803009 May 19 01:04:08 PM PDT 24 May 19 01:05:09 PM PDT 24 6235180705 ps
T848 /workspace/coverage/default/19.lc_ctrl_state_failure.2832206225 May 19 01:04:49 PM PDT 24 May 19 01:05:21 PM PDT 24 1365508960 ps
T849 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.4053923504 May 19 01:05:56 PM PDT 24 May 19 01:06:08 PM PDT 24 6045715204 ps
T850 /workspace/coverage/default/28.lc_ctrl_stress_all.3984629766 May 19 01:05:22 PM PDT 24 May 19 01:07:43 PM PDT 24 24551084199 ps
T851 /workspace/coverage/default/32.lc_ctrl_state_failure.3739210663 May 19 01:05:42 PM PDT 24 May 19 01:06:13 PM PDT 24 621798598 ps
T852 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.279093494 May 19 01:05:52 PM PDT 24 May 19 01:05:53 PM PDT 24 10899786 ps
T76 /workspace/coverage/default/2.lc_ctrl_alert_test.3515525539 May 19 01:02:52 PM PDT 24 May 19 01:02:55 PM PDT 24 52643299 ps
T853 /workspace/coverage/default/5.lc_ctrl_alert_test.533508673 May 19 01:03:30 PM PDT 24 May 19 01:03:32 PM PDT 24 29675567 ps
T854 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.4177926285 May 19 01:05:08 PM PDT 24 May 19 01:05:18 PM PDT 24 5950667836 ps
T855 /workspace/coverage/default/32.lc_ctrl_prog_failure.1133077161 May 19 01:05:37 PM PDT 24 May 19 01:05:42 PM PDT 24 144009365 ps
T856 /workspace/coverage/default/3.lc_ctrl_jtag_priority.146163985 May 19 01:03:07 PM PDT 24 May 19 01:03:14 PM PDT 24 257753763 ps
T857 /workspace/coverage/default/29.lc_ctrl_security_escalation.1297899365 May 19 01:05:27 PM PDT 24 May 19 01:05:39 PM PDT 24 572065435 ps
T858 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1960896488 May 19 01:04:11 PM PDT 24 May 19 01:04:26 PM PDT 24 1967887668 ps
T859 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1602769072 May 19 01:05:39 PM PDT 24 May 19 01:05:54 PM PDT 24 3576467024 ps
T860 /workspace/coverage/default/5.lc_ctrl_state_post_trans.216084271 May 19 01:03:16 PM PDT 24 May 19 01:03:22 PM PDT 24 99545220 ps
T861 /workspace/coverage/default/18.lc_ctrl_smoke.2232223440 May 19 01:04:56 PM PDT 24 May 19 01:05:00 PM PDT 24 48562296 ps
T862 /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.111497566 May 19 01:06:01 PM PDT 24 May 19 01:06:03 PM PDT 24 51071280 ps
T863 /workspace/coverage/default/4.lc_ctrl_security_escalation.1725564062 May 19 01:03:04 PM PDT 24 May 19 01:03:12 PM PDT 24 1314596431 ps
T864 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1267281307 May 19 01:03:53 PM PDT 24 May 19 01:04:09 PM PDT 24 6076369891 ps
T865 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3662205818 May 19 01:04:19 PM PDT 24 May 19 01:14:18 PM PDT 24 64099200825 ps
T866 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.4157069359 May 19 01:05:13 PM PDT 24 May 19 01:05:33 PM PDT 24 534703106 ps
T867 /workspace/coverage/default/22.lc_ctrl_security_escalation.3726549680 May 19 01:05:01 PM PDT 24 May 19 01:05:17 PM PDT 24 1860384131 ps
T113 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3826296638 May 19 12:58:50 PM PDT 24 May 19 12:58:53 PM PDT 24 1058480140 ps
T118 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3541392963 May 19 12:58:23 PM PDT 24 May 19 12:58:25 PM PDT 24 707543538 ps
T114 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1637584198 May 19 12:58:20 PM PDT 24 May 19 12:58:22 PM PDT 24 192463567 ps
T868 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3150419175 May 19 12:58:44 PM PDT 24 May 19 12:58:50 PM PDT 24 186773750 ps
T137 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2933440133 May 19 12:58:35 PM PDT 24 May 19 12:58:37 PM PDT 24 64484746 ps
T138 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2801276320 May 19 12:58:10 PM PDT 24 May 19 12:58:12 PM PDT 24 19074259 ps
T869 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4183041677 May 19 12:58:47 PM PDT 24 May 19 12:58:50 PM PDT 24 186986109 ps
T870 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1829640911 May 19 12:58:37 PM PDT 24 May 19 12:58:40 PM PDT 24 70892113 ps
T139 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3918491886 May 19 12:58:54 PM PDT 24 May 19 12:58:55 PM PDT 24 13711632 ps
T115 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4081504554 May 19 12:58:43 PM PDT 24 May 19 12:58:46 PM PDT 24 80935690 ps
T136 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1111294571 May 19 12:58:57 PM PDT 24 May 19 12:59:00 PM PDT 24 70964982 ps
T104 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.829985026 May 19 12:58:47 PM PDT 24 May 19 12:58:52 PM PDT 24 67300537 ps
T205 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4071404807 May 19 12:58:54 PM PDT 24 May 19 12:58:56 PM PDT 24 39080249 ps
T153 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3818219796 May 19 12:58:58 PM PDT 24 May 19 12:59:00 PM PDT 24 18951213 ps
T108 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.150213361 May 19 12:58:54 PM PDT 24 May 19 12:58:58 PM PDT 24 77415504 ps
T871 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1505741828 May 19 12:58:55 PM PDT 24 May 19 12:58:57 PM PDT 24 58366028 ps
T173 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3102426544 May 19 12:58:48 PM PDT 24 May 19 12:58:51 PM PDT 24 72109878 ps
T872 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3919768946 May 19 12:58:26 PM PDT 24 May 19 12:58:28 PM PDT 24 99151367 ps
T105 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3046954213 May 19 12:59:02 PM PDT 24 May 19 12:59:05 PM PDT 24 44373824 ps
T154 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2701551167 May 19 12:58:24 PM PDT 24 May 19 12:58:25 PM PDT 24 87463044 ps
T873 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3819039532 May 19 12:58:42 PM PDT 24 May 19 12:58:45 PM PDT 24 46852261 ps
T135 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2739850944 May 19 12:58:25 PM PDT 24 May 19 12:58:38 PM PDT 24 15337898610 ps
T874 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3518782136 May 19 12:58:10 PM PDT 24 May 19 12:58:12 PM PDT 24 27847749 ps
T875 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.391981937 May 19 12:58:15 PM PDT 24 May 19 12:58:34 PM PDT 24 6822814756 ps
T206 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.517658801 May 19 12:58:56 PM PDT 24 May 19 12:58:58 PM PDT 24 24425741 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3144479796 May 19 12:58:09 PM PDT 24 May 19 12:58:14 PM PDT 24 234442754 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.368236719 May 19 12:58:22 PM PDT 24 May 19 12:58:25 PM PDT 24 65594346 ps
T155 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4255887028 May 19 12:58:15 PM PDT 24 May 19 12:58:17 PM PDT 24 156213407 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2985247535 May 19 12:58:08 PM PDT 24 May 19 12:58:10 PM PDT 24 188333047 ps
T156 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3380171993 May 19 12:58:28 PM PDT 24 May 19 12:58:30 PM PDT 24 38239039 ps
T111 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.327136025 May 19 12:58:49 PM PDT 24 May 19 12:58:53 PM PDT 24 68187699 ps
T106 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2174338530 May 19 12:58:53 PM PDT 24 May 19 12:58:55 PM PDT 24 23815151 ps
T110 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3569570210 May 19 12:58:16 PM PDT 24 May 19 12:58:20 PM PDT 24 78729064 ps
T109 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4127716015 May 19 12:58:42 PM PDT 24 May 19 12:58:45 PM PDT 24 91215679 ps
T112 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3745977456 May 19 12:58:43 PM PDT 24 May 19 12:58:46 PM PDT 24 64540260 ps
T174 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1846383438 May 19 12:59:05 PM PDT 24 May 19 12:59:07 PM PDT 24 14540072 ps
T157 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.237149771 May 19 12:59:00 PM PDT 24 May 19 12:59:03 PM PDT 24 58617189 ps
T122 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3172594898 May 19 12:58:58 PM PDT 24 May 19 12:59:03 PM PDT 24 50816348 ps
T158 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3913254209 May 19 12:58:10 PM PDT 24 May 19 12:58:15 PM PDT 24 534750059 ps
T207 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2761870514 May 19 12:58:47 PM PDT 24 May 19 12:58:50 PM PDT 24 38602682 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3728617619 May 19 12:58:57 PM PDT 24 May 19 12:59:01 PM PDT 24 972004581 ps
T208 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.150007021 May 19 12:58:49 PM PDT 24 May 19 12:58:52 PM PDT 24 138715235 ps
T209 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4065719209 May 19 12:58:16 PM PDT 24 May 19 12:58:18 PM PDT 24 102986804 ps
T159 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2038448580 May 19 12:58:30 PM PDT 24 May 19 12:58:32 PM PDT 24 192642069 ps
T880 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1737593594 May 19 12:58:42 PM PDT 24 May 19 12:58:48 PM PDT 24 348435683 ps
T123 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1272451146 May 19 12:58:52 PM PDT 24 May 19 12:58:57 PM PDT 24 412744193 ps
T210 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.326015941 May 19 12:58:32 PM PDT 24 May 19 12:58:34 PM PDT 24 30707179 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.603746621 May 19 12:58:10 PM PDT 24 May 19 12:58:13 PM PDT 24 14665225 ps
T882 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3165421543 May 19 12:58:49 PM PDT 24 May 19 12:58:52 PM PDT 24 19334391 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3190301643 May 19 12:58:27 PM PDT 24 May 19 12:58:30 PM PDT 24 654069493 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3754140455 May 19 12:58:06 PM PDT 24 May 19 12:58:09 PM PDT 24 92845672 ps
T197 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2706552323 May 19 12:58:23 PM PDT 24 May 19 12:58:25 PM PDT 24 27529025 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2940774609 May 19 12:58:45 PM PDT 24 May 19 12:58:47 PM PDT 24 27494817 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3216010892 May 19 12:58:09 PM PDT 24 May 19 12:58:14 PM PDT 24 1149316880 ps
T887 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2072054829 May 19 12:58:52 PM PDT 24 May 19 12:58:54 PM PDT 24 46883509 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2830763580 May 19 12:58:10 PM PDT 24 May 19 12:58:13 PM PDT 24 28918973 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1984769531 May 19 12:58:28 PM PDT 24 May 19 12:58:30 PM PDT 24 313367893 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3439270949 May 19 12:58:16 PM PDT 24 May 19 12:58:19 PM PDT 24 834663894 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3606044848 May 19 12:58:47 PM PDT 24 May 19 12:58:50 PM PDT 24 138703878 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2530453488 May 19 12:58:19 PM PDT 24 May 19 12:58:28 PM PDT 24 2835597835 ps
T893 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3193673085 May 19 12:58:59 PM PDT 24 May 19 12:59:02 PM PDT 24 94341499 ps
T894 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.869734562 May 19 12:58:56 PM PDT 24 May 19 12:59:00 PM PDT 24 83424423 ps
T895 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4050599467 May 19 12:58:15 PM PDT 24 May 19 12:58:17 PM PDT 24 45480785 ps
T896 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.479696235 May 19 12:59:00 PM PDT 24 May 19 12:59:02 PM PDT 24 37590623 ps
T897 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.505513234 May 19 12:58:49 PM PDT 24 May 19 12:58:53 PM PDT 24 233639978 ps
T898 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2653487628 May 19 12:58:49 PM PDT 24 May 19 12:58:52 PM PDT 24 62698789 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3500160248 May 19 12:58:09 PM PDT 24 May 19 12:58:11 PM PDT 24 198629270 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3806675654 May 19 12:58:31 PM PDT 24 May 19 12:58:36 PM PDT 24 1483050548 ps
T900 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.764049838 May 19 12:58:48 PM PDT 24 May 19 12:58:50 PM PDT 24 30235146 ps
T901 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1164734697 May 19 12:58:44 PM PDT 24 May 19 12:58:46 PM PDT 24 14562372 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3717998239 May 19 12:58:32 PM PDT 24 May 19 12:58:34 PM PDT 24 81521228 ps
T903 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1228918835 May 19 12:58:34 PM PDT 24 May 19 12:58:38 PM PDT 24 64444133 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.822043525 May 19 12:58:04 PM PDT 24 May 19 12:58:07 PM PDT 24 19908149 ps
T127 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2814307354 May 19 12:58:45 PM PDT 24 May 19 12:58:49 PM PDT 24 320098924 ps
T905 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1145040941 May 19 12:58:49 PM PDT 24 May 19 12:58:52 PM PDT 24 168817969 ps
T198 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4275275424 May 19 12:58:37 PM PDT 24 May 19 12:58:39 PM PDT 24 43324492 ps
T906 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.570548858 May 19 12:59:04 PM PDT 24 May 19 12:59:06 PM PDT 24 97608298 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2143893349 May 19 12:58:44 PM PDT 24 May 19 12:58:48 PM PDT 24 132183946 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.634390955 May 19 12:58:26 PM PDT 24 May 19 12:58:28 PM PDT 24 49284591 ps
T909 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2641239457 May 19 12:58:43 PM PDT 24 May 19 12:58:45 PM PDT 24 33067965 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1503508581 May 19 12:58:27 PM PDT 24 May 19 12:58:30 PM PDT 24 27590613 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3024425525 May 19 12:58:24 PM PDT 24 May 19 12:58:26 PM PDT 24 72385860 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.239842214 May 19 12:58:37 PM PDT 24 May 19 12:59:24 PM PDT 24 9241525651 ps
T913 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1208410683 May 19 12:58:23 PM PDT 24 May 19 12:58:25 PM PDT 24 68456067 ps
T914 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3033676632 May 19 12:58:58 PM PDT 24 May 19 12:59:01 PM PDT 24 22399589 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1717537253 May 19 12:58:31 PM PDT 24 May 19 12:58:44 PM PDT 24 546704281 ps
T916 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1406270462 May 19 12:58:59 PM PDT 24 May 19 12:59:01 PM PDT 24 23348175 ps
T917 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3330348985 May 19 12:59:04 PM PDT 24 May 19 12:59:06 PM PDT 24 54863634 ps
T918 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2845103859 May 19 12:58:54 PM PDT 24 May 19 12:58:56 PM PDT 24 14648711 ps
T919 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.730325810 May 19 12:58:58 PM PDT 24 May 19 12:59:00 PM PDT 24 42622932 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2837324609 May 19 12:58:45 PM PDT 24 May 19 12:58:49 PM PDT 24 757943322 ps
T921 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2087474114 May 19 12:58:04 PM PDT 24 May 19 12:58:08 PM PDT 24 37391845 ps
T922 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2871911203 May 19 12:58:28 PM PDT 24 May 19 12:58:40 PM PDT 24 5134115483 ps
T923 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.481947494 May 19 12:58:53 PM PDT 24 May 19 12:58:55 PM PDT 24 43126964 ps
T924 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1063379722 May 19 12:58:37 PM PDT 24 May 19 12:58:39 PM PDT 24 53165844 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.191843886 May 19 12:58:05 PM PDT 24 May 19 12:58:09 PM PDT 24 591180481 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.9946974 May 19 12:58:34 PM PDT 24 May 19 12:58:37 PM PDT 24 53150343 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1532517965 May 19 12:58:11 PM PDT 24 May 19 12:58:14 PM PDT 24 89858086 ps
T928 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2266225023 May 19 12:59:05 PM PDT 24 May 19 12:59:07 PM PDT 24 42541288 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2690243733 May 19 12:58:47 PM PDT 24 May 19 12:59:17 PM PDT 24 1399163894 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1473374632 May 19 12:58:22 PM PDT 24 May 19 12:58:24 PM PDT 24 73800704 ps
T931 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1202946301 May 19 12:58:43 PM PDT 24 May 19 12:58:45 PM PDT 24 369669397 ps
T932 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4117498164 May 19 12:58:46 PM PDT 24 May 19 12:58:48 PM PDT 24 46572241 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.738938427 May 19 12:58:43 PM PDT 24 May 19 12:58:47 PM PDT 24 80063550 ps
T199 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1565506972 May 19 12:58:10 PM PDT 24 May 19 12:58:13 PM PDT 24 13303699 ps
T934 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2907251086 May 19 12:58:49 PM PDT 24 May 19 12:58:52 PM PDT 24 179976769 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2415102202 May 19 12:58:34 PM PDT 24 May 19 12:58:52 PM PDT 24 4876859337 ps
T936 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2916485149 May 19 12:58:54 PM PDT 24 May 19 12:58:56 PM PDT 24 53302450 ps
T133 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.580094691 May 19 12:58:10 PM PDT 24 May 19 12:58:13 PM PDT 24 59961855 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4022943657 May 19 12:58:43 PM PDT 24 May 19 12:58:45 PM PDT 24 14702788 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3632441959 May 19 12:58:36 PM PDT 24 May 19 12:58:39 PM PDT 24 111952440 ps
T124 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2617310849 May 19 12:58:36 PM PDT 24 May 19 12:58:42 PM PDT 24 106974254 ps
T200 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.873189314 May 19 12:58:05 PM PDT 24 May 19 12:58:08 PM PDT 24 18040168 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1247544215 May 19 12:58:04 PM PDT 24 May 19 12:58:13 PM PDT 24 1349677039 ps
T132 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2795747055 May 19 12:58:21 PM PDT 24 May 19 12:58:23 PM PDT 24 269098361 ps
T116 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4253539335 May 19 12:58:44 PM PDT 24 May 19 12:58:48 PM PDT 24 82537988 ps
T940 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.363868858 May 19 12:58:59 PM PDT 24 May 19 12:59:02 PM PDT 24 50248788 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1419552779 May 19 12:58:04 PM PDT 24 May 19 12:58:12 PM PDT 24 219647827 ps
T942 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3926027501 May 19 12:58:41 PM PDT 24 May 19 12:59:01 PM PDT 24 3511256127 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.135450658 May 19 12:58:44 PM PDT 24 May 19 12:58:47 PM PDT 24 37779046 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2436269336 May 19 12:58:16 PM PDT 24 May 19 12:58:25 PM PDT 24 1827769251 ps
T120 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1522506429 May 19 12:58:46 PM PDT 24 May 19 12:58:50 PM PDT 24 202055221 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3896470709 May 19 12:58:48 PM PDT 24 May 19 12:59:11 PM PDT 24 9499979956 ps
T946 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2805021938 May 19 12:58:27 PM PDT 24 May 19 12:58:28 PM PDT 24 50422505 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.679292919 May 19 12:58:10 PM PDT 24 May 19 12:58:13 PM PDT 24 144505372 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2504680286 May 19 12:58:44 PM PDT 24 May 19 12:58:47 PM PDT 24 68980452 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1190222187 May 19 12:58:41 PM PDT 24 May 19 12:58:43 PM PDT 24 27593992 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2135050383 May 19 12:58:34 PM PDT 24 May 19 12:58:36 PM PDT 24 133572057 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2713765780 May 19 12:58:34 PM PDT 24 May 19 12:58:36 PM PDT 24 17242907 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3262764412 May 19 12:58:43 PM PDT 24 May 19 12:58:45 PM PDT 24 63848459 ps
T953 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1264707574 May 19 12:58:52 PM PDT 24 May 19 12:58:54 PM PDT 24 47175202 ps
T130 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.282738727 May 19 12:58:58 PM PDT 24 May 19 12:59:01 PM PDT 24 241935502 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1103064673 May 19 12:58:04 PM PDT 24 May 19 12:58:07 PM PDT 24 35583406 ps
T128 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.321466852 May 19 12:58:53 PM PDT 24 May 19 12:58:57 PM PDT 24 96113710 ps
T955 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3636958832 May 19 12:58:48 PM PDT 24 May 19 12:58:53 PM PDT 24 167071741 ps
T956 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3085885779 May 19 12:58:05 PM PDT 24 May 19 12:58:12 PM PDT 24 190776647 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3501024047 May 19 12:58:48 PM PDT 24 May 19 12:58:51 PM PDT 24 55583620 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.126096882 May 19 12:58:46 PM PDT 24 May 19 12:58:50 PM PDT 24 161590322 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2754956727 May 19 12:58:48 PM PDT 24 May 19 12:58:52 PM PDT 24 38408209 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.400178723 May 19 12:58:21 PM PDT 24 May 19 12:58:24 PM PDT 24 48800332 ps
T960 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3740490305 May 19 12:59:02 PM PDT 24 May 19 12:59:05 PM PDT 24 63942039 ps
T961 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2454759681 May 19 12:58:47 PM PDT 24 May 19 12:58:53 PM PDT 24 501186498 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.519747009 May 19 12:58:27 PM PDT 24 May 19 12:58:30 PM PDT 24 276560339 ps
T963 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1265701264 May 19 12:58:48 PM PDT 24 May 19 12:58:51 PM PDT 24 15825774 ps
T129 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.743608385 May 19 12:58:57 PM PDT 24 May 19 12:59:00 PM PDT 24 52472830 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3760765677 May 19 12:58:09 PM PDT 24 May 19 12:58:12 PM PDT 24 60676189 ps
T201 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2805781172 May 19 12:58:58 PM PDT 24 May 19 12:59:00 PM PDT 24 20009916 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1009197350 May 19 12:58:34 PM PDT 24 May 19 12:58:37 PM PDT 24 253286982 ps
T202 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2413138643 May 19 12:58:10 PM PDT 24 May 19 12:58:12 PM PDT 24 34259118 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3474381600 May 19 12:58:36 PM PDT 24 May 19 12:58:39 PM PDT 24 95319573 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2271397726 May 19 12:58:20 PM PDT 24 May 19 12:58:22 PM PDT 24 45823181 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1281941918 May 19 12:58:42 PM PDT 24 May 19 12:58:45 PM PDT 24 137134957 ps
T969 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.658251385 May 19 12:58:36 PM PDT 24 May 19 12:58:41 PM PDT 24 639951154 ps
T117 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1650110089 May 19 12:58:59 PM PDT 24 May 19 12:59:03 PM PDT 24 1226049403 ps
T970 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2479306019 May 19 12:58:10 PM PDT 24 May 19 12:58:29 PM PDT 24 5674512454 ps
T971 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3934734536 May 19 12:58:58 PM PDT 24 May 19 12:58:59 PM PDT 24 49728884 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.955121343 May 19 12:58:20 PM PDT 24 May 19 12:58:26 PM PDT 24 865339495 ps
T125 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2184708657 May 19 12:58:53 PM PDT 24 May 19 12:58:56 PM PDT 24 115508379 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3803806338 May 19 12:58:26 PM PDT 24 May 19 12:58:28 PM PDT 24 41915134 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2914059133 May 19 12:58:04 PM PDT 24 May 19 12:58:07 PM PDT 24 66871316 ps
T203 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2950323804 May 19 12:58:05 PM PDT 24 May 19 12:58:08 PM PDT 24 157229583 ps
T126 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.568721849 May 19 12:58:48 PM PDT 24 May 19 12:58:52 PM PDT 24 60208630 ps
T975 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.392726635 May 19 12:58:16 PM PDT 24 May 19 12:58:18 PM PDT 24 447177483 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3737234000 May 19 12:58:43 PM PDT 24 May 19 12:58:45 PM PDT 24 552975075 ps
T977 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1978946073 May 19 12:58:04 PM PDT 24 May 19 12:58:08 PM PDT 24 68324153 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4056921322 May 19 12:58:50 PM PDT 24 May 19 12:58:52 PM PDT 24 81525529 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2939867429 May 19 12:58:36 PM PDT 24 May 19 12:58:47 PM PDT 24 359928298 ps
T980 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1671884438 May 19 12:58:47 PM PDT 24 May 19 12:58:49 PM PDT 24 131872302 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4237862018 May 19 12:58:23 PM PDT 24 May 19 12:58:26 PM PDT 24 98719339 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1469423884 May 19 12:58:37 PM PDT 24 May 19 12:58:40 PM PDT 24 70280958 ps
T983 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2339653666 May 19 12:58:04 PM PDT 24 May 19 12:58:06 PM PDT 24 145513058 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.208234707 May 19 12:58:35 PM PDT 24 May 19 12:58:37 PM PDT 24 47639763 ps
T985 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.874448702 May 19 12:58:10 PM PDT 24 May 19 12:58:13 PM PDT 24 249262746 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.397128619 May 19 12:58:20 PM PDT 24 May 19 12:58:22 PM PDT 24 43803831 ps
T987 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3491478462 May 19 12:58:21 PM PDT 24 May 19 12:58:24 PM PDT 24 182743496 ps
T131 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3268261086 May 19 12:58:53 PM PDT 24 May 19 12:58:56 PM PDT 24 184055032 ps
T988 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1181762544 May 19 12:58:53 PM PDT 24 May 19 12:58:56 PM PDT 24 136938882 ps
T989 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1592993118 May 19 12:58:48 PM PDT 24 May 19 12:58:53 PM PDT 24 139027818 ps
T990 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.616029861 May 19 12:58:59 PM PDT 24 May 19 12:59:03 PM PDT 24 74528674 ps
T991 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.996582592 May 19 12:58:53 PM PDT 24 May 19 12:58:57 PM PDT 24 90774872 ps
T992 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.699199175 May 19 12:58:37 PM PDT 24 May 19 12:58:39 PM PDT 24 20893182 ps
T993 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3365340283 May 19 12:58:09 PM PDT 24 May 19 12:58:11 PM PDT 24 109259189 ps
T204 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4227070607 May 19 12:58:53 PM PDT 24 May 19 12:58:55 PM PDT 24 14175821 ps
T121 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1029814283 May 19 12:58:56 PM PDT 24 May 19 12:59:03 PM PDT 24 204949193 ps
T994 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.243288775 May 19 12:58:49 PM PDT 24 May 19 12:58:56 PM PDT 24 774221589 ps

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3842719034
Short name T4
Test name
Test status
Simulation time 26185552001 ps
CPU time 303.49 seconds
Started May 19 01:04:53 PM PDT 24
Finished May 19 01:09:58 PM PDT 24
Peak memory 252004 kb
Host smart-83a2fe07-7b07-423b-9fb3-49a0af93e335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842719034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3842719034
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1396680717
Short name T46
Test name
Test status
Simulation time 1660023825 ps
CPU time 9.89 seconds
Started May 19 01:05:31 PM PDT 24
Finished May 19 01:05:42 PM PDT 24
Peak memory 218148 kb
Host smart-5e5609b6-6e84-441c-9dd5-c6dbbd4de9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396680717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1396680717
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2035707740
Short name T53
Test name
Test status
Simulation time 549264577 ps
CPU time 22.38 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 219000 kb
Host smart-e85c4a69-49f9-4d75-a097-d34ef0b91a54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035707740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2035707740
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3234287740
Short name T50
Test name
Test status
Simulation time 118994277175 ps
CPU time 1083.74 seconds
Started May 19 01:02:27 PM PDT 24
Finished May 19 01:20:32 PM PDT 24
Peak memory 496972 kb
Host smart-fc48cc87-4827-42d3-9dd4-fd124be9d898
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3234287740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.3234287740
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.150213361
Short name T108
Test name
Test status
Simulation time 77415504 ps
CPU time 2.78 seconds
Started May 19 12:58:54 PM PDT 24
Finished May 19 12:58:58 PM PDT 24
Peak memory 217704 kb
Host smart-54cb8944-2ea3-4a28-bf14-e6a3190b0821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150213361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.150213361
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.6781868
Short name T29
Test name
Test status
Simulation time 388145420 ps
CPU time 9.6 seconds
Started May 19 01:05:33 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 218072 kb
Host smart-ff5bd4c2-8960-4486-b881-2a48dd359472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6781868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.6781868
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.504456145
Short name T38
Test name
Test status
Simulation time 37423169 ps
CPU time 0.76 seconds
Started May 19 01:06:27 PM PDT 24
Finished May 19 01:06:29 PM PDT 24
Peak memory 208468 kb
Host smart-00a86e12-ba88-485c-abd6-42cca97ef9cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504456145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.504456145
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.450648203
Short name T62
Test name
Test status
Simulation time 1104691726 ps
CPU time 39.8 seconds
Started May 19 01:02:25 PM PDT 24
Finished May 19 01:03:07 PM PDT 24
Peak memory 268832 kb
Host smart-9ba3fc52-dab9-4827-aae0-6dc060d8e58c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450648203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.450648203
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2289583956
Short name T6
Test name
Test status
Simulation time 589564743 ps
CPU time 8.4 seconds
Started May 19 01:02:37 PM PDT 24
Finished May 19 01:02:46 PM PDT 24
Peak memory 209548 kb
Host smart-d520ebe5-ac8e-46d1-86c0-4bf0ecf89d8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289583956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2289583956
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2291978135
Short name T14
Test name
Test status
Simulation time 451226527 ps
CPU time 10.34 seconds
Started May 19 01:06:04 PM PDT 24
Finished May 19 01:06:15 PM PDT 24
Peak memory 217992 kb
Host smart-d039698c-c68a-435f-ab4e-81e889ee1efc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291978135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2291978135
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.829985026
Short name T104
Test name
Test status
Simulation time 67300537 ps
CPU time 2.84 seconds
Started May 19 12:58:47 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 217736 kb
Host smart-d903ad29-de57-4314-b870-3164d927f766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829985026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.829985026
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3056336217
Short name T169
Test name
Test status
Simulation time 1789968470 ps
CPU time 11.08 seconds
Started May 19 01:05:57 PM PDT 24
Finished May 19 01:06:09 PM PDT 24
Peak memory 218032 kb
Host smart-0fda226e-a119-4bbd-9c32-1487dea4a857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056336217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3056336217
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.566907896
Short name T21
Test name
Test status
Simulation time 141807335 ps
CPU time 0.94 seconds
Started May 19 01:05:35 PM PDT 24
Finished May 19 01:05:37 PM PDT 24
Peak memory 209660 kb
Host smart-3dc0b70e-c6ba-4180-8290-2b397647a60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566907896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.566907896
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1637584198
Short name T114
Test name
Test status
Simulation time 192463567 ps
CPU time 1.21 seconds
Started May 19 12:58:20 PM PDT 24
Finished May 19 12:58:22 PM PDT 24
Peak memory 210532 kb
Host smart-e4de1d6b-6566-4c0a-816f-6d00d6880865
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637584198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1637584198
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2413138643
Short name T202
Test name
Test status
Simulation time 34259118 ps
CPU time 1.03 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:12 PM PDT 24
Peak memory 210640 kb
Host smart-57442256-8539-4dcd-9411-761127eee549
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413138643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2413138643
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1654183709
Short name T45
Test name
Test status
Simulation time 1408728395 ps
CPU time 12.94 seconds
Started May 19 01:03:38 PM PDT 24
Finished May 19 01:03:52 PM PDT 24
Peak memory 217992 kb
Host smart-39a7f108-c1f0-4695-823f-8866715f93b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654183709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1654183709
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2814307354
Short name T127
Test name
Test status
Simulation time 320098924 ps
CPU time 2.81 seconds
Started May 19 12:58:45 PM PDT 24
Finished May 19 12:58:49 PM PDT 24
Peak memory 221928 kb
Host smart-0685f9ca-a256-453b-a2ba-63a9a752352d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814307354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2814307354
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4064039605
Short name T64
Test name
Test status
Simulation time 15465585659 ps
CPU time 157.16 seconds
Started May 19 01:04:31 PM PDT 24
Finished May 19 01:07:09 PM PDT 24
Peak memory 269036 kb
Host smart-dc41f463-a6ea-4e2b-acc7-ac1f6f937290
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064039605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4064039605
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1650110089
Short name T117
Test name
Test status
Simulation time 1226049403 ps
CPU time 4.06 seconds
Started May 19 12:58:59 PM PDT 24
Finished May 19 12:59:03 PM PDT 24
Peak memory 217524 kb
Host smart-dc3a1e5b-22a6-4df0-bebd-d33b477e6af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650110089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1650110089
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.869734562
Short name T894
Test name
Test status
Simulation time 83424423 ps
CPU time 2.58 seconds
Started May 19 12:58:56 PM PDT 24
Finished May 19 12:59:00 PM PDT 24
Peak memory 217752 kb
Host smart-3a6ee6d3-2819-4485-a974-fb6291160604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869734562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.869734562
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2184708657
Short name T125
Test name
Test status
Simulation time 115508379 ps
CPU time 2.54 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:56 PM PDT 24
Peak memory 221564 kb
Host smart-73cb612b-8331-4c4d-b571-52caed4dfae3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184708657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2184708657
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1972641359
Short name T35
Test name
Test status
Simulation time 917758824 ps
CPU time 8.97 seconds
Started May 19 01:02:47 PM PDT 24
Finished May 19 01:02:56 PM PDT 24
Peak memory 217948 kb
Host smart-69408b35-be4b-456b-852e-b12b6a6892a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972641359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1972641359
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.4252828241
Short name T103
Test name
Test status
Simulation time 5223778074 ps
CPU time 106.84 seconds
Started May 19 01:04:15 PM PDT 24
Finished May 19 01:06:03 PM PDT 24
Peak memory 276480 kb
Host smart-b0784b46-422f-4bbe-b25c-0cba71467332
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252828241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.4252828241
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.282738727
Short name T130
Test name
Test status
Simulation time 241935502 ps
CPU time 1.99 seconds
Started May 19 12:58:58 PM PDT 24
Finished May 19 12:59:01 PM PDT 24
Peak memory 222152 kb
Host smart-a2aee154-87db-44c5-8dc9-add4960e8330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282738727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.282738727
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.150007021
Short name T208
Test name
Test status
Simulation time 138715235 ps
CPU time 1.45 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 211368 kb
Host smart-c873fba7-37d5-4351-a900-a279fd2e167d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150007021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.150007021
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2700185697
Short name T11
Test name
Test status
Simulation time 2395921032 ps
CPU time 12.08 seconds
Started May 19 01:05:41 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 218128 kb
Host smart-a6bc451d-86de-4904-8a8a-79512d0290c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700185697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2700185697
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.580094691
Short name T133
Test name
Test status
Simulation time 59961855 ps
CPU time 2.15 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:13 PM PDT 24
Peak memory 222056 kb
Host smart-34a6809a-0bd2-4998-a06b-105ece4305d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580094691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.580094691
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1029814283
Short name T121
Test name
Test status
Simulation time 204949193 ps
CPU time 6.17 seconds
Started May 19 12:58:56 PM PDT 24
Finished May 19 12:59:03 PM PDT 24
Peak memory 217600 kb
Host smart-547f3636-2c9a-4939-ac32-aaab26d96418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029814283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1029814283
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3124669379
Short name T212
Test name
Test status
Simulation time 19058060 ps
CPU time 0.92 seconds
Started May 19 01:02:29 PM PDT 24
Finished May 19 01:02:30 PM PDT 24
Peak memory 209800 kb
Host smart-14b1a31b-e5d0-4034-be0c-04aee8a1d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124669379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3124669379
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1473498219
Short name T214
Test name
Test status
Simulation time 19635180 ps
CPU time 0.9 seconds
Started May 19 01:03:00 PM PDT 24
Finished May 19 01:03:02 PM PDT 24
Peak memory 209800 kb
Host smart-ec6e195f-f4e9-492a-8e25-455670cb5e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473498219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1473498219
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1522506429
Short name T120
Test name
Test status
Simulation time 202055221 ps
CPU time 3.25 seconds
Started May 19 12:58:46 PM PDT 24
Finished May 19 12:58:50 PM PDT 24
Peak memory 217712 kb
Host smart-6d5b8a83-72d4-40dd-a82d-c8219781bfaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522506429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1522506429
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3268261086
Short name T131
Test name
Test status
Simulation time 184055032 ps
CPU time 1.87 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:56 PM PDT 24
Peak memory 221764 kb
Host smart-e87775a3-8d0e-4b3d-b5aa-9ba48597e4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268261086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3268261086
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3046954213
Short name T105
Test name
Test status
Simulation time 44373824 ps
CPU time 1.9 seconds
Started May 19 12:59:02 PM PDT 24
Finished May 19 12:59:05 PM PDT 24
Peak memory 221884 kb
Host smart-315b2578-eb86-4a9d-9f4c-34d2bf4e0dea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046954213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3046954213
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3806675654
Short name T119
Test name
Test status
Simulation time 1483050548 ps
CPU time 4.84 seconds
Started May 19 12:58:31 PM PDT 24
Finished May 19 12:58:36 PM PDT 24
Peak memory 217628 kb
Host smart-6e066ff8-aef8-40bc-894c-9a1950c8e969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806675654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3806675654
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2650050206
Short name T58
Test name
Test status
Simulation time 7554464022 ps
CPU time 147.99 seconds
Started May 19 01:05:44 PM PDT 24
Finished May 19 01:08:13 PM PDT 24
Peak memory 308328 kb
Host smart-ff14c1f9-49d6-4c9e-aaa0-b45c85f95fde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650050206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2650050206
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2620843521
Short name T1
Test name
Test status
Simulation time 1226537874 ps
CPU time 8.21 seconds
Started May 19 01:02:47 PM PDT 24
Finished May 19 01:02:55 PM PDT 24
Peak memory 218136 kb
Host smart-768126f4-7c5b-4b38-a782-a1c8b43abbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620843521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2620843521
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.873189314
Short name T200
Test name
Test status
Simulation time 18040168 ps
CPU time 1.18 seconds
Started May 19 12:58:05 PM PDT 24
Finished May 19 12:58:08 PM PDT 24
Peak memory 209704 kb
Host smart-26567f6e-b94e-47b7-920c-313228ac14d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873189314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.873189314
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.822043525
Short name T904
Test name
Test status
Simulation time 19908149 ps
CPU time 1.13 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:07 PM PDT 24
Peak memory 209268 kb
Host smart-046137f2-887f-438b-8c58-7cb3f1f9ce96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822043525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.822043525
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2339653666
Short name T983
Test name
Test status
Simulation time 145513058 ps
CPU time 1.16 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:06 PM PDT 24
Peak memory 217776 kb
Host smart-92054e98-8f79-45e7-9d73-4acaa0f160cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339653666 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2339653666
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2950323804
Short name T203
Test name
Test status
Simulation time 157229583 ps
CPU time 0.87 seconds
Started May 19 12:58:05 PM PDT 24
Finished May 19 12:58:08 PM PDT 24
Peak memory 209200 kb
Host smart-e9785ce0-d8ec-4a81-a9b7-236fbede462c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950323804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2950323804
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1978946073
Short name T977
Test name
Test status
Simulation time 68324153 ps
CPU time 2.2 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:08 PM PDT 24
Peak memory 208028 kb
Host smart-e3ebc122-123c-4f42-86c9-7fa7282c9056
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978946073 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1978946073
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1419552779
Short name T941
Test name
Test status
Simulation time 219647827 ps
CPU time 6.15 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:12 PM PDT 24
Peak memory 209196 kb
Host smart-3e214383-fda5-4628-b88b-2501422148d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419552779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1419552779
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2479306019
Short name T970
Test name
Test status
Simulation time 5674512454 ps
CPU time 18.48 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:29 PM PDT 24
Peak memory 208488 kb
Host smart-8b119662-3127-4b21-b13f-2e64b8838b7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479306019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2479306019
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2985247535
Short name T878
Test name
Test status
Simulation time 188333047 ps
CPU time 1.34 seconds
Started May 19 12:58:08 PM PDT 24
Finished May 19 12:58:10 PM PDT 24
Peak memory 210684 kb
Host smart-c6e0728a-b910-412b-b79e-0dabc29c1b76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985247535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2985247535
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3216010892
Short name T886
Test name
Test status
Simulation time 1149316880 ps
CPU time 2.98 seconds
Started May 19 12:58:09 PM PDT 24
Finished May 19 12:58:14 PM PDT 24
Peak memory 219236 kb
Host smart-e694872e-b478-41da-8b0b-2ad6d570b3a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321601
0892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3216010892
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2087474114
Short name T921
Test name
Test status
Simulation time 37391845 ps
CPU time 1.13 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:08 PM PDT 24
Peak memory 209280 kb
Host smart-5ffb107f-7159-40a3-bfa8-caced321c6cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087474114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2087474114
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1103064673
Short name T954
Test name
Test status
Simulation time 35583406 ps
CPU time 1 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:07 PM PDT 24
Peak memory 217580 kb
Host smart-483c818b-ffc8-4d9a-91d6-fd3804f9645a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103064673 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1103064673
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2830763580
Short name T888
Test name
Test status
Simulation time 28918973 ps
CPU time 1.47 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:13 PM PDT 24
Peak memory 209448 kb
Host smart-bd4e1e64-84cf-46af-aefb-d2738a05a06a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830763580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2830763580
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.191843886
Short name T925
Test name
Test status
Simulation time 591180481 ps
CPU time 2.55 seconds
Started May 19 12:58:05 PM PDT 24
Finished May 19 12:58:09 PM PDT 24
Peak memory 218440 kb
Host smart-2c6fd76f-0b72-44c7-b830-c33b3e875db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191843886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.191843886
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3365340283
Short name T993
Test name
Test status
Simulation time 109259189 ps
CPU time 1.9 seconds
Started May 19 12:58:09 PM PDT 24
Finished May 19 12:58:11 PM PDT 24
Peak memory 221796 kb
Host smart-6bc06e92-39aa-45f3-b2b7-8bbffed9abed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365340283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3365340283
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.679292919
Short name T947
Test name
Test status
Simulation time 144505372 ps
CPU time 1.66 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:13 PM PDT 24
Peak memory 209552 kb
Host smart-b244fc2b-d67f-4d1e-840f-20cda3969c55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679292919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.679292919
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2801276320
Short name T138
Test name
Test status
Simulation time 19074259 ps
CPU time 1.15 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:12 PM PDT 24
Peak memory 208564 kb
Host smart-bc61140d-616d-4537-959c-3b9036d44001
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801276320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2801276320
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3518782136
Short name T874
Test name
Test status
Simulation time 27847749 ps
CPU time 1.02 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:12 PM PDT 24
Peak memory 210296 kb
Host smart-56ba73a6-1b9e-46bf-97e5-c24cab6cd6dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518782136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3518782136
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.874448702
Short name T985
Test name
Test status
Simulation time 249262746 ps
CPU time 1.41 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:13 PM PDT 24
Peak memory 217792 kb
Host smart-f6640bdd-1f36-474d-ad9f-fc9dec0245ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874448702 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.874448702
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1565506972
Short name T199
Test name
Test status
Simulation time 13303699 ps
CPU time 0.89 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:13 PM PDT 24
Peak memory 209160 kb
Host smart-2e5991a7-3e1a-4c53-8e0c-d8ef2d59b02d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565506972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1565506972
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3500160248
Short name T899
Test name
Test status
Simulation time 198629270 ps
CPU time 1.35 seconds
Started May 19 12:58:09 PM PDT 24
Finished May 19 12:58:11 PM PDT 24
Peak memory 209136 kb
Host smart-5280f190-9b6c-42d4-a4cf-289388f472ea
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500160248 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3500160248
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3085885779
Short name T956
Test name
Test status
Simulation time 190776647 ps
CPU time 5.3 seconds
Started May 19 12:58:05 PM PDT 24
Finished May 19 12:58:12 PM PDT 24
Peak memory 208548 kb
Host smart-cd0c2fc3-cb7e-4b82-a198-2e27c633f14d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085885779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3085885779
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1247544215
Short name T939
Test name
Test status
Simulation time 1349677039 ps
CPU time 8.11 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:13 PM PDT 24
Peak memory 208548 kb
Host smart-b7da8308-55ed-4709-9e06-c50eada37d06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247544215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1247544215
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3754140455
Short name T884
Test name
Test status
Simulation time 92845672 ps
CPU time 1.81 seconds
Started May 19 12:58:06 PM PDT 24
Finished May 19 12:58:09 PM PDT 24
Peak memory 210912 kb
Host smart-2f20db62-ee3e-499b-b863-bd7068931943
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754140455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3754140455
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3913254209
Short name T158
Test name
Test status
Simulation time 534750059 ps
CPU time 3.59 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:15 PM PDT 24
Peak memory 217612 kb
Host smart-f02e118b-2897-4d90-892d-0c56b56dbf4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391325
4209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3913254209
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2914059133
Short name T974
Test name
Test status
Simulation time 66871316 ps
CPU time 1.54 seconds
Started May 19 12:58:04 PM PDT 24
Finished May 19 12:58:07 PM PDT 24
Peak memory 209256 kb
Host smart-523874d7-cd77-46dd-a4bf-7a6fe80a623f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914059133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2914059133
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.603746621
Short name T881
Test name
Test status
Simulation time 14665225 ps
CPU time 1.17 seconds
Started May 19 12:58:10 PM PDT 24
Finished May 19 12:58:13 PM PDT 24
Peak memory 209396 kb
Host smart-39777e98-2733-497a-bd51-5818f3e2e07c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603746621 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.603746621
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3760765677
Short name T964
Test name
Test status
Simulation time 60676189 ps
CPU time 1.45 seconds
Started May 19 12:58:09 PM PDT 24
Finished May 19 12:58:12 PM PDT 24
Peak memory 209444 kb
Host smart-612c29d8-ad16-43e0-aa87-f049123c0112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760765677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3760765677
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1532517965
Short name T927
Test name
Test status
Simulation time 89858086 ps
CPU time 2.36 seconds
Started May 19 12:58:11 PM PDT 24
Finished May 19 12:58:14 PM PDT 24
Peak memory 217696 kb
Host smart-28e5ce8b-2ba6-4ae6-a5b7-484b06c62024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532517965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1532517965
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.764049838
Short name T900
Test name
Test status
Simulation time 30235146 ps
CPU time 1.18 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:50 PM PDT 24
Peak memory 220464 kb
Host smart-cb34b066-f976-4282-a1ca-dc7453f3e55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764049838 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.764049838
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3165421543
Short name T882
Test name
Test status
Simulation time 19334391 ps
CPU time 1.03 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 208856 kb
Host smart-39445887-f2fa-4894-b524-a8e3bfaf65b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165421543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3165421543
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3636958832
Short name T955
Test name
Test status
Simulation time 167071741 ps
CPU time 3.12 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:53 PM PDT 24
Peak memory 217764 kb
Host smart-6b9d3fd1-42b5-490b-81fc-f9e5052eaa07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636958832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3636958832
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1671884438
Short name T980
Test name
Test status
Simulation time 131872302 ps
CPU time 1.68 seconds
Started May 19 12:58:47 PM PDT 24
Finished May 19 12:58:49 PM PDT 24
Peak memory 217712 kb
Host smart-113b6089-4a1b-4f27-bc05-20729f066ba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671884438 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1671884438
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.481947494
Short name T923
Test name
Test status
Simulation time 43126964 ps
CPU time 0.9 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:55 PM PDT 24
Peak memory 209296 kb
Host smart-c72e6a11-77c0-4399-886b-45df1bda9574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481947494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.481947494
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2653487628
Short name T898
Test name
Test status
Simulation time 62698789 ps
CPU time 1.12 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 209360 kb
Host smart-da7da055-aa31-49ef-ba66-88c4e00d74b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653487628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2653487628
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.243288775
Short name T994
Test name
Test status
Simulation time 774221589 ps
CPU time 5.08 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:56 PM PDT 24
Peak memory 217748 kb
Host smart-0c7f3bd1-afa9-403e-8ef8-924c87133ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243288775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.243288775
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2916485149
Short name T936
Test name
Test status
Simulation time 53302450 ps
CPU time 1.16 seconds
Started May 19 12:58:54 PM PDT 24
Finished May 19 12:58:56 PM PDT 24
Peak memory 217772 kb
Host smart-ba286c84-0810-46e7-b00e-862b03a07bf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916485149 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2916485149
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4227070607
Short name T204
Test name
Test status
Simulation time 14175821 ps
CPU time 0.94 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:55 PM PDT 24
Peak memory 209004 kb
Host smart-a110f415-7edc-45d4-a630-e01adacda4b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227070607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.4227070607
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1264707574
Short name T953
Test name
Test status
Simulation time 47175202 ps
CPU time 0.98 seconds
Started May 19 12:58:52 PM PDT 24
Finished May 19 12:58:54 PM PDT 24
Peak memory 209468 kb
Host smart-b63c9145-4a5c-4e29-aacf-9a193bb650d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264707574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1264707574
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.996582592
Short name T991
Test name
Test status
Simulation time 90774872 ps
CPU time 2.85 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:57 PM PDT 24
Peak memory 217704 kb
Host smart-4381ab50-7416-4ed8-977d-223e9c95cfc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996582592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.996582592
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2174338530
Short name T106
Test name
Test status
Simulation time 23815151 ps
CPU time 1.58 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:55 PM PDT 24
Peak memory 218864 kb
Host smart-e0f5c2b8-99b5-42e2-826f-4a25e04780e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174338530 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2174338530
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2072054829
Short name T887
Test name
Test status
Simulation time 46883509 ps
CPU time 0.9 seconds
Started May 19 12:58:52 PM PDT 24
Finished May 19 12:58:54 PM PDT 24
Peak memory 209156 kb
Host smart-9656dfb7-1e8e-4e34-9dbc-af6c6d3b9cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072054829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2072054829
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.517658801
Short name T206
Test name
Test status
Simulation time 24425741 ps
CPU time 1.36 seconds
Started May 19 12:58:56 PM PDT 24
Finished May 19 12:58:58 PM PDT 24
Peak memory 209460 kb
Host smart-0cf427fb-9bca-4671-abd8-9e750c225377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517658801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.517658801
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2845103859
Short name T918
Test name
Test status
Simulation time 14648711 ps
CPU time 0.95 seconds
Started May 19 12:58:54 PM PDT 24
Finished May 19 12:58:56 PM PDT 24
Peak memory 217628 kb
Host smart-8b7a0681-f918-486d-b688-85acf2ab9edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845103859 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2845103859
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1505741828
Short name T871
Test name
Test status
Simulation time 58366028 ps
CPU time 0.91 seconds
Started May 19 12:58:55 PM PDT 24
Finished May 19 12:58:57 PM PDT 24
Peak memory 209368 kb
Host smart-eb6bc56a-5a69-470c-9c82-593f3fd81069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505741828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1505741828
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4071404807
Short name T205
Test name
Test status
Simulation time 39080249 ps
CPU time 1.49 seconds
Started May 19 12:58:54 PM PDT 24
Finished May 19 12:58:56 PM PDT 24
Peak memory 211444 kb
Host smart-af99daf3-669c-471f-bb0c-18b019546868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071404807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.4071404807
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.321466852
Short name T128
Test name
Test status
Simulation time 96113710 ps
CPU time 2.3 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:57 PM PDT 24
Peak memory 217632 kb
Host smart-3eb8f785-a943-4f2d-929f-ee7da6b513bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321466852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.321466852
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3193673085
Short name T893
Test name
Test status
Simulation time 94341499 ps
CPU time 1.5 seconds
Started May 19 12:58:59 PM PDT 24
Finished May 19 12:59:02 PM PDT 24
Peak memory 217608 kb
Host smart-3c864437-bee1-4880-acb6-8115ff16be87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193673085 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3193673085
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3918491886
Short name T139
Test name
Test status
Simulation time 13711632 ps
CPU time 0.83 seconds
Started May 19 12:58:54 PM PDT 24
Finished May 19 12:58:55 PM PDT 24
Peak memory 209340 kb
Host smart-b6b7be20-dbe1-43e8-95c5-8f244c3bbb63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918491886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3918491886
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1111294571
Short name T136
Test name
Test status
Simulation time 70964982 ps
CPU time 1.69 seconds
Started May 19 12:58:57 PM PDT 24
Finished May 19 12:59:00 PM PDT 24
Peak memory 211404 kb
Host smart-f5f3a6de-2437-4585-b5f2-8c880f3785e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111294571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1111294571
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1272451146
Short name T123
Test name
Test status
Simulation time 412744193 ps
CPU time 3.85 seconds
Started May 19 12:58:52 PM PDT 24
Finished May 19 12:58:57 PM PDT 24
Peak memory 217684 kb
Host smart-62e8eb4c-9200-40d5-8f33-95464562d184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272451146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1272451146
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3033676632
Short name T914
Test name
Test status
Simulation time 22399589 ps
CPU time 1.84 seconds
Started May 19 12:58:58 PM PDT 24
Finished May 19 12:59:01 PM PDT 24
Peak memory 219952 kb
Host smart-74391aeb-c675-463d-9bb5-7000073ed811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033676632 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3033676632
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3934734536
Short name T971
Test name
Test status
Simulation time 49728884 ps
CPU time 0.91 seconds
Started May 19 12:58:58 PM PDT 24
Finished May 19 12:58:59 PM PDT 24
Peak memory 209428 kb
Host smart-40acff60-0d71-4237-adf9-eed9ae031a88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934734536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3934734536
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2266225023
Short name T928
Test name
Test status
Simulation time 42541288 ps
CPU time 1.33 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 12:59:07 PM PDT 24
Peak memory 209392 kb
Host smart-6b592688-4d9f-428d-b24c-df6db30f7f4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266225023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2266225023
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.363868858
Short name T940
Test name
Test status
Simulation time 50248788 ps
CPU time 1.67 seconds
Started May 19 12:58:59 PM PDT 24
Finished May 19 12:59:02 PM PDT 24
Peak memory 217700 kb
Host smart-c1846b69-acf8-48f6-8ecd-9fd1692db08b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363868858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.363868858
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1846383438
Short name T174
Test name
Test status
Simulation time 14540072 ps
CPU time 1.24 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 12:59:07 PM PDT 24
Peak memory 218752 kb
Host smart-553c6b61-0392-453f-9e48-e6c09573f541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846383438 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1846383438
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.479696235
Short name T896
Test name
Test status
Simulation time 37590623 ps
CPU time 0.81 seconds
Started May 19 12:59:00 PM PDT 24
Finished May 19 12:59:02 PM PDT 24
Peak memory 208460 kb
Host smart-b6749537-7196-4db8-9fc9-974c3c117da7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479696235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.479696235
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.237149771
Short name T157
Test name
Test status
Simulation time 58617189 ps
CPU time 2.11 seconds
Started May 19 12:59:00 PM PDT 24
Finished May 19 12:59:03 PM PDT 24
Peak memory 211512 kb
Host smart-fece402c-c82a-479c-97f9-791bff156f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237149771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.237149771
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.616029861
Short name T990
Test name
Test status
Simulation time 74528674 ps
CPU time 3.4 seconds
Started May 19 12:58:59 PM PDT 24
Finished May 19 12:59:03 PM PDT 24
Peak memory 217636 kb
Host smart-0a2f0d91-a7b2-45fc-b737-1b3e53d6d2a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616029861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.616029861
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.743608385
Short name T129
Test name
Test status
Simulation time 52472830 ps
CPU time 1.99 seconds
Started May 19 12:58:57 PM PDT 24
Finished May 19 12:59:00 PM PDT 24
Peak memory 221868 kb
Host smart-6ad14108-b010-4150-9d0a-8c837c5b906a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743608385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.743608385
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1406270462
Short name T916
Test name
Test status
Simulation time 23348175 ps
CPU time 1.2 seconds
Started May 19 12:58:59 PM PDT 24
Finished May 19 12:59:01 PM PDT 24
Peak memory 219608 kb
Host smart-7bd8cc05-8e0c-4906-9e72-e7ca697e13fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406270462 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1406270462
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3818219796
Short name T153
Test name
Test status
Simulation time 18951213 ps
CPU time 0.99 seconds
Started May 19 12:58:58 PM PDT 24
Finished May 19 12:59:00 PM PDT 24
Peak memory 209440 kb
Host smart-dde56f2c-c463-443e-b47f-3cb126236b7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818219796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3818219796
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.730325810
Short name T919
Test name
Test status
Simulation time 42622932 ps
CPU time 0.98 seconds
Started May 19 12:58:58 PM PDT 24
Finished May 19 12:59:00 PM PDT 24
Peak memory 209420 kb
Host smart-8b22e1f4-8bb9-4385-893e-6abde7787642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730325810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.730325810
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3740490305
Short name T960
Test name
Test status
Simulation time 63942039 ps
CPU time 1.51 seconds
Started May 19 12:59:02 PM PDT 24
Finished May 19 12:59:05 PM PDT 24
Peak memory 217700 kb
Host smart-ae1369c9-b8a4-4f69-b13c-f00abec5149c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740490305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3740490305
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3330348985
Short name T917
Test name
Test status
Simulation time 54863634 ps
CPU time 1.35 seconds
Started May 19 12:59:04 PM PDT 24
Finished May 19 12:59:06 PM PDT 24
Peak memory 218288 kb
Host smart-4a6f966d-fb72-4954-bd71-bdab1642afcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330348985 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3330348985
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2805781172
Short name T201
Test name
Test status
Simulation time 20009916 ps
CPU time 1.18 seconds
Started May 19 12:58:58 PM PDT 24
Finished May 19 12:59:00 PM PDT 24
Peak memory 209444 kb
Host smart-a9633434-5540-4dae-bccf-6e844da0bc22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805781172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2805781172
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.570548858
Short name T906
Test name
Test status
Simulation time 97608298 ps
CPU time 1.22 seconds
Started May 19 12:59:04 PM PDT 24
Finished May 19 12:59:06 PM PDT 24
Peak memory 209428 kb
Host smart-a1bc9c52-9d13-413c-abf0-37938f330134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570548858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.570548858
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3172594898
Short name T122
Test name
Test status
Simulation time 50816348 ps
CPU time 3.59 seconds
Started May 19 12:58:58 PM PDT 24
Finished May 19 12:59:03 PM PDT 24
Peak memory 218776 kb
Host smart-1aa6daf5-0f8b-4348-9f35-e2c703e558c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172594898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3172594898
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2701551167
Short name T154
Test name
Test status
Simulation time 87463044 ps
CPU time 1.04 seconds
Started May 19 12:58:24 PM PDT 24
Finished May 19 12:58:25 PM PDT 24
Peak memory 209372 kb
Host smart-0767272d-eba2-4d69-931a-1620435f5da4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701551167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2701551167
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1208410683
Short name T913
Test name
Test status
Simulation time 68456067 ps
CPU time 1.11 seconds
Started May 19 12:58:23 PM PDT 24
Finished May 19 12:58:25 PM PDT 24
Peak memory 209384 kb
Host smart-e4feaf5f-63d6-4528-9b88-a1e199cde9c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208410683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1208410683
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2706552323
Short name T197
Test name
Test status
Simulation time 27529025 ps
CPU time 1.09 seconds
Started May 19 12:58:23 PM PDT 24
Finished May 19 12:58:25 PM PDT 24
Peak memory 218120 kb
Host smart-777393f1-c983-406a-93f8-0f1639e9a57f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706552323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2706552323
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.392726635
Short name T975
Test name
Test status
Simulation time 447177483 ps
CPU time 1.22 seconds
Started May 19 12:58:16 PM PDT 24
Finished May 19 12:58:18 PM PDT 24
Peak memory 218796 kb
Host smart-950d533e-ee9a-421b-aa3e-7731c5c359f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392726635 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.392726635
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4065719209
Short name T209
Test name
Test status
Simulation time 102986804 ps
CPU time 0.76 seconds
Started May 19 12:58:16 PM PDT 24
Finished May 19 12:58:18 PM PDT 24
Peak memory 209124 kb
Host smart-01d33d13-a903-4483-a059-9b299b4abe7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065719209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4065719209
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3024425525
Short name T911
Test name
Test status
Simulation time 72385860 ps
CPU time 1.56 seconds
Started May 19 12:58:24 PM PDT 24
Finished May 19 12:58:26 PM PDT 24
Peak memory 209256 kb
Host smart-c5250d48-bfc3-4ab5-b85a-6d811940b2f0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024425525 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3024425525
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2436269336
Short name T944
Test name
Test status
Simulation time 1827769251 ps
CPU time 8.42 seconds
Started May 19 12:58:16 PM PDT 24
Finished May 19 12:58:25 PM PDT 24
Peak memory 207680 kb
Host smart-95efdca5-8beb-4ee5-a38c-be210bcbe570
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436269336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2436269336
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.391981937
Short name T875
Test name
Test status
Simulation time 6822814756 ps
CPU time 18.95 seconds
Started May 19 12:58:15 PM PDT 24
Finished May 19 12:58:34 PM PDT 24
Peak memory 209280 kb
Host smart-67147103-3f5c-4439-af7f-e1fb1b675f5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391981937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.391981937
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3144479796
Short name T876
Test name
Test status
Simulation time 234442754 ps
CPU time 3.33 seconds
Started May 19 12:58:09 PM PDT 24
Finished May 19 12:58:14 PM PDT 24
Peak memory 210864 kb
Host smart-885f8240-f00f-4835-a94c-6a13d704c8c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144479796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3144479796
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3439270949
Short name T890
Test name
Test status
Simulation time 834663894 ps
CPU time 2.01 seconds
Started May 19 12:58:16 PM PDT 24
Finished May 19 12:58:19 PM PDT 24
Peak memory 219260 kb
Host smart-a1c12ece-6141-4134-9937-ba99b2a59cbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343927
0949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3439270949
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3541392963
Short name T118
Test name
Test status
Simulation time 707543538 ps
CPU time 1.34 seconds
Started May 19 12:58:23 PM PDT 24
Finished May 19 12:58:25 PM PDT 24
Peak memory 209300 kb
Host smart-b483f7c5-b74c-4c47-9a48-3f9eac1423a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541392963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3541392963
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4050599467
Short name T895
Test name
Test status
Simulation time 45480785 ps
CPU time 1.07 seconds
Started May 19 12:58:15 PM PDT 24
Finished May 19 12:58:17 PM PDT 24
Peak memory 209300 kb
Host smart-47d81ce5-c97f-4507-992b-6d121306d572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050599467 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4050599467
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4255887028
Short name T155
Test name
Test status
Simulation time 156213407 ps
CPU time 1.33 seconds
Started May 19 12:58:15 PM PDT 24
Finished May 19 12:58:17 PM PDT 24
Peak memory 209416 kb
Host smart-93ad1f97-7ed2-4704-bb72-fca4fca00397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255887028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4255887028
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4237862018
Short name T981
Test name
Test status
Simulation time 98719339 ps
CPU time 1.77 seconds
Started May 19 12:58:23 PM PDT 24
Finished May 19 12:58:26 PM PDT 24
Peak memory 217724 kb
Host smart-adcb7466-9371-4de1-bc14-5e14809395f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237862018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.4237862018
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3569570210
Short name T110
Test name
Test status
Simulation time 78729064 ps
CPU time 3.3 seconds
Started May 19 12:58:16 PM PDT 24
Finished May 19 12:58:20 PM PDT 24
Peak memory 217672 kb
Host smart-f2a11953-884e-403d-b5d8-2ddbf6ed8cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569570210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3569570210
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3380171993
Short name T156
Test name
Test status
Simulation time 38239039 ps
CPU time 1.39 seconds
Started May 19 12:58:28 PM PDT 24
Finished May 19 12:58:30 PM PDT 24
Peak memory 209612 kb
Host smart-fc72136a-c65e-41d2-85da-866552e9a802
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380171993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3380171993
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2038448580
Short name T159
Test name
Test status
Simulation time 192642069 ps
CPU time 1.48 seconds
Started May 19 12:58:30 PM PDT 24
Finished May 19 12:58:32 PM PDT 24
Peak memory 209440 kb
Host smart-1040ed4a-c3ee-4ec9-8894-454f9d2c7933
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038448580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2038448580
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.397128619
Short name T986
Test name
Test status
Simulation time 43803831 ps
CPU time 1.02 seconds
Started May 19 12:58:20 PM PDT 24
Finished May 19 12:58:22 PM PDT 24
Peak memory 209636 kb
Host smart-5c7f3c44-345b-429f-b285-ce995af34c95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397128619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.397128619
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.634390955
Short name T908
Test name
Test status
Simulation time 49284591 ps
CPU time 1.19 seconds
Started May 19 12:58:26 PM PDT 24
Finished May 19 12:58:28 PM PDT 24
Peak memory 217604 kb
Host smart-4fc63029-178d-4355-ab00-e90589fd1fd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634390955 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.634390955
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2271397726
Short name T967
Test name
Test status
Simulation time 45823181 ps
CPU time 0.85 seconds
Started May 19 12:58:20 PM PDT 24
Finished May 19 12:58:22 PM PDT 24
Peak memory 208676 kb
Host smart-d3ffb527-4e32-4ae8-b567-b8046f05511b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271397726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2271397726
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.368236719
Short name T877
Test name
Test status
Simulation time 65594346 ps
CPU time 2.11 seconds
Started May 19 12:58:22 PM PDT 24
Finished May 19 12:58:25 PM PDT 24
Peak memory 209148 kb
Host smart-8555670a-09e2-414c-add0-ff93ace617c1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368236719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.368236719
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3728617619
Short name T879
Test name
Test status
Simulation time 972004581 ps
CPU time 3.35 seconds
Started May 19 12:58:57 PM PDT 24
Finished May 19 12:59:01 PM PDT 24
Peak memory 209116 kb
Host smart-8ead563d-62ab-4c74-9bd5-dd8b3a58bbc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728617619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3728617619
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2530453488
Short name T892
Test name
Test status
Simulation time 2835597835 ps
CPU time 8.32 seconds
Started May 19 12:58:19 PM PDT 24
Finished May 19 12:58:28 PM PDT 24
Peak memory 208600 kb
Host smart-d46c5f25-9d74-44e3-b80a-a23d680f0609
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530453488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2530453488
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.955121343
Short name T972
Test name
Test status
Simulation time 865339495 ps
CPU time 5.36 seconds
Started May 19 12:58:20 PM PDT 24
Finished May 19 12:58:26 PM PDT 24
Peak memory 222920 kb
Host smart-3f949243-a34b-4ed4-aa93-a18654d4fd11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955121
343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.955121343
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1473374632
Short name T930
Test name
Test status
Simulation time 73800704 ps
CPU time 1.32 seconds
Started May 19 12:58:22 PM PDT 24
Finished May 19 12:58:24 PM PDT 24
Peak memory 209260 kb
Host smart-19be5ea9-9546-4df4-bc5e-0f28ebffe82a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473374632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1473374632
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.400178723
Short name T959
Test name
Test status
Simulation time 48800332 ps
CPU time 2.16 seconds
Started May 19 12:58:21 PM PDT 24
Finished May 19 12:58:24 PM PDT 24
Peak memory 211472 kb
Host smart-9b59705c-4fd5-466f-a8db-2b795a836f6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400178723 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.400178723
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1503508581
Short name T910
Test name
Test status
Simulation time 27590613 ps
CPU time 1.47 seconds
Started May 19 12:58:27 PM PDT 24
Finished May 19 12:58:30 PM PDT 24
Peak memory 209664 kb
Host smart-eeec2c29-916a-45bc-8ce2-65f848702e81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503508581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1503508581
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3491478462
Short name T987
Test name
Test status
Simulation time 182743496 ps
CPU time 2.46 seconds
Started May 19 12:58:21 PM PDT 24
Finished May 19 12:58:24 PM PDT 24
Peak memory 217764 kb
Host smart-4f076b71-04eb-459c-9786-094fe1f1d6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491478462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3491478462
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2795747055
Short name T132
Test name
Test status
Simulation time 269098361 ps
CPU time 2 seconds
Started May 19 12:58:21 PM PDT 24
Finished May 19 12:58:23 PM PDT 24
Peak memory 221856 kb
Host smart-66aafd06-b82b-44d1-a8e2-7b302c8d18aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795747055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2795747055
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2933440133
Short name T137
Test name
Test status
Simulation time 64484746 ps
CPU time 0.99 seconds
Started May 19 12:58:35 PM PDT 24
Finished May 19 12:58:37 PM PDT 24
Peak memory 209236 kb
Host smart-c1487409-38b4-4741-9a87-2ebafdeadd00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933440133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2933440133
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1228918835
Short name T903
Test name
Test status
Simulation time 64444133 ps
CPU time 2.63 seconds
Started May 19 12:58:34 PM PDT 24
Finished May 19 12:58:38 PM PDT 24
Peak memory 209648 kb
Host smart-b210c6b8-f2e4-43ef-a200-19e7366a9d26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228918835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1228918835
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2713765780
Short name T951
Test name
Test status
Simulation time 17242907 ps
CPU time 1.09 seconds
Started May 19 12:58:34 PM PDT 24
Finished May 19 12:58:36 PM PDT 24
Peak memory 209816 kb
Host smart-5795cbe5-88f6-4adb-9da6-ae76683bec0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713765780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2713765780
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.9946974
Short name T926
Test name
Test status
Simulation time 53150343 ps
CPU time 1.71 seconds
Started May 19 12:58:34 PM PDT 24
Finished May 19 12:58:37 PM PDT 24
Peak memory 217704 kb
Host smart-2acdf966-7f29-47c4-bf6a-f55662249dc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9946974 -assert nopostproc +UVM_TESTNAME=lc
_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.9946974
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2135050383
Short name T950
Test name
Test status
Simulation time 133572057 ps
CPU time 0.82 seconds
Started May 19 12:58:34 PM PDT 24
Finished May 19 12:58:36 PM PDT 24
Peak memory 208516 kb
Host smart-1a31046f-c4fa-4245-851a-1ca18d068161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135050383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2135050383
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3803806338
Short name T973
Test name
Test status
Simulation time 41915134 ps
CPU time 1.63 seconds
Started May 19 12:58:26 PM PDT 24
Finished May 19 12:58:28 PM PDT 24
Peak memory 209320 kb
Host smart-0d18a2fe-4554-4d47-8cab-6dffc3dd74a1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803806338 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3803806338
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2739850944
Short name T135
Test name
Test status
Simulation time 15337898610 ps
CPU time 12.39 seconds
Started May 19 12:58:25 PM PDT 24
Finished May 19 12:58:38 PM PDT 24
Peak memory 208612 kb
Host smart-228bc759-38de-4743-8ffe-9165ba3a4f15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739850944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2739850944
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2871911203
Short name T922
Test name
Test status
Simulation time 5134115483 ps
CPU time 11.4 seconds
Started May 19 12:58:28 PM PDT 24
Finished May 19 12:58:40 PM PDT 24
Peak memory 209388 kb
Host smart-bc69600f-af41-4b79-9439-af7e6ecfdd9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871911203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2871911203
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3919768946
Short name T872
Test name
Test status
Simulation time 99151367 ps
CPU time 1.97 seconds
Started May 19 12:58:26 PM PDT 24
Finished May 19 12:58:28 PM PDT 24
Peak memory 210764 kb
Host smart-b8e6c44a-6a13-4d98-9f38-c90c462bf9d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919768946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3919768946
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3190301643
Short name T883
Test name
Test status
Simulation time 654069493 ps
CPU time 2.66 seconds
Started May 19 12:58:27 PM PDT 24
Finished May 19 12:58:30 PM PDT 24
Peak memory 217696 kb
Host smart-b6640c99-de6a-4769-83b5-c3d7182bf760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319030
1643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3190301643
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.519747009
Short name T962
Test name
Test status
Simulation time 276560339 ps
CPU time 1.72 seconds
Started May 19 12:58:27 PM PDT 24
Finished May 19 12:58:30 PM PDT 24
Peak memory 209280 kb
Host smart-e6673d0b-559e-410f-bd10-dbd3053bf87f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519747009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.519747009
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2805021938
Short name T946
Test name
Test status
Simulation time 50422505 ps
CPU time 1.03 seconds
Started May 19 12:58:27 PM PDT 24
Finished May 19 12:58:28 PM PDT 24
Peak memory 209524 kb
Host smart-ec3c676b-4328-47c5-ae5d-7c0713fd242d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805021938 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2805021938
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1009197350
Short name T965
Test name
Test status
Simulation time 253286982 ps
CPU time 1.53 seconds
Started May 19 12:58:34 PM PDT 24
Finished May 19 12:58:37 PM PDT 24
Peak memory 211456 kb
Host smart-47f7b331-c79b-4157-8788-598ef4dd75ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009197350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1009197350
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1984769531
Short name T889
Test name
Test status
Simulation time 313367893 ps
CPU time 1.87 seconds
Started May 19 12:58:28 PM PDT 24
Finished May 19 12:58:30 PM PDT 24
Peak memory 217720 kb
Host smart-cc8ae7d7-b6ea-4fe9-87d5-b069c4dcf3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984769531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1984769531
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.699199175
Short name T992
Test name
Test status
Simulation time 20893182 ps
CPU time 1.26 seconds
Started May 19 12:58:37 PM PDT 24
Finished May 19 12:58:39 PM PDT 24
Peak memory 219216 kb
Host smart-2a3a9b94-5e09-4255-bcd8-ab2b8b9bf243
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699199175 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.699199175
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4275275424
Short name T198
Test name
Test status
Simulation time 43324492 ps
CPU time 0.87 seconds
Started May 19 12:58:37 PM PDT 24
Finished May 19 12:58:39 PM PDT 24
Peak memory 209628 kb
Host smart-56e53d96-b319-40c7-abeb-783aaa74c03e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275275424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.4275275424
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1829640911
Short name T870
Test name
Test status
Simulation time 70892113 ps
CPU time 1.94 seconds
Started May 19 12:58:37 PM PDT 24
Finished May 19 12:58:40 PM PDT 24
Peak memory 209164 kb
Host smart-501196f3-1f4a-4442-9b2e-e810cd1d5b4a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829640911 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1829640911
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2415102202
Short name T935
Test name
Test status
Simulation time 4876859337 ps
CPU time 16.57 seconds
Started May 19 12:58:34 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 208568 kb
Host smart-ad9bc57a-927f-4d56-8417-a596d2318f32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415102202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2415102202
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1717537253
Short name T915
Test name
Test status
Simulation time 546704281 ps
CPU time 12.45 seconds
Started May 19 12:58:31 PM PDT 24
Finished May 19 12:58:44 PM PDT 24
Peak memory 209136 kb
Host smart-f40b7d98-7b2f-44bb-a3d3-79e3ada08766
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717537253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1717537253
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.208234707
Short name T984
Test name
Test status
Simulation time 47639763 ps
CPU time 1.21 seconds
Started May 19 12:58:35 PM PDT 24
Finished May 19 12:58:37 PM PDT 24
Peak memory 210664 kb
Host smart-80cb8013-45d8-4e42-ad26-debd4355f3ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208234707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.208234707
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3474381600
Short name T966
Test name
Test status
Simulation time 95319573 ps
CPU time 1.9 seconds
Started May 19 12:58:36 PM PDT 24
Finished May 19 12:58:39 PM PDT 24
Peak memory 217932 kb
Host smart-fb9cec0e-2bad-4038-96d3-11b6bd871805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347438
1600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3474381600
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3717998239
Short name T902
Test name
Test status
Simulation time 81521228 ps
CPU time 1.13 seconds
Started May 19 12:58:32 PM PDT 24
Finished May 19 12:58:34 PM PDT 24
Peak memory 209360 kb
Host smart-f20f21f9-8268-4a04-aa29-a13eafc2fb44
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717998239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3717998239
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.326015941
Short name T210
Test name
Test status
Simulation time 30707179 ps
CPU time 1.47 seconds
Started May 19 12:58:32 PM PDT 24
Finished May 19 12:58:34 PM PDT 24
Peak memory 209448 kb
Host smart-842eeca4-c76c-43d1-9890-b8b969587f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326015941 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.326015941
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3632441959
Short name T938
Test name
Test status
Simulation time 111952440 ps
CPU time 1.51 seconds
Started May 19 12:58:36 PM PDT 24
Finished May 19 12:58:39 PM PDT 24
Peak memory 211364 kb
Host smart-e10800e2-22e9-4372-baae-35a0d94b14ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632441959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3632441959
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.658251385
Short name T969
Test name
Test status
Simulation time 639951154 ps
CPU time 4.24 seconds
Started May 19 12:58:36 PM PDT 24
Finished May 19 12:58:41 PM PDT 24
Peak memory 217628 kb
Host smart-1156e826-2a8d-440f-9eb0-8bbb1e4b9ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658251385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.658251385
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2617310849
Short name T124
Test name
Test status
Simulation time 106974254 ps
CPU time 4.3 seconds
Started May 19 12:58:36 PM PDT 24
Finished May 19 12:58:42 PM PDT 24
Peak memory 217608 kb
Host smart-d8e6c394-b3a4-4767-ae6b-685cadbb70c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617310849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2617310849
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2504680286
Short name T948
Test name
Test status
Simulation time 68980452 ps
CPU time 1.2 seconds
Started May 19 12:58:44 PM PDT 24
Finished May 19 12:58:47 PM PDT 24
Peak memory 217808 kb
Host smart-885032eb-ce2c-4bb8-b22a-ca33753a5d0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504680286 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2504680286
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4022943657
Short name T937
Test name
Test status
Simulation time 14702788 ps
CPU time 0.87 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 209624 kb
Host smart-9cfcc1f6-17b6-4616-b40f-cc0337b54865
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022943657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4022943657
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3262764412
Short name T952
Test name
Test status
Simulation time 63848459 ps
CPU time 0.99 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 209524 kb
Host smart-070f58b7-f88a-4168-a9a8-71e8860018d1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262764412 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3262764412
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2939867429
Short name T979
Test name
Test status
Simulation time 359928298 ps
CPU time 8.9 seconds
Started May 19 12:58:36 PM PDT 24
Finished May 19 12:58:47 PM PDT 24
Peak memory 209368 kb
Host smart-3858bacd-6930-41b3-bd2d-3caa82a7cf99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939867429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2939867429
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.239842214
Short name T912
Test name
Test status
Simulation time 9241525651 ps
CPU time 45.83 seconds
Started May 19 12:58:37 PM PDT 24
Finished May 19 12:59:24 PM PDT 24
Peak memory 209316 kb
Host smart-63a8e725-d84e-4646-92a7-6bee317d6064
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239842214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.239842214
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1469423884
Short name T982
Test name
Test status
Simulation time 70280958 ps
CPU time 1.41 seconds
Started May 19 12:58:37 PM PDT 24
Finished May 19 12:58:40 PM PDT 24
Peak memory 210788 kb
Host smart-f8705cf0-4be6-4ccb-936c-caf1de905b4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469423884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1469423884
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2837324609
Short name T920
Test name
Test status
Simulation time 757943322 ps
CPU time 3.02 seconds
Started May 19 12:58:45 PM PDT 24
Finished May 19 12:58:49 PM PDT 24
Peak memory 219112 kb
Host smart-cce44956-6f90-4525-a857-0b593527e949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283732
4609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2837324609
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1063379722
Short name T924
Test name
Test status
Simulation time 53165844 ps
CPU time 1.46 seconds
Started May 19 12:58:37 PM PDT 24
Finished May 19 12:58:39 PM PDT 24
Peak memory 209228 kb
Host smart-f59e8579-b671-4e6a-9338-4067e9f83e53
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063379722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1063379722
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.135450658
Short name T943
Test name
Test status
Simulation time 37779046 ps
CPU time 1.79 seconds
Started May 19 12:58:44 PM PDT 24
Finished May 19 12:58:47 PM PDT 24
Peak memory 209320 kb
Host smart-4d500e6a-cb0a-4a14-a798-37ffadf3b30e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135450658 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.135450658
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2940774609
Short name T885
Test name
Test status
Simulation time 27494817 ps
CPU time 1.17 seconds
Started May 19 12:58:45 PM PDT 24
Finished May 19 12:58:47 PM PDT 24
Peak memory 209424 kb
Host smart-9ae0c10e-6be1-40c3-9459-8ba412ffb1d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940774609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2940774609
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4127716015
Short name T109
Test name
Test status
Simulation time 91215679 ps
CPU time 1.85 seconds
Started May 19 12:58:42 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 217664 kb
Host smart-0f5170c4-13fc-4940-9227-a77e7710b000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127716015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4127716015
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2641239457
Short name T909
Test name
Test status
Simulation time 33067965 ps
CPU time 1.69 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 217796 kb
Host smart-209547c2-68aa-4ed3-9f21-e91957c64542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641239457 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2641239457
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1164734697
Short name T901
Test name
Test status
Simulation time 14562372 ps
CPU time 0.95 seconds
Started May 19 12:58:44 PM PDT 24
Finished May 19 12:58:46 PM PDT 24
Peak memory 209428 kb
Host smart-1885c25e-f663-47f5-a865-f6a32c79e0a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164734697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1164734697
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3737234000
Short name T976
Test name
Test status
Simulation time 552975075 ps
CPU time 1.26 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 209380 kb
Host smart-4fce9817-0661-49bb-916b-ce5c7b2ab829
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737234000 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3737234000
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3150419175
Short name T868
Test name
Test status
Simulation time 186773750 ps
CPU time 4.93 seconds
Started May 19 12:58:44 PM PDT 24
Finished May 19 12:58:50 PM PDT 24
Peak memory 209132 kb
Host smart-76dd74cf-fc44-4c53-a6a1-34a35f5767bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150419175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3150419175
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3926027501
Short name T942
Test name
Test status
Simulation time 3511256127 ps
CPU time 19.23 seconds
Started May 19 12:58:41 PM PDT 24
Finished May 19 12:59:01 PM PDT 24
Peak memory 209296 kb
Host smart-73a3a4e9-6788-42ed-a0d5-aeb324c0f423
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926027501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3926027501
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3819039532
Short name T873
Test name
Test status
Simulation time 46852261 ps
CPU time 1.84 seconds
Started May 19 12:58:42 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 210296 kb
Host smart-aa0cace7-f7e2-4fcc-99ad-e6cae2a71579
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819039532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3819039532
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2143893349
Short name T907
Test name
Test status
Simulation time 132183946 ps
CPU time 2.41 seconds
Started May 19 12:58:44 PM PDT 24
Finished May 19 12:58:48 PM PDT 24
Peak memory 218764 kb
Host smart-243d3c01-2195-4f89-8bef-0da48c1c59a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214389
3349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2143893349
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1202946301
Short name T931
Test name
Test status
Simulation time 369669397 ps
CPU time 1.47 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 208368 kb
Host smart-c937c92c-b3be-48a3-9a03-e39773038ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202946301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1202946301
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1190222187
Short name T949
Test name
Test status
Simulation time 27593992 ps
CPU time 1.11 seconds
Started May 19 12:58:41 PM PDT 24
Finished May 19 12:58:43 PM PDT 24
Peak memory 209448 kb
Host smart-d973b24e-30a7-420c-bbe3-9f941bc97dc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190222187 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1190222187
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4081504554
Short name T115
Test name
Test status
Simulation time 80935690 ps
CPU time 1.82 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:46 PM PDT 24
Peak memory 209640 kb
Host smart-b04b11f8-9a56-489f-95a9-31084ab841ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081504554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4081504554
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3745977456
Short name T112
Test name
Test status
Simulation time 64540260 ps
CPU time 1.62 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:46 PM PDT 24
Peak memory 217724 kb
Host smart-eceadeaf-307b-45ca-95c8-b6a7157c1cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745977456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3745977456
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4253539335
Short name T116
Test name
Test status
Simulation time 82537988 ps
CPU time 2.78 seconds
Started May 19 12:58:44 PM PDT 24
Finished May 19 12:58:48 PM PDT 24
Peak memory 221984 kb
Host smart-918be3fe-6afa-4804-af9d-bcf4fdbec2de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253539335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4253539335
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4056921322
Short name T978
Test name
Test status
Simulation time 81525529 ps
CPU time 1.1 seconds
Started May 19 12:58:50 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 219020 kb
Host smart-51f42836-c7d0-4ecf-833e-032a44bece4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056921322 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4056921322
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4117498164
Short name T932
Test name
Test status
Simulation time 46572241 ps
CPU time 0.89 seconds
Started May 19 12:58:46 PM PDT 24
Finished May 19 12:58:48 PM PDT 24
Peak memory 209408 kb
Host smart-d8396c1e-4abf-46a3-8a0d-eb8f5961dfea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117498164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.4117498164
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4183041677
Short name T869
Test name
Test status
Simulation time 186986109 ps
CPU time 1.71 seconds
Started May 19 12:58:47 PM PDT 24
Finished May 19 12:58:50 PM PDT 24
Peak memory 209376 kb
Host smart-921e1779-7a8b-4559-9177-a9ebfb7c2743
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183041677 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4183041677
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2690243733
Short name T929
Test name
Test status
Simulation time 1399163894 ps
CPU time 28.56 seconds
Started May 19 12:58:47 PM PDT 24
Finished May 19 12:59:17 PM PDT 24
Peak memory 209196 kb
Host smart-baa38f34-130e-4c77-9bdc-b8a334ebf99f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690243733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2690243733
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1737593594
Short name T880
Test name
Test status
Simulation time 348435683 ps
CPU time 4.88 seconds
Started May 19 12:58:42 PM PDT 24
Finished May 19 12:58:48 PM PDT 24
Peak memory 209328 kb
Host smart-624ecec1-80fb-4ab7-970a-3969053f4d2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737593594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1737593594
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1281941918
Short name T968
Test name
Test status
Simulation time 137134957 ps
CPU time 1.74 seconds
Started May 19 12:58:42 PM PDT 24
Finished May 19 12:58:45 PM PDT 24
Peak memory 210768 kb
Host smart-686f388f-bcdc-4c4e-a297-a97217b36cc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281941918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1281941918
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3102426544
Short name T173
Test name
Test status
Simulation time 72109878 ps
CPU time 1.42 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:51 PM PDT 24
Peak memory 217724 kb
Host smart-e3e67e11-d678-4c72-82fc-300a38cee8ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310242
6544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3102426544
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.738938427
Short name T933
Test name
Test status
Simulation time 80063550 ps
CPU time 2.51 seconds
Started May 19 12:58:43 PM PDT 24
Finished May 19 12:58:47 PM PDT 24
Peak memory 208788 kb
Host smart-2a0f28a0-6f88-451a-b263-69612dd54efd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738938427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.738938427
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2754956727
Short name T958
Test name
Test status
Simulation time 38408209 ps
CPU time 1.76 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 211588 kb
Host smart-17b603a3-074a-4c8f-819a-007b3688de0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754956727 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2754956727
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1145040941
Short name T905
Test name
Test status
Simulation time 168817969 ps
CPU time 1.9 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 209500 kb
Host smart-7e8b5e28-680d-49ec-8afc-6904e92e00eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145040941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1145040941
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1592993118
Short name T989
Test name
Test status
Simulation time 139027818 ps
CPU time 2.57 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:53 PM PDT 24
Peak memory 217688 kb
Host smart-2f954086-1476-4653-8c4f-f26a32d06aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592993118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1592993118
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.126096882
Short name T134
Test name
Test status
Simulation time 161590322 ps
CPU time 3.51 seconds
Started May 19 12:58:46 PM PDT 24
Finished May 19 12:58:50 PM PDT 24
Peak memory 217652 kb
Host smart-df000450-e08e-4d00-beca-03244814a190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126096882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.126096882
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2907251086
Short name T934
Test name
Test status
Simulation time 179976769 ps
CPU time 1.63 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 217680 kb
Host smart-39177c6d-c3e5-47a9-a671-157435c6bd10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907251086 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2907251086
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2761870514
Short name T207
Test name
Test status
Simulation time 38602682 ps
CPU time 1.03 seconds
Started May 19 12:58:47 PM PDT 24
Finished May 19 12:58:50 PM PDT 24
Peak memory 209408 kb
Host smart-344b45ba-4782-4fa4-a691-e7269d126c86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761870514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2761870514
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3606044848
Short name T891
Test name
Test status
Simulation time 138703878 ps
CPU time 2.36 seconds
Started May 19 12:58:47 PM PDT 24
Finished May 19 12:58:50 PM PDT 24
Peak memory 209384 kb
Host smart-aea682a8-94c5-4534-8a9a-849dbde0e30a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606044848 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3606044848
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2454759681
Short name T961
Test name
Test status
Simulation time 501186498 ps
CPU time 5.35 seconds
Started May 19 12:58:47 PM PDT 24
Finished May 19 12:58:53 PM PDT 24
Peak memory 208428 kb
Host smart-258b5ad4-4bff-468e-9e62-cfdbdc1d1576
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454759681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2454759681
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3896470709
Short name T945
Test name
Test status
Simulation time 9499979956 ps
CPU time 21.4 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:59:11 PM PDT 24
Peak memory 208300 kb
Host smart-2d57b231-4ed1-4a2c-b437-1e18db713b4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896470709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3896470709
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3826296638
Short name T113
Test name
Test status
Simulation time 1058480140 ps
CPU time 1.98 seconds
Started May 19 12:58:50 PM PDT 24
Finished May 19 12:58:53 PM PDT 24
Peak memory 210916 kb
Host smart-ee308c28-932a-4ff5-adf0-23130d5dc8ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826296638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3826296638
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.327136025
Short name T111
Test name
Test status
Simulation time 68187699 ps
CPU time 2.69 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:53 PM PDT 24
Peak memory 218784 kb
Host smart-3cdb8949-e05f-4007-9aff-8cf06974aa85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327136
025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.327136025
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3501024047
Short name T957
Test name
Test status
Simulation time 55583620 ps
CPU time 1.26 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:51 PM PDT 24
Peak memory 209336 kb
Host smart-5d5004f6-8c31-4744-812c-c9fab1873787
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501024047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3501024047
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1181762544
Short name T988
Test name
Test status
Simulation time 136938882 ps
CPU time 1.31 seconds
Started May 19 12:58:53 PM PDT 24
Finished May 19 12:58:56 PM PDT 24
Peak memory 209156 kb
Host smart-d803bc18-d069-4e52-a497-b9d3f76cf493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181762544 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1181762544
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1265701264
Short name T963
Test name
Test status
Simulation time 15825774 ps
CPU time 1.17 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:51 PM PDT 24
Peak memory 209384 kb
Host smart-579d2873-c6d7-4b66-a3e1-bc7a18e48645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265701264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1265701264
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.505513234
Short name T897
Test name
Test status
Simulation time 233639978 ps
CPU time 2.07 seconds
Started May 19 12:58:49 PM PDT 24
Finished May 19 12:58:53 PM PDT 24
Peak memory 217924 kb
Host smart-7180473e-bbc9-4d03-a625-5b21921cfb11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505513234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.505513234
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.568721849
Short name T126
Test name
Test status
Simulation time 60208630 ps
CPU time 1.99 seconds
Started May 19 12:58:48 PM PDT 24
Finished May 19 12:58:52 PM PDT 24
Peak memory 221824 kb
Host smart-18dc7615-5826-4dc7-8179-158530a6029b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568721849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.568721849
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.140159863
Short name T100
Test name
Test status
Simulation time 20343941 ps
CPU time 0.94 seconds
Started May 19 01:02:25 PM PDT 24
Finished May 19 01:02:27 PM PDT 24
Peak memory 209660 kb
Host smart-41e50055-a3fa-47d2-b249-0392a5d43501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140159863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.140159863
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3869507693
Short name T406
Test name
Test status
Simulation time 33792391 ps
CPU time 0.77 seconds
Started May 19 01:02:10 PM PDT 24
Finished May 19 01:02:11 PM PDT 24
Peak memory 209480 kb
Host smart-86ab0f9d-efff-4465-989e-dc3de072ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869507693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3869507693
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1422358711
Short name T293
Test name
Test status
Simulation time 3952395531 ps
CPU time 17.23 seconds
Started May 19 01:02:10 PM PDT 24
Finished May 19 01:02:28 PM PDT 24
Peak memory 218032 kb
Host smart-bd505af7-eb9a-4747-b80a-713c07c3d7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422358711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1422358711
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3754831702
Short name T782
Test name
Test status
Simulation time 793339570 ps
CPU time 4.06 seconds
Started May 19 01:02:19 PM PDT 24
Finished May 19 01:02:23 PM PDT 24
Peak memory 216928 kb
Host smart-cb35ec66-ebde-4920-bd80-b898e3b5eafd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754831702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3754831702
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2608745023
Short name T482
Test name
Test status
Simulation time 4332300381 ps
CPU time 40.25 seconds
Started May 19 01:02:13 PM PDT 24
Finished May 19 01:02:54 PM PDT 24
Peak memory 218056 kb
Host smart-d5cf0781-8683-46cd-b563-a2a6a7187dee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608745023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2608745023
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3925788550
Short name T582
Test name
Test status
Simulation time 4870538678 ps
CPU time 20.39 seconds
Started May 19 01:02:20 PM PDT 24
Finished May 19 01:02:41 PM PDT 24
Peak memory 217744 kb
Host smart-0a35921f-e176-4c51-a110-4fd3c6622157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925788550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
925788550
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.4143315240
Short name T632
Test name
Test status
Simulation time 139862643 ps
CPU time 3.1 seconds
Started May 19 01:02:15 PM PDT 24
Finished May 19 01:02:18 PM PDT 24
Peak memory 218096 kb
Host smart-28279808-8990-4c51-a69e-1748b678cbdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143315240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.4143315240
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3514198794
Short name T565
Test name
Test status
Simulation time 3000650811 ps
CPU time 20.39 seconds
Started May 19 01:02:19 PM PDT 24
Finished May 19 01:02:40 PM PDT 24
Peak memory 213488 kb
Host smart-81daa0e5-6495-4e33-9f27-bbeb2344ce43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514198794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3514198794
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3468300368
Short name T78
Test name
Test status
Simulation time 352890024 ps
CPU time 7.76 seconds
Started May 19 01:02:13 PM PDT 24
Finished May 19 01:02:22 PM PDT 24
Peak memory 213484 kb
Host smart-0a4deb80-ae81-47b9-8666-319022402992
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468300368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3468300368
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2728745177
Short name T513
Test name
Test status
Simulation time 1818862198 ps
CPU time 32.66 seconds
Started May 19 01:02:13 PM PDT 24
Finished May 19 01:02:46 PM PDT 24
Peak memory 250908 kb
Host smart-76152c78-dfcd-4261-943c-faa7552fe96b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728745177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2728745177
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2565348421
Short name T364
Test name
Test status
Simulation time 1307137289 ps
CPU time 14.08 seconds
Started May 19 01:02:14 PM PDT 24
Finished May 19 01:02:29 PM PDT 24
Peak memory 250484 kb
Host smart-37487870-a92e-4636-9c96-b47f2d18a5a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565348421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2565348421
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2255265477
Short name T276
Test name
Test status
Simulation time 136783837 ps
CPU time 2.57 seconds
Started May 19 01:02:08 PM PDT 24
Finished May 19 01:02:12 PM PDT 24
Peak memory 217996 kb
Host smart-0c032ca1-6de3-4699-ba4e-11f8919170ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255265477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2255265477
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1452397565
Short name T389
Test name
Test status
Simulation time 906148729 ps
CPU time 6.46 seconds
Started May 19 01:02:09 PM PDT 24
Finished May 19 01:02:16 PM PDT 24
Peak memory 218212 kb
Host smart-b64bef4a-f7a7-4d62-bebd-850dddb39ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452397565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1452397565
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1358268634
Short name T738
Test name
Test status
Simulation time 4070176603 ps
CPU time 12.08 seconds
Started May 19 01:02:20 PM PDT 24
Finished May 19 01:02:32 PM PDT 24
Peak memory 218468 kb
Host smart-a1485791-75fd-4f20-9fc3-fe14597dcc89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358268634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1358268634
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.787545901
Short name T145
Test name
Test status
Simulation time 4241328733 ps
CPU time 7.14 seconds
Started May 19 01:02:23 PM PDT 24
Finished May 19 01:02:31 PM PDT 24
Peak memory 217908 kb
Host smart-56ecd86b-e0cd-4df1-a986-60e30275d3de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787545901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.787545901
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3228410143
Short name T229
Test name
Test status
Simulation time 173784461 ps
CPU time 6.45 seconds
Started May 19 01:02:19 PM PDT 24
Finished May 19 01:02:26 PM PDT 24
Peak memory 217948 kb
Host smart-80fe04c5-0ad8-4b5b-9a06-f0415f0fba11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228410143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
228410143
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.4080965552
Short name T560
Test name
Test status
Simulation time 1139275709 ps
CPU time 8.85 seconds
Started May 19 01:02:08 PM PDT 24
Finished May 19 01:02:18 PM PDT 24
Peak memory 218120 kb
Host smart-bfd7dca7-db3f-4744-b355-ee70cc5c6a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080965552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4080965552
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.73929006
Short name T96
Test name
Test status
Simulation time 70621156 ps
CPU time 1.47 seconds
Started May 19 01:02:12 PM PDT 24
Finished May 19 01:02:14 PM PDT 24
Peak memory 213716 kb
Host smart-c685888c-7da4-43a6-9a5a-64a01f47bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73929006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.73929006
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.689354812
Short name T332
Test name
Test status
Simulation time 300341177 ps
CPU time 22.86 seconds
Started May 19 01:02:11 PM PDT 24
Finished May 19 01:02:35 PM PDT 24
Peak memory 250952 kb
Host smart-f0081bf5-9a00-47f2-8def-dd4ee9ddf4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689354812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.689354812
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3191836523
Short name T244
Test name
Test status
Simulation time 358976142 ps
CPU time 6.97 seconds
Started May 19 01:02:09 PM PDT 24
Finished May 19 01:02:17 PM PDT 24
Peak memory 251064 kb
Host smart-5cbbfac8-de21-48c5-bc59-e109de13eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191836523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3191836523
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1697622916
Short name T846
Test name
Test status
Simulation time 6765814393 ps
CPU time 155.2 seconds
Started May 19 01:02:23 PM PDT 24
Finished May 19 01:04:59 PM PDT 24
Peak memory 280740 kb
Host smart-d6dd7872-6c25-4023-97f9-97e4386464ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697622916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1697622916
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2667790722
Short name T546
Test name
Test status
Simulation time 11789175 ps
CPU time 0.97 seconds
Started May 19 01:02:11 PM PDT 24
Finished May 19 01:02:12 PM PDT 24
Peak memory 208748 kb
Host smart-37d4c709-ae4d-4bcf-bb71-d5739dac934f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667790722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2667790722
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2485902250
Short name T256
Test name
Test status
Simulation time 29751044 ps
CPU time 0.88 seconds
Started May 19 01:02:45 PM PDT 24
Finished May 19 01:02:46 PM PDT 24
Peak memory 209572 kb
Host smart-b6de0c5e-7041-4b48-a00e-570e1e296343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485902250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2485902250
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1181809248
Short name T55
Test name
Test status
Simulation time 1418075903 ps
CPU time 22.82 seconds
Started May 19 01:02:25 PM PDT 24
Finished May 19 01:02:49 PM PDT 24
Peak memory 218252 kb
Host smart-9472ebf5-9263-4f51-968c-c2e7831943c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181809248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1181809248
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1500607750
Short name T672
Test name
Test status
Simulation time 4090155551 ps
CPU time 44.28 seconds
Started May 19 01:02:37 PM PDT 24
Finished May 19 01:03:21 PM PDT 24
Peak memory 218980 kb
Host smart-f59743e6-22d5-4677-91d5-9ee5e096421b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500607750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1500607750
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2211110616
Short name T193
Test name
Test status
Simulation time 4426115803 ps
CPU time 14.44 seconds
Started May 19 01:02:36 PM PDT 24
Finished May 19 01:02:51 PM PDT 24
Peak memory 217772 kb
Host smart-e2e587ec-4c2a-44eb-abba-194116fe07e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211110616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
211110616
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3801340538
Short name T191
Test name
Test status
Simulation time 1556168915 ps
CPU time 3.93 seconds
Started May 19 01:02:36 PM PDT 24
Finished May 19 01:02:41 PM PDT 24
Peak memory 217932 kb
Host smart-72c1c39f-03b9-4e9b-ab29-fe180d6eba1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801340538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3801340538
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3684488864
Short name T533
Test name
Test status
Simulation time 896929808 ps
CPU time 27.17 seconds
Started May 19 01:02:36 PM PDT 24
Finished May 19 01:03:03 PM PDT 24
Peak memory 213188 kb
Host smart-6946df28-061a-430d-8bec-9eed8fe1dafd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684488864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3684488864
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.116141413
Short name T593
Test name
Test status
Simulation time 50626083 ps
CPU time 1.34 seconds
Started May 19 01:02:31 PM PDT 24
Finished May 19 01:02:32 PM PDT 24
Peak memory 212612 kb
Host smart-5b39a8c0-6997-4bff-b481-f049758b8e6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116141413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.116141413
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3300022885
Short name T577
Test name
Test status
Simulation time 1619693709 ps
CPU time 35.88 seconds
Started May 19 01:02:28 PM PDT 24
Finished May 19 01:03:04 PM PDT 24
Peak memory 250868 kb
Host smart-5705414f-9d1e-4a44-a2da-29f7b64b6ff9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300022885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3300022885
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1548499804
Short name T388
Test name
Test status
Simulation time 1335492409 ps
CPU time 14.7 seconds
Started May 19 01:02:37 PM PDT 24
Finished May 19 01:02:52 PM PDT 24
Peak memory 250908 kb
Host smart-5172a9fc-5a5c-489e-9726-70d4b591d1e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548499804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1548499804
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1349351160
Short name T844
Test name
Test status
Simulation time 58929147 ps
CPU time 3.12 seconds
Started May 19 01:02:25 PM PDT 24
Finished May 19 01:02:29 PM PDT 24
Peak memory 218064 kb
Host smart-bf4233b9-4b0d-4ec8-b834-85d29f50adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349351160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1349351160
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.434768571
Short name T69
Test name
Test status
Simulation time 1908596333 ps
CPU time 23.3 seconds
Started May 19 01:02:28 PM PDT 24
Finished May 19 01:02:52 PM PDT 24
Peak memory 217996 kb
Host smart-49341f03-7dae-40f2-98de-c010f9d83d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434768571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.434768571
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3849547140
Short name T94
Test name
Test status
Simulation time 1644544293 ps
CPU time 41.62 seconds
Started May 19 01:02:42 PM PDT 24
Finished May 19 01:03:25 PM PDT 24
Peak memory 269320 kb
Host smart-8473b4d6-80ab-4c8b-981b-390b638c141b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849547140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3849547140
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1933562639
Short name T296
Test name
Test status
Simulation time 532198005 ps
CPU time 14.05 seconds
Started May 19 01:02:35 PM PDT 24
Finished May 19 01:02:50 PM PDT 24
Peak memory 218948 kb
Host smart-2a53b90e-c38d-4b19-a5e5-b3e347a734ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933562639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1933562639
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.256496836
Short name T188
Test name
Test status
Simulation time 541641960 ps
CPU time 16 seconds
Started May 19 01:02:36 PM PDT 24
Finished May 19 01:02:52 PM PDT 24
Peak memory 218000 kb
Host smart-35534c93-19d4-4763-a7e1-4559e504e569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256496836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.256496836
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2161222627
Short name T44
Test name
Test status
Simulation time 1340688422 ps
CPU time 9.61 seconds
Started May 19 01:02:36 PM PDT 24
Finished May 19 01:02:46 PM PDT 24
Peak memory 217988 kb
Host smart-3042de98-22d4-44c7-a89a-67f9e793208c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161222627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
161222627
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3847754936
Short name T561
Test name
Test status
Simulation time 249376688 ps
CPU time 10.28 seconds
Started May 19 01:02:31 PM PDT 24
Finished May 19 01:02:41 PM PDT 24
Peak memory 218172 kb
Host smart-9d966edd-237b-4648-9a93-9dbd7d806921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847754936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3847754936
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3925835414
Short name T65
Test name
Test status
Simulation time 39825013 ps
CPU time 1.66 seconds
Started May 19 01:02:26 PM PDT 24
Finished May 19 01:02:29 PM PDT 24
Peak memory 213824 kb
Host smart-6334b8a3-5de2-48ac-9b08-7313943619f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925835414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3925835414
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.4248797878
Short name T736
Test name
Test status
Simulation time 243820103 ps
CPU time 25.99 seconds
Started May 19 01:02:26 PM PDT 24
Finished May 19 01:02:53 PM PDT 24
Peak memory 250896 kb
Host smart-d0fc5061-dd7d-4c03-aa00-b9bddb0fd3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248797878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4248797878
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2265921889
Short name T334
Test name
Test status
Simulation time 147180065 ps
CPU time 3.84 seconds
Started May 19 01:02:26 PM PDT 24
Finished May 19 01:02:31 PM PDT 24
Peak memory 226320 kb
Host smart-60eb9d31-d45e-4fab-a11a-d5ac3b15c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265921889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2265921889
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2208599653
Short name T342
Test name
Test status
Simulation time 4900819346 ps
CPU time 175.89 seconds
Started May 19 01:02:43 PM PDT 24
Finished May 19 01:05:39 PM PDT 24
Peak memory 277044 kb
Host smart-6fc08f4c-aac1-48e5-b98c-ac278bbd2e63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208599653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2208599653
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.51951855
Short name T425
Test name
Test status
Simulation time 41233568 ps
CPU time 0.95 seconds
Started May 19 01:02:26 PM PDT 24
Finished May 19 01:02:28 PM PDT 24
Peak memory 208836 kb
Host smart-64244666-4b7c-429a-ade6-2e09791d8672
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51951855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_volatile_unlock_smoke.51951855
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3091223690
Short name T432
Test name
Test status
Simulation time 41124560 ps
CPU time 0.82 seconds
Started May 19 01:04:08 PM PDT 24
Finished May 19 01:04:10 PM PDT 24
Peak memory 209492 kb
Host smart-c104cba3-3379-4302-88d0-bbed8d0d4ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091223690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3091223690
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1727826160
Short name T688
Test name
Test status
Simulation time 367349645 ps
CPU time 12.1 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:16 PM PDT 24
Peak memory 218032 kb
Host smart-7486f9cf-37ed-40fa-a3d4-16c1b6940699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727826160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1727826160
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.205595613
Short name T26
Test name
Test status
Simulation time 1422852745 ps
CPU time 10.3 seconds
Started May 19 01:04:04 PM PDT 24
Finished May 19 01:04:15 PM PDT 24
Peak memory 209576 kb
Host smart-9e0ba7c8-f8d9-4778-91a7-3ec8720a5608
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205595613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.205595613
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1851065714
Short name T459
Test name
Test status
Simulation time 1147504518 ps
CPU time 34.98 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:39 PM PDT 24
Peak memory 218008 kb
Host smart-a3b53480-c494-4ccc-8d3b-58bd9e858e4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851065714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1851065714
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3414154997
Short name T5
Test name
Test status
Simulation time 181757819 ps
CPU time 3.84 seconds
Started May 19 01:04:05 PM PDT 24
Finished May 19 01:04:09 PM PDT 24
Peak memory 217964 kb
Host smart-e621b6d8-8606-4105-9a2d-54a72d0b4b13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414154997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3414154997
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.884481040
Short name T71
Test name
Test status
Simulation time 768408949 ps
CPU time 4.37 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:09 PM PDT 24
Peak memory 213612 kb
Host smart-510259ae-17ef-4d52-85b4-f80770595499
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884481040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
884481040
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1677912832
Short name T537
Test name
Test status
Simulation time 7680798632 ps
CPU time 73.08 seconds
Started May 19 01:04:06 PM PDT 24
Finished May 19 01:05:19 PM PDT 24
Peak memory 276620 kb
Host smart-e75e62d6-3293-4596-8a0d-7fa07c5477e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677912832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1677912832
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3425417202
Short name T491
Test name
Test status
Simulation time 1481180712 ps
CPU time 18.21 seconds
Started May 19 01:04:05 PM PDT 24
Finished May 19 01:04:24 PM PDT 24
Peak memory 250204 kb
Host smart-1ce21a20-15b2-4544-9760-8bd84ee73e70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425417202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3425417202
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1742088627
Short name T667
Test name
Test status
Simulation time 40086752 ps
CPU time 2.72 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:07 PM PDT 24
Peak memory 218076 kb
Host smart-2b835375-2b36-4b4a-a6e4-84754b127a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742088627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1742088627
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3016047349
Short name T773
Test name
Test status
Simulation time 1789336734 ps
CPU time 14.61 seconds
Started May 19 01:04:04 PM PDT 24
Finished May 19 01:04:20 PM PDT 24
Peak memory 226084 kb
Host smart-e3586256-cd22-4118-ab10-ee435c503155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016047349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3016047349
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3104561279
Short name T784
Test name
Test status
Simulation time 377791164 ps
CPU time 15.12 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:19 PM PDT 24
Peak memory 217932 kb
Host smart-b8f1e3ea-c64c-4a8f-92b3-82fb6387dfd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104561279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3104561279
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.699222417
Short name T627
Test name
Test status
Simulation time 248121978 ps
CPU time 9.38 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:13 PM PDT 24
Peak memory 217940 kb
Host smart-b4f02ee4-119c-4640-9c10-053282e09a61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699222417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.699222417
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3103468515
Short name T288
Test name
Test status
Simulation time 321521228 ps
CPU time 11.77 seconds
Started May 19 01:04:05 PM PDT 24
Finished May 19 01:04:17 PM PDT 24
Peak memory 218104 kb
Host smart-dfc56f9c-9fa9-47b7-addf-1c1abc43ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103468515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3103468515
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.4214928357
Short name T279
Test name
Test status
Simulation time 121416818 ps
CPU time 2.87 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:07 PM PDT 24
Peak memory 214432 kb
Host smart-a57e133d-b836-4b38-b6e8-102a53b1ae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214928357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.4214928357
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2142014766
Short name T263
Test name
Test status
Simulation time 196600520 ps
CPU time 30.55 seconds
Started May 19 01:03:57 PM PDT 24
Finished May 19 01:04:29 PM PDT 24
Peak memory 250772 kb
Host smart-3e7777ae-073d-411d-a8e3-1719b0736d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142014766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2142014766
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2170920602
Short name T32
Test name
Test status
Simulation time 419696639 ps
CPU time 3.6 seconds
Started May 19 01:04:01 PM PDT 24
Finished May 19 01:04:05 PM PDT 24
Peak memory 224168 kb
Host smart-e00b7ccb-478a-4df3-aefd-524885d630f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170920602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2170920602
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.750766745
Short name T234
Test name
Test status
Simulation time 856835645 ps
CPU time 5.75 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:10 PM PDT 24
Peak memory 224604 kb
Host smart-6e0de4c0-6d39-4c16-b655-ebb708c37cce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750766745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.750766745
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3398713623
Short name T92
Test name
Test status
Simulation time 17556531105 ps
CPU time 315.15 seconds
Started May 19 01:04:05 PM PDT 24
Finished May 19 01:09:20 PM PDT 24
Peak memory 300184 kb
Host smart-1ca6abfb-ce12-4a2d-8567-de62ff1928c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3398713623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3398713623
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.164632882
Short name T781
Test name
Test status
Simulation time 45554774 ps
CPU time 1.06 seconds
Started May 19 01:03:59 PM PDT 24
Finished May 19 01:04:01 PM PDT 24
Peak memory 212768 kb
Host smart-4b27cc27-5d1b-4e9f-8f2c-5d79bbf69c27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164632882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.164632882
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3033097795
Short name T420
Test name
Test status
Simulation time 22168644 ps
CPU time 0.9 seconds
Started May 19 01:04:08 PM PDT 24
Finished May 19 01:04:10 PM PDT 24
Peak memory 209616 kb
Host smart-b7d10bd0-c443-43a2-b73f-d8263aa546c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033097795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3033097795
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3746188389
Short name T284
Test name
Test status
Simulation time 1774270791 ps
CPU time 15.04 seconds
Started May 19 01:04:07 PM PDT 24
Finished May 19 01:04:23 PM PDT 24
Peak memory 218016 kb
Host smart-816d6a26-c03a-4eb2-950d-8bfc9bd41655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746188389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3746188389
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2336684085
Short name T833
Test name
Test status
Simulation time 229155910 ps
CPU time 3.25 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:13 PM PDT 24
Peak memory 209536 kb
Host smart-a53513ba-6174-4454-a1b0-276613d69102
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336684085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2336684085
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2068099419
Short name T49
Test name
Test status
Simulation time 4419703742 ps
CPU time 36.34 seconds
Started May 19 01:04:14 PM PDT 24
Finished May 19 01:04:52 PM PDT 24
Peak memory 218112 kb
Host smart-49d37d89-d603-4649-8c5e-73ccb61e8768
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068099419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2068099419
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1960896488
Short name T858
Test name
Test status
Simulation time 1967887668 ps
CPU time 14.11 seconds
Started May 19 01:04:11 PM PDT 24
Finished May 19 01:04:26 PM PDT 24
Peak memory 217980 kb
Host smart-40de3a72-1d9b-404b-af81-b73c843ed739
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960896488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1960896488
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.335586450
Short name T357
Test name
Test status
Simulation time 96224246 ps
CPU time 1.69 seconds
Started May 19 01:04:11 PM PDT 24
Finished May 19 01:04:14 PM PDT 24
Peak memory 212572 kb
Host smart-66177ed0-ca81-4ec8-8684-55964d1b8991
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335586450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
335586450
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.936803009
Short name T847
Test name
Test status
Simulation time 6235180705 ps
CPU time 60.18 seconds
Started May 19 01:04:08 PM PDT 24
Finished May 19 01:05:09 PM PDT 24
Peak memory 267356 kb
Host smart-c54b6ad6-50c3-4f3f-a1c9-7fbc621b9cdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936803009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.936803009
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3068379696
Short name T19
Test name
Test status
Simulation time 1494813423 ps
CPU time 12.14 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:22 PM PDT 24
Peak memory 250900 kb
Host smart-5681ccdd-8ffc-4ed5-888b-5042764866dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068379696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3068379696
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1915035272
Short name T239
Test name
Test status
Simulation time 59745357 ps
CPU time 2.42 seconds
Started May 19 01:04:07 PM PDT 24
Finished May 19 01:04:10 PM PDT 24
Peak memory 218344 kb
Host smart-832bf787-d6bd-4a4a-88e4-0ad9a7fdae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915035272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1915035272
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.725354586
Short name T579
Test name
Test status
Simulation time 270777842 ps
CPU time 12.79 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:23 PM PDT 24
Peak memory 226348 kb
Host smart-901ec643-df2e-426f-a88d-cbc5dd9dabb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725354586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.725354586
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.4250797218
Short name T464
Test name
Test status
Simulation time 883385471 ps
CPU time 11.5 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:21 PM PDT 24
Peak memory 217964 kb
Host smart-a84f6ce5-cfcd-49b3-8db1-8a3e6804bf7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250797218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.4250797218
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2224598533
Short name T392
Test name
Test status
Simulation time 3777211557 ps
CPU time 8.84 seconds
Started May 19 01:04:11 PM PDT 24
Finished May 19 01:04:21 PM PDT 24
Peak memory 218064 kb
Host smart-5a564ec8-5090-468f-8ddc-7276611677b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224598533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2224598533
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2610869870
Short name T826
Test name
Test status
Simulation time 212047849 ps
CPU time 8.3 seconds
Started May 19 01:04:07 PM PDT 24
Finished May 19 01:04:16 PM PDT 24
Peak memory 224888 kb
Host smart-3a069def-5ba0-4765-b3db-cfda2a7de824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610869870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2610869870
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.631892861
Short name T189
Test name
Test status
Simulation time 1337834611 ps
CPU time 5.96 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:16 PM PDT 24
Peak memory 214516 kb
Host smart-7788b714-f61f-4b75-9939-5e1a6ee235cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631892861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.631892861
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3587068110
Short name T410
Test name
Test status
Simulation time 205395012 ps
CPU time 19.09 seconds
Started May 19 01:04:10 PM PDT 24
Finished May 19 01:04:30 PM PDT 24
Peak memory 250928 kb
Host smart-f22c1917-c58b-4da8-855d-8066549e0a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587068110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3587068110
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1987731093
Short name T260
Test name
Test status
Simulation time 811817310 ps
CPU time 7.66 seconds
Started May 19 01:04:11 PM PDT 24
Finished May 19 01:04:19 PM PDT 24
Peak memory 246672 kb
Host smart-e425c9f2-dbc0-40d5-af8d-c43be2bc5b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987731093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1987731093
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2284284918
Short name T456
Test name
Test status
Simulation time 21383530485 ps
CPU time 422.47 seconds
Started May 19 01:04:10 PM PDT 24
Finished May 19 01:11:13 PM PDT 24
Peak memory 277152 kb
Host smart-15ea5021-c557-4a49-bd9b-4e6e3e970333
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284284918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2284284918
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.43428740
Short name T183
Test name
Test status
Simulation time 68193974859 ps
CPU time 569.03 seconds
Started May 19 01:04:08 PM PDT 24
Finished May 19 01:13:38 PM PDT 24
Peak memory 300260 kb
Host smart-d1d88e5c-9b61-49ce-a37f-9e2c0fb3f45f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=43428740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.43428740
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.781598223
Short name T669
Test name
Test status
Simulation time 13395220 ps
CPU time 0.94 seconds
Started May 19 01:04:10 PM PDT 24
Finished May 19 01:04:12 PM PDT 24
Peak memory 208700 kb
Host smart-30ebdea5-c61e-4393-ba58-4e12480bd194
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781598223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.781598223
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4156507713
Short name T719
Test name
Test status
Simulation time 20295396 ps
CPU time 1.19 seconds
Started May 19 01:04:15 PM PDT 24
Finished May 19 01:04:17 PM PDT 24
Peak memory 209624 kb
Host smart-9f823680-5054-4643-b47e-30c8a4912ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156507713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4156507713
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2389966315
Short name T471
Test name
Test status
Simulation time 1147324451 ps
CPU time 9.85 seconds
Started May 19 01:04:08 PM PDT 24
Finished May 19 01:04:18 PM PDT 24
Peak memory 218032 kb
Host smart-a1587b9e-f9a9-4300-b639-b8ff03f406e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389966315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2389966315
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2009471980
Short name T554
Test name
Test status
Simulation time 1215078455 ps
CPU time 3.69 seconds
Started May 19 01:04:11 PM PDT 24
Finished May 19 01:04:16 PM PDT 24
Peak memory 209560 kb
Host smart-5075ad4e-4bb7-4fe5-8def-723b03720dac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009471980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2009471980
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3942545723
Short name T607
Test name
Test status
Simulation time 5633488696 ps
CPU time 23.97 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:34 PM PDT 24
Peak memory 218400 kb
Host smart-7f99ab66-9f8b-4d05-ba3e-fd18af12aa21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942545723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3942545723
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2963428112
Short name T830
Test name
Test status
Simulation time 534469848 ps
CPU time 10.76 seconds
Started May 19 01:04:10 PM PDT 24
Finished May 19 01:04:22 PM PDT 24
Peak memory 217968 kb
Host smart-56223918-8be0-4c9d-a4bb-28b8a840ddbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963428112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2963428112
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.4109047765
Short name T835
Test name
Test status
Simulation time 41306260 ps
CPU time 1.8 seconds
Started May 19 01:04:15 PM PDT 24
Finished May 19 01:04:18 PM PDT 24
Peak memory 212660 kb
Host smart-4b15d889-f1f5-4959-a34e-0f27b872cc0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109047765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.4109047765
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.231257877
Short name T770
Test name
Test status
Simulation time 2258058737 ps
CPU time 40.39 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:51 PM PDT 24
Peak memory 250944 kb
Host smart-4caaad39-e662-4c07-8050-ea4f9514f7eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231257877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.231257877
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1590668559
Short name T497
Test name
Test status
Simulation time 494023673 ps
CPU time 17.64 seconds
Started May 19 01:04:15 PM PDT 24
Finished May 19 01:04:33 PM PDT 24
Peak memory 250884 kb
Host smart-e8811c1f-b831-49ee-8b9e-3a8ca6338f1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590668559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1590668559
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3445869467
Short name T794
Test name
Test status
Simulation time 49921617 ps
CPU time 1.8 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:12 PM PDT 24
Peak memory 217996 kb
Host smart-dc460d5e-68f4-483d-8d3d-1677c8b49200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445869467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3445869467
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3157806599
Short name T709
Test name
Test status
Simulation time 1262599176 ps
CPU time 20.03 seconds
Started May 19 01:04:14 PM PDT 24
Finished May 19 01:04:34 PM PDT 24
Peak memory 226112 kb
Host smart-27c5f14d-4faf-403d-beef-f91d74ee931b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157806599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3157806599
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1326883472
Short name T292
Test name
Test status
Simulation time 6340342049 ps
CPU time 12.61 seconds
Started May 19 01:04:14 PM PDT 24
Finished May 19 01:04:28 PM PDT 24
Peak memory 218068 kb
Host smart-3c3b5dce-ff63-4394-90cb-eae0d0babd36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326883472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1326883472
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2773759972
Short name T817
Test name
Test status
Simulation time 444923988 ps
CPU time 10.79 seconds
Started May 19 01:04:16 PM PDT 24
Finished May 19 01:04:27 PM PDT 24
Peak memory 217996 kb
Host smart-dae0e698-534c-424c-87b7-5160fc612da2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773759972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2773759972
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.4085415203
Short name T60
Test name
Test status
Simulation time 324587896 ps
CPU time 13.28 seconds
Started May 19 01:04:10 PM PDT 24
Finished May 19 01:04:24 PM PDT 24
Peak memory 218072 kb
Host smart-766db90c-a8dc-4b9e-9da0-49dca3657851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085415203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.4085415203
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1248752951
Short name T574
Test name
Test status
Simulation time 302822726 ps
CPU time 1.92 seconds
Started May 19 01:04:08 PM PDT 24
Finished May 19 01:04:11 PM PDT 24
Peak memory 213580 kb
Host smart-2ea9f3f8-2d92-4761-8dc9-e29234986909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248752951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1248752951
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.526908579
Short name T640
Test name
Test status
Simulation time 564948309 ps
CPU time 31.98 seconds
Started May 19 01:04:15 PM PDT 24
Finished May 19 01:04:48 PM PDT 24
Peak memory 250928 kb
Host smart-cf6ffd87-7972-490d-920c-ab6b1bf65666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526908579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.526908579
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1554099389
Short name T428
Test name
Test status
Simulation time 67747837 ps
CPU time 3.94 seconds
Started May 19 01:04:09 PM PDT 24
Finished May 19 01:04:14 PM PDT 24
Peak memory 222540 kb
Host smart-e2425d99-910e-4fb5-99de-22b78b421a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554099389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1554099389
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3945471732
Short name T534
Test name
Test status
Simulation time 12282912 ps
CPU time 1.02 seconds
Started May 19 01:04:14 PM PDT 24
Finished May 19 01:04:16 PM PDT 24
Peak memory 211600 kb
Host smart-ec55f0a2-709b-46b4-98ff-617a4e39cea7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945471732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3945471732
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.604511777
Short name T300
Test name
Test status
Simulation time 75037253 ps
CPU time 1.17 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:22 PM PDT 24
Peak memory 209580 kb
Host smart-e981eb9f-29af-4f5d-bc27-e8c5705b8ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604511777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.604511777
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.748848894
Short name T380
Test name
Test status
Simulation time 3099346858 ps
CPU time 16.13 seconds
Started May 19 01:04:14 PM PDT 24
Finished May 19 01:04:30 PM PDT 24
Peak memory 219020 kb
Host smart-7e9dcfb1-ece2-4935-960b-a969c8b5a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748848894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.748848894
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3699638134
Short name T713
Test name
Test status
Simulation time 3438179588 ps
CPU time 5.01 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:26 PM PDT 24
Peak memory 209636 kb
Host smart-4c6f327c-a741-4342-89ad-4b5381ab6ee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699638134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3699638134
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.551255740
Short name T690
Test name
Test status
Simulation time 12835953194 ps
CPU time 87.86 seconds
Started May 19 01:04:21 PM PDT 24
Finished May 19 01:05:50 PM PDT 24
Peak memory 218952 kb
Host smart-a2683146-2828-46bc-8fc7-a3106bb59ad8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551255740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.551255740
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.969298743
Short name T685
Test name
Test status
Simulation time 3683228670 ps
CPU time 26.43 seconds
Started May 19 01:04:21 PM PDT 24
Finished May 19 01:04:49 PM PDT 24
Peak memory 218952 kb
Host smart-b6cb4756-ffd1-4706-bf1a-55d58d337ec2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969298743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.969298743
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2260379544
Short name T515
Test name
Test status
Simulation time 273160306 ps
CPU time 8.04 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:30 PM PDT 24
Peak memory 213564 kb
Host smart-58b8e79e-531a-4b54-a33b-dfcfdc7aa85b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260379544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2260379544
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1636413380
Short name T162
Test name
Test status
Simulation time 7714463832 ps
CPU time 48.27 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:05:09 PM PDT 24
Peak memory 276616 kb
Host smart-27a9ea4f-7368-42ba-bfb0-65459a76ae71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636413380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1636413380
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1107939571
Short name T3
Test name
Test status
Simulation time 2872746800 ps
CPU time 13.08 seconds
Started May 19 01:04:21 PM PDT 24
Finished May 19 01:04:35 PM PDT 24
Peak memory 250952 kb
Host smart-1c34daee-3b52-4895-a352-c6e48a3c521d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107939571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1107939571
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.144054066
Short name T304
Test name
Test status
Simulation time 65568852 ps
CPU time 1.54 seconds
Started May 19 01:04:17 PM PDT 24
Finished May 19 01:04:19 PM PDT 24
Peak memory 218120 kb
Host smart-0e2727e7-59e5-4d8a-a03b-49719312ea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144054066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.144054066
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.92081733
Short name T629
Test name
Test status
Simulation time 415593962 ps
CPU time 14.49 seconds
Started May 19 01:04:21 PM PDT 24
Finished May 19 01:04:37 PM PDT 24
Peak memory 218916 kb
Host smart-0d3cf8a4-2e14-46b4-a8df-71c75f018aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92081733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.92081733
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3389932116
Short name T616
Test name
Test status
Simulation time 683095660 ps
CPU time 10.46 seconds
Started May 19 01:04:23 PM PDT 24
Finished May 19 01:04:34 PM PDT 24
Peak memory 217928 kb
Host smart-8f58e2c8-cd21-404a-a089-691d49730910
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389932116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3389932116
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.109018744
Short name T457
Test name
Test status
Simulation time 238933398 ps
CPU time 8.75 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:29 PM PDT 24
Peak memory 217952 kb
Host smart-9e4e18cb-0cbe-4193-be31-bd86dcd12473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109018744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.109018744
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.600583043
Short name T653
Test name
Test status
Simulation time 6900612938 ps
CPU time 10.07 seconds
Started May 19 01:04:14 PM PDT 24
Finished May 19 01:04:25 PM PDT 24
Peak memory 218136 kb
Host smart-f36802d6-20a0-4685-8cae-a40d6689197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600583043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.600583043
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3116486372
Short name T644
Test name
Test status
Simulation time 106912298 ps
CPU time 2.07 seconds
Started May 19 01:04:13 PM PDT 24
Finished May 19 01:04:16 PM PDT 24
Peak memory 214120 kb
Host smart-9887161e-b9df-4b71-b2bd-b249b57311fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116486372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3116486372
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.4075988921
Short name T806
Test name
Test status
Simulation time 250372003 ps
CPU time 29.24 seconds
Started May 19 01:04:15 PM PDT 24
Finished May 19 01:04:45 PM PDT 24
Peak memory 251020 kb
Host smart-c213fca7-f672-4e94-baaf-71a2b425a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075988921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.4075988921
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2948120624
Short name T801
Test name
Test status
Simulation time 46497455 ps
CPU time 6.57 seconds
Started May 19 01:04:14 PM PDT 24
Finished May 19 01:04:22 PM PDT 24
Peak memory 246600 kb
Host smart-b811aca8-dbe3-4a0a-97e9-7ac1bb217533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948120624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2948120624
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4170729716
Short name T416
Test name
Test status
Simulation time 7157994219 ps
CPU time 102.7 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:06:03 PM PDT 24
Peak memory 273796 kb
Host smart-4f058fb1-f8ab-4627-a837-f47f83e67984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170729716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4170729716
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3662205818
Short name T865
Test name
Test status
Simulation time 64099200825 ps
CPU time 598.22 seconds
Started May 19 01:04:19 PM PDT 24
Finished May 19 01:14:18 PM PDT 24
Peak memory 284032 kb
Host smart-0e631f42-1177-47bc-a465-2e9b35a92132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3662205818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3662205818
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3657689569
Short name T605
Test name
Test status
Simulation time 15526278 ps
CPU time 0.95 seconds
Started May 19 01:04:16 PM PDT 24
Finished May 19 01:04:17 PM PDT 24
Peak memory 211588 kb
Host smart-fd3c6a42-3b30-4679-8325-856e161f5708
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657689569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3657689569
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3989895851
Short name T240
Test name
Test status
Simulation time 27151011 ps
CPU time 1.29 seconds
Started May 19 01:04:25 PM PDT 24
Finished May 19 01:04:27 PM PDT 24
Peak memory 209540 kb
Host smart-934a1e34-5bdc-494e-8ab2-cf63ffeb5bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989895851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3989895851
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3117162646
Short name T51
Test name
Test status
Simulation time 217311859 ps
CPU time 7.86 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:29 PM PDT 24
Peak memory 218016 kb
Host smart-a28ae81c-400f-4899-aa28-ef064e8418c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117162646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3117162646
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3823318363
Short name T419
Test name
Test status
Simulation time 264343160 ps
CPU time 1.6 seconds
Started May 19 01:04:27 PM PDT 24
Finished May 19 01:04:29 PM PDT 24
Peak memory 216900 kb
Host smart-cc07f22e-13ea-4bfc-9ad2-b4a2dcf67f01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823318363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3823318363
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.200303154
Short name T695
Test name
Test status
Simulation time 5351807418 ps
CPU time 70.78 seconds
Started May 19 01:04:26 PM PDT 24
Finished May 19 01:05:38 PM PDT 24
Peak memory 218120 kb
Host smart-275992d3-b5cb-43f1-9e29-d6ceced3e0d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200303154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.200303154
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3633229429
Short name T221
Test name
Test status
Simulation time 163765068 ps
CPU time 5.4 seconds
Started May 19 01:04:27 PM PDT 24
Finished May 19 01:04:33 PM PDT 24
Peak memory 218016 kb
Host smart-25dd897a-c37d-44f4-8faf-2da92c20da7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633229429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3633229429
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2924379138
Short name T804
Test name
Test status
Simulation time 846719056 ps
CPU time 9.7 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:31 PM PDT 24
Peak memory 213632 kb
Host smart-d18a4d85-29a5-49a8-9261-16d67e96ae80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924379138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2924379138
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2529777976
Short name T219
Test name
Test status
Simulation time 10992419516 ps
CPU time 90.65 seconds
Started May 19 01:04:22 PM PDT 24
Finished May 19 01:05:54 PM PDT 24
Peak memory 273920 kb
Host smart-db3b176e-9f84-483c-ab68-d84047d78981
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529777976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2529777976
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1010942687
Short name T728
Test name
Test status
Simulation time 334717472 ps
CPU time 11.35 seconds
Started May 19 01:04:23 PM PDT 24
Finished May 19 01:04:35 PM PDT 24
Peak memory 221660 kb
Host smart-f2f38c69-8ab3-44e7-85cf-9ef8c1be8d33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010942687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1010942687
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.627391516
Short name T563
Test name
Test status
Simulation time 130912518 ps
CPU time 2.2 seconds
Started May 19 01:04:22 PM PDT 24
Finished May 19 01:04:25 PM PDT 24
Peak memory 218104 kb
Host smart-8cf402f7-a2c0-4eca-9d31-70cbd5f40b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627391516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.627391516
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2741054135
Short name T488
Test name
Test status
Simulation time 425866592 ps
CPU time 19.91 seconds
Started May 19 01:04:26 PM PDT 24
Finished May 19 01:04:47 PM PDT 24
Peak memory 218948 kb
Host smart-e185391c-52fe-4a84-b90f-6a327bdefba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741054135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2741054135
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3413599812
Short name T252
Test name
Test status
Simulation time 1866517068 ps
CPU time 10.94 seconds
Started May 19 01:04:26 PM PDT 24
Finished May 19 01:04:37 PM PDT 24
Peak memory 217980 kb
Host smart-1c493949-5d52-494a-b842-a4d89409c5ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413599812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3413599812
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.280393223
Short name T253
Test name
Test status
Simulation time 238353037 ps
CPU time 7.19 seconds
Started May 19 01:04:26 PM PDT 24
Finished May 19 01:04:33 PM PDT 24
Peak memory 217916 kb
Host smart-2788de21-723b-46b0-a044-0f68d3369046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280393223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.280393223
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1732749983
Short name T799
Test name
Test status
Simulation time 359480148 ps
CPU time 8.34 seconds
Started May 19 01:04:22 PM PDT 24
Finished May 19 01:04:31 PM PDT 24
Peak memory 218136 kb
Host smart-20477eae-d671-4396-8aeb-f27ba294ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732749983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1732749983
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.42650071
Short name T612
Test name
Test status
Simulation time 336549452 ps
CPU time 9.23 seconds
Started May 19 01:04:22 PM PDT 24
Finished May 19 01:04:32 PM PDT 24
Peak memory 217740 kb
Host smart-f68f931e-896d-46f1-a460-7960311d5be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42650071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.42650071
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.77939317
Short name T230
Test name
Test status
Simulation time 215614825 ps
CPU time 21.25 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:43 PM PDT 24
Peak memory 250928 kb
Host smart-f1351b55-0ad0-4a8a-a8af-ee6a38234fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77939317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.77939317
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1551252122
Short name T250
Test name
Test status
Simulation time 997294282 ps
CPU time 3.01 seconds
Started May 19 01:04:21 PM PDT 24
Finished May 19 01:04:25 PM PDT 24
Peak memory 222184 kb
Host smart-bee18cc7-0594-4626-88f5-2e287fe7d93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551252122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1551252122
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2778468351
Short name T803
Test name
Test status
Simulation time 5152221913 ps
CPU time 109.39 seconds
Started May 19 01:04:26 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 267920 kb
Host smart-2f80e58d-9086-49fa-8ecd-c4b817cc03a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778468351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2778468351
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2306541947
Short name T318
Test name
Test status
Simulation time 38283724 ps
CPU time 1.01 seconds
Started May 19 01:04:20 PM PDT 24
Finished May 19 01:04:23 PM PDT 24
Peak memory 211552 kb
Host smart-4f60d8e3-a719-4c5a-83c9-65dbcd5a8361
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306541947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2306541947
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1702103076
Short name T671
Test name
Test status
Simulation time 30731567 ps
CPU time 0.93 seconds
Started May 19 01:04:37 PM PDT 24
Finished May 19 01:04:38 PM PDT 24
Peak memory 209616 kb
Host smart-0b072717-b341-483c-a626-336122476c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702103076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1702103076
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2588617629
Short name T433
Test name
Test status
Simulation time 1963393584 ps
CPU time 14.39 seconds
Started May 19 01:04:33 PM PDT 24
Finished May 19 01:04:48 PM PDT 24
Peak memory 218004 kb
Host smart-9f8b4dc1-7741-4fa1-97c3-2b277680b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588617629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2588617629
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.635377792
Short name T721
Test name
Test status
Simulation time 1223148097 ps
CPU time 5.91 seconds
Started May 19 01:04:32 PM PDT 24
Finished May 19 01:04:38 PM PDT 24
Peak memory 209568 kb
Host smart-6654fc6a-52e8-4ad8-942a-84aab15b7a0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635377792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.635377792
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3045835637
Short name T407
Test name
Test status
Simulation time 940277711 ps
CPU time 19.57 seconds
Started May 19 01:04:32 PM PDT 24
Finished May 19 01:04:52 PM PDT 24
Peak memory 217944 kb
Host smart-1d4aff0e-5137-4ce9-81d8-9e0c1c07d9c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045835637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3045835637
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.724566864
Short name T402
Test name
Test status
Simulation time 3522320021 ps
CPU time 8.59 seconds
Started May 19 01:04:38 PM PDT 24
Finished May 19 01:04:47 PM PDT 24
Peak memory 218136 kb
Host smart-3f3ea8e4-9c87-40b9-b25f-e3d72887cc11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724566864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.724566864
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2485760709
Short name T354
Test name
Test status
Simulation time 363034384 ps
CPU time 5.55 seconds
Started May 19 01:04:32 PM PDT 24
Finished May 19 01:04:38 PM PDT 24
Peak memory 213684 kb
Host smart-a11f3819-e507-4dab-b0f5-83e70bbe058a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485760709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2485760709
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3263422497
Short name T344
Test name
Test status
Simulation time 3566710267 ps
CPU time 31.16 seconds
Started May 19 01:04:31 PM PDT 24
Finished May 19 01:05:03 PM PDT 24
Peak memory 250988 kb
Host smart-632f1623-ce19-45f1-ac08-620c01b36d1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263422497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3263422497
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.166840140
Short name T725
Test name
Test status
Simulation time 1939265474 ps
CPU time 31.06 seconds
Started May 19 01:04:34 PM PDT 24
Finished May 19 01:05:06 PM PDT 24
Peak memory 250832 kb
Host smart-8650b3c2-966e-4c86-9b0b-18fc58c984db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166840140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.166840140
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.417362527
Short name T609
Test name
Test status
Simulation time 52627648 ps
CPU time 2.31 seconds
Started May 19 01:04:30 PM PDT 24
Finished May 19 01:04:33 PM PDT 24
Peak memory 218016 kb
Host smart-3e23cf97-4e78-4e53-be5b-3ccfbe6c476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417362527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.417362527
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.848228573
Short name T320
Test name
Test status
Simulation time 592625779 ps
CPU time 11.79 seconds
Started May 19 01:04:34 PM PDT 24
Finished May 19 01:04:46 PM PDT 24
Peak memory 226092 kb
Host smart-afc35054-8c73-4efa-9fec-a3ccf55f7689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848228573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.848228573
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1760912159
Short name T43
Test name
Test status
Simulation time 587057095 ps
CPU time 13.11 seconds
Started May 19 01:04:31 PM PDT 24
Finished May 19 01:04:45 PM PDT 24
Peak memory 218056 kb
Host smart-cc3ad3eb-bce7-454f-9590-4b49f1d45ad8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760912159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1760912159
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3869919006
Short name T617
Test name
Test status
Simulation time 286137554 ps
CPU time 10.74 seconds
Started May 19 01:04:32 PM PDT 24
Finished May 19 01:04:43 PM PDT 24
Peak memory 218040 kb
Host smart-e0b3a934-98a6-4183-9148-ecae8e858360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869919006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3869919006
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2468627464
Short name T216
Test name
Test status
Simulation time 369395482 ps
CPU time 10.75 seconds
Started May 19 01:04:31 PM PDT 24
Finished May 19 01:04:43 PM PDT 24
Peak memory 218076 kb
Host smart-2fe984e7-9ac1-4927-9c14-d797ac995c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468627464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2468627464
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2013128332
Short name T779
Test name
Test status
Simulation time 398511328 ps
CPU time 2.83 seconds
Started May 19 01:04:26 PM PDT 24
Finished May 19 01:04:29 PM PDT 24
Peak memory 214464 kb
Host smart-4578141a-fc68-4a09-9f1c-9c65f9e9e797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013128332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2013128332
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1985804120
Short name T151
Test name
Test status
Simulation time 189855715 ps
CPU time 22.86 seconds
Started May 19 01:04:24 PM PDT 24
Finished May 19 01:04:48 PM PDT 24
Peak memory 251048 kb
Host smart-a9b62b3f-4dcb-413c-8836-a43e6401e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985804120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1985804120
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.293046522
Short name T337
Test name
Test status
Simulation time 231483047 ps
CPU time 9.92 seconds
Started May 19 01:04:32 PM PDT 24
Finished May 19 01:04:42 PM PDT 24
Peak memory 251216 kb
Host smart-9b67c987-e091-4541-9060-6910268530c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293046522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.293046522
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4084581135
Short name T683
Test name
Test status
Simulation time 26937311 ps
CPU time 0.93 seconds
Started May 19 01:04:26 PM PDT 24
Finished May 19 01:04:28 PM PDT 24
Peak memory 211456 kb
Host smart-20fa6a5e-9930-438c-875b-6743752115b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084581135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4084581135
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.322526632
Short name T175
Test name
Test status
Simulation time 55618769 ps
CPU time 1.01 seconds
Started May 19 01:04:50 PM PDT 24
Finished May 19 01:04:52 PM PDT 24
Peak memory 209468 kb
Host smart-ad10c90b-e080-4004-8b95-0451c9e7026e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322526632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.322526632
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1679762684
Short name T361
Test name
Test status
Simulation time 245621986 ps
CPU time 9.73 seconds
Started May 19 01:04:38 PM PDT 24
Finished May 19 01:04:48 PM PDT 24
Peak memory 217992 kb
Host smart-aec33428-2df8-424a-9f9b-3f11ac7b3c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679762684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1679762684
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2219158662
Short name T211
Test name
Test status
Simulation time 539232970 ps
CPU time 1.11 seconds
Started May 19 01:04:38 PM PDT 24
Finished May 19 01:04:39 PM PDT 24
Peak memory 209548 kb
Host smart-68b3b004-150c-4a64-a8fa-5b47d1ae7ef2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219158662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2219158662
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.119037429
Short name T567
Test name
Test status
Simulation time 5791695914 ps
CPU time 44.54 seconds
Started May 19 01:04:35 PM PDT 24
Finished May 19 01:05:20 PM PDT 24
Peak memory 218012 kb
Host smart-71c7ad90-05b0-435a-b669-dae0ecddc816
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119037429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.119037429
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2886584485
Short name T710
Test name
Test status
Simulation time 355734061 ps
CPU time 2.38 seconds
Started May 19 01:04:39 PM PDT 24
Finished May 19 01:04:42 PM PDT 24
Peak memory 217988 kb
Host smart-d63e5c7f-17bd-4ada-aa3c-f683b23aa330
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886584485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2886584485
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3150857677
Short name T793
Test name
Test status
Simulation time 1454615995 ps
CPU time 5.1 seconds
Started May 19 01:04:36 PM PDT 24
Finished May 19 01:04:41 PM PDT 24
Peak memory 213288 kb
Host smart-9eebeb31-dc3c-42c0-a018-0ebb56978e17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150857677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3150857677
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.662672599
Short name T327
Test name
Test status
Simulation time 21817906501 ps
CPU time 85.38 seconds
Started May 19 01:04:38 PM PDT 24
Finished May 19 01:06:04 PM PDT 24
Peak memory 282744 kb
Host smart-e893a6e0-3448-4bfb-8ce8-8dc9c5e2bace
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662672599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.662672599
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2360439651
Short name T413
Test name
Test status
Simulation time 315696110 ps
CPU time 9.77 seconds
Started May 19 01:04:37 PM PDT 24
Finished May 19 01:04:47 PM PDT 24
Peak memory 247456 kb
Host smart-9cee2dcd-24a0-41c1-a3b7-7b644e37e566
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360439651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2360439651
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3025215973
Short name T694
Test name
Test status
Simulation time 19749958 ps
CPU time 1.83 seconds
Started May 19 01:04:37 PM PDT 24
Finished May 19 01:04:40 PM PDT 24
Peak memory 218052 kb
Host smart-83c55490-4f75-4038-bae8-22f1fdf057bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025215973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3025215973
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1060514175
Short name T598
Test name
Test status
Simulation time 354289431 ps
CPU time 12.99 seconds
Started May 19 01:04:43 PM PDT 24
Finished May 19 01:04:57 PM PDT 24
Peak memory 218980 kb
Host smart-858b6555-a84b-4fad-9707-05db13689d85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060514175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1060514175
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2764702774
Short name T661
Test name
Test status
Simulation time 1306354015 ps
CPU time 10.94 seconds
Started May 19 01:04:43 PM PDT 24
Finished May 19 01:04:55 PM PDT 24
Peak memory 218012 kb
Host smart-64e90669-7d15-483b-be61-63fa7b9fd0d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764702774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2764702774
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.63754977
Short name T460
Test name
Test status
Simulation time 1200696016 ps
CPU time 10.16 seconds
Started May 19 01:04:43 PM PDT 24
Finished May 19 01:04:55 PM PDT 24
Peak memory 218072 kb
Host smart-d795ff30-5764-4c19-994a-493119951f36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63754977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.63754977
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.4149761944
Short name T349
Test name
Test status
Simulation time 163561945 ps
CPU time 6.95 seconds
Started May 19 01:04:37 PM PDT 24
Finished May 19 01:04:45 PM PDT 24
Peak memory 218088 kb
Host smart-93ea7fe5-ae65-4f6c-8fdd-cb115547e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149761944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.4149761944
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1764199189
Short name T272
Test name
Test status
Simulation time 40285655 ps
CPU time 2.94 seconds
Started May 19 01:04:39 PM PDT 24
Finished May 19 01:04:43 PM PDT 24
Peak memory 217972 kb
Host smart-b72bc5ea-0d3e-4a8d-9bb5-5c078611b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764199189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1764199189
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3228516575
Short name T810
Test name
Test status
Simulation time 198117615 ps
CPU time 21.39 seconds
Started May 19 01:04:39 PM PDT 24
Finished May 19 01:05:01 PM PDT 24
Peak memory 250972 kb
Host smart-3763f85e-98bb-4f53-a4a3-9daa193149c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228516575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3228516575
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1754335400
Short name T760
Test name
Test status
Simulation time 89048238 ps
CPU time 4.1 seconds
Started May 19 01:04:40 PM PDT 24
Finished May 19 01:04:44 PM PDT 24
Peak memory 217980 kb
Host smart-d5b7a0e3-33c5-42aa-b137-6d2be4b1f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754335400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1754335400
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2351225308
Short name T517
Test name
Test status
Simulation time 45636345258 ps
CPU time 627.5 seconds
Started May 19 01:04:50 PM PDT 24
Finished May 19 01:15:19 PM PDT 24
Peak memory 227840 kb
Host smart-0cc5c9e2-eb9e-47ea-a97e-505a73ea3b5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351225308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2351225308
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2019241548
Short name T39
Test name
Test status
Simulation time 16897801 ps
CPU time 1.17 seconds
Started May 19 01:04:37 PM PDT 24
Finished May 19 01:04:39 PM PDT 24
Peak memory 211596 kb
Host smart-43fee7e5-a7bf-4888-986a-3fc5f98721a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019241548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2019241548
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1737111242
Short name T269
Test name
Test status
Simulation time 23636696 ps
CPU time 0.94 seconds
Started May 19 01:04:48 PM PDT 24
Finished May 19 01:04:50 PM PDT 24
Peak memory 209580 kb
Host smart-9e99c305-c84c-4eff-b9c8-b543b0009df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737111242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1737111242
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.98562424
Short name T313
Test name
Test status
Simulation time 1659810315 ps
CPU time 14.43 seconds
Started May 19 01:04:50 PM PDT 24
Finished May 19 01:05:06 PM PDT 24
Peak memory 217892 kb
Host smart-7d1d8a48-bdb7-4504-a69d-8477f1c04163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98562424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.98562424
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1369604563
Short name T790
Test name
Test status
Simulation time 1062840999 ps
CPU time 4.69 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:04:50 PM PDT 24
Peak memory 209516 kb
Host smart-cb75e874-aa70-4cae-aa92-2a19a88235a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369604563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1369604563
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3459994263
Short name T752
Test name
Test status
Simulation time 2371550119 ps
CPU time 34.85 seconds
Started May 19 01:04:41 PM PDT 24
Finished May 19 01:05:17 PM PDT 24
Peak memory 218908 kb
Host smart-39e4b22c-719e-43e2-9829-0123f9048578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459994263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3459994263
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1645402974
Short name T747
Test name
Test status
Simulation time 697428860 ps
CPU time 5.78 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:04:51 PM PDT 24
Peak memory 217972 kb
Host smart-c9f80deb-b224-456b-9c65-0c3bd0c1694c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645402974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1645402974
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.854481474
Short name T421
Test name
Test status
Simulation time 403792595 ps
CPU time 6.21 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:04:51 PM PDT 24
Peak memory 213800 kb
Host smart-4b937a0a-6b0c-4753-b9d8-9cdff1dcfc65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854481474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
854481474
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1474755445
Short name T476
Test name
Test status
Simulation time 6184561480 ps
CPU time 61.86 seconds
Started May 19 01:04:42 PM PDT 24
Finished May 19 01:05:44 PM PDT 24
Peak memory 276648 kb
Host smart-f593e1fd-4cb3-4419-851b-b4f9e142cc0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474755445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1474755445
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.15393620
Short name T620
Test name
Test status
Simulation time 1680371840 ps
CPU time 19.29 seconds
Started May 19 01:04:43 PM PDT 24
Finished May 19 01:05:03 PM PDT 24
Peak memory 250848 kb
Host smart-c5081d10-2f30-4a16-8ef7-ea1e5148f70b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15393620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_j
tag_state_post_trans.15393620
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2804000405
Short name T238
Test name
Test status
Simulation time 250471196 ps
CPU time 2.75 seconds
Started May 19 01:04:43 PM PDT 24
Finished May 19 01:04:46 PM PDT 24
Peak memory 217932 kb
Host smart-44f8ee18-421e-4aab-afba-7479ed4cb363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804000405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2804000405
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.993279801
Short name T767
Test name
Test status
Simulation time 1384464043 ps
CPU time 8.61 seconds
Started May 19 01:04:48 PM PDT 24
Finished May 19 01:04:57 PM PDT 24
Peak memory 218140 kb
Host smart-799ee435-f3b8-451e-ac23-4d02afc4a351
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993279801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.993279801
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1736166747
Short name T525
Test name
Test status
Simulation time 797435591 ps
CPU time 14.44 seconds
Started May 19 01:04:50 PM PDT 24
Finished May 19 01:05:06 PM PDT 24
Peak memory 217876 kb
Host smart-5523fc6c-c1f2-42a3-a830-03c00244c1d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736166747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1736166747
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.222016687
Short name T386
Test name
Test status
Simulation time 750657186 ps
CPU time 8.11 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:04:53 PM PDT 24
Peak memory 217964 kb
Host smart-c795fa73-400b-4ba6-a933-812da7c153ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222016687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.222016687
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3023497457
Short name T743
Test name
Test status
Simulation time 470846403 ps
CPU time 8.69 seconds
Started May 19 01:04:42 PM PDT 24
Finished May 19 01:04:52 PM PDT 24
Peak memory 218052 kb
Host smart-0cd35d5f-859f-4530-a17e-a5f2adf9eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023497457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3023497457
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1876208511
Short name T243
Test name
Test status
Simulation time 151290594 ps
CPU time 2.75 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:04:48 PM PDT 24
Peak memory 213648 kb
Host smart-0b9cb30f-af9a-48f8-9d19-0a08d2057b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876208511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1876208511
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.240109774
Short name T298
Test name
Test status
Simulation time 443582643 ps
CPU time 22.01 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:05:07 PM PDT 24
Peak memory 250948 kb
Host smart-32856d4f-7300-4947-abf2-564dc4e31c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240109774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.240109774
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4122996736
Short name T33
Test name
Test status
Simulation time 72774475 ps
CPU time 6.93 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:04:52 PM PDT 24
Peak memory 250912 kb
Host smart-5b24a467-e4f7-456c-96b8-8f41a5ca4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122996736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4122996736
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.436725113
Short name T659
Test name
Test status
Simulation time 1605998941 ps
CPU time 70.43 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:06:07 PM PDT 24
Peak memory 251052 kb
Host smart-21358693-9f2c-4899-89a6-64767944764e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436725113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.436725113
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1488750582
Short name T330
Test name
Test status
Simulation time 13586634 ps
CPU time 0.97 seconds
Started May 19 01:04:44 PM PDT 24
Finished May 19 01:04:46 PM PDT 24
Peak memory 208644 kb
Host smart-da4f4bef-5a0a-4f1b-970c-41a9f83d90cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488750582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1488750582
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.991271970
Short name T636
Test name
Test status
Simulation time 25232742 ps
CPU time 1.32 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:05:05 PM PDT 24
Peak memory 209568 kb
Host smart-9d3c7965-7fce-47f1-a143-727301e8cdff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991271970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.991271970
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2807487522
Short name T160
Test name
Test status
Simulation time 742575417 ps
CPU time 8.32 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:04:59 PM PDT 24
Peak memory 218068 kb
Host smart-65ccd4f0-0a9a-4ee6-a711-8d1f80f8c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807487522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2807487522
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1270546268
Short name T195
Test name
Test status
Simulation time 3317272385 ps
CPU time 6.11 seconds
Started May 19 01:05:03 PM PDT 24
Finished May 19 01:05:10 PM PDT 24
Peak memory 209636 kb
Host smart-bc31907e-2e3c-4ff2-bb68-706fb851b8bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270546268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1270546268
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.871097660
Short name T336
Test name
Test status
Simulation time 4396976375 ps
CPU time 26.74 seconds
Started May 19 01:04:51 PM PDT 24
Finished May 19 01:05:19 PM PDT 24
Peak memory 218032 kb
Host smart-6695658e-7049-48af-abc5-9369e3781f84
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871097660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.871097660
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1874527337
Short name T500
Test name
Test status
Simulation time 872809899 ps
CPU time 6.34 seconds
Started May 19 01:04:56 PM PDT 24
Finished May 19 01:05:03 PM PDT 24
Peak memory 217988 kb
Host smart-54855a5e-942c-490b-be06-041376d60248
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874527337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1874527337
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1043883954
Short name T618
Test name
Test status
Simulation time 3248920341 ps
CPU time 20.95 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 214264 kb
Host smart-7ebd5db5-7b2c-409e-81ec-29b19837e4ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043883954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1043883954
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3926902135
Short name T843
Test name
Test status
Simulation time 1345606819 ps
CPU time 62.84 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 250904 kb
Host smart-ae6502b0-e3e7-4057-ac27-ddc72e3cb8dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926902135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3926902135
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1216792680
Short name T845
Test name
Test status
Simulation time 1213311383 ps
CPU time 14 seconds
Started May 19 01:04:48 PM PDT 24
Finished May 19 01:05:04 PM PDT 24
Peak memory 250388 kb
Host smart-e9daa492-ef44-407a-8ef6-b8e176c1a506
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216792680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1216792680
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.167641980
Short name T374
Test name
Test status
Simulation time 35485498 ps
CPU time 1.89 seconds
Started May 19 01:04:50 PM PDT 24
Finished May 19 01:04:53 PM PDT 24
Peak memory 218124 kb
Host smart-80833957-5cee-4a05-8ca1-a0f3a688d3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167641980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.167641980
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2842376204
Short name T275
Test name
Test status
Simulation time 869939165 ps
CPU time 8.85 seconds
Started May 19 01:04:48 PM PDT 24
Finished May 19 01:04:57 PM PDT 24
Peak memory 226132 kb
Host smart-19f44168-4b1c-4731-a84e-2750f65cd9ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842376204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2842376204
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3243630128
Short name T166
Test name
Test status
Simulation time 2435710342 ps
CPU time 13.95 seconds
Started May 19 01:04:51 PM PDT 24
Finished May 19 01:05:06 PM PDT 24
Peak memory 218000 kb
Host smart-166d9df9-10c6-403d-beeb-d79ad13c81bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243630128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3243630128
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.726641882
Short name T422
Test name
Test status
Simulation time 1900549327 ps
CPU time 8.59 seconds
Started May 19 01:04:56 PM PDT 24
Finished May 19 01:05:06 PM PDT 24
Peak memory 218072 kb
Host smart-f0700d37-a7b9-4538-aaa2-4638f67141b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726641882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.726641882
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1135316798
Short name T733
Test name
Test status
Simulation time 553348904 ps
CPU time 8.5 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:04:59 PM PDT 24
Peak memory 218072 kb
Host smart-75686b48-eda6-4035-82df-af23be4dd54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135316798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1135316798
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2232223440
Short name T861
Test name
Test status
Simulation time 48562296 ps
CPU time 2.71 seconds
Started May 19 01:04:56 PM PDT 24
Finished May 19 01:05:00 PM PDT 24
Peak memory 217872 kb
Host smart-a811c430-7651-4394-93df-fb9357480497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232223440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2232223440
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.975585760
Short name T575
Test name
Test status
Simulation time 1691663700 ps
CPU time 24.3 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:05:21 PM PDT 24
Peak memory 250980 kb
Host smart-f17caf5d-7665-458a-832b-53e72e241659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975585760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.975585760
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1326751557
Short name T735
Test name
Test status
Simulation time 480055942 ps
CPU time 8.61 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:05:00 PM PDT 24
Peak memory 250836 kb
Host smart-99fd10b2-e9d2-4713-abd6-d9a76d145dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326751557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1326751557
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2330284722
Short name T637
Test name
Test status
Simulation time 61341776276 ps
CPU time 365.09 seconds
Started May 19 01:05:03 PM PDT 24
Finished May 19 01:11:09 PM PDT 24
Peak memory 283704 kb
Host smart-9449fbd7-27eb-477e-8702-74da8a2fab20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330284722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2330284722
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.173001775
Short name T468
Test name
Test status
Simulation time 39470182 ps
CPU time 0.76 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:04:51 PM PDT 24
Peak memory 206848 kb
Host smart-693ff95f-1bf8-4c1e-9391-119d13f24f8c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173001775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.173001775
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.140325761
Short name T348
Test name
Test status
Simulation time 87451332 ps
CPU time 1.08 seconds
Started May 19 01:04:54 PM PDT 24
Finished May 19 01:04:57 PM PDT 24
Peak memory 209648 kb
Host smart-17789d0b-fc17-4343-9b80-1761644d5c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140325761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.140325761
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3150489825
Short name T664
Test name
Test status
Simulation time 1308568857 ps
CPU time 10.93 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:05:14 PM PDT 24
Peak memory 218040 kb
Host smart-852add5e-49b5-485c-b92c-031b52558db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150489825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3150489825
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2380065570
Short name T645
Test name
Test status
Simulation time 987493296 ps
CPU time 7.06 seconds
Started May 19 01:05:03 PM PDT 24
Finished May 19 01:05:11 PM PDT 24
Peak memory 209488 kb
Host smart-03123b6b-1500-4326-a1b4-5e01f6bc2bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380065570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2380065570
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1182043333
Short name T641
Test name
Test status
Simulation time 4113732455 ps
CPU time 50.73 seconds
Started May 19 01:04:48 PM PDT 24
Finished May 19 01:05:40 PM PDT 24
Peak memory 218020 kb
Host smart-293222e2-f0ab-48dc-98b1-52ee6a2748bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182043333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1182043333
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1783558293
Short name T480
Test name
Test status
Simulation time 393490956 ps
CPU time 8.04 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:04:58 PM PDT 24
Peak memory 217960 kb
Host smart-1b282bc8-dc01-4474-b3cf-69272da71a17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783558293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1783558293
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2290580681
Short name T373
Test name
Test status
Simulation time 1380564034 ps
CPU time 5.48 seconds
Started May 19 01:04:47 PM PDT 24
Finished May 19 01:04:54 PM PDT 24
Peak memory 213516 kb
Host smart-3e0d213f-4de9-4454-a616-ccb264c24e66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290580681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2290580681
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1677852385
Short name T218
Test name
Test status
Simulation time 8982730980 ps
CPU time 40.92 seconds
Started May 19 01:04:48 PM PDT 24
Finished May 19 01:05:29 PM PDT 24
Peak memory 250948 kb
Host smart-a44bd38a-1517-43e8-b869-ce6463e613ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677852385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1677852385
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1633600557
Short name T434
Test name
Test status
Simulation time 5022686196 ps
CPU time 14.45 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:05:11 PM PDT 24
Peak memory 218032 kb
Host smart-889bcb42-49be-443e-bb29-e29fc5a4126f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633600557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1633600557
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2024971196
Short name T2
Test name
Test status
Simulation time 48300765 ps
CPU time 2.33 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:04:53 PM PDT 24
Peak memory 217920 kb
Host smart-aadda59d-73fa-4c32-85cd-a19b518e5084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024971196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2024971196
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3819898288
Short name T427
Test name
Test status
Simulation time 617051877 ps
CPU time 14.78 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:05:05 PM PDT 24
Peak memory 218952 kb
Host smart-b916d40c-38ac-4b52-8378-f97ad6724030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819898288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3819898288
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2996250611
Short name T226
Test name
Test status
Simulation time 358223030 ps
CPU time 7.58 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:05:04 PM PDT 24
Peak memory 217972 kb
Host smart-0f103bee-cf0c-4e39-bfbc-a553adb99112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996250611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2996250611
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.4243534283
Short name T754
Test name
Test status
Simulation time 340085611 ps
CPU time 10.23 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:05:13 PM PDT 24
Peak memory 217988 kb
Host smart-0a8d1024-6f91-4876-9f02-e02419b754a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243534283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
4243534283
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.4002176368
Short name T31
Test name
Test status
Simulation time 251633031 ps
CPU time 10.37 seconds
Started May 19 01:04:48 PM PDT 24
Finished May 19 01:05:00 PM PDT 24
Peak memory 218348 kb
Host smart-5f77b974-ee05-41c1-8b3d-a86ec1cdfef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002176368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.4002176368
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1642645107
Short name T396
Test name
Test status
Simulation time 81095813 ps
CPU time 5.01 seconds
Started May 19 01:05:03 PM PDT 24
Finished May 19 01:05:09 PM PDT 24
Peak memory 217680 kb
Host smart-6e70f780-d4e5-4656-bd8b-a00f8fbfeaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642645107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1642645107
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2832206225
Short name T848
Test name
Test status
Simulation time 1365508960 ps
CPU time 30.36 seconds
Started May 19 01:04:49 PM PDT 24
Finished May 19 01:05:21 PM PDT 24
Peak memory 250964 kb
Host smart-73064f36-4da0-443c-b6b8-02cd08ee1ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832206225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2832206225
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3114482564
Short name T372
Test name
Test status
Simulation time 193328292 ps
CPU time 6.62 seconds
Started May 19 01:04:50 PM PDT 24
Finished May 19 01:04:58 PM PDT 24
Peak memory 250372 kb
Host smart-262db100-5de0-49f5-af03-dcbb68a47ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114482564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3114482564
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1651264722
Short name T626
Test name
Test status
Simulation time 29220915010 ps
CPU time 150.5 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:07:27 PM PDT 24
Peak memory 275828 kb
Host smart-1ca34f62-a57c-4a24-b17e-67dc4f5da416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651264722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1651264722
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3887959753
Short name T141
Test name
Test status
Simulation time 81572864146 ps
CPU time 435.99 seconds
Started May 19 01:04:56 PM PDT 24
Finished May 19 01:12:13 PM PDT 24
Peak memory 283988 kb
Host smart-250afb4d-4ea0-4a70-aea2-8b3774d48d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3887959753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3887959753
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.838581955
Short name T479
Test name
Test status
Simulation time 40506714 ps
CPU time 0.93 seconds
Started May 19 01:04:47 PM PDT 24
Finished May 19 01:04:49 PM PDT 24
Peak memory 212592 kb
Host smart-75ad16b3-6165-46db-b1fa-208d4600dd41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838581955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.838581955
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3515525539
Short name T76
Test name
Test status
Simulation time 52643299 ps
CPU time 1.03 seconds
Started May 19 01:02:52 PM PDT 24
Finished May 19 01:02:55 PM PDT 24
Peak memory 209604 kb
Host smart-3ef3fcd5-57f9-4d20-8c4f-69aeaa08dd0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515525539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3515525539
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2950123415
Short name T75
Test name
Test status
Simulation time 41028110 ps
CPU time 0.92 seconds
Started May 19 01:02:48 PM PDT 24
Finished May 19 01:02:50 PM PDT 24
Peak memory 209520 kb
Host smart-11923b13-1119-402f-ae0c-c7742e1b6d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950123415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2950123415
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1601398925
Short name T481
Test name
Test status
Simulation time 71042433 ps
CPU time 2.54 seconds
Started May 19 01:02:50 PM PDT 24
Finished May 19 01:02:53 PM PDT 24
Peak memory 209564 kb
Host smart-7d35b6ee-f1f5-48df-978e-4167712659b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601398925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1601398925
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.14274683
Short name T520
Test name
Test status
Simulation time 2984474503 ps
CPU time 40.4 seconds
Started May 19 01:02:50 PM PDT 24
Finished May 19 01:03:31 PM PDT 24
Peak memory 218032 kb
Host smart-61a96581-bd32-4c51-9e4d-7176316984c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14274683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_erro
rs.14274683
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.578536041
Short name T570
Test name
Test status
Simulation time 1800447244 ps
CPU time 39.98 seconds
Started May 19 01:02:48 PM PDT 24
Finished May 19 01:03:29 PM PDT 24
Peak memory 217804 kb
Host smart-90f5c223-581c-4eb2-a2c4-77f4daff7e4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578536041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.578536041
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2183874430
Short name T15
Test name
Test status
Simulation time 580473530 ps
CPU time 9.47 seconds
Started May 19 01:02:47 PM PDT 24
Finished May 19 01:02:57 PM PDT 24
Peak memory 218276 kb
Host smart-dbbda076-c5f7-4e3c-8b62-feb70b698000
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183874430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2183874430
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.871543514
Short name T18
Test name
Test status
Simulation time 1169689444 ps
CPU time 34.26 seconds
Started May 19 01:02:49 PM PDT 24
Finished May 19 01:03:24 PM PDT 24
Peak memory 213432 kb
Host smart-31376617-26a2-4542-b7ab-e11d0c268445
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871543514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.871543514
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3996341271
Short name T95
Test name
Test status
Simulation time 2129095672 ps
CPU time 10.18 seconds
Started May 19 01:02:49 PM PDT 24
Finished May 19 01:03:00 PM PDT 24
Peak memory 213648 kb
Host smart-93b9101c-fa89-4262-9295-6c26625fc747
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996341271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3996341271
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1093703079
Short name T180
Test name
Test status
Simulation time 2593282165 ps
CPU time 85.34 seconds
Started May 19 01:02:50 PM PDT 24
Finished May 19 01:04:17 PM PDT 24
Peak memory 277004 kb
Host smart-73715e92-dc62-4155-9455-9e77c6b80a43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093703079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1093703079
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2689293317
Short name T499
Test name
Test status
Simulation time 409111403 ps
CPU time 11.16 seconds
Started May 19 01:02:48 PM PDT 24
Finished May 19 01:02:59 PM PDT 24
Peak memory 247520 kb
Host smart-dff8be58-1647-455e-96b5-b81eccb89cf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689293317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2689293317
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3208268812
Short name T604
Test name
Test status
Simulation time 75054837 ps
CPU time 3.03 seconds
Started May 19 01:02:48 PM PDT 24
Finished May 19 01:02:51 PM PDT 24
Peak memory 218016 kb
Host smart-cef922f9-aa36-4e55-a0ca-485f3586cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208268812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3208268812
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.599930854
Short name T87
Test name
Test status
Simulation time 205665217 ps
CPU time 23.85 seconds
Started May 19 01:02:53 PM PDT 24
Finished May 19 01:03:18 PM PDT 24
Peak memory 284092 kb
Host smart-cefcd2b6-9215-4851-985f-353330299157
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599930854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.599930854
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1510811405
Short name T622
Test name
Test status
Simulation time 566737339 ps
CPU time 16.56 seconds
Started May 19 01:02:48 PM PDT 24
Finished May 19 01:03:05 PM PDT 24
Peak memory 219000 kb
Host smart-44b9a01a-064f-42d7-86ed-dd2a72ee590c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510811405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1510811405
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1200258079
Short name T290
Test name
Test status
Simulation time 5266763878 ps
CPU time 9.36 seconds
Started May 19 01:02:48 PM PDT 24
Finished May 19 01:02:58 PM PDT 24
Peak memory 218128 kb
Host smart-02ee2a94-5727-4aad-8dc0-91a505866ea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200258079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1200258079
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2412909474
Short name T355
Test name
Test status
Simulation time 513776644 ps
CPU time 11.94 seconds
Started May 19 01:02:47 PM PDT 24
Finished May 19 01:02:59 PM PDT 24
Peak memory 217972 kb
Host smart-c774867a-8e4d-435f-8690-bc4587f720b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412909474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
412909474
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1848876478
Short name T572
Test name
Test status
Simulation time 1034264535 ps
CPU time 11.65 seconds
Started May 19 01:02:50 PM PDT 24
Finished May 19 01:03:03 PM PDT 24
Peak memory 218020 kb
Host smart-b45f5a54-ae07-44c5-9abf-4b4e25d5a6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848876478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1848876478
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.258761227
Short name T352
Test name
Test status
Simulation time 324945161 ps
CPU time 2.32 seconds
Started May 19 01:02:44 PM PDT 24
Finished May 19 01:02:47 PM PDT 24
Peak memory 222544 kb
Host smart-ce1770d1-100b-447c-941f-543ae9575e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258761227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.258761227
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3129621260
Short name T496
Test name
Test status
Simulation time 551410424 ps
CPU time 26.14 seconds
Started May 19 01:02:44 PM PDT 24
Finished May 19 01:03:10 PM PDT 24
Peak memory 250968 kb
Host smart-35ab8918-65ab-4132-ae0c-23d9206f8f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129621260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3129621260
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3558618151
Short name T727
Test name
Test status
Simulation time 347376449 ps
CPU time 7.99 seconds
Started May 19 01:02:43 PM PDT 24
Finished May 19 01:02:52 PM PDT 24
Peak memory 250960 kb
Host smart-0abc5ee6-7266-4d61-bc2d-2f82cdba847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558618151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3558618151
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2051958990
Short name T329
Test name
Test status
Simulation time 11549231889 ps
CPU time 76.83 seconds
Started May 19 01:02:53 PM PDT 24
Finished May 19 01:04:10 PM PDT 24
Peak memory 283296 kb
Host smart-a5854130-71d5-4d2f-b408-43a93d968306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051958990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2051958990
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2146837076
Short name T825
Test name
Test status
Simulation time 12754072 ps
CPU time 0.85 seconds
Started May 19 01:02:42 PM PDT 24
Finished May 19 01:02:43 PM PDT 24
Peak memory 208496 kb
Host smart-9cf72965-c1f6-41dc-9201-dc31bd5638bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146837076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2146837076
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1818639646
Short name T328
Test name
Test status
Simulation time 22406724 ps
CPU time 0.98 seconds
Started May 19 01:04:53 PM PDT 24
Finished May 19 01:04:54 PM PDT 24
Peak memory 209628 kb
Host smart-7d6eb070-0caa-4ee3-b9ec-90de9c5d7451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818639646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1818639646
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.736437025
Short name T655
Test name
Test status
Simulation time 2354131953 ps
CPU time 13.23 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:05:10 PM PDT 24
Peak memory 218132 kb
Host smart-fa27fe12-a578-4ccd-91d4-62c135d843f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736437025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.736437025
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1415509512
Short name T27
Test name
Test status
Simulation time 675843838 ps
CPU time 2.66 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:04:59 PM PDT 24
Peak memory 209516 kb
Host smart-f699e4c4-ddb6-404b-9998-e97063476ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415509512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1415509512
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1301732285
Short name T530
Test name
Test status
Simulation time 296672091 ps
CPU time 4.04 seconds
Started May 19 01:04:54 PM PDT 24
Finished May 19 01:04:59 PM PDT 24
Peak memory 218044 kb
Host smart-dc43cfc5-d267-4194-9501-a6ba034cb2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301732285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1301732285
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4097889236
Short name T54
Test name
Test status
Simulation time 1348513326 ps
CPU time 15.47 seconds
Started May 19 01:04:54 PM PDT 24
Finished May 19 01:05:10 PM PDT 24
Peak memory 218224 kb
Host smart-c7d4fb83-82a0-445c-b48d-492f31e54131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097889236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4097889236
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1296988194
Short name T739
Test name
Test status
Simulation time 635126284 ps
CPU time 8.6 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:05:05 PM PDT 24
Peak memory 218192 kb
Host smart-1a78c8d5-20ce-4435-8832-b0be3eac9f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296988194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1296988194
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1970026242
Short name T662
Test name
Test status
Simulation time 230077984 ps
CPU time 10.54 seconds
Started May 19 01:04:54 PM PDT 24
Finished May 19 01:05:06 PM PDT 24
Peak memory 218064 kb
Host smart-8abdb83d-ebb5-4ef5-8667-3e7befdb1c57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970026242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1970026242
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.981692519
Short name T742
Test name
Test status
Simulation time 1039406576 ps
CPU time 11.44 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:05:08 PM PDT 24
Peak memory 218176 kb
Host smart-10ba2974-28af-4fb4-9573-077cc65a2081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981692519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.981692519
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.981664846
Short name T268
Test name
Test status
Simulation time 48414427 ps
CPU time 1.3 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:04:58 PM PDT 24
Peak memory 213396 kb
Host smart-5a3851b0-7258-4f11-ba75-0d6052e1c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981664846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.981664846
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2046954443
Short name T744
Test name
Test status
Simulation time 464985090 ps
CPU time 25.02 seconds
Started May 19 01:04:53 PM PDT 24
Finished May 19 01:05:19 PM PDT 24
Peak memory 251244 kb
Host smart-bce6a0a1-cdc2-4cf6-861f-6392af5c6588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046954443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2046954443
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3566833387
Short name T730
Test name
Test status
Simulation time 49004747 ps
CPU time 6.31 seconds
Started May 19 01:04:58 PM PDT 24
Finished May 19 01:05:04 PM PDT 24
Peak memory 246996 kb
Host smart-e317cceb-4b18-4a9b-8ffb-83d51cb8d157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566833387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3566833387
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.919567640
Short name T91
Test name
Test status
Simulation time 159083509538 ps
CPU time 829.43 seconds
Started May 19 01:04:56 PM PDT 24
Finished May 19 01:18:47 PM PDT 24
Peak memory 422176 kb
Host smart-b0d07caa-8187-454c-ac45-953b1cb94d2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=919567640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.919567640
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3220502519
Short name T316
Test name
Test status
Simulation time 21353780 ps
CPU time 0.77 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:04:57 PM PDT 24
Peak memory 208728 kb
Host smart-cc258c76-d54f-447f-b1c7-cc03b5a8ff3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220502519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3220502519
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3945166559
Short name T274
Test name
Test status
Simulation time 26763481 ps
CPU time 1.3 seconds
Started May 19 01:04:59 PM PDT 24
Finished May 19 01:05:02 PM PDT 24
Peak memory 209616 kb
Host smart-f80dddce-3848-4da7-a028-8331662e2e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945166559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3945166559
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.977914206
Short name T625
Test name
Test status
Simulation time 1784034473 ps
CPU time 16.32 seconds
Started May 19 01:05:00 PM PDT 24
Finished May 19 01:05:17 PM PDT 24
Peak memory 218244 kb
Host smart-d3361d1e-4be4-4a76-a41b-32cbfbaa0a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977914206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.977914206
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.184280209
Short name T385
Test name
Test status
Simulation time 1776494114 ps
CPU time 7.47 seconds
Started May 19 01:04:59 PM PDT 24
Finished May 19 01:05:08 PM PDT 24
Peak memory 209620 kb
Host smart-f461c50f-fef6-4d61-8c19-93a1770ca38b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184280209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.184280209
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.643806629
Short name T469
Test name
Test status
Simulation time 410834765 ps
CPU time 3.62 seconds
Started May 19 01:05:00 PM PDT 24
Finished May 19 01:05:04 PM PDT 24
Peak memory 218052 kb
Host smart-fbe2c837-ee1b-44d6-880b-ad44d5ab7971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643806629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.643806629
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1711133425
Short name T52
Test name
Test status
Simulation time 2543780333 ps
CPU time 13.73 seconds
Started May 19 01:05:00 PM PDT 24
Finished May 19 01:05:15 PM PDT 24
Peak memory 226200 kb
Host smart-e5780d6f-03c9-46e3-a00a-c3e5a9cb9afa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711133425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1711133425
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3113141988
Short name T278
Test name
Test status
Simulation time 351221810 ps
CPU time 11.05 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:05:14 PM PDT 24
Peak memory 224764 kb
Host smart-2cd1da68-d665-41b2-bd66-a0e1e0e5579b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113141988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3113141988
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.768886399
Short name T281
Test name
Test status
Simulation time 1369807289 ps
CPU time 10.28 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:05:13 PM PDT 24
Peak memory 217960 kb
Host smart-4965bd9c-21be-4e4e-ba58-fe6b8945d3ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768886399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.768886399
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2226537343
Short name T610
Test name
Test status
Simulation time 1731538299 ps
CPU time 11.26 seconds
Started May 19 01:05:01 PM PDT 24
Finished May 19 01:05:13 PM PDT 24
Peak memory 218128 kb
Host smart-77a7e5d9-f855-472b-82cd-1fc40d1e75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226537343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2226537343
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4224494463
Short name T529
Test name
Test status
Simulation time 1482823774 ps
CPU time 6.76 seconds
Started May 19 01:04:54 PM PDT 24
Finished May 19 01:05:03 PM PDT 24
Peak memory 217844 kb
Host smart-4b3965fd-efb2-4d9f-86ac-3469f32949cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224494463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4224494463
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1139966945
Short name T465
Test name
Test status
Simulation time 329962768 ps
CPU time 28.07 seconds
Started May 19 01:04:54 PM PDT 24
Finished May 19 01:05:23 PM PDT 24
Peak memory 250984 kb
Host smart-b2c92c1c-6800-472c-a2a1-551b9e3c98a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139966945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1139966945
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1086146510
Short name T12
Test name
Test status
Simulation time 565056030 ps
CPU time 12.09 seconds
Started May 19 01:05:00 PM PDT 24
Finished May 19 01:05:13 PM PDT 24
Peak memory 250940 kb
Host smart-319dac7a-ef0e-4581-8ef9-190ed9cd215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086146510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1086146510
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2055054214
Short name T828
Test name
Test status
Simulation time 122085429292 ps
CPU time 297.37 seconds
Started May 19 01:05:00 PM PDT 24
Finished May 19 01:09:59 PM PDT 24
Peak memory 219820 kb
Host smart-076c91c8-28b0-4996-8326-f0ab7865c0a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055054214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2055054214
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.482713321
Short name T48
Test name
Test status
Simulation time 13254113 ps
CPU time 0.77 seconds
Started May 19 01:04:55 PM PDT 24
Finished May 19 01:04:57 PM PDT 24
Peak memory 208508 kb
Host smart-7f991904-01ce-49be-a9cf-94b702ba2433
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482713321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.482713321
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2598395334
Short name T101
Test name
Test status
Simulation time 68653484 ps
CPU time 0.92 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:07 PM PDT 24
Peak memory 209584 kb
Host smart-693a363e-3c53-4061-9e4d-2d117ec2e865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598395334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2598395334
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3054362742
Short name T808
Test name
Test status
Simulation time 554985048 ps
CPU time 23.3 seconds
Started May 19 01:04:59 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 218044 kb
Host smart-fecc0626-9a7a-4fd5-b786-1bc20a310cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054362742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3054362742
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3080254679
Short name T523
Test name
Test status
Simulation time 595633991 ps
CPU time 4.02 seconds
Started May 19 01:04:58 PM PDT 24
Finished May 19 01:05:03 PM PDT 24
Peak memory 209548 kb
Host smart-d9018513-7c78-4310-90b1-d543984630bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080254679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3080254679
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3764069144
Short name T740
Test name
Test status
Simulation time 429257511 ps
CPU time 2.17 seconds
Started May 19 01:04:59 PM PDT 24
Finished May 19 01:05:03 PM PDT 24
Peak memory 218108 kb
Host smart-663002d1-e918-4d0f-9beb-35b3f2de79f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764069144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3764069144
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2344988577
Short name T444
Test name
Test status
Simulation time 451235698 ps
CPU time 12.53 seconds
Started May 19 01:04:58 PM PDT 24
Finished May 19 01:05:12 PM PDT 24
Peak memory 226112 kb
Host smart-ae7001ec-f34c-4334-9144-b8b86d1dcb5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344988577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2344988577
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4094444475
Short name T535
Test name
Test status
Simulation time 374390359 ps
CPU time 10.13 seconds
Started May 19 01:05:02 PM PDT 24
Finished May 19 01:05:13 PM PDT 24
Peak memory 218048 kb
Host smart-58fa85aa-a0dc-4f09-906b-90f85fdacf6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094444475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4094444475
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1000306911
Short name T759
Test name
Test status
Simulation time 1129458090 ps
CPU time 6.37 seconds
Started May 19 01:04:59 PM PDT 24
Finished May 19 01:05:07 PM PDT 24
Peak memory 218004 kb
Host smart-1e0f15af-f417-413e-a311-8b467688d788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000306911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1000306911
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3726549680
Short name T867
Test name
Test status
Simulation time 1860384131 ps
CPU time 15.01 seconds
Started May 19 01:05:01 PM PDT 24
Finished May 19 01:05:17 PM PDT 24
Peak memory 218064 kb
Host smart-41d1d73d-5c80-4c3a-82b5-9bb8b1e19727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726549680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3726549680
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.769498854
Short name T453
Test name
Test status
Simulation time 89958603 ps
CPU time 1.57 seconds
Started May 19 01:05:00 PM PDT 24
Finished May 19 01:05:03 PM PDT 24
Peak memory 213584 kb
Host smart-fc486c57-7db5-4380-86c8-7406da85b2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769498854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.769498854
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.542945516
Short name T798
Test name
Test status
Simulation time 4981144486 ps
CPU time 30.49 seconds
Started May 19 01:05:00 PM PDT 24
Finished May 19 01:05:32 PM PDT 24
Peak memory 251040 kb
Host smart-63e17cbd-7c80-4ad4-bc7f-7d2aeabd0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542945516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.542945516
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1802443165
Short name T251
Test name
Test status
Simulation time 103558890 ps
CPU time 7.75 seconds
Started May 19 01:04:59 PM PDT 24
Finished May 19 01:05:08 PM PDT 24
Peak memory 250988 kb
Host smart-9bb631be-914d-4766-af1d-a722b82a9e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802443165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1802443165
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2696128835
Short name T455
Test name
Test status
Simulation time 14213352 ps
CPU time 0.8 seconds
Started May 19 01:04:59 PM PDT 24
Finished May 19 01:05:01 PM PDT 24
Peak memory 208928 kb
Host smart-5dfe04c1-e2b6-465d-b12c-d448c97078f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696128835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2696128835
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2049332885
Short name T538
Test name
Test status
Simulation time 26495392 ps
CPU time 1.35 seconds
Started May 19 01:05:06 PM PDT 24
Finished May 19 01:05:09 PM PDT 24
Peak memory 209628 kb
Host smart-69037344-b663-4269-894a-f3e29c65d6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049332885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2049332885
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3466320524
Short name T10
Test name
Test status
Simulation time 409474772 ps
CPU time 13.08 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:19 PM PDT 24
Peak memory 217992 kb
Host smart-5a338fe9-f868-4d40-be6f-ff5d8894546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466320524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3466320524
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1101806923
Short name T693
Test name
Test status
Simulation time 72409485 ps
CPU time 1.59 seconds
Started May 19 01:05:06 PM PDT 24
Finished May 19 01:05:09 PM PDT 24
Peak memory 209536 kb
Host smart-8d193923-0058-42ec-9ff3-b1c4ee9ad5f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101806923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1101806923
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2803330069
Short name T161
Test name
Test status
Simulation time 135852842 ps
CPU time 3.72 seconds
Started May 19 01:05:09 PM PDT 24
Finished May 19 01:05:14 PM PDT 24
Peak memory 218116 kb
Host smart-ab93111f-8bc7-45c6-94fe-350a1535843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803330069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2803330069
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3436865009
Short name T286
Test name
Test status
Simulation time 1492584285 ps
CPU time 16.37 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:23 PM PDT 24
Peak memory 218952 kb
Host smart-cc56cd24-b58a-4ca2-80af-19a791b4451c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436865009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3436865009
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2382769423
Short name T495
Test name
Test status
Simulation time 1773385995 ps
CPU time 11.49 seconds
Started May 19 01:05:04 PM PDT 24
Finished May 19 01:05:16 PM PDT 24
Peak memory 217936 kb
Host smart-952a934d-e6e3-4d90-a3cb-5ccdcd4d8f9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382769423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2382769423
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1350284062
Short name T192
Test name
Test status
Simulation time 1025147884 ps
CPU time 9.88 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:16 PM PDT 24
Peak memory 217996 kb
Host smart-e752931d-f678-4dfd-a4e8-d6d8dfcddbb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350284062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1350284062
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1994472574
Short name T399
Test name
Test status
Simulation time 1214818736 ps
CPU time 12.41 seconds
Started May 19 01:05:06 PM PDT 24
Finished May 19 01:05:20 PM PDT 24
Peak memory 218124 kb
Host smart-a71135c9-e633-407b-9786-ccb2571d9430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994472574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1994472574
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2586879327
Short name T395
Test name
Test status
Simulation time 35706510 ps
CPU time 1.74 seconds
Started May 19 01:05:06 PM PDT 24
Finished May 19 01:05:09 PM PDT 24
Peak memory 213420 kb
Host smart-7165221e-5687-4713-84b3-7d1eb3976f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586879327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2586879327
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3632753282
Short name T424
Test name
Test status
Simulation time 1694202321 ps
CPU time 23.06 seconds
Started May 19 01:05:04 PM PDT 24
Finished May 19 01:05:29 PM PDT 24
Peak memory 250888 kb
Host smart-e5bd3e07-273f-4323-a274-ca77eeb4c6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632753282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3632753282
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3489563675
Short name T443
Test name
Test status
Simulation time 167493999 ps
CPU time 4.71 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:11 PM PDT 24
Peak memory 222772 kb
Host smart-57774784-8077-4c4f-8e44-1e3ea3cfbc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489563675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3489563675
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3904559038
Short name T717
Test name
Test status
Simulation time 7641170786 ps
CPU time 90.27 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 269644 kb
Host smart-96ccfcea-5a67-4a48-b6be-ab27f16a9e8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904559038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3904559038
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.260242218
Short name T144
Test name
Test status
Simulation time 35719799456 ps
CPU time 702.8 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:16:49 PM PDT 24
Peak memory 267660 kb
Host smart-fd6b5e02-1889-4bff-bea3-8b68d9749a43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=260242218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.260242218
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2945634648
Short name T310
Test name
Test status
Simulation time 44297958 ps
CPU time 0.79 seconds
Started May 19 01:05:04 PM PDT 24
Finished May 19 01:05:07 PM PDT 24
Peak memory 208636 kb
Host smart-3861a39c-f99c-46af-a851-8125dd479c9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945634648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2945634648
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.415775616
Short name T165
Test name
Test status
Simulation time 78524026 ps
CPU time 1.29 seconds
Started May 19 01:05:14 PM PDT 24
Finished May 19 01:05:16 PM PDT 24
Peak memory 209608 kb
Host smart-fd43ac35-6fd9-4e7c-b1f7-eb2c07913984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415775616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.415775616
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.195006379
Short name T829
Test name
Test status
Simulation time 859517886 ps
CPU time 12.83 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:19 PM PDT 24
Peak memory 218108 kb
Host smart-6259aded-1a05-43b0-9073-6ec5d5e9cbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195006379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.195006379
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1440380302
Short name T589
Test name
Test status
Simulation time 386117987 ps
CPU time 4.38 seconds
Started May 19 01:05:09 PM PDT 24
Finished May 19 01:05:14 PM PDT 24
Peak memory 216960 kb
Host smart-da3babbf-f823-4823-ae72-3c66518cabe1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440380302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1440380302
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3722855543
Short name T602
Test name
Test status
Simulation time 330996446 ps
CPU time 2.77 seconds
Started May 19 01:05:08 PM PDT 24
Finished May 19 01:05:12 PM PDT 24
Peak memory 218008 kb
Host smart-00c91f96-f765-481b-b067-2b3f68a24f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722855543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3722855543
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.107195257
Short name T66
Test name
Test status
Simulation time 413583560 ps
CPU time 12.09 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:18 PM PDT 24
Peak memory 218164 kb
Host smart-8499c536-fdf6-44cd-a4d0-c6e5a585fbaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107195257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.107195257
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.119128439
Short name T271
Test name
Test status
Simulation time 1111320888 ps
CPU time 13.3 seconds
Started May 19 01:05:13 PM PDT 24
Finished May 19 01:05:27 PM PDT 24
Peak memory 217944 kb
Host smart-9a9d9f02-bab2-49cb-abf1-4fc83a363798
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119128439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.119128439
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.4177926285
Short name T854
Test name
Test status
Simulation time 5950667836 ps
CPU time 8.94 seconds
Started May 19 01:05:08 PM PDT 24
Finished May 19 01:05:18 PM PDT 24
Peak memory 218096 kb
Host smart-f2d081bb-11f0-4187-a10d-1fbadb75fdce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177926285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
4177926285
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2633287655
Short name T311
Test name
Test status
Simulation time 958080253 ps
CPU time 9.46 seconds
Started May 19 01:05:09 PM PDT 24
Finished May 19 01:05:20 PM PDT 24
Peak memory 218084 kb
Host smart-a5190250-b816-41f0-b5d2-05475973d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633287655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2633287655
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.810188870
Short name T63
Test name
Test status
Simulation time 289688331 ps
CPU time 3.8 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:10 PM PDT 24
Peak memory 214780 kb
Host smart-8680d99c-8721-4681-84a2-d2e9292fa342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810188870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.810188870
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4004675023
Short name T186
Test name
Test status
Simulation time 615842151 ps
CPU time 18.05 seconds
Started May 19 01:05:04 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 250896 kb
Host smart-db552402-6d7d-4fb2-b42a-5bf12cf3ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004675023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4004675023
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3273101066
Short name T708
Test name
Test status
Simulation time 76754389 ps
CPU time 3.24 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:10 PM PDT 24
Peak memory 226352 kb
Host smart-43271e97-6039-43b6-87c7-03d732a38fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273101066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3273101066
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3806913559
Short name T475
Test name
Test status
Simulation time 19741716640 ps
CPU time 195.77 seconds
Started May 19 01:05:13 PM PDT 24
Finished May 19 01:08:30 PM PDT 24
Peak memory 251348 kb
Host smart-fe096a43-c890-46fb-ac6c-add4dab14470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806913559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3806913559
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.499843857
Short name T576
Test name
Test status
Simulation time 36689877 ps
CPU time 1 seconds
Started May 19 01:05:05 PM PDT 24
Finished May 19 01:05:08 PM PDT 24
Peak memory 211604 kb
Host smart-2cbb622e-07fb-42b9-afe0-10c68aa6ff9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499843857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.499843857
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3448456295
Short name T277
Test name
Test status
Simulation time 29130210 ps
CPU time 1.36 seconds
Started May 19 01:05:21 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 209636 kb
Host smart-3dac8156-34c7-459a-b790-cfcfe5945c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448456295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3448456295
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1167774776
Short name T774
Test name
Test status
Simulation time 452244728 ps
CPU time 11.11 seconds
Started May 19 01:05:13 PM PDT 24
Finished May 19 01:05:25 PM PDT 24
Peak memory 218008 kb
Host smart-486b3f5a-86d2-4744-a747-e7ba457d2146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167774776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1167774776
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1304359687
Short name T691
Test name
Test status
Simulation time 37455289 ps
CPU time 1.26 seconds
Started May 19 01:05:12 PM PDT 24
Finished May 19 01:05:15 PM PDT 24
Peak memory 209600 kb
Host smart-59abfeda-325e-4125-804a-10f6842a1fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304359687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1304359687
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2609930913
Short name T751
Test name
Test status
Simulation time 71052375 ps
CPU time 1.83 seconds
Started May 19 01:05:11 PM PDT 24
Finished May 19 01:05:13 PM PDT 24
Peak memory 218080 kb
Host smart-b0b1e0d5-79e0-46ce-bd39-825eba8c294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609930913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2609930913
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2341375548
Short name T785
Test name
Test status
Simulation time 328492387 ps
CPU time 9.31 seconds
Started May 19 01:05:14 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 218980 kb
Host smart-6fcc674c-2b37-43a9-83a9-a3a72f0577c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341375548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2341375548
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.4157069359
Short name T866
Test name
Test status
Simulation time 534703106 ps
CPU time 19.17 seconds
Started May 19 01:05:13 PM PDT 24
Finished May 19 01:05:33 PM PDT 24
Peak memory 218040 kb
Host smart-d4dd6141-6b40-4e5b-9c1c-3f88761d405a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157069359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.4157069359
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2105212237
Short name T698
Test name
Test status
Simulation time 380759040 ps
CPU time 8.59 seconds
Started May 19 01:05:11 PM PDT 24
Finished May 19 01:05:20 PM PDT 24
Peak memory 217968 kb
Host smart-57b6c7cf-4d13-41ef-8b6a-a605f2f09341
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105212237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2105212237
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2301236953
Short name T540
Test name
Test status
Simulation time 235282406 ps
CPU time 9.25 seconds
Started May 19 01:05:11 PM PDT 24
Finished May 19 01:05:21 PM PDT 24
Peak memory 218028 kb
Host smart-c6326ce7-6949-4436-a87b-b39333fa1342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301236953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2301236953
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3005582661
Short name T307
Test name
Test status
Simulation time 35387953 ps
CPU time 2.22 seconds
Started May 19 01:05:13 PM PDT 24
Finished May 19 01:05:16 PM PDT 24
Peak memory 214064 kb
Host smart-2cd579c2-f949-4b17-a438-f29e60203efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005582661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3005582661
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3169878960
Short name T816
Test name
Test status
Simulation time 252257032 ps
CPU time 21.27 seconds
Started May 19 01:05:12 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 250952 kb
Host smart-f55d3302-4bcb-405f-bfa6-6ddfbdfa36cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169878960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3169878960
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3020063589
Short name T224
Test name
Test status
Simulation time 119138142 ps
CPU time 9.64 seconds
Started May 19 01:05:14 PM PDT 24
Finished May 19 01:05:25 PM PDT 24
Peak memory 250928 kb
Host smart-df8f869c-996a-4cd9-a778-8e20a86d2dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020063589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3020063589
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.877127464
Short name T17
Test name
Test status
Simulation time 1808474239 ps
CPU time 31.09 seconds
Started May 19 01:05:13 PM PDT 24
Finished May 19 01:05:45 PM PDT 24
Peak memory 250856 kb
Host smart-9edb087c-9e00-4d2d-a5c5-690f890fde76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877127464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.877127464
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2630249706
Short name T486
Test name
Test status
Simulation time 24049574 ps
CPU time 1.05 seconds
Started May 19 01:05:15 PM PDT 24
Finished May 19 01:05:17 PM PDT 24
Peak memory 212728 kb
Host smart-9ae7c48d-1b4d-4bf1-83e0-979927507573
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630249706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2630249706
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4039103365
Short name T586
Test name
Test status
Simulation time 63261360 ps
CPU time 0.96 seconds
Started May 19 01:05:15 PM PDT 24
Finished May 19 01:05:18 PM PDT 24
Peak memory 209532 kb
Host smart-40fce10b-6a86-456c-9821-1a6c7665bf82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039103365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4039103365
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3799913954
Short name T594
Test name
Test status
Simulation time 225998153 ps
CPU time 8.82 seconds
Started May 19 01:05:17 PM PDT 24
Finished May 19 01:05:27 PM PDT 24
Peak memory 217964 kb
Host smart-c80e0310-acfc-4cbd-bc79-901f29236115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799913954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3799913954
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3805419176
Short name T22
Test name
Test status
Simulation time 1107882738 ps
CPU time 4.13 seconds
Started May 19 01:05:21 PM PDT 24
Finished May 19 01:05:26 PM PDT 24
Peak memory 209572 kb
Host smart-999536c3-2742-4849-a712-f4cfbdd14dc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805419176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3805419176
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2174902020
Short name T652
Test name
Test status
Simulation time 76827266 ps
CPU time 3.05 seconds
Started May 19 01:05:15 PM PDT 24
Finished May 19 01:05:20 PM PDT 24
Peak memory 218056 kb
Host smart-9f989553-67aa-4d36-91fd-ab09ee3e8650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174902020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2174902020
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.4086664943
Short name T634
Test name
Test status
Simulation time 311352052 ps
CPU time 15.51 seconds
Started May 19 01:05:15 PM PDT 24
Finished May 19 01:05:32 PM PDT 24
Peak memory 219008 kb
Host smart-b84ddc82-ca31-4938-890e-ddbcab22530f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086664943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4086664943
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.513384755
Short name T436
Test name
Test status
Simulation time 2010127741 ps
CPU time 12.59 seconds
Started May 19 01:05:17 PM PDT 24
Finished May 19 01:05:31 PM PDT 24
Peak memory 218024 kb
Host smart-76ef2c31-c13a-4363-a495-bc2853df2835
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513384755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.513384755
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3551276110
Short name T651
Test name
Test status
Simulation time 332613206 ps
CPU time 8.94 seconds
Started May 19 01:05:16 PM PDT 24
Finished May 19 01:05:27 PM PDT 24
Peak memory 217992 kb
Host smart-0d96e036-783c-458c-9e2d-50d3afa9b051
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551276110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3551276110
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2696975252
Short name T673
Test name
Test status
Simulation time 463287902 ps
CPU time 15.91 seconds
Started May 19 01:05:16 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 218060 kb
Host smart-75f068c7-6973-4c77-ad57-6745f3818532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696975252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2696975252
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.921338157
Short name T608
Test name
Test status
Simulation time 23833078 ps
CPU time 1.72 seconds
Started May 19 01:05:15 PM PDT 24
Finished May 19 01:05:18 PM PDT 24
Peak memory 213668 kb
Host smart-3415661a-1e10-4464-b252-b1a44d32715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921338157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.921338157
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1943274978
Short name T531
Test name
Test status
Simulation time 823326681 ps
CPU time 21.24 seconds
Started May 19 01:05:20 PM PDT 24
Finished May 19 01:05:42 PM PDT 24
Peak memory 247280 kb
Host smart-c1bd6b0f-e97c-471f-b13d-f6e73af44f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943274978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1943274978
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.554420531
Short name T228
Test name
Test status
Simulation time 318218975 ps
CPU time 4.17 seconds
Started May 19 01:05:18 PM PDT 24
Finished May 19 01:05:23 PM PDT 24
Peak memory 222348 kb
Host smart-76795807-b69f-465a-a32b-fb0ae6a23fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554420531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.554420531
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2115795475
Short name T409
Test name
Test status
Simulation time 22525528971 ps
CPU time 23.06 seconds
Started May 19 01:05:15 PM PDT 24
Finished May 19 01:05:40 PM PDT 24
Peak memory 243244 kb
Host smart-04bb9913-e961-4c4a-acec-b709ca124094
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115795475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2115795475
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2438200867
Short name T41
Test name
Test status
Simulation time 15003628 ps
CPU time 0.98 seconds
Started May 19 01:05:16 PM PDT 24
Finished May 19 01:05:18 PM PDT 24
Peak memory 208572 kb
Host smart-8b522d77-ee71-49b9-b013-345dcc859936
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438200867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2438200867
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.128104173
Short name T305
Test name
Test status
Simulation time 66965598 ps
CPU time 0.9 seconds
Started May 19 01:05:23 PM PDT 24
Finished May 19 01:05:25 PM PDT 24
Peak memory 209892 kb
Host smart-368f8395-fe71-44eb-bb34-1ae4f1f0e45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128104173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.128104173
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1869171670
Short name T541
Test name
Test status
Simulation time 1241332638 ps
CPU time 9.13 seconds
Started May 19 01:05:17 PM PDT 24
Finished May 19 01:05:27 PM PDT 24
Peak memory 218004 kb
Host smart-f904331b-7e20-4f2f-962e-31609ce6af08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869171670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1869171670
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.281047247
Short name T699
Test name
Test status
Simulation time 308468866 ps
CPU time 5.73 seconds
Started May 19 01:05:24 PM PDT 24
Finished May 19 01:05:31 PM PDT 24
Peak memory 209680 kb
Host smart-8f92d88b-d301-4cf2-a06f-ffff25d439f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281047247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.281047247
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2868977847
Short name T452
Test name
Test status
Simulation time 143283151 ps
CPU time 5.68 seconds
Started May 19 01:05:16 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 218028 kb
Host smart-1889ad02-e2f3-4ae6-9f17-d15d021bea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868977847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2868977847
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.205398245
Short name T633
Test name
Test status
Simulation time 2447472196 ps
CPU time 9.89 seconds
Started May 19 01:05:22 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 218072 kb
Host smart-6e4e20dc-77cb-4583-94ba-57baf45d6f1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205398245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.205398245
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.719982996
Short name T619
Test name
Test status
Simulation time 2588474082 ps
CPU time 14.94 seconds
Started May 19 01:05:21 PM PDT 24
Finished May 19 01:05:38 PM PDT 24
Peak memory 218056 kb
Host smart-79150f78-3d60-40a7-bb76-f7fcadf58aaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719982996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.719982996
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.75117806
Short name T783
Test name
Test status
Simulation time 576345145 ps
CPU time 10.81 seconds
Started May 19 01:05:24 PM PDT 24
Finished May 19 01:05:36 PM PDT 24
Peak memory 218004 kb
Host smart-16e5ceec-8e97-4e13-a00a-40e567a2c5e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75117806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.75117806
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4168258358
Short name T59
Test name
Test status
Simulation time 503279659 ps
CPU time 17.62 seconds
Started May 19 01:05:24 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 218172 kb
Host smart-8027fcec-bf0e-4e3d-9ae5-bc1910e48531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168258358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4168258358
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3151424404
Short name T681
Test name
Test status
Simulation time 539507658 ps
CPU time 2.6 seconds
Started May 19 01:05:17 PM PDT 24
Finished May 19 01:05:21 PM PDT 24
Peak memory 213612 kb
Host smart-41449a5a-0612-4470-91eb-cf77fe19bd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151424404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3151424404
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1346060635
Short name T638
Test name
Test status
Simulation time 289431359 ps
CPU time 25.72 seconds
Started May 19 01:05:16 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 250972 kb
Host smart-1d290279-072f-498e-8245-3394cbfbbca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346060635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1346060635
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3482128487
Short name T700
Test name
Test status
Simulation time 466740662 ps
CPU time 6.32 seconds
Started May 19 01:05:17 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 246584 kb
Host smart-e8e72649-7827-4200-afbf-5b30ff242eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482128487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3482128487
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2234851221
Short name T181
Test name
Test status
Simulation time 2870714542 ps
CPU time 52 seconds
Started May 19 01:05:22 PM PDT 24
Finished May 19 01:06:15 PM PDT 24
Peak memory 250592 kb
Host smart-66d4b87e-8291-4419-97ab-333182cd4ead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234851221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2234851221
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3827871059
Short name T107
Test name
Test status
Simulation time 19564295184 ps
CPU time 283.68 seconds
Started May 19 01:05:24 PM PDT 24
Finished May 19 01:10:10 PM PDT 24
Peak memory 283920 kb
Host smart-bc693d1c-94aa-4acc-b49e-a54d726ef140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3827871059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3827871059
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2697099216
Short name T335
Test name
Test status
Simulation time 15409012 ps
CPU time 1.17 seconds
Started May 19 01:05:16 PM PDT 24
Finished May 19 01:05:18 PM PDT 24
Peak memory 211588 kb
Host smart-78dcaeeb-0cd3-4778-a9ec-30f1159a20f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697099216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2697099216
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2919492804
Short name T836
Test name
Test status
Simulation time 19681790 ps
CPU time 1.1 seconds
Started May 19 01:05:29 PM PDT 24
Finished May 19 01:05:31 PM PDT 24
Peak memory 209604 kb
Host smart-f282f9bd-9141-4443-88c8-55d29c64096b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919492804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2919492804
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1380615671
Short name T42
Test name
Test status
Simulation time 248487862 ps
CPU time 12.11 seconds
Started May 19 01:05:21 PM PDT 24
Finished May 19 01:05:35 PM PDT 24
Peak memory 217964 kb
Host smart-059046fd-25b7-48f5-a962-4d2efda69a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380615671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1380615671
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3860021859
Short name T580
Test name
Test status
Simulation time 131931992 ps
CPU time 2.24 seconds
Started May 19 01:05:22 PM PDT 24
Finished May 19 01:05:26 PM PDT 24
Peak memory 209584 kb
Host smart-c33a126a-4f4d-4cfa-bc5d-8052a76023b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860021859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3860021859
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.4268916181
Short name T463
Test name
Test status
Simulation time 80910167 ps
CPU time 3.65 seconds
Started May 19 01:05:21 PM PDT 24
Finished May 19 01:05:26 PM PDT 24
Peak memory 218352 kb
Host smart-d3250b10-38b5-4281-8760-e35dc2d912ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268916181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.4268916181
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3085449734
Short name T492
Test name
Test status
Simulation time 724715722 ps
CPU time 16.47 seconds
Started May 19 01:05:22 PM PDT 24
Finished May 19 01:05:40 PM PDT 24
Peak memory 226152 kb
Host smart-03d3eda0-aaa9-4273-9525-457ad6358583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085449734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3085449734
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2279288458
Short name T177
Test name
Test status
Simulation time 533522306 ps
CPU time 9.75 seconds
Started May 19 01:05:25 PM PDT 24
Finished May 19 01:05:36 PM PDT 24
Peak memory 218008 kb
Host smart-abc51183-8a48-4afd-a2e4-b847383faac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279288458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2279288458
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2107124915
Short name T510
Test name
Test status
Simulation time 541351283 ps
CPU time 11.48 seconds
Started May 19 01:05:23 PM PDT 24
Finished May 19 01:05:36 PM PDT 24
Peak memory 218264 kb
Host smart-9cb6b4f3-ae96-4404-b198-b031f2f5765d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107124915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2107124915
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1248261813
Short name T521
Test name
Test status
Simulation time 839754534 ps
CPU time 7.79 seconds
Started May 19 01:05:24 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 218100 kb
Host smart-712bcf3e-b725-4723-9958-c16dd36108ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248261813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1248261813
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2886285280
Short name T81
Test name
Test status
Simulation time 19965808 ps
CPU time 1.33 seconds
Started May 19 01:05:22 PM PDT 24
Finished May 19 01:05:24 PM PDT 24
Peak memory 213328 kb
Host smart-904c92a7-1c6c-4f3f-aa87-5bd3ac666ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886285280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2886285280
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2771225203
Short name T225
Test name
Test status
Simulation time 454790533 ps
CPU time 30.86 seconds
Started May 19 01:05:23 PM PDT 24
Finished May 19 01:05:56 PM PDT 24
Peak memory 250916 kb
Host smart-66e4ab02-d893-42f1-8280-2399a3f5b077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771225203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2771225203
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1222410076
Short name T584
Test name
Test status
Simulation time 200777246 ps
CPU time 6.42 seconds
Started May 19 01:05:23 PM PDT 24
Finished May 19 01:05:32 PM PDT 24
Peak memory 246872 kb
Host smart-f3a91241-d3a6-4c8c-9c4f-9a629e7cb020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222410076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1222410076
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3984629766
Short name T850
Test name
Test status
Simulation time 24551084199 ps
CPU time 140.2 seconds
Started May 19 01:05:22 PM PDT 24
Finished May 19 01:07:43 PM PDT 24
Peak memory 267992 kb
Host smart-d329b243-2230-4a06-aac0-18f5129c8899
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984629766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3984629766
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1329532615
Short name T47
Test name
Test status
Simulation time 41174136 ps
CPU time 0.89 seconds
Started May 19 01:05:22 PM PDT 24
Finished May 19 01:05:25 PM PDT 24
Peak memory 208536 kb
Host smart-78e4efd0-04f6-4dbe-8a4c-be806a28bcae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329532615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1329532615
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.226637935
Short name T679
Test name
Test status
Simulation time 28901984 ps
CPU time 0.92 seconds
Started May 19 01:05:28 PM PDT 24
Finished May 19 01:05:31 PM PDT 24
Peak memory 209576 kb
Host smart-db568167-4174-4969-81b9-bf63355681fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226637935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.226637935
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2432978245
Short name T611
Test name
Test status
Simulation time 353874517 ps
CPU time 16.78 seconds
Started May 19 01:05:29 PM PDT 24
Finished May 19 01:05:47 PM PDT 24
Peak memory 218036 kb
Host smart-43a9adcf-57f5-4b72-a032-d4bc0b75ba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432978245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2432978245
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2985647023
Short name T28
Test name
Test status
Simulation time 368303920 ps
CPU time 4.73 seconds
Started May 19 01:05:26 PM PDT 24
Finished May 19 01:05:33 PM PDT 24
Peak memory 209528 kb
Host smart-b1e0e3ae-f56e-4004-b9c7-5c4a5a3678d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985647023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2985647023
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.904580025
Short name T227
Test name
Test status
Simulation time 414435397 ps
CPU time 4.1 seconds
Started May 19 01:05:28 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 218080 kb
Host smart-a00fa85e-093f-451f-a36d-2df82630cfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904580025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.904580025
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2887177396
Short name T358
Test name
Test status
Simulation time 3157408690 ps
CPU time 15.65 seconds
Started May 19 01:05:27 PM PDT 24
Finished May 19 01:05:45 PM PDT 24
Peak memory 219332 kb
Host smart-8b6a1b9d-a3df-4c45-a041-48f9f0962b16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887177396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2887177396
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2951285006
Short name T259
Test name
Test status
Simulation time 6425376566 ps
CPU time 11.87 seconds
Started May 19 01:05:30 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 218132 kb
Host smart-ba799a2e-049b-4848-a4aa-6678f545fb77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951285006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2951285006
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2761337558
Short name T553
Test name
Test status
Simulation time 1543181282 ps
CPU time 9.11 seconds
Started May 19 01:05:27 PM PDT 24
Finished May 19 01:05:38 PM PDT 24
Peak memory 218088 kb
Host smart-6feba0f5-46a4-4432-929f-f2f2d1de9c1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761337558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2761337558
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1297899365
Short name T857
Test name
Test status
Simulation time 572065435 ps
CPU time 10.62 seconds
Started May 19 01:05:27 PM PDT 24
Finished May 19 01:05:39 PM PDT 24
Peak memory 218104 kb
Host smart-abcdcbff-0717-4810-83db-8e08964c7167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297899365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1297899365
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.139825061
Short name T737
Test name
Test status
Simulation time 23324667 ps
CPU time 1.52 seconds
Started May 19 01:05:27 PM PDT 24
Finished May 19 01:05:30 PM PDT 24
Peak memory 217716 kb
Host smart-e1b2212b-9294-4351-847f-59475b204c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139825061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.139825061
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3949824013
Short name T501
Test name
Test status
Simulation time 178890594 ps
CPU time 16.19 seconds
Started May 19 01:05:29 PM PDT 24
Finished May 19 01:05:47 PM PDT 24
Peak memory 250960 kb
Host smart-d823e731-e98d-4af7-a84b-ac9d64be2de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949824013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3949824013
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2386114448
Short name T223
Test name
Test status
Simulation time 66078439 ps
CPU time 7.25 seconds
Started May 19 01:05:30 PM PDT 24
Finished May 19 01:05:38 PM PDT 24
Peak memory 243192 kb
Host smart-3c60292f-5bde-4d9a-b9bc-72ac986dcb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386114448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2386114448
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2459161798
Short name T548
Test name
Test status
Simulation time 3241460613 ps
CPU time 77.37 seconds
Started May 19 01:05:28 PM PDT 24
Finished May 19 01:06:47 PM PDT 24
Peak memory 267640 kb
Host smart-899908b1-1283-4e43-b91c-bf9a88b2c2b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459161798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2459161798
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4279961318
Short name T163
Test name
Test status
Simulation time 39179744 ps
CPU time 0.76 seconds
Started May 19 01:05:28 PM PDT 24
Finished May 19 01:05:30 PM PDT 24
Peak memory 208432 kb
Host smart-ba382eaa-3672-4fa6-9491-d64e6d9cd88d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279961318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4279961318
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3536234215
Short name T648
Test name
Test status
Simulation time 22721952 ps
CPU time 1.24 seconds
Started May 19 01:03:10 PM PDT 24
Finished May 19 01:03:11 PM PDT 24
Peak memory 209588 kb
Host smart-58600ea0-cbcd-4a27-97c3-e9df57285e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536234215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3536234215
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.4023873934
Short name T30
Test name
Test status
Simulation time 788638862 ps
CPU time 16.72 seconds
Started May 19 01:03:00 PM PDT 24
Finished May 19 01:03:18 PM PDT 24
Peak memory 218244 kb
Host smart-3296a078-c2a1-479b-9628-979267400a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023873934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.4023873934
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1204045033
Short name T23
Test name
Test status
Simulation time 6892047498 ps
CPU time 6.76 seconds
Started May 19 01:03:00 PM PDT 24
Finished May 19 01:03:07 PM PDT 24
Peak memory 209600 kb
Host smart-9478b2a6-1245-40b3-98b0-10dfe8bede9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204045033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1204045033
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2950435183
Short name T36
Test name
Test status
Simulation time 4520261415 ps
CPU time 19.74 seconds
Started May 19 01:03:00 PM PDT 24
Finished May 19 01:03:21 PM PDT 24
Peak memory 218332 kb
Host smart-855247d1-02c2-47e6-9c04-501008ebb45d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950435183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2950435183
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.146163985
Short name T856
Test name
Test status
Simulation time 257753763 ps
CPU time 7.05 seconds
Started May 19 01:03:07 PM PDT 24
Finished May 19 01:03:14 PM PDT 24
Peak memory 217792 kb
Host smart-8c19a9c0-02dd-4537-aa51-a77460ce9010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146163985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.146163985
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3796642708
Short name T16
Test name
Test status
Simulation time 889635403 ps
CPU time 5.14 seconds
Started May 19 01:03:29 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 217968 kb
Host smart-32b99cf3-3f9c-42c5-aa16-ca7e747ecdff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796642708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3796642708
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3261779277
Short name T13
Test name
Test status
Simulation time 666879356 ps
CPU time 10 seconds
Started May 19 01:03:06 PM PDT 24
Finished May 19 01:03:17 PM PDT 24
Peak memory 213060 kb
Host smart-c506fafa-5fe3-4367-b5d0-8b7e1c697e6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261779277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3261779277
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3571853058
Short name T82
Test name
Test status
Simulation time 775862842 ps
CPU time 3.15 seconds
Started May 19 01:03:02 PM PDT 24
Finished May 19 01:03:06 PM PDT 24
Peak memory 212984 kb
Host smart-c5556c0c-55cd-4041-a32b-15098c98704a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571853058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3571853058
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3751109371
Short name T792
Test name
Test status
Simulation time 4812228626 ps
CPU time 39.82 seconds
Started May 19 01:03:01 PM PDT 24
Finished May 19 01:03:42 PM PDT 24
Peak memory 251120 kb
Host smart-6e69bcd4-ecc7-422c-aadd-aef3f9ff3f17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751109371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3751109371
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.384355802
Short name T426
Test name
Test status
Simulation time 1033661442 ps
CPU time 20.8 seconds
Started May 19 01:03:02 PM PDT 24
Finished May 19 01:03:23 PM PDT 24
Peak memory 250924 kb
Host smart-17e8e9c6-98e9-4094-b826-43d1a9d8e8f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384355802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.384355802
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1597824982
Short name T461
Test name
Test status
Simulation time 276798865 ps
CPU time 3.11 seconds
Started May 19 01:03:01 PM PDT 24
Finished May 19 01:03:04 PM PDT 24
Peak memory 218040 kb
Host smart-45f51cfd-3957-481e-82be-e2792d4d3b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597824982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1597824982
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.305178305
Short name T557
Test name
Test status
Simulation time 641960683 ps
CPU time 13.52 seconds
Started May 19 01:03:00 PM PDT 24
Finished May 19 01:03:14 PM PDT 24
Peak memory 214472 kb
Host smart-6729dd77-df39-4c8d-b3e8-777a80c7c0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305178305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.305178305
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2975920946
Short name T88
Test name
Test status
Simulation time 430221168 ps
CPU time 34.52 seconds
Started May 19 01:03:06 PM PDT 24
Finished May 19 01:03:41 PM PDT 24
Peak memory 284104 kb
Host smart-bcca5138-114f-4df0-819f-e5064c4e4805
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975920946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2975920946
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3625434840
Short name T581
Test name
Test status
Simulation time 769823599 ps
CPU time 18.02 seconds
Started May 19 01:03:08 PM PDT 24
Finished May 19 01:03:26 PM PDT 24
Peak memory 219000 kb
Host smart-cf414f0e-38a9-4089-ac2f-f2473c9c2786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625434840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3625434840
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2135399314
Short name T502
Test name
Test status
Simulation time 1105774484 ps
CPU time 12.76 seconds
Started May 19 01:03:04 PM PDT 24
Finished May 19 01:03:17 PM PDT 24
Peak memory 218032 kb
Host smart-06e67391-8423-4dab-a598-6fbb016dee92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135399314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2135399314
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1607892067
Short name T504
Test name
Test status
Simulation time 740401457 ps
CPU time 7.58 seconds
Started May 19 01:03:08 PM PDT 24
Finished May 19 01:03:16 PM PDT 24
Peak memory 218088 kb
Host smart-85b66573-1e79-4970-8021-3a2278883032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607892067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
607892067
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.311845005
Short name T518
Test name
Test status
Simulation time 533187263 ps
CPU time 10.77 seconds
Started May 19 01:03:00 PM PDT 24
Finished May 19 01:03:11 PM PDT 24
Peak memory 218104 kb
Host smart-8c54c79e-11e5-433b-a8a9-9987a6018faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311845005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.311845005
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2616403226
Short name T772
Test name
Test status
Simulation time 99560475 ps
CPU time 1.55 seconds
Started May 19 01:02:53 PM PDT 24
Finished May 19 01:02:56 PM PDT 24
Peak memory 213648 kb
Host smart-650089bf-90af-4ab5-aea0-d708ad96fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616403226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2616403226
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1226135876
Short name T505
Test name
Test status
Simulation time 841554604 ps
CPU time 25.46 seconds
Started May 19 01:02:55 PM PDT 24
Finished May 19 01:03:21 PM PDT 24
Peak memory 250960 kb
Host smart-804c778e-5cfb-4d05-b36f-77e7a51b17aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226135876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1226135876
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2487214634
Short name T99
Test name
Test status
Simulation time 314356458 ps
CPU time 8.67 seconds
Started May 19 01:02:54 PM PDT 24
Finished May 19 01:03:04 PM PDT 24
Peak memory 250916 kb
Host smart-4e24db27-344e-4e47-a6fb-f7ac75dab43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487214634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2487214634
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2037177238
Short name T339
Test name
Test status
Simulation time 8984750306 ps
CPU time 149.78 seconds
Started May 19 01:03:05 PM PDT 24
Finished May 19 01:05:35 PM PDT 24
Peak memory 251272 kb
Host smart-d57205e8-a32d-46c4-a85e-a525f115ef72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037177238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2037177238
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1753331321
Short name T658
Test name
Test status
Simulation time 72396485 ps
CPU time 0.92 seconds
Started May 19 01:03:06 PM PDT 24
Finished May 19 01:03:08 PM PDT 24
Peak memory 211620 kb
Host smart-9bc30e16-5f5d-4e78-ac83-dd9871a8d512
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753331321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1753331321
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.84349143
Short name T524
Test name
Test status
Simulation time 201516509 ps
CPU time 8.29 seconds
Started May 19 01:05:35 PM PDT 24
Finished May 19 01:05:44 PM PDT 24
Peak memory 217992 kb
Host smart-84109a2c-b402-4316-a1c4-db68632bf2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84349143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.84349143
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.711824309
Short name T675
Test name
Test status
Simulation time 401590987 ps
CPU time 3.24 seconds
Started May 19 01:05:35 PM PDT 24
Finished May 19 01:05:40 PM PDT 24
Peak memory 217016 kb
Host smart-f85681bf-2068-4ee0-98da-a6a402abef1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711824309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.711824309
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1807053165
Short name T498
Test name
Test status
Simulation time 20586065 ps
CPU time 1.65 seconds
Started May 19 01:05:33 PM PDT 24
Finished May 19 01:05:36 PM PDT 24
Peak memory 217968 kb
Host smart-5a210fb6-7bf5-4c9d-90ec-015f66607949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807053165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1807053165
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1115765601
Short name T564
Test name
Test status
Simulation time 428296633 ps
CPU time 18.04 seconds
Started May 19 01:05:31 PM PDT 24
Finished May 19 01:05:50 PM PDT 24
Peak memory 226224 kb
Host smart-a93a49fc-6a15-475b-b296-cf8eea4db672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115765601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1115765601
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1631924392
Short name T487
Test name
Test status
Simulation time 446363218 ps
CPU time 10.76 seconds
Started May 19 01:05:35 PM PDT 24
Finished May 19 01:05:47 PM PDT 24
Peak memory 217952 kb
Host smart-9b2bae27-7f63-4893-bdd7-c48bf389bc8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631924392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1631924392
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2152292115
Short name T306
Test name
Test status
Simulation time 1979188172 ps
CPU time 6.88 seconds
Started May 19 01:05:34 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 218004 kb
Host smart-a0c932d8-173c-4c2c-a67a-ba4fff1152d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152292115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2152292115
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.4167036922
Short name T718
Test name
Test status
Simulation time 63062680 ps
CPU time 1.42 seconds
Started May 19 01:05:28 PM PDT 24
Finished May 19 01:05:31 PM PDT 24
Peak memory 213544 kb
Host smart-14343753-ea31-4357-99ab-9b3153776a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167036922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.4167036922
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3597206656
Short name T473
Test name
Test status
Simulation time 650782240 ps
CPU time 29.85 seconds
Started May 19 01:05:28 PM PDT 24
Finished May 19 01:05:59 PM PDT 24
Peak memory 251176 kb
Host smart-d3a344a8-8556-4077-ae3b-b7a0fcae7ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597206656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3597206656
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1379328564
Short name T592
Test name
Test status
Simulation time 59692536 ps
CPU time 6.65 seconds
Started May 19 01:05:31 PM PDT 24
Finished May 19 01:05:38 PM PDT 24
Peak memory 246428 kb
Host smart-3bc93b41-14a8-4344-8fba-dfa4136330db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379328564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1379328564
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3850717646
Short name T338
Test name
Test status
Simulation time 1858678576 ps
CPU time 49.5 seconds
Started May 19 01:05:35 PM PDT 24
Finished May 19 01:06:26 PM PDT 24
Peak memory 250940 kb
Host smart-2106bace-1d16-4ecb-ab54-11f09d8e12b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850717646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3850717646
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1335766988
Short name T786
Test name
Test status
Simulation time 26327318 ps
CPU time 0.79 seconds
Started May 19 01:05:29 PM PDT 24
Finished May 19 01:05:31 PM PDT 24
Peak memory 208708 kb
Host smart-7cd544fc-98df-4d5b-af06-01a96e295957
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335766988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1335766988
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1473507910
Short name T678
Test name
Test status
Simulation time 35357581 ps
CPU time 0.86 seconds
Started May 19 01:05:33 PM PDT 24
Finished May 19 01:05:36 PM PDT 24
Peak memory 209560 kb
Host smart-a13a959b-9703-4780-8a13-137e1e75232c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473507910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1473507910
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1290652685
Short name T447
Test name
Test status
Simulation time 699216140 ps
CPU time 16.75 seconds
Started May 19 01:05:35 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 218136 kb
Host smart-bc139187-f337-4c83-af4d-47c22663ff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290652685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1290652685
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2691957028
Short name T415
Test name
Test status
Simulation time 377975748 ps
CPU time 6.1 seconds
Started May 19 01:05:35 PM PDT 24
Finished May 19 01:05:42 PM PDT 24
Peak memory 217332 kb
Host smart-bde0afa2-126a-4059-b353-53bfb710f255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691957028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2691957028
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.787930321
Short name T544
Test name
Test status
Simulation time 83349344 ps
CPU time 2.07 seconds
Started May 19 01:05:30 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 218104 kb
Host smart-00cb5668-e0c4-4d98-bb47-e64082442501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787930321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.787930321
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3105667119
Short name T414
Test name
Test status
Simulation time 2265685466 ps
CPU time 10.47 seconds
Started May 19 01:05:34 PM PDT 24
Finished May 19 01:05:46 PM PDT 24
Peak memory 226196 kb
Host smart-3f2df2bc-052c-400f-b963-64efcb6c7026
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105667119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3105667119
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3163930551
Short name T246
Test name
Test status
Simulation time 225481220 ps
CPU time 9.86 seconds
Started May 19 01:05:33 PM PDT 24
Finished May 19 01:05:44 PM PDT 24
Peak memory 217968 kb
Host smart-d0617ac8-35d5-4f7f-a7f8-4f9d03cf5315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163930551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3163930551
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.79417929
Short name T441
Test name
Test status
Simulation time 2152882877 ps
CPU time 8.51 seconds
Started May 19 01:05:34 PM PDT 24
Finished May 19 01:05:44 PM PDT 24
Peak memory 218108 kb
Host smart-3f69cdc8-4ec6-4d72-b966-68db955ff5ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79417929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.79417929
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.804412506
Short name T231
Test name
Test status
Simulation time 34056789 ps
CPU time 1.36 seconds
Started May 19 01:05:34 PM PDT 24
Finished May 19 01:05:37 PM PDT 24
Peak memory 213264 kb
Host smart-08a9db6e-89c1-414c-a7d5-4120129c401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804412506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.804412506
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3760300113
Short name T668
Test name
Test status
Simulation time 1745737188 ps
CPU time 29.07 seconds
Started May 19 01:05:34 PM PDT 24
Finished May 19 01:06:04 PM PDT 24
Peak memory 250844 kb
Host smart-747ed9f4-7c68-4fcc-b735-7d6c0c1c64de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760300113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3760300113
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.891967616
Short name T571
Test name
Test status
Simulation time 653861619 ps
CPU time 7.74 seconds
Started May 19 01:05:33 PM PDT 24
Finished May 19 01:05:41 PM PDT 24
Peak memory 250932 kb
Host smart-294c5b9f-a91c-4cce-be2e-e8e0f2e5cc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891967616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.891967616
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2230848002
Short name T360
Test name
Test status
Simulation time 7867366742 ps
CPU time 145.4 seconds
Started May 19 01:05:33 PM PDT 24
Finished May 19 01:07:59 PM PDT 24
Peak memory 252104 kb
Host smart-822395e0-68b5-4392-815c-4843bebb32cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230848002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2230848002
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.744332005
Short name T642
Test name
Test status
Simulation time 47164553 ps
CPU time 0.91 seconds
Started May 19 01:05:32 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 211540 kb
Host smart-e4a6a7f4-5994-4c0b-a7f4-35d2b20f4aaf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744332005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.744332005
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2965334308
Short name T839
Test name
Test status
Simulation time 19448303 ps
CPU time 0.92 seconds
Started May 19 01:05:41 PM PDT 24
Finished May 19 01:05:42 PM PDT 24
Peak memory 209612 kb
Host smart-a8e47ace-8a4a-47aa-b03e-914e2779f587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965334308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2965334308
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3874470270
Short name T588
Test name
Test status
Simulation time 1550771617 ps
CPU time 10.23 seconds
Started May 19 01:05:38 PM PDT 24
Finished May 19 01:05:50 PM PDT 24
Peak memory 218040 kb
Host smart-4b447fe3-5694-4b61-adc8-32697d493c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874470270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3874470270
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.385237370
Short name T591
Test name
Test status
Simulation time 1432598530 ps
CPU time 32.96 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:06:13 PM PDT 24
Peak memory 217164 kb
Host smart-94c8a854-c4cc-4a7e-a848-07f017e9d984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385237370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.385237370
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1133077161
Short name T855
Test name
Test status
Simulation time 144009365 ps
CPU time 4.45 seconds
Started May 19 01:05:37 PM PDT 24
Finished May 19 01:05:42 PM PDT 24
Peak memory 218284 kb
Host smart-5755b208-c670-4e4a-826e-871cdd428eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133077161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1133077161
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1579854497
Short name T351
Test name
Test status
Simulation time 1660147183 ps
CPU time 14.22 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:55 PM PDT 24
Peak memory 226344 kb
Host smart-de09a75f-2329-4682-9263-f95a96e152de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579854497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1579854497
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1464571618
Short name T769
Test name
Test status
Simulation time 333812408 ps
CPU time 10.28 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:50 PM PDT 24
Peak memory 217984 kb
Host smart-e4267c13-f25e-4a89-bc61-c2d1dfb1ed93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464571618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1464571618
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1497447108
Short name T282
Test name
Test status
Simulation time 1403687773 ps
CPU time 10.78 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:50 PM PDT 24
Peak memory 218056 kb
Host smart-be85d8dc-f21b-478b-99b9-4f6d07612d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497447108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1497447108
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1451294881
Short name T834
Test name
Test status
Simulation time 60865419 ps
CPU time 1.51 seconds
Started May 19 01:05:32 PM PDT 24
Finished May 19 01:05:34 PM PDT 24
Peak memory 213808 kb
Host smart-f7126b90-f953-4725-aa0c-86d732fc9dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451294881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1451294881
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3739210663
Short name T851
Test name
Test status
Simulation time 621798598 ps
CPU time 29.64 seconds
Started May 19 01:05:42 PM PDT 24
Finished May 19 01:06:13 PM PDT 24
Peak memory 250668 kb
Host smart-92885270-9ee4-4b00-a853-b09f9ba7a2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739210663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3739210663
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.245581294
Short name T86
Test name
Test status
Simulation time 218576101 ps
CPU time 5.51 seconds
Started May 19 01:05:42 PM PDT 24
Finished May 19 01:05:48 PM PDT 24
Peak memory 246544 kb
Host smart-9238478d-c2eb-447a-9b2b-de7932ca0668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245581294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.245581294
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4110046691
Short name T79
Test name
Test status
Simulation time 12961991975 ps
CPU time 363 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:11:43 PM PDT 24
Peak memory 283756 kb
Host smart-217260f5-ad1b-4769-842c-59933636201b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110046691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4110046691
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2264533038
Short name T732
Test name
Test status
Simulation time 40003561 ps
CPU time 0.91 seconds
Started May 19 01:05:37 PM PDT 24
Finished May 19 01:05:39 PM PDT 24
Peak memory 208596 kb
Host smart-a1fcd088-398c-49ce-8079-f2e0b59c5624
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264533038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2264533038
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2935347403
Short name T445
Test name
Test status
Simulation time 36129092 ps
CPU time 1.12 seconds
Started May 19 01:05:46 PM PDT 24
Finished May 19 01:05:48 PM PDT 24
Peak memory 209628 kb
Host smart-6adb209a-2f6d-48eb-bcb2-4040d79342d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935347403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2935347403
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2988377714
Short name T791
Test name
Test status
Simulation time 556783940 ps
CPU time 23.04 seconds
Started May 19 01:05:41 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 217932 kb
Host smart-5e6643f1-9325-46ac-a026-7d854a4855e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988377714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2988377714
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1365116781
Short name T24
Test name
Test status
Simulation time 816842185 ps
CPU time 10.43 seconds
Started May 19 01:05:38 PM PDT 24
Finished May 19 01:05:49 PM PDT 24
Peak memory 209528 kb
Host smart-a51f9087-a9a1-4af5-83dc-0a4c77c123e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365116781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1365116781
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2675508438
Short name T821
Test name
Test status
Simulation time 544287817 ps
CPU time 3.23 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 218080 kb
Host smart-1f7269d9-c103-4209-9bc2-158c370d18aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675508438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2675508438
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2825752506
Short name T470
Test name
Test status
Simulation time 10398827076 ps
CPU time 16.25 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:57 PM PDT 24
Peak memory 226200 kb
Host smart-05897773-86de-4118-8c7c-3d21d039a8ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825752506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2825752506
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1602769072
Short name T859
Test name
Test status
Simulation time 3576467024 ps
CPU time 13.34 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:54 PM PDT 24
Peak memory 219200 kb
Host smart-57db34d4-b6c6-4720-90ba-5bcfb5f42ad8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602769072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1602769072
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3894011820
Short name T257
Test name
Test status
Simulation time 756127408 ps
CPU time 7.03 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:47 PM PDT 24
Peak memory 217912 kb
Host smart-609614eb-e2b4-48ec-9006-f08e4f7cec5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894011820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3894011820
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2264114129
Short name T676
Test name
Test status
Simulation time 1160253252 ps
CPU time 8.18 seconds
Started May 19 01:05:40 PM PDT 24
Finished May 19 01:05:49 PM PDT 24
Peak memory 218180 kb
Host smart-786c217a-c80f-43a3-819f-adb1d37c7f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264114129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2264114129
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1764235695
Short name T371
Test name
Test status
Simulation time 81665548 ps
CPU time 1.5 seconds
Started May 19 01:05:41 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 217852 kb
Host smart-ecc2fc16-8cc2-4859-b9b7-59e57f01d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764235695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1764235695
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2215973987
Short name T437
Test name
Test status
Simulation time 469757669 ps
CPU time 27.94 seconds
Started May 19 01:05:38 PM PDT 24
Finished May 19 01:06:06 PM PDT 24
Peak memory 250996 kb
Host smart-305b9944-c096-4922-8a01-f02af9a68d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215973987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2215973987
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3079289101
Short name T254
Test name
Test status
Simulation time 345190631 ps
CPU time 8.61 seconds
Started May 19 01:05:39 PM PDT 24
Finished May 19 01:05:49 PM PDT 24
Peak memory 246836 kb
Host smart-f9fe53b1-ac4e-414f-9f25-4b5d12bc29c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079289101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3079289101
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3294534859
Short name T341
Test name
Test status
Simulation time 1870981581 ps
CPU time 61.04 seconds
Started May 19 01:05:37 PM PDT 24
Finished May 19 01:06:39 PM PDT 24
Peak memory 272516 kb
Host smart-32c618f2-137d-4af1-8942-3b701fac2f1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294534859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3294534859
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.45174323
Short name T431
Test name
Test status
Simulation time 20966302 ps
CPU time 0.9 seconds
Started May 19 01:05:37 PM PDT 24
Finished May 19 01:05:39 PM PDT 24
Peak memory 208436 kb
Host smart-1cb98edf-5b2e-4b2f-8bce-0e7098fc0fb0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45174323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctr
l_volatile_unlock_smoke.45174323
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3138567231
Short name T146
Test name
Test status
Simulation time 32965276 ps
CPU time 0.86 seconds
Started May 19 01:05:47 PM PDT 24
Finished May 19 01:05:49 PM PDT 24
Peak memory 209556 kb
Host smart-fdcd67e5-f01d-4bda-96b7-1bbac7fbb902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138567231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3138567231
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1201003847
Short name T822
Test name
Test status
Simulation time 636510032 ps
CPU time 8.36 seconds
Started May 19 01:05:46 PM PDT 24
Finished May 19 01:05:55 PM PDT 24
Peak memory 217996 kb
Host smart-aaefca6e-39b7-4035-9498-6f2d34b67dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201003847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1201003847
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.634866837
Short name T840
Test name
Test status
Simulation time 1754275878 ps
CPU time 11.54 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:58 PM PDT 24
Peak memory 209768 kb
Host smart-51da99cf-add2-42ba-9425-0f491bdc058a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634866837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.634866837
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1078590710
Short name T514
Test name
Test status
Simulation time 926795397 ps
CPU time 3.28 seconds
Started May 19 01:05:43 PM PDT 24
Finished May 19 01:05:46 PM PDT 24
Peak memory 218124 kb
Host smart-130ef6c1-4743-4490-9142-745b4b94fecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078590710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1078590710
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1583677461
Short name T365
Test name
Test status
Simulation time 3403866910 ps
CPU time 14.25 seconds
Started May 19 01:05:47 PM PDT 24
Finished May 19 01:06:02 PM PDT 24
Peak memory 226136 kb
Host smart-6856d189-dc56-4976-960f-92304cf7e0ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583677461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1583677461
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3404359198
Short name T391
Test name
Test status
Simulation time 2959125853 ps
CPU time 12.81 seconds
Started May 19 01:05:46 PM PDT 24
Finished May 19 01:05:59 PM PDT 24
Peak memory 218044 kb
Host smart-81175571-2a61-46db-8fe8-02666b541697
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404359198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3404359198
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3112527189
Short name T569
Test name
Test status
Simulation time 676144648 ps
CPU time 12.56 seconds
Started May 19 01:05:47 PM PDT 24
Finished May 19 01:06:00 PM PDT 24
Peak memory 218004 kb
Host smart-d9abfda3-ed83-45bc-a7be-25bd612ec0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112527189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3112527189
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3136292969
Short name T98
Test name
Test status
Simulation time 351430195 ps
CPU time 8.51 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:55 PM PDT 24
Peak memory 218020 kb
Host smart-0751f6ed-863a-41de-8abf-669a687cd82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136292969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3136292969
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1120565763
Short name T375
Test name
Test status
Simulation time 185832001 ps
CPU time 3.06 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:05:58 PM PDT 24
Peak memory 214364 kb
Host smart-06452ce7-eebf-4e41-96be-461f9f488721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120565763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1120565763
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.4257148368
Short name T807
Test name
Test status
Simulation time 497654876 ps
CPU time 24.94 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:06:10 PM PDT 24
Peak memory 250940 kb
Host smart-4f482393-7eab-4a1b-ab13-f4c3e8dd71be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257148368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4257148368
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3797343822
Short name T556
Test name
Test status
Simulation time 60516982 ps
CPU time 7.17 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 247024 kb
Host smart-f7d4f838-549a-417a-9d16-dc3c0c700d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797343822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3797343822
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1038708260
Short name T333
Test name
Test status
Simulation time 21350470056 ps
CPU time 182.2 seconds
Started May 19 01:05:47 PM PDT 24
Finished May 19 01:08:50 PM PDT 24
Peak memory 251032 kb
Host smart-a733462f-78e7-4160-a0e5-292a704d1126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038708260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1038708260
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2118450941
Short name T568
Test name
Test status
Simulation time 18966933 ps
CPU time 0.79 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:46 PM PDT 24
Peak memory 208480 kb
Host smart-21a7e026-bec8-4606-8625-fc2e4552f41e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118450941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2118450941
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.818519700
Short name T687
Test name
Test status
Simulation time 39134464 ps
CPU time 1.05 seconds
Started May 19 01:05:50 PM PDT 24
Finished May 19 01:05:52 PM PDT 24
Peak memory 209460 kb
Host smart-724eff52-d3d5-4476-85ad-dd03f11611ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818519700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.818519700
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1822814127
Short name T631
Test name
Test status
Simulation time 292737269 ps
CPU time 7.97 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:54 PM PDT 24
Peak memory 217884 kb
Host smart-dede440f-250f-4da6-8bb9-805d1dbe0438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822814127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1822814127
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1853040817
Short name T295
Test name
Test status
Simulation time 1926541221 ps
CPU time 4.84 seconds
Started May 19 01:05:47 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 216924 kb
Host smart-bbe39901-d85c-41ca-94f8-47c3d16c54d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853040817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1853040817
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3180713400
Short name T578
Test name
Test status
Simulation time 53719887 ps
CPU time 2.04 seconds
Started May 19 01:05:44 PM PDT 24
Finished May 19 01:05:46 PM PDT 24
Peak memory 218008 kb
Host smart-9f613469-b185-4f82-ac26-343a10947674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180713400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3180713400
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4152786682
Short name T720
Test name
Test status
Simulation time 440196592 ps
CPU time 11.84 seconds
Started May 19 01:05:44 PM PDT 24
Finished May 19 01:05:56 PM PDT 24
Peak memory 226048 kb
Host smart-e8ce631c-8bd4-4b5c-bd16-f0a5e784e3fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152786682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4152786682
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2437143318
Short name T237
Test name
Test status
Simulation time 238279841 ps
CPU time 9.89 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:55 PM PDT 24
Peak memory 217968 kb
Host smart-b328bf4d-f4da-4593-bdbf-c34b3d6b9430
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437143318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2437143318
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2957978338
Short name T314
Test name
Test status
Simulation time 968861338 ps
CPU time 7.76 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:54 PM PDT 24
Peak memory 217956 kb
Host smart-383d957a-b885-4f86-9914-cd524485fe40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957978338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2957978338
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.437533987
Short name T376
Test name
Test status
Simulation time 271160987 ps
CPU time 9.79 seconds
Started May 19 01:05:47 PM PDT 24
Finished May 19 01:05:57 PM PDT 24
Peak memory 218120 kb
Host smart-4e68a7aa-559f-48ae-a3a5-edb720f980c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437533987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.437533987
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1035134519
Short name T270
Test name
Test status
Simulation time 89387021 ps
CPU time 1.11 seconds
Started May 19 01:05:47 PM PDT 24
Finished May 19 01:05:49 PM PDT 24
Peak memory 212844 kb
Host smart-0a51a684-ed1f-48f4-8a44-6aedc7b9188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035134519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1035134519
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2528492546
Short name T551
Test name
Test status
Simulation time 873762375 ps
CPU time 33.8 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:06:20 PM PDT 24
Peak memory 250936 kb
Host smart-cc580adb-1448-4ac0-96ca-7c9e17c16972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528492546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2528492546
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2402389729
Short name T761
Test name
Test status
Simulation time 205757841 ps
CPU time 6.8 seconds
Started May 19 01:05:45 PM PDT 24
Finished May 19 01:05:52 PM PDT 24
Peak memory 246120 kb
Host smart-bc78d54c-cd57-4970-8c09-cbeb0c6af791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402389729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2402389729
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1593955250
Short name T771
Test name
Test status
Simulation time 31056121538 ps
CPU time 194.61 seconds
Started May 19 01:05:57 PM PDT 24
Finished May 19 01:09:12 PM PDT 24
Peak memory 278200 kb
Host smart-f2d38a57-8ba2-48ac-8f13-db70e1f328d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1593955250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1593955250
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1064188769
Short name T716
Test name
Test status
Simulation time 183820193 ps
CPU time 0.98 seconds
Started May 19 01:05:44 PM PDT 24
Finished May 19 01:05:45 PM PDT 24
Peak memory 212608 kb
Host smart-9f1d5ca4-2da9-4a29-9813-39daac605e4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064188769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1064188769
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3466116346
Short name T507
Test name
Test status
Simulation time 58087016 ps
CPU time 1.14 seconds
Started May 19 01:05:57 PM PDT 24
Finished May 19 01:05:59 PM PDT 24
Peak memory 209548 kb
Host smart-a20ddcd6-e6a8-4773-95fe-55394e696d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466116346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3466116346
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1794307944
Short name T689
Test name
Test status
Simulation time 332482022 ps
CPU time 13.95 seconds
Started May 19 01:05:57 PM PDT 24
Finished May 19 01:06:11 PM PDT 24
Peak memory 218040 kb
Host smart-ab23825d-e962-4035-b805-5e6cad88b934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794307944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1794307944
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1981602876
Short name T97
Test name
Test status
Simulation time 2403269328 ps
CPU time 5.6 seconds
Started May 19 01:05:49 PM PDT 24
Finished May 19 01:05:56 PM PDT 24
Peak memory 209636 kb
Host smart-f1b01af9-c019-48bb-81da-121a6d60273f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981602876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1981602876
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.362456996
Short name T236
Test name
Test status
Simulation time 48886974 ps
CPU time 2.3 seconds
Started May 19 01:05:52 PM PDT 24
Finished May 19 01:05:55 PM PDT 24
Peak memory 218116 kb
Host smart-34d2e68b-7ade-4a4a-983e-6432f6c38158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362456996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.362456996
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3250597667
Short name T435
Test name
Test status
Simulation time 589985849 ps
CPU time 15.56 seconds
Started May 19 01:05:49 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 218996 kb
Host smart-5143c1ec-5fa6-49dc-87b6-15bdb18b6cbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250597667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3250597667
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1871480217
Short name T595
Test name
Test status
Simulation time 1844392044 ps
CPU time 15.11 seconds
Started May 19 01:05:50 PM PDT 24
Finished May 19 01:06:06 PM PDT 24
Peak memory 218008 kb
Host smart-e5691cc8-76e3-497e-b0d3-3ba00200f92e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871480217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1871480217
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1943839050
Short name T707
Test name
Test status
Simulation time 1450380417 ps
CPU time 14.5 seconds
Started May 19 01:05:50 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 217964 kb
Host smart-ceb79991-e6e5-4e36-b97c-507cdeb2a72e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943839050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1943839050
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1061613984
Short name T387
Test name
Test status
Simulation time 282636802 ps
CPU time 10.31 seconds
Started May 19 01:05:57 PM PDT 24
Finished May 19 01:06:08 PM PDT 24
Peak memory 218048 kb
Host smart-4dd38556-dd1c-471d-a1e7-43fadce9d0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061613984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1061613984
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1639379559
Short name T527
Test name
Test status
Simulation time 28547760 ps
CPU time 1.15 seconds
Started May 19 01:05:51 PM PDT 24
Finished May 19 01:05:52 PM PDT 24
Peak memory 213204 kb
Host smart-b8219376-1683-423d-86a6-9b2c090a7121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639379559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1639379559
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3432966198
Short name T838
Test name
Test status
Simulation time 270219535 ps
CPU time 32.45 seconds
Started May 19 01:05:50 PM PDT 24
Finished May 19 01:06:23 PM PDT 24
Peak memory 250976 kb
Host smart-b2594c27-d51d-4f25-bc62-80a8759d54db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432966198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3432966198
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.932494952
Short name T448
Test name
Test status
Simulation time 93598575 ps
CPU time 3.3 seconds
Started May 19 01:05:49 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 222256 kb
Host smart-c0101545-b5c6-4ba1-848c-2bf7f1502ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932494952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.932494952
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.403728920
Short name T294
Test name
Test status
Simulation time 10856200572 ps
CPU time 132.59 seconds
Started May 19 01:05:50 PM PDT 24
Finished May 19 01:08:03 PM PDT 24
Peak memory 283760 kb
Host smart-fd73450a-081a-4c0c-a3cd-1af0fef7f31e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403728920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.403728920
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3284554053
Short name T340
Test name
Test status
Simulation time 29657975 ps
CPU time 0.99 seconds
Started May 19 01:05:52 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 211548 kb
Host smart-4a8bdb65-688c-45fc-9391-db35ddb97029
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284554053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3284554053
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1701708261
Short name T516
Test name
Test status
Simulation time 26808057 ps
CPU time 1.27 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:05:57 PM PDT 24
Peak memory 209612 kb
Host smart-2cf5ba73-7448-438a-88a5-7c69eea07848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701708261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1701708261
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2085831020
Short name T663
Test name
Test status
Simulation time 310434482 ps
CPU time 12.48 seconds
Started May 19 01:05:51 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 218072 kb
Host smart-67dce711-6d2f-4c44-8968-8449aed62365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085831020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2085831020
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2655924921
Short name T9
Test name
Test status
Simulation time 608844302 ps
CPU time 4.68 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:06:00 PM PDT 24
Peak memory 216948 kb
Host smart-f823f41a-9ea5-420f-ad7b-c7e2795176a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655924921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2655924921
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1807677409
Short name T715
Test name
Test status
Simulation time 44206238 ps
CPU time 2.23 seconds
Started May 19 01:05:51 PM PDT 24
Finished May 19 01:05:54 PM PDT 24
Peak memory 217872 kb
Host smart-a3afbbbf-a085-4e16-b809-8151a78b78bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807677409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1807677409
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2631587191
Short name T280
Test name
Test status
Simulation time 807751977 ps
CPU time 11.33 seconds
Started May 19 01:05:50 PM PDT 24
Finished May 19 01:06:02 PM PDT 24
Peak memory 226508 kb
Host smart-2c16f627-ff34-4005-bc52-4b6855bdb6dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631587191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2631587191
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2596615596
Short name T823
Test name
Test status
Simulation time 808461888 ps
CPU time 8.17 seconds
Started May 19 01:05:51 PM PDT 24
Finished May 19 01:06:00 PM PDT 24
Peak memory 218244 kb
Host smart-e59e7297-dcc2-4bb1-a33e-cffe97035304
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596615596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2596615596
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2121071742
Short name T303
Test name
Test status
Simulation time 265720534 ps
CPU time 7.29 seconds
Started May 19 01:05:49 PM PDT 24
Finished May 19 01:05:58 PM PDT 24
Peak memory 218036 kb
Host smart-84e9b0b3-9281-4aac-869e-53705630b0fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121071742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2121071742
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2920662705
Short name T84
Test name
Test status
Simulation time 84834113 ps
CPU time 2.54 seconds
Started May 19 01:05:49 PM PDT 24
Finished May 19 01:05:52 PM PDT 24
Peak memory 214292 kb
Host smart-0788f026-b9c7-4701-b0c8-a9eaed18e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920662705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2920662705
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1822981280
Short name T755
Test name
Test status
Simulation time 736822932 ps
CPU time 21.66 seconds
Started May 19 01:05:50 PM PDT 24
Finished May 19 01:06:12 PM PDT 24
Peak memory 250888 kb
Host smart-71031788-9835-4778-b7b8-690009cd3865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822981280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1822981280
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.603398408
Short name T222
Test name
Test status
Simulation time 225623930 ps
CPU time 2.85 seconds
Started May 19 01:05:49 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 218000 kb
Host smart-a789f56f-87e3-42fd-81ff-7c62556820a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603398408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.603398408
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2399992394
Short name T393
Test name
Test status
Simulation time 4290467066 ps
CPU time 169.95 seconds
Started May 19 01:05:55 PM PDT 24
Finished May 19 01:08:45 PM PDT 24
Peak memory 272580 kb
Host smart-d092bc7a-6039-4654-9408-d79217af95bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399992394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2399992394
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.279093494
Short name T852
Test name
Test status
Simulation time 10899786 ps
CPU time 0.93 seconds
Started May 19 01:05:52 PM PDT 24
Finished May 19 01:05:53 PM PDT 24
Peak memory 208592 kb
Host smart-15156c78-e4c1-463c-beed-5acfa4e8a767
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279093494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.279093494
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1997792198
Short name T187
Test name
Test status
Simulation time 19079699 ps
CPU time 1.16 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:05:56 PM PDT 24
Peak memory 209612 kb
Host smart-015e1b93-c38c-4c35-a522-ea2b92dda508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997792198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1997792198
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.392804104
Short name T723
Test name
Test status
Simulation time 839230458 ps
CPU time 11.19 seconds
Started May 19 01:05:53 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 218088 kb
Host smart-28be0020-89dd-4861-991e-b9dca2a8fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392804104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.392804104
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.171819062
Short name T646
Test name
Test status
Simulation time 227141570 ps
CPU time 2 seconds
Started May 19 01:05:58 PM PDT 24
Finished May 19 01:06:00 PM PDT 24
Peak memory 209536 kb
Host smart-7ba4aaba-7083-4447-9cdf-b16d5df82156
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171819062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.171819062
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1797272450
Short name T403
Test name
Test status
Simulation time 16469251 ps
CPU time 1.5 seconds
Started May 19 01:05:56 PM PDT 24
Finished May 19 01:05:58 PM PDT 24
Peak memory 218048 kb
Host smart-403af479-0c1a-49c8-84a4-8308fb97462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797272450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1797272450
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2471034181
Short name T555
Test name
Test status
Simulation time 1321239306 ps
CPU time 13.27 seconds
Started May 19 01:05:53 PM PDT 24
Finished May 19 01:06:07 PM PDT 24
Peak memory 218952 kb
Host smart-fc78e471-3a48-4a88-b6f9-747c548a0fee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471034181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2471034181
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.314077202
Short name T362
Test name
Test status
Simulation time 1260037064 ps
CPU time 8.83 seconds
Started May 19 01:05:55 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 217904 kb
Host smart-e5db93fd-bc6d-428e-a574-375de9d40128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314077202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.314077202
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.4053923504
Short name T849
Test name
Test status
Simulation time 6045715204 ps
CPU time 12 seconds
Started May 19 01:05:56 PM PDT 24
Finished May 19 01:06:08 PM PDT 24
Peak memory 218012 kb
Host smart-2b541dd5-413d-4c6d-a1e6-6b21be3c6fa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053923504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
4053923504
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3409150151
Short name T701
Test name
Test status
Simulation time 1422230317 ps
CPU time 8.73 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:06:04 PM PDT 24
Peak memory 218060 kb
Host smart-525a116f-250d-45cd-a226-00fef0ade942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409150151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3409150151
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4235264263
Short name T267
Test name
Test status
Simulation time 128259317 ps
CPU time 5.09 seconds
Started May 19 01:05:57 PM PDT 24
Finished May 19 01:06:03 PM PDT 24
Peak memory 214672 kb
Host smart-f5d0671f-261d-45db-9a60-df1fd4b92384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235264263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4235264263
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3558736042
Short name T670
Test name
Test status
Simulation time 241364642 ps
CPU time 33.59 seconds
Started May 19 01:05:56 PM PDT 24
Finished May 19 01:06:30 PM PDT 24
Peak memory 250804 kb
Host smart-39805ab6-9cd2-44f9-b013-cd5345a970de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558736042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3558736042
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3434078069
Short name T748
Test name
Test status
Simulation time 228657061 ps
CPU time 7.89 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:06:02 PM PDT 24
Peak memory 250932 kb
Host smart-125defd8-c021-49d2-8064-0e7605792d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434078069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3434078069
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3247310039
Short name T172
Test name
Test status
Simulation time 17594271222 ps
CPU time 158.02 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:08:33 PM PDT 24
Peak memory 275672 kb
Host smart-a6bf4d5f-80e1-4fb0-9d60-cf6eb93115e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247310039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3247310039
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.746964091
Short name T600
Test name
Test status
Simulation time 20872911 ps
CPU time 1.16 seconds
Started May 19 01:05:58 PM PDT 24
Finished May 19 01:05:59 PM PDT 24
Peak memory 212676 kb
Host smart-35ba8a28-e7f0-41ad-9165-68f09da6f96a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746964091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.746964091
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1074257598
Short name T558
Test name
Test status
Simulation time 22252243 ps
CPU time 1.25 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 209752 kb
Host smart-f4275ad5-9c36-4373-bd3b-aca2bd8709a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074257598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1074257598
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.697370423
Short name T321
Test name
Test status
Simulation time 10273937553 ps
CPU time 19.2 seconds
Started May 19 01:05:56 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 218100 kb
Host smart-cc809bce-75c9-4704-bc4a-abb22a66d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697370423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.697370423
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2590434042
Short name T384
Test name
Test status
Simulation time 151983909 ps
CPU time 4.75 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:08 PM PDT 24
Peak memory 216960 kb
Host smart-95312c7b-cfc9-41e3-bda1-d9d9dd0ac57c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590434042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2590434042
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2907597992
Short name T149
Test name
Test status
Simulation time 251223946 ps
CPU time 3.11 seconds
Started May 19 01:05:53 PM PDT 24
Finished May 19 01:05:56 PM PDT 24
Peak memory 218056 kb
Host smart-9fca48cf-4627-4720-b925-904fe1459d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907597992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2907597992
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2195494876
Short name T265
Test name
Test status
Simulation time 414514911 ps
CPU time 13.94 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:17 PM PDT 24
Peak memory 218988 kb
Host smart-34feaa62-fa08-43be-b65c-001771958058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195494876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2195494876
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.19393809
Short name T660
Test name
Test status
Simulation time 1164913474 ps
CPU time 8.71 seconds
Started May 19 01:06:00 PM PDT 24
Finished May 19 01:06:09 PM PDT 24
Peak memory 218004 kb
Host smart-c20756ff-29c4-4071-b580-021c50b57a01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19393809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_dig
est.19393809
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3687139512
Short name T309
Test name
Test status
Simulation time 420655612 ps
CPU time 12.05 seconds
Started May 19 01:06:01 PM PDT 24
Finished May 19 01:06:14 PM PDT 24
Peak memory 218308 kb
Host smart-9b68eaf0-62d5-446b-ae74-760ab9201282
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687139512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3687139512
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3224522646
Short name T820
Test name
Test status
Simulation time 438789277 ps
CPU time 12.37 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:14 PM PDT 24
Peak memory 218100 kb
Host smart-26ed954f-307e-4b42-bbda-9fcb02660022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224522646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3224522646
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3969510007
Short name T649
Test name
Test status
Simulation time 256736988 ps
CPU time 2.36 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:05:58 PM PDT 24
Peak memory 213772 kb
Host smart-46021410-78ed-46e0-83e0-962882e51e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969510007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3969510007
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3328739196
Short name T809
Test name
Test status
Simulation time 1324393676 ps
CPU time 28.08 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:06:23 PM PDT 24
Peak memory 251240 kb
Host smart-b1d15b9a-fd46-4c05-8302-529082b498e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328739196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3328739196
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2829718111
Short name T549
Test name
Test status
Simulation time 62248132 ps
CPU time 8.8 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:06:04 PM PDT 24
Peak memory 250928 kb
Host smart-c233d0f9-fa2f-40e3-82cf-2e9b80aa1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829718111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2829718111
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2650096112
Short name T423
Test name
Test status
Simulation time 2486615339 ps
CPU time 62.07 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:07:05 PM PDT 24
Peak memory 270648 kb
Host smart-0a7c85c6-05c7-4cd3-9835-6dc3d702c13d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650096112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2650096112
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3719640947
Short name T824
Test name
Test status
Simulation time 43876694 ps
CPU time 0.94 seconds
Started May 19 01:05:54 PM PDT 24
Finished May 19 01:05:56 PM PDT 24
Peak memory 208828 kb
Host smart-83878f26-64fd-4e76-952a-a2941b9b0cf7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719640947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3719640947
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.849320955
Short name T606
Test name
Test status
Simulation time 125693562 ps
CPU time 0.89 seconds
Started May 19 01:03:22 PM PDT 24
Finished May 19 01:03:24 PM PDT 24
Peak memory 209568 kb
Host smart-5fbdfefb-99aa-4597-afd2-913c918e9465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849320955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.849320955
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.155551568
Short name T776
Test name
Test status
Simulation time 12279691 ps
CPU time 0.84 seconds
Started May 19 01:03:11 PM PDT 24
Finished May 19 01:03:12 PM PDT 24
Peak memory 209440 kb
Host smart-4e6b43cf-0847-4b73-ae9f-17d948c40aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155551568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.155551568
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.785234238
Short name T408
Test name
Test status
Simulation time 900806718 ps
CPU time 11.89 seconds
Started May 19 01:03:08 PM PDT 24
Finished May 19 01:03:20 PM PDT 24
Peak memory 218008 kb
Host smart-9d5efc10-1389-4314-a1a6-34674a87bced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785234238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.785234238
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2211918768
Short name T765
Test name
Test status
Simulation time 1784900751 ps
CPU time 6.34 seconds
Started May 19 01:03:12 PM PDT 24
Finished May 19 01:03:19 PM PDT 24
Peak memory 209528 kb
Host smart-8a995028-1764-4c3f-bc95-80b312376d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211918768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2211918768
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2881123779
Short name T777
Test name
Test status
Simulation time 6346803346 ps
CPU time 44.66 seconds
Started May 19 01:03:11 PM PDT 24
Finished May 19 01:03:56 PM PDT 24
Peak memory 218988 kb
Host smart-b408ad7b-18a0-4e33-917c-6abb3644a3c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881123779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2881123779
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1813298385
Short name T758
Test name
Test status
Simulation time 550661584 ps
CPU time 13.54 seconds
Started May 19 01:03:11 PM PDT 24
Finished May 19 01:03:25 PM PDT 24
Peak memory 217080 kb
Host smart-3548649b-63ff-4056-9346-10cb5e79c0e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813298385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
813298385
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.530247363
Short name T706
Test name
Test status
Simulation time 1401907267 ps
CPU time 10.43 seconds
Started May 19 01:03:11 PM PDT 24
Finished May 19 01:03:23 PM PDT 24
Peak memory 217976 kb
Host smart-513fe0aa-2f9b-474f-a9fa-0c14ffdaa901
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530247363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.530247363
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3528736897
Short name T684
Test name
Test status
Simulation time 1335716552 ps
CPU time 38.98 seconds
Started May 19 01:03:23 PM PDT 24
Finished May 19 01:04:03 PM PDT 24
Peak memory 213488 kb
Host smart-4fbfbee3-f043-42fb-8355-d06b39498aa4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528736897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3528736897
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4005911663
Short name T639
Test name
Test status
Simulation time 376283280 ps
CPU time 2.01 seconds
Started May 19 01:03:11 PM PDT 24
Finished May 19 01:03:13 PM PDT 24
Peak memory 212984 kb
Host smart-84be9797-c769-48f6-943f-eb8d6f3fce63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005911663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4005911663
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2969543041
Short name T526
Test name
Test status
Simulation time 1216608628 ps
CPU time 47.87 seconds
Started May 19 01:03:12 PM PDT 24
Finished May 19 01:04:00 PM PDT 24
Peak memory 251456 kb
Host smart-eb688ea2-2248-44dc-90cc-c43ab5716876
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969543041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2969543041
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3894904549
Short name T842
Test name
Test status
Simulation time 729294795 ps
CPU time 12.66 seconds
Started May 19 01:03:11 PM PDT 24
Finished May 19 01:03:25 PM PDT 24
Peak memory 222988 kb
Host smart-09ea37e6-3fae-4213-af6c-6f5504def876
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894904549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3894904549
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1346826860
Short name T440
Test name
Test status
Simulation time 93314057 ps
CPU time 4.37 seconds
Started May 19 01:03:05 PM PDT 24
Finished May 19 01:03:09 PM PDT 24
Peak memory 218052 kb
Host smart-dc6b38d1-8af6-4b28-85b8-956e073de04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346826860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1346826860
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2940402875
Short name T734
Test name
Test status
Simulation time 614633648 ps
CPU time 12.08 seconds
Started May 19 01:03:12 PM PDT 24
Finished May 19 01:03:25 PM PDT 24
Peak memory 217896 kb
Host smart-5cc2657e-c8b1-44db-885d-3e5e3896ad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940402875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2940402875
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2207712459
Short name T61
Test name
Test status
Simulation time 440468002 ps
CPU time 25.66 seconds
Started May 19 01:03:18 PM PDT 24
Finished May 19 01:03:44 PM PDT 24
Peak memory 284148 kb
Host smart-7f86b0d8-22a7-4754-95fc-3ff19bd17e5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207712459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2207712459
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.992320352
Short name T67
Test name
Test status
Simulation time 318401240 ps
CPU time 10.08 seconds
Started May 19 01:03:20 PM PDT 24
Finished May 19 01:03:31 PM PDT 24
Peak memory 226244 kb
Host smart-e7f5f035-56f6-4089-8e13-17a81c8bf060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992320352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.992320352
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2886886740
Short name T235
Test name
Test status
Simulation time 764860186 ps
CPU time 10.68 seconds
Started May 19 01:03:20 PM PDT 24
Finished May 19 01:03:31 PM PDT 24
Peak memory 217984 kb
Host smart-b51e0144-d27e-4b39-a176-beb418101133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886886740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2886886740
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.363663962
Short name T185
Test name
Test status
Simulation time 1672446460 ps
CPU time 12.9 seconds
Started May 19 01:03:22 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 218000 kb
Host smart-10246fb9-def6-4f69-b518-a7b55d2faa55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363663962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.363663962
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1725564062
Short name T863
Test name
Test status
Simulation time 1314596431 ps
CPU time 8.12 seconds
Started May 19 01:03:04 PM PDT 24
Finished May 19 01:03:12 PM PDT 24
Peak memory 218052 kb
Host smart-08533dad-09b5-4a03-984f-3a433469b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725564062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1725564062
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3035433945
Short name T778
Test name
Test status
Simulation time 18901300 ps
CPU time 1.7 seconds
Started May 19 01:03:06 PM PDT 24
Finished May 19 01:03:08 PM PDT 24
Peak memory 213524 kb
Host smart-bd9f853a-c3a2-4af9-bdda-61cb40eee3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035433945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3035433945
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.859399330
Short name T326
Test name
Test status
Simulation time 364144627 ps
CPU time 25.91 seconds
Started May 19 01:03:06 PM PDT 24
Finished May 19 01:03:32 PM PDT 24
Peak memory 250748 kb
Host smart-70571188-7a85-41da-b3ae-8ff830597fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859399330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.859399330
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1253423832
Short name T766
Test name
Test status
Simulation time 311669460 ps
CPU time 2.84 seconds
Started May 19 01:03:05 PM PDT 24
Finished May 19 01:03:08 PM PDT 24
Peak memory 226412 kb
Host smart-31f0bc48-1f09-4638-8b34-cb8d7551699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253423832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1253423832
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3016024624
Short name T170
Test name
Test status
Simulation time 17122541924 ps
CPU time 113.12 seconds
Started May 19 01:03:18 PM PDT 24
Finished May 19 01:05:12 PM PDT 24
Peak memory 274776 kb
Host smart-2926a118-b743-4feb-8a6c-31b5742c1003
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016024624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3016024624
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3028821147
Short name T697
Test name
Test status
Simulation time 17003350 ps
CPU time 0.96 seconds
Started May 19 01:03:06 PM PDT 24
Finished May 19 01:03:07 PM PDT 24
Peak memory 212588 kb
Host smart-7f412c6a-e30c-405f-a8fa-cf192309dcb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028821147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3028821147
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3565711221
Short name T614
Test name
Test status
Simulation time 33205442 ps
CPU time 1.06 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 209628 kb
Host smart-38cc20f8-c94f-4227-a45f-70b9ae7bb5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565711221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3565711221
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2735431746
Short name T56
Test name
Test status
Simulation time 282452069 ps
CPU time 12.27 seconds
Started May 19 01:06:03 PM PDT 24
Finished May 19 01:06:17 PM PDT 24
Peak memory 217976 kb
Host smart-e11a1d3f-33bf-4af3-a5cf-f1a211db8e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735431746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2735431746
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1611562149
Short name T665
Test name
Test status
Simulation time 156081684 ps
CPU time 1.17 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 209532 kb
Host smart-4b019906-cd93-4766-a512-0eba46283694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611562149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1611562149
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2091212379
Short name T363
Test name
Test status
Simulation time 244619712 ps
CPU time 3.34 seconds
Started May 19 01:06:03 PM PDT 24
Finished May 19 01:06:07 PM PDT 24
Peak memory 218140 kb
Host smart-5db75bde-eb1d-4583-9988-cfeb8f799470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091212379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2091212379
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1774179376
Short name T827
Test name
Test status
Simulation time 1444883900 ps
CPU time 17.4 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:21 PM PDT 24
Peak memory 218988 kb
Host smart-3eb7499b-7c24-4ac9-9410-2233fd990743
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774179376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1774179376
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1512022123
Short name T472
Test name
Test status
Simulation time 1910474816 ps
CPU time 13.29 seconds
Started May 19 01:06:03 PM PDT 24
Finished May 19 01:06:17 PM PDT 24
Peak memory 218060 kb
Host smart-4be4ce2c-cc4b-47bd-8635-e6935aa51c32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512022123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1512022123
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3957548417
Short name T429
Test name
Test status
Simulation time 1013600087 ps
CPU time 8.21 seconds
Started May 19 01:06:01 PM PDT 24
Finished May 19 01:06:10 PM PDT 24
Peak memory 217996 kb
Host smart-24f6448c-cef2-41de-a0c2-9f04b67c641d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957548417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3957548417
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3666728899
Short name T400
Test name
Test status
Simulation time 172860849 ps
CPU time 7.53 seconds
Started May 19 01:06:03 PM PDT 24
Finished May 19 01:06:11 PM PDT 24
Peak memory 218132 kb
Host smart-61c5d7dc-7bf3-4a8d-a736-9140d8e9c7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666728899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3666728899
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1553656433
Short name T390
Test name
Test status
Simulation time 164306193 ps
CPU time 2.64 seconds
Started May 19 01:06:03 PM PDT 24
Finished May 19 01:06:07 PM PDT 24
Peak memory 214048 kb
Host smart-55a5215c-14bb-4266-974e-ae45ca483709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553656433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1553656433
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.549945177
Short name T417
Test name
Test status
Simulation time 841716019 ps
CPU time 24.8 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 250896 kb
Host smart-7acab4cf-6bbb-4360-ab26-92a60a06a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549945177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.549945177
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.473407495
Short name T317
Test name
Test status
Simulation time 264072357 ps
CPU time 5.9 seconds
Started May 19 01:06:01 PM PDT 24
Finished May 19 01:06:07 PM PDT 24
Peak memory 244772 kb
Host smart-4cbfacd1-f944-4577-9421-46988bd8f2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473407495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.473407495
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.4105146820
Short name T613
Test name
Test status
Simulation time 1996629919 ps
CPU time 30.73 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:33 PM PDT 24
Peak memory 226132 kb
Host smart-fd9c582d-2bf0-431d-a158-62e0c519e7ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105146820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.4105146820
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.111497566
Short name T862
Test name
Test status
Simulation time 51071280 ps
CPU time 1.02 seconds
Started May 19 01:06:01 PM PDT 24
Finished May 19 01:06:03 PM PDT 24
Peak memory 211464 kb
Host smart-bf47aa08-4d31-4356-b52d-563eec8919ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111497566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.111497566
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1412820658
Short name T73
Test name
Test status
Simulation time 36764795 ps
CPU time 0.94 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:15 PM PDT 24
Peak memory 209636 kb
Host smart-ca923de5-2277-43f0-934f-4b79aa682c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412820658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1412820658
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.824241064
Short name T815
Test name
Test status
Simulation time 377270429 ps
CPU time 18.2 seconds
Started May 19 01:06:05 PM PDT 24
Finished May 19 01:06:24 PM PDT 24
Peak memory 218372 kb
Host smart-77b68b98-0dce-40cf-a133-14e2a8486ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824241064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.824241064
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1374392976
Short name T630
Test name
Test status
Simulation time 1362751109 ps
CPU time 12.61 seconds
Started May 19 01:06:03 PM PDT 24
Finished May 19 01:06:17 PM PDT 24
Peak memory 217300 kb
Host smart-9d02432e-65b2-4f89-bb76-9ee24e00d558
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374392976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1374392976
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.238667216
Short name T485
Test name
Test status
Simulation time 134579464 ps
CPU time 2.36 seconds
Started May 19 01:06:05 PM PDT 24
Finished May 19 01:06:08 PM PDT 24
Peak memory 218052 kb
Host smart-6a447ece-5a05-471c-a915-44e50debea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238667216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.238667216
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3203702204
Short name T430
Test name
Test status
Simulation time 327833507 ps
CPU time 10.13 seconds
Started May 19 01:06:05 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 226008 kb
Host smart-84e19e5e-6c3e-4aff-a32b-a928c65d9663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203702204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3203702204
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1573721992
Short name T677
Test name
Test status
Simulation time 177317438 ps
CPU time 8.54 seconds
Started May 19 01:06:07 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 217940 kb
Host smart-98c26f00-cce8-4997-bc62-46b237691c21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573721992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1573721992
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2863467048
Short name T542
Test name
Test status
Simulation time 1757559207 ps
CPU time 11.03 seconds
Started May 19 01:06:05 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 218136 kb
Host smart-488abd65-da85-4f05-bccb-72a373340206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863467048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2863467048
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2518476667
Short name T308
Test name
Test status
Simulation time 116115692 ps
CPU time 2.83 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:06 PM PDT 24
Peak memory 217792 kb
Host smart-1e068036-34b1-4314-ab9d-b55a0503adbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518476667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2518476667
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.881911575
Short name T489
Test name
Test status
Simulation time 620244371 ps
CPU time 28.71 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:32 PM PDT 24
Peak memory 250984 kb
Host smart-9d3c5b46-326a-40b1-9add-049e4f95a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881911575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.881911575
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.5260598
Short name T368
Test name
Test status
Simulation time 199216001 ps
CPU time 8.51 seconds
Started May 19 01:06:11 PM PDT 24
Finished May 19 01:06:20 PM PDT 24
Peak memory 250684 kb
Host smart-418ffc19-38c4-428e-b408-a954f04996a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5260598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.5260598
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2158544008
Short name T102
Test name
Test status
Simulation time 137125877997 ps
CPU time 711.62 seconds
Started May 19 01:06:11 PM PDT 24
Finished May 19 01:18:04 PM PDT 24
Peak memory 373084 kb
Host smart-b7d768d5-9abe-4d08-acc4-1f64a2daa50c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2158544008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2158544008
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2355589365
Short name T656
Test name
Test status
Simulation time 16919043 ps
CPU time 0.99 seconds
Started May 19 01:06:02 PM PDT 24
Finished May 19 01:06:04 PM PDT 24
Peak memory 212624 kb
Host smart-84397188-4204-4a32-8121-81f25d7f11b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355589365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2355589365
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1846947405
Short name T89
Test name
Test status
Simulation time 14977547 ps
CPU time 0.99 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:15 PM PDT 24
Peak memory 209624 kb
Host smart-3b6ed171-34bc-468b-ae2d-a35ec61b3c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846947405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1846947405
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3217439807
Short name T745
Test name
Test status
Simulation time 460063209 ps
CPU time 14.36 seconds
Started May 19 01:06:11 PM PDT 24
Finished May 19 01:06:27 PM PDT 24
Peak memory 217972 kb
Host smart-783c9f3c-3b93-407e-90f9-2d229b05e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217439807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3217439807
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.504862218
Short name T353
Test name
Test status
Simulation time 1528416179 ps
CPU time 4.03 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:19 PM PDT 24
Peak memory 209568 kb
Host smart-5629f706-6726-4f19-9dff-e2605f82cf76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504862218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.504862218
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.610040873
Short name T350
Test name
Test status
Simulation time 270291508 ps
CPU time 3.33 seconds
Started May 19 01:06:11 PM PDT 24
Finished May 19 01:06:15 PM PDT 24
Peak memory 218128 kb
Host smart-c366ddd9-ef14-4d7d-ae0c-394cbfe11891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610040873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.610040873
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.472993467
Short name T590
Test name
Test status
Simulation time 3479971549 ps
CPU time 15.77 seconds
Started May 19 01:06:04 PM PDT 24
Finished May 19 01:06:21 PM PDT 24
Peak memory 218924 kb
Host smart-15ca6908-5a8e-4272-a65a-c999a2904ef2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472993467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.472993467
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3795126732
Short name T462
Test name
Test status
Simulation time 884064161 ps
CPU time 9.51 seconds
Started May 19 01:06:04 PM PDT 24
Finished May 19 01:06:15 PM PDT 24
Peak memory 218032 kb
Host smart-e4929a52-3b78-4fe3-a24b-9fc73e4c9725
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795126732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3795126732
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.426495935
Short name T343
Test name
Test status
Simulation time 787233441 ps
CPU time 13.63 seconds
Started May 19 01:06:06 PM PDT 24
Finished May 19 01:06:20 PM PDT 24
Peak memory 218164 kb
Host smart-ca7a01f4-8e8a-4d01-9a1e-312fb2747577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426495935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.426495935
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.865701443
Short name T70
Test name
Test status
Simulation time 194658575 ps
CPU time 1.28 seconds
Started May 19 01:06:06 PM PDT 24
Finished May 19 01:06:08 PM PDT 24
Peak memory 213460 kb
Host smart-fc348798-a3fa-4408-ae06-954506abd192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865701443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.865701443
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4165840593
Short name T603
Test name
Test status
Simulation time 868708164 ps
CPU time 16.55 seconds
Started May 19 01:06:06 PM PDT 24
Finished May 19 01:06:23 PM PDT 24
Peak memory 250952 kb
Host smart-96ae778d-1b7a-40e2-a9cc-00efa9ac0495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165840593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4165840593
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3341983239
Short name T547
Test name
Test status
Simulation time 49664294 ps
CPU time 5.66 seconds
Started May 19 01:06:05 PM PDT 24
Finished May 19 01:06:11 PM PDT 24
Peak memory 246724 kb
Host smart-bbc13644-7c15-4412-a7d6-3797de9c921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341983239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3341983239
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3701774289
Short name T171
Test name
Test status
Simulation time 19237034672 ps
CPU time 334.9 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:11:49 PM PDT 24
Peak memory 267444 kb
Host smart-412abd90-d059-42fa-a85b-2aa2b9f7de9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701774289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3701774289
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2895432493
Short name T442
Test name
Test status
Simulation time 78336114 ps
CPU time 0.93 seconds
Started May 19 01:06:07 PM PDT 24
Finished May 19 01:06:08 PM PDT 24
Peak memory 208548 kb
Host smart-25ab6336-77e4-45d1-8e50-a85189c248a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895432493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2895432493
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3315598421
Short name T74
Test name
Test status
Simulation time 21108434 ps
CPU time 0.96 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 209564 kb
Host smart-2af4e764-7002-4f2a-9e2d-00a12823cdef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315598421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3315598421
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1398432255
Short name T168
Test name
Test status
Simulation time 456960402 ps
CPU time 14.51 seconds
Started May 19 01:06:15 PM PDT 24
Finished May 19 01:06:30 PM PDT 24
Peak memory 217980 kb
Host smart-9032d2a2-5fda-406c-b824-15ff54df2440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398432255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1398432255
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2747367851
Short name T194
Test name
Test status
Simulation time 56716509 ps
CPU time 1.43 seconds
Started May 19 01:06:14 PM PDT 24
Finished May 19 01:06:17 PM PDT 24
Peak memory 216752 kb
Host smart-4569af87-01a9-4b4a-801a-652b8c24da90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747367851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2747367851
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.920376252
Short name T532
Test name
Test status
Simulation time 40148359 ps
CPU time 1.7 seconds
Started May 19 01:06:11 PM PDT 24
Finished May 19 01:06:13 PM PDT 24
Peak memory 218040 kb
Host smart-69f2dda2-c7f9-4f94-9edb-1c4c78dc9023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920376252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.920376252
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.366209109
Short name T299
Test name
Test status
Simulation time 1189005708 ps
CPU time 7.97 seconds
Started May 19 01:06:14 PM PDT 24
Finished May 19 01:06:23 PM PDT 24
Peak memory 226168 kb
Host smart-5b81d8f1-46bc-47ae-816f-044d82e3a1ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366209109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.366209109
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3747450275
Short name T647
Test name
Test status
Simulation time 224785762 ps
CPU time 7.67 seconds
Started May 19 01:06:12 PM PDT 24
Finished May 19 01:06:21 PM PDT 24
Peak memory 218288 kb
Host smart-a5596f2f-7f44-4f52-afc6-7b6c6df76ca6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747450275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3747450275
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1655458303
Short name T741
Test name
Test status
Simulation time 2700875881 ps
CPU time 10.7 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:25 PM PDT 24
Peak memory 217980 kb
Host smart-94ddd4ca-c204-4ac9-9fed-e43d9a0ed03d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655458303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1655458303
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.4169064655
Short name T439
Test name
Test status
Simulation time 1492645682 ps
CPU time 9.29 seconds
Started May 19 01:06:11 PM PDT 24
Finished May 19 01:06:21 PM PDT 24
Peak memory 218076 kb
Host smart-0b4dfc51-d54f-4f34-8130-6841017c8317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169064655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.4169064655
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.766118041
Short name T768
Test name
Test status
Simulation time 140537501 ps
CPU time 2.71 seconds
Started May 19 01:06:22 PM PDT 24
Finished May 19 01:06:25 PM PDT 24
Peak memory 214304 kb
Host smart-e660992c-8868-4685-bd5a-9fdf50b10d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766118041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.766118041
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.10245119
Short name T796
Test name
Test status
Simulation time 463939873 ps
CPU time 25.91 seconds
Started May 19 01:06:21 PM PDT 24
Finished May 19 01:06:48 PM PDT 24
Peak memory 250956 kb
Host smart-97903861-21de-48bf-9011-0b61f08597c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10245119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.10245119
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2666154538
Short name T85
Test name
Test status
Simulation time 774108248 ps
CPU time 7.27 seconds
Started May 19 01:06:14 PM PDT 24
Finished May 19 01:06:22 PM PDT 24
Peak memory 250736 kb
Host smart-d7188d55-999b-478b-93e0-0f6ca02e7c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666154538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2666154538
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1164191517
Short name T757
Test name
Test status
Simulation time 55588515495 ps
CPU time 480.35 seconds
Started May 19 01:06:14 PM PDT 24
Finished May 19 01:14:15 PM PDT 24
Peak memory 269944 kb
Host smart-571324dd-0c8f-4372-8c47-f697009aaa66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164191517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1164191517
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3700501619
Short name T72
Test name
Test status
Simulation time 71980609 ps
CPU time 0.94 seconds
Started May 19 01:06:14 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 212080 kb
Host smart-10c18c91-1ceb-40a9-9da4-1eaccb7493d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700501619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3700501619
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1671419575
Short name T536
Test name
Test status
Simulation time 69797044 ps
CPU time 1.12 seconds
Started May 19 01:06:17 PM PDT 24
Finished May 19 01:06:19 PM PDT 24
Peak memory 209576 kb
Host smart-0cc5f08c-58d5-483b-9809-e49e07c6bade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671419575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1671419575
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2178675918
Short name T493
Test name
Test status
Simulation time 1244860510 ps
CPU time 10.94 seconds
Started May 19 01:06:15 PM PDT 24
Finished May 19 01:06:27 PM PDT 24
Peak memory 218036 kb
Host smart-7c703d6d-79b3-4092-b81a-f405fe8bd2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178675918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2178675918
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.136810917
Short name T814
Test name
Test status
Simulation time 750353818 ps
CPU time 4.47 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:18 PM PDT 24
Peak memory 209512 kb
Host smart-13480109-919c-4b86-8511-dea5c4cf6a09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136810917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.136810917
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2116427666
Short name T696
Test name
Test status
Simulation time 122185474 ps
CPU time 1.92 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 218064 kb
Host smart-970b1739-be88-4140-9d7e-2c58f019dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116427666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2116427666
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3084890785
Short name T764
Test name
Test status
Simulation time 1093030054 ps
CPU time 12.67 seconds
Started May 19 01:06:12 PM PDT 24
Finished May 19 01:06:26 PM PDT 24
Peak memory 225988 kb
Host smart-ae414407-3ee0-4356-8a83-9081461ec27c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084890785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3084890785
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1702249483
Short name T301
Test name
Test status
Simulation time 1080116408 ps
CPU time 10.1 seconds
Started May 19 01:06:20 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 217980 kb
Host smart-840e49db-6f22-40e2-a0b4-ccc17e62f913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702249483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1702249483
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3007014042
Short name T466
Test name
Test status
Simulation time 277819043 ps
CPU time 7.12 seconds
Started May 19 01:06:16 PM PDT 24
Finished May 19 01:06:24 PM PDT 24
Peak memory 218016 kb
Host smart-a0d13262-7dcf-4519-99bf-df1cf20165a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007014042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3007014042
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1667614101
Short name T287
Test name
Test status
Simulation time 346694862 ps
CPU time 7.87 seconds
Started May 19 01:06:12 PM PDT 24
Finished May 19 01:06:21 PM PDT 24
Peak memory 218092 kb
Host smart-72593e5d-c94d-44f5-9d48-cbdf76aa7db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667614101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1667614101
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.119985014
Short name T178
Test name
Test status
Simulation time 30214759 ps
CPU time 2.2 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:17 PM PDT 24
Peak memory 214124 kb
Host smart-1eededdf-e91d-45d7-bcac-214e15c51c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119985014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.119985014
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.933997044
Short name T573
Test name
Test status
Simulation time 576981050 ps
CPU time 25.42 seconds
Started May 19 01:06:14 PM PDT 24
Finished May 19 01:06:40 PM PDT 24
Peak memory 250740 kb
Host smart-0873d063-e301-42fb-8abb-9ea9da6406e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933997044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.933997044
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.883229671
Short name T805
Test name
Test status
Simulation time 381251426 ps
CPU time 3.7 seconds
Started May 19 01:06:12 PM PDT 24
Finished May 19 01:06:17 PM PDT 24
Peak memory 226260 kb
Host smart-112980e8-76c4-49e4-a561-00c17280b9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883229671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.883229671
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2166583826
Short name T377
Test name
Test status
Simulation time 3695079819 ps
CPU time 90.42 seconds
Started May 19 01:06:17 PM PDT 24
Finished May 19 01:07:48 PM PDT 24
Peak memory 283676 kb
Host smart-185d6f4e-8059-4a65-b14f-b3a693d3b0f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166583826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2166583826
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1454934582
Short name T57
Test name
Test status
Simulation time 65386236622 ps
CPU time 374.55 seconds
Started May 19 01:06:18 PM PDT 24
Finished May 19 01:12:33 PM PDT 24
Peak memory 276888 kb
Host smart-a3143b03-2095-4da2-99e1-c58952b30fe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1454934582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1454934582
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.253296468
Short name T40
Test name
Test status
Simulation time 35416590 ps
CPU time 0.9 seconds
Started May 19 01:06:13 PM PDT 24
Finished May 19 01:06:16 PM PDT 24
Peak memory 208556 kb
Host smart-71e21f42-00ec-4a7d-888f-067a5a36d2a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253296468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.253296468
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3731991755
Short name T249
Test name
Test status
Simulation time 74820886 ps
CPU time 1.35 seconds
Started May 19 01:06:18 PM PDT 24
Finished May 19 01:06:19 PM PDT 24
Peak memory 209644 kb
Host smart-d6353b27-ee5c-4096-a692-7bf1349aa753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731991755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3731991755
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2526878235
Short name T484
Test name
Test status
Simulation time 318590502 ps
CPU time 13.46 seconds
Started May 19 01:06:31 PM PDT 24
Finished May 19 01:06:45 PM PDT 24
Peak memory 217904 kb
Host smart-66379402-5fe8-4ef7-bcf7-0bd875ab059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526878235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2526878235
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.331553096
Short name T477
Test name
Test status
Simulation time 104802005 ps
CPU time 2.01 seconds
Started May 19 01:06:19 PM PDT 24
Finished May 19 01:06:22 PM PDT 24
Peak memory 217128 kb
Host smart-13669760-5633-43ce-84ca-dca3e57272a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331553096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.331553096
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.166567621
Short name T273
Test name
Test status
Simulation time 107504896 ps
CPU time 3.31 seconds
Started May 19 01:06:27 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 218052 kb
Host smart-d7e439fa-350c-4185-abb5-8e8b8a89a106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166567621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.166567621
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1433082538
Short name T643
Test name
Test status
Simulation time 2276815063 ps
CPU time 17.17 seconds
Started May 19 01:06:26 PM PDT 24
Finished May 19 01:06:44 PM PDT 24
Peak memory 218200 kb
Host smart-e0c52efc-ed27-4dbc-bddd-1f78b7ea2654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433082538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1433082538
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1918839333
Short name T680
Test name
Test status
Simulation time 1350627123 ps
CPU time 11.97 seconds
Started May 19 01:06:31 PM PDT 24
Finished May 19 01:06:44 PM PDT 24
Peak memory 217848 kb
Host smart-8e6a0633-8b64-4230-83d6-c7152c46f625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918839333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1918839333
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.739750297
Short name T382
Test name
Test status
Simulation time 299269062 ps
CPU time 11 seconds
Started May 19 01:06:17 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 217944 kb
Host smart-ae1f2cf5-2868-49e9-a3d9-894a8df8c742
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739750297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.739750297
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.288118885
Short name T366
Test name
Test status
Simulation time 1121741328 ps
CPU time 10.28 seconds
Started May 19 01:06:17 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 217980 kb
Host smart-96298d49-740e-436e-b8fa-2013c3cb1955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288118885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.288118885
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4145152515
Short name T832
Test name
Test status
Simulation time 84544908 ps
CPU time 1.69 seconds
Started May 19 01:06:32 PM PDT 24
Finished May 19 01:06:34 PM PDT 24
Peak memory 213864 kb
Host smart-79f4c4ff-302f-4d1c-99be-1dca891f0bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145152515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4145152515
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4108427366
Short name T20
Test name
Test status
Simulation time 392786399 ps
CPU time 22.14 seconds
Started May 19 01:06:15 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 251020 kb
Host smart-f8fd362a-89eb-45a4-a453-784456e85b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108427366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4108427366
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3739628844
Short name T597
Test name
Test status
Simulation time 96592539 ps
CPU time 9.31 seconds
Started May 19 01:06:18 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 250928 kb
Host smart-d12bfb23-afc7-4294-ab5e-65365e48024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739628844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3739628844
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.490823965
Short name T190
Test name
Test status
Simulation time 9477221899 ps
CPU time 55.92 seconds
Started May 19 01:06:32 PM PDT 24
Finished May 19 01:07:29 PM PDT 24
Peak memory 250696 kb
Host smart-c258bc56-6bfb-4622-956c-66c08b35f83e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490823965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.490823965
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.16426852
Short name T37
Test name
Test status
Simulation time 51493137 ps
CPU time 0.86 seconds
Started May 19 01:06:19 PM PDT 24
Finished May 19 01:06:21 PM PDT 24
Peak memory 211664 kb
Host smart-22f5c1af-771a-4e78-83fd-0272dbc46254
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctr
l_volatile_unlock_smoke.16426852
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.286261217
Short name T756
Test name
Test status
Simulation time 17756611 ps
CPU time 1.12 seconds
Started May 19 01:06:22 PM PDT 24
Finished May 19 01:06:24 PM PDT 24
Peak memory 209580 kb
Host smart-43d3785b-c462-4ec4-9524-6da02012ed0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286261217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.286261217
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2585038299
Short name T217
Test name
Test status
Simulation time 3010379246 ps
CPU time 10.95 seconds
Started May 19 01:06:18 PM PDT 24
Finished May 19 01:06:30 PM PDT 24
Peak memory 218064 kb
Host smart-bf1b7fa9-e158-4d02-84d3-f5b100e52add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585038299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2585038299
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1896531281
Short name T25
Test name
Test status
Simulation time 410901152 ps
CPU time 5.46 seconds
Started May 19 01:06:19 PM PDT 24
Finished May 19 01:06:25 PM PDT 24
Peak memory 209828 kb
Host smart-22c7d93d-0379-4a38-873f-5fa226de295d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896531281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1896531281
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3838922349
Short name T324
Test name
Test status
Simulation time 166689317 ps
CPU time 3.34 seconds
Started May 19 01:06:26 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 218052 kb
Host smart-cb35532d-22b1-4120-90c0-eb8fccd31225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838922349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3838922349
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.4255189863
Short name T763
Test name
Test status
Simulation time 1399139517 ps
CPU time 12.77 seconds
Started May 19 01:06:20 PM PDT 24
Finished May 19 01:06:33 PM PDT 24
Peak memory 225720 kb
Host smart-b5ed301f-b9d8-4f55-ad64-dc7375f43c5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255189863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.4255189863
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.75831985
Short name T245
Test name
Test status
Simulation time 701400423 ps
CPU time 14.89 seconds
Started May 19 01:06:17 PM PDT 24
Finished May 19 01:06:32 PM PDT 24
Peak memory 217952 kb
Host smart-4a7fbd5f-5b34-4948-a584-ce24064ae425
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75831985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_dig
est.75831985
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2126000192
Short name T762
Test name
Test status
Simulation time 1975579304 ps
CPU time 11.68 seconds
Started May 19 01:06:18 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 217960 kb
Host smart-ff41ebf0-b703-4115-ab4b-d1145611ab98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126000192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2126000192
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3341762967
Short name T657
Test name
Test status
Simulation time 4933427835 ps
CPU time 10.84 seconds
Started May 19 01:06:27 PM PDT 24
Finished May 19 01:06:39 PM PDT 24
Peak memory 218244 kb
Host smart-b35cf6b8-5ff5-40ed-97ef-897db964355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341762967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3341762967
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2858063302
Short name T148
Test name
Test status
Simulation time 632594769 ps
CPU time 2.7 seconds
Started May 19 01:06:17 PM PDT 24
Finished May 19 01:06:20 PM PDT 24
Peak memory 214100 kb
Host smart-7c8ffe1e-d184-4a68-96d6-efd27ad757aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858063302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2858063302
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1937283375
Short name T775
Test name
Test status
Simulation time 608510949 ps
CPU time 26.61 seconds
Started May 19 01:06:27 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 250800 kb
Host smart-bcb396f4-71cf-464c-927a-92bd1eed1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937283375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1937283375
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1267342553
Short name T508
Test name
Test status
Simulation time 124233646 ps
CPU time 6.7 seconds
Started May 19 01:06:31 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 246068 kb
Host smart-8bc8d21d-96ef-4f48-ae76-1dc6361d68c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267342553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1267342553
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2755252540
Short name T150
Test name
Test status
Simulation time 1499629052 ps
CPU time 30.56 seconds
Started May 19 01:06:19 PM PDT 24
Finished May 19 01:06:50 PM PDT 24
Peak memory 250900 kb
Host smart-3a9741ee-b9bc-47b0-9e5b-44c63e1cf0b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755252540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2755252540
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1079012417
Short name T90
Test name
Test status
Simulation time 54985827 ps
CPU time 1.09 seconds
Started May 19 01:06:22 PM PDT 24
Finished May 19 01:06:24 PM PDT 24
Peak memory 209584 kb
Host smart-0ac5fd24-19c0-401b-bfc0-e1c0860c41ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079012417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1079012417
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2156264831
Short name T179
Test name
Test status
Simulation time 3185896321 ps
CPU time 15.71 seconds
Started May 19 01:06:22 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 218176 kb
Host smart-b9c42724-fa86-458b-874e-0299e834113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156264831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2156264831
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.85804618
Short name T454
Test name
Test status
Simulation time 174706056 ps
CPU time 5.11 seconds
Started May 19 01:06:22 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 209808 kb
Host smart-e65ee176-baa1-4111-9a7c-f17b583de1e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85804618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.85804618
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2722465475
Short name T450
Test name
Test status
Simulation time 123226112 ps
CPU time 2.11 seconds
Started May 19 01:06:26 PM PDT 24
Finished May 19 01:06:29 PM PDT 24
Peak memory 218120 kb
Host smart-71062436-2bd8-4883-86fc-8072f379cf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722465475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2722465475
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3474120239
Short name T412
Test name
Test status
Simulation time 285493427 ps
CPU time 14.4 seconds
Started May 19 01:06:24 PM PDT 24
Finished May 19 01:06:39 PM PDT 24
Peak memory 219008 kb
Host smart-c8c642fc-56d0-403d-85a1-8101e09de719
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474120239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3474120239
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2043027933
Short name T370
Test name
Test status
Simulation time 1619086831 ps
CPU time 16.21 seconds
Started May 19 01:06:24 PM PDT 24
Finished May 19 01:06:41 PM PDT 24
Peak memory 217976 kb
Host smart-901e013d-1191-4b40-ab9e-750ef93ab004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043027933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2043027933
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2612801833
Short name T248
Test name
Test status
Simulation time 351706894 ps
CPU time 13.52 seconds
Started May 19 01:06:23 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 217948 kb
Host smart-c29db0e6-37cd-4986-97f8-3b0b0267f788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612801833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2612801833
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4259263215
Short name T449
Test name
Test status
Simulation time 1409747629 ps
CPU time 11.86 seconds
Started May 19 01:06:24 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 218020 kb
Host smart-87a22d56-add8-49ff-9f0b-8e903ffd6065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259263215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4259263215
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3547504227
Short name T522
Test name
Test status
Simulation time 59165447 ps
CPU time 1.25 seconds
Started May 19 01:06:23 PM PDT 24
Finished May 19 01:06:25 PM PDT 24
Peak memory 213412 kb
Host smart-ff9c1908-b52c-4333-b6db-9a612e196379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547504227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3547504227
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1252825913
Short name T837
Test name
Test status
Simulation time 267384542 ps
CPU time 23.35 seconds
Started May 19 01:06:25 PM PDT 24
Finished May 19 01:06:49 PM PDT 24
Peak memory 250936 kb
Host smart-90bfd3ab-1ca1-48d1-b181-ccaac9d98959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252825913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1252825913
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2369159790
Short name T184
Test name
Test status
Simulation time 748548032 ps
CPU time 7.31 seconds
Started May 19 01:06:21 PM PDT 24
Finished May 19 01:06:29 PM PDT 24
Peak memory 250932 kb
Host smart-f0d90013-8e52-4d7a-affc-749907fe4261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369159790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2369159790
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.639968076
Short name T703
Test name
Test status
Simulation time 17587198657 ps
CPU time 238.9 seconds
Started May 19 01:06:23 PM PDT 24
Finished May 19 01:10:23 PM PDT 24
Peak memory 316492 kb
Host smart-16132c49-8efd-4181-927e-ba592e2b7e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639968076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.639968076
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3874286332
Short name T519
Test name
Test status
Simulation time 21830958 ps
CPU time 0.79 seconds
Started May 19 01:06:22 PM PDT 24
Finished May 19 01:06:24 PM PDT 24
Peak memory 208488 kb
Host smart-71628645-6191-474a-8a3e-39ad3dd30bdc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874286332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3874286332
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2792015263
Short name T467
Test name
Test status
Simulation time 18180282 ps
CPU time 1.18 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 209656 kb
Host smart-c9904e24-204b-4ef5-a3e9-9e3338be34f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792015263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2792015263
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.141899044
Short name T552
Test name
Test status
Simulation time 327647900 ps
CPU time 14.23 seconds
Started May 19 01:06:22 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 217948 kb
Host smart-a81c215a-d410-4f54-8d34-33da6006a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141899044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.141899044
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1841414294
Short name T506
Test name
Test status
Simulation time 596616680 ps
CPU time 4.07 seconds
Started May 19 01:06:23 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 216880 kb
Host smart-9a32a87e-d8e6-4e5c-969c-01b29753d133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841414294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1841414294
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1206851315
Short name T285
Test name
Test status
Simulation time 30722253 ps
CPU time 2.03 seconds
Started May 19 01:06:23 PM PDT 24
Finished May 19 01:06:25 PM PDT 24
Peak memory 218032 kb
Host smart-1c434a5b-48d1-45fa-ae52-8643f27ded73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206851315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1206851315
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.152223433
Short name T599
Test name
Test status
Simulation time 349955273 ps
CPU time 10.01 seconds
Started May 19 01:06:24 PM PDT 24
Finished May 19 01:06:35 PM PDT 24
Peak memory 218064 kb
Host smart-1da75b19-bce2-4933-a335-42d0cb047045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152223433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.152223433
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.798568449
Short name T258
Test name
Test status
Simulation time 659419186 ps
CPU time 25.13 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 217984 kb
Host smart-2966eccf-65cd-4a2e-973e-c7abd020eb5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798568449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.798568449
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1778348084
Short name T726
Test name
Test status
Simulation time 906557255 ps
CPU time 9.14 seconds
Started May 19 01:06:24 PM PDT 24
Finished May 19 01:06:34 PM PDT 24
Peak memory 218008 kb
Host smart-8ae0c98c-2ee4-4d50-a40e-7a9d9ac2616e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778348084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1778348084
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4061001482
Short name T818
Test name
Test status
Simulation time 729283963 ps
CPU time 8.17 seconds
Started May 19 01:06:24 PM PDT 24
Finished May 19 01:06:33 PM PDT 24
Peak memory 218120 kb
Host smart-da300e14-b733-40be-a0df-8ac7fb0a43c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061001482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4061001482
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.390531176
Short name T483
Test name
Test status
Simulation time 106291456 ps
CPU time 3.18 seconds
Started May 19 01:06:23 PM PDT 24
Finished May 19 01:06:27 PM PDT 24
Peak memory 214548 kb
Host smart-96ca1aba-2692-4f6a-a7ab-0fdfd7453633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390531176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.390531176
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3800416683
Short name T587
Test name
Test status
Simulation time 1110086151 ps
CPU time 24.81 seconds
Started May 19 01:06:23 PM PDT 24
Finished May 19 01:06:49 PM PDT 24
Peak memory 250964 kb
Host smart-e7b4916d-444e-47fc-ad7b-bc2ff7b46467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800416683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3800416683
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2594247899
Short name T356
Test name
Test status
Simulation time 93575681 ps
CPU time 9.13 seconds
Started May 19 01:06:24 PM PDT 24
Finished May 19 01:06:34 PM PDT 24
Peak memory 250956 kb
Host smart-d8f8a627-70d5-407a-8820-2c03e49ebbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594247899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2594247899
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3629189705
Short name T418
Test name
Test status
Simulation time 26728349362 ps
CPU time 418.3 seconds
Started May 19 01:06:30 PM PDT 24
Finished May 19 01:13:30 PM PDT 24
Peak memory 250936 kb
Host smart-04b2fdba-9415-4b53-b236-3bbb37fa92be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629189705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3629189705
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3970875847
Short name T621
Test name
Test status
Simulation time 13037159 ps
CPU time 0.96 seconds
Started May 19 01:06:25 PM PDT 24
Finished May 19 01:06:26 PM PDT 24
Peak memory 208640 kb
Host smart-5dff7012-55f6-4693-ba78-b95e5570c732
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970875847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3970875847
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.563048799
Short name T562
Test name
Test status
Simulation time 55997485 ps
CPU time 1.01 seconds
Started May 19 01:06:30 PM PDT 24
Finished May 19 01:06:32 PM PDT 24
Peak memory 209664 kb
Host smart-bd289da1-fad3-4ab4-8a50-13da1ee6dc40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563048799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.563048799
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1790228330
Short name T704
Test name
Test status
Simulation time 1047886679 ps
CPU time 11.98 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 218084 kb
Host smart-2d68f138-4aab-4238-816e-fb8cdc3bae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790228330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1790228330
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2552541442
Short name T196
Test name
Test status
Simulation time 1379784999 ps
CPU time 9.94 seconds
Started May 19 01:06:30 PM PDT 24
Finished May 19 01:06:41 PM PDT 24
Peak memory 209548 kb
Host smart-2b5197b5-6757-452f-9993-bed255308f6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552541442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2552541442
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1290509934
Short name T345
Test name
Test status
Simulation time 56024035 ps
CPU time 3.18 seconds
Started May 19 01:06:27 PM PDT 24
Finished May 19 01:06:32 PM PDT 24
Peak memory 218052 kb
Host smart-904c98f0-fdf0-470d-b703-68b692b2f296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290509934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1290509934
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4273405253
Short name T383
Test name
Test status
Simulation time 258468935 ps
CPU time 11.62 seconds
Started May 19 01:06:28 PM PDT 24
Finished May 19 01:06:41 PM PDT 24
Peak memory 226084 kb
Host smart-3cf954e7-ccc4-4a13-9e66-80cab5fd5db7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273405253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4273405253
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1276627203
Short name T800
Test name
Test status
Simulation time 1008004356 ps
CPU time 11.63 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 218020 kb
Host smart-71b50b36-d7cd-49c1-a10b-ba15fb565a07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276627203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1276627203
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1510246599
Short name T367
Test name
Test status
Simulation time 436529187 ps
CPU time 8.1 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 218000 kb
Host smart-3c181954-b71d-4dce-96ea-05eae948b0b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510246599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1510246599
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.584825436
Short name T322
Test name
Test status
Simulation time 515428676 ps
CPU time 8.39 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:39 PM PDT 24
Peak memory 218176 kb
Host smart-91340b60-4f8e-48b3-8af1-6d92b65b1a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584825436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.584825436
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2571099966
Short name T80
Test name
Test status
Simulation time 48538069 ps
CPU time 2.66 seconds
Started May 19 01:06:27 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 214580 kb
Host smart-cc884dae-cdd5-41c7-81dc-4ec946559d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571099966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2571099966
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.494505752
Short name T722
Test name
Test status
Simulation time 922052635 ps
CPU time 28.14 seconds
Started May 19 01:06:27 PM PDT 24
Finished May 19 01:06:56 PM PDT 24
Peak memory 250936 kb
Host smart-87cdf32a-c8fc-4cd7-aa72-e210365687cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494505752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.494505752
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2222317081
Short name T291
Test name
Test status
Simulation time 305518815 ps
CPU time 7.37 seconds
Started May 19 01:06:28 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 250808 kb
Host smart-b7bd64dd-e796-42da-a243-fefb5f0d8730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222317081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2222317081
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.77703805
Short name T77
Test name
Test status
Simulation time 6875744538 ps
CPU time 106.7 seconds
Started May 19 01:06:33 PM PDT 24
Finished May 19 01:08:22 PM PDT 24
Peak memory 250804 kb
Host smart-8ebb9d88-3fb7-4445-bed7-9413a8470eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77703805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.lc_ctrl_stress_all.77703805
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3835375525
Short name T140
Test name
Test status
Simulation time 70311356471 ps
CPU time 371.94 seconds
Started May 19 01:06:28 PM PDT 24
Finished May 19 01:12:41 PM PDT 24
Peak memory 496888 kb
Host smart-1e9d6399-4684-43d9-9ce3-aa72cc9b7631
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3835375525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3835375525
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3386928223
Short name T247
Test name
Test status
Simulation time 15843503 ps
CPU time 0.96 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 211392 kb
Host smart-e6796228-89d9-43d6-a5fa-136ee8a3cd41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386928223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3386928223
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.533508673
Short name T853
Test name
Test status
Simulation time 29675567 ps
CPU time 1.3 seconds
Started May 19 01:03:30 PM PDT 24
Finished May 19 01:03:32 PM PDT 24
Peak memory 209620 kb
Host smart-4e3cc90b-ca77-44ec-b77c-ba5c361fe84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533508673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.533508673
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1662694797
Short name T509
Test name
Test status
Simulation time 28570424 ps
CPU time 0.89 seconds
Started May 19 01:03:24 PM PDT 24
Finished May 19 01:03:26 PM PDT 24
Peak memory 209540 kb
Host smart-032a2c78-a71b-4e36-b2bc-7798fd3801b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662694797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1662694797
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.707921480
Short name T750
Test name
Test status
Simulation time 437530595 ps
CPU time 9.81 seconds
Started May 19 01:03:22 PM PDT 24
Finished May 19 01:03:33 PM PDT 24
Peak memory 218056 kb
Host smart-21b3aeef-4773-47bb-bd37-90e4dbbb0a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707921480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.707921480
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.675648019
Short name T8
Test name
Test status
Simulation time 442418950 ps
CPU time 11.33 seconds
Started May 19 01:03:22 PM PDT 24
Finished May 19 01:03:34 PM PDT 24
Peak memory 217040 kb
Host smart-913f2ef9-b3a5-47f4-a342-2c3a243be2ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675648019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.675648019
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1128346308
Short name T654
Test name
Test status
Simulation time 11584764928 ps
CPU time 124.44 seconds
Started May 19 01:03:26 PM PDT 24
Finished May 19 01:05:31 PM PDT 24
Peak memory 219584 kb
Host smart-1ff7fa3d-ec71-4b8d-8cf4-c33f4105742c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128346308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1128346308
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.4135325077
Short name T266
Test name
Test status
Simulation time 1466243877 ps
CPU time 10.03 seconds
Started May 19 01:03:25 PM PDT 24
Finished May 19 01:03:36 PM PDT 24
Peak memory 217816 kb
Host smart-479f43df-3a56-48dd-b3ae-628be1e3f5f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135325077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.4
135325077
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3314608780
Short name T503
Test name
Test status
Simulation time 799190562 ps
CPU time 12.15 seconds
Started May 19 01:03:23 PM PDT 24
Finished May 19 01:03:36 PM PDT 24
Peak memory 217956 kb
Host smart-beefa1ce-9a19-47d5-96c5-c181fa195eff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314608780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3314608780
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3010625346
Short name T68
Test name
Test status
Simulation time 5156753875 ps
CPU time 10.91 seconds
Started May 19 01:03:24 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 213612 kb
Host smart-8aad21b4-e57c-4c7c-9ed2-9e0bcc054dfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010625346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3010625346
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1131148966
Short name T731
Test name
Test status
Simulation time 174828251 ps
CPU time 5.44 seconds
Started May 19 01:03:23 PM PDT 24
Finished May 19 01:03:29 PM PDT 24
Peak memory 213240 kb
Host smart-0d3ec869-c25f-4cd9-83b9-fa76efa63831
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131148966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1131148966
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.141589566
Short name T325
Test name
Test status
Simulation time 1820214348 ps
CPU time 66.3 seconds
Started May 19 01:03:23 PM PDT 24
Finished May 19 01:04:30 PM PDT 24
Peak memory 267268 kb
Host smart-a90f108e-1cf5-426f-be35-48a1bcfda76d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141589566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.141589566
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4289049514
Short name T315
Test name
Test status
Simulation time 2132323201 ps
CPU time 9.81 seconds
Started May 19 01:03:24 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 222932 kb
Host smart-d63756d2-2121-4e39-81bc-080605198673
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289049514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4289049514
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3907953476
Short name T451
Test name
Test status
Simulation time 255940557 ps
CPU time 3.47 seconds
Started May 19 01:03:18 PM PDT 24
Finished May 19 01:03:22 PM PDT 24
Peak memory 218012 kb
Host smart-40e7e261-97c6-4e8d-968e-9a336005a3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907953476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3907953476
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.961806604
Short name T550
Test name
Test status
Simulation time 710705793 ps
CPU time 8.58 seconds
Started May 19 01:03:24 PM PDT 24
Finished May 19 01:03:33 PM PDT 24
Peak memory 214292 kb
Host smart-8933935f-e039-4f3b-a718-2fa14a2d0885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961806604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.961806604
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3176833160
Short name T182
Test name
Test status
Simulation time 3114365700 ps
CPU time 11.71 seconds
Started May 19 01:03:22 PM PDT 24
Finished May 19 01:03:34 PM PDT 24
Peak memory 226208 kb
Host smart-72ae3cc9-5578-479d-8446-8562f3d296d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176833160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3176833160
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1566523710
Short name T394
Test name
Test status
Simulation time 4010685579 ps
CPU time 11.17 seconds
Started May 19 01:03:22 PM PDT 24
Finished May 19 01:03:33 PM PDT 24
Peak memory 218088 kb
Host smart-4056d05a-ae8d-47cc-addf-86a59a884e78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566523710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1566523710
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.443808452
Short name T789
Test name
Test status
Simulation time 1232748010 ps
CPU time 8.91 seconds
Started May 19 01:03:21 PM PDT 24
Finished May 19 01:03:30 PM PDT 24
Peak memory 218236 kb
Host smart-4b9d4a26-d442-4068-b8b5-6617fe3b4c6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443808452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.443808452
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3024223958
Short name T692
Test name
Test status
Simulation time 1176905098 ps
CPU time 11.84 seconds
Started May 19 01:03:23 PM PDT 24
Finished May 19 01:03:36 PM PDT 24
Peak memory 218024 kb
Host smart-6537fb24-bf73-4430-a9b0-c013555c86e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024223958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3024223958
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.516213812
Short name T729
Test name
Test status
Simulation time 45968051 ps
CPU time 1.19 seconds
Started May 19 01:03:21 PM PDT 24
Finished May 19 01:03:22 PM PDT 24
Peak memory 213400 kb
Host smart-b5f8f89c-faf8-478d-8043-ef6b615a2e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516213812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.516213812
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3428288307
Short name T242
Test name
Test status
Simulation time 198963806 ps
CPU time 26.18 seconds
Started May 19 01:03:16 PM PDT 24
Finished May 19 01:03:43 PM PDT 24
Peak memory 250936 kb
Host smart-fc267a2d-5562-4d9b-9dbb-8be6bb5727ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428288307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3428288307
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.216084271
Short name T860
Test name
Test status
Simulation time 99545220 ps
CPU time 5.85 seconds
Started May 19 01:03:16 PM PDT 24
Finished May 19 01:03:22 PM PDT 24
Peak memory 246728 kb
Host smart-bd58b2a1-61aa-47ec-b6ca-77a977409bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216084271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.216084271
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.293052543
Short name T650
Test name
Test status
Simulation time 45396684711 ps
CPU time 67.86 seconds
Started May 19 01:03:24 PM PDT 24
Finished May 19 01:04:33 PM PDT 24
Peak memory 271584 kb
Host smart-88d91248-ba84-4db7-ac8a-ae548f72867e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293052543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.293052543
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1068644008
Short name T152
Test name
Test status
Simulation time 139108743433 ps
CPU time 1504.16 seconds
Started May 19 01:03:23 PM PDT 24
Finished May 19 01:28:28 PM PDT 24
Peak memory 644380 kb
Host smart-7689f4f4-654a-4d05-9059-87f30d6ef008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1068644008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1068644008
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1628915501
Short name T264
Test name
Test status
Simulation time 92589566 ps
CPU time 0.88 seconds
Started May 19 01:03:17 PM PDT 24
Finished May 19 01:03:18 PM PDT 24
Peak memory 211568 kb
Host smart-09f0d313-3181-438f-a405-dc0c705072e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628915501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1628915501
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3306595435
Short name T624
Test name
Test status
Simulation time 51260163 ps
CPU time 0.92 seconds
Started May 19 01:03:34 PM PDT 24
Finished May 19 01:03:36 PM PDT 24
Peak memory 209612 kb
Host smart-d69dc8ce-521e-49a1-b7f6-3637f181e4bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306595435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3306595435
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3232991574
Short name T176
Test name
Test status
Simulation time 19868082 ps
CPU time 0.92 seconds
Started May 19 01:03:28 PM PDT 24
Finished May 19 01:03:29 PM PDT 24
Peak memory 209524 kb
Host smart-a34ee3b0-6bd8-4254-a94e-9dbdfa22de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232991574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3232991574
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3435132554
Short name T255
Test name
Test status
Simulation time 769228041 ps
CPU time 10.35 seconds
Started May 19 01:03:30 PM PDT 24
Finished May 19 01:03:40 PM PDT 24
Peak memory 218000 kb
Host smart-f4e12aa5-937f-49c8-ba59-84a16fc3414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435132554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3435132554
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.829341758
Short name T289
Test name
Test status
Simulation time 4098218928 ps
CPU time 9.63 seconds
Started May 19 01:03:28 PM PDT 24
Finished May 19 01:03:38 PM PDT 24
Peak memory 209596 kb
Host smart-5477746d-62c7-4907-a454-e07d70142ae0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829341758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.829341758
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3741565318
Short name T539
Test name
Test status
Simulation time 7930516769 ps
CPU time 58.88 seconds
Started May 19 01:03:28 PM PDT 24
Finished May 19 01:04:27 PM PDT 24
Peak memory 218940 kb
Host smart-849dcda0-b9c8-46ed-9cec-0078fd77c0d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741565318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3741565318
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1911682022
Short name T7
Test name
Test status
Simulation time 238130114 ps
CPU time 3.81 seconds
Started May 19 01:03:30 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 217164 kb
Host smart-c72042d1-3580-422c-a3f0-e3108e9a4cda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911682022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
911682022
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.304111451
Short name T405
Test name
Test status
Simulation time 200569796 ps
CPU time 3.14 seconds
Started May 19 01:03:30 PM PDT 24
Finished May 19 01:03:33 PM PDT 24
Peak memory 218036 kb
Host smart-48368212-1eb7-4e4c-8bb7-07e37e90f4b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304111451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.304111451
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2283640997
Short name T83
Test name
Test status
Simulation time 1677029746 ps
CPU time 22.19 seconds
Started May 19 01:03:28 PM PDT 24
Finished May 19 01:03:51 PM PDT 24
Peak memory 213192 kb
Host smart-e729bdd9-2f5c-423d-b7ea-ce7dc1d44182
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283640997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2283640997
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2399871953
Short name T511
Test name
Test status
Simulation time 313398752 ps
CPU time 4.97 seconds
Started May 19 01:03:30 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 213260 kb
Host smart-9d44e564-a121-45b4-89f5-09bfdc8bf663
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399871953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2399871953
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4048833030
Short name T312
Test name
Test status
Simulation time 11325354729 ps
CPU time 66.1 seconds
Started May 19 01:03:27 PM PDT 24
Finished May 19 01:04:33 PM PDT 24
Peak memory 267748 kb
Host smart-f88e674e-7c6b-4913-afa9-9499e6eb8b95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048833030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4048833030
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3612361911
Short name T490
Test name
Test status
Simulation time 280896955 ps
CPU time 9.16 seconds
Started May 19 01:03:28 PM PDT 24
Finished May 19 01:03:38 PM PDT 24
Peak memory 246464 kb
Host smart-4dcb41e5-824a-4102-9de6-c6e866022f05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612361911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3612361911
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3209803477
Short name T682
Test name
Test status
Simulation time 56861335 ps
CPU time 1.55 seconds
Started May 19 01:03:29 PM PDT 24
Finished May 19 01:03:31 PM PDT 24
Peak memory 218028 kb
Host smart-b7d93624-6cdc-4003-8489-147a0c0a3279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209803477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3209803477
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.4038731122
Short name T585
Test name
Test status
Simulation time 2320937154 ps
CPU time 9.51 seconds
Started May 19 01:03:28 PM PDT 24
Finished May 19 01:03:38 PM PDT 24
Peak memory 213972 kb
Host smart-e3802905-13e9-4aeb-b428-744a62b465f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038731122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.4038731122
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3674736204
Short name T379
Test name
Test status
Simulation time 462534768 ps
CPU time 14.15 seconds
Started May 19 01:03:32 PM PDT 24
Finished May 19 01:03:47 PM PDT 24
Peak memory 218360 kb
Host smart-c87dc5a7-c9c2-4a98-b411-b4a0a77d8bed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674736204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3674736204
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3521438022
Short name T446
Test name
Test status
Simulation time 322981522 ps
CPU time 11.91 seconds
Started May 19 01:03:34 PM PDT 24
Finished May 19 01:03:47 PM PDT 24
Peak memory 218068 kb
Host smart-a187a7ca-cd20-4338-ae3b-ab30f4f3a660
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521438022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
521438022
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3013770960
Short name T746
Test name
Test status
Simulation time 1124900008 ps
CPU time 7.34 seconds
Started May 19 01:03:29 PM PDT 24
Finished May 19 01:03:37 PM PDT 24
Peak memory 218068 kb
Host smart-0b67ca27-6751-49d8-a0ba-934ba0c5cc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013770960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3013770960
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.43168211
Short name T369
Test name
Test status
Simulation time 179662242 ps
CPU time 3.31 seconds
Started May 19 01:03:28 PM PDT 24
Finished May 19 01:03:32 PM PDT 24
Peak memory 214752 kb
Host smart-9f883b47-4d2b-4aeb-970e-8a3d7a0eff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43168211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.43168211
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3198246780
Short name T802
Test name
Test status
Simulation time 892034601 ps
CPU time 24.89 seconds
Started May 19 01:03:27 PM PDT 24
Finished May 19 01:03:53 PM PDT 24
Peak memory 250820 kb
Host smart-7377b250-718d-4fb8-b104-167f272a261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198246780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3198246780
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.550914534
Short name T233
Test name
Test status
Simulation time 254387998 ps
CPU time 8.9 seconds
Started May 19 01:03:27 PM PDT 24
Finished May 19 01:03:36 PM PDT 24
Peak memory 250980 kb
Host smart-7d24cfe6-74a2-409b-9b12-9e9b0341a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550914534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.550914534
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1100125215
Short name T378
Test name
Test status
Simulation time 1367698787 ps
CPU time 12.88 seconds
Started May 19 01:03:34 PM PDT 24
Finished May 19 01:03:48 PM PDT 24
Peak memory 226100 kb
Host smart-65d86f25-ee21-4bb1-831e-24a15a494d11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100125215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1100125215
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1581398179
Short name T143
Test name
Test status
Simulation time 26692491886 ps
CPU time 659.71 seconds
Started May 19 01:03:33 PM PDT 24
Finished May 19 01:14:33 PM PDT 24
Peak memory 422076 kb
Host smart-5710f2c5-6e36-42d2-b897-d6d710931514
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1581398179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1581398179
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2142238311
Short name T302
Test name
Test status
Simulation time 15174778 ps
CPU time 0.82 seconds
Started May 19 01:03:29 PM PDT 24
Finished May 19 01:03:30 PM PDT 24
Peak memory 208972 kb
Host smart-9d6c46ef-3292-48a2-b6ed-5de5f76441fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142238311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2142238311
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1303908349
Short name T702
Test name
Test status
Simulation time 157365077 ps
CPU time 0.91 seconds
Started May 19 01:03:43 PM PDT 24
Finished May 19 01:03:45 PM PDT 24
Peak memory 209640 kb
Host smart-78f50c34-ffc1-49f1-85be-85502baf6830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303908349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1303908349
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3027617228
Short name T215
Test name
Test status
Simulation time 30529851 ps
CPU time 0.9 seconds
Started May 19 01:03:40 PM PDT 24
Finished May 19 01:03:42 PM PDT 24
Peak memory 209540 kb
Host smart-93960d0d-b6eb-4aab-942a-2d3e606686df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027617228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3027617228
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1986104427
Short name T474
Test name
Test status
Simulation time 352041489 ps
CPU time 15.33 seconds
Started May 19 01:03:46 PM PDT 24
Finished May 19 01:04:02 PM PDT 24
Peak memory 217984 kb
Host smart-f9571c96-7822-4457-bc21-b8fa988a7a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986104427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1986104427
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.195986820
Short name T635
Test name
Test status
Simulation time 2903129865 ps
CPU time 7.7 seconds
Started May 19 01:03:46 PM PDT 24
Finished May 19 01:03:54 PM PDT 24
Peak memory 209576 kb
Host smart-34080fb7-ed09-453b-970c-32c203d3e85e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195986820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.195986820
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3370104401
Short name T528
Test name
Test status
Simulation time 65247682856 ps
CPU time 46.86 seconds
Started May 19 01:03:41 PM PDT 24
Finished May 19 01:04:29 PM PDT 24
Peak memory 218956 kb
Host smart-265fa6e1-d140-426e-bf62-054a43fd475d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370104401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3370104401
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2557782074
Short name T711
Test name
Test status
Simulation time 433661898 ps
CPU time 5.09 seconds
Started May 19 01:03:41 PM PDT 24
Finished May 19 01:03:47 PM PDT 24
Peak memory 217148 kb
Host smart-9d3f926e-bd69-4f1c-b95b-3eaeb5a3c9de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557782074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
557782074
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.47893863
Short name T220
Test name
Test status
Simulation time 1093280304 ps
CPU time 4.52 seconds
Started May 19 01:03:40 PM PDT 24
Finished May 19 01:03:45 PM PDT 24
Peak memory 217904 kb
Host smart-4219fb74-29b3-46fa-90a2-0c13e6f23a39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47893863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_p
rog_failure.47893863
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1905890427
Short name T583
Test name
Test status
Simulation time 776557354 ps
CPU time 21.09 seconds
Started May 19 01:03:39 PM PDT 24
Finished May 19 01:04:00 PM PDT 24
Peak memory 213108 kb
Host smart-be7a69e2-b964-4291-abbb-b97b1e41207b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905890427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1905890427
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1688248943
Short name T559
Test name
Test status
Simulation time 306488106 ps
CPU time 1.85 seconds
Started May 19 01:03:46 PM PDT 24
Finished May 19 01:03:49 PM PDT 24
Peak memory 212892 kb
Host smart-9af3f988-b951-46eb-8560-b1bc9a839304
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688248943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1688248943
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2062428065
Short name T753
Test name
Test status
Simulation time 4515246304 ps
CPU time 49.59 seconds
Started May 19 01:03:40 PM PDT 24
Finished May 19 01:04:30 PM PDT 24
Peak memory 275756 kb
Host smart-b2cc168a-d387-4b43-a024-317c6b6c032d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062428065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2062428065
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2125717895
Short name T543
Test name
Test status
Simulation time 1730659535 ps
CPU time 12.5 seconds
Started May 19 01:03:41 PM PDT 24
Finished May 19 01:03:55 PM PDT 24
Peak memory 245212 kb
Host smart-93485152-484d-4dd5-8bca-2da0f18f5ff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125717895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2125717895
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1348450071
Short name T397
Test name
Test status
Simulation time 160307670 ps
CPU time 2.13 seconds
Started May 19 01:03:41 PM PDT 24
Finished May 19 01:03:44 PM PDT 24
Peak memory 218120 kb
Host smart-541429fc-d657-468d-9a6e-65202d76f6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348450071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1348450071
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3575393486
Short name T147
Test name
Test status
Simulation time 395747688 ps
CPU time 7.58 seconds
Started May 19 01:03:40 PM PDT 24
Finished May 19 01:03:48 PM PDT 24
Peak memory 214188 kb
Host smart-f1294941-75a5-42d9-bc2b-054d05abf4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575393486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3575393486
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.812519279
Short name T404
Test name
Test status
Simulation time 438654362 ps
CPU time 17.75 seconds
Started May 19 01:03:39 PM PDT 24
Finished May 19 01:03:58 PM PDT 24
Peak memory 226140 kb
Host smart-364fcdc1-9999-44c9-b027-fd48b88299cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812519279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.812519279
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2087662951
Short name T164
Test name
Test status
Simulation time 774879869 ps
CPU time 13.51 seconds
Started May 19 01:03:44 PM PDT 24
Finished May 19 01:03:59 PM PDT 24
Peak memory 217968 kb
Host smart-152b1abf-1e21-4438-b126-115037058d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087662951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2087662951
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1058863516
Short name T615
Test name
Test status
Simulation time 1150007632 ps
CPU time 11.57 seconds
Started May 19 01:03:45 PM PDT 24
Finished May 19 01:03:58 PM PDT 24
Peak memory 218016 kb
Host smart-9f305b9b-875b-4b9f-a5be-e3660f8534ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058863516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
058863516
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3245772509
Short name T780
Test name
Test status
Simulation time 357649202 ps
CPU time 7.69 seconds
Started May 19 01:03:40 PM PDT 24
Finished May 19 01:03:49 PM PDT 24
Peak memory 218068 kb
Host smart-c89ee09f-5252-4999-8252-6a7cb61239e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245772509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3245772509
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2852612234
Short name T297
Test name
Test status
Simulation time 150796586 ps
CPU time 3.04 seconds
Started May 19 01:03:34 PM PDT 24
Finished May 19 01:03:37 PM PDT 24
Peak memory 214848 kb
Host smart-a7bfc8ae-60b9-4a05-acd1-23576310304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852612234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2852612234
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2141242018
Short name T261
Test name
Test status
Simulation time 899221413 ps
CPU time 23.42 seconds
Started May 19 01:03:46 PM PDT 24
Finished May 19 01:04:11 PM PDT 24
Peak memory 250916 kb
Host smart-52501f03-351b-49f6-8c99-b3f3a2af187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141242018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2141242018
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2014616355
Short name T93
Test name
Test status
Simulation time 71242188 ps
CPU time 3.23 seconds
Started May 19 01:03:42 PM PDT 24
Finished May 19 01:03:45 PM PDT 24
Peak memory 222384 kb
Host smart-fb8119c2-4355-414c-8b26-e1a61f2062a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014616355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2014616355
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1521321724
Short name T283
Test name
Test status
Simulation time 2395920204 ps
CPU time 48.32 seconds
Started May 19 01:03:45 PM PDT 24
Finished May 19 01:04:34 PM PDT 24
Peak memory 248940 kb
Host smart-7c23cb75-e65f-4a9a-b982-c169a50203f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521321724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1521321724
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.26333870
Short name T712
Test name
Test status
Simulation time 43758722 ps
CPU time 0.92 seconds
Started May 19 01:03:34 PM PDT 24
Finished May 19 01:03:36 PM PDT 24
Peak memory 208584 kb
Host smart-1420a5f5-425d-4b5b-ab4c-325593c52f9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26333870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_volatile_unlock_smoke.26333870
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.672026928
Short name T232
Test name
Test status
Simulation time 35883484 ps
CPU time 0.79 seconds
Started May 19 01:03:55 PM PDT 24
Finished May 19 01:03:56 PM PDT 24
Peak memory 209516 kb
Host smart-cf8a626d-269a-4bb5-ad79-442e3cf1e684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672026928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.672026928
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2732026615
Short name T262
Test name
Test status
Simulation time 12007226 ps
CPU time 0.8 seconds
Started May 19 01:03:44 PM PDT 24
Finished May 19 01:03:46 PM PDT 24
Peak memory 209492 kb
Host smart-b76bcc16-e785-42b4-8e74-4bba33664a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732026615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2732026615
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.536475018
Short name T411
Test name
Test status
Simulation time 1461233895 ps
CPU time 11.21 seconds
Started May 19 01:03:44 PM PDT 24
Finished May 19 01:03:56 PM PDT 24
Peak memory 218116 kb
Host smart-37117cec-6bc1-481d-a3f8-1d05e465f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536475018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.536475018
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1050095467
Short name T601
Test name
Test status
Simulation time 472993978 ps
CPU time 2.19 seconds
Started May 19 01:03:52 PM PDT 24
Finished May 19 01:03:55 PM PDT 24
Peak memory 216820 kb
Host smart-693ff77d-d497-4e34-8c9f-72a72bd57a0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050095467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1050095467
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1899701416
Short name T819
Test name
Test status
Simulation time 6774113614 ps
CPU time 26.64 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:04:21 PM PDT 24
Peak memory 218988 kb
Host smart-34c01eac-d870-48b5-9d64-27f34a589dfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899701416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1899701416
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3096715117
Short name T398
Test name
Test status
Simulation time 1577334830 ps
CPU time 8.29 seconds
Started May 19 01:03:52 PM PDT 24
Finished May 19 01:04:01 PM PDT 24
Peak memory 217332 kb
Host smart-e49f5e43-9263-407b-ac2e-f2e3f5a79d05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096715117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
096715117
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1267281307
Short name T864
Test name
Test status
Simulation time 6076369891 ps
CPU time 14.87 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:04:09 PM PDT 24
Peak memory 218024 kb
Host smart-cb5375b2-9d0e-4dc9-998a-357cdfcd2a9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267281307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1267281307
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.159415438
Short name T674
Test name
Test status
Simulation time 1023975159 ps
CPU time 16.81 seconds
Started May 19 01:03:50 PM PDT 24
Finished May 19 01:04:08 PM PDT 24
Peak memory 213128 kb
Host smart-4467c275-a212-454b-9a5b-3d940223ed97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159415438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.159415438
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.409622583
Short name T347
Test name
Test status
Simulation time 586501437 ps
CPU time 7.43 seconds
Started May 19 01:03:46 PM PDT 24
Finished May 19 01:03:54 PM PDT 24
Peak memory 213856 kb
Host smart-8a4e892f-3957-496c-bfc8-33a873b823d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409622583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.409622583
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.128098950
Short name T346
Test name
Test status
Simulation time 2747227597 ps
CPU time 44.48 seconds
Started May 19 01:03:47 PM PDT 24
Finished May 19 01:04:32 PM PDT 24
Peak memory 275548 kb
Host smart-88f21c2d-d7f9-49f2-a723-76d01b185dce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128098950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.128098950
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.716096217
Short name T545
Test name
Test status
Simulation time 278196807 ps
CPU time 15.82 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:04:10 PM PDT 24
Peak memory 250964 kb
Host smart-7acb842b-2e65-4b61-8e6e-49327e486a17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716096217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.716096217
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.199348979
Short name T438
Test name
Test status
Simulation time 56477482 ps
CPU time 3.07 seconds
Started May 19 01:03:44 PM PDT 24
Finished May 19 01:03:48 PM PDT 24
Peak memory 218280 kb
Host smart-74ae5842-7320-4435-a0d8-18af354f167d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199348979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.199348979
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.376500279
Short name T686
Test name
Test status
Simulation time 584735441 ps
CPU time 10.78 seconds
Started May 19 01:03:47 PM PDT 24
Finished May 19 01:03:59 PM PDT 24
Peak memory 213740 kb
Host smart-9a097e04-9c5b-4be9-b932-8ae02eb0324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376500279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.376500279
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2530964968
Short name T623
Test name
Test status
Simulation time 4410904099 ps
CPU time 21.94 seconds
Started May 19 01:03:52 PM PDT 24
Finished May 19 01:04:14 PM PDT 24
Peak memory 219520 kb
Host smart-17624e7f-8964-45f5-a0b8-19754adf95db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530964968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2530964968
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2029041563
Short name T458
Test name
Test status
Simulation time 5914051299 ps
CPU time 11.67 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:04:06 PM PDT 24
Peak memory 218056 kb
Host smart-f56242c6-adae-4593-9783-131c69dd6461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029041563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2029041563
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2547328467
Short name T241
Test name
Test status
Simulation time 258339522 ps
CPU time 7.77 seconds
Started May 19 01:03:56 PM PDT 24
Finished May 19 01:04:04 PM PDT 24
Peak memory 218064 kb
Host smart-eec5dcc7-e4fc-496d-92a0-305eb3205a52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547328467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
547328467
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2610986241
Short name T331
Test name
Test status
Simulation time 197296908 ps
CPU time 7.04 seconds
Started May 19 01:03:44 PM PDT 24
Finished May 19 01:03:51 PM PDT 24
Peak memory 218108 kb
Host smart-61561849-1b76-409b-a6b8-3dc6eb0bc202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610986241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2610986241
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.152327262
Short name T167
Test name
Test status
Simulation time 34838412 ps
CPU time 1.58 seconds
Started May 19 01:03:46 PM PDT 24
Finished May 19 01:03:48 PM PDT 24
Peak memory 213432 kb
Host smart-3536c401-dd19-4d63-8b34-d4823fdc05ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152327262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.152327262
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.164969933
Short name T628
Test name
Test status
Simulation time 947718323 ps
CPU time 26.24 seconds
Started May 19 01:03:44 PM PDT 24
Finished May 19 01:04:11 PM PDT 24
Peak memory 250932 kb
Host smart-582f779c-8e7f-4655-a094-4f77d5e7d6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164969933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.164969933
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.873928333
Short name T359
Test name
Test status
Simulation time 81503067 ps
CPU time 7.29 seconds
Started May 19 01:03:47 PM PDT 24
Finished May 19 01:03:55 PM PDT 24
Peak memory 247436 kb
Host smart-07ff3d37-42be-48aa-8ee1-d61605b7f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873928333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.873928333
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3713436443
Short name T34
Test name
Test status
Simulation time 4283565191 ps
CPU time 64.91 seconds
Started May 19 01:03:51 PM PDT 24
Finished May 19 01:04:56 PM PDT 24
Peak memory 220292 kb
Host smart-62f7df9c-4e69-4496-94dc-e287318aac72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713436443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3713436443
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3541245744
Short name T797
Test name
Test status
Simulation time 81269212828 ps
CPU time 503.28 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:12:17 PM PDT 24
Peak memory 349360 kb
Host smart-48498744-54f2-47f8-a7bd-bc68d26eb823
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3541245744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3541245744
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.777285844
Short name T795
Test name
Test status
Simulation time 42887335 ps
CPU time 0.94 seconds
Started May 19 01:03:45 PM PDT 24
Finished May 19 01:03:47 PM PDT 24
Peak memory 212652 kb
Host smart-6924f5e1-8c08-4cee-9f90-f7b77ab8b5e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777285844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.777285844
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.497398123
Short name T566
Test name
Test status
Simulation time 29096147 ps
CPU time 1.14 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:05 PM PDT 24
Peak memory 209584 kb
Host smart-e345d6e1-a620-48ea-b92a-3b2c695701e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497398123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.497398123
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3938251159
Short name T213
Test name
Test status
Simulation time 17081561 ps
CPU time 0.9 seconds
Started May 19 01:03:59 PM PDT 24
Finished May 19 01:04:01 PM PDT 24
Peak memory 209500 kb
Host smart-93fc1ed5-edf2-4a23-aae3-5bb673b837e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938251159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3938251159
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1511336136
Short name T724
Test name
Test status
Simulation time 335693829 ps
CPU time 13.62 seconds
Started May 19 01:03:58 PM PDT 24
Finished May 19 01:04:13 PM PDT 24
Peak memory 218048 kb
Host smart-5f371607-25cc-4826-bad9-563a6992e820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511336136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1511336136
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3363607631
Short name T319
Test name
Test status
Simulation time 62988168 ps
CPU time 1.6 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:06 PM PDT 24
Peak memory 209560 kb
Host smart-f8e7144d-7ac0-4d33-a2a5-3242fb08df4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363607631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3363607631
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3874437621
Short name T812
Test name
Test status
Simulation time 29729951048 ps
CPU time 28.18 seconds
Started May 19 01:03:57 PM PDT 24
Finished May 19 01:04:26 PM PDT 24
Peak memory 218936 kb
Host smart-a8684dcf-461b-4d73-b998-d259260f5ede
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874437621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3874437621
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1570747109
Short name T749
Test name
Test status
Simulation time 151230833 ps
CPU time 2.44 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:04:06 PM PDT 24
Peak memory 217752 kb
Host smart-2ba39ac0-4926-4929-a61e-bed971cdb7fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570747109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
570747109
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2235713930
Short name T596
Test name
Test status
Simulation time 2764555288 ps
CPU time 8.79 seconds
Started May 19 01:03:57 PM PDT 24
Finished May 19 01:04:07 PM PDT 24
Peak memory 217900 kb
Host smart-292e2855-065c-47b8-ab00-e78a1b21d027
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235713930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2235713930
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3639563014
Short name T813
Test name
Test status
Simulation time 3077289561 ps
CPU time 9.7 seconds
Started May 19 01:04:06 PM PDT 24
Finished May 19 01:04:17 PM PDT 24
Peak memory 213368 kb
Host smart-71074b1d-172f-4006-8afc-3f451d4232fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639563014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3639563014
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3116822438
Short name T714
Test name
Test status
Simulation time 298844105 ps
CPU time 4.79 seconds
Started May 19 01:03:58 PM PDT 24
Finished May 19 01:04:04 PM PDT 24
Peak memory 213320 kb
Host smart-ed889c8f-4abe-4345-a6f5-5890e0c7eb38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116822438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3116822438
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.684177218
Short name T494
Test name
Test status
Simulation time 12391183441 ps
CPU time 30.94 seconds
Started May 19 01:03:57 PM PDT 24
Finished May 19 01:04:30 PM PDT 24
Peak memory 250960 kb
Host smart-2d04ae4e-473d-46ac-84f6-9fb9d19032e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684177218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.684177218
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1880318158
Short name T841
Test name
Test status
Simulation time 539287265 ps
CPU time 20.56 seconds
Started May 19 01:03:58 PM PDT 24
Finished May 19 01:04:19 PM PDT 24
Peak memory 242704 kb
Host smart-98c4152e-67ec-4dd5-ad7c-49fb5f8bd1e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880318158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1880318158
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1886874853
Short name T811
Test name
Test status
Simulation time 111837529 ps
CPU time 4.81 seconds
Started May 19 01:03:58 PM PDT 24
Finished May 19 01:04:04 PM PDT 24
Peak memory 218044 kb
Host smart-663c14c7-25d2-4867-856c-bc590545af4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886874853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1886874853
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2936711351
Short name T787
Test name
Test status
Simulation time 739341544 ps
CPU time 9.83 seconds
Started May 19 01:03:58 PM PDT 24
Finished May 19 01:04:09 PM PDT 24
Peak memory 217756 kb
Host smart-fedeb0d3-809b-498a-801e-b7a73a5ab5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936711351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2936711351
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1712977358
Short name T831
Test name
Test status
Simulation time 2418567799 ps
CPU time 12.06 seconds
Started May 19 01:03:58 PM PDT 24
Finished May 19 01:04:11 PM PDT 24
Peak memory 226188 kb
Host smart-4328132a-8396-4cb9-a6d6-a2bd8485d245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712977358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1712977358
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1098562912
Short name T323
Test name
Test status
Simulation time 2335578851 ps
CPU time 21.37 seconds
Started May 19 01:04:06 PM PDT 24
Finished May 19 01:04:28 PM PDT 24
Peak memory 218008 kb
Host smart-2f9acb31-409b-4bd9-9fd0-9d3fc8250125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098562912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1098562912
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.4166932703
Short name T401
Test name
Test status
Simulation time 957383979 ps
CPU time 7.77 seconds
Started May 19 01:03:57 PM PDT 24
Finished May 19 01:04:06 PM PDT 24
Peak memory 218284 kb
Host smart-e6491268-a3bb-46f9-a4ff-37a9f8c66057
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166932703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.4
166932703
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3647904803
Short name T705
Test name
Test status
Simulation time 7882083872 ps
CPU time 14.68 seconds
Started May 19 01:03:59 PM PDT 24
Finished May 19 01:04:14 PM PDT 24
Peak memory 218148 kb
Host smart-a5cf4126-5d7e-4228-a6d4-40c47588edbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647904803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3647904803
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.69721798
Short name T381
Test name
Test status
Simulation time 858068722 ps
CPU time 3.8 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:03:58 PM PDT 24
Peak memory 214560 kb
Host smart-2ae86b61-dade-4234-a9cc-3df49a08f4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69721798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.69721798
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3394965413
Short name T478
Test name
Test status
Simulation time 1244165445 ps
CPU time 24.71 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:04:18 PM PDT 24
Peak memory 251168 kb
Host smart-460ce89d-d4e5-4716-aadc-2038c3784a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394965413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3394965413
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1188745854
Short name T666
Test name
Test status
Simulation time 82117106 ps
CPU time 8.62 seconds
Started May 19 01:03:52 PM PDT 24
Finished May 19 01:04:01 PM PDT 24
Peak memory 250920 kb
Host smart-794abfa8-6fef-4424-9f29-cd622aef2206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188745854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1188745854
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2399884750
Short name T512
Test name
Test status
Simulation time 13444948193 ps
CPU time 103.2 seconds
Started May 19 01:04:03 PM PDT 24
Finished May 19 01:05:47 PM PDT 24
Peak memory 269604 kb
Host smart-3a3e7220-322f-49ee-ac03-241a5ba126dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399884750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2399884750
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1236859125
Short name T142
Test name
Test status
Simulation time 111306696867 ps
CPU time 725.5 seconds
Started May 19 01:03:58 PM PDT 24
Finished May 19 01:16:05 PM PDT 24
Peak memory 333348 kb
Host smart-7e2eaa1f-c2dd-43a1-88f9-a6379728f7c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1236859125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1236859125
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1590227965
Short name T788
Test name
Test status
Simulation time 16287817 ps
CPU time 1.15 seconds
Started May 19 01:03:53 PM PDT 24
Finished May 19 01:03:55 PM PDT 24
Peak memory 211536 kb
Host smart-ceaad68a-2321-4b01-add2-acd4ba3feb9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590227965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1590227965
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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