Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95668081

1

T1

64520

T2

4352

T3

9943

auto[1]

1414981

1

T5

297

T10

1089

T6

1078

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95661406

1

T1

64520

T2

4352

T3

9943

auto[1]

1421656

1

T5

396

T10

1683

T6

882

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6761475	1			T1	257		T2	1287		T3	68
auto[IdleSt]	19645542	1			T1	64263		T2	1411		T3	9875
auto[ClkMuxSt]	34015	1			T2	14		T4	98		T5	66
auto[CntIncrSt]	33782	1			T2	14		T4	98		T5	66
auto[CntProgSt]	1685834	1			T2	28		T4	3437		T5	117
auto[TransCheckSt]	26229	1			T2	14		T4	98		T5	55
auto[TokenHashSt]	40630643	1			T2	284		T4	2085		T5	442
auto[FlashRmaSt]	26981	1			T2	14		T5	23		T10	52
auto[TokenCheck0St]	12249	1			T2	14		T5	11		T10	35
auto[TokenCheck1St]	9077	1			T2	14		T5	7		T10	26
auto[TransProgSt]	400706	1			T2	28		T5	12		T10	258
auto[PostTransSt]	11293332	1			T2	1230		T4	14289		T5	11508
auto[ScrapSt]	202651	1			T16	395		T41	3		T17	6156
auto[EscalateSt]	6178045	1			T5	1014		T10	3845		T6	8138
auto[InvalidSt]	10140671	1			T10	2422		T16	107856		T44	5640

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1830	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10140671	1			T10	2422		T16	107856		T44	5640
EscalateSt	6178045	1			T5	1014		T10	3845		T6	8138
ScrapSt	202651	1			T16	395		T41	3		T17	6156
PostTransSt	11293332	1			T2	1230		T4	14289		T5	11508
TransProgSt	400706	1			T2	28		T5	12		T10	258
TokenCheck1St	9077	1			T2	14		T5	7		T10	26
TokenCheck0St	12249	1			T2	14		T5	11		T10	35
FlashRmaSt	26981	1			T2	14		T5	23		T10	52
TokenHashSt	40630643	1			T2	284		T4	2085		T5	442
TransCheckSt	26229	1			T2	14		T4	98		T5	55
CntProgSt	1685834	1			T2	28		T4	3437		T5	117
CntIncrSt	33782	1			T2	14		T4	98		T5	66
ClkMuxSt	34015	1			T2	14		T4	98		T5	66
IdleSt	19645542	1			T1	64263		T2	1411		T3	9875
ResetSt	6761475	1			T1	257		T2	1287		T3	68
arcs[ResetSt=>IdleSt]	51956	1			T1	1		T2	14		T3	1
arcs[IdleSt=>ScrapSt]	293	1			T16	2		T41	1		T17	1
arcs[IdleSt=>ClkMuxSt]	33841	1			T2	14		T4	98		T5	66
arcs[ClkMuxSt=>CntIncrSt]	33782	1			T2	14		T4	98		T5	66
arcs[CntIncrSt=>PostTransSt]	1627	1			T5	4		T13	4		T14	10
arcs[CntIncrSt=>CntProgSt]	32068	1			T2	14		T4	98		T5	62
arcs[CntProgSt=>PostTransSt]	4663	1			T5	7		T10	12		T6	20
arcs[CntProgSt=>TransCheckSt]	26229	1			T2	14		T4	98		T5	55
arcs[TransCheckSt=>PostTransSt]	3584	1			T5	14		T11	33		T12	41
arcs[TransCheckSt=>TokenHashSt]	22507	1			T2	14		T4	98		T5	41
arcs[TokenHashSt=>PostTransSt]	9445	1			T4	98		T5	30		T10	6
arcs[TokenHashSt=>FlashRmaSt]	12339	1			T2	14		T5	11		T10	35
arcs[FlashRmaSt=>TokenCheck0St]	12249	1			T2	14		T5	11		T10	35
arcs[TokenCheck0St=>PostTransSt]	3126	1			T5	4		T10	9		T11	15
arcs[TokenCheck0St=>TokenCheck1St]	9077	1			T2	14		T5	7		T10	26
arcs[TokenCheck1St=>PostTransSt]	669	1			T5	1		T10	1		T11	9
arcs[TransProgSt=>PostTransSt]	7416	1			T2	14		T5	6		T10	25
arcs[IdleSt=>EscalateSt]	198	1			T53	3		T54	4		T55	5
arcs[ClkMuxSt=>EscalateSt]	59	1			T53	2		T54	1		T55	2
arcs[CntIncrSt=>EscalateSt]	87	1			T41	1		T53	3		T54	2
arcs[CntProgSt=>EscalateSt]	1176	1			T41	33		T53	10		T54	10
arcs[TransCheckSt=>EscalateSt]	138	1			T41	6		T53	9		T54	14
arcs[TokenHashSt=>EscalateSt]	723	1			T41	20		T53	23		T38	2
arcs[FlashRmaSt=>EscalateSt]	90	1			T41	3		T53	4		T55	1
arcs[TokenCheck0St=>EscalateSt]	46	1			T53	1		T55	3		T59	2
arcs[TokenCheck1St=>EscalateSt]	180	1			T41	4		T53	2		T54	3
arcs[TransProgSt=>EscalateSt]	812	1			T41	21		T53	9		T54	11
arcs[PostTransSt=>EscalateSt]	4909	1			T5	7		T10	12		T6	20
arcs[InvalidSt=>EscalateSt]	13700	1			T10	16		T16	170		T44	76

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6761285	1			T1	257		T2	1287		T3	68
auto[0]	auto[IdleSt]	19645404	1			T1	64263		T2	1411		T3	9875
auto[0]	auto[ClkMuxSt]	33979	1			T2	14		T4	98		T5	66
auto[0]	auto[CntIncrSt]	33720	1			T2	14		T4	98		T5	66
auto[0]	auto[CntProgSt]	1685014	1			T2	28		T4	3437		T5	117
auto[0]	auto[TransCheckSt]	26144	1			T2	14		T4	98		T5	55
auto[0]	auto[TokenHashSt]	40630183	1			T2	284		T4	2085		T5	442
auto[0]	auto[FlashRmaSt]	26923	1			T2	14		T5	23		T10	52
auto[0]	auto[TokenCheck0St]	12213	1			T2	14		T5	11		T10	35
auto[0]	auto[TokenCheck1St]	8973	1			T2	14		T5	7		T10	26
auto[0]	auto[TransProgSt]	400148	1			T2	28		T5	12		T10	258
auto[0]	auto[PostTransSt]	11290813	1			T2	1230		T4	14289		T5	11505
auto[0]	auto[ScrapSt]	202612	1			T16	395		T41	2		T17	6156
auto[0]	auto[EscalateSt]	4774901	1			T5	720		T10	2767		T6	7071
auto[0]	auto[InvalidSt]	10133939	1			T10	2416		T16	107765		T44	5604
auto[1]	auto[ResetSt]	190	1			T41	3		T53	6		T54	5
auto[1]	auto[IdleSt]	138	1			T53	3		T54	2		T55	2
auto[1]	auto[ClkMuxSt]	36	1			T55	1		T59	1		T159	1
auto[1]	auto[CntIncrSt]	62	1			T53	1		T54	2		T173	2
auto[1]	auto[CntProgSt]	820	1			T41	27		T53	8		T54	7
auto[1]	auto[TransCheckSt]	85	1			T41	4		T53	7		T54	11
auto[1]	auto[TokenHashSt]	460	1			T41	12		T53	15		T54	20
auto[1]	auto[FlashRmaSt]	58	1			T41	2		T53	4		T55	1
auto[1]	auto[TokenCheck0St]	36	1			T55	2		T59	1		T159	2
auto[1]	auto[TokenCheck1St]	104	1			T41	3		T53	1		T54	2
auto[1]	auto[TransProgSt]	558	1			T41	15		T53	6		T54	8
auto[1]	auto[PostTransSt]	2519	1			T5	3		T10	5		T6	11
auto[1]	auto[ScrapSt]	39	1			T41	1		T55	1		T59	2
auto[1]	auto[EscalateSt]	1403144	1			T5	294		T10	1078		T6	1067
auto[1]	auto[InvalidSt]	6732	1			T10	6		T16	91		T44	36

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6761297	1			T1	257		T2	1287		T3	68
auto[0]	auto[IdleSt]	19645412	1			T1	64263		T2	1411		T3	9875
auto[0]	auto[ClkMuxSt]	33971	1			T2	14		T4	98		T5	66
auto[0]	auto[CntIncrSt]	33721	1			T2	14		T4	98		T5	66
auto[0]	auto[CntProgSt]	1685066	1			T2	28		T4	3437		T5	117
auto[0]	auto[TransCheckSt]	26137	1			T2	14		T4	98		T5	55
auto[0]	auto[TokenHashSt]	40630161	1			T2	284		T4	2085		T5	442
auto[0]	auto[FlashRmaSt]	26929	1			T2	14		T5	23		T10	52
auto[0]	auto[TokenCheck0St]	12217	1			T2	14		T5	11		T10	35
auto[0]	auto[TokenCheck1St]	8944	1			T2	14		T5	7		T10	26
auto[0]	auto[TransProgSt]	400169	1			T2	28		T5	12		T10	258
auto[0]	auto[PostTransSt]	11290864	1			T2	1230		T4	14289		T5	11504
auto[0]	auto[ScrapSt]	202609	1			T16	395		T41	2		T17	6156
auto[0]	auto[EscalateSt]	4768376	1			T5	622		T10	2179		T6	7265
auto[0]	auto[InvalidSt]	10133703	1			T10	2412		T16	107777		T44	5600
auto[1]	auto[ResetSt]	178	1			T41	7		T53	2		T54	5
auto[1]	auto[IdleSt]	130	1			T53	1		T54	3		T55	4
auto[1]	auto[ClkMuxSt]	44	1			T53	2		T54	1		T55	2
auto[1]	auto[CntIncrSt]	61	1			T41	1		T53	3		T54	1
auto[1]	auto[CntProgSt]	768	1			T41	23		T53	5		T54	3
auto[1]	auto[TransCheckSt]	92	1			T41	3		T53	3		T54	10
auto[1]	auto[TokenHashSt]	482	1			T41	15		T53	12		T38	2
auto[1]	auto[FlashRmaSt]	52	1			T41	1		T53	1		T55	1
auto[1]	auto[TokenCheck0St]	32	1			T53	1		T55	3		T59	2
auto[1]	auto[TokenCheck1St]	133	1			T41	2		T53	2		T54	2
auto[1]	auto[TransProgSt]	537	1			T41	12		T53	5		T54	7
auto[1]	auto[PostTransSt]	2468	1			T5	4		T10	7		T6	9
auto[1]	auto[ScrapSt]	42	1			T41	1		T54	1		T55	1
auto[1]	auto[EscalateSt]	1409669	1			T5	392		T10	1666		T6	873
auto[1]	auto[InvalidSt]	6968	1			T10	10		T16	79		T44	40