Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50335 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1738 |
1 |
|
|
T20 |
37 |
|
T23 |
7 |
|
T33 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51305 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
768 |
1 |
|
|
T16 |
20 |
|
T44 |
16 |
|
T52 |
20 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50271 |
1 |
|
|
T1 |
19 |
|
T2 |
56 |
|
T4 |
51 |
auto[1] |
1802 |
1 |
|
|
T2 |
9 |
|
T15 |
1 |
|
T6 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50205 |
1 |
|
|
T1 |
19 |
|
T2 |
57 |
|
T4 |
51 |
auto[1] |
1868 |
1 |
|
|
T2 |
8 |
|
T20 |
21 |
|
T21 |
18 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50270 |
1 |
|
|
T1 |
19 |
|
T2 |
61 |
|
T4 |
51 |
auto[1] |
1803 |
1 |
|
|
T2 |
4 |
|
T46 |
1 |
|
T20 |
37 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
47505 |
1 |
|
|
T2 |
65 |
|
T4 |
51 |
|
T5 |
6 |
no_err_inj |
4568 |
1 |
|
|
T1 |
19 |
|
T5 |
4 |
|
T15 |
9 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50242 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1831 |
1 |
|
|
T20 |
38 |
|
T23 |
16 |
|
T33 |
8 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51325 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
748 |
1 |
|
|
T16 |
15 |
|
T44 |
18 |
|
T52 |
19 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36679 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[1] |
15394 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50292 |
1 |
|
|
T1 |
19 |
|
T2 |
57 |
|
T4 |
51 |
auto[1] |
1781 |
1 |
|
|
T2 |
8 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50267 |
1 |
|
|
T1 |
19 |
|
T2 |
59 |
|
T4 |
51 |
auto[1] |
1806 |
1 |
|
|
T2 |
6 |
|
T5 |
1 |
|
T20 |
34 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50320 |
1 |
|
|
T1 |
19 |
|
T2 |
58 |
|
T4 |
51 |
auto[1] |
1753 |
1 |
|
|
T2 |
7 |
|
T5 |
1 |
|
T46 |
2 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50326 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1747 |
1 |
|
|
T20 |
37 |
|
T23 |
13 |
|
T33 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50139 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1934 |
1 |
|
|
T20 |
47 |
|
T21 |
17 |
|
T67 |
1 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51333 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
740 |
1 |
|
|
T16 |
13 |
|
T44 |
22 |
|
T52 |
19 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51307 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
766 |
1 |
|
|
T16 |
8 |
|
T44 |
19 |
|
T52 |
17 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51308 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
765 |
1 |
|
|
T16 |
12 |
|
T44 |
22 |
|
T52 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49611 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
2462 |
1 |
|
|
T5 |
10 |
|
T15 |
12 |
|
T6 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48290 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
3783 |
1 |
|
|
T18 |
69 |
|
T19 |
57 |
|
T58 |
82 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50260 |
1 |
|
|
T1 |
19 |
|
T2 |
61 |
|
T4 |
51 |
auto[1] |
1813 |
1 |
|
|
T2 |
4 |
|
T5 |
1 |
|
T20 |
31 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50288 |
1 |
|
|
T1 |
19 |
|
T2 |
57 |
|
T4 |
51 |
auto[1] |
1785 |
1 |
|
|
T2 |
8 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50222 |
1 |
|
|
T1 |
19 |
|
T2 |
54 |
|
T4 |
51 |
auto[1] |
1851 |
1 |
|
|
T2 |
11 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50276 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1797 |
1 |
|
|
T20 |
44 |
|
T23 |
12 |
|
T33 |
4 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46551 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T5 |
10 |
auto[1] |
5522 |
1 |
|
|
T4 |
51 |
|
T20 |
43 |
|
T92 |
83 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48373 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
3700 |
1 |
|
|
T14 |
75 |
|
T57 |
59 |
|
T68 |
97 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52073 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50282 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1791 |
1 |
|
|
T20 |
46 |
|
T23 |
11 |
|
T33 |
5 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50289 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1784 |
1 |
|
|
T20 |
45 |
|
T23 |
10 |
|
T33 |
11 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50244 |
1 |
|
|
T1 |
19 |
|
T2 |
65 |
|
T4 |
51 |
auto[1] |
1829 |
1 |
|
|
T20 |
36 |
|
T23 |
8 |
|
T33 |
5 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
46271 |
1 |
|
|
T2 |
65 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
no_err_inj |
3340 |
1 |
|
|
T1 |
19 |
|
T45 |
7 |
|
T20 |
73 |
auto[1] |
err_inj |
1234 |
1 |
|
|
T5 |
6 |
|
T15 |
3 |
|
T6 |
4 |
auto[1] |
no_err_inj |
1228 |
1 |
|
|
T5 |
4 |
|
T15 |
9 |
|
T6 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47959 |
1 |
|
|
T1 |
19 |
|
T2 |
57 |
|
T4 |
51 |
auto[0] |
auto[1] |
1652 |
1 |
|
|
T2 |
8 |
|
T20 |
34 |
|
T21 |
13 |
auto[1] |
auto[0] |
2329 |
1 |
|
|
T5 |
9 |
|
T15 |
12 |
|
T6 |
10 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T5 |
1 |
|
T6 |
2 |
|
T20 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47929 |
1 |
|
|
T1 |
19 |
|
T2 |
59 |
|
T4 |
51 |
auto[0] |
auto[1] |
1682 |
1 |
|
|
T2 |
6 |
|
T20 |
32 |
|
T21 |
22 |
auto[1] |
auto[0] |
2338 |
1 |
|
|
T5 |
9 |
|
T15 |
12 |
|
T6 |
12 |
auto[1] |
auto[1] |
124 |
1 |
|
|
T5 |
1 |
|
T20 |
2 |
|
T22 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47889 |
1 |
|
|
T1 |
19 |
|
T2 |
54 |
|
T4 |
51 |
auto[0] |
auto[1] |
1722 |
1 |
|
|
T2 |
11 |
|
T20 |
29 |
|
T21 |
12 |
auto[1] |
auto[0] |
2333 |
1 |
|
|
T5 |
9 |
|
T15 |
11 |
|
T6 |
12 |
auto[1] |
auto[1] |
129 |
1 |
|
|
T5 |
1 |
|
T15 |
1 |
|
T46 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47882 |
1 |
|
|
T1 |
19 |
|
T2 |
57 |
|
T4 |
51 |
auto[0] |
auto[1] |
1729 |
1 |
|
|
T2 |
8 |
|
T20 |
19 |
|
T21 |
18 |
auto[1] |
auto[0] |
2323 |
1 |
|
|
T5 |
10 |
|
T15 |
12 |
|
T6 |
12 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T20 |
2 |
|
T93 |
2 |
|
T210 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47935 |
1 |
|
|
T1 |
19 |
|
T2 |
61 |
|
T4 |
51 |
auto[0] |
auto[1] |
1676 |
1 |
|
|
T2 |
4 |
|
T20 |
35 |
|
T21 |
12 |
auto[1] |
auto[0] |
2335 |
1 |
|
|
T5 |
10 |
|
T15 |
12 |
|
T6 |
12 |
auto[1] |
auto[1] |
127 |
1 |
|
|
T46 |
1 |
|
T20 |
2 |
|
T22 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47942 |
1 |
|
|
T1 |
19 |
|
T2 |
56 |
|
T4 |
51 |
auto[0] |
auto[1] |
1669 |
1 |
|
|
T2 |
9 |
|
T20 |
30 |
|
T21 |
15 |
auto[1] |
auto[0] |
2329 |
1 |
|
|
T5 |
10 |
|
T15 |
11 |
|
T6 |
11 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T15 |
1 |
|
T6 |
1 |
|
T46 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35671 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1008 |
1 |
|
|
T20 |
13 |
|
T33 |
8 |
|
T37 |
5 |
auto[1] |
auto[0] |
14664 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
730 |
1 |
|
|
T20 |
24 |
|
T23 |
7 |
|
T69 |
6 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35627 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T20 |
14 |
|
T33 |
8 |
|
T37 |
9 |
auto[1] |
auto[0] |
14615 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
779 |
1 |
|
|
T20 |
24 |
|
T23 |
16 |
|
T69 |
5 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35467 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1212 |
1 |
|
|
T20 |
39 |
|
T67 |
1 |
|
T38 |
16 |
auto[1] |
auto[0] |
14672 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
722 |
1 |
|
|
T20 |
8 |
|
T21 |
17 |
|
T69 |
13 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35665 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1014 |
1 |
|
|
T20 |
18 |
|
T33 |
11 |
|
T37 |
10 |
auto[1] |
auto[0] |
14661 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
733 |
1 |
|
|
T20 |
19 |
|
T23 |
13 |
|
T69 |
7 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31896 |
1 |
|
|
T1 |
19 |
|
T14 |
75 |
|
T15 |
12 |
auto[0] |
auto[1] |
4783 |
1 |
|
|
T4 |
51 |
|
T20 |
13 |
|
T92 |
83 |
auto[1] |
auto[0] |
14655 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
739 |
1 |
|
|
T20 |
30 |
|
T23 |
13 |
|
T69 |
7 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35619 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1060 |
1 |
|
|
T20 |
16 |
|
T21 |
3 |
|
T36 |
8 |
auto[1] |
auto[0] |
14669 |
1 |
|
|
T2 |
57 |
|
T5 |
9 |
|
T6 |
10 |
auto[1] |
auto[1] |
725 |
1 |
|
|
T2 |
8 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35588 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1091 |
1 |
|
|
T20 |
9 |
|
T21 |
8 |
|
T36 |
7 |
auto[1] |
auto[0] |
14672 |
1 |
|
|
T2 |
61 |
|
T5 |
9 |
|
T6 |
12 |
auto[1] |
auto[1] |
722 |
1 |
|
|
T2 |
4 |
|
T5 |
1 |
|
T20 |
22 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35600 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1079 |
1 |
|
|
T20 |
9 |
|
T21 |
8 |
|
T36 |
6 |
auto[1] |
auto[0] |
14667 |
1 |
|
|
T2 |
59 |
|
T5 |
9 |
|
T6 |
12 |
auto[1] |
auto[1] |
727 |
1 |
|
|
T2 |
6 |
|
T5 |
1 |
|
T20 |
25 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35646 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1033 |
1 |
|
|
T15 |
1 |
|
T20 |
11 |
|
T21 |
7 |
auto[1] |
auto[0] |
14646 |
1 |
|
|
T2 |
57 |
|
T5 |
9 |
|
T6 |
11 |
auto[1] |
auto[1] |
748 |
1 |
|
|
T2 |
8 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35560 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1119 |
1 |
|
|
T20 |
7 |
|
T21 |
8 |
|
T93 |
2 |
auto[1] |
auto[0] |
14645 |
1 |
|
|
T2 |
57 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
749 |
1 |
|
|
T2 |
8 |
|
T20 |
14 |
|
T21 |
10 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35582 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1097 |
1 |
|
|
T15 |
1 |
|
T46 |
1 |
|
T20 |
12 |
auto[1] |
auto[0] |
14689 |
1 |
|
|
T2 |
56 |
|
T5 |
10 |
|
T6 |
11 |
auto[1] |
auto[1] |
705 |
1 |
|
|
T2 |
9 |
|
T6 |
1 |
|
T20 |
19 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35666 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1013 |
1 |
|
|
T20 |
9 |
|
T33 |
5 |
|
T37 |
9 |
auto[1] |
auto[0] |
14578 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
816 |
1 |
|
|
T20 |
27 |
|
T23 |
8 |
|
T69 |
11 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35715 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
964 |
1 |
|
|
T20 |
16 |
|
T33 |
11 |
|
T37 |
9 |
auto[1] |
auto[0] |
14574 |
1 |
|
|
T2 |
65 |
|
T5 |
10 |
|
T6 |
12 |
auto[1] |
auto[1] |
820 |
1 |
|
|
T20 |
29 |
|
T23 |
10 |
|
T69 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35186 |
1 |
|
|
T1 |
19 |
|
T4 |
51 |
|
T14 |
75 |
auto[0] |
auto[1] |
1493 |
1 |
|
|
T15 |
12 |
|
T46 |
15 |
|
T20 |
23 |
auto[1] |
auto[0] |
14425 |
1 |
|
|
T2 |
65 |
|
T20 |
443 |
|
T21 |
125 |
auto[1] |
auto[1] |
969 |
1 |
|
|
T5 |
10 |
|
T6 |
12 |
|
T20 |
14 |