Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94505354

1

T1

7650

T2

83797

T3

1663

auto[1]

1356755

1

T2

2058

T15

198

T16

1386

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94504903

1

T1

7650

T2

83307

T3

1663

auto[1]

1357206

1

T2

2548

T5

392

T16

1386

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6792838	1			T1	1785		T2	14537		T3	105
auto[IdleSt]	20772793	1			T1	2502		T2	5767		T3	1558
auto[ClkMuxSt]	34595	1			T1	19		T4	51		T5	4
auto[CntIncrSt]	34334	1			T1	19		T4	51		T5	4
auto[CntProgSt]	1762723	1			T1	382		T4	102		T5	77
auto[TransCheckSt]	26950	1			T1	19		T4	51		T5	4
auto[TokenHashSt]	36529142	1			T1	1266		T4	2997		T5	90
auto[FlashRmaSt]	26771	1			T1	19		T5	25		T11	1
auto[TokenCheck0St]	12380	1			T1	19		T5	4		T11	1
auto[TokenCheck1St]	9173	1			T1	19		T5	4		T11	1
auto[TransProgSt]	486459	1			T1	405		T5	143		T11	80
auto[PostTransSt]	12268408	1			T1	1196		T4	7802		T5	16137
auto[ScrapSt]	188802	1			T17	1		T18	3		T19	9
auto[EscalateSt]	6227866	1			T2	16608		T5	9715		T15	577
auto[InvalidSt]	10687008	1			T2	48937		T5	11516		T15	364

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1867	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10687008	1			T2	48937		T5	11516		T15	364
EscalateSt	6227866	1			T2	16608		T5	9715		T15	577
ScrapSt	188802	1			T17	1		T18	3		T19	9
PostTransSt	12268408	1			T1	1196		T4	7802		T5	16137
TransProgSt	486459	1			T1	405		T5	143		T11	80
TokenCheck1St	9173	1			T1	19		T5	4		T11	1
TokenCheck0St	12380	1			T1	19		T5	4		T11	1
FlashRmaSt	26771	1			T1	19		T5	25		T11	1
TokenHashSt	36529142	1			T1	1266		T4	2997		T5	90
TransCheckSt	26950	1			T1	19		T4	51		T5	4
CntProgSt	1762723	1			T1	382		T4	102		T5	77
CntIncrSt	34334	1			T1	19		T4	51		T5	4
ClkMuxSt	34595	1			T1	19		T4	51		T5	4
IdleSt	20772793	1			T1	2502		T2	5767		T3	1558
ResetSt	6792838	1			T1	1785		T2	14537		T3	105
arcs[ResetSt=>IdleSt]	52330	1			T1	19		T2	59		T3	1
arcs[IdleSt=>ScrapSt]	295	1			T17	1		T18	1		T19	3
arcs[IdleSt=>ClkMuxSt]	34395	1			T1	19		T4	51		T5	4
arcs[ClkMuxSt=>CntIncrSt]	34334	1			T1	19		T4	51		T5	4
arcs[CntIncrSt=>PostTransSt]	1786	1			T20	45		T23	10		T33	11
arcs[CntIncrSt=>CntProgSt]	32478	1			T1	19		T4	51		T5	4
arcs[CntProgSt=>PostTransSt]	4407	1			T16	20		T20	86		T21	17
arcs[CntProgSt=>TransCheckSt]	26950	1			T1	19		T4	51		T5	4
arcs[TransCheckSt=>PostTransSt]	3719	1			T14	42		T20	36		T57	32
arcs[TransCheckSt=>TokenHashSt]	23112	1			T1	19		T4	51		T5	4
arcs[TokenHashSt=>PostTransSt]	10008	1			T4	51		T14	14		T16	8
arcs[TokenHashSt=>FlashRmaSt]	12470	1			T1	19		T5	4		T11	1
arcs[FlashRmaSt=>TokenCheck0St]	12380	1			T1	19		T5	4		T11	1
arcs[TokenCheck0St=>PostTransSt]	3186	1			T14	10		T16	15		T20	35
arcs[TokenCheck0St=>TokenCheck1St]	9173	1			T1	19		T5	4		T11	1
arcs[TokenCheck1St=>PostTransSt]	652	1			T14	9		T20	2		T57	10
arcs[TransProgSt=>PostTransSt]	7616	1			T1	19		T5	4		T11	1
arcs[IdleSt=>EscalateSt]	213	1			T18	5		T58	7		T39	4
arcs[ClkMuxSt=>EscalateSt]	61	1			T18	1		T58	2		T59	2
arcs[CntIncrSt=>EscalateSt]	70	1			T18	2		T19	1		T58	2
arcs[CntProgSt=>EscalateSt]	1121	1			T18	31		T19	29		T58	24
arcs[TransCheckSt=>EscalateSt]	119	1			T58	1		T39	1		T62	8
arcs[TokenHashSt=>EscalateSt]	634	1			T18	5		T19	6		T58	14
arcs[FlashRmaSt=>EscalateSt]	90	1			T19	1		T58	3		T39	1
arcs[TokenCheck0St=>EscalateSt]	21	1			T58	1		T62	1		T63	1
arcs[TokenCheck1St=>EscalateSt]	146	1			T18	6		T19	2		T58	3
arcs[TransProgSt=>EscalateSt]	759	1			T18	13		T19	12		T58	16
arcs[PostTransSt=>EscalateSt]	4657	1			T16	20		T18	1		T19	1
arcs[InvalidSt=>EscalateSt]	13437	1			T2	47		T5	4		T15	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6792666	1			T1	1785		T2	14537		T3	105
auto[0]	auto[IdleSt]	20772652	1			T1	2502		T2	5767		T3	1558
auto[0]	auto[ClkMuxSt]	34558	1			T1	19		T4	51		T5	4
auto[0]	auto[CntIncrSt]	34288	1			T1	19		T4	51		T5	4
auto[0]	auto[CntProgSt]	1761965	1			T1	382		T4	102		T5	77
auto[0]	auto[TransCheckSt]	26868	1			T1	19		T4	51		T5	4
auto[0]	auto[TokenHashSt]	36528704	1			T1	1266		T4	2997		T5	90
auto[0]	auto[FlashRmaSt]	26719	1			T1	19		T5	25		T11	1
auto[0]	auto[TokenCheck0St]	12368	1			T1	19		T5	4		T11	1
auto[0]	auto[TokenCheck1St]	9075	1			T1	19		T5	4		T11	1
auto[0]	auto[TransProgSt]	485963	1			T1	405		T5	143		T11	80
auto[0]	auto[PostTransSt]	12266019	1			T1	1196		T4	7802		T5	16137
auto[0]	auto[ScrapSt]	188753	1			T17	1		T18	2		T19	8
auto[0]	auto[EscalateSt]	4882581	1			T2	14571		T5	9715		T15	381
auto[0]	auto[InvalidSt]	10680308	1			T2	48916		T5	11516		T15	362
auto[1]	auto[ResetSt]	172	1			T18	3		T19	1		T58	3
auto[1]	auto[IdleSt]	141	1			T18	3		T58	6		T39	3
auto[1]	auto[ClkMuxSt]	37	1			T58	1		T59	2		T39	2
auto[1]	auto[CntIncrSt]	46	1			T18	1		T58	2		T59	3
auto[1]	auto[CntProgSt]	758	1			T18	22		T19	23		T58	14
auto[1]	auto[TransCheckSt]	82	1			T58	1		T62	4		T63	5
auto[1]	auto[TokenHashSt]	438	1			T18	4		T19	5		T58	10
auto[1]	auto[FlashRmaSt]	52	1			T19	1		T58	1		T62	2
auto[1]	auto[TokenCheck0St]	12	1			T58	1		T62	1		T63	1
auto[1]	auto[TokenCheck1St]	98	1			T18	5		T19	1		T58	1
auto[1]	auto[TransProgSt]	496	1			T18	8		T19	10		T58	11
auto[1]	auto[PostTransSt]	2389	1			T16	11		T18	1		T19	1
auto[1]	auto[ScrapSt]	49	1			T18	1		T19	1		T58	1
auto[1]	auto[EscalateSt]	1345285	1			T2	2037		T15	196		T16	1372
auto[1]	auto[InvalidSt]	6700	1			T2	21		T15	2		T16	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6792663	1			T1	1785		T2	14537		T3	105
auto[0]	auto[IdleSt]	20772637	1			T1	2502		T2	5767		T3	1558
auto[0]	auto[ClkMuxSt]	34553	1			T1	19		T4	51		T5	4
auto[0]	auto[CntIncrSt]	34285	1			T1	19		T4	51		T5	4
auto[0]	auto[CntProgSt]	1761994	1			T1	382		T4	102		T5	77
auto[0]	auto[TransCheckSt]	26867	1			T1	19		T4	51		T5	4
auto[0]	auto[TokenHashSt]	36528729	1			T1	1266		T4	2997		T5	90
auto[0]	auto[FlashRmaSt]	26704	1			T1	19		T5	25		T11	1
auto[0]	auto[TokenCheck0St]	12362	1			T1	19		T5	4		T11	1
auto[0]	auto[TokenCheck1St]	9075	1			T1	19		T5	4		T11	1
auto[0]	auto[TransProgSt]	485947	1			T1	405		T5	143		T11	80
auto[0]	auto[PostTransSt]	12266061	1			T1	1196		T4	7802		T5	16137
auto[0]	auto[ScrapSt]	188751	1			T17	1		T18	3		T19	7
auto[0]	auto[EscalateSt]	4882137	1			T2	14086		T5	9327		T15	577
auto[0]	auto[InvalidSt]	10680271	1			T2	48911		T5	11512		T15	364
auto[1]	auto[ResetSt]	175	1			T18	4		T19	2		T58	4
auto[1]	auto[IdleSt]	156	1			T18	3		T58	5		T39	4
auto[1]	auto[ClkMuxSt]	42	1			T18	1		T58	2		T39	2
auto[1]	auto[CntIncrSt]	49	1			T18	2		T19	1		T58	1
auto[1]	auto[CntProgSt]	729	1			T18	21		T19	18		T58	17
auto[1]	auto[TransCheckSt]	83	1			T58	1		T39	1		T62	6
auto[1]	auto[TokenHashSt]	413	1			T18	5		T19	2		T58	10
auto[1]	auto[FlashRmaSt]	67	1			T19	1		T58	2		T39	1
auto[1]	auto[TokenCheck0St]	18	1			T58	1		T62	1		T209	1
auto[1]	auto[TokenCheck1St]	98	1			T18	3		T19	2		T58	2
auto[1]	auto[TransProgSt]	512	1			T18	9		T19	7		T58	11
auto[1]	auto[PostTransSt]	2347	1			T16	9		T18	1		T20	44
auto[1]	auto[ScrapSt]	51	1			T19	2		T58	1		T62	1
auto[1]	auto[EscalateSt]	1345729	1			T2	2522		T5	388		T16	1372
auto[1]	auto[InvalidSt]	6737	1			T2	26		T5	4		T16	5