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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.89 95.95 93.31 100.00 98.55 98.76 96.29


Total test records in report: 999
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T820 /workspace/coverage/default/36.lc_ctrl_jtag_access.2584851901 May 26 02:54:20 PM PDT 24 May 26 02:54:36 PM PDT 24 533166610 ps
T821 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.459946815 May 26 02:53:10 PM PDT 24 May 26 02:53:15 PM PDT 24 149224816 ps
T822 /workspace/coverage/default/2.lc_ctrl_jtag_priority.323044786 May 26 02:52:56 PM PDT 24 May 26 02:53:00 PM PDT 24 238683367 ps
T823 /workspace/coverage/default/23.lc_ctrl_prog_failure.3995414958 May 26 02:53:58 PM PDT 24 May 26 02:54:04 PM PDT 24 98386162 ps
T824 /workspace/coverage/default/19.lc_ctrl_jtag_errors.3367141150 May 26 02:53:51 PM PDT 24 May 26 02:54:26 PM PDT 24 5641067792 ps
T825 /workspace/coverage/default/4.lc_ctrl_sec_mubi.2649175704 May 26 02:53:07 PM PDT 24 May 26 02:53:26 PM PDT 24 756666619 ps
T826 /workspace/coverage/default/26.lc_ctrl_smoke.3376618449 May 26 02:54:03 PM PDT 24 May 26 02:54:10 PM PDT 24 88167297 ps
T827 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2966143867 May 26 02:54:03 PM PDT 24 May 26 02:54:16 PM PDT 24 426690152 ps
T828 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3495714186 May 26 02:54:09 PM PDT 24 May 26 02:54:15 PM PDT 24 22834688 ps
T76 /workspace/coverage/default/34.lc_ctrl_smoke.1898981151 May 26 02:54:11 PM PDT 24 May 26 02:54:17 PM PDT 24 72924042 ps
T829 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2169837181 May 26 02:54:35 PM PDT 24 May 26 02:54:51 PM PDT 24 1822136791 ps
T830 /workspace/coverage/default/41.lc_ctrl_alert_test.3378348879 May 26 02:54:48 PM PDT 24 May 26 02:54:51 PM PDT 24 75286956 ps
T831 /workspace/coverage/default/33.lc_ctrl_prog_failure.319723036 May 26 02:54:13 PM PDT 24 May 26 02:54:18 PM PDT 24 188645531 ps
T832 /workspace/coverage/default/30.lc_ctrl_errors.2879737390 May 26 02:54:02 PM PDT 24 May 26 02:54:18 PM PDT 24 273092635 ps
T833 /workspace/coverage/default/3.lc_ctrl_state_failure.3386383006 May 26 02:52:58 PM PDT 24 May 26 02:53:28 PM PDT 24 243579455 ps
T834 /workspace/coverage/default/45.lc_ctrl_state_failure.779313737 May 26 02:54:45 PM PDT 24 May 26 02:55:14 PM PDT 24 416345114 ps
T835 /workspace/coverage/default/32.lc_ctrl_prog_failure.456766692 May 26 02:54:10 PM PDT 24 May 26 02:54:17 PM PDT 24 88669709 ps
T836 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2357283600 May 26 02:53:44 PM PDT 24 May 26 02:53:54 PM PDT 24 398613481 ps
T837 /workspace/coverage/default/26.lc_ctrl_alert_test.2002499837 May 26 02:54:00 PM PDT 24 May 26 02:54:04 PM PDT 24 20931657 ps
T838 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2215857205 May 26 02:54:52 PM PDT 24 May 26 02:54:56 PM PDT 24 45195945 ps
T839 /workspace/coverage/default/24.lc_ctrl_alert_test.835890554 May 26 02:53:57 PM PDT 24 May 26 02:54:01 PM PDT 24 31589015 ps
T840 /workspace/coverage/default/45.lc_ctrl_smoke.3302576767 May 26 02:54:48 PM PDT 24 May 26 02:54:58 PM PDT 24 528427972 ps
T841 /workspace/coverage/default/15.lc_ctrl_sec_mubi.3472473393 May 26 02:53:25 PM PDT 24 May 26 02:53:41 PM PDT 24 311282357 ps
T842 /workspace/coverage/default/0.lc_ctrl_state_post_trans.1895631902 May 26 02:52:39 PM PDT 24 May 26 02:52:50 PM PDT 24 98090227 ps
T843 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2194978182 May 26 02:53:16 PM PDT 24 May 26 02:53:33 PM PDT 24 2502807554 ps
T844 /workspace/coverage/default/5.lc_ctrl_prog_failure.3855873784 May 26 02:53:04 PM PDT 24 May 26 02:53:09 PM PDT 24 95673004 ps
T845 /workspace/coverage/default/40.lc_ctrl_security_escalation.381858765 May 26 02:54:42 PM PDT 24 May 26 02:54:57 PM PDT 24 3173373009 ps
T846 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2388333566 May 26 02:53:25 PM PDT 24 May 26 02:53:45 PM PDT 24 2179364007 ps
T847 /workspace/coverage/default/25.lc_ctrl_state_failure.3191497229 May 26 02:54:01 PM PDT 24 May 26 02:54:28 PM PDT 24 919079345 ps
T848 /workspace/coverage/default/13.lc_ctrl_prog_failure.4085400642 May 26 02:53:29 PM PDT 24 May 26 02:53:37 PM PDT 24 72737921 ps
T849 /workspace/coverage/default/38.lc_ctrl_smoke.670861543 May 26 02:54:22 PM PDT 24 May 26 02:54:27 PM PDT 24 94635327 ps
T850 /workspace/coverage/default/28.lc_ctrl_stress_all.1497494927 May 26 02:54:04 PM PDT 24 May 26 02:54:57 PM PDT 24 10747877534 ps
T851 /workspace/coverage/default/43.lc_ctrl_sec_mubi.548014342 May 26 02:54:48 PM PDT 24 May 26 02:55:11 PM PDT 24 1121777522 ps
T852 /workspace/coverage/default/20.lc_ctrl_security_escalation.3386583324 May 26 02:53:57 PM PDT 24 May 26 02:54:11 PM PDT 24 875888598 ps
T853 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2392133212 May 26 02:54:03 PM PDT 24 May 26 02:54:06 PM PDT 24 234493864 ps
T854 /workspace/coverage/default/15.lc_ctrl_prog_failure.1077121369 May 26 02:53:27 PM PDT 24 May 26 02:53:34 PM PDT 24 404569112 ps
T208 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2465707109 May 26 02:52:44 PM PDT 24 May 26 02:52:47 PM PDT 24 30275157 ps
T855 /workspace/coverage/default/47.lc_ctrl_stress_all.4183866786 May 26 02:54:54 PM PDT 24 May 26 02:56:31 PM PDT 24 2482942086 ps
T856 /workspace/coverage/default/0.lc_ctrl_stress_all.1743669785 May 26 02:53:06 PM PDT 24 May 26 02:57:08 PM PDT 24 7749452777 ps
T857 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4169644887 May 26 02:53:18 PM PDT 24 May 26 02:53:32 PM PDT 24 916570016 ps
T858 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2690193880 May 26 02:54:24 PM PDT 24 May 26 02:54:35 PM PDT 24 419075049 ps
T859 /workspace/coverage/default/42.lc_ctrl_sec_mubi.1623745310 May 26 02:54:41 PM PDT 24 May 26 02:54:57 PM PDT 24 1259974468 ps
T860 /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1821699667 May 26 02:53:01 PM PDT 24 May 26 02:53:08 PM PDT 24 1556869496 ps
T861 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1162948955 May 26 02:53:29 PM PDT 24 May 26 02:53:46 PM PDT 24 550199643 ps
T862 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.888664860 May 26 02:53:13 PM PDT 24 May 26 02:53:36 PM PDT 24 1508137384 ps
T863 /workspace/coverage/default/5.lc_ctrl_jtag_priority.1195122119 May 26 02:53:06 PM PDT 24 May 26 02:53:15 PM PDT 24 1864143765 ps
T864 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2633099700 May 26 02:53:23 PM PDT 24 May 26 02:53:35 PM PDT 24 2958350223 ps
T865 /workspace/coverage/default/18.lc_ctrl_sec_mubi.3940223708 May 26 02:53:27 PM PDT 24 May 26 02:53:48 PM PDT 24 517476390 ps
T866 /workspace/coverage/default/9.lc_ctrl_stress_all.194582347 May 26 02:53:26 PM PDT 24 May 26 02:55:22 PM PDT 24 2969976446 ps
T867 /workspace/coverage/default/6.lc_ctrl_jtag_priority.285248651 May 26 02:53:13 PM PDT 24 May 26 02:53:29 PM PDT 24 1943815448 ps
T868 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2677875924 May 26 02:53:27 PM PDT 24 May 26 02:54:20 PM PDT 24 4644590667 ps
T869 /workspace/coverage/default/5.lc_ctrl_sec_mubi.2867383230 May 26 02:53:05 PM PDT 24 May 26 02:53:16 PM PDT 24 269616979 ps
T870 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.916902611 May 26 02:53:11 PM PDT 24 May 26 02:53:23 PM PDT 24 744435274 ps
T871 /workspace/coverage/default/30.lc_ctrl_security_escalation.1703245755 May 26 02:54:08 PM PDT 24 May 26 02:54:22 PM PDT 24 1203887243 ps
T872 /workspace/coverage/default/2.lc_ctrl_state_failure.1714494939 May 26 02:52:38 PM PDT 24 May 26 02:53:13 PM PDT 24 299648346 ps
T873 /workspace/coverage/default/32.lc_ctrl_state_failure.815633181 May 26 02:54:19 PM PDT 24 May 26 02:54:47 PM PDT 24 1421882835 ps
T874 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3997398707 May 26 02:53:27 PM PDT 24 May 26 02:54:34 PM PDT 24 10830421097 ps
T875 /workspace/coverage/default/19.lc_ctrl_smoke.1901443559 May 26 02:53:54 PM PDT 24 May 26 02:53:58 PM PDT 24 18330080 ps
T876 /workspace/coverage/default/38.lc_ctrl_state_post_trans.3824589793 May 26 02:54:22 PM PDT 24 May 26 02:54:32 PM PDT 24 87927584 ps
T877 /workspace/coverage/default/0.lc_ctrl_smoke.3093754512 May 26 02:52:40 PM PDT 24 May 26 02:52:46 PM PDT 24 66824209 ps
T878 /workspace/coverage/default/48.lc_ctrl_stress_all.2603028427 May 26 02:54:51 PM PDT 24 May 26 02:56:28 PM PDT 24 3250832206 ps
T879 /workspace/coverage/default/0.lc_ctrl_prog_failure.2528352555 May 26 02:52:41 PM PDT 24 May 26 02:52:47 PM PDT 24 60814180 ps
T880 /workspace/coverage/default/1.lc_ctrl_alert_test.400206288 May 26 02:52:50 PM PDT 24 May 26 02:52:52 PM PDT 24 62880975 ps
T881 /workspace/coverage/default/29.lc_ctrl_alert_test.3270218590 May 26 02:54:06 PM PDT 24 May 26 02:54:10 PM PDT 24 25802965 ps
T104 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4042520757 May 26 02:52:18 PM PDT 24 May 26 02:52:24 PM PDT 24 211907115 ps
T108 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.821094451 May 26 02:52:24 PM PDT 24 May 26 02:52:28 PM PDT 24 39347598 ps
T109 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3768120380 May 26 02:52:33 PM PDT 24 May 26 02:52:37 PM PDT 24 150034363 ps
T96 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.723837665 May 26 02:52:39 PM PDT 24 May 26 02:52:44 PM PDT 24 359011048 ps
T131 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3990809153 May 26 02:52:27 PM PDT 24 May 26 02:52:33 PM PDT 24 2041508962 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3256960647 May 26 02:52:18 PM PDT 24 May 26 02:52:24 PM PDT 24 97659758 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.817092026 May 26 02:52:24 PM PDT 24 May 26 02:52:28 PM PDT 24 194946689 ps
T99 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1898768503 May 26 02:52:14 PM PDT 24 May 26 02:52:18 PM PDT 24 71163880 ps
T883 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3053932711 May 26 02:52:38 PM PDT 24 May 26 02:52:42 PM PDT 24 12083114 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3622246855 May 26 02:52:22 PM PDT 24 May 26 02:52:27 PM PDT 24 70432211 ps
T186 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2820057483 May 26 02:52:41 PM PDT 24 May 26 02:52:45 PM PDT 24 11867406 ps
T141 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1892325885 May 26 02:52:24 PM PDT 24 May 26 02:52:28 PM PDT 24 46857722 ps
T187 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1668366450 May 26 02:52:48 PM PDT 24 May 26 02:52:55 PM PDT 24 12210189 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1152386563 May 26 02:52:33 PM PDT 24 May 26 02:52:44 PM PDT 24 503365767 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2987470451 May 26 02:52:19 PM PDT 24 May 26 02:52:26 PM PDT 24 225665521 ps
T129 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2870104145 May 26 02:52:39 PM PDT 24 May 26 02:52:43 PM PDT 24 609206909 ps
T885 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2714968960 May 26 02:52:16 PM PDT 24 May 26 02:52:21 PM PDT 24 46263330 ps
T130 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3670160392 May 26 02:52:31 PM PDT 24 May 26 02:52:35 PM PDT 24 103443588 ps
T198 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.265191672 May 26 02:52:39 PM PDT 24 May 26 02:52:44 PM PDT 24 38616972 ps
T100 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.138553182 May 26 02:52:25 PM PDT 24 May 26 02:52:34 PM PDT 24 1070008616 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1788895633 May 26 02:52:27 PM PDT 24 May 26 02:52:32 PM PDT 24 411517020 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2943784803 May 26 02:52:23 PM PDT 24 May 26 02:52:40 PM PDT 24 1129905969 ps
T101 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.74082700 May 26 02:52:24 PM PDT 24 May 26 02:52:29 PM PDT 24 67650471 ps
T97 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3349009656 May 26 02:52:38 PM PDT 24 May 26 02:52:44 PM PDT 24 398372762 ps
T199 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3876917756 May 26 02:52:38 PM PDT 24 May 26 02:52:42 PM PDT 24 18503458 ps
T200 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.949355133 May 26 02:52:35 PM PDT 24 May 26 02:52:39 PM PDT 24 31378934 ps
T98 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3374329615 May 26 02:52:33 PM PDT 24 May 26 02:52:39 PM PDT 24 75613388 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.992569146 May 26 02:52:17 PM PDT 24 May 26 02:52:23 PM PDT 24 46713575 ps
T142 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3759005308 May 26 02:52:15 PM PDT 24 May 26 02:52:20 PM PDT 24 21029493 ps
T202 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.614392997 May 26 02:52:29 PM PDT 24 May 26 02:52:32 PM PDT 24 21469421 ps
T888 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3191658397 May 26 02:52:35 PM PDT 24 May 26 02:52:38 PM PDT 24 15085311 ps
T203 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3925540380 May 26 02:52:42 PM PDT 24 May 26 02:52:45 PM PDT 24 36866097 ps
T156 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2569647147 May 26 02:52:34 PM PDT 24 May 26 02:52:38 PM PDT 24 63984572 ps
T166 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2393055456 May 26 02:52:37 PM PDT 24 May 26 02:52:41 PM PDT 24 102317143 ps
T188 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1054219309 May 26 02:52:15 PM PDT 24 May 26 02:52:20 PM PDT 24 126171086 ps
T157 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1632452217 May 26 02:52:35 PM PDT 24 May 26 02:52:38 PM PDT 24 62229954 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3590250921 May 26 02:52:28 PM PDT 24 May 26 02:52:32 PM PDT 24 206670612 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.708882822 May 26 02:52:14 PM PDT 24 May 26 02:52:18 PM PDT 24 32681436 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2566421456 May 26 02:52:18 PM PDT 24 May 26 02:52:51 PM PDT 24 6583924617 ps
T158 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3579294084 May 26 02:52:23 PM PDT 24 May 26 02:52:28 PM PDT 24 79071256 ps
T167 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3285431457 May 26 02:52:18 PM PDT 24 May 26 02:52:25 PM PDT 24 210735145 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.853050369 May 26 02:52:31 PM PDT 24 May 26 02:52:43 PM PDT 24 2957673649 ps
T892 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2477264135 May 26 02:52:39 PM PDT 24 May 26 02:52:43 PM PDT 24 14342497 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2614589934 May 26 02:52:18 PM PDT 24 May 26 02:52:24 PM PDT 24 121523946 ps
T144 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2771767980 May 26 02:52:18 PM PDT 24 May 26 02:52:25 PM PDT 24 253509615 ps
T110 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.898894883 May 26 02:52:36 PM PDT 24 May 26 02:52:42 PM PDT 24 159827314 ps
T189 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2823518561 May 26 02:52:17 PM PDT 24 May 26 02:52:23 PM PDT 24 18889437 ps
T894 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1708139627 May 26 02:52:39 PM PDT 24 May 26 02:52:43 PM PDT 24 38238483 ps
T102 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.686868669 May 26 02:52:40 PM PDT 24 May 26 02:52:44 PM PDT 24 80042268 ps
T168 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1021305581 May 26 02:52:36 PM PDT 24 May 26 02:52:40 PM PDT 24 38831939 ps
T895 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2871099682 May 26 02:52:31 PM PDT 24 May 26 02:52:40 PM PDT 24 2865439558 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.167808811 May 26 02:52:26 PM PDT 24 May 26 02:52:29 PM PDT 24 55040797 ps
T124 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4107781821 May 26 02:52:34 PM PDT 24 May 26 02:52:39 PM PDT 24 123174386 ps
T105 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3217583573 May 26 02:52:38 PM PDT 24 May 26 02:52:42 PM PDT 24 65044744 ps
T103 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.418994648 May 26 02:52:38 PM PDT 24 May 26 02:52:44 PM PDT 24 83239055 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1760435695 May 26 02:52:17 PM PDT 24 May 26 02:52:23 PM PDT 24 105595801 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3036679321 May 26 02:52:22 PM PDT 24 May 26 02:52:29 PM PDT 24 269380071 ps
T113 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2725380348 May 26 02:52:31 PM PDT 24 May 26 02:52:36 PM PDT 24 127910698 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.294976442 May 26 02:52:17 PM PDT 24 May 26 02:52:23 PM PDT 24 338232693 ps
T900 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.788408327 May 26 02:52:17 PM PDT 24 May 26 02:52:23 PM PDT 24 68906585 ps
T106 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4269597776 May 26 02:52:36 PM PDT 24 May 26 02:52:42 PM PDT 24 357224895 ps
T107 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3064465438 May 26 02:52:38 PM PDT 24 May 26 02:52:44 PM PDT 24 42486950 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.5681322 May 26 02:52:15 PM PDT 24 May 26 02:52:21 PM PDT 24 23433084 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.261785710 May 26 02:52:16 PM PDT 24 May 26 02:52:21 PM PDT 24 14282067 ps
T190 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3548662675 May 26 02:52:38 PM PDT 24 May 26 02:52:41 PM PDT 24 28725345 ps
T120 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3859973520 May 26 02:52:16 PM PDT 24 May 26 02:52:22 PM PDT 24 259927376 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.80725474 May 26 02:52:34 PM PDT 24 May 26 02:52:38 PM PDT 24 179470263 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.814332334 May 26 02:52:31 PM PDT 24 May 26 02:52:35 PM PDT 24 105959272 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.74700097 May 26 02:52:24 PM PDT 24 May 26 02:52:29 PM PDT 24 960461805 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3222883790 May 26 02:52:16 PM PDT 24 May 26 02:52:34 PM PDT 24 498204879 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3770393885 May 26 02:52:34 PM PDT 24 May 26 02:52:38 PM PDT 24 24304113 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3418284124 May 26 02:52:14 PM PDT 24 May 26 02:52:21 PM PDT 24 497321101 ps
T909 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3801058435 May 26 02:52:50 PM PDT 24 May 26 02:52:54 PM PDT 24 179396939 ps
T145 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2129610747 May 26 02:52:19 PM PDT 24 May 26 02:52:25 PM PDT 24 117414908 ps
T910 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1547728567 May 26 02:52:15 PM PDT 24 May 26 02:52:21 PM PDT 24 412433170 ps
T911 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3803391818 May 26 02:52:19 PM PDT 24 May 26 02:52:44 PM PDT 24 10154562409 ps
T114 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2232117421 May 26 02:52:39 PM PDT 24 May 26 02:52:45 PM PDT 24 205360593 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2648984958 May 26 02:52:22 PM PDT 24 May 26 02:52:32 PM PDT 24 997687058 ps
T913 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.688780916 May 26 02:52:17 PM PDT 24 May 26 02:52:23 PM PDT 24 37798535 ps
T118 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.811701295 May 26 02:52:32 PM PDT 24 May 26 02:52:35 PM PDT 24 88363717 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.691571970 May 26 02:52:32 PM PDT 24 May 26 02:52:49 PM PDT 24 2284599338 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1105892742 May 26 02:52:15 PM PDT 24 May 26 02:52:20 PM PDT 24 65527870 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2586799104 May 26 02:52:36 PM PDT 24 May 26 02:52:40 PM PDT 24 145197064 ps
T917 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2588123220 May 26 02:52:40 PM PDT 24 May 26 02:52:45 PM PDT 24 377605588 ps
T918 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.299171340 May 26 02:52:23 PM PDT 24 May 26 02:52:27 PM PDT 24 21278290 ps
T919 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3868949715 May 26 02:52:32 PM PDT 24 May 26 02:52:35 PM PDT 24 16767149 ps
T920 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2907830942 May 26 02:52:34 PM PDT 24 May 26 02:52:37 PM PDT 24 26985866 ps
T921 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.174778756 May 26 02:52:21 PM PDT 24 May 26 02:52:28 PM PDT 24 633363310 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1607701179 May 26 02:52:17 PM PDT 24 May 26 02:52:23 PM PDT 24 141184113 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1007025111 May 26 02:52:30 PM PDT 24 May 26 02:52:35 PM PDT 24 254248651 ps
T924 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2991906055 May 26 02:52:48 PM PDT 24 May 26 02:52:50 PM PDT 24 23698863 ps
T191 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3883351330 May 26 02:52:33 PM PDT 24 May 26 02:52:37 PM PDT 24 20867746 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4262079986 May 26 02:52:29 PM PDT 24 May 26 02:52:33 PM PDT 24 29919788 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1148794969 May 26 02:52:15 PM PDT 24 May 26 02:52:20 PM PDT 24 85389784 ps
T119 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2802410983 May 26 02:52:31 PM PDT 24 May 26 02:52:36 PM PDT 24 85199653 ps
T927 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4104202536 May 26 02:52:20 PM PDT 24 May 26 02:52:26 PM PDT 24 66832695 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2309026350 May 26 02:52:21 PM PDT 24 May 26 02:52:27 PM PDT 24 365195118 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1563867932 May 26 02:52:37 PM PDT 24 May 26 02:52:40 PM PDT 24 43802442 ps
T930 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2593881321 May 26 02:52:36 PM PDT 24 May 26 02:52:39 PM PDT 24 68144721 ps
T192 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2496992566 May 26 02:52:33 PM PDT 24 May 26 02:52:37 PM PDT 24 17181836 ps
T931 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1573192382 May 26 02:52:43 PM PDT 24 May 26 02:52:47 PM PDT 24 175193127 ps
T932 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.914375001 May 26 02:52:40 PM PDT 24 May 26 02:52:44 PM PDT 24 405689645 ps
T933 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1988494746 May 26 02:52:27 PM PDT 24 May 26 02:52:37 PM PDT 24 676231879 ps
T934 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1054016227 May 26 02:52:35 PM PDT 24 May 26 02:52:39 PM PDT 24 65918344 ps
T935 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2708535579 May 26 02:52:36 PM PDT 24 May 26 02:52:39 PM PDT 24 58636069 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2931490929 May 26 02:52:34 PM PDT 24 May 26 02:52:39 PM PDT 24 92630957 ps
T937 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1678942303 May 26 02:52:38 PM PDT 24 May 26 02:52:42 PM PDT 24 56670148 ps
T193 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3842813208 May 26 02:52:15 PM PDT 24 May 26 02:52:19 PM PDT 24 33688237 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1464600365 May 26 02:52:18 PM PDT 24 May 26 02:52:24 PM PDT 24 583840160 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2131540339 May 26 02:52:30 PM PDT 24 May 26 02:52:32 PM PDT 24 32327728 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1015018566 May 26 02:52:23 PM PDT 24 May 26 02:52:27 PM PDT 24 12484533 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.364552704 May 26 02:52:14 PM PDT 24 May 26 02:52:21 PM PDT 24 612228596 ps
T942 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2574719373 May 26 02:52:38 PM PDT 24 May 26 02:52:42 PM PDT 24 23044114 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.421063714 May 26 02:52:32 PM PDT 24 May 26 02:52:36 PM PDT 24 64911629 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1423563977 May 26 02:52:26 PM PDT 24 May 26 02:52:30 PM PDT 24 408161891 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1065449843 May 26 02:52:35 PM PDT 24 May 26 02:52:49 PM PDT 24 3476861991 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1163410969 May 26 02:52:33 PM PDT 24 May 26 02:52:48 PM PDT 24 2128550110 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2610858234 May 26 02:52:21 PM PDT 24 May 26 02:52:27 PM PDT 24 93752051 ps
T194 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3660833724 May 26 02:52:16 PM PDT 24 May 26 02:52:21 PM PDT 24 13234980 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3228204957 May 26 02:52:34 PM PDT 24 May 26 02:52:38 PM PDT 24 28921969 ps
T949 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.358453044 May 26 02:52:38 PM PDT 24 May 26 02:52:45 PM PDT 24 414980679 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.784257411 May 26 02:52:21 PM PDT 24 May 26 02:52:26 PM PDT 24 119481271 ps
T951 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1145424121 May 26 02:52:28 PM PDT 24 May 26 02:52:32 PM PDT 24 796779671 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1941057126 May 26 02:52:31 PM PDT 24 May 26 02:52:34 PM PDT 24 50075477 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1735926313 May 26 02:52:31 PM PDT 24 May 26 02:52:35 PM PDT 24 224321995 ps
T953 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1225218179 May 26 02:52:24 PM PDT 24 May 26 02:52:29 PM PDT 24 133475774 ps
T954 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1378141092 May 26 02:52:38 PM PDT 24 May 26 02:52:42 PM PDT 24 21666737 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.990846892 May 26 02:52:19 PM PDT 24 May 26 02:52:29 PM PDT 24 1505907128 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4274544258 May 26 02:52:38 PM PDT 24 May 26 02:52:45 PM PDT 24 51927256 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4200458836 May 26 02:52:24 PM PDT 24 May 26 02:52:28 PM PDT 24 13434060 ps
T958 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.154492285 May 26 02:52:15 PM PDT 24 May 26 02:52:20 PM PDT 24 235424840 ps
T112 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3921412444 May 26 02:52:38 PM PDT 24 May 26 02:52:45 PM PDT 24 422377322 ps
T122 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1046881687 May 26 02:52:14 PM PDT 24 May 26 02:52:19 PM PDT 24 219819692 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3579353187 May 26 02:52:34 PM PDT 24 May 26 02:52:37 PM PDT 24 17123715 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1438456168 May 26 02:52:43 PM PDT 24 May 26 02:52:47 PM PDT 24 31875193 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1817099370 May 26 02:52:16 PM PDT 24 May 26 02:52:27 PM PDT 24 741583167 ps
T123 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2644849015 May 26 02:52:28 PM PDT 24 May 26 02:52:33 PM PDT 24 208438246 ps
T195 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3431889354 May 26 02:52:27 PM PDT 24 May 26 02:52:31 PM PDT 24 37874795 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4082202230 May 26 02:52:33 PM PDT 24 May 26 02:52:36 PM PDT 24 114106602 ps
T963 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2577746585 May 26 02:52:24 PM PDT 24 May 26 02:52:29 PM PDT 24 87188595 ps
T964 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3624262731 May 26 02:52:28 PM PDT 24 May 26 02:53:02 PM PDT 24 9108504442 ps
T121 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.289516980 May 26 02:52:44 PM PDT 24 May 26 02:52:49 PM PDT 24 152758460 ps
T965 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2344561663 May 26 02:52:39 PM PDT 24 May 26 02:52:43 PM PDT 24 26888115 ps
T966 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1578508824 May 26 02:52:22 PM PDT 24 May 26 02:52:27 PM PDT 24 220147517 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3767423144 May 26 02:52:21 PM PDT 24 May 26 02:52:26 PM PDT 24 15994777 ps
T196 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.698580108 May 26 02:52:38 PM PDT 24 May 26 02:52:42 PM PDT 24 14405440 ps
T111 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3190572660 May 26 02:52:43 PM PDT 24 May 26 02:52:50 PM PDT 24 1064102719 ps
T968 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2897552073 May 26 02:52:22 PM PDT 24 May 26 02:52:28 PM PDT 24 509338768 ps
T127 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3983083149 May 26 02:52:32 PM PDT 24 May 26 02:52:37 PM PDT 24 229719966 ps
T969 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3523637160 May 26 02:52:37 PM PDT 24 May 26 02:52:40 PM PDT 24 26206203 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3930710972 May 26 02:52:15 PM PDT 24 May 26 02:52:21 PM PDT 24 116137913 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3392808579 May 26 02:52:32 PM PDT 24 May 26 02:52:35 PM PDT 24 494106359 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3899367544 May 26 02:52:31 PM PDT 24 May 26 02:52:34 PM PDT 24 107820390 ps
T973 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3381366797 May 26 02:52:24 PM PDT 24 May 26 02:52:29 PM PDT 24 106391102 ps
T974 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3768484380 May 26 02:52:24 PM PDT 24 May 26 02:52:28 PM PDT 24 26041778 ps
T975 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3107725400 May 26 02:52:35 PM PDT 24 May 26 02:52:40 PM PDT 24 148438541 ps
T197 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.354709528 May 26 02:52:36 PM PDT 24 May 26 02:52:39 PM PDT 24 171737636 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.828767637 May 26 02:52:24 PM PDT 24 May 26 02:52:58 PM PDT 24 12952788755 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1642380880 May 26 02:52:33 PM PDT 24 May 26 02:52:37 PM PDT 24 112967506 ps
T978 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1010196446 May 26 02:52:24 PM PDT 24 May 26 02:52:30 PM PDT 24 214850922 ps
T979 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2530122833 May 26 02:52:37 PM PDT 24 May 26 02:52:41 PM PDT 24 335887507 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4086792879 May 26 02:52:34 PM PDT 24 May 26 02:52:37 PM PDT 24 16808683 ps
T117 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.656955567 May 26 02:52:08 PM PDT 24 May 26 02:52:12 PM PDT 24 529988192 ps
T981 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3751961135 May 26 02:52:37 PM PDT 24 May 26 02:52:41 PM PDT 24 25321473 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3391434475 May 26 02:52:32 PM PDT 24 May 26 02:52:38 PM PDT 24 133371565 ps
T983 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2349612219 May 26 02:52:41 PM PDT 24 May 26 02:52:46 PM PDT 24 41666296 ps
T984 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2548755557 May 26 02:52:30 PM PDT 24 May 26 02:52:34 PM PDT 24 249083401 ps
T985 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3487202745 May 26 02:52:38 PM PDT 24 May 26 02:52:43 PM PDT 24 65880986 ps
T986 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3563888939 May 26 02:52:30 PM PDT 24 May 26 02:52:34 PM PDT 24 243609850 ps
T115 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1034574328 May 26 02:52:36 PM PDT 24 May 26 02:52:41 PM PDT 24 396954581 ps
T987 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.935138646 May 26 02:52:34 PM PDT 24 May 26 02:52:48 PM PDT 24 535192138 ps
T988 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2829123378 May 26 02:52:36 PM PDT 24 May 26 02:52:40 PM PDT 24 47617367 ps
T989 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.809543075 May 26 02:52:31 PM PDT 24 May 26 02:52:34 PM PDT 24 18178195 ps
T990 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.820541110 May 26 02:52:34 PM PDT 24 May 26 02:52:39 PM PDT 24 102521449 ps
T991 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1082275597 May 26 02:52:34 PM PDT 24 May 26 02:52:42 PM PDT 24 422367964 ps
T992 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3445748772 May 26 02:52:30 PM PDT 24 May 26 02:52:32 PM PDT 24 22679511 ps
T993 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128414362 May 26 02:52:15 PM PDT 24 May 26 02:52:24 PM PDT 24 4825563410 ps
T994 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2636386460 May 26 02:52:31 PM PDT 24 May 26 02:52:34 PM PDT 24 179901711 ps
T116 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3658730764 May 26 02:52:26 PM PDT 24 May 26 02:52:31 PM PDT 24 286869670 ps
T995 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.163524268 May 26 02:52:33 PM PDT 24 May 26 02:52:37 PM PDT 24 103191812 ps
T996 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2473905462 May 26 02:52:17 PM PDT 24 May 26 02:52:25 PM PDT 24 191188722 ps
T997 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4143036089 May 26 02:52:18 PM PDT 24 May 26 02:52:25 PM PDT 24 14494581 ps
T998 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2590367808 May 26 02:52:35 PM PDT 24 May 26 02:52:40 PM PDT 24 76633888 ps
T126 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2913308359 May 26 02:52:36 PM PDT 24 May 26 02:52:41 PM PDT 24 169962109 ps
T999 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2301450479 May 26 02:52:23 PM PDT 24 May 26 02:52:37 PM PDT 24 431875150 ps

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1196677403
Short name T14
Test name
Test status
Simulation time 1282858701 ps
CPU time 10.66 seconds
Started May 26 02:53:59 PM PDT 24
Finished May 26 02:54:13 PM PDT 24
Peak memory 218152 kb
Host smart-e69a7a52-2444-4ff5-b4de-99b19cb1dc82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196677403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1196677403
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3879387831
Short name T20
Test name
Test status
Simulation time 60126458242 ps
CPU time 988.93 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 03:10:42 PM PDT 24
Peak memory 333140 kb
Host smart-eea14803-1eb5-440c-8ed4-e17475d6b261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3879387831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3879387831
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3445340907
Short name T58
Test name
Test status
Simulation time 5182182531 ps
CPU time 12.95 seconds
Started May 26 02:54:16 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 218172 kb
Host smart-a8cc70e3-ead0-4b62-b8c9-cce36ce3d7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445340907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3445340907
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1674551464
Short name T16
Test name
Test status
Simulation time 347446639 ps
CPU time 11.48 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:53:44 PM PDT 24
Peak memory 218364 kb
Host smart-136b5e5d-1815-45ea-919d-5724683e93cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674551464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1674551464
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.138553182
Short name T100
Test name
Test status
Simulation time 1070008616 ps
CPU time 6.8 seconds
Started May 26 02:52:25 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 217800 kb
Host smart-74474184-8679-44a8-91af-bac00c4a7e0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138553
182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.138553182
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1355599945
Short name T21
Test name
Test status
Simulation time 6889087397 ps
CPU time 250.36 seconds
Started May 26 02:54:43 PM PDT 24
Finished May 26 02:58:55 PM PDT 24
Peak memory 273020 kb
Host smart-9cf3701b-1462-44d2-8272-61256084b30e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355599945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1355599945
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2225843839
Short name T40
Test name
Test status
Simulation time 12046136 ps
CPU time 0.85 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 208588 kb
Host smart-d5d70ebc-128c-4685-9687-e40a2bf98364
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225843839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2225843839
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2955570177
Short name T60
Test name
Test status
Simulation time 208922141 ps
CPU time 40.25 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 283276 kb
Host smart-0cface6a-013e-4b8e-baa9-3bfeb79dfeac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955570177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2955570177
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.723837665
Short name T96
Test name
Test status
Simulation time 359011048 ps
CPU time 2.53 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 217688 kb
Host smart-4671a9c1-228c-489f-85c1-a46bf61ee102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723837665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.723837665
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.651450309
Short name T50
Test name
Test status
Simulation time 28004868055 ps
CPU time 292.4 seconds
Started May 26 02:52:53 PM PDT 24
Finished May 26 02:57:46 PM PDT 24
Peak memory 229076 kb
Host smart-c556b194-d950-45da-a54a-9e9df89b0fc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651450309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.651450309
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.653622478
Short name T63
Test name
Test status
Simulation time 2699720901 ps
CPU time 14.53 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 218288 kb
Host smart-d386cd05-7988-4030-aaec-c229bfc9d53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653622478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.653622478
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.389279674
Short name T13
Test name
Test status
Simulation time 95318514 ps
CPU time 1.18 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:31 PM PDT 24
Peak memory 209652 kb
Host smart-17c52be4-9e87-4a9e-891b-06e42f1cce07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389279674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.389279674
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1976056938
Short name T25
Test name
Test status
Simulation time 439720633 ps
CPU time 12.7 seconds
Started May 26 02:52:51 PM PDT 24
Finished May 26 02:53:05 PM PDT 24
Peak memory 209648 kb
Host smart-ce21e467-7ec3-449b-b0ee-138a71fb9431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976056938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1976056938
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1668366450
Short name T187
Test name
Test status
Simulation time 12210189 ps
CPU time 1.06 seconds
Started May 26 02:52:48 PM PDT 24
Finished May 26 02:52:55 PM PDT 24
Peak memory 209504 kb
Host smart-9e1298d0-b3c1-41d7-8a87-623ff2791038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668366450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1668366450
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2725380348
Short name T113
Test name
Test status
Simulation time 127910698 ps
CPU time 2.75 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:36 PM PDT 24
Peak memory 221888 kb
Host smart-d2bdaec8-85e1-4d60-a7dc-527f7a982c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725380348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2725380348
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.529962818
Short name T54
Test name
Test status
Simulation time 161146332484 ps
CPU time 1183.84 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 03:13:04 PM PDT 24
Peak memory 316664 kb
Host smart-5888ea04-a6a1-46c5-9e9a-a5c0e06cb329
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=529962818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.529962818
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4269597776
Short name T106
Test name
Test status
Simulation time 357224895 ps
CPU time 2.84 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 217756 kb
Host smart-d1da89c2-0936-47cf-ab8f-e1d3b31c1605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269597776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4269597776
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.898894883
Short name T110
Test name
Test status
Simulation time 159827314 ps
CPU time 3.62 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 217788 kb
Host smart-6b7b94bf-3f00-4920-8d8b-bfda33e43bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898894883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.898894883
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.448385164
Short name T95
Test name
Test status
Simulation time 3029791673 ps
CPU time 69.83 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:54:41 PM PDT 24
Peak memory 282660 kb
Host smart-43d8ad0f-e057-40f3-9896-25918b37eec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448385164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.448385164
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.951621532
Short name T15
Test name
Test status
Simulation time 446467860 ps
CPU time 7.29 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 250468 kb
Host smart-de2f0c8d-8a45-4154-a2c6-f35e08c3e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951621532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.951621532
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3349009656
Short name T97
Test name
Test status
Simulation time 398372762 ps
CPU time 3.94 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 217640 kb
Host smart-0561bd3a-eca6-4537-8593-e0e794b1f537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349009656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3349009656
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.698580108
Short name T196
Test name
Test status
Simulation time 14405440 ps
CPU time 1.04 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 209540 kb
Host smart-6ccc25d8-1fbf-4908-bb34-af339f3f3bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698580108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.698580108
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.811701295
Short name T118
Test name
Test status
Simulation time 88363717 ps
CPU time 1.77 seconds
Started May 26 02:52:32 PM PDT 24
Finished May 26 02:52:35 PM PDT 24
Peak memory 221612 kb
Host smart-8e83a619-5254-482d-a462-e0de63d2c6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811701295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.811701295
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2232117421
Short name T114
Test name
Test status
Simulation time 205360593 ps
CPU time 3.18 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 222516 kb
Host smart-7e0f4639-d536-4c76-bda3-67225402e446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232117421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2232117421
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3921412444
Short name T112
Test name
Test status
Simulation time 422377322 ps
CPU time 4.04 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 217696 kb
Host smart-77fd846c-d835-444a-9715-94d473e77d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921412444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3921412444
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.4163722890
Short name T206
Test name
Test status
Simulation time 13073494 ps
CPU time 0.95 seconds
Started May 26 02:52:45 PM PDT 24
Finished May 26 02:52:47 PM PDT 24
Peak memory 209588 kb
Host smart-4c3ce03f-6236-4c90-b177-c5231243156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163722890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4163722890
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2465707109
Short name T208
Test name
Test status
Simulation time 30275157 ps
CPU time 0.87 seconds
Started May 26 02:52:44 PM PDT 24
Finished May 26 02:52:47 PM PDT 24
Peak memory 209232 kb
Host smart-035cf6e3-fc80-492f-87c7-08a6de5f7fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465707109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2465707109
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3130007824
Short name T175
Test name
Test status
Simulation time 35027440 ps
CPU time 0.96 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:12 PM PDT 24
Peak memory 209580 kb
Host smart-9250566a-6396-47f7-937a-28daed6996c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130007824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3130007824
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2358924619
Short name T177
Test name
Test status
Simulation time 41725595 ps
CPU time 0.8 seconds
Started May 26 02:53:09 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 209524 kb
Host smart-89d7333a-c678-417a-91fc-bb59917b36d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358924619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2358924619
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1898768503
Short name T99
Test name
Test status
Simulation time 71163880 ps
CPU time 1.49 seconds
Started May 26 02:52:14 PM PDT 24
Finished May 26 02:52:18 PM PDT 24
Peak memory 219968 kb
Host smart-ad0ebb17-7800-4337-a3ce-e007fd350c00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898768503 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1898768503
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1046881687
Short name T122
Test name
Test status
Simulation time 219819692 ps
CPU time 2.5 seconds
Started May 26 02:52:14 PM PDT 24
Finished May 26 02:52:19 PM PDT 24
Peak memory 217772 kb
Host smart-81710014-a7fd-440c-a1c9-86a7dff7cc32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046881687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1046881687
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3374329615
Short name T98
Test name
Test status
Simulation time 75613388 ps
CPU time 3.39 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 222368 kb
Host smart-f508ebaf-9449-4203-9c6f-fb8b90f82c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374329615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3374329615
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1034574328
Short name T115
Test name
Test status
Simulation time 396954581 ps
CPU time 3.18 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:41 PM PDT 24
Peak memory 222256 kb
Host smart-11e570dc-b526-4bf8-a6c0-1dc21ef67380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034574328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1034574328
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3190572660
Short name T111
Test name
Test status
Simulation time 1064102719 ps
CPU time 4 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:52:50 PM PDT 24
Peak memory 217728 kb
Host smart-0a608da4-8954-4840-922d-47f76e4dd806
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190572660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3190572660
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2644849015
Short name T123
Test name
Test status
Simulation time 208438246 ps
CPU time 2.46 seconds
Started May 26 02:52:28 PM PDT 24
Finished May 26 02:52:33 PM PDT 24
Peak memory 217748 kb
Host smart-7cd9dfcf-24d3-4414-bd16-b76589e21145
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644849015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2644849015
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3464872951
Short name T45
Test name
Test status
Simulation time 106434168 ps
CPU time 1.95 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 217828 kb
Host smart-28a1f746-02ae-4b99-8100-09aa014f50b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464872951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3464872951
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2210444394
Short name T4
Test name
Test status
Simulation time 422883238 ps
CPU time 6.51 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:50 PM PDT 24
Peak memory 217948 kb
Host smart-503635fb-c546-4ab1-abad-5ff6dae5a831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210444394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2210444394
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3660833724
Short name T194
Test name
Test status
Simulation time 13234980 ps
CPU time 1 seconds
Started May 26 02:52:16 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 209584 kb
Host smart-7df22efe-2a15-4771-9458-ed286a6f98b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660833724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3660833724
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2610858234
Short name T947
Test name
Test status
Simulation time 93752051 ps
CPU time 2 seconds
Started May 26 02:52:21 PM PDT 24
Finished May 26 02:52:27 PM PDT 24
Peak memory 209076 kb
Host smart-b4627381-b025-45db-852a-0071aab9a1cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610858234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2610858234
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4200458836
Short name T957
Test name
Test status
Simulation time 13434060 ps
CPU time 0.88 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 209612 kb
Host smart-057e8661-b99e-41b0-8684-5b63db582fb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200458836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.4200458836
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1015018566
Short name T940
Test name
Test status
Simulation time 12484533 ps
CPU time 0.99 seconds
Started May 26 02:52:23 PM PDT 24
Finished May 26 02:52:27 PM PDT 24
Peak memory 209476 kb
Host smart-6636eddf-1a9d-4292-8b52-aec11cf155e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015018566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1015018566
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1607701179
Short name T922
Test name
Test status
Simulation time 141184113 ps
CPU time 1.08 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:23 PM PDT 24
Peak memory 207992 kb
Host smart-cb6cc16a-1081-47cd-881f-77f27e3083bc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607701179 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1607701179
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3222883790
Short name T906
Test name
Test status
Simulation time 498204879 ps
CPU time 13.14 seconds
Started May 26 02:52:16 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 209328 kb
Host smart-6cec05d0-700c-4f97-abd4-75a3df19eef5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222883790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3222883790
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1817099370
Short name T961
Test name
Test status
Simulation time 741583167 ps
CPU time 6.93 seconds
Started May 26 02:52:16 PM PDT 24
Finished May 26 02:52:27 PM PDT 24
Peak memory 209136 kb
Host smart-aca2adb5-6954-45d4-b696-d14ccb700fce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817099370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1817099370
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2309026350
Short name T928
Test name
Test status
Simulation time 365195118 ps
CPU time 1.86 seconds
Started May 26 02:52:21 PM PDT 24
Finished May 26 02:52:27 PM PDT 24
Peak memory 210976 kb
Host smart-02134a08-e0b2-4c66-98a0-081f1d336d69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309026350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2309026350
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3285431457
Short name T167
Test name
Test status
Simulation time 210735145 ps
CPU time 1.32 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:25 PM PDT 24
Peak memory 217764 kb
Host smart-e592e0b5-76d1-4de1-be16-393687f5cac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328543
1457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3285431457
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1464600365
Short name T938
Test name
Test status
Simulation time 583840160 ps
CPU time 2.06 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:24 PM PDT 24
Peak memory 209380 kb
Host smart-8ca787c8-e821-4621-a643-ca25bd3f6487
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464600365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1464600365
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.992569146
Short name T201
Test name
Test status
Simulation time 46713575 ps
CPU time 1.44 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:23 PM PDT 24
Peak memory 209528 kb
Host smart-5ccd0646-445d-4924-8d7e-eea00c76e51b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992569146 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.992569146
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4143036089
Short name T997
Test name
Test status
Simulation time 14494581 ps
CPU time 1.01 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:25 PM PDT 24
Peak memory 209468 kb
Host smart-16a9a753-abfe-41d0-8bf3-32e7b0dea1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143036089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4143036089
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3418284124
Short name T908
Test name
Test status
Simulation time 497321101 ps
CPU time 4.86 seconds
Started May 26 02:52:14 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 217752 kb
Host smart-19241edc-63dd-495a-a840-207053d0567f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418284124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3418284124
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.656955567
Short name T117
Test name
Test status
Simulation time 529988192 ps
CPU time 3.06 seconds
Started May 26 02:52:08 PM PDT 24
Finished May 26 02:52:12 PM PDT 24
Peak memory 222116 kb
Host smart-be6a4932-cd81-4385-b2b6-71c7fe308fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656955567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.656955567
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2714968960
Short name T885
Test name
Test status
Simulation time 46263330 ps
CPU time 1.24 seconds
Started May 26 02:52:16 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 209444 kb
Host smart-5d20b0c0-79e8-4c92-86f3-fa106083b3a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714968960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2714968960
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.821094451
Short name T108
Test name
Test status
Simulation time 39347598 ps
CPU time 1.35 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 208448 kb
Host smart-4d0ae100-8918-475c-9e65-5b629c75a726
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821094451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.821094451
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3842813208
Short name T193
Test name
Test status
Simulation time 33688237 ps
CPU time 1.08 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:19 PM PDT 24
Peak memory 210088 kb
Host smart-04801e11-8e10-4708-bc66-63a808e621ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842813208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3842813208
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.788408327
Short name T900
Test name
Test status
Simulation time 68906585 ps
CPU time 1.26 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:23 PM PDT 24
Peak memory 217760 kb
Host smart-f950782d-89fd-4a70-a93e-662d5ae824b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788408327 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.788408327
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.261785710
Short name T902
Test name
Test status
Simulation time 14282067 ps
CPU time 0.89 seconds
Started May 26 02:52:16 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 208920 kb
Host smart-79b8991a-de1a-4c3c-b77d-28929bf837fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261785710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.261785710
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1105892742
Short name T915
Test name
Test status
Simulation time 65527870 ps
CPU time 1.25 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:20 PM PDT 24
Peak memory 209332 kb
Host smart-85ac26bf-28a0-4c09-8497-14ba59823df5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105892742 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1105892742
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2943784803
Short name T887
Test name
Test status
Simulation time 1129905969 ps
CPU time 13.65 seconds
Started May 26 02:52:23 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 209200 kb
Host smart-6ded1697-80c6-45da-b06f-232eec9514c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943784803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2943784803
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.364552704
Short name T941
Test name
Test status
Simulation time 612228596 ps
CPU time 6.11 seconds
Started May 26 02:52:14 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 209464 kb
Host smart-5e722a67-8e9a-47de-94ea-8a5418fa18fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364552704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.364552704
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3036679321
Short name T898
Test name
Test status
Simulation time 269380071 ps
CPU time 3.67 seconds
Started May 26 02:52:22 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 210828 kb
Host smart-3e2db7c0-858e-4bf1-b1d6-237e22e73564
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036679321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3036679321
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128414362
Short name T993
Test name
Test status
Simulation time 4825563410 ps
CPU time 6.25 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:24 PM PDT 24
Peak memory 217748 kb
Host smart-93c4fb0d-1fd8-4437-ac15-ac706db0aaa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412841
4362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128414362
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1148794969
Short name T926
Test name
Test status
Simulation time 85389784 ps
CPU time 1.75 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:20 PM PDT 24
Peak memory 209396 kb
Host smart-2bbd1ccb-6016-4417-b804-da89a6363d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148794969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1148794969
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4042520757
Short name T104
Test name
Test status
Simulation time 211907115 ps
CPU time 1.36 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:24 PM PDT 24
Peak memory 209496 kb
Host smart-d444965b-3b29-4e68-bd37-41d35d6a1a7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042520757 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.4042520757
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.708882822
Short name T889
Test name
Test status
Simulation time 32681436 ps
CPU time 1.28 seconds
Started May 26 02:52:14 PM PDT 24
Finished May 26 02:52:18 PM PDT 24
Peak memory 217720 kb
Host smart-243b616f-0df8-4e3e-964a-0e14122b418d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708882822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.708882822
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1547728567
Short name T910
Test name
Test status
Simulation time 412433170 ps
CPU time 2.24 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 217748 kb
Host smart-5bd4bf39-0d4a-412d-865a-d6852ada00dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547728567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1547728567
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2991906055
Short name T924
Test name
Test status
Simulation time 23698863 ps
CPU time 1.33 seconds
Started May 26 02:52:48 PM PDT 24
Finished May 26 02:52:50 PM PDT 24
Peak memory 217752 kb
Host smart-81061225-3980-476a-b0fe-41e47a1bc202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991906055 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2991906055
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1708139627
Short name T894
Test name
Test status
Simulation time 38238483 ps
CPU time 1.4 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:43 PM PDT 24
Peak memory 211832 kb
Host smart-e9a243ab-8de8-423e-b9ab-5ac1401c431d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708139627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1708139627
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2548755557
Short name T984
Test name
Test status
Simulation time 249083401 ps
CPU time 2.82 seconds
Started May 26 02:52:30 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 217704 kb
Host smart-76351a8d-7c06-4268-a8e2-65e1d56597f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548755557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2548755557
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1021305581
Short name T168
Test name
Test status
Simulation time 38831939 ps
CPU time 1.28 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 219628 kb
Host smart-bf867046-d916-460c-a50c-1497e8e857b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021305581 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1021305581
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3925540380
Short name T203
Test name
Test status
Simulation time 36866097 ps
CPU time 1.25 seconds
Started May 26 02:52:42 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 209468 kb
Host smart-7a272718-9c6d-4cbb-82c8-27e744c160bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925540380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3925540380
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3107725400
Short name T975
Test name
Test status
Simulation time 148438541 ps
CPU time 2.2 seconds
Started May 26 02:52:35 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 217788 kb
Host smart-de318f4c-7dbc-4faf-a671-a2358ad6322f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107725400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3107725400
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2802410983
Short name T119
Test name
Test status
Simulation time 85199653 ps
CPU time 2.89 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:36 PM PDT 24
Peak memory 222452 kb
Host smart-71d3c6ce-2cee-4d33-8c9e-65663d9bc823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802410983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2802410983
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3751961135
Short name T981
Test name
Test status
Simulation time 25321473 ps
CPU time 1.24 seconds
Started May 26 02:52:37 PM PDT 24
Finished May 26 02:52:41 PM PDT 24
Peak memory 217784 kb
Host smart-e341c278-13ea-4e87-a6a1-ce7a3a48ad8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751961135 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3751961135
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2708535579
Short name T935
Test name
Test status
Simulation time 58636069 ps
CPU time 0.87 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 209372 kb
Host smart-1368d869-fda2-4e0f-9477-b0a0b5716baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708535579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2708535579
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3876917756
Short name T199
Test name
Test status
Simulation time 18503458 ps
CPU time 1.28 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 209420 kb
Host smart-d70d6c22-5e03-438b-80bc-94be3e99f502
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876917756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3876917756
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2913308359
Short name T126
Test name
Test status
Simulation time 169962109 ps
CPU time 3.09 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:41 PM PDT 24
Peak memory 221924 kb
Host smart-b66f358a-a2f5-4fa4-9c41-662bd6779bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913308359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2913308359
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3523637160
Short name T969
Test name
Test status
Simulation time 26206203 ps
CPU time 1.23 seconds
Started May 26 02:52:37 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 219012 kb
Host smart-2f038db3-3a29-438f-8ac0-2ee3a384a216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523637160 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3523637160
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.809543075
Short name T989
Test name
Test status
Simulation time 18178195 ps
CPU time 1.17 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 209572 kb
Host smart-6689a9b0-674b-4b4e-a806-9616e59d6bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809543075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.809543075
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2530122833
Short name T979
Test name
Test status
Simulation time 335887507 ps
CPU time 1.85 seconds
Started May 26 02:52:37 PM PDT 24
Finished May 26 02:52:41 PM PDT 24
Peak memory 211556 kb
Host smart-2e9c23a0-3165-4943-bf1f-499b37aebd49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530122833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2530122833
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.418994648
Short name T103
Test name
Test status
Simulation time 83239055 ps
CPU time 2.68 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 218388 kb
Host smart-b0d59750-5e97-4fb1-ad49-4d202a775932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418994648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.418994648
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.163524268
Short name T995
Test name
Test status
Simulation time 103191812 ps
CPU time 1.36 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 217924 kb
Host smart-7bb1868e-dc95-4d93-9930-53c22a866b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163524268 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.163524268
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3053932711
Short name T883
Test name
Test status
Simulation time 12083114 ps
CPU time 1.01 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 209468 kb
Host smart-5bbb070e-1746-4649-9f0d-43ead1de4c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053932711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3053932711
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1678942303
Short name T937
Test name
Test status
Simulation time 56670148 ps
CPU time 1.18 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 209468 kb
Host smart-31fe8e00-b88d-4591-907d-1530e6710c34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678942303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1678942303
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.358453044
Short name T949
Test name
Test status
Simulation time 414980679 ps
CPU time 4.43 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 217760 kb
Host smart-5a98639c-088d-4f5f-aa29-93c83e14257f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358453044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.358453044
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.820541110
Short name T990
Test name
Test status
Simulation time 102521449 ps
CPU time 1.77 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 217748 kb
Host smart-24a21ab6-3124-4d6e-9df7-50f5c7034ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820541110 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.820541110
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.354709528
Short name T197
Test name
Test status
Simulation time 171737636 ps
CPU time 0.89 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 209464 kb
Host smart-def1044a-ee42-4058-9664-db47ed115ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354709528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.354709528
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.914375001
Short name T932
Test name
Test status
Simulation time 405689645 ps
CPU time 1.32 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 209196 kb
Host smart-7dc1970c-bcdf-4364-b240-ff300888a7a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914375001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.914375001
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3487202745
Short name T985
Test name
Test status
Simulation time 65880986 ps
CPU time 2.07 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:43 PM PDT 24
Peak memory 217696 kb
Host smart-fff44791-109d-486b-9851-db179265bb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487202745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3487202745
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3217583573
Short name T105
Test name
Test status
Simulation time 65044744 ps
CPU time 2.25 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 219932 kb
Host smart-124adbc4-e94e-47b8-b253-eed9107f719e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217583573 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3217583573
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3548662675
Short name T190
Test name
Test status
Simulation time 28725345 ps
CPU time 1.08 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:41 PM PDT 24
Peak memory 209204 kb
Host smart-7589039c-1530-48a1-ac31-b647105fa161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548662675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3548662675
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1378141092
Short name T954
Test name
Test status
Simulation time 21666737 ps
CPU time 1.31 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 211548 kb
Host smart-b39aad03-f553-450d-b984-52c523a7b4af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378141092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1378141092
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3563888939
Short name T986
Test name
Test status
Simulation time 243609850 ps
CPU time 2.61 seconds
Started May 26 02:52:30 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 217708 kb
Host smart-6546ad63-0db3-4e64-be9d-d1bce4ff42f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563888939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3563888939
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3983083149
Short name T127
Test name
Test status
Simulation time 229719966 ps
CPU time 2.73 seconds
Started May 26 02:52:32 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 217720 kb
Host smart-850a6ebc-0765-41c3-8255-c0a4daea9f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983083149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3983083149
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2829123378
Short name T988
Test name
Test status
Simulation time 47617367 ps
CPU time 1.64 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 218840 kb
Host smart-5789e308-e56a-425e-b024-a1a64eaf45c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829123378 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2829123378
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2907830942
Short name T920
Test name
Test status
Simulation time 26985866 ps
CPU time 1.06 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 209004 kb
Host smart-4bd23268-9ca4-45dc-ab75-691495001999
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907830942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2907830942
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3768120380
Short name T109
Test name
Test status
Simulation time 150034363 ps
CPU time 1.3 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 209492 kb
Host smart-861fa73a-32bd-46e6-94d5-a6ef5e29a336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768120380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3768120380
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2574719373
Short name T942
Test name
Test status
Simulation time 23044114 ps
CPU time 1.74 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 217860 kb
Host smart-d1547128-254a-4db2-9f81-7152fbd93804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574719373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2574719373
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.686868669
Short name T102
Test name
Test status
Simulation time 80042268 ps
CPU time 1.37 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 217708 kb
Host smart-c69904b8-cf94-49f3-9be9-6ca6255f752b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686868669 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.686868669
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2477264135
Short name T892
Test name
Test status
Simulation time 14342497 ps
CPU time 1 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:43 PM PDT 24
Peak memory 209488 kb
Host smart-96408d68-e9ce-4276-8428-c625efeaff1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477264135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2477264135
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.265191672
Short name T198
Test name
Test status
Simulation time 38616972 ps
CPU time 1.45 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 211524 kb
Host smart-177d14ac-6293-4a4b-8fd4-e46755bff591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265191672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.265191672
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2349612219
Short name T983
Test name
Test status
Simulation time 41666296 ps
CPU time 2.47 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:46 PM PDT 24
Peak memory 217888 kb
Host smart-8123802c-283d-4507-a64d-22f2b3f9fd27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349612219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2349612219
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.289516980
Short name T121
Test name
Test status
Simulation time 152758460 ps
CPU time 2.62 seconds
Started May 26 02:52:44 PM PDT 24
Finished May 26 02:52:49 PM PDT 24
Peak memory 217744 kb
Host smart-50815113-e6e7-4ba7-9e11-f6c2333efc6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289516980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.289516980
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1573192382
Short name T931
Test name
Test status
Simulation time 175193127 ps
CPU time 1.74 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:52:47 PM PDT 24
Peak memory 219788 kb
Host smart-d8e1fb14-5ac7-42ed-9437-65a9897203f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573192382 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1573192382
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2820057483
Short name T186
Test name
Test status
Simulation time 11867406 ps
CPU time 0.91 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 208628 kb
Host smart-138d3c75-c3c3-4561-926f-aa17871e5de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820057483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2820057483
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2344561663
Short name T965
Test name
Test status
Simulation time 26888115 ps
CPU time 1.04 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:43 PM PDT 24
Peak memory 209496 kb
Host smart-4102436e-c532-407a-9a42-7fc6c28b0fd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344561663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2344561663
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3801058435
Short name T909
Test name
Test status
Simulation time 179396939 ps
CPU time 3.65 seconds
Started May 26 02:52:50 PM PDT 24
Finished May 26 02:52:54 PM PDT 24
Peak memory 217884 kb
Host smart-bddf96cb-f89b-4c1a-88bb-19b38a675050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801058435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3801058435
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1423563977
Short name T944
Test name
Test status
Simulation time 408161891 ps
CPU time 1.63 seconds
Started May 26 02:52:26 PM PDT 24
Finished May 26 02:52:30 PM PDT 24
Peak memory 208944 kb
Host smart-2d8c704b-e1fb-43bb-b079-ee537d06ea45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423563977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1423563977
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.688780916
Short name T913
Test name
Test status
Simulation time 37798535 ps
CPU time 1.16 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:23 PM PDT 24
Peak memory 208312 kb
Host smart-a79c6dff-2262-4fe2-b9ce-40af289fef7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688780916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.688780916
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3759005308
Short name T142
Test name
Test status
Simulation time 21029493 ps
CPU time 1.14 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:20 PM PDT 24
Peak memory 209968 kb
Host smart-8d8f7c77-348e-42b0-b1cb-675180b7db6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759005308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3759005308
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3768484380
Short name T974
Test name
Test status
Simulation time 26041778 ps
CPU time 1.09 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 221324 kb
Host smart-cb0a5ac7-1ff0-482c-bef6-7e2f2d865df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768484380 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3768484380
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3767423144
Short name T967
Test name
Test status
Simulation time 15994777 ps
CPU time 1.11 seconds
Started May 26 02:52:21 PM PDT 24
Finished May 26 02:52:26 PM PDT 24
Peak memory 209484 kb
Host smart-03d4b758-cb4c-40c5-88a5-e01de19c8872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767423144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3767423144
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.294976442
Short name T899
Test name
Test status
Simulation time 338232693 ps
CPU time 1.51 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:23 PM PDT 24
Peak memory 209392 kb
Host smart-90c6dc8c-337e-495f-9c0a-8cb1c7a493d1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294976442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.294976442
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3990809153
Short name T131
Test name
Test status
Simulation time 2041508962 ps
CPU time 3.9 seconds
Started May 26 02:52:27 PM PDT 24
Finished May 26 02:52:33 PM PDT 24
Peak memory 209184 kb
Host smart-c5a7188b-517d-481e-8fbc-b69c5ccebf4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990809153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3990809153
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2566421456
Short name T890
Test name
Test status
Simulation time 6583924617 ps
CPU time 28.45 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:51 PM PDT 24
Peak memory 208832 kb
Host smart-3a670fec-2b9e-40a3-80ff-e569662d9c74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566421456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2566421456
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3930710972
Short name T970
Test name
Test status
Simulation time 116137913 ps
CPU time 2.51 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 210864 kb
Host smart-a04df3ee-36bf-4f4e-ba74-eb5dd418d4df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930710972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3930710972
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1760435695
Short name T897
Test name
Test status
Simulation time 105595801 ps
CPU time 1.53 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:23 PM PDT 24
Peak memory 219572 kb
Host smart-200af31a-7e0a-49dd-9af8-daaf7a6e63f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176043
5695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1760435695
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.817092026
Short name T132
Test name
Test status
Simulation time 194946689 ps
CPU time 1.59 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 209396 kb
Host smart-4ad921db-b1fc-48ca-aedd-51b756f98dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817092026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.817092026
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4104202536
Short name T927
Test name
Test status
Simulation time 66832695 ps
CPU time 1.17 seconds
Started May 26 02:52:20 PM PDT 24
Finished May 26 02:52:26 PM PDT 24
Peak memory 209524 kb
Host smart-5d419635-f486-458f-afca-589ac088ece4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104202536 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4104202536
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2771767980
Short name T144
Test name
Test status
Simulation time 253509615 ps
CPU time 2.03 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:25 PM PDT 24
Peak memory 209456 kb
Host smart-61d54940-b608-44e2-aff4-6172f269e2cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771767980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2771767980
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3859973520
Short name T120
Test name
Test status
Simulation time 259927376 ps
CPU time 1.99 seconds
Started May 26 02:52:16 PM PDT 24
Finished May 26 02:52:22 PM PDT 24
Peak memory 217752 kb
Host smart-d019c2d8-1ac9-4e1f-a1c1-268a60731ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859973520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3859973520
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3658730764
Short name T116
Test name
Test status
Simulation time 286869670 ps
CPU time 2.68 seconds
Started May 26 02:52:26 PM PDT 24
Finished May 26 02:52:31 PM PDT 24
Peak memory 221960 kb
Host smart-64190624-bf54-41d2-b9b1-170053ebc8dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658730764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3658730764
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1892325885
Short name T141
Test name
Test status
Simulation time 46857722 ps
CPU time 1.36 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 209560 kb
Host smart-237137c6-eb58-4229-b1ec-7cb75a090d91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892325885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1892325885
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3256960647
Short name T882
Test name
Test status
Simulation time 97659758 ps
CPU time 1.56 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:24 PM PDT 24
Peak memory 209596 kb
Host smart-ce1e03d2-c945-4d3b-8240-cfeca86b8455
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256960647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3256960647
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3883351330
Short name T191
Test name
Test status
Simulation time 20867746 ps
CPU time 1.26 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 219392 kb
Host smart-abe95604-f6c9-4e5c-ae3e-7ecceb638a60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883351330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3883351330
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3579294084
Short name T158
Test name
Test status
Simulation time 79071256 ps
CPU time 1.5 seconds
Started May 26 02:52:23 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 219736 kb
Host smart-cf629130-fe7b-4da3-b9f4-35f1236e8942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579294084 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3579294084
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3579353187
Short name T959
Test name
Test status
Simulation time 17123715 ps
CPU time 1.14 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 217492 kb
Host smart-6f7d15e7-7ba7-4914-bc8a-905de222c240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579353187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3579353187
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2931490929
Short name T936
Test name
Test status
Simulation time 92630957 ps
CPU time 2.69 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 209196 kb
Host smart-6215f1de-95dd-4811-9db5-88c9ac7eb71f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931490929 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2931490929
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2897552073
Short name T968
Test name
Test status
Simulation time 509338768 ps
CPU time 3.01 seconds
Started May 26 02:52:22 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 207704 kb
Host smart-3385f116-2040-4f06-9fb1-868944884a3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897552073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2897552073
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.828767637
Short name T976
Test name
Test status
Simulation time 12952788755 ps
CPU time 31.68 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:58 PM PDT 24
Peak memory 209572 kb
Host smart-7064388c-f95c-4206-99d7-0289e92d4fac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828767637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.828767637
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.74700097
Short name T905
Test name
Test status
Simulation time 960461805 ps
CPU time 2.76 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 211060 kb
Host smart-c51fa77b-e05d-46b9-ae4b-f501491471c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74700097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.74700097
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.174778756
Short name T921
Test name
Test status
Simulation time 633363310 ps
CPU time 3.39 seconds
Started May 26 02:52:21 PM PDT 24
Finished May 26 02:52:28 PM PDT 24
Peak memory 217728 kb
Host smart-4117762b-86c4-4144-887d-196dc0424d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174778
756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.174778756
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2473905462
Short name T996
Test name
Test status
Simulation time 191188722 ps
CPU time 3.06 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:25 PM PDT 24
Peak memory 209420 kb
Host smart-72f248ae-69f4-4b12-af94-2899d6866a89
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473905462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2473905462
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2636386460
Short name T994
Test name
Test status
Simulation time 179901711 ps
CPU time 1.54 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 211728 kb
Host smart-dac597dc-9743-4d74-b8e0-f4b3291b53f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636386460 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2636386460
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.154492285
Short name T958
Test name
Test status
Simulation time 235424840 ps
CPU time 1.07 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:20 PM PDT 24
Peak memory 209408 kb
Host smart-41fc206c-f8c5-4a9d-88ce-d097e7f5682d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154492285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.154492285
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.5681322
Short name T901
Test name
Test status
Simulation time 23433084 ps
CPU time 1.61 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:21 PM PDT 24
Peak memory 218884 kb
Host smart-4432dda2-dcdf-49c0-882e-d4e04180d776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5681322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.5681322
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1054219309
Short name T188
Test name
Test status
Simulation time 126171086 ps
CPU time 1.07 seconds
Started May 26 02:52:15 PM PDT 24
Finished May 26 02:52:20 PM PDT 24
Peak memory 209436 kb
Host smart-5cd6c044-e6e0-491e-a1bc-b29297470bfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054219309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1054219309
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3622246855
Short name T884
Test name
Test status
Simulation time 70432211 ps
CPU time 1.32 seconds
Started May 26 02:52:22 PM PDT 24
Finished May 26 02:52:27 PM PDT 24
Peak memory 208736 kb
Host smart-6c0cd681-ea86-4e8c-8066-539bda1049e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622246855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3622246855
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2823518561
Short name T189
Test name
Test status
Simulation time 18889437 ps
CPU time 0.86 seconds
Started May 26 02:52:17 PM PDT 24
Finished May 26 02:52:23 PM PDT 24
Peak memory 209788 kb
Host smart-542fee20-af8d-4123-a123-f065b1c1e73f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823518561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2823518561
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1578508824
Short name T966
Test name
Test status
Simulation time 220147517 ps
CPU time 1.37 seconds
Started May 26 02:52:22 PM PDT 24
Finished May 26 02:52:27 PM PDT 24
Peak memory 219160 kb
Host smart-e929c3ab-884a-408e-8c8a-a31c2d4c9afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578508824 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1578508824
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.784257411
Short name T950
Test name
Test status
Simulation time 119481271 ps
CPU time 0.89 seconds
Started May 26 02:52:21 PM PDT 24
Finished May 26 02:52:26 PM PDT 24
Peak memory 209332 kb
Host smart-7bc9c507-4690-4043-9737-10bbecba57df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784257411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.784257411
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2614589934
Short name T893
Test name
Test status
Simulation time 121523946 ps
CPU time 1 seconds
Started May 26 02:52:18 PM PDT 24
Finished May 26 02:52:24 PM PDT 24
Peak memory 209332 kb
Host smart-ce9de0d7-d584-43d9-83a5-245cced389e8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614589934 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2614589934
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2648984958
Short name T912
Test name
Test status
Simulation time 997687058 ps
CPU time 6.56 seconds
Started May 26 02:52:22 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 209224 kb
Host smart-31e69164-b8c8-4416-9bf1-e285f26fca7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648984958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2648984958
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3624262731
Short name T964
Test name
Test status
Simulation time 9108504442 ps
CPU time 31.42 seconds
Started May 26 02:52:28 PM PDT 24
Finished May 26 02:53:02 PM PDT 24
Peak memory 208696 kb
Host smart-7feaed6b-617f-4352-8aba-b82e0989e2e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624262731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3624262731
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2987470451
Short name T128
Test name
Test status
Simulation time 225665521 ps
CPU time 1.98 seconds
Started May 26 02:52:19 PM PDT 24
Finished May 26 02:52:26 PM PDT 24
Peak memory 211064 kb
Host smart-53494f53-95ae-4ce8-a698-3884ec7d50df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987470451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2987470451
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2577746585
Short name T963
Test name
Test status
Simulation time 87188595 ps
CPU time 2.05 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 217744 kb
Host smart-9128c148-3287-4d5d-887b-5951cb97d0d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257774
6585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2577746585
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1225218179
Short name T953
Test name
Test status
Simulation time 133475774 ps
CPU time 2.14 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 209532 kb
Host smart-65b60c4a-2145-4322-9512-e49331561b8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225218179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1225218179
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4082202230
Short name T962
Test name
Test status
Simulation time 114106602 ps
CPU time 1.05 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:36 PM PDT 24
Peak memory 209528 kb
Host smart-1bcd9700-808b-4f9d-a92b-0e328d48a3e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082202230 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4082202230
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2129610747
Short name T145
Test name
Test status
Simulation time 117414908 ps
CPU time 1.08 seconds
Started May 26 02:52:19 PM PDT 24
Finished May 26 02:52:25 PM PDT 24
Peak memory 209524 kb
Host smart-d8dd70fc-d62d-4529-a6fd-f59f45f3949d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129610747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2129610747
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.990846892
Short name T955
Test name
Test status
Simulation time 1505907128 ps
CPU time 4.61 seconds
Started May 26 02:52:19 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 217804 kb
Host smart-d24b0155-bc03-456b-b7ec-1d2082a35092
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990846892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.990846892
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4262079986
Short name T925
Test name
Test status
Simulation time 29919788 ps
CPU time 1.74 seconds
Started May 26 02:52:29 PM PDT 24
Finished May 26 02:52:33 PM PDT 24
Peak memory 219068 kb
Host smart-7e807b58-7fdd-44d8-8640-4e978deacdf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262079986 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4262079986
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3431889354
Short name T195
Test name
Test status
Simulation time 37874795 ps
CPU time 0.86 seconds
Started May 26 02:52:27 PM PDT 24
Finished May 26 02:52:31 PM PDT 24
Peak memory 208712 kb
Host smart-7054468c-79ee-4389-8000-0bfb99cb9a5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431889354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3431889354
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2586799104
Short name T916
Test name
Test status
Simulation time 145197064 ps
CPU time 1.17 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 209268 kb
Host smart-3beeff58-968d-4981-beea-6ea5405df3cf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586799104 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2586799104
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2301450479
Short name T999
Test name
Test status
Simulation time 431875150 ps
CPU time 10.56 seconds
Started May 26 02:52:23 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 209196 kb
Host smart-400a0dcf-98cc-4819-9928-4f4d810f4928
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301450479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2301450479
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3803391818
Short name T911
Test name
Test status
Simulation time 10154562409 ps
CPU time 19.74 seconds
Started May 26 02:52:19 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 209384 kb
Host smart-c5c73d4a-5633-4f67-91f0-da9aa0e38c90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803391818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3803391818
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1788895633
Short name T886
Test name
Test status
Simulation time 411517020 ps
CPU time 2.76 seconds
Started May 26 02:52:27 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 211032 kb
Host smart-35aa3c3f-cd27-401e-97fe-7af80b51cf95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788895633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1788895633
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2593881321
Short name T930
Test name
Test status
Simulation time 68144721 ps
CPU time 1.07 seconds
Started May 26 02:52:36 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 209400 kb
Host smart-aeb1687e-fb29-491d-a413-33b3928e9a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593881321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2593881321
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3590250921
Short name T143
Test name
Test status
Simulation time 206670612 ps
CPU time 1.5 seconds
Started May 26 02:52:28 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 217652 kb
Host smart-39555649-15b1-4387-8696-99dd9258e647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590250921 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3590250921
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1642380880
Short name T977
Test name
Test status
Simulation time 112967506 ps
CPU time 1.38 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 209496 kb
Host smart-8b986250-aa4d-4baa-aa5a-6d03f308f35a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642380880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1642380880
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.814332334
Short name T904
Test name
Test status
Simulation time 105959272 ps
CPU time 3.2 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:35 PM PDT 24
Peak memory 217948 kb
Host smart-fb35cdbc-1af4-45de-97e3-ac94b7983afc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814332334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.814332334
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1735926313
Short name T125
Test name
Test status
Simulation time 224321995 ps
CPU time 1.93 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:35 PM PDT 24
Peak memory 217692 kb
Host smart-bfd3fab5-006c-45db-8f61-d7e5a2cb9622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735926313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1735926313
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.299171340
Short name T918
Test name
Test status
Simulation time 21278290 ps
CPU time 1.16 seconds
Started May 26 02:52:23 PM PDT 24
Finished May 26 02:52:27 PM PDT 24
Peak memory 218796 kb
Host smart-8d1b837e-61bd-4be6-9228-8cc84364c65a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299171340 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.299171340
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3770393885
Short name T907
Test name
Test status
Simulation time 24304113 ps
CPU time 0.95 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:38 PM PDT 24
Peak memory 209500 kb
Host smart-c8572d0e-ee67-473f-9771-a18125c281b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770393885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3770393885
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1941057126
Short name T952
Test name
Test status
Simulation time 50075477 ps
CPU time 1.13 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 209368 kb
Host smart-a455b477-e7fa-4926-aa4b-14c70aa5750e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941057126 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1941057126
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1152386563
Short name T133
Test name
Test status
Simulation time 503365767 ps
CPU time 8.51 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 208600 kb
Host smart-9b3a873f-1f7a-4281-bb78-ebbf26e192c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152386563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1152386563
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1988494746
Short name T933
Test name
Test status
Simulation time 676231879 ps
CPU time 8.26 seconds
Started May 26 02:52:27 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 208620 kb
Host smart-da4b364e-4628-4858-a14f-c9d46afc40cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988494746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1988494746
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1145424121
Short name T951
Test name
Test status
Simulation time 796779671 ps
CPU time 1.76 seconds
Started May 26 02:52:28 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 211048 kb
Host smart-fa1e89d0-e59b-4635-8b02-82ef8416fd6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145424121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1145424121
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2569647147
Short name T156
Test name
Test status
Simulation time 63984572 ps
CPU time 2.21 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:38 PM PDT 24
Peak memory 217740 kb
Host smart-3606bfb2-b32f-45f7-b817-2f8d8a9aa28e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256964
7147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2569647147
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1010196446
Short name T978
Test name
Test status
Simulation time 214850922 ps
CPU time 3.18 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:30 PM PDT 24
Peak memory 209392 kb
Host smart-86c53d72-ff3e-4a5c-a3ab-d6dcee877e0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010196446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1010196446
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3445748772
Short name T992
Test name
Test status
Simulation time 22679511 ps
CPU time 1.22 seconds
Started May 26 02:52:30 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 209496 kb
Host smart-9af97ba7-5876-4429-aceb-9c04d0f6c340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445748772 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3445748772
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.949355133
Short name T200
Test name
Test status
Simulation time 31378934 ps
CPU time 1.08 seconds
Started May 26 02:52:35 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 209484 kb
Host smart-64e9dbd3-63d6-4214-88e9-b7ce9247e18f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949355133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.949355133
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1007025111
Short name T923
Test name
Test status
Simulation time 254248651 ps
CPU time 3.84 seconds
Started May 26 02:52:30 PM PDT 24
Finished May 26 02:52:35 PM PDT 24
Peak memory 217752 kb
Host smart-54362806-0bcc-4610-8f1a-4c4fea2b03d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007025111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1007025111
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.74082700
Short name T101
Test name
Test status
Simulation time 67650471 ps
CPU time 1.6 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 218112 kb
Host smart-05f64963-2550-459e-a38c-439bf97e7a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74082700 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.74082700
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2496992566
Short name T192
Test name
Test status
Simulation time 17181836 ps
CPU time 1.05 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 209436 kb
Host smart-658c498e-6a14-4081-9390-f29d3b8d628b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496992566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2496992566
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3392808579
Short name T971
Test name
Test status
Simulation time 494106359 ps
CPU time 0.98 seconds
Started May 26 02:52:32 PM PDT 24
Finished May 26 02:52:35 PM PDT 24
Peak memory 209568 kb
Host smart-15b8a83a-b1c2-4ddb-9206-f4957a16855f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392808579 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3392808579
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1163410969
Short name T946
Test name
Test status
Simulation time 2128550110 ps
CPU time 11.7 seconds
Started May 26 02:52:33 PM PDT 24
Finished May 26 02:52:48 PM PDT 24
Peak memory 208592 kb
Host smart-b0904158-3b1f-4e2c-b3ac-ddd7609cacc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163410969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1163410969
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.853050369
Short name T891
Test name
Test status
Simulation time 2957673649 ps
CPU time 9.76 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:43 PM PDT 24
Peak memory 209368 kb
Host smart-589f5e89-a26e-4cd9-9544-6ee1aa427b0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853050369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.853050369
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3381366797
Short name T973
Test name
Test status
Simulation time 106391102 ps
CPU time 1.85 seconds
Started May 26 02:52:24 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 210732 kb
Host smart-2d2c0da9-b437-4eb6-a7af-315ef45bc518
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381366797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3381366797
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1082275597
Short name T991
Test name
Test status
Simulation time 422367964 ps
CPU time 6 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:42 PM PDT 24
Peak memory 217752 kb
Host smart-3175b283-b8c5-4beb-8f43-1eaa9f7b3b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108227
5597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1082275597
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2131540339
Short name T939
Test name
Test status
Simulation time 32327728 ps
CPU time 1.09 seconds
Started May 26 02:52:30 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 209400 kb
Host smart-7d1a5320-4b49-4af5-ac18-d8b0e5d07103
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131540339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2131540339
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.614392997
Short name T202
Test name
Test status
Simulation time 21469421 ps
CPU time 1.49 seconds
Started May 26 02:52:29 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 211552 kb
Host smart-44c30a31-667f-46ba-9da8-17f8a87b343f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614392997 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.614392997
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.167808811
Short name T896
Test name
Test status
Simulation time 55040797 ps
CPU time 1.45 seconds
Started May 26 02:52:26 PM PDT 24
Finished May 26 02:52:29 PM PDT 24
Peak memory 209500 kb
Host smart-72d6b674-0dba-41c2-95e1-8b94997eca4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167808811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.167808811
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3391434475
Short name T982
Test name
Test status
Simulation time 133371565 ps
CPU time 5.02 seconds
Started May 26 02:52:32 PM PDT 24
Finished May 26 02:52:38 PM PDT 24
Peak memory 217716 kb
Host smart-8f7bbc2c-8fac-45d1-9bcc-621f05f5d578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391434475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3391434475
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4107781821
Short name T124
Test name
Test status
Simulation time 123174386 ps
CPU time 2.58 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 217724 kb
Host smart-adcbfeb1-6dda-4c0a-ab98-112c4c9c2559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107781821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4107781821
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1632452217
Short name T157
Test name
Test status
Simulation time 62229954 ps
CPU time 1.27 seconds
Started May 26 02:52:35 PM PDT 24
Finished May 26 02:52:38 PM PDT 24
Peak memory 217732 kb
Host smart-9007cc4a-2f6b-483b-90f7-bc2367262235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632452217 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1632452217
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4086792879
Short name T980
Test name
Test status
Simulation time 16808683 ps
CPU time 1.15 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:37 PM PDT 24
Peak memory 209284 kb
Host smart-5c53afb6-ceb4-42f4-aaa1-0471cad56378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086792879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.4086792879
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.80725474
Short name T903
Test name
Test status
Simulation time 179470263 ps
CPU time 1.13 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:38 PM PDT 24
Peak memory 207992 kb
Host smart-6ada1f09-3e2d-49c5-87de-866019aa4412
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80725474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_alert_test.80725474
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.935138646
Short name T987
Test name
Test status
Simulation time 535192138 ps
CPU time 11.55 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:48 PM PDT 24
Peak memory 209172 kb
Host smart-9b8d5a58-5768-4e2b-9b86-6f09c25e5da3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935138646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.935138646
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.691571970
Short name T914
Test name
Test status
Simulation time 2284599338 ps
CPU time 14.04 seconds
Started May 26 02:52:32 PM PDT 24
Finished May 26 02:52:49 PM PDT 24
Peak memory 209220 kb
Host smart-72d93721-d08a-4364-8dad-b12da3547885
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691571970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.691571970
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3670160392
Short name T130
Test name
Test status
Simulation time 103443588 ps
CPU time 1.39 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:35 PM PDT 24
Peak memory 210740 kb
Host smart-d77409cc-0fc2-48dd-a89e-f5c0413331a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670160392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3670160392
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2393055456
Short name T166
Test name
Test status
Simulation time 102317143 ps
CPU time 1.31 seconds
Started May 26 02:52:37 PM PDT 24
Finished May 26 02:52:41 PM PDT 24
Peak memory 218692 kb
Host smart-a7d830e5-f8d3-4d02-905d-7c0698b22b17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239305
5456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2393055456
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2588123220
Short name T917
Test name
Test status
Simulation time 377605588 ps
CPU time 1.52 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 208548 kb
Host smart-270c9686-2c5f-4c89-8d50-ccd1825e2b97
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588123220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2588123220
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1563867932
Short name T929
Test name
Test status
Simulation time 43802442 ps
CPU time 1.34 seconds
Started May 26 02:52:37 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 209496 kb
Host smart-efa01591-5fcc-43e5-a2e6-5d460bfc5190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563867932 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1563867932
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3868949715
Short name T919
Test name
Test status
Simulation time 16767149 ps
CPU time 1.02 seconds
Started May 26 02:52:32 PM PDT 24
Finished May 26 02:52:35 PM PDT 24
Peak memory 209480 kb
Host smart-67dd26f0-2108-4088-9bd6-fa31186e0199
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868949715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3868949715
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3064465438
Short name T107
Test name
Test status
Simulation time 42486950 ps
CPU time 2.78 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 218696 kb
Host smart-42e1332c-aaa6-4d1e-a62e-d9549a030ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064465438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3064465438
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3228204957
Short name T948
Test name
Test status
Simulation time 28921969 ps
CPU time 1.6 seconds
Started May 26 02:52:34 PM PDT 24
Finished May 26 02:52:38 PM PDT 24
Peak memory 218252 kb
Host smart-0dd4bbfb-90e3-4972-ac5c-8adeae890ed6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228204957 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3228204957
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3191658397
Short name T888
Test name
Test status
Simulation time 15085311 ps
CPU time 0.89 seconds
Started May 26 02:52:35 PM PDT 24
Finished May 26 02:52:38 PM PDT 24
Peak memory 208964 kb
Host smart-c69185ae-5934-40b1-bc23-24a4034a8e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191658397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3191658397
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1438456168
Short name T960
Test name
Test status
Simulation time 31875193 ps
CPU time 1.36 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:52:47 PM PDT 24
Peak memory 209352 kb
Host smart-6b6fe5ce-ac91-47a1-8ad9-8eaf57ef79f7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438456168 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1438456168
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1065449843
Short name T945
Test name
Test status
Simulation time 3476861991 ps
CPU time 10.78 seconds
Started May 26 02:52:35 PM PDT 24
Finished May 26 02:52:49 PM PDT 24
Peak memory 208180 kb
Host smart-967c3f11-f88e-4062-ade7-8a0e94b35de3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065449843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1065449843
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2871099682
Short name T895
Test name
Test status
Simulation time 2865439558 ps
CPU time 6.8 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 209448 kb
Host smart-e842e089-8f28-48f9-9515-f564a3e824cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871099682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2871099682
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2590367808
Short name T998
Test name
Test status
Simulation time 76633888 ps
CPU time 1.71 seconds
Started May 26 02:52:35 PM PDT 24
Finished May 26 02:52:40 PM PDT 24
Peak memory 210736 kb
Host smart-04eaaa26-0516-4abb-bf85-35b71807ddaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590367808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2590367808
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1054016227
Short name T934
Test name
Test status
Simulation time 65918344 ps
CPU time 1.62 seconds
Started May 26 02:52:35 PM PDT 24
Finished May 26 02:52:39 PM PDT 24
Peak memory 217740 kb
Host smart-56182cdc-355b-4777-af2f-ceb94797df0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105401
6227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1054016227
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2870104145
Short name T129
Test name
Test status
Simulation time 609206909 ps
CPU time 1.14 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:43 PM PDT 24
Peak memory 208532 kb
Host smart-659c119c-60df-4fb4-99fd-49b9ae3d563c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870104145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2870104145
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.421063714
Short name T943
Test name
Test status
Simulation time 64911629 ps
CPU time 0.98 seconds
Started May 26 02:52:32 PM PDT 24
Finished May 26 02:52:36 PM PDT 24
Peak memory 209492 kb
Host smart-0f6b5137-b561-421b-b773-3d8bdbfa336d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421063714 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.421063714
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3899367544
Short name T972
Test name
Test status
Simulation time 107820390 ps
CPU time 1.16 seconds
Started May 26 02:52:31 PM PDT 24
Finished May 26 02:52:34 PM PDT 24
Peak memory 209484 kb
Host smart-8799d6cc-9e65-4e2d-9059-73f44597f6e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899367544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3899367544
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4274544258
Short name T956
Test name
Test status
Simulation time 51927256 ps
CPU time 3.24 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 219176 kb
Host smart-eda8ea77-c6de-4c0a-af29-726955bcf5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274544258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4274544258
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2366397072
Short name T255
Test name
Test status
Simulation time 22711924 ps
CPU time 1.08 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 209684 kb
Host smart-e8487a71-1e44-4e14-82c5-7083cfcb847f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366397072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2366397072
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.4016284895
Short name T714
Test name
Test status
Simulation time 3777660458 ps
CPU time 14.38 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:56 PM PDT 24
Peak memory 219108 kb
Host smart-d279039c-e778-4906-b02c-0b6cc6034a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016284895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.4016284895
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.305931491
Short name T371
Test name
Test status
Simulation time 226680291 ps
CPU time 3.42 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:52:48 PM PDT 24
Peak memory 209624 kb
Host smart-a17ba7c3-bfb6-45e1-899c-2fed6d9290c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305931491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.305931491
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2731971617
Short name T23
Test name
Test status
Simulation time 7697341291 ps
CPU time 38.79 seconds
Started May 26 02:52:50 PM PDT 24
Finished May 26 02:53:30 PM PDT 24
Peak memory 219032 kb
Host smart-79dd049c-5511-4b82-bfb6-49fdf11cf8b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731971617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2731971617
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3003563765
Short name T742
Test name
Test status
Simulation time 385764884 ps
CPU time 2.78 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 217264 kb
Host smart-d723c167-330a-49c9-8239-7c0cfd53ce27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003563765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
003563765
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.170690371
Short name T290
Test name
Test status
Simulation time 473446299 ps
CPU time 2.87 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:46 PM PDT 24
Peak memory 217904 kb
Host smart-85545133-ae5a-4d16-9dba-f276dfc0610d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170690371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.170690371
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2639958728
Short name T269
Test name
Test status
Simulation time 24192044202 ps
CPU time 18.51 seconds
Started May 26 02:52:52 PM PDT 24
Finished May 26 02:53:11 PM PDT 24
Peak memory 214052 kb
Host smart-5daec790-192c-4b72-b209-d5446e7d3904
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639958728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2639958728
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.509297251
Short name T683
Test name
Test status
Simulation time 452405920 ps
CPU time 11.88 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:53:00 PM PDT 24
Peak memory 213736 kb
Host smart-4de93e7b-0c43-4fdd-a1b7-cce8c77b242b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509297251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.509297251
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.197159002
Short name T755
Test name
Test status
Simulation time 5766214920 ps
CPU time 94.96 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 267356 kb
Host smart-2e288197-4d9d-4a02-abbb-cf73f030456b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197159002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.197159002
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3317482592
Short name T518
Test name
Test status
Simulation time 451535984 ps
CPU time 19.05 seconds
Started May 26 02:52:45 PM PDT 24
Finished May 26 02:53:05 PM PDT 24
Peak memory 250900 kb
Host smart-dcac432e-d140-4f1f-8893-00169ed6a773
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317482592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3317482592
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2528352555
Short name T879
Test name
Test status
Simulation time 60814180 ps
CPU time 2.76 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:47 PM PDT 24
Peak memory 218192 kb
Host smart-020ff9e8-1d27-4db4-afac-1242668dee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528352555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2528352555
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2631972077
Short name T433
Test name
Test status
Simulation time 192883104 ps
CPU time 7.65 seconds
Started May 26 02:52:44 PM PDT 24
Finished May 26 02:52:53 PM PDT 24
Peak memory 218028 kb
Host smart-6926db44-99db-414b-821e-11e961d31163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631972077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2631972077
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3386469700
Short name T774
Test name
Test status
Simulation time 3585279073 ps
CPU time 19.6 seconds
Started May 26 02:52:42 PM PDT 24
Finished May 26 02:53:04 PM PDT 24
Peak memory 226268 kb
Host smart-580e947c-6c22-4750-9864-8009d587f2b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386469700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3386469700
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.533736457
Short name T302
Test name
Test status
Simulation time 438041344 ps
CPU time 17.68 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:31 PM PDT 24
Peak memory 218052 kb
Host smart-2ebdb262-6526-43d8-acea-7f1f0992e128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533736457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.533736457
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.452835613
Short name T449
Test name
Test status
Simulation time 641987367 ps
CPU time 9.03 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:52:52 PM PDT 24
Peak memory 218056 kb
Host smart-6ee43316-5489-4a64-a0c6-4189f8f7b16d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452835613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.452835613
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.4235374808
Short name T248
Test name
Test status
Simulation time 339969795 ps
CPU time 12.98 seconds
Started May 26 02:52:42 PM PDT 24
Finished May 26 02:52:57 PM PDT 24
Peak memory 218168 kb
Host smart-67c84fb9-346e-439e-b065-0929dea2013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235374808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4235374808
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3093754512
Short name T877
Test name
Test status
Simulation time 66824209 ps
CPU time 2.68 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:52:46 PM PDT 24
Peak memory 214496 kb
Host smart-0007bef7-fba0-4333-80ae-e8f4fc4f4fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093754512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3093754512
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.961144409
Short name T692
Test name
Test status
Simulation time 562476809 ps
CPU time 17.45 seconds
Started May 26 02:52:46 PM PDT 24
Finished May 26 02:53:05 PM PDT 24
Peak memory 250988 kb
Host smart-758ebca2-b39a-479d-bc5c-cc0938d54faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961144409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.961144409
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1895631902
Short name T842
Test name
Test status
Simulation time 98090227 ps
CPU time 7.27 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:50 PM PDT 24
Peak memory 250564 kb
Host smart-14065c1d-2fab-42ad-8de0-4f1873a8dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895631902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1895631902
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1743669785
Short name T856
Test name
Test status
Simulation time 7749452777 ps
CPU time 238.65 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:57:08 PM PDT 24
Peak memory 272088 kb
Host smart-be01b6c9-1bbf-4233-bb0a-87b6b76cb36e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743669785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1743669785
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2851427635
Short name T374
Test name
Test status
Simulation time 12392268 ps
CPU time 0.98 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:43 PM PDT 24
Peak memory 211604 kb
Host smart-479b6446-c302-4e9a-abbf-1483396da50f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851427635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2851427635
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.400206288
Short name T880
Test name
Test status
Simulation time 62880975 ps
CPU time 0.99 seconds
Started May 26 02:52:50 PM PDT 24
Finished May 26 02:52:52 PM PDT 24
Peak memory 209664 kb
Host smart-85404dea-c897-40d0-9461-d19b98772b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400206288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.400206288
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3187480755
Short name T602
Test name
Test status
Simulation time 26114467 ps
CPU time 0.83 seconds
Started May 26 02:53:12 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 209556 kb
Host smart-0f767bc5-0e47-46de-bd15-b8e56afe5285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187480755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3187480755
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1832601665
Short name T536
Test name
Test status
Simulation time 1441332104 ps
CPU time 18.44 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:53:00 PM PDT 24
Peak memory 218156 kb
Host smart-4cf7e0c0-8b93-4c40-8aec-ff0da3ec05a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832601665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1832601665
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3074138916
Short name T643
Test name
Test status
Simulation time 2969941805 ps
CPU time 25.34 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:53:09 PM PDT 24
Peak memory 218048 kb
Host smart-3282d3ff-19c3-419d-9d68-f48da0bcfd4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074138916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3074138916
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2260907679
Short name T204
Test name
Test status
Simulation time 577265401 ps
CPU time 8.47 seconds
Started May 26 02:52:44 PM PDT 24
Finished May 26 02:52:54 PM PDT 24
Peak memory 217660 kb
Host smart-f4e744e0-e708-4ef8-87b6-4b66d6c438ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260907679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
260907679
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.4057844717
Short name T288
Test name
Test status
Simulation time 320079339 ps
CPU time 3.55 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:45 PM PDT 24
Peak memory 218052 kb
Host smart-ed405660-544f-48fe-8475-470d0baa64f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057844717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.4057844717
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.881173352
Short name T684
Test name
Test status
Simulation time 2945047319 ps
CPU time 18.84 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:53:01 PM PDT 24
Peak memory 213696 kb
Host smart-4958d621-16b7-49dd-944a-e8caf8d27e4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881173352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.881173352
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3803977351
Short name T664
Test name
Test status
Simulation time 406234083 ps
CPU time 7.06 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:52:49 PM PDT 24
Peak memory 213868 kb
Host smart-e6d80ac9-a939-454c-8c39-1ae38dc6796d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803977351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3803977351
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.780775847
Short name T2
Test name
Test status
Simulation time 885101211 ps
CPU time 30.91 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 251120 kb
Host smart-6b3f393c-884e-4ae0-8322-68ef09df86ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780775847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.780775847
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.209675937
Short name T356
Test name
Test status
Simulation time 2719965995 ps
CPU time 16.69 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:53:02 PM PDT 24
Peak memory 250976 kb
Host smart-59ac5a2d-3025-46da-a4df-307d4e001f4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209675937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.209675937
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1809037110
Short name T402
Test name
Test status
Simulation time 295507368 ps
CPU time 3.99 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:52:49 PM PDT 24
Peak memory 218104 kb
Host smart-e4d6ae3d-3383-45a1-b201-d6db7334312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809037110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1809037110
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.640558738
Short name T154
Test name
Test status
Simulation time 358467285 ps
CPU time 9.13 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:53 PM PDT 24
Peak memory 217932 kb
Host smart-e66b4684-0df3-45c0-9cc5-1c7cfb8d7115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640558738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.640558738
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.335688459
Short name T61
Test name
Test status
Simulation time 521332639 ps
CPU time 22.28 seconds
Started May 26 02:52:45 PM PDT 24
Finished May 26 02:53:08 PM PDT 24
Peak memory 281388 kb
Host smart-44506dc2-dc8c-4b2d-985b-bb1e5d618f5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335688459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.335688459
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1379673079
Short name T754
Test name
Test status
Simulation time 218370439 ps
CPU time 9.59 seconds
Started May 26 02:52:53 PM PDT 24
Finished May 26 02:53:03 PM PDT 24
Peak memory 219240 kb
Host smart-60ae77ed-7d88-4373-816c-06eb5139b805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379673079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1379673079
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3945030459
Short name T654
Test name
Test status
Simulation time 296535133 ps
CPU time 8.4 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:52:51 PM PDT 24
Peak memory 218052 kb
Host smart-25bb97d5-d36c-4312-a04d-0860047858f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945030459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
945030459
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2529933672
Short name T369
Test name
Test status
Simulation time 229828237 ps
CPU time 6.27 seconds
Started May 26 02:52:49 PM PDT 24
Finished May 26 02:52:56 PM PDT 24
Peak memory 218184 kb
Host smart-c5abd0f2-cade-4d53-8d4c-b1f80477bfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529933672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2529933672
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1220266045
Short name T698
Test name
Test status
Simulation time 88406650 ps
CPU time 2.68 seconds
Started May 26 02:52:44 PM PDT 24
Finished May 26 02:52:49 PM PDT 24
Peak memory 217992 kb
Host smart-c775ad2e-e78b-4d0d-81d5-42c8e604c0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220266045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1220266045
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.300281217
Short name T452
Test name
Test status
Simulation time 2175000962 ps
CPU time 26.41 seconds
Started May 26 02:52:39 PM PDT 24
Finished May 26 02:53:08 PM PDT 24
Peak memory 251096 kb
Host smart-631b829a-e5db-4f57-a893-0f397f19b002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300281217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.300281217
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3485916129
Short name T705
Test name
Test status
Simulation time 327394963 ps
CPU time 7.45 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:17 PM PDT 24
Peak memory 250504 kb
Host smart-49686ae4-9123-4d04-b67e-edb477d1186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485916129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3485916129
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.222170856
Short name T588
Test name
Test status
Simulation time 8869426393 ps
CPU time 36.56 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:53:19 PM PDT 24
Peak memory 245912 kb
Host smart-67c49bb7-04d8-41a0-8e2a-f0838eea12ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222170856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.222170856
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4076725636
Short name T410
Test name
Test status
Simulation time 74616596 ps
CPU time 1.08 seconds
Started May 26 02:52:49 PM PDT 24
Finished May 26 02:52:51 PM PDT 24
Peak memory 211656 kb
Host smart-d36becd9-c864-4893-a805-fbadbce5d1ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076725636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.4076725636
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.72019747
Short name T432
Test name
Test status
Simulation time 31813918 ps
CPU time 0.85 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:20 PM PDT 24
Peak memory 209652 kb
Host smart-2f24fd8c-21de-4dde-9ad0-8746d6dbb6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72019747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.72019747
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2533287329
Short name T510
Test name
Test status
Simulation time 307119331 ps
CPU time 9.14 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:42 PM PDT 24
Peak memory 218120 kb
Host smart-d901b685-a0d4-46f1-9f3f-fb75918ad535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533287329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2533287329
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.166245635
Short name T574
Test name
Test status
Simulation time 629877244 ps
CPU time 2.85 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 216960 kb
Host smart-626ba2b5-b468-4b73-a099-0b0b0ee2ea72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166245635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.166245635
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1886735337
Short name T728
Test name
Test status
Simulation time 1279092327 ps
CPU time 20.41 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:41 PM PDT 24
Peak memory 217996 kb
Host smart-a661c4dc-a1f9-4f9d-b458-c644f71fbb7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886735337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1886735337
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2386322708
Short name T551
Test name
Test status
Simulation time 207502928 ps
CPU time 3.76 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 218072 kb
Host smart-640977b3-cf0d-4e4d-acad-23679f0ae4f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386322708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2386322708
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3407512102
Short name T493
Test name
Test status
Simulation time 661591952 ps
CPU time 3.77 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 213420 kb
Host smart-cf98835b-0263-4bf1-94ea-a5f6bfbdae33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407512102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3407512102
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3687844951
Short name T675
Test name
Test status
Simulation time 8650288927 ps
CPU time 32.65 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:54 PM PDT 24
Peak memory 251040 kb
Host smart-5c531306-6b3a-413b-ba34-aa33d57fe83b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687844951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3687844951
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1222844183
Short name T5
Test name
Test status
Simulation time 1207146393 ps
CPU time 20.86 seconds
Started May 26 02:53:20 PM PDT 24
Finished May 26 02:53:44 PM PDT 24
Peak memory 246168 kb
Host smart-f820701e-233b-4480-b3e5-1c97adcfecea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222844183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1222844183
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1382541871
Short name T327
Test name
Test status
Simulation time 56849810 ps
CPU time 2.74 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:29 PM PDT 24
Peak memory 218140 kb
Host smart-1d8f6af0-caa1-4541-bbcb-7c73b7f4b198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382541871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1382541871
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2760909666
Short name T780
Test name
Test status
Simulation time 1345503467 ps
CPU time 10.01 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 219072 kb
Host smart-d92f0b91-aeb2-471d-b2ad-6a2c278fa0ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760909666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2760909666
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.708413193
Short name T353
Test name
Test status
Simulation time 1488386818 ps
CPU time 15.52 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 218108 kb
Host smart-17898342-3ef5-4a8f-a84f-2b8f63c0a96f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708413193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.708413193
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1463945838
Short name T748
Test name
Test status
Simulation time 1359933556 ps
CPU time 13.35 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 218032 kb
Host smart-eba1e3a5-b41a-4640-af18-b28e28438e93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463945838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1463945838
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.565513542
Short name T673
Test name
Test status
Simulation time 265975665 ps
CPU time 7.1 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 218188 kb
Host smart-60b58e6d-bf44-4cdc-85b6-35984a382135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565513542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.565513542
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.791166142
Short name T72
Test name
Test status
Simulation time 69760031 ps
CPU time 1.54 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 213588 kb
Host smart-34bd3292-b3a9-4209-b156-3614cd84df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791166142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.791166142
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2603873814
Short name T384
Test name
Test status
Simulation time 533196039 ps
CPU time 31.28 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:53:56 PM PDT 24
Peak memory 251176 kb
Host smart-91d72c3c-b08a-47de-92a2-05ececdfa07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603873814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2603873814
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2247375445
Short name T626
Test name
Test status
Simulation time 203087754 ps
CPU time 3.79 seconds
Started May 26 02:53:12 PM PDT 24
Finished May 26 02:53:19 PM PDT 24
Peak memory 222824 kb
Host smart-2d52c0e8-d3bf-41bf-a5e6-bd0216446afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247375445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2247375445
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1383356397
Short name T405
Test name
Test status
Simulation time 603201610 ps
CPU time 42.64 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:54:02 PM PDT 24
Peak memory 267452 kb
Host smart-e4fda687-7d1f-40bf-91c3-98ef67bf86aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383356397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1383356397
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4212738487
Short name T48
Test name
Test status
Simulation time 23588202 ps
CPU time 1.04 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 211612 kb
Host smart-2d141c8f-9a24-4a4c-b594-a3eabf8db527
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212738487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4212738487
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2348509229
Short name T519
Test name
Test status
Simulation time 16432692 ps
CPU time 0.9 seconds
Started May 26 02:53:12 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 209692 kb
Host smart-ca10c44f-f667-4eea-a588-6c3160bb9cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348509229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2348509229
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.919077267
Short name T236
Test name
Test status
Simulation time 1602417547 ps
CPU time 12.46 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 218116 kb
Host smart-f86e5b7d-6056-47e4-8b99-f2ab7acdfe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919077267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.919077267
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.983537205
Short name T377
Test name
Test status
Simulation time 499013409 ps
CPU time 2.2 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 216932 kb
Host smart-37121824-1bd9-4178-9229-010f761a6416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983537205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.983537205
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.226280313
Short name T809
Test name
Test status
Simulation time 7574225486 ps
CPU time 61.29 seconds
Started May 26 02:53:19 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 219104 kb
Host smart-954095ac-e042-4b88-bd78-96d19db27b88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226280313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.226280313
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4169644887
Short name T857
Test name
Test status
Simulation time 916570016 ps
CPU time 11.18 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:32 PM PDT 24
Peak memory 217980 kb
Host smart-69d1a330-9da2-443e-bbe4-90310e26514c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169644887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4169644887
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1007066613
Short name T289
Test name
Test status
Simulation time 255915489 ps
CPU time 4 seconds
Started May 26 02:53:24 PM PDT 24
Finished May 26 02:53:30 PM PDT 24
Peak memory 213292 kb
Host smart-b2877e81-cc80-4b47-8eaf-d118f4704a70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007066613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1007066613
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3379552453
Short name T745
Test name
Test status
Simulation time 5991405157 ps
CPU time 53.33 seconds
Started May 26 02:53:23 PM PDT 24
Finished May 26 02:54:18 PM PDT 24
Peak memory 275588 kb
Host smart-07df8bb5-dc60-4da2-9181-7ad70b470d8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379552453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3379552453
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1317561342
Short name T657
Test name
Test status
Simulation time 442066193 ps
CPU time 18.21 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 249608 kb
Host smart-132b6d8e-d2bf-4bc6-8252-926f72adff9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317561342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1317561342
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.738654059
Short name T366
Test name
Test status
Simulation time 68878932 ps
CPU time 1.42 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 218192 kb
Host smart-bf8f4fa0-e445-4273-ad61-9e28cfd26006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738654059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.738654059
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4067683861
Short name T44
Test name
Test status
Simulation time 1728090252 ps
CPU time 17.65 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 226184 kb
Host smart-a8c831d4-1d23-48ee-9248-77c7b2066d83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067683861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4067683861
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1162948955
Short name T861
Test name
Test status
Simulation time 550199643 ps
CPU time 12.38 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 218060 kb
Host smart-fd7f0d34-ed8d-4b95-bae8-fa83a1304772
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162948955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1162948955
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2194978182
Short name T843
Test name
Test status
Simulation time 2502807554 ps
CPU time 12.4 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 218128 kb
Host smart-78d98793-7d02-4ec4-a8ad-75c47c49c0ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194978182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2194978182
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1179625446
Short name T453
Test name
Test status
Simulation time 503541244 ps
CPU time 16.53 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 218168 kb
Host smart-57a93beb-55e6-4440-9db3-4078a4cabe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179625446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1179625446
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.387934187
Short name T529
Test name
Test status
Simulation time 40929751 ps
CPU time 1.99 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 213928 kb
Host smart-605b416a-df5f-4004-9c51-e6a1dbc2c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387934187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.387934187
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3123174022
Short name T273
Test name
Test status
Simulation time 554030550 ps
CPU time 34.93 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:55 PM PDT 24
Peak memory 251028 kb
Host smart-9540713a-1d9d-4318-8ed6-39da49316adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123174022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3123174022
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.78941630
Short name T615
Test name
Test status
Simulation time 94784636 ps
CPU time 7.89 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:25 PM PDT 24
Peak memory 247440 kb
Host smart-9fae8bd9-1d28-4a1e-842b-fa30682c82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78941630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.78941630
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2324609621
Short name T612
Test name
Test status
Simulation time 2409303967 ps
CPU time 120.22 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:55:24 PM PDT 24
Peak memory 251124 kb
Host smart-5a08916a-52ce-45c6-bf18-f704acc4bc0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324609621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2324609621
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.856257552
Short name T56
Test name
Test status
Simulation time 22314461804 ps
CPU time 384.03 seconds
Started May 26 02:53:21 PM PDT 24
Finished May 26 02:59:48 PM PDT 24
Peak memory 283952 kb
Host smart-e2aaba2c-05fb-45a1-859c-60540873b5d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=856257552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.856257552
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1722526277
Short name T764
Test name
Test status
Simulation time 14429707 ps
CPU time 0.87 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 211636 kb
Host smart-6d6bca8a-1249-40e9-9651-9a98b3d9f5ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722526277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1722526277
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1855061622
Short name T603
Test name
Test status
Simulation time 14029383 ps
CPU time 0.89 seconds
Started May 26 02:53:49 PM PDT 24
Finished May 26 02:53:51 PM PDT 24
Peak memory 209688 kb
Host smart-85dd74f3-8084-4492-a197-04cbddb9e046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855061622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1855061622
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2732643570
Short name T409
Test name
Test status
Simulation time 459450784 ps
CPU time 11.35 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:43 PM PDT 24
Peak memory 218144 kb
Host smart-562b44eb-3ffc-4b4f-905a-53d5c02df554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732643570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2732643570
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3303741908
Short name T9
Test name
Test status
Simulation time 395872599 ps
CPU time 4.88 seconds
Started May 26 02:53:37 PM PDT 24
Finished May 26 02:53:44 PM PDT 24
Peak memory 209632 kb
Host smart-0f5b2494-9303-4380-b47f-96a186ed2762
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303741908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3303741908
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2579452592
Short name T487
Test name
Test status
Simulation time 13639660039 ps
CPU time 50.16 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 219604 kb
Host smart-728a96a0-5fb6-4bb8-947a-3fc57e9d5229
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579452592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2579452592
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2717410545
Short name T309
Test name
Test status
Simulation time 649568568 ps
CPU time 6.23 seconds
Started May 26 02:53:24 PM PDT 24
Finished May 26 02:53:31 PM PDT 24
Peak memory 218144 kb
Host smart-1520fa12-1bdd-4639-8226-1c7b25ea9fc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717410545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2717410545
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3653714035
Short name T589
Test name
Test status
Simulation time 979479841 ps
CPU time 3.67 seconds
Started May 26 02:53:19 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 213208 kb
Host smart-9671ac43-25a9-4215-8e43-9b1e1551ac1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653714035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3653714035
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3997398707
Short name T874
Test name
Test status
Simulation time 10830421097 ps
CPU time 62.08 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:54:34 PM PDT 24
Peak memory 283792 kb
Host smart-0d92f5ba-423b-4bad-9132-023424a54c73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997398707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3997398707
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2560757694
Short name T737
Test name
Test status
Simulation time 1312106399 ps
CPU time 14.7 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:53:48 PM PDT 24
Peak memory 250484 kb
Host smart-7e64e8b5-7bc2-4df9-9642-7564c76be03c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560757694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2560757694
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3616914908
Short name T38
Test name
Test status
Simulation time 114945736 ps
CPU time 3.2 seconds
Started May 26 02:53:21 PM PDT 24
Finished May 26 02:53:27 PM PDT 24
Peak memory 218100 kb
Host smart-ea052cb5-ac62-41ff-85ec-6fe54f63c5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616914908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3616914908
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.4218967295
Short name T607
Test name
Test status
Simulation time 272053476 ps
CPU time 10.47 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 226168 kb
Host smart-a2e225b1-3a14-4ade-acbe-d8a818b4a549
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218967295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.4218967295
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.296846079
Short name T284
Test name
Test status
Simulation time 418773841 ps
CPU time 6.94 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 218060 kb
Host smart-4a39e131-60f7-4d56-aac7-7b981286e9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296846079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.296846079
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2992679556
Short name T454
Test name
Test status
Simulation time 233923368 ps
CPU time 7.44 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 218068 kb
Host smart-5bf03092-8553-47e2-ac03-59f1c75ed5ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992679556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2992679556
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2969924723
Short name T544
Test name
Test status
Simulation time 516518844 ps
CPU time 10.23 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 218136 kb
Host smart-a01abc00-b729-48f8-9a1c-1e66318a8c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969924723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2969924723
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.32205553
Short name T758
Test name
Test status
Simulation time 76353435 ps
CPU time 1.21 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 213516 kb
Host smart-e789e000-577c-4add-965e-3554935369f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32205553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.32205553
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1897373780
Short name T326
Test name
Test status
Simulation time 3918349319 ps
CPU time 25.06 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 251064 kb
Host smart-a9106e71-9146-435b-a77c-bab77a906a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897373780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1897373780
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1234817694
Short name T328
Test name
Test status
Simulation time 391804995 ps
CPU time 6.97 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:27 PM PDT 24
Peak memory 250600 kb
Host smart-3d081f67-0a43-4c51-939c-feaf3be026a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234817694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1234817694
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.404326078
Short name T252
Test name
Test status
Simulation time 264641255 ps
CPU time 18.05 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:50 PM PDT 24
Peak memory 246824 kb
Host smart-6ff83454-82a1-4584-8db9-c87b337b8bcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404326078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.404326078
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3755074278
Short name T750
Test name
Test status
Simulation time 133925935 ps
CPU time 0.94 seconds
Started May 26 02:53:17 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 208652 kb
Host smart-bf615584-6300-43f6-9e4d-6b87351e479e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755074278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3755074278
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2086683167
Short name T317
Test name
Test status
Simulation time 3578428934 ps
CPU time 10.24 seconds
Started May 26 02:53:24 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 218264 kb
Host smart-ee7e3ae2-a4f3-4787-93db-6cf72ee29ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086683167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2086683167
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3095169680
Short name T367
Test name
Test status
Simulation time 148101333 ps
CPU time 2.37 seconds
Started May 26 02:53:40 PM PDT 24
Finished May 26 02:53:43 PM PDT 24
Peak memory 209628 kb
Host smart-87ac53d7-a27e-4b67-af1b-5f28fcbc622e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095169680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3095169680
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.4208264983
Short name T178
Test name
Test status
Simulation time 3158038940 ps
CPU time 49.32 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:54:14 PM PDT 24
Peak memory 219044 kb
Host smart-737cd444-ca0d-4d26-b1d1-d2f78404268b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208264983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.4208264983
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3098534690
Short name T482
Test name
Test status
Simulation time 949270411 ps
CPU time 4.19 seconds
Started May 26 02:53:21 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 218244 kb
Host smart-e87f3a4b-d37a-4499-a138-beb66ef1a3df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098534690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3098534690
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2298569226
Short name T306
Test name
Test status
Simulation time 2568798781 ps
CPU time 7.6 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 213952 kb
Host smart-c2891459-1a47-4e75-8a02-6653930eb6e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298569226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2298569226
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2829244947
Short name T604
Test name
Test status
Simulation time 14555727330 ps
CPU time 54.5 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 277896 kb
Host smart-5cea479a-9a08-4d12-a1cd-8214618f062d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829244947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2829244947
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1762191344
Short name T22
Test name
Test status
Simulation time 798838939 ps
CPU time 11.8 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 250332 kb
Host smart-f83c146e-e582-43d3-b567-382a8079cc73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762191344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1762191344
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4085400642
Short name T848
Test name
Test status
Simulation time 72737921 ps
CPU time 3.08 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 218144 kb
Host smart-86a28039-152f-40cc-9fa1-29d9b3b38474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085400642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4085400642
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3719653393
Short name T211
Test name
Test status
Simulation time 464257257 ps
CPU time 17.39 seconds
Started May 26 02:53:20 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 219064 kb
Host smart-52b2533c-59dc-45ae-8dbc-d60f2a8307aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719653393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3719653393
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2914027979
Short name T267
Test name
Test status
Simulation time 254066523 ps
CPU time 7.65 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:34 PM PDT 24
Peak memory 218052 kb
Host smart-b1a8009b-2ad1-4eb9-97a9-0d80250a6576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914027979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2914027979
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2633099700
Short name T864
Test name
Test status
Simulation time 2958350223 ps
CPU time 9.5 seconds
Started May 26 02:53:23 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 218112 kb
Host smart-a685cc05-6e71-4c0c-88d1-684318a522d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633099700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2633099700
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.899354050
Short name T419
Test name
Test status
Simulation time 405301490 ps
CPU time 10.75 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:41 PM PDT 24
Peak memory 218200 kb
Host smart-d2f85c20-9cc9-4909-833e-5396d3972bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899354050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.899354050
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2002752664
Short name T724
Test name
Test status
Simulation time 82938163 ps
CPU time 2.67 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:31 PM PDT 24
Peak memory 217932 kb
Host smart-09d79e95-fb70-483c-8ac7-8e9de1d36be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002752664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2002752664
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2659710019
Short name T296
Test name
Test status
Simulation time 793000182 ps
CPU time 30.19 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:54:03 PM PDT 24
Peak memory 251072 kb
Host smart-8cffc3f0-1cd4-4e21-82fd-1bfab0eadb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659710019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2659710019
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1533772741
Short name T164
Test name
Test status
Simulation time 216648135 ps
CPU time 5.88 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:34 PM PDT 24
Peak memory 250696 kb
Host smart-9e0a6a54-cde5-452c-a100-7b510521ccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533772741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1533772741
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4172886685
Short name T420
Test name
Test status
Simulation time 15115378 ps
CPU time 1.16 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 211760 kb
Host smart-04741a6c-4518-4617-b023-edaaf99e6977
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172886685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.4172886685
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3892561931
Short name T520
Test name
Test status
Simulation time 17070173 ps
CPU time 0.95 seconds
Started May 26 02:53:20 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 209620 kb
Host smart-c6679040-485c-4d2e-9b56-96b0ecc87daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892561931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3892561931
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2095219322
Short name T153
Test name
Test status
Simulation time 1170534799 ps
CPU time 12.46 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:43 PM PDT 24
Peak memory 218120 kb
Host smart-f025908d-8b39-4d29-b718-c2eb95186886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095219322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2095219322
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3166362217
Short name T697
Test name
Test status
Simulation time 3479822651 ps
CPU time 5.29 seconds
Started May 26 02:53:36 PM PDT 24
Finished May 26 02:53:43 PM PDT 24
Peak memory 209748 kb
Host smart-6d18cdf1-c889-4f80-b1bf-af48b87f6121
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166362217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3166362217
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2608750620
Short name T817
Test name
Test status
Simulation time 2870075087 ps
CPU time 41.21 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:54:11 PM PDT 24
Peak memory 219020 kb
Host smart-57c3df4f-a310-48ae-a2f0-be811fb3b45d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608750620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2608750620
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2362195533
Short name T393
Test name
Test status
Simulation time 1949820940 ps
CPU time 6.95 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 218048 kb
Host smart-c25f00fc-449d-4c9a-aba1-6865ab977989
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362195533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2362195533
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.470839471
Short name T649
Test name
Test status
Simulation time 2446231906 ps
CPU time 5.26 seconds
Started May 26 02:53:19 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 213644 kb
Host smart-1f845139-bad9-4eea-8e4a-15bc97b0344f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470839471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
470839471
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2677875924
Short name T868
Test name
Test status
Simulation time 4644590667 ps
CPU time 48.3 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:54:20 PM PDT 24
Peak memory 252412 kb
Host smart-910be90f-ae8d-42f3-a32d-489524babb5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677875924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2677875924
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1066546265
Short name T375
Test name
Test status
Simulation time 4980563203 ps
CPU time 14.53 seconds
Started May 26 02:53:36 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 248340 kb
Host smart-678b9457-b8a7-4b74-8d49-55f8d2501236
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066546265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1066546265
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2142267927
Short name T632
Test name
Test status
Simulation time 73425575 ps
CPU time 3.38 seconds
Started May 26 02:53:43 PM PDT 24
Finished May 26 02:53:47 PM PDT 24
Peak memory 218176 kb
Host smart-c1f91f49-65e4-4eb8-a76e-5c3797ead33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142267927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2142267927
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3880107455
Short name T819
Test name
Test status
Simulation time 483068088 ps
CPU time 14.14 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:44 PM PDT 24
Peak memory 218308 kb
Host smart-4696b3eb-244e-4654-9032-4c090181c972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880107455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3880107455
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1765989254
Short name T232
Test name
Test status
Simulation time 1713443124 ps
CPU time 16.26 seconds
Started May 26 02:53:19 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 218116 kb
Host smart-c2e11bf3-1912-448f-b6ec-732a39de6595
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765989254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1765989254
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3161397613
Short name T676
Test name
Test status
Simulation time 272278373 ps
CPU time 8.01 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 218204 kb
Host smart-2f79f6aa-7e99-455c-a06b-64d9f348f5a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161397613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3161397613
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2900503206
Short name T613
Test name
Test status
Simulation time 802747288 ps
CPU time 10.67 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 218172 kb
Host smart-391c89bc-c5ae-465c-9138-65c60d838448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900503206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2900503206
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2281028603
Short name T84
Test name
Test status
Simulation time 356920207 ps
CPU time 2.59 seconds
Started May 26 02:53:21 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 214164 kb
Host smart-a6a7ce34-25fc-4fd2-acce-e2f33965b9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281028603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2281028603
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2560997042
Short name T815
Test name
Test status
Simulation time 202577288 ps
CPU time 13.86 seconds
Started May 26 02:53:36 PM PDT 24
Finished May 26 02:53:52 PM PDT 24
Peak memory 250892 kb
Host smart-9604b5cd-fd88-457a-949f-d55cbbd7bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560997042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2560997042
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3654270905
Short name T70
Test name
Test status
Simulation time 10389752516 ps
CPU time 67.33 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:54:42 PM PDT 24
Peak memory 248644 kb
Host smart-3f14c859-6de9-4b0f-849a-20aad4ca8a34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654270905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3654270905
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2703070402
Short name T792
Test name
Test status
Simulation time 138746004810 ps
CPU time 1233.45 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 03:14:04 PM PDT 24
Peak memory 389436 kb
Host smart-0ff07996-14f4-45fc-8212-87e0b27edd67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2703070402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2703070402
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.4046169801
Short name T229
Test name
Test status
Simulation time 21482272 ps
CPU time 0.96 seconds
Started May 26 02:53:31 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 209692 kb
Host smart-1cf44e82-b22d-4d21-9007-e2e2e643eb41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046169801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4046169801
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2077396678
Short name T314
Test name
Test status
Simulation time 1600818031 ps
CPU time 17.64 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:50 PM PDT 24
Peak memory 217936 kb
Host smart-b312181d-ae3e-483e-b024-c72fa4b31eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077396678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2077396678
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2385898753
Short name T10
Test name
Test status
Simulation time 2029177766 ps
CPU time 6.51 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 217436 kb
Host smart-528fa51d-87af-4036-adfe-a811cf71b370
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385898753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2385898753
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.498155472
Short name T663
Test name
Test status
Simulation time 8009648188 ps
CPU time 35.36 seconds
Started May 26 02:53:38 PM PDT 24
Finished May 26 02:54:15 PM PDT 24
Peak memory 218444 kb
Host smart-35b6734d-173c-4630-a400-7beb43e29f45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498155472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.498155472
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2178654108
Short name T443
Test name
Test status
Simulation time 1493274612 ps
CPU time 5.42 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 217816 kb
Host smart-c1e0325d-f059-4d2a-93f8-45b1efa859d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178654108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2178654108
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2988310331
Short name T355
Test name
Test status
Simulation time 175312573 ps
CPU time 3.4 seconds
Started May 26 02:53:41 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 213212 kb
Host smart-c63f8e0a-abb1-4a71-a6bc-b58095b0f20f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988310331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2988310331
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.4147923591
Short name T610
Test name
Test status
Simulation time 2924327265 ps
CPU time 57.75 seconds
Started May 26 02:53:44 PM PDT 24
Finished May 26 02:54:43 PM PDT 24
Peak memory 283672 kb
Host smart-4ac47935-c55d-49f8-98db-8ded3d0a57b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147923591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.4147923591
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.793412792
Short name T800
Test name
Test status
Simulation time 2325126338 ps
CPU time 16.04 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:48 PM PDT 24
Peak memory 251028 kb
Host smart-bf0398ef-e826-464b-a027-6b9be90cb3b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793412792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.793412792
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1077121369
Short name T854
Test name
Test status
Simulation time 404569112 ps
CPU time 3.46 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:34 PM PDT 24
Peak memory 217852 kb
Host smart-46376d2b-b55a-41ff-af2e-d31a821129b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077121369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1077121369
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3472473393
Short name T841
Test name
Test status
Simulation time 311282357 ps
CPU time 13 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:41 PM PDT 24
Peak memory 218304 kb
Host smart-453e18d2-b7a2-4188-bd33-13afc5a771bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472473393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3472473393
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3625037235
Short name T287
Test name
Test status
Simulation time 2356000755 ps
CPU time 14.47 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:53:49 PM PDT 24
Peak memory 218112 kb
Host smart-16fdb6df-397c-4399-ba1e-ffe4252d47a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625037235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3625037235
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.136303221
Short name T351
Test name
Test status
Simulation time 215583158 ps
CPU time 5.89 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:53:41 PM PDT 24
Peak memory 218052 kb
Host smart-c0ec62ce-7ad2-4a48-a1b8-1e591103423d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136303221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.136303221
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1699716564
Short name T259
Test name
Test status
Simulation time 291973728 ps
CPU time 7.37 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:34 PM PDT 24
Peak memory 217988 kb
Host smart-83dbd803-a3cd-4c04-9d52-52fdf77ab2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699716564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1699716564
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1329682611
Short name T386
Test name
Test status
Simulation time 151706623 ps
CPU time 4.93 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 217828 kb
Host smart-132093f6-6e4e-4378-a232-448bbb1d91ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329682611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1329682611
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.613585771
Short name T573
Test name
Test status
Simulation time 274810349 ps
CPU time 24.28 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:56 PM PDT 24
Peak memory 251004 kb
Host smart-110f938f-2722-4795-b447-8fc4e0bcb5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613585771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.613585771
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1069815086
Short name T274
Test name
Test status
Simulation time 206625260 ps
CPU time 7.96 seconds
Started May 26 02:53:31 PM PDT 24
Finished May 26 02:53:42 PM PDT 24
Peak memory 251084 kb
Host smart-5264b97c-96cb-409b-bafe-6c66f15ea7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069815086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1069815086
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1641824837
Short name T686
Test name
Test status
Simulation time 8288397024 ps
CPU time 65.42 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 277676 kb
Host smart-a6a3e60d-bb57-47fb-a7de-d27b12747662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641824837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1641824837
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.292293344
Short name T802
Test name
Test status
Simulation time 155439702509 ps
CPU time 909.83 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 03:08:39 PM PDT 24
Peak memory 496928 kb
Host smart-73e8ab1b-8f91-4dd0-8170-15855459f72d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=292293344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.292293344
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.707623815
Short name T756
Test name
Test status
Simulation time 35863534 ps
CPU time 0.92 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:29 PM PDT 24
Peak memory 208576 kb
Host smart-1a8056a9-3a08-4f7d-92e0-b635041f3b02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707623815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.707623815
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.304219728
Short name T547
Test name
Test status
Simulation time 21616090 ps
CPU time 1.33 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 209664 kb
Host smart-e7d73d9a-82ef-4343-b916-380c39c656c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304219728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.304219728
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2489728493
Short name T680
Test name
Test status
Simulation time 1320294151 ps
CPU time 9.35 seconds
Started May 26 02:53:43 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 218252 kb
Host smart-670d89fc-fd2f-44fe-b670-822ac7675b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489728493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2489728493
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3249220019
Short name T8
Test name
Test status
Simulation time 632907940 ps
CPU time 8.04 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 209652 kb
Host smart-c0ac4212-bd66-47d6-9619-4316c8427d64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249220019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3249220019
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.673920452
Short name T522
Test name
Test status
Simulation time 3936645416 ps
CPU time 31.73 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:54:07 PM PDT 24
Peak memory 219052 kb
Host smart-8ab13883-9f24-4454-8117-68840509e74a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673920452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.673920452
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3510782047
Short name T638
Test name
Test status
Simulation time 2215812265 ps
CPU time 5.99 seconds
Started May 26 02:53:48 PM PDT 24
Finished May 26 02:53:55 PM PDT 24
Peak memory 218120 kb
Host smart-b7940ffa-0d54-4571-b77c-99ae850473ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510782047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3510782047
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3707462134
Short name T331
Test name
Test status
Simulation time 3335339076 ps
CPU time 10.86 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 214548 kb
Host smart-f856c537-6f37-4d4a-885b-0dc58dd34cf2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707462134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3707462134
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2140497747
Short name T555
Test name
Test status
Simulation time 15800719370 ps
CPU time 128.23 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:55:39 PM PDT 24
Peak memory 283132 kb
Host smart-56a99b65-c7c3-47b6-baea-15bf1f3e212f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140497747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2140497747
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2663873750
Short name T210
Test name
Test status
Simulation time 591989314 ps
CPU time 23.72 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:55 PM PDT 24
Peak memory 250968 kb
Host smart-583393c9-01ef-42c0-a4d1-2b3a7b0f1943
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663873750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2663873750
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3011611418
Short name T275
Test name
Test status
Simulation time 447338907 ps
CPU time 3.52 seconds
Started May 26 02:53:46 PM PDT 24
Finished May 26 02:53:50 PM PDT 24
Peak memory 218024 kb
Host smart-91b63a8f-eff3-4a5c-9037-b06b8fd791a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011611418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3011611418
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2660333302
Short name T567
Test name
Test status
Simulation time 621369172 ps
CPU time 14.15 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:53:50 PM PDT 24
Peak memory 217932 kb
Host smart-fb01b0ab-0318-4ef4-b277-a377a7b644cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660333302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2660333302
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2009165534
Short name T580
Test name
Test status
Simulation time 526678788 ps
CPU time 8.23 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 218056 kb
Host smart-2c4b6f3c-1d09-4028-9478-01c2fda78936
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009165534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2009165534
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3104185903
Short name T234
Test name
Test status
Simulation time 826643744 ps
CPU time 9.14 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:41 PM PDT 24
Peak memory 218060 kb
Host smart-9121436b-e6ab-4508-ba03-d0aebbc6be42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104185903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3104185903
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1025929452
Short name T18
Test name
Test status
Simulation time 363594837 ps
CPU time 8.39 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 218248 kb
Host smart-6629b46a-9fc4-4352-b141-57c51f2e7169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025929452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1025929452
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1401519590
Short name T771
Test name
Test status
Simulation time 64823741 ps
CPU time 1.32 seconds
Started May 26 02:53:31 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 213656 kb
Host smart-6e2d8c64-bb1d-44fb-8cef-998cd5e3851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401519590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1401519590
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4177633374
Short name T591
Test name
Test status
Simulation time 777533169 ps
CPU time 26.05 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:59 PM PDT 24
Peak memory 251040 kb
Host smart-1dd60e99-5d8b-444c-b603-b2e2d0e0433b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177633374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4177633374
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.4118674248
Short name T237
Test name
Test status
Simulation time 201103188 ps
CPU time 5.87 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 246504 kb
Host smart-fac2b499-8919-48b7-ada9-4a433306ce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118674248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.4118674248
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.309426536
Short name T49
Test name
Test status
Simulation time 15998940514 ps
CPU time 82.38 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:54:54 PM PDT 24
Peak memory 267436 kb
Host smart-e19c430e-a300-472a-9975-ace7484bbd18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309426536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.309426536
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3931147957
Short name T359
Test name
Test status
Simulation time 13960882 ps
CPU time 0.82 seconds
Started May 26 02:53:38 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 208500 kb
Host smart-e5f170ac-af50-4fa3-98b0-7cf10f68f4fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931147957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3931147957
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2351244646
Short name T484
Test name
Test status
Simulation time 56360978 ps
CPU time 1.07 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 209488 kb
Host smart-ae0d216b-f3d3-40d6-baeb-744f68ddc1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351244646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2351244646
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.379250058
Short name T559
Test name
Test status
Simulation time 429458480 ps
CPU time 13.69 seconds
Started May 26 02:53:30 PM PDT 24
Finished May 26 02:53:48 PM PDT 24
Peak memory 218096 kb
Host smart-81949d7d-b679-49c0-81cf-ae10d1133232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379250058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.379250058
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3953952811
Short name T741
Test name
Test status
Simulation time 13742888659 ps
CPU time 20.31 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:56 PM PDT 24
Peak memory 217716 kb
Host smart-182b9ef3-f2b7-47e0-b5d7-d3b8493595ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953952811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3953952811
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2029632963
Short name T460
Test name
Test status
Simulation time 6259699683 ps
CPU time 70.8 seconds
Started May 26 02:53:35 PM PDT 24
Finished May 26 02:54:48 PM PDT 24
Peak memory 218656 kb
Host smart-21d00f06-66b4-4986-b554-99604bbd17e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029632963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2029632963
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3200987209
Short name T239
Test name
Test status
Simulation time 1534818292 ps
CPU time 6.76 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 218060 kb
Host smart-b9bd57be-ad7f-4661-9916-6fbc0150466f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200987209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3200987209
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.969897754
Short name T412
Test name
Test status
Simulation time 3369075183 ps
CPU time 6.24 seconds
Started May 26 02:53:35 PM PDT 24
Finished May 26 02:53:44 PM PDT 24
Peak memory 214144 kb
Host smart-937130dc-1367-4b70-b6a3-b5fc089c6a22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969897754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
969897754
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2521817367
Short name T301
Test name
Test status
Simulation time 4991844527 ps
CPU time 34.9 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 267556 kb
Host smart-e1e99fe4-dd51-4eef-9b73-a4a228bf42d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521817367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2521817367
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1717598220
Short name T347
Test name
Test status
Simulation time 3302191093 ps
CPU time 28.27 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:54:01 PM PDT 24
Peak memory 250780 kb
Host smart-a0d4011b-6f04-4837-af96-cb1b4ea8c630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717598220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1717598220
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3472620372
Short name T667
Test name
Test status
Simulation time 274932039 ps
CPU time 2.99 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 218076 kb
Host smart-4b6591d0-9b16-4c65-af82-05a2c80e1122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472620372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3472620372
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3375289923
Short name T722
Test name
Test status
Simulation time 196935949 ps
CPU time 7.14 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 218036 kb
Host smart-64dee931-8e6f-41a5-96ca-5c9e76edd397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375289923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3375289923
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2921051231
Short name T340
Test name
Test status
Simulation time 415766426 ps
CPU time 8.11 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 218076 kb
Host smart-670e8fcb-e4d9-4e60-964f-7f34fd79e476
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921051231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2921051231
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2298460059
Short name T293
Test name
Test status
Simulation time 259375217 ps
CPU time 9.68 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:53:43 PM PDT 24
Peak memory 218136 kb
Host smart-b50ee63a-26a2-47c3-a73b-ee4cd399a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298460059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2298460059
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1176804474
Short name T171
Test name
Test status
Simulation time 13075361 ps
CPU time 1.01 seconds
Started May 26 02:53:31 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 211976 kb
Host smart-e382c90a-7b8b-4f3a-bc16-2a5417b30dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176804474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1176804474
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.413683381
Short name T587
Test name
Test status
Simulation time 703815333 ps
CPU time 21.09 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 246184 kb
Host smart-4cd68506-e61d-41ff-b36f-50b4d5400c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413683381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.413683381
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3180132519
Short name T417
Test name
Test status
Simulation time 299040906 ps
CPU time 7.38 seconds
Started May 26 02:53:38 PM PDT 24
Finished May 26 02:53:47 PM PDT 24
Peak memory 246528 kb
Host smart-e041f639-ee01-4395-b999-4780edc40c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180132519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3180132519
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1469564642
Short name T94
Test name
Test status
Simulation time 3635901386 ps
CPU time 122.96 seconds
Started May 26 02:53:49 PM PDT 24
Finished May 26 02:55:53 PM PDT 24
Peak memory 276700 kb
Host smart-55ad4ff3-ed0e-49e5-95d2-716a4ad57d68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469564642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1469564642
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1921537687
Short name T505
Test name
Test status
Simulation time 28442974 ps
CPU time 0.77 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 208500 kb
Host smart-da516f51-1bf6-4892-b71c-e15eedf2b9b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921537687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1921537687
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2264518901
Short name T213
Test name
Test status
Simulation time 26323446 ps
CPU time 0.98 seconds
Started May 26 02:53:45 PM PDT 24
Finished May 26 02:53:47 PM PDT 24
Peak memory 209664 kb
Host smart-21e14a7a-a303-4282-996b-9d9f90b5f90b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264518901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2264518901
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.298512442
Short name T479
Test name
Test status
Simulation time 4977378356 ps
CPU time 10.67 seconds
Started May 26 02:53:31 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 218388 kb
Host smart-7406ff43-4244-4110-93a1-db073605a39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298512442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.298512442
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.948707114
Short name T710
Test name
Test status
Simulation time 468757351 ps
CPU time 2.1 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 209636 kb
Host smart-bdbcea9c-948d-46cd-b745-a1493c944792
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948707114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.948707114
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.857191009
Short name T592
Test name
Test status
Simulation time 6946577954 ps
CPU time 28.52 seconds
Started May 26 02:53:38 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 218144 kb
Host smart-0ea26e43-0a56-4b2e-9efa-4f43d49b98e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857191009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.857191009
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2017188110
Short name T285
Test name
Test status
Simulation time 310818234 ps
CPU time 5.68 seconds
Started May 26 02:53:31 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 218096 kb
Host smart-f8de4110-c43a-449f-983a-e559c0bc741e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017188110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2017188110
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1822855517
Short name T784
Test name
Test status
Simulation time 120844040 ps
CPU time 2.69 seconds
Started May 26 02:53:48 PM PDT 24
Finished May 26 02:53:52 PM PDT 24
Peak memory 213212 kb
Host smart-da4faf54-ef55-4f17-89bd-5d556695a375
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822855517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1822855517
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2822927550
Short name T474
Test name
Test status
Simulation time 21763641600 ps
CPU time 95.13 seconds
Started May 26 02:53:32 PM PDT 24
Finished May 26 02:55:11 PM PDT 24
Peak memory 278888 kb
Host smart-170228f8-4c14-4b1b-9348-33a198b891c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822927550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2822927550
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2357283600
Short name T836
Test name
Test status
Simulation time 398613481 ps
CPU time 8.95 seconds
Started May 26 02:53:44 PM PDT 24
Finished May 26 02:53:54 PM PDT 24
Peak memory 223132 kb
Host smart-1d3a8f1c-d999-424a-bbb4-c210cebfa9c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357283600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2357283600
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3047845472
Short name T511
Test name
Test status
Simulation time 242652305 ps
CPU time 3.11 seconds
Started May 26 02:53:28 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 218184 kb
Host smart-ed8dfa48-b154-4f03-8206-21ec45520676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047845472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3047845472
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3940223708
Short name T865
Test name
Test status
Simulation time 517476390 ps
CPU time 16.41 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:48 PM PDT 24
Peak memory 226124 kb
Host smart-7d9fb0f3-6082-46d8-9f03-0b14baef2972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940223708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3940223708
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2754710445
Short name T712
Test name
Test status
Simulation time 276499440 ps
CPU time 9.16 seconds
Started May 26 02:53:34 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 218052 kb
Host smart-553901ab-608e-47fd-80c7-eea61011a944
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754710445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2754710445
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2156450672
Short name T163
Test name
Test status
Simulation time 585877990 ps
CPU time 16.2 seconds
Started May 26 02:53:38 PM PDT 24
Finished May 26 02:53:55 PM PDT 24
Peak memory 218024 kb
Host smart-379974c3-8e8b-4044-ae13-0faf421e4680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156450672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2156450672
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1616053047
Short name T245
Test name
Test status
Simulation time 378724105 ps
CPU time 12.33 seconds
Started May 26 02:53:29 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 218228 kb
Host smart-ff2ff207-705d-4da7-95ea-8dd1ee6d5dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616053047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1616053047
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.376206627
Short name T244
Test name
Test status
Simulation time 206102938 ps
CPU time 3.64 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 218176 kb
Host smart-6d878be0-26f4-43ff-968f-218016699490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376206627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.376206627
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3506018595
Short name T354
Test name
Test status
Simulation time 337066362 ps
CPU time 31.53 seconds
Started May 26 02:53:27 PM PDT 24
Finished May 26 02:54:02 PM PDT 24
Peak memory 251048 kb
Host smart-feab302d-5c53-47f2-ad4f-7dabe28838c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506018595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3506018595
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.935166731
Short name T818
Test name
Test status
Simulation time 212794715 ps
CPU time 7.12 seconds
Started May 26 02:53:36 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 246560 kb
Host smart-b401e7ce-de25-4919-945d-d149da6ba6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935166731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.935166731
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.725047858
Short name T566
Test name
Test status
Simulation time 1848339549 ps
CPU time 34.8 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 226208 kb
Host smart-0b70e930-96d3-46c5-b5c3-59f92a8b2e0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725047858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.725047858
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4050193107
Short name T43
Test name
Test status
Simulation time 40794898 ps
CPU time 0.76 seconds
Started May 26 02:53:38 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 208672 kb
Host smart-bc7cd832-9740-40c7-9622-74f30e654657
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050193107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4050193107
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.562576499
Short name T648
Test name
Test status
Simulation time 31121442 ps
CPU time 0.94 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:02 PM PDT 24
Peak memory 209628 kb
Host smart-08b2d620-d0e7-46c4-b293-7b1acb4c7870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562576499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.562576499
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1009256232
Short name T292
Test name
Test status
Simulation time 2283489628 ps
CPU time 18.79 seconds
Started May 26 02:53:33 PM PDT 24
Finished May 26 02:53:55 PM PDT 24
Peak memory 218164 kb
Host smart-2105a582-d8a0-40ec-ba95-6338c7e5f7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009256232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1009256232
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3144863507
Short name T27
Test name
Test status
Simulation time 668835163 ps
CPU time 7.32 seconds
Started May 26 02:53:52 PM PDT 24
Finished May 26 02:54:01 PM PDT 24
Peak memory 217120 kb
Host smart-ce6dac11-9c3b-4cb5-9e0b-996600b5b6e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144863507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3144863507
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3367141150
Short name T824
Test name
Test status
Simulation time 5641067792 ps
CPU time 33.09 seconds
Started May 26 02:53:51 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 218144 kb
Host smart-f499b7c5-af81-4776-8c4e-4936e373f20c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367141150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3367141150
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.275881240
Short name T600
Test name
Test status
Simulation time 3539010568 ps
CPU time 19.36 seconds
Started May 26 02:53:35 PM PDT 24
Finished May 26 02:53:57 PM PDT 24
Peak memory 218112 kb
Host smart-c8975e2b-b8a3-46fc-a17e-b8d07b2f1a86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275881240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.275881240
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1794031839
Short name T563
Test name
Test status
Simulation time 448639715 ps
CPU time 6.85 seconds
Started May 26 02:53:45 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 213652 kb
Host smart-8909cbfa-b2f5-4f65-bc48-f80ffec7d908
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794031839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1794031839
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.75273983
Short name T606
Test name
Test status
Simulation time 1972220169 ps
CPU time 43.79 seconds
Started May 26 02:53:45 PM PDT 24
Finished May 26 02:54:29 PM PDT 24
Peak memory 267372 kb
Host smart-56ea2c5d-dec2-4f56-9414-ce5c20efa38f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75273983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_state_failure.75273983
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.443624669
Short name T391
Test name
Test status
Simulation time 564476101 ps
CPU time 18.1 seconds
Started May 26 02:53:36 PM PDT 24
Finished May 26 02:53:57 PM PDT 24
Peak memory 218052 kb
Host smart-5dc8b18c-fdfe-4302-990a-7c1fb288ec55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443624669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.443624669
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.377067567
Short name T446
Test name
Test status
Simulation time 84328997 ps
CPU time 2.27 seconds
Started May 26 02:53:36 PM PDT 24
Finished May 26 02:53:40 PM PDT 24
Peak memory 218320 kb
Host smart-1856715c-b445-44e9-84cc-757f6f2f7a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377067567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.377067567
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1122574560
Short name T515
Test name
Test status
Simulation time 356587844 ps
CPU time 12.08 seconds
Started May 26 02:53:38 PM PDT 24
Finished May 26 02:53:52 PM PDT 24
Peak memory 218548 kb
Host smart-6d4fdd3c-06de-4856-9c2e-74c6b25317fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122574560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1122574560
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1668530749
Short name T295
Test name
Test status
Simulation time 610748599 ps
CPU time 11.26 seconds
Started May 26 02:53:33 PM PDT 24
Finished May 26 02:53:48 PM PDT 24
Peak memory 218040 kb
Host smart-45c41e15-27f3-4580-a1ef-e13d9401f7f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668530749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1668530749
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2522239894
Short name T689
Test name
Test status
Simulation time 443723977 ps
CPU time 5.81 seconds
Started May 26 02:53:41 PM PDT 24
Finished May 26 02:53:47 PM PDT 24
Peak memory 218076 kb
Host smart-b7157900-16a3-485f-97a7-a4f594988cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522239894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2522239894
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.283998480
Short name T500
Test name
Test status
Simulation time 5190191005 ps
CPU time 7.97 seconds
Started May 26 02:53:36 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 217608 kb
Host smart-9f276190-7aa9-4d75-9b25-48f4c1bc4314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283998480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.283998480
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1901443559
Short name T875
Test name
Test status
Simulation time 18330080 ps
CPU time 1.53 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:53:58 PM PDT 24
Peak memory 217952 kb
Host smart-ac54679e-a537-4d1a-8bb4-63e3540769fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901443559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1901443559
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2215711576
Short name T508
Test name
Test status
Simulation time 2415659422 ps
CPU time 32.25 seconds
Started May 26 02:53:34 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 251100 kb
Host smart-043370bf-3f61-4caa-8e37-f57fb7f8d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215711576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2215711576
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2655228894
Short name T578
Test name
Test status
Simulation time 113119348 ps
CPU time 7.85 seconds
Started May 26 02:53:48 PM PDT 24
Finished May 26 02:53:56 PM PDT 24
Peak memory 251052 kb
Host smart-569f089b-9b00-4752-92be-4aa0644b61b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655228894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2655228894
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.264090900
Short name T660
Test name
Test status
Simulation time 12335122757 ps
CPU time 203.31 seconds
Started May 26 02:53:33 PM PDT 24
Finished May 26 02:56:59 PM PDT 24
Peak memory 227112 kb
Host smart-b4910615-1e34-47f0-be64-c2db654cce62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264090900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.264090900
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3181370946
Short name T298
Test name
Test status
Simulation time 45375737 ps
CPU time 1.15 seconds
Started May 26 02:53:33 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 212660 kb
Host smart-fe034925-2154-41b3-9384-935d612c0b21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181370946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3181370946
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1277719111
Short name T12
Test name
Test status
Simulation time 36459158 ps
CPU time 0.94 seconds
Started May 26 02:53:00 PM PDT 24
Finished May 26 02:53:02 PM PDT 24
Peak memory 209676 kb
Host smart-39c9c1d2-819c-46f6-ba88-ad847bcb2d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277719111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1277719111
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1632057969
Short name T442
Test name
Test status
Simulation time 747358145 ps
CPU time 11.84 seconds
Started May 26 02:53:02 PM PDT 24
Finished May 26 02:53:15 PM PDT 24
Peak memory 218112 kb
Host smart-8ea541ec-dd11-4b14-b243-52e4e250f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632057969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1632057969
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.711197326
Short name T557
Test name
Test status
Simulation time 974648948 ps
CPU time 11.87 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:52:57 PM PDT 24
Peak memory 217064 kb
Host smart-cdf9d73e-4d05-405b-afed-d6f854777752
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711197326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.711197326
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1041558854
Short name T803
Test name
Test status
Simulation time 2900185426 ps
CPU time 55.21 seconds
Started May 26 02:52:44 PM PDT 24
Finished May 26 02:53:41 PM PDT 24
Peak memory 217924 kb
Host smart-b12bdd1b-7afb-463e-9105-411e66629e93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041558854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1041558854
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.323044786
Short name T822
Test name
Test status
Simulation time 238683367 ps
CPU time 3.73 seconds
Started May 26 02:52:56 PM PDT 24
Finished May 26 02:53:00 PM PDT 24
Peak memory 217888 kb
Host smart-07dc0c47-5fea-415c-b2c4-528613a1ed02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323044786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.323044786
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.405488220
Short name T674
Test name
Test status
Simulation time 1635986245 ps
CPU time 6.25 seconds
Started May 26 02:52:57 PM PDT 24
Finished May 26 02:53:05 PM PDT 24
Peak memory 218056 kb
Host smart-5957d296-1f8e-482e-b8ec-a970d9c97fbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405488220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.405488220
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1525770381
Short name T553
Test name
Test status
Simulation time 896240307 ps
CPU time 20.76 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:34 PM PDT 24
Peak memory 213240 kb
Host smart-1733158f-6437-4efd-82b1-0075ed3f0353
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525770381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1525770381
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2330857856
Short name T82
Test name
Test status
Simulation time 1281487830 ps
CPU time 3.81 seconds
Started May 26 02:52:45 PM PDT 24
Finished May 26 02:52:50 PM PDT 24
Peak memory 213300 kb
Host smart-fa2d7954-fe58-430f-8982-4c3d8e969f09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330857856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2330857856
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3387898644
Short name T241
Test name
Test status
Simulation time 3951678395 ps
CPU time 98.23 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:54:21 PM PDT 24
Peak memory 282980 kb
Host smart-b64854ed-1fe8-4386-a660-5dfa96f750c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387898644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3387898644
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1822505424
Short name T696
Test name
Test status
Simulation time 352521933 ps
CPU time 17.07 seconds
Started May 26 02:52:44 PM PDT 24
Finished May 26 02:53:03 PM PDT 24
Peak memory 250692 kb
Host smart-94bc865f-90ac-40f4-a82b-eb47fbadc9a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822505424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1822505424
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2844931079
Short name T509
Test name
Test status
Simulation time 47414067 ps
CPU time 1.91 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 218116 kb
Host smart-13f74304-bde0-45bd-98fe-0af48efe25ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844931079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2844931079
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.505821610
Short name T183
Test name
Test status
Simulation time 322289957 ps
CPU time 7.88 seconds
Started May 26 02:53:11 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 217932 kb
Host smart-091a0cc7-34b4-49a5-9085-ca4af69ffcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505821610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.505821610
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3192739573
Short name T89
Test name
Test status
Simulation time 567984029 ps
CPU time 23.96 seconds
Started May 26 02:52:59 PM PDT 24
Finished May 26 02:53:25 PM PDT 24
Peak memory 268392 kb
Host smart-1532f8f4-d401-4b99-9daf-62e41d033529
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192739573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3192739573
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2074458276
Short name T627
Test name
Test status
Simulation time 3652908661 ps
CPU time 11.73 seconds
Started May 26 02:52:41 PM PDT 24
Finished May 26 02:52:55 PM PDT 24
Peak memory 226288 kb
Host smart-881f0deb-3b7c-4343-81c0-d74aaef2cd13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074458276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2074458276
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.62161303
Short name T400
Test name
Test status
Simulation time 1575133750 ps
CPU time 22.17 seconds
Started May 26 02:52:59 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 218044 kb
Host smart-92b89be7-8497-4f31-bc51-068e540255d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62161303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dige
st.62161303
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3697940515
Short name T146
Test name
Test status
Simulation time 764845344 ps
CPU time 5.57 seconds
Started May 26 02:52:51 PM PDT 24
Finished May 26 02:52:57 PM PDT 24
Peak memory 218064 kb
Host smart-522426e7-fefe-4895-afed-3123a612853b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697940515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
697940515
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.824916612
Short name T360
Test name
Test status
Simulation time 1345468209 ps
CPU time 8.62 seconds
Started May 26 02:53:11 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 218240 kb
Host smart-a096f09e-3da5-4fb4-b391-5e8e1159a97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824916612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.824916612
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2911873237
Short name T731
Test name
Test status
Simulation time 19404414 ps
CPU time 1.05 seconds
Started May 26 02:52:45 PM PDT 24
Finished May 26 02:52:47 PM PDT 24
Peak memory 212844 kb
Host smart-67c854ea-15e0-4dd0-860a-a4126d05a7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911873237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2911873237
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1714494939
Short name T872
Test name
Test status
Simulation time 299648346 ps
CPU time 31.43 seconds
Started May 26 02:52:38 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 251052 kb
Host smart-4572924e-ac0d-4070-b056-584c38572cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714494939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1714494939
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1013150269
Short name T672
Test name
Test status
Simulation time 753661345 ps
CPU time 6.35 seconds
Started May 26 02:52:43 PM PDT 24
Finished May 26 02:52:52 PM PDT 24
Peak memory 246392 kb
Host smart-71aa4d88-d086-4cdb-a0dc-f698f714fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013150269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1013150269
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.4043832970
Short name T801
Test name
Test status
Simulation time 19060637523 ps
CPU time 136.24 seconds
Started May 26 02:53:03 PM PDT 24
Finished May 26 02:55:22 PM PDT 24
Peak memory 251084 kb
Host smart-dd628558-3d45-4412-a834-4592447162bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043832970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.4043832970
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2040153097
Short name T769
Test name
Test status
Simulation time 14431902 ps
CPU time 0.84 seconds
Started May 26 02:52:40 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 208612 kb
Host smart-829726e7-3880-4ed0-ba1c-93afd1f8cef2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040153097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2040153097
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4059725116
Short name T303
Test name
Test status
Simulation time 23899537 ps
CPU time 1 seconds
Started May 26 02:53:51 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 209736 kb
Host smart-f4ed5c08-eed3-4735-9dea-2f3178ae4c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059725116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4059725116
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1432588590
Short name T773
Test name
Test status
Simulation time 636800345 ps
CPU time 13.94 seconds
Started May 26 02:53:52 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 218120 kb
Host smart-152b3f9e-43e4-486c-b3f0-1d921dd67039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432588590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1432588590
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.5942435
Short name T160
Test name
Test status
Simulation time 537713575 ps
CPU time 1.18 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:53:59 PM PDT 24
Peak memory 209724 kb
Host smart-2839d011-19a5-4dc1-89c5-f0b1b5c747ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5942435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.5942435
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1158076675
Short name T507
Test name
Test status
Simulation time 104860674 ps
CPU time 3.16 seconds
Started May 26 02:53:50 PM PDT 24
Finished May 26 02:53:54 PM PDT 24
Peak memory 218136 kb
Host smart-578f2238-53f8-438a-b660-83bc4bae96da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158076675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1158076675
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3885266293
Short name T435
Test name
Test status
Simulation time 406310371 ps
CPU time 13.26 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:54:11 PM PDT 24
Peak memory 226176 kb
Host smart-b6559fbd-38cb-470e-b336-20609ce9a945
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885266293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3885266293
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.4052883403
Short name T655
Test name
Test status
Simulation time 323095575 ps
CPU time 12.63 seconds
Started May 26 02:53:50 PM PDT 24
Finished May 26 02:54:04 PM PDT 24
Peak memory 218040 kb
Host smart-b31caa01-33ec-462d-a498-da7be3c11388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052883403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.4052883403
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1749460679
Short name T376
Test name
Test status
Simulation time 476777192 ps
CPU time 12.15 seconds
Started May 26 02:53:56 PM PDT 24
Finished May 26 02:54:11 PM PDT 24
Peak memory 218068 kb
Host smart-771f26a1-103b-4471-8a4d-7cc057ff66b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749460679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1749460679
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3386583324
Short name T852
Test name
Test status
Simulation time 875888598 ps
CPU time 11.96 seconds
Started May 26 02:53:57 PM PDT 24
Finished May 26 02:54:11 PM PDT 24
Peak memory 218188 kb
Host smart-973af5ac-70e9-4715-b663-9fd8436f3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386583324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3386583324
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.534184255
Short name T397
Test name
Test status
Simulation time 98014422 ps
CPU time 2.89 seconds
Started May 26 02:53:46 PM PDT 24
Finished May 26 02:53:50 PM PDT 24
Peak memory 214124 kb
Host smart-b5519b1f-aa59-4d25-bf0c-ba003bf708b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534184255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.534184255
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.470595937
Short name T501
Test name
Test status
Simulation time 180481121 ps
CPU time 22.66 seconds
Started May 26 02:53:56 PM PDT 24
Finished May 26 02:54:21 PM PDT 24
Peak memory 245808 kb
Host smart-9ddc4989-6239-4279-a0e6-d97b20c33ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470595937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.470595937
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1852744503
Short name T582
Test name
Test status
Simulation time 84593846 ps
CPU time 7.54 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:54:03 PM PDT 24
Peak memory 251040 kb
Host smart-0c78e243-5ba9-4993-9955-555f87eb6b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852744503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1852744503
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4195032341
Short name T418
Test name
Test status
Simulation time 2057700862 ps
CPU time 88.22 seconds
Started May 26 02:53:51 PM PDT 24
Finished May 26 02:55:21 PM PDT 24
Peak memory 274364 kb
Host smart-33965233-3751-4a6c-b419-63a26746826c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195032341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4195032341
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.953546803
Short name T720
Test name
Test status
Simulation time 41993972 ps
CPU time 0.89 seconds
Started May 26 02:53:51 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 208908 kb
Host smart-a96a56c7-2654-4c28-b68c-8454e1eafe73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953546803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.953546803
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2298205169
Short name T789
Test name
Test status
Simulation time 25980724 ps
CPU time 1.09 seconds
Started May 26 02:53:56 PM PDT 24
Finished May 26 02:54:00 PM PDT 24
Peak memory 209732 kb
Host smart-662e8194-0a78-4c22-9483-6124337e4005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298205169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2298205169
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2422380075
Short name T527
Test name
Test status
Simulation time 1083197726 ps
CPU time 12.17 seconds
Started May 26 02:53:57 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 218152 kb
Host smart-d98f9e45-cc59-4d9e-be1d-dbdeac82ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422380075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2422380075
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1603774703
Short name T761
Test name
Test status
Simulation time 173804938 ps
CPU time 1.54 seconds
Started May 26 02:53:44 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 209624 kb
Host smart-0054c167-5e7a-45d7-870c-1644d0d34ebf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603774703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1603774703
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3085038739
Short name T401
Test name
Test status
Simulation time 55742092 ps
CPU time 1.58 seconds
Started May 26 02:53:50 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 218184 kb
Host smart-59495702-2ac0-47f5-9446-aec79dd5de16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085038739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3085038739
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3970272749
Short name T279
Test name
Test status
Simulation time 390685192 ps
CPU time 14.23 seconds
Started May 26 02:53:53 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 218952 kb
Host smart-e5392a36-ff4b-4926-a025-b47adffadb6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970272749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3970272749
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2377368022
Short name T169
Test name
Test status
Simulation time 513544749 ps
CPU time 11.05 seconds
Started May 26 02:53:53 PM PDT 24
Finished May 26 02:54:06 PM PDT 24
Peak memory 218060 kb
Host smart-bb07042b-e310-42e4-a798-6b851bb3c53c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377368022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2377368022
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.427498171
Short name T263
Test name
Test status
Simulation time 3349459170 ps
CPU time 13.28 seconds
Started May 26 02:53:53 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 218132 kb
Host smart-701747ca-80fe-471f-b8eb-a1eef642706d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427498171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.427498171
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1713174002
Short name T407
Test name
Test status
Simulation time 3694763958 ps
CPU time 6.69 seconds
Started May 26 02:53:52 PM PDT 24
Finished May 26 02:54:00 PM PDT 24
Peak memory 218232 kb
Host smart-25e2b452-23c1-4819-99b7-25986cbb1dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713174002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1713174002
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2330738855
Short name T77
Test name
Test status
Simulation time 30110123 ps
CPU time 2.26 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:54:00 PM PDT 24
Peak memory 213864 kb
Host smart-4fc6b80e-9838-4046-ad9f-1c22810c5f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330738855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2330738855
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.366127666
Short name T315
Test name
Test status
Simulation time 595041512 ps
CPU time 30.2 seconds
Started May 26 02:53:52 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 249756 kb
Host smart-6ae93042-6479-4d90-8fc7-2e0e67627279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366127666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.366127666
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3480657282
Short name T362
Test name
Test status
Simulation time 726209437 ps
CPU time 3.4 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:54:00 PM PDT 24
Peak memory 222188 kb
Host smart-ae0fdbbe-1ed2-41e3-80b5-b896a50130d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480657282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3480657282
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3885376379
Short name T475
Test name
Test status
Simulation time 5043055365 ps
CPU time 86.47 seconds
Started May 26 02:53:46 PM PDT 24
Finished May 26 02:55:14 PM PDT 24
Peak memory 283612 kb
Host smart-f161cca7-789c-4fba-8529-2afe0c254eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885376379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3885376379
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4174651451
Short name T437
Test name
Test status
Simulation time 16386762 ps
CPU time 1.22 seconds
Started May 26 02:53:52 PM PDT 24
Finished May 26 02:53:55 PM PDT 24
Peak memory 211708 kb
Host smart-0b579013-d249-4dfd-8876-f4fcb5a9cd5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174651451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4174651451
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3328217428
Short name T586
Test name
Test status
Simulation time 85026955 ps
CPU time 1.33 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:02 PM PDT 24
Peak memory 209596 kb
Host smart-9ae640b1-1e1a-4880-8f2a-8131e4a3d642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328217428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3328217428
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2185363785
Short name T305
Test name
Test status
Simulation time 520941697 ps
CPU time 17.11 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:54:13 PM PDT 24
Peak memory 218100 kb
Host smart-37e165c0-c332-4c35-9eec-9d0a577d2170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185363785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2185363785
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2745729137
Short name T577
Test name
Test status
Simulation time 828110646 ps
CPU time 7.99 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:54:05 PM PDT 24
Peak memory 209592 kb
Host smart-1ed8bb6a-4c65-4d3a-bc5f-02f4e700ced4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745729137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2745729137
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1059624137
Short name T593
Test name
Test status
Simulation time 42354455 ps
CPU time 2.43 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:04 PM PDT 24
Peak memory 218104 kb
Host smart-bbb9a664-5efc-48d4-8ce9-07b10109abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059624137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1059624137
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3852149297
Short name T372
Test name
Test status
Simulation time 1253630952 ps
CPU time 15.04 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:22 PM PDT 24
Peak memory 226176 kb
Host smart-180a6190-7787-40d0-9048-bc3dacef3e8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852149297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3852149297
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3343668586
Short name T64
Test name
Test status
Simulation time 584034316 ps
CPU time 8.12 seconds
Started May 26 02:53:59 PM PDT 24
Finished May 26 02:54:10 PM PDT 24
Peak memory 218036 kb
Host smart-8a58d1f9-708a-43a0-9abf-145960ca1094
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343668586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3343668586
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3290978485
Short name T262
Test name
Test status
Simulation time 1281206470 ps
CPU time 8.87 seconds
Started May 26 02:53:52 PM PDT 24
Finished May 26 02:54:02 PM PDT 24
Peak memory 218068 kb
Host smart-60eaf9dd-4b4e-4541-829e-9fd366d3bbb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290978485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3290978485
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3404839478
Short name T148
Test name
Test status
Simulation time 381307523 ps
CPU time 13.65 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 218244 kb
Host smart-dc5a5697-8698-489a-ae6a-68757b76e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404839478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3404839478
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1229592183
Short name T80
Test name
Test status
Simulation time 28818487 ps
CPU time 1.36 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:53:58 PM PDT 24
Peak memory 213544 kb
Host smart-fbdccc7e-979c-4ae8-a94b-b3fdcd146530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229592183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1229592183
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.792156131
Short name T222
Test name
Test status
Simulation time 205466213 ps
CPU time 19.76 seconds
Started May 26 02:53:56 PM PDT 24
Finished May 26 02:54:19 PM PDT 24
Peak memory 251084 kb
Host smart-f0a3a4f4-f1a8-4f35-b55b-c474d3ad889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792156131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.792156131
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3532976433
Short name T795
Test name
Test status
Simulation time 466711505 ps
CPU time 6.99 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:07 PM PDT 24
Peak memory 246620 kb
Host smart-d14d38df-aa4e-4069-85cc-3c0199a7f628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532976433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3532976433
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2733371706
Short name T88
Test name
Test status
Simulation time 1526501175 ps
CPU time 66.26 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:55:12 PM PDT 24
Peak memory 273252 kb
Host smart-b887e612-5976-4097-93d4-3b0a114b67e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733371706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2733371706
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2523113810
Short name T242
Test name
Test status
Simulation time 16411624 ps
CPU time 1.2 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:53:58 PM PDT 24
Peak memory 211632 kb
Host smart-b7d55296-c5dc-4480-b1a9-6f44442f1274
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523113810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2523113810
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3484984337
Short name T753
Test name
Test status
Simulation time 14491576 ps
CPU time 0.82 seconds
Started May 26 02:54:01 PM PDT 24
Finished May 26 02:54:05 PM PDT 24
Peak memory 209628 kb
Host smart-3f6a0926-4acb-4b82-b50c-47563592a8f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484984337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3484984337
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2489090062
Short name T601
Test name
Test status
Simulation time 1349953880 ps
CPU time 15.5 seconds
Started May 26 02:53:59 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 218136 kb
Host smart-39bb5480-8594-467e-8583-ad558a8268a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489090062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2489090062
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1205117308
Short name T361
Test name
Test status
Simulation time 1074393688 ps
CPU time 4.74 seconds
Started May 26 02:53:59 PM PDT 24
Finished May 26 02:54:07 PM PDT 24
Peak memory 209604 kb
Host smart-5d6374cf-30a0-41f7-90ef-f9a4c87f3680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205117308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1205117308
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3995414958
Short name T823
Test name
Test status
Simulation time 98386162 ps
CPU time 2.9 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:04 PM PDT 24
Peak memory 218112 kb
Host smart-af384239-4416-45b5-b620-750bbdf5894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995414958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3995414958
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.344737051
Short name T706
Test name
Test status
Simulation time 1349696534 ps
CPU time 14.02 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:21 PM PDT 24
Peak memory 219068 kb
Host smart-0a770154-782d-4e0f-b7b0-67f1754909e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344737051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.344737051
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2830566018
Short name T595
Test name
Test status
Simulation time 1731829938 ps
CPU time 16.32 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:54:14 PM PDT 24
Peak memory 218016 kb
Host smart-23aec72e-40e8-4406-84c8-5167ad6362c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830566018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2830566018
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.843444591
Short name T718
Test name
Test status
Simulation time 1288751256 ps
CPU time 12.39 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:54:10 PM PDT 24
Peak memory 218136 kb
Host smart-5cdfec55-0811-4bd5-ac24-54b7610b0d44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843444591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.843444591
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1985403693
Short name T596
Test name
Test status
Simulation time 341780358 ps
CPU time 13.79 seconds
Started May 26 02:53:56 PM PDT 24
Finished May 26 02:54:13 PM PDT 24
Peak memory 218192 kb
Host smart-d608153d-7807-43f4-a3a1-39e064dcc987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985403693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1985403693
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3022048573
Short name T373
Test name
Test status
Simulation time 67712187 ps
CPU time 3.51 seconds
Started May 26 02:54:00 PM PDT 24
Finished May 26 02:54:07 PM PDT 24
Peak memory 217828 kb
Host smart-d4e82cf9-f80e-48b2-acd2-611434edd05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022048573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3022048573
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.721958566
Short name T635
Test name
Test status
Simulation time 738978597 ps
CPU time 33.16 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:34 PM PDT 24
Peak memory 251128 kb
Host smart-39ab666d-9692-413d-9105-e96734570695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721958566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.721958566
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1985349174
Short name T336
Test name
Test status
Simulation time 155568562 ps
CPU time 7.11 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 250628 kb
Host smart-7b0f972e-01a3-4322-8135-a1fe935c3423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985349174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1985349174
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3772086206
Short name T392
Test name
Test status
Simulation time 21740490053 ps
CPU time 672.38 seconds
Started May 26 02:54:00 PM PDT 24
Finished May 26 03:05:16 PM PDT 24
Peak memory 277056 kb
Host smart-0c9c9ea2-9258-4c93-87c0-f32eff9385a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772086206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3772086206
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.952799323
Short name T707
Test name
Test status
Simulation time 96582097743 ps
CPU time 646.67 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 03:04:48 PM PDT 24
Peak memory 438516 kb
Host smart-c397fcd1-ab24-4d54-803f-a34a43f3fe49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=952799323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.952799323
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.379034018
Short name T286
Test name
Test status
Simulation time 13711997 ps
CPU time 1.12 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:07 PM PDT 24
Peak memory 211732 kb
Host smart-4a5c0c51-7b21-475d-a018-a1b3b5b01da4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379034018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.379034018
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.835890554
Short name T839
Test name
Test status
Simulation time 31589015 ps
CPU time 1.16 seconds
Started May 26 02:53:57 PM PDT 24
Finished May 26 02:54:01 PM PDT 24
Peak memory 209648 kb
Host smart-eabcbb45-cb5a-4ca7-bd73-b3da5b87b1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835890554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.835890554
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3890462057
Short name T159
Test name
Test status
Simulation time 1720077264 ps
CPU time 13.25 seconds
Started May 26 02:53:59 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 218244 kb
Host smart-fbe5d44c-293b-4180-ae0d-85a814c0c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890462057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3890462057
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2040719885
Short name T30
Test name
Test status
Simulation time 1241660961 ps
CPU time 8.08 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:54:05 PM PDT 24
Peak memory 217060 kb
Host smart-3c80251a-b2dd-435f-8245-0b74f00d2ea8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040719885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2040719885
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.21043822
Short name T659
Test name
Test status
Simulation time 73223657 ps
CPU time 1.59 seconds
Started May 26 02:53:53 PM PDT 24
Finished May 26 02:53:56 PM PDT 24
Peak memory 218116 kb
Host smart-9303f28d-3a23-4dca-8085-18148f8dabe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21043822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.21043822
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2006374820
Short name T760
Test name
Test status
Simulation time 713540204 ps
CPU time 9.78 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:54:06 PM PDT 24
Peak memory 218124 kb
Host smart-500ac039-ba4a-4a72-8374-0604348c9195
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006374820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2006374820
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1583424419
Short name T270
Test name
Test status
Simulation time 979015315 ps
CPU time 11.9 seconds
Started May 26 02:53:59 PM PDT 24
Finished May 26 02:54:14 PM PDT 24
Peak memory 218064 kb
Host smart-44b78289-53bc-4416-a54d-c6b05bd39fe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583424419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1583424419
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3589603795
Short name T636
Test name
Test status
Simulation time 297317422 ps
CPU time 9.03 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:54:05 PM PDT 24
Peak memory 218104 kb
Host smart-d96300fd-bc8b-4062-8dd8-1b7161565863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589603795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3589603795
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3568672535
Short name T496
Test name
Test status
Simulation time 3990743813 ps
CPU time 30.98 seconds
Started May 26 02:53:53 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 251084 kb
Host smart-d7c79c41-7f49-428f-9cba-9b3be6ae1b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568672535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3568672535
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1457200561
Short name T469
Test name
Test status
Simulation time 413716072 ps
CPU time 10.4 seconds
Started May 26 02:54:02 PM PDT 24
Finished May 26 02:54:15 PM PDT 24
Peak memory 250948 kb
Host smart-fdfcd5f7-6cb4-48cc-a6b3-992d81ddde00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457200561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1457200561
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.28047688
Short name T182
Test name
Test status
Simulation time 7024590397 ps
CPU time 228.98 seconds
Started May 26 02:53:57 PM PDT 24
Finished May 26 02:57:49 PM PDT 24
Peak memory 250964 kb
Host smart-65174c0f-4758-4d9d-91ed-43632eda589a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28047688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.lc_ctrl_stress_all.28047688
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.700367227
Short name T665
Test name
Test status
Simulation time 81480490 ps
CPU time 1.1 seconds
Started May 26 02:53:54 PM PDT 24
Finished May 26 02:53:57 PM PDT 24
Peak memory 212696 kb
Host smart-63a24a4f-f53b-4b62-8229-ac1346366fe4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700367227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.700367227
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.4255083629
Short name T212
Test name
Test status
Simulation time 39844559 ps
CPU time 0.99 seconds
Started May 26 02:54:01 PM PDT 24
Finished May 26 02:54:05 PM PDT 24
Peak memory 209700 kb
Host smart-e4acc80d-0aa0-4137-8b53-ec83747606a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255083629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.4255083629
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3750344703
Short name T220
Test name
Test status
Simulation time 341668039 ps
CPU time 11.54 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 218124 kb
Host smart-1d39b813-f19b-42ec-a72f-275f11591b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750344703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3750344703
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3055543681
Short name T581
Test name
Test status
Simulation time 1529624724 ps
CPU time 4.3 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:06 PM PDT 24
Peak memory 209640 kb
Host smart-0240a9c2-8701-46fa-b325-611c8af5c512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055543681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3055543681
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.949595325
Short name T477
Test name
Test status
Simulation time 214018748 ps
CPU time 2.73 seconds
Started May 26 02:54:00 PM PDT 24
Finished May 26 02:54:06 PM PDT 24
Peak memory 218192 kb
Host smart-1fa5b332-58ad-4831-8173-0df89dc42557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949595325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.949595325
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2449711922
Short name T685
Test name
Test status
Simulation time 1511517809 ps
CPU time 10.41 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 219068 kb
Host smart-8924dd5c-0eb0-41ff-98b3-050a3f30e173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449711922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2449711922
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.196733714
Short name T590
Test name
Test status
Simulation time 884313192 ps
CPU time 17.68 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:19 PM PDT 24
Peak memory 218180 kb
Host smart-9682f51e-6a36-486b-b07b-7bf0880f7540
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196733714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.196733714
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1912222679
Short name T342
Test name
Test status
Simulation time 754157126 ps
CPU time 7.98 seconds
Started May 26 02:53:57 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 218140 kb
Host smart-9be1341b-9389-4a69-b657-2d1686fa157a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912222679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1912222679
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1092104672
Short name T149
Test name
Test status
Simulation time 270642765 ps
CPU time 9.91 seconds
Started May 26 02:54:02 PM PDT 24
Finished May 26 02:54:15 PM PDT 24
Peak memory 218152 kb
Host smart-ac41a0d0-b5e7-4397-b62e-94be05690301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092104672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1092104672
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2721274557
Short name T598
Test name
Test status
Simulation time 26102288 ps
CPU time 1.45 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:03 PM PDT 24
Peak memory 213528 kb
Host smart-313a6d24-81fa-4860-bf90-170d4c7232d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721274557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2721274557
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3191497229
Short name T847
Test name
Test status
Simulation time 919079345 ps
CPU time 24.38 seconds
Started May 26 02:54:01 PM PDT 24
Finished May 26 02:54:28 PM PDT 24
Peak memory 250952 kb
Host smart-f96f8eab-3fda-4a32-9368-a22bb7bffcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191497229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3191497229
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.4179165534
Short name T264
Test name
Test status
Simulation time 321809570 ps
CPU time 6.34 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:13 PM PDT 24
Peak memory 247060 kb
Host smart-acd5c8a3-b388-4bc3-91f7-b75418d053e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179165534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.4179165534
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3139115205
Short name T424
Test name
Test status
Simulation time 98365701163 ps
CPU time 171.21 seconds
Started May 26 02:54:00 PM PDT 24
Finished May 26 02:56:54 PM PDT 24
Peak memory 270080 kb
Host smart-0e3171fe-4135-4673-bf15-fe8b8a52ec6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139115205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3139115205
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3376889142
Short name T205
Test name
Test status
Simulation time 57952333523 ps
CPU time 458.18 seconds
Started May 26 02:54:01 PM PDT 24
Finished May 26 03:01:42 PM PDT 24
Peak memory 280096 kb
Host smart-ebcaae32-0abd-4bc7-ad19-8a44a4502b0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3376889142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3376889142
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1308206131
Short name T618
Test name
Test status
Simulation time 36950503 ps
CPU time 1.3 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:02 PM PDT 24
Peak memory 212668 kb
Host smart-9cd2f63f-d47d-4435-8121-4a0599a552af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308206131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1308206131
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2002499837
Short name T837
Test name
Test status
Simulation time 20931657 ps
CPU time 1.18 seconds
Started May 26 02:54:00 PM PDT 24
Finished May 26 02:54:04 PM PDT 24
Peak memory 209692 kb
Host smart-59755e42-c1db-42a0-a985-380571e7f368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002499837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2002499837
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3761698312
Short name T759
Test name
Test status
Simulation time 330149455 ps
CPU time 7.62 seconds
Started May 26 02:54:00 PM PDT 24
Finished May 26 02:54:10 PM PDT 24
Peak memory 218220 kb
Host smart-bba8bf5b-a74b-476d-810a-391087645918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761698312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3761698312
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1353943597
Short name T634
Test name
Test status
Simulation time 341079850 ps
CPU time 5.2 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:11 PM PDT 24
Peak memory 217212 kb
Host smart-68600df6-aaee-46ab-bda7-c126e7412388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353943597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1353943597
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1558898176
Short name T762
Test name
Test status
Simulation time 528391963 ps
CPU time 3.18 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:10 PM PDT 24
Peak memory 218112 kb
Host smart-f908d028-bcca-4e24-8164-4fb9aa3788e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558898176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1558898176
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.894964536
Short name T150
Test name
Test status
Simulation time 1491982043 ps
CPU time 13.73 seconds
Started May 26 02:54:06 PM PDT 24
Finished May 26 02:54:22 PM PDT 24
Peak memory 226324 kb
Host smart-d96e2984-da42-4ae4-8d1a-d915acc48951
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894964536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.894964536
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1571112264
Short name T806
Test name
Test status
Simulation time 512319655 ps
CPU time 11.63 seconds
Started May 26 02:54:00 PM PDT 24
Finished May 26 02:54:14 PM PDT 24
Peak memory 218040 kb
Host smart-1706855d-cba6-41c6-872c-24cc9809e82f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571112264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1571112264
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1796813721
Short name T258
Test name
Test status
Simulation time 476227604 ps
CPU time 7.64 seconds
Started May 26 02:53:58 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 218068 kb
Host smart-65c5c309-08ef-4a66-a315-8716cc41f75e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796813721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1796813721
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.344101731
Short name T798
Test name
Test status
Simulation time 437608814 ps
CPU time 9.5 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 218152 kb
Host smart-f3be6cc9-0c9c-4419-b1ba-cad5626607fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344101731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.344101731
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3376618449
Short name T826
Test name
Test status
Simulation time 88167297 ps
CPU time 3.92 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:10 PM PDT 24
Peak memory 217812 kb
Host smart-f07609ab-721a-40d2-95ec-2f734b45ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376618449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3376618449
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1001232512
Short name T671
Test name
Test status
Simulation time 176134633 ps
CPU time 18.22 seconds
Started May 26 02:54:05 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 250784 kb
Host smart-f4891480-ea7c-4cc2-a911-26f5db4eef26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001232512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1001232512
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2685556254
Short name T629
Test name
Test status
Simulation time 86078061 ps
CPU time 4.22 seconds
Started May 26 02:54:01 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 222732 kb
Host smart-d7aab270-b8fe-41b2-b9d9-c3eef4c03e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685556254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2685556254
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2596383565
Short name T79
Test name
Test status
Simulation time 2522663923 ps
CPU time 86.8 seconds
Started May 26 02:53:55 PM PDT 24
Finished May 26 02:55:25 PM PDT 24
Peak memory 246852 kb
Host smart-f8c42893-418c-4359-ae83-00476afc3344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596383565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2596383565
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.936061614
Short name T476
Test name
Test status
Simulation time 35847292 ps
CPU time 0.9 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:07 PM PDT 24
Peak memory 211688 kb
Host smart-be1a9de7-856c-4ac7-85d2-a8debd478055
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936061614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.936061614
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2340031109
Short name T506
Test name
Test status
Simulation time 11985505 ps
CPU time 0.98 seconds
Started May 26 02:54:06 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 209596 kb
Host smart-19ab11cb-9e6a-4c4d-8850-65b09c285d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340031109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2340031109
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2431151095
Short name T709
Test name
Test status
Simulation time 479567246 ps
CPU time 12.07 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 218104 kb
Host smart-99f97adf-51f8-42ea-adde-148af8b0c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431151095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2431151095
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2126390405
Short name T468
Test name
Test status
Simulation time 226281599 ps
CPU time 2.78 seconds
Started May 26 02:54:02 PM PDT 24
Finished May 26 02:54:07 PM PDT 24
Peak memory 209592 kb
Host smart-c18fae83-fe22-4b3e-85dd-b948cfce86f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126390405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2126390405
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1338888042
Short name T793
Test name
Test status
Simulation time 100867311 ps
CPU time 2.46 seconds
Started May 26 02:54:08 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 218116 kb
Host smart-79308635-4b55-4761-8076-2c0ac9564b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338888042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1338888042
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4114842612
Short name T599
Test name
Test status
Simulation time 295754814 ps
CPU time 12.83 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 226204 kb
Host smart-08f78e4d-1315-4052-88f2-a2f83c6ee046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114842612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4114842612
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4188740098
Short name T743
Test name
Test status
Simulation time 343819846 ps
CPU time 15.55 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:22 PM PDT 24
Peak memory 226140 kb
Host smart-139f8a35-e888-4d90-99bd-4ad08c46cce5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188740098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4188740098
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2966143867
Short name T827
Test name
Test status
Simulation time 426690152 ps
CPU time 11.17 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 218064 kb
Host smart-a2e4418e-6a23-4ad4-8218-81c8016ac8c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966143867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2966143867
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2934418157
Short name T338
Test name
Test status
Simulation time 298602093 ps
CPU time 9.5 seconds
Started May 26 02:54:05 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 218140 kb
Host smart-75ddbecf-34e0-406c-9dff-4c30915fea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934418157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2934418157
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1117559289
Short name T85
Test name
Test status
Simulation time 22883265 ps
CPU time 1.06 seconds
Started May 26 02:54:07 PM PDT 24
Finished May 26 02:54:10 PM PDT 24
Peak memory 212856 kb
Host smart-2fe81ed1-9def-4623-b086-725e02101fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117559289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1117559289
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.4253636066
Short name T271
Test name
Test status
Simulation time 928651074 ps
CPU time 27.14 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:42 PM PDT 24
Peak memory 250580 kb
Host smart-af340e39-fd88-49aa-a5ff-0eecb144943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253636066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.4253636066
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3686127708
Short name T813
Test name
Test status
Simulation time 592535389 ps
CPU time 8.23 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:15 PM PDT 24
Peak memory 251036 kb
Host smart-fd8eec9e-fa31-4f3f-b79f-5a4a603b3780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686127708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3686127708
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.582260700
Short name T464
Test name
Test status
Simulation time 74139854725 ps
CPU time 328.56 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:59:34 PM PDT 24
Peak memory 284796 kb
Host smart-e06db5b4-db92-48e4-a8af-f42d3bcba4df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582260700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.582260700
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3959550702
Short name T562
Test name
Test status
Simulation time 12091159 ps
CPU time 0.95 seconds
Started May 26 02:54:06 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 208860 kb
Host smart-b7c9a5a9-3998-42db-b716-2916834a0152
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959550702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3959550702
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1102861364
Short name T480
Test name
Test status
Simulation time 14536249 ps
CPU time 0.84 seconds
Started May 26 02:54:05 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 209032 kb
Host smart-51ec6307-a1f2-4bf5-aea1-0333ed132b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102861364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1102861364
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2805685079
Short name T423
Test name
Test status
Simulation time 3448449179 ps
CPU time 19.01 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:34 PM PDT 24
Peak memory 219128 kb
Host smart-8bf33b97-472c-4e39-9e50-d606583c74f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805685079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2805685079
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3926035284
Short name T513
Test name
Test status
Simulation time 779584225 ps
CPU time 5.23 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:11 PM PDT 24
Peak memory 216928 kb
Host smart-09d7abfd-d82f-4805-bf4f-0b1531d55ec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926035284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3926035284
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1657184474
Short name T478
Test name
Test status
Simulation time 161062188 ps
CPU time 4.73 seconds
Started May 26 02:54:05 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 218264 kb
Host smart-d75452ab-8836-4bdc-9e04-4db0ecb699d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657184474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1657184474
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3186081472
Short name T421
Test name
Test status
Simulation time 1662829693 ps
CPU time 16.77 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:30 PM PDT 24
Peak memory 219056 kb
Host smart-6c74235f-ff67-443a-ac04-02953faf8140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186081472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3186081472
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1308502758
Short name T34
Test name
Test status
Simulation time 2659658656 ps
CPU time 14.52 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 218188 kb
Host smart-b42e34ed-236b-44f2-a2ce-0b116c0f3991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308502758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1308502758
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.143118076
Short name T68
Test name
Test status
Simulation time 6285738496 ps
CPU time 10.36 seconds
Started May 26 02:54:06 PM PDT 24
Finished May 26 02:54:19 PM PDT 24
Peak memory 218144 kb
Host smart-83d11584-92ae-4758-b4b4-0c44c4a3351c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143118076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.143118076
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2799775910
Short name T272
Test name
Test status
Simulation time 267787340 ps
CPU time 8.03 seconds
Started May 26 02:54:02 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 218160 kb
Host smart-0408cef0-bdfe-4900-a387-fc97cb6a01e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799775910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2799775910
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1452494114
Short name T650
Test name
Test status
Simulation time 25839618 ps
CPU time 1.14 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 212032 kb
Host smart-01103be7-1a37-4686-bb35-25eb9677cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452494114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1452494114
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2574371443
Short name T560
Test name
Test status
Simulation time 162977018 ps
CPU time 20.74 seconds
Started May 26 02:54:08 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 251024 kb
Host smart-354e780b-5452-4379-ad9c-8b3cf350ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574371443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2574371443
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3588594417
Short name T488
Test name
Test status
Simulation time 1048419630 ps
CPU time 6.8 seconds
Started May 26 02:54:08 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 250960 kb
Host smart-b33ea554-0fe6-48ce-84fe-1c8256b02b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588594417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3588594417
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1497494927
Short name T850
Test name
Test status
Simulation time 10747877534 ps
CPU time 50.7 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:57 PM PDT 24
Peak memory 226236 kb
Host smart-548b2c0f-1fea-43c9-b33c-19612a8c4550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497494927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1497494927
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3495714186
Short name T828
Test name
Test status
Simulation time 22834688 ps
CPU time 1.37 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:15 PM PDT 24
Peak memory 212820 kb
Host smart-26ee557e-ed06-4215-ae81-0435f7989e02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495714186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3495714186
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3270218590
Short name T881
Test name
Test status
Simulation time 25802965 ps
CPU time 0.89 seconds
Started May 26 02:54:06 PM PDT 24
Finished May 26 02:54:10 PM PDT 24
Peak memory 209640 kb
Host smart-47868526-3850-45fe-a192-cbada7547a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270218590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3270218590
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3763723346
Short name T693
Test name
Test status
Simulation time 844205391 ps
CPU time 10.62 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 218180 kb
Host smart-8d77d5b8-d845-4a7a-a5f5-c4acf4af21ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763723346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3763723346
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1587305057
Short name T647
Test name
Test status
Simulation time 1140072438 ps
CPU time 3.3 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 216988 kb
Host smart-08320387-8344-4818-9fc7-85245d50ebc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587305057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1587305057
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.258590898
Short name T297
Test name
Test status
Simulation time 57194842 ps
CPU time 2.96 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 218216 kb
Host smart-2b3739f1-dca9-4e19-97ab-ceaf03045a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258590898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.258590898
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1128315256
Short name T343
Test name
Test status
Simulation time 5440935860 ps
CPU time 11.55 seconds
Started May 26 02:54:07 PM PDT 24
Finished May 26 02:54:21 PM PDT 24
Peak memory 226200 kb
Host smart-ff1b3853-eb52-47e6-befd-ef4a4eb508c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128315256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1128315256
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3515257061
Short name T92
Test name
Test status
Simulation time 1952937987 ps
CPU time 14.69 seconds
Started May 26 02:54:07 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 217984 kb
Host smart-729aa4a0-3ef3-4ef0-8a10-fe9da2fa3abd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515257061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3515257061
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2186495998
Short name T816
Test name
Test status
Simulation time 1307602083 ps
CPU time 8.33 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:14 PM PDT 24
Peak memory 218076 kb
Host smart-bc88621a-da3e-421a-b274-d9adc3ee81db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186495998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2186495998
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4075666425
Short name T725
Test name
Test status
Simulation time 422441628 ps
CPU time 8.36 seconds
Started May 26 02:54:07 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 218104 kb
Host smart-d5aaa74e-2eb8-49e8-8dfd-671be9999f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075666425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4075666425
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2206716232
Short name T494
Test name
Test status
Simulation time 94747178 ps
CPU time 2.29 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:15 PM PDT 24
Peak memory 214300 kb
Host smart-084bb72d-fffb-4480-898e-e55a40bedea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206716232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2206716232
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.855029981
Short name T721
Test name
Test status
Simulation time 1344386075 ps
CPU time 29.46 seconds
Started May 26 02:54:07 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 251044 kb
Host smart-b86d1fba-085b-445d-8112-957bd9c0c8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855029981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.855029981
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2131982655
Short name T570
Test name
Test status
Simulation time 86690766 ps
CPU time 7.94 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:22 PM PDT 24
Peak memory 251152 kb
Host smart-e2a3e422-82ef-4faf-8d79-d33174482b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131982655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2131982655
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1713609962
Short name T294
Test name
Test status
Simulation time 28274540138 ps
CPU time 176.61 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:57:10 PM PDT 24
Peak memory 283852 kb
Host smart-0f0f05c4-bc88-474e-bf07-3da2af67da19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713609962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1713609962
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1513009544
Short name T661
Test name
Test status
Simulation time 41567362498 ps
CPU time 824.75 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 03:07:50 PM PDT 24
Peak memory 272356 kb
Host smart-741cbf7f-a45c-4393-b787-e28047dccd58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1513009544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1513009544
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3831990545
Short name T639
Test name
Test status
Simulation time 48616363 ps
CPU time 0.84 seconds
Started May 26 02:54:05 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 208540 kb
Host smart-304d7f79-bad0-45f3-be99-d4396b46ed54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831990545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3831990545
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2810442001
Short name T181
Test name
Test status
Simulation time 21678714 ps
CPU time 1 seconds
Started May 26 02:53:03 PM PDT 24
Finished May 26 02:53:06 PM PDT 24
Peak memory 209692 kb
Host smart-e9dedc9f-126d-4f97-b3e7-72ceea13c8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810442001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2810442001
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.362406570
Short name T524
Test name
Test status
Simulation time 19466967 ps
CPU time 0.83 seconds
Started May 26 02:53:03 PM PDT 24
Finished May 26 02:53:06 PM PDT 24
Peak memory 209420 kb
Host smart-11d37148-c7de-4876-ac7c-afb803c053f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362406570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.362406570
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.888750828
Short name T37
Test name
Test status
Simulation time 3938747072 ps
CPU time 10.66 seconds
Started May 26 02:52:59 PM PDT 24
Finished May 26 02:53:10 PM PDT 24
Peak memory 218480 kb
Host smart-62803fcf-afec-4f84-9854-728e8a7856de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888750828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.888750828
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4279402887
Short name T358
Test name
Test status
Simulation time 262407428 ps
CPU time 2.41 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:10 PM PDT 24
Peak memory 209644 kb
Host smart-548191a4-b9be-4a22-b383-5f59bd364c94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279402887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4279402887
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.4104324709
Short name T333
Test name
Test status
Simulation time 1144247673 ps
CPU time 34.73 seconds
Started May 26 02:52:48 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 218056 kb
Host smart-c976cb06-9cc2-4167-bd1c-79ea2d05e37f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104324709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.4104324709
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3101037575
Short name T456
Test name
Test status
Simulation time 1723493064 ps
CPU time 7.23 seconds
Started May 26 02:52:56 PM PDT 24
Finished May 26 02:53:04 PM PDT 24
Peak memory 217424 kb
Host smart-5bb551ac-f143-45bc-88e0-d2166f8ce102
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101037575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
101037575
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.287729133
Short name T231
Test name
Test status
Simulation time 231000759 ps
CPU time 6.73 seconds
Started May 26 02:53:04 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 217960 kb
Host smart-afb43f67-338f-42b8-aa2a-3f28f5a44c37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287729133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.287729133
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1918440735
Short name T637
Test name
Test status
Simulation time 1183957398 ps
CPU time 15.45 seconds
Started May 26 02:52:56 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 213300 kb
Host smart-47523cc4-d198-44dd-bf72-e201d422e9f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918440735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1918440735
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3927322177
Short name T325
Test name
Test status
Simulation time 192834373 ps
CPU time 3.34 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:12 PM PDT 24
Peak memory 213148 kb
Host smart-4ee6a7f4-f3a9-48dd-936d-3009a604af1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927322177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3927322177
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.794433764
Short name T723
Test name
Test status
Simulation time 5794800603 ps
CPU time 41.54 seconds
Started May 26 02:53:00 PM PDT 24
Finished May 26 02:53:42 PM PDT 24
Peak memory 253380 kb
Host smart-afafc2be-8a2f-4d7d-979c-cbdeae48b424
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794433764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.794433764
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2096735485
Short name T463
Test name
Test status
Simulation time 1307823330 ps
CPU time 16.91 seconds
Started May 26 02:53:00 PM PDT 24
Finished May 26 02:53:18 PM PDT 24
Peak memory 244484 kb
Host smart-e921042b-459c-4d26-92d6-b2d5066241c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096735485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2096735485
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4254252955
Short name T594
Test name
Test status
Simulation time 68027136 ps
CPU time 3.63 seconds
Started May 26 02:53:02 PM PDT 24
Finished May 26 02:53:07 PM PDT 24
Peak memory 218176 kb
Host smart-a63c1561-d433-4e5a-b41e-ef366128f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254252955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4254252955
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1170087299
Short name T32
Test name
Test status
Simulation time 523404380 ps
CPU time 17.81 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 214544 kb
Host smart-c87cbd8d-53bb-4e6e-bcfd-e16d383b4d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170087299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1170087299
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2100673235
Short name T17
Test name
Test status
Simulation time 1202909149 ps
CPU time 23.66 seconds
Started May 26 02:53:01 PM PDT 24
Finished May 26 02:53:27 PM PDT 24
Peak memory 268404 kb
Host smart-e0b47e31-795f-4035-bcfc-ca0f25133777
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100673235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2100673235
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2479083096
Short name T246
Test name
Test status
Simulation time 776618270 ps
CPU time 16.52 seconds
Started May 26 02:53:04 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 218976 kb
Host smart-d4166ad9-f45d-479e-9e9c-fa6aabe3a8f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479083096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2479083096
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3973943976
Short name T521
Test name
Test status
Simulation time 996934378 ps
CPU time 9.09 seconds
Started May 26 02:52:59 PM PDT 24
Finished May 26 02:53:10 PM PDT 24
Peak memory 218056 kb
Host smart-84a80ab3-c664-4d90-a222-2c1b20ba4def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973943976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3973943976
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.34022437
Short name T516
Test name
Test status
Simulation time 1533502663 ps
CPU time 8.71 seconds
Started May 26 02:52:52 PM PDT 24
Finished May 26 02:53:02 PM PDT 24
Peak memory 218144 kb
Host smart-a80c561d-328f-4643-aec5-c573df4b0e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34022437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.34022437
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.757631928
Short name T788
Test name
Test status
Simulation time 240008776 ps
CPU time 9.71 seconds
Started May 26 02:53:04 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 218092 kb
Host smart-c7c004d2-b7b6-4670-abef-4bcaf89515b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757631928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.757631928
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2929947995
Short name T726
Test name
Test status
Simulation time 22154495 ps
CPU time 1.5 seconds
Started May 26 02:52:48 PM PDT 24
Finished May 26 02:52:50 PM PDT 24
Peak memory 213452 kb
Host smart-9daa9f2d-c8bd-4014-9771-13b8db0f895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929947995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2929947995
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3386383006
Short name T833
Test name
Test status
Simulation time 243579455 ps
CPU time 28.55 seconds
Started May 26 02:52:58 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 251032 kb
Host smart-430cb998-afc1-4dad-929b-de1e46bff7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386383006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3386383006
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3947642499
Short name T690
Test name
Test status
Simulation time 666117072 ps
CPU time 3.43 seconds
Started May 26 02:52:54 PM PDT 24
Finished May 26 02:52:58 PM PDT 24
Peak memory 222684 kb
Host smart-b1117cbc-1ddf-40af-9b58-fc29690a4b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947642499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3947642499
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.4106160055
Short name T775
Test name
Test status
Simulation time 84779721802 ps
CPU time 556.21 seconds
Started May 26 02:52:57 PM PDT 24
Finished May 26 03:02:15 PM PDT 24
Peak memory 496948 kb
Host smart-dcd92bd1-58fe-4c8a-bcad-1174f872af22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4106160055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.4106160055
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4063858180
Short name T344
Test name
Test status
Simulation time 63730377 ps
CPU time 0.77 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:10 PM PDT 24
Peak memory 208500 kb
Host smart-37deb4b5-c554-4743-b93f-7770bc170a6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063858180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4063858180
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.456434921
Short name T227
Test name
Test status
Simulation time 24008466 ps
CPU time 0.9 seconds
Started May 26 02:54:14 PM PDT 24
Finished May 26 02:54:18 PM PDT 24
Peak memory 209608 kb
Host smart-29f0c93d-023c-4d5a-a7fb-f2c6dac4ef15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456434921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.456434921
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2879737390
Short name T832
Test name
Test status
Simulation time 273092635 ps
CPU time 12.94 seconds
Started May 26 02:54:02 PM PDT 24
Finished May 26 02:54:18 PM PDT 24
Peak memory 218136 kb
Host smart-34fbc044-3ee6-46c3-801c-9c33741e7eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879737390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2879737390
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2085772629
Short name T459
Test name
Test status
Simulation time 1538283452 ps
CPU time 5.7 seconds
Started May 26 02:54:05 PM PDT 24
Finished May 26 02:54:13 PM PDT 24
Peak memory 216616 kb
Host smart-486f8a94-fcd8-4fef-be18-44c10e3d57c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085772629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2085772629
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1895574055
Short name T321
Test name
Test status
Simulation time 268302191 ps
CPU time 3.95 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:11 PM PDT 24
Peak memory 218120 kb
Host smart-970f02b5-3009-4e3f-b3f6-fcd37ee1cb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895574055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1895574055
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3715091544
Short name T751
Test name
Test status
Simulation time 359859998 ps
CPU time 16.89 seconds
Started May 26 02:54:04 PM PDT 24
Finished May 26 02:54:23 PM PDT 24
Peak memory 219076 kb
Host smart-fee50d37-9fc8-48ed-b332-331d7e9c4a8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715091544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3715091544
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.167947115
Short name T389
Test name
Test status
Simulation time 390274566 ps
CPU time 14.38 seconds
Started May 26 02:54:08 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 218048 kb
Host smart-6bf3cb2d-b797-4479-af58-3934f378b62e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167947115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.167947115
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3636649771
Short name T787
Test name
Test status
Simulation time 498369471 ps
CPU time 7.72 seconds
Started May 26 02:54:02 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 218044 kb
Host smart-8b060d8b-c64b-44fc-a6ee-ff3fb2c1cfd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636649771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3636649771
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1703245755
Short name T871
Test name
Test status
Simulation time 1203887243 ps
CPU time 11.95 seconds
Started May 26 02:54:08 PM PDT 24
Finished May 26 02:54:22 PM PDT 24
Peak memory 218268 kb
Host smart-a9c6629f-35d5-48ed-a04f-65c3cdf7b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703245755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1703245755
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.105087006
Short name T605
Test name
Test status
Simulation time 31341530 ps
CPU time 1.53 seconds
Started May 26 02:54:08 PM PDT 24
Finished May 26 02:54:12 PM PDT 24
Peak memory 217804 kb
Host smart-8c34d7fb-a62c-45f2-a071-5d606f8901e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105087006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.105087006
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.592875463
Short name T250
Test name
Test status
Simulation time 227435837 ps
CPU time 25.76 seconds
Started May 26 02:54:02 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 250912 kb
Host smart-beb1b846-0984-45b1-932a-ef1de6f6bec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592875463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.592875463
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3266364541
Short name T46
Test name
Test status
Simulation time 110307320 ps
CPU time 6.45 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:20 PM PDT 24
Peak memory 250516 kb
Host smart-6ef66af6-7572-4606-9736-cc3bfe20f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266364541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3266364541
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3569087615
Short name T277
Test name
Test status
Simulation time 20825474646 ps
CPU time 151.13 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:56:46 PM PDT 24
Peak memory 283820 kb
Host smart-6763ab56-21bb-4692-98b3-1b1dff4ebbb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569087615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3569087615
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1358836095
Short name T91
Test name
Test status
Simulation time 11885779411 ps
CPU time 252.99 seconds
Started May 26 02:54:07 PM PDT 24
Finished May 26 02:58:22 PM PDT 24
Peak memory 283948 kb
Host smart-a7091e2f-a3c2-4007-84cd-9182ae9b1fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1358836095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1358836095
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2392133212
Short name T853
Test name
Test status
Simulation time 234493864 ps
CPU time 0.99 seconds
Started May 26 02:54:03 PM PDT 24
Finished May 26 02:54:06 PM PDT 24
Peak memory 212768 kb
Host smart-630994a3-4c33-44bd-990d-f994012d5176
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392133212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2392133212
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3473203286
Short name T3
Test name
Test status
Simulation time 33960879 ps
CPU time 1.2 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 209696 kb
Host smart-4ffd0304-008c-4c72-af1f-42452aebcd52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473203286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3473203286
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3664927543
Short name T678
Test name
Test status
Simulation time 1361231288 ps
CPU time 8.13 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:20 PM PDT 24
Peak memory 218112 kb
Host smart-b6bf466b-66ff-4975-948a-72effe1de26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664927543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3664927543
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4117895447
Short name T552
Test name
Test status
Simulation time 889627465 ps
CPU time 10.65 seconds
Started May 26 02:54:12 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 209632 kb
Host smart-d6c0308f-f1e8-4780-9c6d-a24810240fa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117895447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.4117895447
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1980660860
Short name T268
Test name
Test status
Simulation time 253925046 ps
CPU time 2.73 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 218144 kb
Host smart-f51f8d73-db86-4fd5-8ab4-685892d35617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980660860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1980660860
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4094127994
Short name T695
Test name
Test status
Simulation time 3652704378 ps
CPU time 17.46 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 220144 kb
Host smart-4208b395-954e-42cc-8b13-fce146838a50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094127994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4094127994
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.360795345
Short name T531
Test name
Test status
Simulation time 1936668098 ps
CPU time 12.35 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 217976 kb
Host smart-d1df7f1c-2336-4ad1-a694-7c412dc8c7e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360795345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.360795345
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3003254819
Short name T174
Test name
Test status
Simulation time 1358049545 ps
CPU time 13.4 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 218188 kb
Host smart-f1c6370c-8e21-485d-b6c9-33c346132fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003254819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3003254819
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1354594572
Short name T455
Test name
Test status
Simulation time 630105869 ps
CPU time 9.17 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 218172 kb
Host smart-cef8129e-1324-43e4-8224-5ee039588bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354594572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1354594572
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1812917733
Short name T694
Test name
Test status
Simulation time 60247473 ps
CPU time 1.88 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 217784 kb
Host smart-49151024-d3da-473c-9479-e09d15b6a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812917733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1812917733
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3456539773
Short name T662
Test name
Test status
Simulation time 1559063977 ps
CPU time 29.07 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:44 PM PDT 24
Peak memory 250620 kb
Host smart-8d31c17a-2919-4689-8efa-a1dd8723e1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456539773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3456539773
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.123920010
Short name T543
Test name
Test status
Simulation time 158493313 ps
CPU time 7.87 seconds
Started May 26 02:54:08 PM PDT 24
Finished May 26 02:54:19 PM PDT 24
Peak memory 246908 kb
Host smart-5dcd0122-e32f-4561-a0d9-4dd33d11d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123920010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.123920010
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.521810437
Short name T730
Test name
Test status
Simulation time 20916530277 ps
CPU time 141.45 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:56:37 PM PDT 24
Peak memory 279404 kb
Host smart-5ba21926-9b59-42a6-92ab-862d06638c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521810437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.521810437
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2032820407
Short name T804
Test name
Test status
Simulation time 92681003261 ps
CPU time 677.14 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 03:05:32 PM PDT 24
Peak memory 300476 kb
Host smart-f9321f3f-3441-422a-9a42-bc5629e2d125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2032820407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2032820407
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2277456242
Short name T265
Test name
Test status
Simulation time 14643534 ps
CPU time 1.05 seconds
Started May 26 02:54:05 PM PDT 24
Finished May 26 02:54:08 PM PDT 24
Peak memory 212800 kb
Host smart-4ebc687e-4f93-4008-bb94-2e4e36e26c7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277456242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2277456242
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1829624628
Short name T172
Test name
Test status
Simulation time 24736179 ps
CPU time 1.03 seconds
Started May 26 02:54:09 PM PDT 24
Finished May 26 02:54:14 PM PDT 24
Peak memory 209700 kb
Host smart-2414b819-3060-4040-b065-a456be0d6e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829624628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1829624628
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1082065854
Short name T304
Test name
Test status
Simulation time 2210143594 ps
CPU time 19.86 seconds
Started May 26 02:54:17 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 218112 kb
Host smart-ed7de23c-adce-49fd-8f29-aa93f43d5591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082065854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1082065854
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.425811931
Short name T738
Test name
Test status
Simulation time 517553257 ps
CPU time 13.58 seconds
Started May 26 02:54:16 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 209636 kb
Host smart-360fb942-93f7-4918-a647-16d8f4dae56e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425811931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.425811931
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.456766692
Short name T835
Test name
Test status
Simulation time 88669709 ps
CPU time 3.61 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 218132 kb
Host smart-fa0e3faf-8824-49b3-a046-3a68f5220fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456766692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.456766692
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2890733375
Short name T228
Test name
Test status
Simulation time 399507822 ps
CPU time 14.19 seconds
Started May 26 02:54:18 PM PDT 24
Finished May 26 02:54:34 PM PDT 24
Peak memory 226224 kb
Host smart-95da4e72-864b-4afa-8636-5561e47ffb54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890733375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2890733375
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4091404101
Short name T310
Test name
Test status
Simulation time 1099148998 ps
CPU time 10.26 seconds
Started May 26 02:54:12 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 218184 kb
Host smart-39a09a94-aef1-4651-ad0b-02b55d19dde5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091404101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4091404101
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3642504250
Short name T349
Test name
Test status
Simulation time 2452388588 ps
CPU time 9.38 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:23 PM PDT 24
Peak memory 218140 kb
Host smart-35d495d4-5b30-4f6e-8c1c-f144fe51034b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642504250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3642504250
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1458171266
Short name T87
Test name
Test status
Simulation time 2386331647 ps
CPU time 18.55 seconds
Started May 26 02:54:15 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 218260 kb
Host smart-2d74c76d-c274-45cd-9a8a-b2d5de149bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458171266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1458171266
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3258030238
Short name T546
Test name
Test status
Simulation time 81907762 ps
CPU time 3.21 seconds
Started May 26 02:54:14 PM PDT 24
Finished May 26 02:54:20 PM PDT 24
Peak memory 214608 kb
Host smart-32f34153-0d6b-476e-8ae3-7f8119b676e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258030238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3258030238
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.815633181
Short name T873
Test name
Test status
Simulation time 1421882835 ps
CPU time 27.09 seconds
Started May 26 02:54:19 PM PDT 24
Finished May 26 02:54:47 PM PDT 24
Peak memory 251040 kb
Host smart-b69f7df0-3f2e-46b1-aef6-590a6e221a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815633181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.815633181
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.347972621
Short name T441
Test name
Test status
Simulation time 62008106 ps
CPU time 9.08 seconds
Started May 26 02:54:07 PM PDT 24
Finished May 26 02:54:18 PM PDT 24
Peak memory 251028 kb
Host smart-530cded6-8ef6-42b9-a1c5-1b3a00b414e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347972621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.347972621
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1356056401
Short name T545
Test name
Test status
Simulation time 19645090153 ps
CPU time 170.56 seconds
Started May 26 02:54:15 PM PDT 24
Finished May 26 02:57:08 PM PDT 24
Peak memory 259288 kb
Host smart-c2311fa8-b2b7-468a-9a0a-a38418cc7d2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356056401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1356056401
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1594766654
Short name T499
Test name
Test status
Simulation time 12064070 ps
CPU time 1.08 seconds
Started May 26 02:54:17 PM PDT 24
Finished May 26 02:54:20 PM PDT 24
Peak memory 211656 kb
Host smart-49f0470c-6696-475d-b8e4-875ccabdd4ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594766654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1594766654
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1056711643
Short name T740
Test name
Test status
Simulation time 39664197 ps
CPU time 0.84 seconds
Started May 26 02:54:13 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 209600 kb
Host smart-ff9dee8e-de3a-4b41-af1f-c010b317527a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056711643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1056711643
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2862479797
Short name T247
Test name
Test status
Simulation time 415119957 ps
CPU time 17.72 seconds
Started May 26 02:54:18 PM PDT 24
Finished May 26 02:54:37 PM PDT 24
Peak memory 218128 kb
Host smart-82e05beb-df87-49a7-95d7-15382c0fe13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862479797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2862479797
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.626990307
Short name T185
Test name
Test status
Simulation time 1200191888 ps
CPU time 3.77 seconds
Started May 26 02:54:12 PM PDT 24
Finished May 26 02:54:19 PM PDT 24
Peak memory 217116 kb
Host smart-f40af13c-47f9-4501-a696-528520ab51a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626990307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.626990307
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.319723036
Short name T831
Test name
Test status
Simulation time 188645531 ps
CPU time 2.13 seconds
Started May 26 02:54:13 PM PDT 24
Finished May 26 02:54:18 PM PDT 24
Peak memory 218124 kb
Host smart-1b46a4c8-e2e6-4313-b1e6-0932bf2dc9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319723036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.319723036
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.811272059
Short name T561
Test name
Test status
Simulation time 179822663 ps
CPU time 9.6 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:23 PM PDT 24
Peak memory 226216 kb
Host smart-23dea468-8f67-42a5-b5a2-a529a99f9674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811272059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.811272059
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1846506863
Short name T429
Test name
Test status
Simulation time 1639566007 ps
CPU time 12.4 seconds
Started May 26 02:54:17 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 218076 kb
Host smart-6396c45b-9be8-4de6-9f43-647e66769f75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846506863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1846506863
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2806104974
Short name T713
Test name
Test status
Simulation time 365399196 ps
CPU time 9.46 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:23 PM PDT 24
Peak memory 218108 kb
Host smart-df0ce00f-916d-480d-ba14-b67dd205cdba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806104974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2806104974
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.982936002
Short name T445
Test name
Test status
Simulation time 18572235 ps
CPU time 1.57 seconds
Started May 26 02:54:16 PM PDT 24
Finished May 26 02:54:20 PM PDT 24
Peak memory 213388 kb
Host smart-43e6e263-2bc6-4e8b-88b5-518b3cd4ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982936002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.982936002
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.69848824
Short name T811
Test name
Test status
Simulation time 690110437 ps
CPU time 25.7 seconds
Started May 26 02:54:16 PM PDT 24
Finished May 26 02:54:44 PM PDT 24
Peak memory 251048 kb
Host smart-5349623b-ab0c-403d-898b-4e34554c929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69848824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.69848824
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1666884719
Short name T249
Test name
Test status
Simulation time 313693023 ps
CPU time 6.38 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:21 PM PDT 24
Peak memory 250608 kb
Host smart-64c6efb4-b77e-441c-bd29-0e081c5122ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666884719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1666884719
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.280679681
Short name T736
Test name
Test status
Simulation time 23975908763 ps
CPU time 97.18 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:55:52 PM PDT 24
Peak memory 251048 kb
Host smart-6116b149-1bed-49e6-841e-058424687107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280679681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.280679681
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1844213290
Short name T90
Test name
Test status
Simulation time 44221870479 ps
CPU time 716.46 seconds
Started May 26 02:54:13 PM PDT 24
Finished May 26 03:06:13 PM PDT 24
Peak memory 316736 kb
Host smart-49f4eb80-1931-443d-ac8e-7aa4c8c3bbbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1844213290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.1844213290
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.546080134
Short name T700
Test name
Test status
Simulation time 89820694 ps
CPU time 0.87 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 208832 kb
Host smart-6fb17d52-49b6-4481-a440-397c2f385afa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546080134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.546080134
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2862497419
Short name T653
Test name
Test status
Simulation time 39360096 ps
CPU time 1.27 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:15 PM PDT 24
Peak memory 209696 kb
Host smart-4a58d795-6d5a-47f3-896c-dc791eb15270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862497419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2862497419
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.438773814
Short name T703
Test name
Test status
Simulation time 268907197 ps
CPU time 10.11 seconds
Started May 26 02:54:19 PM PDT 24
Finished May 26 02:54:30 PM PDT 24
Peak memory 218048 kb
Host smart-06ac18d1-b2ca-4f9c-b8f8-24ac9689d6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438773814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.438773814
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1465340539
Short name T523
Test name
Test status
Simulation time 412766766 ps
CPU time 2.72 seconds
Started May 26 02:54:19 PM PDT 24
Finished May 26 02:54:23 PM PDT 24
Peak memory 209716 kb
Host smart-d5e4664c-2683-4635-812f-56e75f8a6fe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465340539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1465340539
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2854770376
Short name T535
Test name
Test status
Simulation time 138136031 ps
CPU time 2.35 seconds
Started May 26 02:54:13 PM PDT 24
Finished May 26 02:54:19 PM PDT 24
Peak memory 217956 kb
Host smart-38b2b1a3-5bf0-4548-b9e6-c431cc96bcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854770376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2854770376
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.897412083
Short name T776
Test name
Test status
Simulation time 665608416 ps
CPU time 13.02 seconds
Started May 26 02:54:14 PM PDT 24
Finished May 26 02:54:30 PM PDT 24
Peak memory 218540 kb
Host smart-ada54aa9-47db-4d1b-9715-431d790e8abc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897412083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.897412083
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2779923388
Short name T233
Test name
Test status
Simulation time 1016257600 ps
CPU time 9.24 seconds
Started May 26 02:54:20 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 218064 kb
Host smart-3d28c222-d4fb-46b7-8642-ec0f9c0695b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779923388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2779923388
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1988885571
Short name T669
Test name
Test status
Simulation time 1280294713 ps
CPU time 9.38 seconds
Started May 26 02:54:16 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 218060 kb
Host smart-474aa4c5-86d3-4801-b9a3-143aec77eadf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988885571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1988885571
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4163772042
Short name T59
Test name
Test status
Simulation time 1416652288 ps
CPU time 11.89 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 218172 kb
Host smart-2dc91c9b-957f-4eed-82ad-d2909db5bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163772042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4163772042
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1898981151
Short name T76
Test name
Test status
Simulation time 72924042 ps
CPU time 1.53 seconds
Started May 26 02:54:11 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 213576 kb
Host smart-1acabd6e-f6e2-4b5b-8b65-04e7bc2ed9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898981151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1898981151
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.113575473
Short name T461
Test name
Test status
Simulation time 1975140675 ps
CPU time 18.12 seconds
Started May 26 02:54:12 PM PDT 24
Finished May 26 02:54:34 PM PDT 24
Peak memory 251040 kb
Host smart-0efa73f7-7a84-4f3f-8d22-6c4fcdf36d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113575473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.113575473
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1193509854
Short name T781
Test name
Test status
Simulation time 45681885 ps
CPU time 6.36 seconds
Started May 26 02:54:16 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 250476 kb
Host smart-d8f76a6f-d7a2-4708-8996-9f65687d221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193509854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1193509854
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3572215880
Short name T230
Test name
Test status
Simulation time 8438362497 ps
CPU time 80.26 seconds
Started May 26 02:54:15 PM PDT 24
Finished May 26 02:55:37 PM PDT 24
Peak memory 251028 kb
Host smart-074ff7e7-49bb-447e-8c48-1f23a53e0271
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572215880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3572215880
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1434057425
Short name T136
Test name
Test status
Simulation time 41781097573 ps
CPU time 4195.52 seconds
Started May 26 02:54:13 PM PDT 24
Finished May 26 04:04:12 PM PDT 24
Peak memory 889276 kb
Host smart-83311796-63a7-43df-b80c-976b6071d6ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1434057425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1434057425
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3435295775
Short name T324
Test name
Test status
Simulation time 15354221 ps
CPU time 1.13 seconds
Started May 26 02:54:18 PM PDT 24
Finished May 26 02:54:21 PM PDT 24
Peak memory 212600 kb
Host smart-03cddc7b-aa64-4678-a4a9-a0c61dbabcd6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435295775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3435295775
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2041484215
Short name T217
Test name
Test status
Simulation time 14875206 ps
CPU time 1.01 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 209688 kb
Host smart-b6fcec51-ea8a-402d-9041-063d8a78621a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041484215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2041484215
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3340456000
Short name T51
Test name
Test status
Simulation time 243067860 ps
CPU time 10.91 seconds
Started May 26 02:54:14 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 218136 kb
Host smart-82d05f0d-ac6c-4b77-8a9f-0e6cc0458cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340456000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3340456000
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3541589417
Short name T514
Test name
Test status
Simulation time 1758998704 ps
CPU time 19.71 seconds
Started May 26 02:54:17 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 209660 kb
Host smart-435585d4-e392-40b7-a862-4cdc4adeb82f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541589417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3541589417
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2994512880
Short name T260
Test name
Test status
Simulation time 118999809 ps
CPU time 1.9 seconds
Started May 26 02:54:10 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 218124 kb
Host smart-805e05dc-ddef-49a2-abf2-90567a766b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994512880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2994512880
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3153159976
Short name T766
Test name
Test status
Simulation time 816655770 ps
CPU time 16.46 seconds
Started May 26 02:54:18 PM PDT 24
Finished May 26 02:54:37 PM PDT 24
Peak memory 219056 kb
Host smart-9b9b026d-0357-4dc0-8e48-c647b0b504fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153159976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3153159976
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1198082501
Short name T282
Test name
Test status
Simulation time 388131369 ps
CPU time 16.11 seconds
Started May 26 02:54:18 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 218044 kb
Host smart-be79225e-4e26-4c8a-bf07-84f16b2d0420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198082501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1198082501
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3229034714
Short name T679
Test name
Test status
Simulation time 1115641235 ps
CPU time 7.7 seconds
Started May 26 02:54:12 PM PDT 24
Finished May 26 02:54:23 PM PDT 24
Peak memory 218140 kb
Host smart-f9706331-d405-4b9b-8b10-3fb21f6a25eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229034714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3229034714
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3191146361
Short name T62
Test name
Test status
Simulation time 462207457 ps
CPU time 14.83 seconds
Started May 26 02:54:18 PM PDT 24
Finished May 26 02:54:35 PM PDT 24
Peak memory 218172 kb
Host smart-c95f1397-0046-48cd-9089-24e2e3aadd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191146361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3191146361
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3580014929
Short name T481
Test name
Test status
Simulation time 58449612 ps
CPU time 3.05 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 214220 kb
Host smart-d6e233ff-381b-4b51-9cdf-3f7d9599c4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580014929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3580014929
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4234202717
Short name T807
Test name
Test status
Simulation time 475162813 ps
CPU time 28.49 seconds
Started May 26 02:54:14 PM PDT 24
Finished May 26 02:54:45 PM PDT 24
Peak memory 250992 kb
Host smart-3604acd3-5906-4f77-8ad0-057011be35c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234202717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4234202717
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.821053400
Short name T652
Test name
Test status
Simulation time 180297332 ps
CPU time 2.64 seconds
Started May 26 02:54:14 PM PDT 24
Finished May 26 02:54:19 PM PDT 24
Peak memory 218112 kb
Host smart-90f20096-f041-4d50-8113-a2dbdf1426f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821053400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.821053400
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2558529332
Short name T155
Test name
Test status
Simulation time 22416379435 ps
CPU time 189.83 seconds
Started May 26 02:54:14 PM PDT 24
Finished May 26 02:57:26 PM PDT 24
Peak memory 283756 kb
Host smart-37466956-363e-43fb-872b-9d1a0ea82c9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558529332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2558529332
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.499849287
Short name T810
Test name
Test status
Simulation time 12578191 ps
CPU time 1.02 seconds
Started May 26 02:54:13 PM PDT 24
Finished May 26 02:54:17 PM PDT 24
Peak memory 211556 kb
Host smart-e3818208-62fe-4a5d-801d-f3ed6bc2355f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499849287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.499849287
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3619757556
Short name T173
Test name
Test status
Simulation time 51032575 ps
CPU time 1.08 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:29 PM PDT 24
Peak memory 209688 kb
Host smart-dbae852b-9e5e-483b-87d2-ad4d35daaf14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619757556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3619757556
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.582753363
Short name T658
Test name
Test status
Simulation time 221258486 ps
CPU time 9.85 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 218108 kb
Host smart-7185e736-e893-484a-ac6e-63678d2cdb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582753363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.582753363
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2584851901
Short name T820
Test name
Test status
Simulation time 533166610 ps
CPU time 14.02 seconds
Started May 26 02:54:20 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 217368 kb
Host smart-5e97f339-712a-40d9-80c0-219f33b211fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584851901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2584851901
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2025750183
Short name T778
Test name
Test status
Simulation time 81010220 ps
CPU time 2.76 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 218180 kb
Host smart-75299eef-41d0-4305-bd12-383216d01c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025750183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2025750183
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1112734485
Short name T711
Test name
Test status
Simulation time 1725757428 ps
CPU time 15.2 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 218940 kb
Host smart-ec8bb341-2671-410b-bc85-2a32bc05e4ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112734485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1112734485
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1144145340
Short name T365
Test name
Test status
Simulation time 311797070 ps
CPU time 12.2 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:41 PM PDT 24
Peak memory 218060 kb
Host smart-2ee49993-6ba0-460e-a53e-0b502cfa449a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144145340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1144145340
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1759198258
Short name T450
Test name
Test status
Simulation time 483452372 ps
CPU time 10.67 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:37 PM PDT 24
Peak memory 218072 kb
Host smart-25c5ef18-ed47-4cf7-9396-209ade009158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759198258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1759198258
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.697206001
Short name T682
Test name
Test status
Simulation time 1300007404 ps
CPU time 13.59 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:39 PM PDT 24
Peak memory 218176 kb
Host smart-cbe96039-537a-451e-905d-b19b1f4d3d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697206001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.697206001
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.4012442322
Short name T78
Test name
Test status
Simulation time 181382225 ps
CPU time 2.04 seconds
Started May 26 02:54:27 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 213716 kb
Host smart-2b014c68-1056-4048-b273-5514eb0c0aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012442322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.4012442322
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.873621670
Short name T630
Test name
Test status
Simulation time 991029025 ps
CPU time 26.38 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:52 PM PDT 24
Peak memory 251128 kb
Host smart-43c43bc7-de9d-4bd4-813e-bf52f5636482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873621670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.873621670
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1351144148
Short name T280
Test name
Test status
Simulation time 222624558 ps
CPU time 9.06 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:35 PM PDT 24
Peak memory 250996 kb
Host smart-ca93a14e-5d29-4bb6-ad98-955f7722cb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351144148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1351144148
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2465368999
Short name T785
Test name
Test status
Simulation time 972953130 ps
CPU time 18.85 seconds
Started May 26 02:54:18 PM PDT 24
Finished May 26 02:54:39 PM PDT 24
Peak memory 226196 kb
Host smart-cdaf7ab2-2d3e-45a6-8479-f36375091571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465368999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2465368999
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2286400432
Short name T140
Test name
Test status
Simulation time 24581523456 ps
CPU time 231.18 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:58:14 PM PDT 24
Peak memory 284048 kb
Host smart-7d63e9d8-ea65-41c1-84fa-38766f00eb39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2286400432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2286400432
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2559438898
Short name T631
Test name
Test status
Simulation time 11395955 ps
CPU time 0.93 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:23 PM PDT 24
Peak memory 208888 kb
Host smart-3a5a08e2-a679-4343-9cf2-89fa64dbed07
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559438898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2559438898
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.833303318
Short name T235
Test name
Test status
Simulation time 40548538 ps
CPU time 0.87 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 209628 kb
Host smart-20318421-58f2-44b0-a77f-f260d598ec50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833303318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.833303318
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.927699509
Short name T814
Test name
Test status
Simulation time 470199280 ps
CPU time 15.97 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:42 PM PDT 24
Peak memory 217996 kb
Host smart-1bc65cd7-7c5c-4aa6-b6e3-9c1b704be1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927699509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.927699509
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2695919199
Short name T184
Test name
Test status
Simulation time 2819133232 ps
CPU time 18.21 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:41 PM PDT 24
Peak memory 209636 kb
Host smart-b293c9c5-f4fe-4490-ad8f-d6a20225bbe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695919199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2695919199
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2539043026
Short name T341
Test name
Test status
Simulation time 643721558 ps
CPU time 2.35 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:28 PM PDT 24
Peak memory 218048 kb
Host smart-f2c50f43-f782-45e5-b842-b7b298dcdd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539043026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2539043026
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2700008783
Short name T311
Test name
Test status
Simulation time 2841826234 ps
CPU time 29.44 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:55 PM PDT 24
Peak memory 218080 kb
Host smart-e892c915-8a68-4469-b384-fa04d66c6910
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700008783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2700008783
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3078899290
Short name T466
Test name
Test status
Simulation time 217055766 ps
CPU time 9.8 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:35 PM PDT 24
Peak memory 218116 kb
Host smart-defb58cc-4f20-4ed2-9039-697f972c5f16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078899290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3078899290
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.86016218
Short name T628
Test name
Test status
Simulation time 608312162 ps
CPU time 13.61 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 218080 kb
Host smart-4286f06d-50c3-45f6-b782-f4e0dda9fcea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86016218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.86016218
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2815116870
Short name T448
Test name
Test status
Simulation time 238565979 ps
CPU time 9.26 seconds
Started May 26 02:54:20 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 218156 kb
Host smart-86d34d35-26f6-4408-8c29-e0abac6aebfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815116870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2815116870
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.217039959
Short name T757
Test name
Test status
Simulation time 47561804 ps
CPU time 2.9 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:29 PM PDT 24
Peak memory 214712 kb
Host smart-ea4926a9-7641-449f-9c24-b3a4fabed553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217039959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.217039959
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3226392008
Short name T719
Test name
Test status
Simulation time 1254079498 ps
CPU time 30.02 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:58 PM PDT 24
Peak memory 251076 kb
Host smart-eea0f82e-e1be-49ad-a5a4-6a468b5ace43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226392008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3226392008
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1071583545
Short name T473
Test name
Test status
Simulation time 147669323 ps
CPU time 6.81 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 248640 kb
Host smart-40096056-9b50-4971-8270-51ecb17165b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071583545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1071583545
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4149383055
Short name T467
Test name
Test status
Simulation time 5651100282 ps
CPU time 30.27 seconds
Started May 26 02:54:27 PM PDT 24
Finished May 26 02:54:59 PM PDT 24
Peak memory 251104 kb
Host smart-c88e42b4-540b-4005-a568-b82e72814a2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149383055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4149383055
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1178957484
Short name T47
Test name
Test status
Simulation time 16982899 ps
CPU time 1.17 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:26 PM PDT 24
Peak memory 211668 kb
Host smart-c8fd288e-ec7d-4a4f-bc68-230652b6f1d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178957484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1178957484
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1412545570
Short name T214
Test name
Test status
Simulation time 25774327 ps
CPU time 0.83 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 209568 kb
Host smart-282aec4c-5117-4661-99c5-a80b4f4a8823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412545570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1412545570
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1010800241
Short name T548
Test name
Test status
Simulation time 748938420 ps
CPU time 11.47 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 218024 kb
Host smart-b20dfd99-4333-4944-8d21-ba9671a965b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010800241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1010800241
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1409869483
Short name T791
Test name
Test status
Simulation time 138722804 ps
CPU time 3.76 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 216996 kb
Host smart-0cb2ecfc-10a9-4829-a915-93d56d8ed972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409869483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1409869483
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3038950850
Short name T772
Test name
Test status
Simulation time 58690099 ps
CPU time 2.14 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 218104 kb
Host smart-32fb71c1-f561-4b43-aa69-3ea122494686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038950850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3038950850
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.441663455
Short name T223
Test name
Test status
Simulation time 1021562599 ps
CPU time 10.28 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 226352 kb
Host smart-c18dcfe5-52e1-498b-a5cf-55f2eee0ecc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441663455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.441663455
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.89552002
Short name T387
Test name
Test status
Simulation time 1194287802 ps
CPU time 19.71 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:44 PM PDT 24
Peak memory 218132 kb
Host smart-85e7a415-98e8-418a-9536-626281683fb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89552002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_dig
est.89552002
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3751390904
Short name T770
Test name
Test status
Simulation time 432284629 ps
CPU time 8.51 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 218036 kb
Host smart-ef43840b-13c1-4de1-bb85-349d05f75384
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751390904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3751390904
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2177681343
Short name T411
Test name
Test status
Simulation time 3592290631 ps
CPU time 13.23 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 218236 kb
Host smart-4b8a544a-69ff-4b75-a277-e5128b37124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177681343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2177681343
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.670861543
Short name T849
Test name
Test status
Simulation time 94635327 ps
CPU time 2.24 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 214280 kb
Host smart-8666f499-d3e4-49b2-9a01-6733ff27127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670861543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.670861543
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.220272711
Short name T765
Test name
Test status
Simulation time 1224764840 ps
CPU time 27.32 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 250992 kb
Host smart-c6d56bbb-85a7-45b8-875c-d374a6dd5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220272711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.220272711
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3824589793
Short name T876
Test name
Test status
Simulation time 87927584 ps
CPU time 7.73 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:32 PM PDT 24
Peak memory 251004 kb
Host smart-22ad9cab-50c3-467a-a746-845296c73b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824589793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3824589793
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.581844824
Short name T337
Test name
Test status
Simulation time 16591681430 ps
CPU time 93.2 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:55:57 PM PDT 24
Peak memory 282804 kb
Host smart-521599b6-ad58-4bc1-9a27-5212727cb6e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581844824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.581844824
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1617637216
Short name T135
Test name
Test status
Simulation time 54111611956 ps
CPU time 572.42 seconds
Started May 26 02:54:20 PM PDT 24
Finished May 26 03:03:54 PM PDT 24
Peak memory 496960 kb
Host smart-8609b904-790b-4b88-a074-4f2980e749e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1617637216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1617637216
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4175464841
Short name T451
Test name
Test status
Simulation time 17597928 ps
CPU time 0.83 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 208812 kb
Host smart-0ed1b7d8-bd61-492f-b4c7-1c03472e1194
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175464841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4175464841
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2376890927
Short name T224
Test name
Test status
Simulation time 24564825 ps
CPU time 1.14 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:54:27 PM PDT 24
Peak memory 209692 kb
Host smart-ebf08d95-a326-4900-ab47-54c73dabbd6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376890927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2376890927
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3035068371
Short name T147
Test name
Test status
Simulation time 1408376249 ps
CPU time 14.05 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:39 PM PDT 24
Peak memory 218180 kb
Host smart-8ae4abbf-96b5-477f-9564-6d3f7756824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035068371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3035068371
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1875451665
Short name T29
Test name
Test status
Simulation time 684493758 ps
CPU time 8.65 seconds
Started May 26 02:54:19 PM PDT 24
Finished May 26 02:54:29 PM PDT 24
Peak memory 209648 kb
Host smart-68d0d23f-463e-4c30-a503-056ec40c106c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875451665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1875451665
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3125503965
Short name T444
Test name
Test status
Simulation time 63317418 ps
CPU time 3.48 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 218044 kb
Host smart-8b5a14fb-3c17-43e5-9522-2d27d52ebd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125503965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3125503965
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1850265360
Short name T431
Test name
Test status
Simulation time 720550561 ps
CPU time 10.94 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:39 PM PDT 24
Peak memory 218264 kb
Host smart-982c19fa-9193-45d1-8dac-ae8682c5c9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850265360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1850265360
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3007354352
Short name T621
Test name
Test status
Simulation time 515135417 ps
CPU time 18.25 seconds
Started May 26 02:54:19 PM PDT 24
Finished May 26 02:54:39 PM PDT 24
Peak memory 218056 kb
Host smart-0a974aa0-db8c-41f6-9245-46b4a3741bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007354352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3007354352
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2690193880
Short name T858
Test name
Test status
Simulation time 419075049 ps
CPU time 8.66 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:35 PM PDT 24
Peak memory 218072 kb
Host smart-575e456a-23db-4944-9b7e-dcfafc8bd370
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690193880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2690193880
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2384226438
Short name T219
Test name
Test status
Simulation time 736960619 ps
CPU time 8.89 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:39 PM PDT 24
Peak memory 218208 kb
Host smart-aaceb1cc-85c3-4e45-b160-2d6fe5748a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384226438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2384226438
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3540709562
Short name T66
Test name
Test status
Simulation time 43931290 ps
CPU time 2.91 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:25 PM PDT 24
Peak memory 214744 kb
Host smart-a731e5ea-9066-43bb-a5f8-fd844d956de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540709562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3540709562
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1899136665
Short name T334
Test name
Test status
Simulation time 1327629838 ps
CPU time 27.27 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:53 PM PDT 24
Peak memory 251020 kb
Host smart-017170a3-f3ff-4ef6-ac5f-b72da4de4087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899136665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1899136665
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.4042895754
Short name T497
Test name
Test status
Simulation time 68873953 ps
CPU time 6.81 seconds
Started May 26 02:54:22 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 246652 kb
Host smart-b4ef6350-19d2-4616-8c03-8d963ecc2c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042895754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4042895754
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.926531070
Short name T320
Test name
Test status
Simulation time 7776311832 ps
CPU time 147.66 seconds
Started May 26 02:54:23 PM PDT 24
Finished May 26 02:56:52 PM PDT 24
Peak memory 283548 kb
Host smart-9564068d-9e42-4c03-aafb-9a0992869f0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926531070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.926531070
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1735323655
Short name T489
Test name
Test status
Simulation time 20205017 ps
CPU time 0.83 seconds
Started May 26 02:54:21 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 208640 kb
Host smart-1255635d-c11c-43fc-93dd-c00139c86716
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735323655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1735323655
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3483847682
Short name T646
Test name
Test status
Simulation time 57425278 ps
CPU time 0.86 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 209584 kb
Host smart-b3de7c07-8393-44c4-98f0-df850da5bd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483847682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3483847682
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.82025311
Short name T569
Test name
Test status
Simulation time 20935852 ps
CPU time 0.82 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:09 PM PDT 24
Peak memory 209528 kb
Host smart-e686097e-a981-47a3-b6a3-ee6f82f90167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82025311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.82025311
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1148266347
Short name T346
Test name
Test status
Simulation time 2044108914 ps
CPU time 14.07 seconds
Started May 26 02:52:59 PM PDT 24
Finished May 26 02:53:14 PM PDT 24
Peak memory 217948 kb
Host smart-378f81d8-f26c-405c-ae20-dd2d13da0e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148266347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1148266347
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1696650718
Short name T319
Test name
Test status
Simulation time 138184879 ps
CPU time 1.53 seconds
Started May 26 02:53:04 PM PDT 24
Finished May 26 02:53:08 PM PDT 24
Peak memory 209644 kb
Host smart-3eacd72a-3073-413c-aa8d-f94d22bdbb18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696650718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1696650718
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3984799889
Short name T438
Test name
Test status
Simulation time 5794074299 ps
CPU time 42.86 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:53 PM PDT 24
Peak memory 219060 kb
Host smart-af4d3122-3b82-4c7f-b4a4-c57594b20068
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984799889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3984799889
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2489326330
Short name T564
Test name
Test status
Simulation time 1356332370 ps
CPU time 8.06 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:19 PM PDT 24
Peak memory 217888 kb
Host smart-f12240be-8090-422d-a769-625760f675c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489326330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
489326330
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4162141586
Short name T579
Test name
Test status
Simulation time 260334768 ps
CPU time 7.57 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:17 PM PDT 24
Peak memory 217980 kb
Host smart-102e2447-482c-47f0-ae98-d6b296317aa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162141586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4162141586
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.447447913
Short name T24
Test name
Test status
Simulation time 782671040 ps
CPU time 23.78 seconds
Started May 26 02:53:11 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 213272 kb
Host smart-e553530d-9705-4ff3-ac45-43e1cedc49dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447447913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.447447913
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2695612416
Short name T406
Test name
Test status
Simulation time 426313204 ps
CPU time 7.2 seconds
Started May 26 02:53:02 PM PDT 24
Finished May 26 02:53:11 PM PDT 24
Peak memory 213620 kb
Host smart-c533775b-b3e3-4b9c-a6fa-aaed1f9cd002
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695612416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2695612416
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2403403751
Short name T490
Test name
Test status
Simulation time 38910857556 ps
CPU time 88.07 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 283764 kb
Host smart-b4390e16-6e7a-4303-aff9-3f9c99802163
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403403751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2403403751
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4103676448
Short name T483
Test name
Test status
Simulation time 1741454280 ps
CPU time 17.39 seconds
Started May 26 02:52:58 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 250508 kb
Host smart-443aba9c-320c-4a88-a018-f78e32b8c81e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103676448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4103676448
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3623454568
Short name T413
Test name
Test status
Simulation time 266523548 ps
CPU time 3.5 seconds
Started May 26 02:53:02 PM PDT 24
Finished May 26 02:53:07 PM PDT 24
Peak memory 218124 kb
Host smart-a4c8d080-1ad5-44fe-8e8a-b63a7c18793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623454568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3623454568
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1488617312
Short name T254
Test name
Test status
Simulation time 342179663 ps
CPU time 8.47 seconds
Started May 26 02:52:55 PM PDT 24
Finished May 26 02:53:04 PM PDT 24
Peak memory 213992 kb
Host smart-a946e831-fe2c-4c0c-a2f6-a4ce5397ae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488617312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1488617312
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3449963678
Short name T74
Test name
Test status
Simulation time 114859143 ps
CPU time 22.49 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:30 PM PDT 24
Peak memory 267984 kb
Host smart-f89c9e5f-97bf-40f8-862c-eac261c18ce3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449963678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3449963678
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2649175704
Short name T825
Test name
Test status
Simulation time 756666619 ps
CPU time 15.83 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 218132 kb
Host smart-cb18e9da-5345-48cc-90ae-6fffdc2907bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649175704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2649175704
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1107477736
Short name T161
Test name
Test status
Simulation time 3441777131 ps
CPU time 16.92 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:30 PM PDT 24
Peak memory 219008 kb
Host smart-d6441bb5-fe38-4701-a1ea-cd41ef4957f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107477736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1107477736
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.916902611
Short name T870
Test name
Test status
Simulation time 744435274 ps
CPU time 8.55 seconds
Started May 26 02:53:11 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 218064 kb
Host smart-7d219f82-ae88-4d71-befb-1973aab5ba4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916902611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.916902611
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.756113095
Short name T390
Test name
Test status
Simulation time 458962643 ps
CPU time 6.77 seconds
Started May 26 02:53:11 PM PDT 24
Finished May 26 02:53:21 PM PDT 24
Peak memory 218132 kb
Host smart-a1043dfb-6e98-40b3-9cf9-df591e9f2418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756113095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.756113095
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3097654606
Short name T73
Test name
Test status
Simulation time 28113484 ps
CPU time 1.94 seconds
Started May 26 02:52:58 PM PDT 24
Finished May 26 02:53:01 PM PDT 24
Peak memory 213932 kb
Host smart-146c59ee-0adb-45f6-8622-dec4ec9082c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097654606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3097654606
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2034540907
Short name T534
Test name
Test status
Simulation time 326974342 ps
CPU time 24.05 seconds
Started May 26 02:53:00 PM PDT 24
Finished May 26 02:53:25 PM PDT 24
Peak memory 250976 kb
Host smart-1cc32235-9fb2-4a92-b18a-4319ead42640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034540907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2034540907
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3706192228
Short name T767
Test name
Test status
Simulation time 337500719 ps
CPU time 8.01 seconds
Started May 26 02:52:59 PM PDT 24
Finished May 26 02:53:09 PM PDT 24
Peak memory 250996 kb
Host smart-de2689d7-d28a-4a94-a4e0-32a63231141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706192228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3706192228
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2383608132
Short name T727
Test name
Test status
Simulation time 25405813903 ps
CPU time 82.34 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:54:30 PM PDT 24
Peak memory 226260 kb
Host smart-198d58ef-4225-408e-b372-c5dcfcf320a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383608132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2383608132
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1362479676
Short name T426
Test name
Test status
Simulation time 25675723 ps
CPU time 1.14 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:10 PM PDT 24
Peak memory 211636 kb
Host smart-417c4cf1-9a7e-42ee-835c-31afc72d9b97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362479676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1362479676
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.458150542
Short name T151
Test name
Test status
Simulation time 33131032 ps
CPU time 1.1 seconds
Started May 26 02:54:42 PM PDT 24
Finished May 26 02:54:44 PM PDT 24
Peak memory 209652 kb
Host smart-df517b87-01a0-4d68-b2c8-70cca054eb74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458150542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.458150542
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3251243914
Short name T633
Test name
Test status
Simulation time 301188155 ps
CPU time 9.19 seconds
Started May 26 02:54:36 PM PDT 24
Finished May 26 02:54:46 PM PDT 24
Peak memory 218104 kb
Host smart-48c91959-20ad-484a-bebd-5df1b79d15ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251243914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3251243914
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.401009917
Short name T414
Test name
Test status
Simulation time 106849068 ps
CPU time 2.03 seconds
Started May 26 02:54:26 PM PDT 24
Finished May 26 02:54:30 PM PDT 24
Peak memory 216984 kb
Host smart-17354937-acfa-4a92-be97-097181c75165
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401009917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.401009917
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.4045553469
Short name T733
Test name
Test status
Simulation time 114225164 ps
CPU time 2.87 seconds
Started May 26 02:54:36 PM PDT 24
Finished May 26 02:54:41 PM PDT 24
Peak memory 218112 kb
Host smart-cae25cad-55d9-4222-8c81-dd6f456b1fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045553469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.4045553469
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2635733924
Short name T179
Test name
Test status
Simulation time 1763361529 ps
CPU time 15.36 seconds
Started May 26 02:54:28 PM PDT 24
Finished May 26 02:54:45 PM PDT 24
Peak memory 226204 kb
Host smart-b54354b4-3a07-4cbf-aca9-9f02371266cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635733924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2635733924
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3539635282
Short name T350
Test name
Test status
Simulation time 273644744 ps
CPU time 10.53 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 218092 kb
Host smart-34805053-fbd5-41fa-84d4-2392f092e46c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539635282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3539635282
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1894465052
Short name T485
Test name
Test status
Simulation time 202136854 ps
CPU time 6.14 seconds
Started May 26 02:54:28 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 218068 kb
Host smart-f3ac05c4-c666-4187-b6fc-eafb872d76b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894465052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1894465052
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.381858765
Short name T845
Test name
Test status
Simulation time 3173373009 ps
CPU time 13.7 seconds
Started May 26 02:54:42 PM PDT 24
Finished May 26 02:54:57 PM PDT 24
Peak memory 218204 kb
Host smart-0a1f74f4-f434-4718-b9d4-2a02dee87055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381858765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.381858765
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1224005960
Short name T313
Test name
Test status
Simulation time 23327978 ps
CPU time 1.91 seconds
Started May 26 02:54:20 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 214052 kb
Host smart-d8643fb5-1380-4614-a69f-7a4ace99463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224005960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1224005960
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3388970668
Short name T715
Test name
Test status
Simulation time 1682408553 ps
CPU time 21.08 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:47 PM PDT 24
Peak memory 251128 kb
Host smart-8bb25685-83f0-4a60-a8c4-2185f59e7739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388970668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3388970668
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.564522782
Short name T688
Test name
Test status
Simulation time 326404468 ps
CPU time 7.5 seconds
Started May 26 02:54:26 PM PDT 24
Finished May 26 02:54:36 PM PDT 24
Peak memory 247080 kb
Host smart-4edbfb55-84cc-46b5-a049-d8682c1cf60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564522782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.564522782
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.593263006
Short name T708
Test name
Test status
Simulation time 3353660697 ps
CPU time 127.86 seconds
Started May 26 02:54:26 PM PDT 24
Finished May 26 02:56:36 PM PDT 24
Peak memory 283864 kb
Host smart-7403c733-b901-4cae-be1f-1b019c4a1269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593263006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.593263006
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3649608815
Short name T134
Test name
Test status
Simulation time 163110554172 ps
CPU time 464.23 seconds
Started May 26 02:54:37 PM PDT 24
Finished May 26 03:02:23 PM PDT 24
Peak memory 279212 kb
Host smart-f18abb26-6f0d-480a-9423-8f9e8ceaea19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3649608815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3649608815
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4072868819
Short name T447
Test name
Test status
Simulation time 22450415 ps
CPU time 1.02 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:29 PM PDT 24
Peak memory 211672 kb
Host smart-2e547dee-ea14-4216-80ab-c47068e341a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072868819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.4072868819
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3378348879
Short name T830
Test name
Test status
Simulation time 75286956 ps
CPU time 0.86 seconds
Started May 26 02:54:48 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 209720 kb
Host smart-b2e18c60-9f85-41b3-8d71-7b8b39b462c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378348879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3378348879
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2815602600
Short name T768
Test name
Test status
Simulation time 1260634666 ps
CPU time 14.03 seconds
Started May 26 02:54:47 PM PDT 24
Finished May 26 02:55:03 PM PDT 24
Peak memory 218076 kb
Host smart-d8c325ba-7005-4b67-93d6-3d11cad13618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815602600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2815602600
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.628477208
Short name T7
Test name
Test status
Simulation time 93859458 ps
CPU time 1.88 seconds
Started May 26 02:54:27 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 209708 kb
Host smart-f114eb72-274d-4e7a-bd40-fe8fd0320dd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628477208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.628477208
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.362906297
Short name T381
Test name
Test status
Simulation time 107278813 ps
CPU time 2 seconds
Started May 26 02:54:43 PM PDT 24
Finished May 26 02:54:45 PM PDT 24
Peak memory 218124 kb
Host smart-90eecd50-c283-4bbb-8214-5b9d37e41fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362906297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.362906297
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2555567421
Short name T52
Test name
Test status
Simulation time 669116630 ps
CPU time 15.24 seconds
Started May 26 02:54:31 PM PDT 24
Finished May 26 02:54:47 PM PDT 24
Peak memory 219304 kb
Host smart-29d19aa7-da74-46e0-9d5f-f24e9343070b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555567421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2555567421
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2030654204
Short name T388
Test name
Test status
Simulation time 290083112 ps
CPU time 13.76 seconds
Started May 26 02:54:26 PM PDT 24
Finished May 26 02:54:42 PM PDT 24
Peak memory 217960 kb
Host smart-b0e7173a-6ba9-42e7-a4f3-9c8d4115009e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030654204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2030654204
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3312746566
Short name T616
Test name
Test status
Simulation time 622590423 ps
CPU time 9.46 seconds
Started May 26 02:54:30 PM PDT 24
Finished May 26 02:54:40 PM PDT 24
Peak memory 218052 kb
Host smart-40780b4b-1d43-423a-93f2-813165118052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312746566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3312746566
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2588134348
Short name T39
Test name
Test status
Simulation time 233417844 ps
CPU time 6.99 seconds
Started May 26 02:54:24 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 218184 kb
Host smart-884f4503-c82f-4f58-a8df-e544ef9ceee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588134348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2588134348
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.4206935908
Short name T345
Test name
Test status
Simulation time 16858308 ps
CPU time 1.54 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:29 PM PDT 24
Peak memory 213564 kb
Host smart-cbf8b958-10ef-4598-90ba-c588613fd374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206935908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.4206935908
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.266398116
Short name T583
Test name
Test status
Simulation time 1581382767 ps
CPU time 31.51 seconds
Started May 26 02:54:27 PM PDT 24
Finished May 26 02:55:00 PM PDT 24
Peak memory 251048 kb
Host smart-8bba3577-08f1-4dcf-b447-c185bbb86dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266398116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.266398116
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4127632137
Short name T576
Test name
Test status
Simulation time 862445274 ps
CPU time 6.49 seconds
Started May 26 02:54:26 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 248676 kb
Host smart-e693e33b-5df7-4f6f-aaf9-184942522cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127632137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4127632137
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1249761204
Short name T65
Test name
Test status
Simulation time 13838413088 ps
CPU time 197.65 seconds
Started May 26 02:54:33 PM PDT 24
Finished May 26 02:57:51 PM PDT 24
Peak memory 283832 kb
Host smart-a5f13457-d965-4b06-a143-a2165ea5495a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249761204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1249761204
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4124193732
Short name T575
Test name
Test status
Simulation time 16858302 ps
CPU time 1.12 seconds
Started May 26 02:54:29 PM PDT 24
Finished May 26 02:54:32 PM PDT 24
Peak memory 212712 kb
Host smart-d2434d5f-6b84-4461-9cfe-684c5997e771
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124193732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4124193732
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3523511363
Short name T797
Test name
Test status
Simulation time 53836258 ps
CPU time 1.29 seconds
Started May 26 02:54:38 PM PDT 24
Finished May 26 02:54:40 PM PDT 24
Peak memory 209688 kb
Host smart-f1f8c78f-32a8-4faf-8fb2-0d64bd5080d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523511363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3523511363
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2553731962
Short name T238
Test name
Test status
Simulation time 1270463056 ps
CPU time 16.08 seconds
Started May 26 02:54:41 PM PDT 24
Finished May 26 02:54:59 PM PDT 24
Peak memory 218088 kb
Host smart-ca13487e-6af2-4e2e-83e2-c7b192a88072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553731962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2553731962
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.207540820
Short name T462
Test name
Test status
Simulation time 1604654993 ps
CPU time 8.36 seconds
Started May 26 02:54:41 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 217208 kb
Host smart-cb60fbec-2d95-4c92-9c46-a8e81fbbacbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207540820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.207540820
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3043620920
Short name T318
Test name
Test status
Simulation time 25544780 ps
CPU time 1.8 seconds
Started May 26 02:54:28 PM PDT 24
Finished May 26 02:54:31 PM PDT 24
Peak memory 218092 kb
Host smart-0035c267-4043-4978-bc64-94e1d95262c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043620920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3043620920
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1623745310
Short name T859
Test name
Test status
Simulation time 1259974468 ps
CPU time 14.22 seconds
Started May 26 02:54:41 PM PDT 24
Finished May 26 02:54:57 PM PDT 24
Peak memory 225716 kb
Host smart-1c52a211-ff11-4442-beb4-f6da78d606da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623745310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1623745310
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.615587677
Short name T782
Test name
Test status
Simulation time 567947210 ps
CPU time 11.23 seconds
Started May 26 02:54:44 PM PDT 24
Finished May 26 02:54:56 PM PDT 24
Peak memory 217960 kb
Host smart-9ebc2713-737f-4cb7-85f0-3bc9370c22e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615587677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.615587677
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1015783195
Short name T609
Test name
Test status
Simulation time 611807214 ps
CPU time 11.03 seconds
Started May 26 02:54:36 PM PDT 24
Finished May 26 02:54:49 PM PDT 24
Peak memory 218068 kb
Host smart-c478560e-8c23-4f0c-b621-c646fec58a6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015783195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1015783195
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.4023383195
Short name T625
Test name
Test status
Simulation time 1301087030 ps
CPU time 9.86 seconds
Started May 26 02:54:26 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 218180 kb
Host smart-b5aa71ef-05a3-4be0-b8fc-ceb45d32611d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023383195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.4023383195
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.503854604
Short name T1
Test name
Test status
Simulation time 78881706 ps
CPU time 3.07 seconds
Started May 26 02:54:28 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 217944 kb
Host smart-35e030c3-55ca-4f59-8938-0ec7e5052aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503854604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.503854604
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3900738671
Short name T495
Test name
Test status
Simulation time 842579943 ps
CPU time 21.14 seconds
Started May 26 02:54:45 PM PDT 24
Finished May 26 02:55:07 PM PDT 24
Peak memory 251084 kb
Host smart-df25df8b-2d31-4cff-8b22-0dde2863da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900738671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3900738671
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3676462982
Short name T436
Test name
Test status
Simulation time 120929110 ps
CPU time 9.27 seconds
Started May 26 02:54:27 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 243804 kb
Host smart-e1a51e43-fdcc-4a37-a012-a2b1c9ec7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676462982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3676462982
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.82862952
Short name T517
Test name
Test status
Simulation time 18968160890 ps
CPU time 86.82 seconds
Started May 26 02:54:37 PM PDT 24
Finished May 26 02:56:05 PM PDT 24
Peak memory 277404 kb
Host smart-2ffeec5e-ea3b-4832-bf45-ff9c69e8b5ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82862952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.lc_ctrl_stress_all.82862952
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3544426506
Short name T558
Test name
Test status
Simulation time 44840231 ps
CPU time 0.96 seconds
Started May 26 02:54:32 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 212768 kb
Host smart-e82ae77b-0281-4761-9846-984bcccda16a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544426506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3544426506
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.470199185
Short name T691
Test name
Test status
Simulation time 36285215 ps
CPU time 0.89 seconds
Started May 26 02:54:51 PM PDT 24
Finished May 26 02:54:55 PM PDT 24
Peak memory 209700 kb
Host smart-497ee305-2964-42eb-879c-18853a0f7b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470199185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.470199185
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2793602067
Short name T218
Test name
Test status
Simulation time 490655511 ps
CPU time 14.39 seconds
Started May 26 02:54:25 PM PDT 24
Finished May 26 02:54:42 PM PDT 24
Peak memory 218104 kb
Host smart-c19267ec-89ec-434f-ac20-68d64d44bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793602067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2793602067
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1295072893
Short name T26
Test name
Test status
Simulation time 350688259 ps
CPU time 8.58 seconds
Started May 26 02:54:41 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 209592 kb
Host smart-72248f5a-0a8b-4c96-b800-177d2a90fda7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295072893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1295072893
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1909702258
Short name T526
Test name
Test status
Simulation time 756683532 ps
CPU time 2.82 seconds
Started May 26 02:54:37 PM PDT 24
Finished May 26 02:54:41 PM PDT 24
Peak memory 218092 kb
Host smart-3180bb37-44f1-448f-8152-5a440940848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909702258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1909702258
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.548014342
Short name T851
Test name
Test status
Simulation time 1121777522 ps
CPU time 20.09 seconds
Started May 26 02:54:48 PM PDT 24
Finished May 26 02:55:11 PM PDT 24
Peak memory 218108 kb
Host smart-49ba7faa-fefc-4364-a687-e0b6ce076819
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548014342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.548014342
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4254430848
Short name T251
Test name
Test status
Simulation time 1041801179 ps
CPU time 8.65 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:55:00 PM PDT 24
Peak memory 218060 kb
Host smart-aa620737-89db-456c-b29e-333e82511c01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254430848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.4254430848
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3675366898
Short name T491
Test name
Test status
Simulation time 264460526 ps
CPU time 10.02 seconds
Started May 26 02:54:47 PM PDT 24
Finished May 26 02:55:00 PM PDT 24
Peak memory 218144 kb
Host smart-f6932195-9245-4d84-b4ab-ea74896051e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675366898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3675366898
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3473694981
Short name T408
Test name
Test status
Simulation time 544019134 ps
CPU time 9.94 seconds
Started May 26 02:54:40 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 218200 kb
Host smart-4f9d4141-aa85-40a8-8fce-3ac160d17961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473694981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3473694981
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1442286600
Short name T422
Test name
Test status
Simulation time 140992447 ps
CPU time 1.85 seconds
Started May 26 02:54:26 PM PDT 24
Finished May 26 02:54:30 PM PDT 24
Peak memory 217816 kb
Host smart-724ef46a-81d5-4978-9d6f-1347595d52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442286600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1442286600
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.269259336
Short name T266
Test name
Test status
Simulation time 1117512383 ps
CPU time 24.35 seconds
Started May 26 02:54:41 PM PDT 24
Finished May 26 02:55:07 PM PDT 24
Peak memory 251016 kb
Host smart-2ed83259-aec9-45d2-af66-0fcb2a1811e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269259336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.269259336
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1527819796
Short name T221
Test name
Test status
Simulation time 270120279 ps
CPU time 6.81 seconds
Started May 26 02:54:43 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 245400 kb
Host smart-71db46ab-757b-4f6b-b582-10d660606708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527819796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1527819796
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2549627965
Short name T53
Test name
Test status
Simulation time 23832950081 ps
CPU time 226.07 seconds
Started May 26 02:54:40 PM PDT 24
Finished May 26 02:58:27 PM PDT 24
Peak memory 270592 kb
Host smart-cfbdfbbd-7953-4a1a-88b9-146f728b106e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549627965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2549627965
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1993428190
Short name T316
Test name
Test status
Simulation time 41542997 ps
CPU time 1.01 seconds
Started May 26 02:54:31 PM PDT 24
Finished May 26 02:54:33 PM PDT 24
Peak memory 211612 kb
Host smart-1c11d59a-9beb-402d-81e2-a36d2c630c4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993428190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1993428190
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1208932306
Short name T549
Test name
Test status
Simulation time 22101807 ps
CPU time 0.97 seconds
Started May 26 02:54:35 PM PDT 24
Finished May 26 02:54:38 PM PDT 24
Peak memory 209640 kb
Host smart-d92f06d3-1b94-4689-8f3e-dcdfd38bc929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208932306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1208932306
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.421339301
Short name T701
Test name
Test status
Simulation time 706643624 ps
CPU time 29.56 seconds
Started May 26 02:54:40 PM PDT 24
Finished May 26 02:55:10 PM PDT 24
Peak memory 218088 kb
Host smart-819cded6-56b9-4007-8bb2-dbaac35fd468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421339301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.421339301
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1039978843
Short name T808
Test name
Test status
Simulation time 675234381 ps
CPU time 17.17 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:55:09 PM PDT 24
Peak memory 209648 kb
Host smart-26699734-0214-4cde-ae53-c7171a59d407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039978843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1039978843
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1480029080
Short name T556
Test name
Test status
Simulation time 875099306 ps
CPU time 3.93 seconds
Started May 26 02:54:39 PM PDT 24
Finished May 26 02:54:44 PM PDT 24
Peak memory 218104 kb
Host smart-547116c2-8a39-422e-9178-d7fabc4081ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480029080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1480029080
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3694404986
Short name T300
Test name
Test status
Simulation time 226048622 ps
CPU time 11.36 seconds
Started May 26 02:54:46 PM PDT 24
Finished May 26 02:54:59 PM PDT 24
Peak memory 218068 kb
Host smart-54f98869-4940-4e53-bd9e-dd959926f628
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694404986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3694404986
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2169837181
Short name T829
Test name
Test status
Simulation time 1822136791 ps
CPU time 14.21 seconds
Started May 26 02:54:35 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 218036 kb
Host smart-302f44bc-9ce6-4ccd-ae7a-7603ad677658
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169837181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2169837181
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1081568178
Short name T537
Test name
Test status
Simulation time 388375006 ps
CPU time 14.48 seconds
Started May 26 02:54:48 PM PDT 24
Finished May 26 02:55:05 PM PDT 24
Peak memory 218144 kb
Host smart-139e4a8e-63c4-4c0e-87e7-8fa066fdd9b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081568178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1081568178
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2972616630
Short name T339
Test name
Test status
Simulation time 432409047 ps
CPU time 7.92 seconds
Started May 26 02:54:40 PM PDT 24
Finished May 26 02:54:50 PM PDT 24
Peak memory 218180 kb
Host smart-985dbe91-c301-4d77-b832-9eb9fc27ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972616630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2972616630
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.674392364
Short name T457
Test name
Test status
Simulation time 90747227 ps
CPU time 5.35 seconds
Started May 26 02:54:39 PM PDT 24
Finished May 26 02:54:45 PM PDT 24
Peak memory 217748 kb
Host smart-cbc2885c-377b-4768-9ccc-c8685dd1ff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674392364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.674392364
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1744261970
Short name T398
Test name
Test status
Simulation time 288766212 ps
CPU time 23.96 seconds
Started May 26 02:54:42 PM PDT 24
Finished May 26 02:55:07 PM PDT 24
Peak memory 250996 kb
Host smart-53280592-a3b0-40d1-9a56-2cf376c4fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744261970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1744261970
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3461650208
Short name T283
Test name
Test status
Simulation time 146055056 ps
CPU time 8.63 seconds
Started May 26 02:54:35 PM PDT 24
Finished May 26 02:54:45 PM PDT 24
Peak memory 251052 kb
Host smart-4f69127c-3833-4cbd-b821-35dfdfeaea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461650208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3461650208
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2691656329
Short name T565
Test name
Test status
Simulation time 12901951 ps
CPU time 1 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:54:53 PM PDT 24
Peak memory 208704 kb
Host smart-509403f5-3f9b-4260-8950-c9cd60163f4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691656329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2691656329
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2444278964
Short name T307
Test name
Test status
Simulation time 293991264 ps
CPU time 1.43 seconds
Started May 26 02:54:47 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 209692 kb
Host smart-f48a7fe7-758a-47d1-a928-01f79d5f2e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444278964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2444278964
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2344589635
Short name T33
Test name
Test status
Simulation time 474506295 ps
CPU time 13.54 seconds
Started May 26 02:54:45 PM PDT 24
Finished May 26 02:55:01 PM PDT 24
Peak memory 218120 kb
Host smart-d07ab88f-8363-423a-8d17-b962aeb7a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344589635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2344589635
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.556496253
Short name T540
Test name
Test status
Simulation time 2720192167 ps
CPU time 10.07 seconds
Started May 26 02:54:39 PM PDT 24
Finished May 26 02:54:50 PM PDT 24
Peak memory 209692 kb
Host smart-79d68d6f-0627-4771-a316-5ff20e937525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556496253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.556496253
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2539034904
Short name T512
Test name
Test status
Simulation time 63164943 ps
CPU time 1.84 seconds
Started May 26 02:54:39 PM PDT 24
Finished May 26 02:54:42 PM PDT 24
Peak memory 218164 kb
Host smart-4136b6a6-47e6-4d2e-a109-d03172b24dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539034904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2539034904
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1593297085
Short name T729
Test name
Test status
Simulation time 3214254419 ps
CPU time 14.47 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:55:06 PM PDT 24
Peak memory 226288 kb
Host smart-c3681b51-3052-4dfb-8f14-e0c9756f00c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593297085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1593297085
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3584133491
Short name T364
Test name
Test status
Simulation time 2056679343 ps
CPU time 8.93 seconds
Started May 26 02:54:39 PM PDT 24
Finished May 26 02:54:49 PM PDT 24
Peak memory 218040 kb
Host smart-edaacb02-3c93-4c39-897c-ebb6086dc971
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584133491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3584133491
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2556424856
Short name T57
Test name
Test status
Simulation time 2680276853 ps
CPU time 10.33 seconds
Started May 26 02:54:47 PM PDT 24
Finished May 26 02:55:00 PM PDT 24
Peak memory 218068 kb
Host smart-a4fd3e18-54a1-44fd-999c-58f756606fe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556424856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2556424856
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2806029212
Short name T702
Test name
Test status
Simulation time 1935884026 ps
CPU time 11.33 seconds
Started May 26 02:54:50 PM PDT 24
Finished May 26 02:55:04 PM PDT 24
Peak memory 218256 kb
Host smart-fcfd42d1-78a4-459c-af4e-65bd4c4c01c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806029212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2806029212
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3302576767
Short name T840
Test name
Test status
Simulation time 528427972 ps
CPU time 7.48 seconds
Started May 26 02:54:48 PM PDT 24
Finished May 26 02:54:58 PM PDT 24
Peak memory 218044 kb
Host smart-3c313e8f-e02e-4c4c-b83b-771241702032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302576767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3302576767
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.779313737
Short name T834
Test name
Test status
Simulation time 416345114 ps
CPU time 27.64 seconds
Started May 26 02:54:45 PM PDT 24
Finished May 26 02:55:14 PM PDT 24
Peak memory 251036 kb
Host smart-af5779c8-2f60-463d-851e-909f42e73dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779313737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.779313737
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3472802375
Short name T395
Test name
Test status
Simulation time 186250878 ps
CPU time 8.28 seconds
Started May 26 02:54:41 PM PDT 24
Finished May 26 02:54:50 PM PDT 24
Peak memory 250896 kb
Host smart-f80abbe5-db8f-446a-9f62-3f7bf1938073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472802375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3472802375
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2355085522
Short name T747
Test name
Test status
Simulation time 14794080818 ps
CPU time 241.68 seconds
Started May 26 02:54:50 PM PDT 24
Finished May 26 02:58:55 PM PDT 24
Peak memory 278424 kb
Host smart-7fa551a6-f63b-4da0-b10d-2b9fd7f4a4b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355085522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2355085522
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.59927863
Short name T42
Test name
Test status
Simulation time 41195110 ps
CPU time 0.94 seconds
Started May 26 02:54:43 PM PDT 24
Finished May 26 02:54:45 PM PDT 24
Peak memory 208668 kb
Host smart-1a47188f-7573-4760-b3ba-ee27ce006e1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59927863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctr
l_volatile_unlock_smoke.59927863
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3892433664
Short name T585
Test name
Test status
Simulation time 14679917 ps
CPU time 0.78 seconds
Started May 26 02:54:56 PM PDT 24
Finished May 26 02:55:01 PM PDT 24
Peak memory 209624 kb
Host smart-4bad1ff8-01b9-4738-8aed-1c27fa34942b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892433664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3892433664
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3540257570
Short name T216
Test name
Test status
Simulation time 694033513 ps
CPU time 17.96 seconds
Started May 26 02:54:45 PM PDT 24
Finished May 26 02:55:05 PM PDT 24
Peak memory 218244 kb
Host smart-367edab0-5849-4eeb-a549-33df9423cad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540257570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3540257570
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2069916457
Short name T790
Test name
Test status
Simulation time 161582562 ps
CPU time 1.22 seconds
Started May 26 02:54:44 PM PDT 24
Finished May 26 02:54:47 PM PDT 24
Peak memory 209640 kb
Host smart-b381566c-82f8-43b1-8005-316bc61fe6cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069916457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2069916457
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3953179338
Short name T348
Test name
Test status
Simulation time 308555582 ps
CPU time 3.91 seconds
Started May 26 02:54:47 PM PDT 24
Finished May 26 02:54:54 PM PDT 24
Peak memory 218192 kb
Host smart-c1a39842-e298-48bf-bb87-70f9640541ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953179338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3953179338
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.864927832
Short name T308
Test name
Test status
Simulation time 317247588 ps
CPU time 9.68 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:55:02 PM PDT 24
Peak memory 226212 kb
Host smart-447d454b-06f6-4014-accc-18bf6a6d6c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864927832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.864927832
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2113265674
Short name T257
Test name
Test status
Simulation time 219649990 ps
CPU time 10.52 seconds
Started May 26 02:54:50 PM PDT 24
Finished May 26 02:55:04 PM PDT 24
Peak memory 218060 kb
Host smart-db316c24-fc28-4eac-a7aa-11c6e62149c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113265674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2113265674
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.145129033
Short name T370
Test name
Test status
Simulation time 862439233 ps
CPU time 14.19 seconds
Started May 26 02:54:55 PM PDT 24
Finished May 26 02:55:12 PM PDT 24
Peak memory 218000 kb
Host smart-ab053b43-154c-4902-9167-69d0b019149a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145129033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.145129033
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1355444349
Short name T530
Test name
Test status
Simulation time 1138392497 ps
CPU time 8.79 seconds
Started May 26 02:54:51 PM PDT 24
Finished May 26 02:55:03 PM PDT 24
Peak memory 218184 kb
Host smart-1d3804f4-6a52-4b16-beca-5a0d28e8c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355444349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1355444349
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3137477618
Short name T656
Test name
Test status
Simulation time 61951128 ps
CPU time 3.2 seconds
Started May 26 02:54:44 PM PDT 24
Finished May 26 02:54:49 PM PDT 24
Peak memory 217828 kb
Host smart-c0af026a-9d87-4c05-a60c-32e2e5fae09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137477618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3137477618
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2767597714
Short name T240
Test name
Test status
Simulation time 1406615237 ps
CPU time 26.98 seconds
Started May 26 02:54:40 PM PDT 24
Finished May 26 02:55:08 PM PDT 24
Peak memory 250952 kb
Host smart-24155a24-c26c-497a-afc9-f6a5c74116cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767597714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2767597714
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3885690036
Short name T93
Test name
Test status
Simulation time 149152403 ps
CPU time 2.61 seconds
Started May 26 02:54:46 PM PDT 24
Finished May 26 02:54:50 PM PDT 24
Peak memory 222440 kb
Host smart-5bb6161b-913b-404a-9a1b-3e6a8d90107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885690036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3885690036
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2882488973
Short name T779
Test name
Test status
Simulation time 4156344187 ps
CPU time 107.89 seconds
Started May 26 02:54:51 PM PDT 24
Finished May 26 02:56:42 PM PDT 24
Peak memory 275712 kb
Host smart-fbc17ae2-4cc6-4fdc-bde6-cd760263eca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882488973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2882488973
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1886057936
Short name T138
Test name
Test status
Simulation time 101448695019 ps
CPU time 501.69 seconds
Started May 26 02:54:53 PM PDT 24
Finished May 26 03:03:18 PM PDT 24
Peak memory 333120 kb
Host smart-1f0983f7-584c-4d50-b166-9aa07970260d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1886057936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1886057936
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.563746044
Short name T597
Test name
Test status
Simulation time 16723123 ps
CPU time 0.95 seconds
Started May 26 02:54:36 PM PDT 24
Finished May 26 02:54:39 PM PDT 24
Peak memory 212608 kb
Host smart-9c6eebbe-e102-4e6a-9113-b1fad459d8c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563746044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.563746044
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3226505869
Short name T226
Test name
Test status
Simulation time 23592380 ps
CPU time 1.01 seconds
Started May 26 02:54:52 PM PDT 24
Finished May 26 02:54:56 PM PDT 24
Peak memory 209692 kb
Host smart-f256b5e7-517e-42b8-b69c-3f06826c5fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226505869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3226505869
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1214727895
Short name T538
Test name
Test status
Simulation time 1036561060 ps
CPU time 10.31 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:55:02 PM PDT 24
Peak memory 218144 kb
Host smart-cc1afe51-02ee-4f82-9076-403387ac6349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214727895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1214727895
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3138585992
Short name T396
Test name
Test status
Simulation time 715288909 ps
CPU time 9.93 seconds
Started May 26 02:54:50 PM PDT 24
Finished May 26 02:55:03 PM PDT 24
Peak memory 209636 kb
Host smart-c56cffd5-ffc5-47a5-9ed5-a22ad0711e6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138585992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3138585992
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.43170781
Short name T256
Test name
Test status
Simulation time 108322301 ps
CPU time 4.11 seconds
Started May 26 02:54:53 PM PDT 24
Finished May 26 02:55:00 PM PDT 24
Peak memory 218104 kb
Host smart-caceeda0-bef7-4cc6-8587-d6a4e37235a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43170781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.43170781
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.788115000
Short name T170
Test name
Test status
Simulation time 567425088 ps
CPU time 22.52 seconds
Started May 26 02:54:44 PM PDT 24
Finished May 26 02:55:08 PM PDT 24
Peak memory 226244 kb
Host smart-af389c41-dc24-48c9-a759-29570de4a966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788115000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.788115000
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3063853113
Short name T619
Test name
Test status
Simulation time 366816073 ps
CPU time 9.44 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:55:02 PM PDT 24
Peak memory 218184 kb
Host smart-61ea1baa-c96e-4066-a2c8-f1f42b417680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063853113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3063853113
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1551604159
Short name T677
Test name
Test status
Simulation time 480098958 ps
CPU time 8.07 seconds
Started May 26 02:54:48 PM PDT 24
Finished May 26 02:54:58 PM PDT 24
Peak memory 218064 kb
Host smart-adf6e7b3-0d94-41d1-9c4c-7910e98059a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551604159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1551604159
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2677126961
Short name T209
Test name
Test status
Simulation time 302295022 ps
CPU time 10.24 seconds
Started May 26 02:54:48 PM PDT 24
Finished May 26 02:55:01 PM PDT 24
Peak memory 218236 kb
Host smart-0cda1945-4c34-4ee3-ab9e-0c74ce5a7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677126961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2677126961
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.4061181401
Short name T176
Test name
Test status
Simulation time 58871311 ps
CPU time 1.43 seconds
Started May 26 02:54:47 PM PDT 24
Finished May 26 02:54:51 PM PDT 24
Peak memory 213788 kb
Host smart-dd4c1cf1-a47c-4951-b1ad-7dba62e02137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061181401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.4061181401
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.4260328329
Short name T380
Test name
Test status
Simulation time 881234601 ps
CPU time 30.92 seconds
Started May 26 02:54:48 PM PDT 24
Finished May 26 02:55:21 PM PDT 24
Peak memory 251008 kb
Host smart-d18e9bf0-3e52-421a-add3-015746322a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260328329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.4260328329
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2146121072
Short name T465
Test name
Test status
Simulation time 494532384 ps
CPU time 6.79 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:54:59 PM PDT 24
Peak memory 246568 kb
Host smart-ace406ee-40a6-410d-a8fa-4da2c78bd0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146121072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2146121072
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4183866786
Short name T855
Test name
Test status
Simulation time 2482942086 ps
CPU time 94.45 seconds
Started May 26 02:54:54 PM PDT 24
Finished May 26 02:56:31 PM PDT 24
Peak memory 251076 kb
Host smart-f75e10fd-49f6-41c1-97c6-23cc7fbbbd7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183866786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4183866786
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2713658710
Short name T71
Test name
Test status
Simulation time 28949313 ps
CPU time 0.96 seconds
Started May 26 02:54:47 PM PDT 24
Finished May 26 02:54:50 PM PDT 24
Peak memory 211692 kb
Host smart-7463a781-3b6b-4273-a615-2d1c36db46e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713658710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2713658710
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3026545023
Short name T503
Test name
Test status
Simulation time 19401749 ps
CPU time 0.94 seconds
Started May 26 02:54:49 PM PDT 24
Finished May 26 02:54:53 PM PDT 24
Peak memory 209684 kb
Host smart-2f3b4b3f-53b5-4516-b460-de0e136bfaa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026545023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3026545023
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2710191088
Short name T539
Test name
Test status
Simulation time 318390917 ps
CPU time 9.09 seconds
Started May 26 02:54:52 PM PDT 24
Finished May 26 02:55:04 PM PDT 24
Peak memory 218192 kb
Host smart-320cc45a-3ee1-403b-af2f-55e017927b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710191088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2710191088
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.511072151
Short name T31
Test name
Test status
Simulation time 381341912 ps
CPU time 10.91 seconds
Started May 26 02:54:56 PM PDT 24
Finished May 26 02:55:10 PM PDT 24
Peak memory 209636 kb
Host smart-045c6a90-4a6d-43b8-9b3a-3c2503952abd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511072151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.511072151
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.864477567
Short name T278
Test name
Test status
Simulation time 224382823 ps
CPU time 2.05 seconds
Started May 26 02:54:50 PM PDT 24
Finished May 26 02:54:55 PM PDT 24
Peak memory 218096 kb
Host smart-23069de3-8533-4fe5-abac-f7fe2df17a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864477567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.864477567
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.106023275
Short name T385
Test name
Test status
Simulation time 512372504 ps
CPU time 10.6 seconds
Started May 26 02:54:54 PM PDT 24
Finished May 26 02:55:08 PM PDT 24
Peak memory 226224 kb
Host smart-ec461dea-4d75-4b6e-9d5b-65313d670142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106023275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.106023275
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.883710785
Short name T687
Test name
Test status
Simulation time 768165714 ps
CPU time 12.39 seconds
Started May 26 02:54:50 PM PDT 24
Finished May 26 02:55:06 PM PDT 24
Peak memory 218060 kb
Host smart-cb33f7c3-b348-4797-8226-974815685591
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883710785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.883710785
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1264465306
Short name T571
Test name
Test status
Simulation time 1227416148 ps
CPU time 8.33 seconds
Started May 26 02:54:51 PM PDT 24
Finished May 26 02:55:03 PM PDT 24
Peak memory 218064 kb
Host smart-201e586b-8a58-4557-8cad-be026a81e48f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264465306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1264465306
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.135405858
Short name T486
Test name
Test status
Simulation time 416347736 ps
CPU time 16.58 seconds
Started May 26 02:54:53 PM PDT 24
Finished May 26 02:55:13 PM PDT 24
Peak memory 218388 kb
Host smart-235009b1-1575-4f78-9802-bd90d456db0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135405858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.135405858
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2330390256
Short name T261
Test name
Test status
Simulation time 59162597 ps
CPU time 3.72 seconds
Started May 26 02:54:56 PM PDT 24
Finished May 26 02:55:03 PM PDT 24
Peak memory 214744 kb
Host smart-d398da09-241b-4ae5-b6ef-a00be77f1094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330390256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2330390256
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3631865496
Short name T739
Test name
Test status
Simulation time 647662295 ps
CPU time 19.53 seconds
Started May 26 02:54:58 PM PDT 24
Finished May 26 02:55:21 PM PDT 24
Peak memory 250948 kb
Host smart-e2cf26cf-1483-402e-9bf9-fef77d62dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631865496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3631865496
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3197881791
Short name T732
Test name
Test status
Simulation time 123536228 ps
CPU time 3.21 seconds
Started May 26 02:54:52 PM PDT 24
Finished May 26 02:54:58 PM PDT 24
Peak memory 222120 kb
Host smart-e2fbc256-1835-4369-a97f-6f458e123878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197881791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3197881791
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2603028427
Short name T878
Test name
Test status
Simulation time 3250832206 ps
CPU time 93.65 seconds
Started May 26 02:54:51 PM PDT 24
Finished May 26 02:56:28 PM PDT 24
Peak memory 278316 kb
Host smart-89b380c7-bfb0-4e33-bd76-89e4cefb517a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603028427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2603028427
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2727113160
Short name T139
Test name
Test status
Simulation time 14470951707 ps
CPU time 463.67 seconds
Started May 26 02:54:58 PM PDT 24
Finished May 26 03:02:45 PM PDT 24
Peak memory 295488 kb
Host smart-5b46359c-1123-4d8b-8624-9d7fac307091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2727113160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2727113160
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2215857205
Short name T838
Test name
Test status
Simulation time 45195945 ps
CPU time 0.77 seconds
Started May 26 02:54:52 PM PDT 24
Finished May 26 02:54:56 PM PDT 24
Peak memory 208604 kb
Host smart-0d43efe5-e9e4-4f5a-b931-85e8a9372214
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215857205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2215857205
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2774895238
Short name T75
Test name
Test status
Simulation time 37444058 ps
CPU time 1.23 seconds
Started May 26 02:54:59 PM PDT 24
Finished May 26 02:55:04 PM PDT 24
Peak memory 209688 kb
Host smart-21c06d31-36bb-4273-a6d6-a4ac9b7957c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774895238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2774895238
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2548491632
Short name T796
Test name
Test status
Simulation time 1934455517 ps
CPU time 13.48 seconds
Started May 26 02:54:55 PM PDT 24
Finished May 26 02:55:12 PM PDT 24
Peak memory 218112 kb
Host smart-b9b093cf-e2c8-4d63-bcc3-41933a765f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548491632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2548491632
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.816562082
Short name T28
Test name
Test status
Simulation time 554408664 ps
CPU time 4.12 seconds
Started May 26 02:55:03 PM PDT 24
Finished May 26 02:55:10 PM PDT 24
Peak memory 216904 kb
Host smart-8b814e38-923e-45ee-8f67-538e56319c65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816562082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.816562082
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3245415043
Short name T67
Test name
Test status
Simulation time 51093733 ps
CPU time 1.43 seconds
Started May 26 02:54:54 PM PDT 24
Finished May 26 02:54:58 PM PDT 24
Peak memory 218192 kb
Host smart-cef1203b-eda2-4c00-b671-ba19cf0ae240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245415043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3245415043
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.608628163
Short name T749
Test name
Test status
Simulation time 415761023 ps
CPU time 12.93 seconds
Started May 26 02:54:55 PM PDT 24
Finished May 26 02:55:11 PM PDT 24
Peak memory 219076 kb
Host smart-2fb3cdac-ef4b-4f9e-a046-8c82c31ff935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608628163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.608628163
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1640140952
Short name T752
Test name
Test status
Simulation time 291071588 ps
CPU time 9.77 seconds
Started May 26 02:54:57 PM PDT 24
Finished May 26 02:55:11 PM PDT 24
Peak memory 218104 kb
Host smart-c11a903c-f649-4780-89bb-ce19f9b67148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640140952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1640140952
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3420484677
Short name T623
Test name
Test status
Simulation time 1585770799 ps
CPU time 9.86 seconds
Started May 26 02:54:58 PM PDT 24
Finished May 26 02:55:12 PM PDT 24
Peak memory 218136 kb
Host smart-33014753-e1d6-4404-bcc5-8b220ddeec40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420484677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3420484677
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3363894103
Short name T330
Test name
Test status
Simulation time 2225655764 ps
CPU time 11.87 seconds
Started May 26 02:54:51 PM PDT 24
Finished May 26 02:55:06 PM PDT 24
Peak memory 218248 kb
Host smart-b5332235-18b5-44de-8699-06530d44beac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363894103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3363894103
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1859792122
Short name T498
Test name
Test status
Simulation time 105097890 ps
CPU time 4.56 seconds
Started May 26 02:54:53 PM PDT 24
Finished May 26 02:55:00 PM PDT 24
Peak memory 217832 kb
Host smart-be052742-ad4f-4c10-97ab-67df53c1cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859792122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1859792122
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1635369731
Short name T644
Test name
Test status
Simulation time 785683057 ps
CPU time 17.42 seconds
Started May 26 02:54:50 PM PDT 24
Finished May 26 02:55:11 PM PDT 24
Peak memory 251044 kb
Host smart-c3560ca8-47ba-4f5d-9247-d6438a00ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635369731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1635369731
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.849103067
Short name T425
Test name
Test status
Simulation time 225029261 ps
CPU time 5.41 seconds
Started May 26 02:54:55 PM PDT 24
Finished May 26 02:55:03 PM PDT 24
Peak memory 222628 kb
Host smart-bb793412-8b64-4d62-989a-4b9fe27bb46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849103067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.849103067
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2296895777
Short name T69
Test name
Test status
Simulation time 2698614947 ps
CPU time 72.33 seconds
Started May 26 02:54:53 PM PDT 24
Finished May 26 02:56:08 PM PDT 24
Peak memory 251092 kb
Host smart-efca82f4-bb7a-46b8-baaa-2da1f1957701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296895777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2296895777
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.956834605
Short name T291
Test name
Test status
Simulation time 46881439 ps
CPU time 0.91 seconds
Started May 26 02:54:55 PM PDT 24
Finished May 26 02:54:59 PM PDT 24
Peak memory 211584 kb
Host smart-2b744317-9d2b-4621-950a-a52c0d6d3ac7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956834605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.956834605
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2433079734
Short name T666
Test name
Test status
Simulation time 30392362 ps
CPU time 1.1 seconds
Started May 26 02:53:01 PM PDT 24
Finished May 26 02:53:04 PM PDT 24
Peak memory 209696 kb
Host smart-cb530699-5439-4534-b53c-db0a1c6066c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433079734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2433079734
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1663428231
Short name T35
Test name
Test status
Simulation time 12346721 ps
CPU time 0.98 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:09 PM PDT 24
Peak memory 209632 kb
Host smart-1bb2890d-20e7-45a9-830d-b9bb3ab282b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663428231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1663428231
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.269290146
Short name T786
Test name
Test status
Simulation time 1811315048 ps
CPU time 19.04 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:30 PM PDT 24
Peak memory 218104 kb
Host smart-f19470ba-c8d9-4552-8c06-841038fa5dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269290146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.269290146
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2971355500
Short name T541
Test name
Test status
Simulation time 1128407293 ps
CPU time 3.78 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:11 PM PDT 24
Peak memory 209680 kb
Host smart-adf480d9-fd09-40a2-8c9f-ac2960461c9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971355500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2971355500
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1179124871
Short name T668
Test name
Test status
Simulation time 1566213000 ps
CPU time 50.29 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:59 PM PDT 24
Peak memory 218072 kb
Host smart-8d93ef46-bb5f-4edb-b1e4-f4a6bf2b7a67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179124871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1179124871
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1195122119
Short name T863
Test name
Test status
Simulation time 1864143765 ps
CPU time 5.57 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:15 PM PDT 24
Peak memory 217888 kb
Host smart-01ebc8da-b2b8-4920-b018-622b1d2eef81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195122119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
195122119
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2839121457
Short name T525
Test name
Test status
Simulation time 64639367 ps
CPU time 2.12 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 218200 kb
Host smart-aefde782-75f7-4ef3-8d5e-0c85d45c0526
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839121457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2839121457
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.729851916
Short name T394
Test name
Test status
Simulation time 1163182001 ps
CPU time 35.25 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 213420 kb
Host smart-d5a00410-46ba-45c4-b0a8-a9fdda3db255
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729851916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.729851916
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.235619639
Short name T439
Test name
Test status
Simulation time 532754205 ps
CPU time 5.49 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:14 PM PDT 24
Peak memory 213524 kb
Host smart-5f6ae6b8-ca1c-44ed-8327-59c5001b1c33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235619639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.235619639
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2278376040
Short name T471
Test name
Test status
Simulation time 9103741675 ps
CPU time 62.14 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:54:13 PM PDT 24
Peak memory 275620 kb
Host smart-a765d37f-3282-41a3-aaac-20ad9294b271
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278376040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2278376040
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2974483743
Short name T572
Test name
Test status
Simulation time 728232134 ps
CPU time 7.64 seconds
Started May 26 02:53:04 PM PDT 24
Finished May 26 02:53:14 PM PDT 24
Peak memory 222168 kb
Host smart-4079dcd7-0298-4726-8681-9ad43f96f8a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974483743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2974483743
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3855873784
Short name T844
Test name
Test status
Simulation time 95673004 ps
CPU time 2.78 seconds
Started May 26 02:53:04 PM PDT 24
Finished May 26 02:53:09 PM PDT 24
Peak memory 218204 kb
Host smart-9694b588-2e95-4f1d-8570-1c3a897c3e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855873784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3855873784
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3769868633
Short name T812
Test name
Test status
Simulation time 473352850 ps
CPU time 15.27 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:27 PM PDT 24
Peak memory 214008 kb
Host smart-07137318-89c3-4060-a716-273b556f483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769868633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3769868633
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2867383230
Short name T869
Test name
Test status
Simulation time 269616979 ps
CPU time 9.05 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 225852 kb
Host smart-df99dacb-ef8a-45ab-8172-2afef835ef59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867383230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2867383230
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3595198346
Short name T382
Test name
Test status
Simulation time 1862328665 ps
CPU time 16.16 seconds
Started May 26 02:53:12 PM PDT 24
Finished May 26 02:53:32 PM PDT 24
Peak memory 218132 kb
Host smart-29086dd2-2b85-41da-8fd9-0fbc22a0dbc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595198346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3595198346
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1122572970
Short name T532
Test name
Test status
Simulation time 4233683683 ps
CPU time 9.22 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 218096 kb
Host smart-35fde786-b07f-4f3b-a797-6d5391360433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122572970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
122572970
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1917508578
Short name T642
Test name
Test status
Simulation time 1224076770 ps
CPU time 12.6 seconds
Started May 26 02:53:11 PM PDT 24
Finished May 26 02:53:27 PM PDT 24
Peak memory 218104 kb
Host smart-fcacbae2-8510-4c63-ac5e-c7961dc7ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917508578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1917508578
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2215935156
Short name T794
Test name
Test status
Simulation time 504712280 ps
CPU time 10.22 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:21 PM PDT 24
Peak memory 217812 kb
Host smart-76cf42e5-19c5-4add-bf5a-63a1cec9f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215935156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2215935156
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1017120189
Short name T430
Test name
Test status
Simulation time 286387293 ps
CPU time 17.97 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 251040 kb
Host smart-fac86771-77d5-4fe7-b088-416ae934e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017120189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1017120189
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.358317303
Short name T744
Test name
Test status
Simulation time 249806134 ps
CPU time 2.62 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 222796 kb
Host smart-4541d0c4-2ed0-4bf5-a1c4-b420e46764a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358317303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.358317303
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.188739937
Short name T528
Test name
Test status
Simulation time 1804863618 ps
CPU time 14.99 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 242784 kb
Host smart-3ebff44b-f236-40db-b6ac-f1692b24e068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188739937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.188739937
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2387534078
Short name T11
Test name
Test status
Simulation time 22928363 ps
CPU time 1.02 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:10 PM PDT 24
Peak memory 211676 kb
Host smart-07ba9210-b553-46af-aa41-bb2069f8c38b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387534078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2387534078
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1930498371
Short name T215
Test name
Test status
Simulation time 20392289 ps
CPU time 0.88 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:20 PM PDT 24
Peak memory 209696 kb
Host smart-5baa6c1d-92ab-4e35-be99-e166507e1ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930498371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1930498371
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1170682297
Short name T428
Test name
Test status
Simulation time 1556843758 ps
CPU time 9.17 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 218084 kb
Host smart-fd59cfbe-10a4-47d0-9ff3-3a49bbabec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170682297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1170682297
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1591474538
Short name T458
Test name
Test status
Simulation time 992625071 ps
CPU time 6.01 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 209724 kb
Host smart-6089f408-4d23-48a1-b363-d490ab3b1b10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591474538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1591474538
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3419715681
Short name T276
Test name
Test status
Simulation time 1897020267 ps
CPU time 29.82 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 218032 kb
Host smart-1d3a3c5b-d802-42b7-bb1a-c691c0727cba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419715681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3419715681
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.285248651
Short name T867
Test name
Test status
Simulation time 1943815448 ps
CPU time 11.65 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:29 PM PDT 24
Peak memory 217512 kb
Host smart-5a38c930-749f-4b73-a1aa-ba1b70042af8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285248651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.285248651
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3612612929
Short name T763
Test name
Test status
Simulation time 344933801 ps
CPU time 6.05 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:17 PM PDT 24
Peak memory 218272 kb
Host smart-291fe9cc-d595-4327-8e41-870254cd4cbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612612929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3612612929
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1889142012
Short name T357
Test name
Test status
Simulation time 2706229301 ps
CPU time 18.56 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 213536 kb
Host smart-f0b9b347-6f10-454a-b328-16b8271a0ee2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889142012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1889142012
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1821699667
Short name T860
Test name
Test status
Simulation time 1556869496 ps
CPU time 5.79 seconds
Started May 26 02:53:01 PM PDT 24
Finished May 26 02:53:08 PM PDT 24
Peak memory 213896 kb
Host smart-18043fd5-ec04-482a-aeb5-d9f61851346b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821699667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1821699667
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3487981288
Short name T533
Test name
Test status
Simulation time 3011121124 ps
CPU time 36.97 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:54 PM PDT 24
Peak memory 251060 kb
Host smart-f54cd53e-b038-4fc9-89bb-5273c4194ade
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487981288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3487981288
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.871622741
Short name T162
Test name
Test status
Simulation time 881043308 ps
CPU time 8.86 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:31 PM PDT 24
Peak memory 222976 kb
Host smart-4678bf54-061e-43c7-8360-95cdaca61bcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871622741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.871622741
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1392309221
Short name T152
Test name
Test status
Simulation time 112445918 ps
CPU time 2.43 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 218116 kb
Host smart-ca34f368-08c5-4950-a3f8-0f55eee161d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392309221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1392309221
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3710800016
Short name T670
Test name
Test status
Simulation time 263044751 ps
CPU time 6.31 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:17 PM PDT 24
Peak memory 217796 kb
Host smart-b70d7ec0-180c-4b6f-8646-f5bc4288500b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710800016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3710800016
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2181679121
Short name T368
Test name
Test status
Simulation time 629641358 ps
CPU time 10.8 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:29 PM PDT 24
Peak memory 226204 kb
Host smart-d554f07e-fca0-4ed2-b7e1-be98c9c79375
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181679121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2181679121
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3704373811
Short name T440
Test name
Test status
Simulation time 2197349967 ps
CPU time 13.63 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 218124 kb
Host smart-68d0c40b-c14d-4d83-b76e-e49926e05716
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704373811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3704373811
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.199293945
Short name T378
Test name
Test status
Simulation time 899952904 ps
CPU time 9.72 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 218096 kb
Host smart-4915ae49-b4cf-4826-a82b-49635e909302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199293945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.199293945
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.335827568
Short name T624
Test name
Test status
Simulation time 66553320 ps
CPU time 2.69 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 214336 kb
Host smart-da0d6db0-0f3e-4a7c-be75-53ebc3e43292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335827568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.335827568
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3335171963
Short name T651
Test name
Test status
Simulation time 224870723 ps
CPU time 22.77 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:32 PM PDT 24
Peak memory 251080 kb
Host smart-fbed1862-8bb0-40e7-893e-9c97b805da32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335171963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3335171963
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3620467545
Short name T329
Test name
Test status
Simulation time 87047640 ps
CPU time 7.57 seconds
Started May 26 02:53:02 PM PDT 24
Finished May 26 02:53:11 PM PDT 24
Peak memory 250960 kb
Host smart-87e38582-6a7a-4b19-b4da-7d0504a0cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620467545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3620467545
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.812529583
Short name T332
Test name
Test status
Simulation time 13788003776 ps
CPU time 93.46 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:54:52 PM PDT 24
Peak memory 227528 kb
Host smart-df8eb9d9-46eb-4489-8883-d96596ebb759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812529583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.812529583
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1674418193
Short name T41
Test name
Test status
Simulation time 77663428 ps
CPU time 1.01 seconds
Started May 26 02:53:03 PM PDT 24
Finished May 26 02:53:06 PM PDT 24
Peak memory 211596 kb
Host smart-5c172f88-2407-40dd-b7f6-e9838fb922dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674418193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1674418193
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2342292211
Short name T614
Test name
Test status
Simulation time 25470924 ps
CPU time 1.13 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:18 PM PDT 24
Peak memory 209796 kb
Host smart-18a63afc-9937-4a5f-841d-e2e0f661c487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342292211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2342292211
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2312582971
Short name T207
Test name
Test status
Simulation time 13210441 ps
CPU time 0.84 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:11 PM PDT 24
Peak memory 209552 kb
Host smart-c9e31100-3f19-4ea6-aa5f-6ad8207c3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312582971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2312582971
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.991491855
Short name T55
Test name
Test status
Simulation time 1236256994 ps
CPU time 12.53 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 218132 kb
Host smart-e7ef03ee-8aeb-4cd7-8f99-c36c4d618910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991491855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.991491855
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2862556463
Short name T403
Test name
Test status
Simulation time 396026241 ps
CPU time 3.49 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 216992 kb
Host smart-3b70be65-06c7-4de4-b780-750e4e6c5bfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862556463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2862556463
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1330048756
Short name T716
Test name
Test status
Simulation time 2129918366 ps
CPU time 33.67 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:50 PM PDT 24
Peak memory 218060 kb
Host smart-6f010b5c-e223-4aaa-aeac-ae9cab36d41b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330048756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1330048756
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3235498302
Short name T299
Test name
Test status
Simulation time 223487307 ps
CPU time 5.75 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 217392 kb
Host smart-58c75f98-3e60-4643-9cc5-dc76fbf0108d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235498302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
235498302
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.260661325
Short name T568
Test name
Test status
Simulation time 1512367809 ps
CPU time 6.39 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:17 PM PDT 24
Peak memory 218144 kb
Host smart-eaf6e63a-b95f-461f-95e1-9697b198a912
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260661325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.260661325
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3168318962
Short name T622
Test name
Test status
Simulation time 5079072965 ps
CPU time 19.58 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 213996 kb
Host smart-e0798421-56e2-4eeb-a502-650d3d8656d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168318962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3168318962
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3464660762
Short name T83
Test name
Test status
Simulation time 1341201773 ps
CPU time 5.59 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:13 PM PDT 24
Peak memory 213480 kb
Host smart-f2fbf988-9375-4bfe-ad5e-d853b6aec781
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464660762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3464660762
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.398341785
Short name T335
Test name
Test status
Simulation time 1080545764 ps
CPU time 36.51 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:54 PM PDT 24
Peak memory 275504 kb
Host smart-2d03f68e-be4e-40d8-9947-9dca88d60c6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398341785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.398341785
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2531869733
Short name T165
Test name
Test status
Simulation time 289268076 ps
CPU time 12.6 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 02:53:32 PM PDT 24
Peak memory 250192 kb
Host smart-d8d6cc5c-dd98-4545-a2ff-b7ae29d0e799
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531869733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2531869733
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1338340540
Short name T434
Test name
Test status
Simulation time 33322712 ps
CPU time 2.31 seconds
Started May 26 02:53:12 PM PDT 24
Finished May 26 02:53:18 PM PDT 24
Peak memory 218124 kb
Host smart-f528fa29-0147-4352-b900-92a9b840cd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338340540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1338340540
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1239268201
Short name T492
Test name
Test status
Simulation time 549729098 ps
CPU time 10.46 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 218008 kb
Host smart-a8fafd76-091a-43d0-ae4b-182d7a2fc1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239268201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1239268201
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1197521137
Short name T180
Test name
Test status
Simulation time 188566973 ps
CPU time 9.47 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 226220 kb
Host smart-f6666d67-f381-4ae4-94be-27aa1641cc4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197521137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1197521137
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.888664860
Short name T862
Test name
Test status
Simulation time 1508137384 ps
CPU time 19.89 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 218104 kb
Host smart-47f19c29-e0b9-4489-ad21-743b0ec3d0b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888664860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.888664860
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3680621943
Short name T281
Test name
Test status
Simulation time 754352828 ps
CPU time 13.3 seconds
Started May 26 02:53:05 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 218116 kb
Host smart-c6926905-8dea-45c4-81b1-800f18929323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680621943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
680621943
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3697893799
Short name T717
Test name
Test status
Simulation time 1794897432 ps
CPU time 15.47 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:32 PM PDT 24
Peak memory 218168 kb
Host smart-3b785639-f7fa-42a5-8a8b-42beb3296029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697893799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3697893799
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3378529784
Short name T86
Test name
Test status
Simulation time 368823884 ps
CPU time 2.31 seconds
Started May 26 02:53:09 PM PDT 24
Finished May 26 02:53:15 PM PDT 24
Peak memory 214100 kb
Host smart-e27314e3-536f-461c-8d2c-e95b1d87c3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378529784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3378529784
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3984839405
Short name T617
Test name
Test status
Simulation time 313217351 ps
CPU time 30.78 seconds
Started May 26 02:53:04 PM PDT 24
Finished May 26 02:53:38 PM PDT 24
Peak memory 251044 kb
Host smart-bb3c6e2c-10ea-490c-8389-76ce7ca2cacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984839405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3984839405
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1736854215
Short name T379
Test name
Test status
Simulation time 172696014 ps
CPU time 6.69 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:18 PM PDT 24
Peak memory 250932 kb
Host smart-7996a958-d72c-42db-98ae-645a9f162f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736854215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1736854215
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3660368818
Short name T504
Test name
Test status
Simulation time 23705262895 ps
CPU time 108.95 seconds
Started May 26 02:53:09 PM PDT 24
Finished May 26 02:55:02 PM PDT 24
Peak memory 251096 kb
Host smart-3f2eaf8a-40b3-49b7-9319-f945414b6c3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660368818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3660368818
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2661044096
Short name T681
Test name
Test status
Simulation time 43272747 ps
CPU time 1 seconds
Started May 26 02:53:12 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 211700 kb
Host smart-1b1fb0cf-f531-4426-8930-5657012be34e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661044096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2661044096
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3344911816
Short name T502
Test name
Test status
Simulation time 59777990 ps
CPU time 1.15 seconds
Started May 26 02:53:11 PM PDT 24
Finished May 26 02:53:15 PM PDT 24
Peak memory 209728 kb
Host smart-8cf6dead-4e64-43e7-b738-56e6991e1350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344911816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3344911816
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3041254286
Short name T243
Test name
Test status
Simulation time 370137565 ps
CPU time 12.16 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 218116 kb
Host smart-a6adf77b-4eb0-41bc-bb50-92593e80b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041254286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3041254286
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3348767837
Short name T312
Test name
Test status
Simulation time 359083913 ps
CPU time 1.47 seconds
Started May 26 02:53:14 PM PDT 24
Finished May 26 02:53:19 PM PDT 24
Peak memory 209716 kb
Host smart-502dcb9d-65e1-4887-8fe2-1ec893f5c178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348767837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3348767837
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3894076932
Short name T584
Test name
Test status
Simulation time 6941374328 ps
CPU time 50.12 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:54:04 PM PDT 24
Peak memory 218120 kb
Host smart-8f2f8c10-4eb3-45c5-b2e4-2783bbf86b7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894076932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3894076932
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.638854186
Short name T415
Test name
Test status
Simulation time 316826135 ps
CPU time 4.63 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:17 PM PDT 24
Peak memory 217900 kb
Host smart-b2dc99b5-4593-46eb-991f-b1283b593acd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638854186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.638854186
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.691492731
Short name T704
Test name
Test status
Simulation time 375478122 ps
CPU time 7.62 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 218040 kb
Host smart-b00f67cb-e287-4cdf-9cf6-e82f8657ae44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691492731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.691492731
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.435636962
Short name T735
Test name
Test status
Simulation time 1129041563 ps
CPU time 14.26 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 213264 kb
Host smart-768471e4-6d9d-43f1-87ad-90ae1a0b8e03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435636962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.435636962
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1435035656
Short name T542
Test name
Test status
Simulation time 677876464 ps
CPU time 6.06 seconds
Started May 26 02:53:09 PM PDT 24
Finished May 26 02:53:19 PM PDT 24
Peak memory 213844 kb
Host smart-b01b9706-292d-462b-a3bb-524d3490426d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435035656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1435035656
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3241648285
Short name T799
Test name
Test status
Simulation time 1502968975 ps
CPU time 47.19 seconds
Started May 26 02:53:19 PM PDT 24
Finished May 26 02:54:09 PM PDT 24
Peak memory 267828 kb
Host smart-d484ba9d-6117-4ee4-9f9a-ae1dd2395231
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241648285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3241648285
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2496960339
Short name T550
Test name
Test status
Simulation time 750602788 ps
CPU time 26.31 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:42 PM PDT 24
Peak memory 250928 kb
Host smart-3fb5c895-614a-4f83-adb3-9773b9273466
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496960339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2496960339
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3897359059
Short name T470
Test name
Test status
Simulation time 280043426 ps
CPU time 3.6 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 218116 kb
Host smart-93597143-ef74-4fe6-96fe-993fb4cb1645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897359059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3897359059
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.49291098
Short name T640
Test name
Test status
Simulation time 3090493702 ps
CPU time 24.26 seconds
Started May 26 02:53:06 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 217924 kb
Host smart-25d5e9cd-8d22-4419-b1ba-22368c78145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49291098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.49291098
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1282798661
Short name T746
Test name
Test status
Simulation time 331870726 ps
CPU time 10.92 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:32 PM PDT 24
Peak memory 218812 kb
Host smart-7b40e235-49c5-4af0-8ae8-8d7c81ef54ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282798661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1282798661
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.449844959
Short name T404
Test name
Test status
Simulation time 4104316286 ps
CPU time 12.2 seconds
Started May 26 02:53:20 PM PDT 24
Finished May 26 02:53:35 PM PDT 24
Peak memory 218124 kb
Host smart-67edb543-cb40-4af2-992a-5a73434a0fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449844959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.449844959
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2879091574
Short name T645
Test name
Test status
Simulation time 184402398 ps
CPU time 6.39 seconds
Started May 26 02:53:18 PM PDT 24
Finished May 26 02:53:28 PM PDT 24
Peak memory 218068 kb
Host smart-88e56466-327c-4897-8dbd-af1e3a5f0530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879091574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
879091574
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.640014197
Short name T19
Test name
Test status
Simulation time 1239539788 ps
CPU time 8.23 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:27 PM PDT 24
Peak memory 218196 kb
Host smart-ea072012-4bbc-4f9b-810b-e238584dd77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640014197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.640014197
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.4245426764
Short name T641
Test name
Test status
Simulation time 159730925 ps
CPU time 2.16 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 218040 kb
Host smart-3cc1ba12-d4d0-4a72-ac15-d7c398cfa807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245426764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4245426764
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3913362069
Short name T416
Test name
Test status
Simulation time 1453702873 ps
CPU time 33.76 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 251048 kb
Host smart-86201f5d-b9a0-4254-9e0d-c3cd13b3a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913362069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3913362069
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.797459771
Short name T472
Test name
Test status
Simulation time 77398384 ps
CPU time 8.57 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 251044 kb
Host smart-8be50529-d6cd-4037-bbd5-bc553077a57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797459771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.797459771
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1060325959
Short name T323
Test name
Test status
Simulation time 73716011983 ps
CPU time 315.45 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:58:30 PM PDT 24
Peak memory 271776 kb
Host smart-7e3e0491-8c7e-4e82-b7a4-78e573939d6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060325959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1060325959
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1238696675
Short name T137
Test name
Test status
Simulation time 12157394057 ps
CPU time 446.3 seconds
Started May 26 02:53:16 PM PDT 24
Finished May 26 03:00:47 PM PDT 24
Peak memory 324712 kb
Host smart-f9e86e66-e34c-490c-bf64-c7bae6325d07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1238696675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1238696675
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1289157754
Short name T783
Test name
Test status
Simulation time 42792437 ps
CPU time 0.86 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:15 PM PDT 24
Peak memory 208512 kb
Host smart-17f90378-e2bd-475c-a6b1-321b0ccbd2ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289157754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1289157754
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2513654778
Short name T608
Test name
Test status
Simulation time 16138729 ps
CPU time 0.91 seconds
Started May 26 02:53:17 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 209680 kb
Host smart-96c3b002-36c5-4fd1-a635-c0efa4360257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513654778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2513654778
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.459946815
Short name T821
Test name
Test status
Simulation time 149224816 ps
CPU time 0.79 seconds
Started May 26 02:53:10 PM PDT 24
Finished May 26 02:53:15 PM PDT 24
Peak memory 209536 kb
Host smart-5612117b-4609-4f66-a3a7-43b8d35e54c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459946815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.459946815
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.978892675
Short name T399
Test name
Test status
Simulation time 1511764399 ps
CPU time 9.85 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:53:34 PM PDT 24
Peak memory 218196 kb
Host smart-50294cfc-6b4d-4a7d-9cb6-269dccba0281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978892675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.978892675
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3380254070
Short name T734
Test name
Test status
Simulation time 5038479623 ps
CPU time 11.88 seconds
Started May 26 02:53:21 PM PDT 24
Finished May 26 02:53:36 PM PDT 24
Peak memory 209656 kb
Host smart-094ff866-3517-406b-abea-555ae6d94033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380254070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3380254070
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.789252772
Short name T611
Test name
Test status
Simulation time 1699209589 ps
CPU time 27.83 seconds
Started May 26 02:53:15 PM PDT 24
Finished May 26 02:53:47 PM PDT 24
Peak memory 217980 kb
Host smart-244323ea-b0a6-42ea-9622-49ce9441529a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789252772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.789252772
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1866599878
Short name T363
Test name
Test status
Simulation time 351378855 ps
CPU time 2.08 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 217116 kb
Host smart-882ab920-376e-4a93-9625-c48d32766cd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866599878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
866599878
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.721890279
Short name T352
Test name
Test status
Simulation time 1636961936 ps
CPU time 7.72 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:24 PM PDT 24
Peak memory 217980 kb
Host smart-173bf763-47ff-46c7-91ac-429fbeb1c5ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721890279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.721890279
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2388333566
Short name T846
Test name
Test status
Simulation time 2179364007 ps
CPU time 17.37 seconds
Started May 26 02:53:25 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 213404 kb
Host smart-2a3b8e1d-001a-4eb4-928d-187a6d1778ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388333566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2388333566
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3670843503
Short name T81
Test name
Test status
Simulation time 864588377 ps
CPU time 7.14 seconds
Started May 26 02:53:21 PM PDT 24
Finished May 26 02:53:31 PM PDT 24
Peak memory 213724 kb
Host smart-22522d3f-8f9a-4f1c-9466-362a8ada03ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670843503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3670843503
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2472840034
Short name T620
Test name
Test status
Simulation time 1363994183 ps
CPU time 37.42 seconds
Started May 26 02:53:22 PM PDT 24
Finished May 26 02:54:01 PM PDT 24
Peak memory 270804 kb
Host smart-dabf18b3-64a0-460a-b5e5-15275f5ed589
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472840034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2472840034
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2486052696
Short name T6
Test name
Test status
Simulation time 407503558 ps
CPU time 16.78 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:53:46 PM PDT 24
Peak memory 250384 kb
Host smart-d0f1b45c-80e2-4016-ba87-832f497c664a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486052696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2486052696
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.393838965
Short name T253
Test name
Test status
Simulation time 88326579 ps
CPU time 2.67 seconds
Started May 26 02:53:17 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 218064 kb
Host smart-421d5cac-d758-4732-9755-b5453b74ca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393838965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.393838965
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2863902632
Short name T699
Test name
Test status
Simulation time 217694658 ps
CPU time 5.41 seconds
Started May 26 02:53:09 PM PDT 24
Finished May 26 02:53:18 PM PDT 24
Peak memory 214212 kb
Host smart-03e6e079-ce1e-4ad5-9293-e609f4ecd10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863902632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2863902632
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2556878466
Short name T225
Test name
Test status
Simulation time 302463584 ps
CPU time 12.47 seconds
Started May 26 02:53:34 PM PDT 24
Finished May 26 02:53:49 PM PDT 24
Peak memory 226000 kb
Host smart-58426486-6a06-45e2-9f84-58723179c621
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556878466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2556878466
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.291352625
Short name T383
Test name
Test status
Simulation time 1125981522 ps
CPU time 12.7 seconds
Started May 26 02:53:23 PM PDT 24
Finished May 26 02:53:37 PM PDT 24
Peak memory 218064 kb
Host smart-88e2fe3a-e20c-44db-9df5-7c3fab4291f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291352625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.291352625
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.553674988
Short name T777
Test name
Test status
Simulation time 187472168 ps
CPU time 8.84 seconds
Started May 26 02:53:24 PM PDT 24
Finished May 26 02:53:41 PM PDT 24
Peak memory 218100 kb
Host smart-1b55e555-9f81-4a51-8087-a11f19526688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553674988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.553674988
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.268080625
Short name T805
Test name
Test status
Simulation time 737339288 ps
CPU time 10.02 seconds
Started May 26 02:53:19 PM PDT 24
Finished May 26 02:53:33 PM PDT 24
Peak memory 218316 kb
Host smart-4a0d0a84-32a5-4eed-b560-316a99eb838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268080625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.268080625
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.661555146
Short name T427
Test name
Test status
Simulation time 25598993 ps
CPU time 1.58 seconds
Started May 26 02:53:08 PM PDT 24
Finished May 26 02:53:19 PM PDT 24
Peak memory 213884 kb
Host smart-9e8074ab-d729-4c24-a10f-ad2571ede290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661555146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.661555146
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3659277446
Short name T36
Test name
Test status
Simulation time 336638393 ps
CPU time 21.56 seconds
Started May 26 02:53:13 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 251080 kb
Host smart-5a6b6bc6-5032-4cec-8f76-fe8b22d47b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659277446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3659277446
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4014213184
Short name T322
Test name
Test status
Simulation time 259897995 ps
CPU time 12.14 seconds
Started May 26 02:53:07 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 251040 kb
Host smart-b27eba53-b883-4e90-94a0-10de1e436504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014213184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4014213184
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.194582347
Short name T866
Test name
Test status
Simulation time 2969976446 ps
CPU time 112.64 seconds
Started May 26 02:53:26 PM PDT 24
Finished May 26 02:55:22 PM PDT 24
Peak memory 278268 kb
Host smart-1e677993-a269-476b-86cd-d58cee091ef4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194582347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.194582347
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2368518071
Short name T554
Test name
Test status
Simulation time 14069312 ps
CPU time 0.78 seconds
Started May 26 02:53:19 PM PDT 24
Finished May 26 02:53:23 PM PDT 24
Peak memory 208564 kb
Host smart-cce91ea5-f552-42c5-acc4-a1b5c60ef233
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368518071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2368518071
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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