Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96587269

1

T1

1921

T2

42532

T3

4603

auto[1]

1409338

1

T2

2277

T3

792

T4

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96593291

1

T1

1921

T2

42928

T3

4999

auto[1]

1403316

1

T2

1881

T3

396

T4

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7376312	1			T1	110		T2	9309		T3	1154
auto[IdleSt]	21741211	1			T1	189		T2	9224		T3	1083
auto[ClkMuxSt]	34978	1			T1	1		T2	76		T3	12
auto[CntIncrSt]	34707	1			T1	1		T2	76		T3	12
auto[CntProgSt]	2010036	1			T1	476		T2	1249		T3	888
auto[TransCheckSt]	27085	1			T1	1		T2	58		T12	64
auto[TokenHashSt]	33831808	1			T1	67		T2	640		T12	698
auto[FlashRmaSt]	27659	1			T1	1		T2	169		T13	28
auto[TokenCheck0St]	12148	1			T1	1		T2	50		T13	5
auto[TokenCheck1St]	8789	1			T1	1		T2	35		T13	5
auto[TransProgSt]	497756	1			T1	137		T2	551		T13	278
auto[PostTransSt]	12973537	1			T1	936		T2	12647		T3	746
auto[ScrapSt]	119070	1			T13	36		T6	708		T51	4
auto[EscalateSt]	6967114	1			T2	6161		T3	1500		T4	557
auto[InvalidSt]	12332472	1			T2	4564		T15	2139		T7	153122

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1925	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12332472	1			T2	4564		T15	2139		T7	153122
EscalateSt	6967114	1			T2	6161		T3	1500		T4	557
ScrapSt	119070	1			T13	36		T6	708		T51	4
PostTransSt	12973537	1			T1	936		T2	12647		T3	746
TransProgSt	497756	1			T1	137		T2	551		T13	278
TokenCheck1St	8789	1			T1	1		T2	35		T13	5
TokenCheck0St	12148	1			T1	1		T2	50		T13	5
FlashRmaSt	27659	1			T1	1		T2	169		T13	28
TokenHashSt	33831808	1			T1	67		T2	640		T12	698
TransCheckSt	27085	1			T1	1		T2	58		T12	64
CntProgSt	2010036	1			T1	476		T2	1249		T3	888
CntIncrSt	34707	1			T1	1		T2	76		T3	12
ClkMuxSt	34978	1			T1	1		T2	76		T3	12
IdleSt	21741211	1			T1	189		T2	9224		T3	1083
ResetSt	7376312	1			T1	110		T2	9309		T3	1154
arcs[ResetSt=>IdleSt]	53435	1			T1	1		T2	101		T3	13
arcs[IdleSt=>ScrapSt]	254	1			T13	1		T6	1		T51	1
arcs[IdleSt=>ClkMuxSt]	34772	1			T1	1		T2	76		T3	12
arcs[ClkMuxSt=>CntIncrSt]	34707	1			T1	1		T2	76		T3	12
arcs[CntIncrSt=>PostTransSt]	1860	1			T22	10		T42	12		T43	11
arcs[CntIncrSt=>CntProgSt]	32791	1			T1	1		T2	76		T3	12
arcs[CntProgSt=>PostTransSt]	4641	1			T2	18		T3	12		T4	4
arcs[CntProgSt=>TransCheckSt]	27085	1			T1	1		T2	58		T12	64
arcs[TransCheckSt=>PostTransSt]	3790	1			T16	27		T26	37		T27	48
arcs[TransCheckSt=>TokenHashSt]	23185	1			T1	1		T2	58		T12	64
arcs[TokenHashSt=>PostTransSt]	10249	1			T2	8		T12	64		T15	5
arcs[TokenHashSt=>FlashRmaSt]	12243	1			T1	1		T2	50		T13	5
arcs[FlashRmaSt=>TokenCheck0St]	12148	1			T1	1		T2	50		T13	5
arcs[TokenCheck0St=>PostTransSt]	3333	1			T2	15		T15	15		T16	12
arcs[TokenCheck0St=>TokenCheck1St]	8789	1			T1	1		T2	35		T13	5
arcs[TokenCheck1St=>PostTransSt]	635	1			T16	6		T26	11		T27	8
arcs[TransProgSt=>PostTransSt]	7258	1			T1	1		T2	35		T13	5
arcs[IdleSt=>EscalateSt]	167	1			T62	10		T64	3		T65	3
arcs[ClkMuxSt=>EscalateSt]	65	1			T50	3		T62	1		T63	3
arcs[CntIncrSt=>EscalateSt]	56	1			T50	1		T62	1		T64	2
arcs[CntProgSt=>EscalateSt]	1065	1			T50	30		T62	20		T63	32
arcs[TransCheckSt=>EscalateSt]	110	1			T62	2		T65	2		T68	7
arcs[TokenHashSt=>EscalateSt]	693	1			T50	5		T62	10		T63	8
arcs[FlashRmaSt=>EscalateSt]	95	1			T50	1		T62	3		T63	4
arcs[TokenCheck0St=>EscalateSt]	26	1			T50	2		T67	1		T64	1
arcs[TokenCheck1St=>EscalateSt]	153	1			T50	3		T62	3		T63	2
arcs[TransProgSt=>EscalateSt]	743	1			T50	12		T62	15		T63	19
arcs[PostTransSt=>EscalateSt]	4898	1			T2	18		T3	12		T4	4
arcs[InvalidSt=>EscalateSt]	14241	1			T2	24		T15	11		T7	51

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7376122	1			T1	110		T2	9309		T3	1154
auto[0]	auto[IdleSt]	21741095	1			T1	189		T2	9224		T3	1083
auto[0]	auto[ClkMuxSt]	34932	1			T1	1		T2	76		T3	12
auto[0]	auto[CntIncrSt]	34668	1			T1	1		T2	76		T3	12
auto[0]	auto[CntProgSt]	2009316	1			T1	476		T2	1249		T3	888
auto[0]	auto[TransCheckSt]	27011	1			T1	1		T2	58		T12	64
auto[0]	auto[TokenHashSt]	33831335	1			T1	67		T2	640		T12	698
auto[0]	auto[FlashRmaSt]	27590	1			T1	1		T2	169		T13	28
auto[0]	auto[TokenCheck0St]	12133	1			T1	1		T2	50		T13	5
auto[0]	auto[TokenCheck1St]	8680	1			T1	1		T2	35		T13	5
auto[0]	auto[TransProgSt]	497267	1			T1	137		T2	551		T13	278
auto[0]	auto[PostTransSt]	12971066	1			T1	936		T2	12636		T3	738
auto[0]	auto[ScrapSt]	119030	1			T13	36		T6	708		T51	4
auto[0]	auto[EscalateSt]	5569721	1			T2	3907		T3	716		T4	361
auto[0]	auto[InvalidSt]	12325378	1			T2	4552		T15	2131		T7	153099
auto[1]	auto[ResetSt]	190	1			T50	2		T62	3		T63	3
auto[1]	auto[IdleSt]	116	1			T62	8		T64	3		T65	3
auto[1]	auto[ClkMuxSt]	46	1			T62	1		T63	2		T67	1
auto[1]	auto[CntIncrSt]	39	1			T50	1		T62	1		T64	2
auto[1]	auto[CntProgSt]	720	1			T50	19		T62	13		T63	25
auto[1]	auto[TransCheckSt]	74	1			T62	1		T65	1		T68	5
auto[1]	auto[TokenHashSt]	473	1			T50	4		T62	6		T63	7
auto[1]	auto[FlashRmaSt]	69	1			T50	1		T62	3		T63	2
auto[1]	auto[TokenCheck0St]	15	1			T50	1		T67	1		T65	1
auto[1]	auto[TokenCheck1St]	109	1			T50	1		T62	2		T63	2
auto[1]	auto[TransProgSt]	489	1			T50	7		T62	12		T63	8
auto[1]	auto[PostTransSt]	2471	1			T2	11		T3	8		T4	2
auto[1]	auto[ScrapSt]	40	1			T62	2		T67	1		T65	1
auto[1]	auto[EscalateSt]	1397393	1			T2	2254		T3	784		T4	196
auto[1]	auto[InvalidSt]	7094	1			T2	12		T15	8		T7	23

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7376125	1			T1	110		T2	9309		T3	1154
auto[0]	auto[IdleSt]	21741107	1			T1	189		T2	9224		T3	1083
auto[0]	auto[ClkMuxSt]	34936	1			T1	1		T2	76		T3	12
auto[0]	auto[CntIncrSt]	34667	1			T1	1		T2	76		T3	12
auto[0]	auto[CntProgSt]	2009322	1			T1	476		T2	1249		T3	888
auto[0]	auto[TransCheckSt]	27019	1			T1	1		T2	58		T12	64
auto[0]	auto[TokenHashSt]	33831352	1			T1	67		T2	640		T12	698
auto[0]	auto[FlashRmaSt]	27610	1			T1	1		T2	169		T13	28
auto[0]	auto[TokenCheck0St]	12131	1			T1	1		T2	50		T13	5
auto[0]	auto[TokenCheck1St]	8681	1			T1	1		T2	35		T13	5
auto[0]	auto[TransProgSt]	497247	1			T1	137		T2	551		T13	278
auto[0]	auto[PostTransSt]	12971038	1			T1	936		T2	12640		T3	742
auto[0]	auto[ScrapSt]	119029	1			T13	36		T6	708		T51	4
auto[0]	auto[EscalateSt]	5575777	1			T2	4299		T3	1108		T4	361
auto[0]	auto[InvalidSt]	12325325	1			T2	4552		T15	2136		T7	153094
auto[1]	auto[ResetSt]	187	1			T50	3		T62	4		T63	6
auto[1]	auto[IdleSt]	104	1			T62	5		T64	1		T65	2
auto[1]	auto[ClkMuxSt]	42	1			T50	3		T63	3		T67	2
auto[1]	auto[CntIncrSt]	40	1			T64	1		T220	3		T221	3
auto[1]	auto[CntProgSt]	714	1			T50	20		T62	15		T63	20
auto[1]	auto[TransCheckSt]	66	1			T62	1		T65	1		T68	4
auto[1]	auto[TokenHashSt]	456	1			T50	2		T62	6		T63	5
auto[1]	auto[FlashRmaSt]	49	1			T62	1		T63	3		T67	1
auto[1]	auto[TokenCheck0St]	17	1			T50	1		T67	1		T64	1
auto[1]	auto[TokenCheck1St]	108	1			T50	2		T62	3		T63	1
auto[1]	auto[TransProgSt]	509	1			T50	7		T62	9		T63	17
auto[1]	auto[PostTransSt]	2499	1			T2	7		T3	4		T4	2
auto[1]	auto[ScrapSt]	41	1			T50	1		T62	1		T63	1
auto[1]	auto[EscalateSt]	1391337	1			T2	1862		T3	392		T4	196
auto[1]	auto[InvalidSt]	7147	1			T2	12		T15	3		T7	28